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From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
To: intel-xe@lists.freedesktop.org
Cc: kernel-dev@igalia.com, Tvrtko Ursulin <tvrtko.ursulin@igalia.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH v13 03/12] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
Date: Mon, 20 Oct 2025 08:58:21 +0100	[thread overview]
Message-ID: <20251020075831.32818-4-tvrtko.ursulin@igalia.com> (raw)
In-Reply-To: <20251020075831.32818-1-tvrtko.ursulin@igalia.com>

According to i915 commit
ad8ebf12217e ("drm/i915/gt: Ensure memory quiesced before invalidation")
quiescing of the memory traffic is required before invalidating the AuxCCS
tables.

Add an extra pipe control flush to achieve that.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_ring_ops.c       | 10 +++++++++-
 drivers/gpu/drm/xe/xe_ring_ops_types.h |  2 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 15fc4010a710..f384c9968859 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -363,12 +363,20 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	struct xe_gt *gt = job->q->gt;
 	struct xe_device *xe = gt_to_xe(gt);
 	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
+	const bool aux_ccs = has_aux_ccs(xe);
 	u32 mask_flags = 0;
 
 	*head = lrc->ring.tail;
 
 	i = emit_copy_timestamp(lrc, dw, i);
 
+	/*
+	 * On AuxCCS platforms the invalidation of the Aux table requires
+	 * quiescing the memory traffic beforehand.
+	 */
+	if (aux_ccs)
+		i = emit_render_cache_flush(job, dw, i);
+
 	dw[i++] = preparser_disable(true);
 	if (lacks_render)
 		mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
@@ -379,7 +387,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
 
 	/* hsdes: 1809175790 */
-	if (has_aux_ccs(xe))
+	if (aux_ccs)
 		i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
 
 	dw[i++] = preparser_disable(false);
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index d7e3e150a9a5..477dc7defd72 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
 
 struct xe_sched_job;
 
-#define MAX_JOB_SIZE_DW 58
+#define MAX_JOB_SIZE_DW 70
 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
 
 /**
-- 
2.48.0


  parent reply	other threads:[~2025-10-20  7:58 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-20  7:58 [PATCH v13 00/12] AuxCCS handling and render compression modifiers Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 01/12] drm/xe: Fix ggtt fb alignment Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 02/12] drm/xe/xelpg: Flush CCS when flushing caches Tvrtko Ursulin
2025-10-20 11:27   ` Ville Syrjälä
2025-10-20  7:58 ` Tvrtko Ursulin [this message]
2025-10-20  7:58 ` [PATCH v13 04/12] drm/xe/xelp: Support auxccs invalidation on blitter Tvrtko Ursulin
2025-10-22 22:58   ` Matt Roper
2025-10-23  7:51     ` Tvrtko Ursulin
2025-10-23 17:10       ` Matt Roper
2025-10-24 10:50         ` Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 05/12] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms Tvrtko Ursulin
2025-10-22 23:13   ` Matt Roper
2025-10-23  7:55     ` Tvrtko Ursulin
2025-10-23 17:14       ` Matt Roper
2025-10-20  7:58 ` [PATCH v13 06/12] drm/xe/xelp: Wait for AuxCCS invalidation to complete Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 07/12] drm/xe: Export xe_emit_aux_table_inv Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 08/12] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds Tvrtko Ursulin
2025-10-20 11:31   ` Ville Syrjälä
2025-10-20 15:13     ` Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 09/12] drm/xe: Flush GGTT writes after populating DPT Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 10/12] drm/xe: Handle DPT in system memory Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 11/12] drm/xe/display: Add support for AuxCCS Tvrtko Ursulin
2025-10-20  7:58 ` [PATCH v13 12/12] drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe Tvrtko Ursulin
2025-10-20 11:46 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers Patchwork
2025-10-20 11:47 ` ✓ CI.KUnit: success " Patchwork
2025-10-20 12:32 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-20 14:52 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-20 15:03   ` Tvrtko Ursulin
2025-10-20 16:35 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers (rev2) Patchwork
2025-10-20 16:37 ` ✓ CI.KUnit: success " Patchwork
2025-10-20 22:10 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-21 16:02 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers (rev3) Patchwork
2025-10-21 16:03 ` ✓ CI.KUnit: success " Patchwork
2025-10-21 16:47 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-21 19:39 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-22  7:36   ` Tvrtko Ursulin
2025-10-22 18:01 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers (rev4) Patchwork
2025-10-22 18:02 ` ✓ CI.KUnit: success " Patchwork
2025-10-22 18:40 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-22 22:10 ` ✗ Xe.CI.Full: failure " Patchwork
2025-10-23 10:54 ` ✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers (rev5) Patchwork
2025-10-23 10:56 ` ✓ CI.KUnit: success " Patchwork
2025-10-23 12:15 ` ✓ Xe.CI.BAT: " Patchwork
2025-10-23 18:58 ` ✗ Xe.CI.Full: failure " Patchwork

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