Re: [PATCH v13 02/12] drm/xe/xelpg: Flush CCS when flushing caches

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Oct 20, 2025 at 08:58:20AM +0100, Tvrtko Ursulin wrote:
> According to i915 PIPE_CONTROL0_CCS_FLUSH needs to be set when flushing
> render caches on gfx ip 12.70+.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/instructions/xe_gpu_commands.h | 1 +
>  drivers/gpu/drm/xe/xe_ring_ops.c                  | 7 ++++++-
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
> index 8cfcd3360896..78c0e87dbd37 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_gpu_commands.h
> @@ -43,6 +43,7 @@
>  
>  #define	  PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE	BIT(10)	/* gen12 */
>  #define	  PIPE_CONTROL0_HDC_PIPELINE_FLUSH		BIT(9)	/* gen12 */
> +#define   PIPE_CONTROL0_CCS_FLUSH                       BIT(13) /* MTL+ */

IIRC that thing exists already on dg2, but we don't use there for
whatever unknown reason.

It also doesn't help that bsepc calls DG2 12.7 as well, but for us
someone has invented the of 12.55 number that's never mentioned
in bspec AFAICS.

>  
>  #define   PIPE_CONTROL_COMMAND_CACHE_INVALIDATE		(1<<29)
>  #define   PIPE_CONTROL_TILE_CACHE_FLUSH			(1<<28)
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
> index ac0c6dcffe15..15fc4010a710 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -176,13 +176,18 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,
>  static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
>  {
>  	struct xe_gt *gt = job->q->gt;
> +	struct xe_device *xe = gt_to_xe(gt);
>  	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
> +	u32 bit_group_0 = PIPE_CONTROL0_HDC_PIPELINE_FLUSH;
>  	u32 flags;
>  
>  	if (XE_GT_WA(gt, 14016712196))
>  		i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
>  				      LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR, 0);
>  
> +	if (GRAPHICS_VERx100(xe) >= 1270)
> +		bit_group_0 |= PIPE_CONTROL0_CCS_FLUSH;
> +
>  	flags = (PIPE_CONTROL_CS_STALL |
>  		 PIPE_CONTROL_TILE_CACHE_FLUSH |
>  		 PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
> @@ -198,7 +203,7 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
>  	else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
>  		flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>  
> -	return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
> +	return emit_pipe_control(dw, i, bit_group_0, flags, 0, 0);
>  }
>  
>  static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)
> -- 
> 2.48.0

-- 
Ville Syrjälä
Intel