Re: [PATCH v13 05/12] drm/xe/xelp: Use MI_FLUSH_DW_CCS on auxccs platforms

[Tvrtko Ursulin <tvrtko.ursulin@igalia.com>]

On 23/10/2025 00:13, Matt Roper wrote:
> On Mon, Oct 20, 2025 at 08:58:23AM +0100, Tvrtko Ursulin wrote:
>> Emit MI_FLUSH_DW_CCS when invalidating on auxccs platforms.
> 
> This is another one that doesn't apply to all platforms.  The
> MI_FLUSH_DW_CCS flag only exists from DG2 onward (and does not exist on
> PVC either).  So MTL/ARL are again the only platforms that this should
> actually apply to.
> 
> The bspec doesn't document any other meaning for this bit on the older
> gen12 platforms, so maybe it's safe to just set it anyway?

Don't ask a person with not access to the docs. :)

Essentially you are saying b70df82b4287 ("drm/i915/gt: Enable the 
CCS_FLUSH bit in the pipe control and in the CS") was wrong to set 
MI_FLUSH_DW_CCS, correct? This one is at least not as suspect as the 
invalidation register story, given the other part of this commit is 
adding a >= 12.70 check, so I can easily fix it.

Regards,

Tvrtko

>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_ring_ops.c | 7 ++++---
>>   1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>> index 87e467972070..d226d3228199 100644
>> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
>> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>> @@ -272,6 +272,8 @@ static void __emit_job_gen12_xcs(struct xe_sched_job *job, struct xe_lrc *lrc,
>>   			      class == XE_ENGINE_CLASS_VIDEO_DECODE ||
>>   			      class == XE_ENGINE_CLASS_VIDEO_ENHANCE);
>>   	const bool invalidate_tlb = aux_ccs || job->ring_ops_flush_tlb;
>> +	const u32 flags = aux_ccs && class == XE_ENGINE_CLASS_COPY ?
>> +			  MI_FLUSH_DW_CCS : 0;
>>   	u32 dw[MAX_JOB_SIZE_DW], i = 0;
>>   
>>   	*head = lrc->ring.tail;
>> @@ -281,9 +283,8 @@ static void __emit_job_gen12_xcs(struct xe_sched_job *job, struct xe_lrc *lrc,
>>   	if (invalidate_tlb) {
>>   		dw[i++] = preparser_disable(true);
>>   		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
>> -					seqno,
>> -					MI_INVALIDATE_TLB,
>> -					dw, i);
>> +					seqno, MI_INVALIDATE_TLB | flags, dw,
>> +					i);
>>   		/* hsdes: 1809175790 */
>>   		if (aux_ccs) {
>>   			struct xe_reg reg;
>> -- 
>> 2.48.0
>>
>