From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: gustavo.sousa@intel.com
Subject: [CI 08/17] drm/i915/xe3p_lpd: Add CDCLK table
Date: Wed, 5 Nov 2025 11:06:57 -0300 [thread overview]
Message-ID: <20251105140651.71713-27-gustavo.sousa@intel.com> (raw)
In-Reply-To: <20251105140651.71713-19-gustavo.sousa@intel.com>
Add CDCLK table for Xe3p_LPD.
Just as with Xe3_LPD, we don't need to send voltage index info in the
PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs.
With the new CDCLK table, we also need to update the maximum CDCLK value
returned by intel_update_max_cdclk().
Bspec: 68861, 68863
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20251103-xe3p_lpd-basic-enabling-v3-8-00e87b510ae7@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 44 +++++++++++++++++++++-
1 file changed, 42 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index bdb42fcc4cb2..4d03cfefc72c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1535,6 +1535,41 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
+ { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
+ { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
+ { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
+ {}
+};
+
static const int cdclk_squash_len = 16;
static int cdclk_squash_divider(u16 waveform)
@@ -3561,7 +3596,9 @@ static int intel_compute_max_dotclk(struct intel_display *display)
*/
void intel_update_max_cdclk(struct intel_display *display)
{
- if (DISPLAY_VERx100(display) >= 3002) {
+ if (DISPLAY_VER(display) >= 35) {
+ display->cdclk.max_cdclk_freq = 787200;
+ } else if (DISPLAY_VERx100(display) >= 3002) {
display->cdclk.max_cdclk_freq = 480000;
} else if (DISPLAY_VER(display) >= 30) {
display->cdclk.max_cdclk_freq = 691200;
@@ -3912,7 +3949,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct intel_display *display)
{
- if (DISPLAY_VER(display) >= 30) {
+ if (DISPLAY_VER(display) >= 35) {
+ display->funcs.cdclk = &xe3lpd_cdclk_funcs;
+ display->cdclk.table = xe3p_lpd_cdclk_table;
+ } else if (DISPLAY_VER(display) >= 30) {
display->funcs.cdclk = &xe3lpd_cdclk_funcs;
display->cdclk.table = xe3lpd_cdclk_table;
} else if (DISPLAY_VER(display) >= 20) {
--
2.51.0
next prev parent reply other threads:[~2025-11-05 14:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-05 14:06 [CI 00/17] Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Gustavo Sousa
2025-11-05 14:06 ` [CI 01/17] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features Gustavo Sousa
2025-11-05 14:06 ` [CI 02/17] drm/i915/xe3p_lpd: Drop north display reset option programming Gustavo Sousa
2025-11-05 14:06 ` [CI 03/17] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() Gustavo Sousa
2025-11-05 14:06 ` [CI 04/17] drm/i915/xe3p_lpd: Update bandwidth parameters Gustavo Sousa
2025-11-05 14:06 ` [CI 05/17] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields Gustavo Sousa
2025-11-05 14:06 ` [CI 06/17] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces Gustavo Sousa
2025-11-05 14:06 ` [CI 07/17] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks Gustavo Sousa
2025-11-05 14:06 ` Gustavo Sousa [this message]
2025-11-05 14:06 ` [CI 09/17] drm/i915/xe3p_lpd: Load DMC firmware Gustavo Sousa
2025-11-05 14:06 ` [CI 10/17] drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa
2025-11-05 14:07 ` [CI 11/17] drm/i915/xe3p_lpd: Extend Wa_16025573575 Gustavo Sousa
2025-11-05 14:07 ` [CI 12/17] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Gustavo Sousa
2025-11-05 14:07 ` [CI 13/17] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D Gustavo Sousa
2025-11-05 14:07 ` [CI 14/17] drm/i915/wm: don't use method1 in Xe3p_LPD onwards Gustavo Sousa
2025-11-05 14:07 ` [CI 15/17] drm/i915/dram: Add field ecc_impacting_de_bw Gustavo Sousa
2025-11-05 14:07 ` [CI 16/17] drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency Gustavo Sousa
2025-11-05 14:07 ` [CI 17/17] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Gustavo Sousa
2025-11-05 14:58 ` ✗ CI.checkpatch: warning for Reviewed patches from: [PATCH v3 00/29] drm/i915/display: Add initial support for Xe3p_LPD Patchwork
2025-11-05 15:00 ` ✓ CI.KUnit: success " Patchwork
2025-11-05 15:15 ` ✗ CI.checksparse: warning " Patchwork
2025-11-05 15:45 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-05 22:42 ` ✗ Xe.CI.Full: failure " Patchwork
2025-11-06 21:13 ` Gustavo Sousa
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