* [PATCH v3 0/3] Selective Fetch and async flip
@ 2025-12-01 13:24 Jouni Högander
2025-12-01 13:24 ` [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR Jouni Högander
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Jouni Högander @ 2025-12-01 13:24 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
This patch set contains fixes for Selective Fetch async flip
sequences. On async flip selective fetch is choosing full ftrame
update. Also subsequent flip/update is still using full frame update
to ensure plane with pending async flip is not taken in to selective
fetch/update.
v3:
- rebase
- fix old_crtc_state->pipe_srcsz_early_tpt
- fix using intel_atomic_get_new_crtc_state
v2:
- check also crtc_state->async_flip_planes in
psr2_sel_fetch_plane_state_supported
Jouni Högander (3):
drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for
PSR
drm/i915/psr: Perform full frame update on async flip
drm/i915/psr: Allow async flip when Selective Fetch enabled
drivers/gpu/drm/i915/display/intel_display.c | 8 ---
drivers/gpu/drm/i915/display/intel_plane.c | 10 ++-
drivers/gpu/drm/i915/display/intel_psr.c | 72 +++++++++++---------
3 files changed, 49 insertions(+), 41 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
@ 2025-12-01 13:24 ` Jouni Högander
2025-12-03 13:15 ` Ville Syrjälä
2025-12-01 13:24 ` [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip Jouni Högander
` (5 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Jouni Högander @ 2025-12-01 13:24 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
Currently plane id bit is set in crtc_state->async_flip_planes only when
async flip toggle workaround is needed. We want to utilize
crtc_state->async_flip_planes further in Selective Fetch calculation.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 7b7619d59251..de0a69c55582 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -603,8 +603,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
new_crtc_state->do_async_flip = true;
new_crtc_state->async_flip_planes |= BIT(plane->id);
- } else if (plane->need_async_flip_toggle_wa &&
- new_crtc_state->uapi.async_flip) {
+ } else if (new_crtc_state->uapi.async_flip) {
/*
* On platforms with double buffered async flip bit we
* set the bit already one frame early during the sync
@@ -612,6 +611,13 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
* hardware will therefore be ready to perform a real
* async flip during the next commit, without having
* to wait yet another frame for the bit to latch.
+ *
+ * async_flip_planes bitmask is also used by selective
+ * fetch calculation to continue full frame updates as
+ * long as there may be pending async flip on any
+ * plane which is part of selective
+ * update. I.e. old_crtc_state->async_flip_planes &
+ * BIT(<plane in su area>->id).
*/
new_crtc_state->async_flip_planes |= BIT(plane->id);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
2025-12-01 13:24 ` [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR Jouni Högander
@ 2025-12-01 13:24 ` Jouni Högander
2025-12-03 13:22 ` Ville Syrjälä
2025-12-01 13:24 ` [PATCH v3 3/3] drm/i915/psr: Allow async flip when Selective Fetch enabled Jouni Högander
` (4 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Jouni Högander @ 2025-12-01 13:24 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
According to bspec selective fetch is not supported with async flips and
instructing full frame update on async flip.
v3:
- rebase
- fix old_crtc_state->pipe_srcsz_early_tpt
- fix using intel_atomic_get_new_crtc_state
v2:
- check also crtc_state->async_flip_planes in
psr2_sel_fetch_plane_state_supported
Bspec: 55229
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++----------
1 file changed, 41 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 15ef3b6caad6..53cf292247d7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
* Plane scaling and rotation is not supported by selective fetch and both
* properties can change without a modeset, so need to be check at every
* atomic commit.
+ *
+ * If plane was having async flip previously we can't use selective
+ * fetch as we don't know if the flip is completed.
*/
-static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
+static bool psr2_sel_fetch_plane_state_supported(const struct intel_crtc_state *old_crtc_state,
+ const struct intel_plane_state *plane_state)
{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+
if (plane_state->uapi.dst.y1 < 0 ||
plane_state->uapi.dst.x1 < 0 ||
plane_state->scaler_id >= 0 ||
- plane_state->hw.rotation != DRM_MODE_ROTATE_0)
+ plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
+ old_crtc_state->async_flip_planes & plane->id)
return false;
return true;
@@ -2749,7 +2756,8 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
*/
static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
{
- if (crtc_state->scaler_state.scaler_id >= 0)
+ if (crtc_state->scaler_state.scaler_id >= 0 ||
+ crtc_state->uapi.async_flip)
return false;
return true;
@@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct intel_display *display = to_intel_display(state);
- struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+ struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
struct intel_plane_state *new_plane_state, *old_plane_state;
struct intel_plane *plane;
bool full_update = false, cursor_in_su_area = false;
int i, ret;
- if (!crtc_state->enable_psr2_sel_fetch)
+ if (!new_crtc_state->enable_psr2_sel_fetch)
return 0;
- if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
+ if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state)) {
full_update = true;
goto skip_sel_fetch_set_loop;
}
- crtc_state->psr2_su_area.x1 = 0;
- crtc_state->psr2_su_area.y1 = -1;
- crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
- crtc_state->psr2_su_area.y2 = -1;
+ new_crtc_state->psr2_su_area.x1 = 0;
+ new_crtc_state->psr2_su_area.y1 = -1;
+ new_crtc_state->psr2_su_area.x2 = drm_rect_width(&new_crtc_state->pipe_src);
+ new_crtc_state->psr2_su_area.y2 = -1;
/*
* Calculate minimal selective fetch area of each plane and calculate
@@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
.x2 = INT_MAX };
- if (new_plane_state->hw.crtc != crtc_state->uapi.crtc)
+ if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc)
continue;
if (!new_plane_state->uapi.visible &&
!old_plane_state->uapi.visible)
continue;
- if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
+ if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
full_update = true;
break;
}
@@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (old_plane_state->uapi.visible) {
damaged_area.y1 = old_plane_state->uapi.dst.y1;
damaged_area.y2 = old_plane_state->uapi.dst.y2;
- clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
- &crtc_state->pipe_src);
+ clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+ &new_crtc_state->pipe_src);
}
if (new_plane_state->uapi.visible) {
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
- clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
- &crtc_state->pipe_src);
+ clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+ &new_crtc_state->pipe_src);
}
continue;
} else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
/* If alpha changed mark the whole plane area as damaged */
damaged_area.y1 = new_plane_state->uapi.dst.y1;
damaged_area.y2 = new_plane_state->uapi.dst.y2;
- clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
- &crtc_state->pipe_src);
+ clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+ &new_crtc_state->pipe_src);
continue;
}
@@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
- clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
+ clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
+ &new_crtc_state->pipe_src);
}
/*
@@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
* should identify cases where this happens and fix the area
* calculation for those.
*/
- if (crtc_state->psr2_su_area.y1 == -1) {
+ if (new_crtc_state->psr2_su_area.y1 == -1) {
drm_info_once(display->drm,
"Selective fetch area calculation failed in pipe %c\n",
pipe_name(crtc->pipe));
@@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
if (full_update)
goto skip_sel_fetch_set_loop;
- intel_psr_apply_su_area_workarounds(crtc_state);
+ intel_psr_apply_su_area_workarounds(new_crtc_state);
ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
if (ret)
@@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
*/
intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
- intel_psr2_sel_fetch_pipe_alignment(crtc_state);
+ intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
/*
* Now that we have the pipe damaged area check if it intersect with
@@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
struct drm_rect *sel_fetch_area, inter;
struct intel_plane *linked = new_plane_state->planar_linked_plane;
- if (new_plane_state->hw.crtc != crtc_state->uapi.crtc ||
+ if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc ||
!new_plane_state->uapi.visible)
continue;
- inter = crtc_state->psr2_su_area;
+ inter = new_crtc_state->psr2_su_area;
sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) {
sel_fetch_area->y1 = -1;
@@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
* disable it
*/
if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0)
- crtc_state->update_planes |= BIT(plane->id);
+ new_crtc_state->update_planes |= BIT(plane->id);
continue;
}
- if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
+ if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
full_update = true;
break;
}
@@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
- crtc_state->update_planes |= BIT(plane->id);
+ new_crtc_state->update_planes |= BIT(plane->id);
/*
* Sel_fetch_area is calculated for UV plane. Use
@@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
linked_sel_fetch_area->y1 = sel_fetch_area->y1;
linked_sel_fetch_area->y2 = sel_fetch_area->y2;
- crtc_state->update_planes |= BIT(linked->id);
+ new_crtc_state->update_planes |= BIT(linked->id);
}
}
skip_sel_fetch_set_loop:
- psr2_man_trk_ctl_calc(crtc_state, full_update);
- crtc_state->pipe_srcsz_early_tpt =
- psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
+ psr2_man_trk_ctl_calc(new_crtc_state, full_update);
+ new_crtc_state->pipe_srcsz_early_tpt =
+ psr2_pipe_srcsz_early_tpt_calc(new_crtc_state, full_update);
return 0;
}
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 3/3] drm/i915/psr: Allow async flip when Selective Fetch enabled
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
2025-12-01 13:24 ` [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR Jouni Högander
2025-12-01 13:24 ` [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip Jouni Högander
@ 2025-12-01 13:24 ` Jouni Högander
2025-12-01 14:45 ` ✓ CI.KUnit: success for Selective Fetch and async flip (rev3) Patchwork
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Jouni Högander @ 2025-12-01 13:24 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: Jouni Högander
Now as Selective Fetch is performing full frame update on async flip and
vblank evasion is done as needed we can allow async flip even when
Selective Fetch is enabled.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e5ce47efc809..b262c033f24e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6017,14 +6017,6 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
return -EINVAL;
}
- /* FIXME: selective fetch should be disabled for async flips */
- if (new_crtc_state->enable_psr2_sel_fetch) {
- drm_dbg_kms(display->drm,
- "[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n",
- crtc->base.base.id, crtc->base.name);
- return -EINVAL;
- }
-
for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
new_plane_state, i) {
if (plane->pipe != crtc->pipe)
--
2.43.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* ✓ CI.KUnit: success for Selective Fetch and async flip (rev3)
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
` (2 preceding siblings ...)
2025-12-01 13:24 ` [PATCH v3 3/3] drm/i915/psr: Allow async flip when Selective Fetch enabled Jouni Högander
@ 2025-12-01 14:45 ` Patchwork
2025-12-01 15:03 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-12-01 14:45 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
== Series Details ==
Series: Selective Fetch and async flip (rev3)
URL : https://patchwork.freedesktop.org/series/158002/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[14:44:22] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:44:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:45:04] Starting KUnit Kernel (1/1)...
[14:45:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:45:04] ================== guc_buf (11 subtests) ===================
[14:45:04] [PASSED] test_smallest
[14:45:04] [PASSED] test_largest
[14:45:04] [PASSED] test_granular
[14:45:04] [PASSED] test_unique
[14:45:04] [PASSED] test_overlap
[14:45:04] [PASSED] test_reusable
[14:45:04] [PASSED] test_too_big
[14:45:04] [PASSED] test_flush
[14:45:04] [PASSED] test_lookup
[14:45:04] [PASSED] test_data
[14:45:04] [PASSED] test_class
[14:45:04] ===================== [PASSED] guc_buf =====================
[14:45:04] =================== guc_dbm (7 subtests) ===================
[14:45:04] [PASSED] test_empty
[14:45:04] [PASSED] test_default
[14:45:04] ======================== test_size ========================
[14:45:04] [PASSED] 4
[14:45:04] [PASSED] 8
[14:45:04] [PASSED] 32
[14:45:04] [PASSED] 256
[14:45:04] ==================== [PASSED] test_size ====================
[14:45:04] ======================= test_reuse ========================
[14:45:04] [PASSED] 4
[14:45:04] [PASSED] 8
[14:45:04] [PASSED] 32
[14:45:04] [PASSED] 256
[14:45:04] =================== [PASSED] test_reuse ====================
[14:45:04] =================== test_range_overlap ====================
[14:45:04] [PASSED] 4
[14:45:04] [PASSED] 8
[14:45:04] [PASSED] 32
[14:45:04] [PASSED] 256
[14:45:04] =============== [PASSED] test_range_overlap ================
[14:45:04] =================== test_range_compact ====================
[14:45:04] [PASSED] 4
[14:45:04] [PASSED] 8
[14:45:04] [PASSED] 32
[14:45:04] [PASSED] 256
[14:45:04] =============== [PASSED] test_range_compact ================
[14:45:04] ==================== test_range_spare =====================
[14:45:04] [PASSED] 4
[14:45:04] [PASSED] 8
[14:45:04] [PASSED] 32
[14:45:04] [PASSED] 256
[14:45:04] ================ [PASSED] test_range_spare =================
[14:45:04] ===================== [PASSED] guc_dbm =====================
[14:45:04] =================== guc_idm (6 subtests) ===================
[14:45:04] [PASSED] bad_init
[14:45:04] [PASSED] no_init
[14:45:04] [PASSED] init_fini
[14:45:04] [PASSED] check_used
[14:45:04] [PASSED] check_quota
[14:45:04] [PASSED] check_all
[14:45:04] ===================== [PASSED] guc_idm =====================
[14:45:04] ================== no_relay (3 subtests) ===================
[14:45:04] [PASSED] xe_drops_guc2pf_if_not_ready
[14:45:04] [PASSED] xe_drops_guc2vf_if_not_ready
[14:45:04] [PASSED] xe_rejects_send_if_not_ready
[14:45:04] ==================== [PASSED] no_relay =====================
[14:45:04] ================== pf_relay (14 subtests) ==================
[14:45:04] [PASSED] pf_rejects_guc2pf_too_short
[14:45:04] [PASSED] pf_rejects_guc2pf_too_long
[14:45:04] [PASSED] pf_rejects_guc2pf_no_payload
[14:45:04] [PASSED] pf_fails_no_payload
[14:45:04] [PASSED] pf_fails_bad_origin
[14:45:04] [PASSED] pf_fails_bad_type
[14:45:04] [PASSED] pf_txn_reports_error
[14:45:04] [PASSED] pf_txn_sends_pf2guc
[14:45:04] [PASSED] pf_sends_pf2guc
[14:45:04] [SKIPPED] pf_loopback_nop
[14:45:04] [SKIPPED] pf_loopback_echo
[14:45:04] [SKIPPED] pf_loopback_fail
[14:45:04] [SKIPPED] pf_loopback_busy
[14:45:04] [SKIPPED] pf_loopback_retry
[14:45:04] ==================== [PASSED] pf_relay =====================
[14:45:04] ================== vf_relay (3 subtests) ===================
[14:45:04] [PASSED] vf_rejects_guc2vf_too_short
[14:45:04] [PASSED] vf_rejects_guc2vf_too_long
[14:45:04] [PASSED] vf_rejects_guc2vf_no_payload
[14:45:04] ==================== [PASSED] vf_relay =====================
[14:45:04] ================ pf_gt_config (6 subtests) =================
[14:45:04] [PASSED] fair_contexts_1vf
[14:45:04] [PASSED] fair_doorbells_1vf
[14:45:04] [PASSED] fair_ggtt_1vf
[14:45:04] ====================== fair_contexts ======================
[14:45:04] [PASSED] 1 VF
[14:45:04] [PASSED] 2 VFs
[14:45:04] [PASSED] 3 VFs
[14:45:04] [PASSED] 4 VFs
[14:45:04] [PASSED] 5 VFs
[14:45:04] [PASSED] 6 VFs
[14:45:04] [PASSED] 7 VFs
[14:45:04] [PASSED] 8 VFs
[14:45:04] [PASSED] 9 VFs
[14:45:04] [PASSED] 10 VFs
[14:45:04] [PASSED] 11 VFs
[14:45:04] [PASSED] 12 VFs
[14:45:04] [PASSED] 13 VFs
[14:45:04] [PASSED] 14 VFs
[14:45:04] [PASSED] 15 VFs
[14:45:04] [PASSED] 16 VFs
[14:45:04] [PASSED] 17 VFs
[14:45:04] [PASSED] 18 VFs
[14:45:04] [PASSED] 19 VFs
[14:45:04] [PASSED] 20 VFs
[14:45:04] [PASSED] 21 VFs
[14:45:04] [PASSED] 22 VFs
[14:45:04] [PASSED] 23 VFs
[14:45:04] [PASSED] 24 VFs
[14:45:04] [PASSED] 25 VFs
[14:45:04] [PASSED] 26 VFs
[14:45:04] [PASSED] 27 VFs
[14:45:04] [PASSED] 28 VFs
[14:45:04] [PASSED] 29 VFs
[14:45:04] [PASSED] 30 VFs
[14:45:04] [PASSED] 31 VFs
[14:45:04] [PASSED] 32 VFs
[14:45:04] [PASSED] 33 VFs
[14:45:04] [PASSED] 34 VFs
[14:45:04] [PASSED] 35 VFs
[14:45:04] [PASSED] 36 VFs
[14:45:04] [PASSED] 37 VFs
[14:45:04] [PASSED] 38 VFs
[14:45:04] [PASSED] 39 VFs
[14:45:04] [PASSED] 40 VFs
[14:45:04] [PASSED] 41 VFs
[14:45:04] [PASSED] 42 VFs
[14:45:04] [PASSED] 43 VFs
[14:45:04] [PASSED] 44 VFs
[14:45:04] [PASSED] 45 VFs
[14:45:04] [PASSED] 46 VFs
[14:45:04] [PASSED] 47 VFs
[14:45:04] [PASSED] 48 VFs
[14:45:04] [PASSED] 49 VFs
[14:45:04] [PASSED] 50 VFs
[14:45:04] [PASSED] 51 VFs
[14:45:04] [PASSED] 52 VFs
[14:45:04] [PASSED] 53 VFs
[14:45:04] [PASSED] 54 VFs
[14:45:04] [PASSED] 55 VFs
[14:45:04] [PASSED] 56 VFs
[14:45:04] [PASSED] 57 VFs
[14:45:04] [PASSED] 58 VFs
[14:45:04] [PASSED] 59 VFs
[14:45:04] [PASSED] 60 VFs
[14:45:04] [PASSED] 61 VFs
[14:45:04] [PASSED] 62 VFs
[14:45:04] [PASSED] 63 VFs
[14:45:04] ================== [PASSED] fair_contexts ==================
[14:45:04] ===================== fair_doorbells ======================
[14:45:04] [PASSED] 1 VF
[14:45:04] [PASSED] 2 VFs
[14:45:04] [PASSED] 3 VFs
[14:45:04] [PASSED] 4 VFs
[14:45:04] [PASSED] 5 VFs
[14:45:04] [PASSED] 6 VFs
[14:45:04] [PASSED] 7 VFs
[14:45:04] [PASSED] 8 VFs
[14:45:04] [PASSED] 9 VFs
[14:45:04] [PASSED] 10 VFs
[14:45:04] [PASSED] 11 VFs
[14:45:04] [PASSED] 12 VFs
[14:45:04] [PASSED] 13 VFs
[14:45:04] [PASSED] 14 VFs
[14:45:04] [PASSED] 15 VFs
[14:45:04] [PASSED] 16 VFs
[14:45:04] [PASSED] 17 VFs
[14:45:04] [PASSED] 18 VFs
[14:45:04] [PASSED] 19 VFs
[14:45:04] [PASSED] 20 VFs
[14:45:04] [PASSED] 21 VFs
[14:45:04] [PASSED] 22 VFs
[14:45:04] [PASSED] 23 VFs
[14:45:04] [PASSED] 24 VFs
[14:45:04] [PASSED] 25 VFs
[14:45:04] [PASSED] 26 VFs
[14:45:04] [PASSED] 27 VFs
[14:45:04] [PASSED] 28 VFs
[14:45:04] [PASSED] 29 VFs
[14:45:04] [PASSED] 30 VFs
[14:45:04] [PASSED] 31 VFs
[14:45:04] [PASSED] 32 VFs
[14:45:04] [PASSED] 33 VFs
[14:45:04] [PASSED] 34 VFs
[14:45:04] [PASSED] 35 VFs
[14:45:04] [PASSED] 36 VFs
[14:45:04] [PASSED] 37 VFs
[14:45:04] [PASSED] 38 VFs
[14:45:04] [PASSED] 39 VFs
[14:45:04] [PASSED] 40 VFs
[14:45:04] [PASSED] 41 VFs
[14:45:04] [PASSED] 42 VFs
[14:45:04] [PASSED] 43 VFs
[14:45:04] [PASSED] 44 VFs
[14:45:04] [PASSED] 45 VFs
[14:45:04] [PASSED] 46 VFs
[14:45:04] [PASSED] 47 VFs
[14:45:04] [PASSED] 48 VFs
[14:45:04] [PASSED] 49 VFs
[14:45:04] [PASSED] 50 VFs
[14:45:04] [PASSED] 51 VFs
[14:45:04] [PASSED] 52 VFs
[14:45:04] [PASSED] 53 VFs
[14:45:04] [PASSED] 54 VFs
[14:45:04] [PASSED] 55 VFs
[14:45:04] [PASSED] 56 VFs
[14:45:04] [PASSED] 57 VFs
[14:45:04] [PASSED] 58 VFs
[14:45:04] [PASSED] 59 VFs
[14:45:04] [PASSED] 60 VFs
[14:45:04] [PASSED] 61 VFs
[14:45:04] [PASSED] 62 VFs
[14:45:04] [PASSED] 63 VFs
[14:45:04] ================= [PASSED] fair_doorbells ==================
[14:45:04] ======================== fair_ggtt ========================
[14:45:04] [PASSED] 1 VF
[14:45:04] [PASSED] 2 VFs
[14:45:04] [PASSED] 3 VFs
[14:45:04] [PASSED] 4 VFs
[14:45:04] [PASSED] 5 VFs
[14:45:04] [PASSED] 6 VFs
[14:45:04] [PASSED] 7 VFs
[14:45:04] [PASSED] 8 VFs
[14:45:04] [PASSED] 9 VFs
[14:45:04] [PASSED] 10 VFs
[14:45:04] [PASSED] 11 VFs
[14:45:04] [PASSED] 12 VFs
[14:45:04] [PASSED] 13 VFs
[14:45:04] [PASSED] 14 VFs
[14:45:04] [PASSED] 15 VFs
[14:45:04] [PASSED] 16 VFs
[14:45:04] [PASSED] 17 VFs
[14:45:04] [PASSED] 18 VFs
[14:45:04] [PASSED] 19 VFs
[14:45:04] [PASSED] 20 VFs
[14:45:04] [PASSED] 21 VFs
[14:45:04] [PASSED] 22 VFs
[14:45:04] [PASSED] 23 VFs
[14:45:04] [PASSED] 24 VFs
[14:45:04] [PASSED] 25 VFs
[14:45:04] [PASSED] 26 VFs
[14:45:04] [PASSED] 27 VFs
[14:45:04] [PASSED] 28 VFs
[14:45:04] [PASSED] 29 VFs
[14:45:04] [PASSED] 30 VFs
[14:45:04] [PASSED] 31 VFs
[14:45:04] [PASSED] 32 VFs
[14:45:04] [PASSED] 33 VFs
[14:45:04] [PASSED] 34 VFs
[14:45:04] [PASSED] 35 VFs
[14:45:04] [PASSED] 36 VFs
[14:45:04] [PASSED] 37 VFs
[14:45:04] [PASSED] 38 VFs
[14:45:04] [PASSED] 39 VFs
[14:45:04] [PASSED] 40 VFs
[14:45:04] [PASSED] 41 VFs
[14:45:04] [PASSED] 42 VFs
[14:45:04] [PASSED] 43 VFs
[14:45:04] [PASSED] 44 VFs
[14:45:04] [PASSED] 45 VFs
[14:45:04] [PASSED] 46 VFs
[14:45:04] [PASSED] 47 VFs
[14:45:04] [PASSED] 48 VFs
[14:45:04] [PASSED] 49 VFs
[14:45:04] [PASSED] 50 VFs
[14:45:04] [PASSED] 51 VFs
[14:45:04] [PASSED] 52 VFs
[14:45:04] [PASSED] 53 VFs
[14:45:04] [PASSED] 54 VFs
[14:45:04] [PASSED] 55 VFs
[14:45:04] [PASSED] 56 VFs
[14:45:04] [PASSED] 57 VFs
[14:45:04] [PASSED] 58 VFs
[14:45:04] [PASSED] 59 VFs
[14:45:04] [PASSED] 60 VFs
[14:45:04] [PASSED] 61 VFs
[14:45:04] [PASSED] 62 VFs
[14:45:04] [PASSED] 63 VFs
[14:45:04] ==================== [PASSED] fair_ggtt ====================
[14:45:04] ================== [PASSED] pf_gt_config ===================
[14:45:04] ===================== lmtt (1 subtest) =====================
[14:45:04] ======================== test_ops =========================
[14:45:04] [PASSED] 2-level
[14:45:04] [PASSED] multi-level
[14:45:04] ==================== [PASSED] test_ops =====================
[14:45:04] ====================== [PASSED] lmtt =======================
[14:45:04] ================= pf_service (11 subtests) =================
[14:45:04] [PASSED] pf_negotiate_any
[14:45:04] [PASSED] pf_negotiate_base_match
[14:45:04] [PASSED] pf_negotiate_base_newer
[14:45:04] [PASSED] pf_negotiate_base_next
[14:45:04] [SKIPPED] pf_negotiate_base_older
[14:45:04] [PASSED] pf_negotiate_base_prev
[14:45:04] [PASSED] pf_negotiate_latest_match
[14:45:04] [PASSED] pf_negotiate_latest_newer
[14:45:04] [PASSED] pf_negotiate_latest_next
[14:45:04] [SKIPPED] pf_negotiate_latest_older
[14:45:04] [SKIPPED] pf_negotiate_latest_prev
[14:45:04] =================== [PASSED] pf_service ====================
[14:45:04] ================= xe_guc_g2g (2 subtests) ==================
[14:45:04] ============== xe_live_guc_g2g_kunit_default ==============
[14:45:04] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[14:45:04] ============== xe_live_guc_g2g_kunit_allmem ===============
[14:45:04] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[14:45:04] =================== [SKIPPED] xe_guc_g2g ===================
[14:45:04] =================== xe_mocs (2 subtests) ===================
[14:45:04] ================ xe_live_mocs_kernel_kunit ================
[14:45:04] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[14:45:04] ================ xe_live_mocs_reset_kunit =================
[14:45:04] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[14:45:04] ==================== [SKIPPED] xe_mocs =====================
[14:45:04] ================= xe_migrate (2 subtests) ==================
[14:45:04] ================= xe_migrate_sanity_kunit =================
[14:45:04] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[14:45:04] ================== xe_validate_ccs_kunit ==================
[14:45:04] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[14:45:04] =================== [SKIPPED] xe_migrate ===================
[14:45:04] ================== xe_dma_buf (1 subtest) ==================
[14:45:04] ==================== xe_dma_buf_kunit =====================
[14:45:04] ================ [SKIPPED] xe_dma_buf_kunit ================
[14:45:04] =================== [SKIPPED] xe_dma_buf ===================
[14:45:04] ================= xe_bo_shrink (1 subtest) =================
[14:45:04] =================== xe_bo_shrink_kunit ====================
[14:45:04] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[14:45:04] ================== [SKIPPED] xe_bo_shrink ==================
[14:45:04] ==================== xe_bo (2 subtests) ====================
[14:45:04] ================== xe_ccs_migrate_kunit ===================
[14:45:04] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[14:45:04] ==================== xe_bo_evict_kunit ====================
[14:45:04] =============== [SKIPPED] xe_bo_evict_kunit ================
[14:45:04] ===================== [SKIPPED] xe_bo ======================
[14:45:04] ==================== args (11 subtests) ====================
[14:45:04] [PASSED] count_args_test
[14:45:04] [PASSED] call_args_example
[14:45:04] [PASSED] call_args_test
[14:45:04] [PASSED] drop_first_arg_example
[14:45:04] [PASSED] drop_first_arg_test
[14:45:04] [PASSED] first_arg_example
[14:45:04] [PASSED] first_arg_test
[14:45:04] [PASSED] last_arg_example
[14:45:04] [PASSED] last_arg_test
[14:45:04] [PASSED] pick_arg_example
[14:45:04] [PASSED] sep_comma_example
[14:45:04] ====================== [PASSED] args =======================
[14:45:04] =================== xe_pci (3 subtests) ====================
[14:45:04] ==================== check_graphics_ip ====================
[14:45:04] [PASSED] 12.00 Xe_LP
[14:45:04] [PASSED] 12.10 Xe_LP+
[14:45:04] [PASSED] 12.55 Xe_HPG
[14:45:04] [PASSED] 12.60 Xe_HPC
[14:45:04] [PASSED] 12.70 Xe_LPG
[14:45:04] [PASSED] 12.71 Xe_LPG
[14:45:04] [PASSED] 12.74 Xe_LPG+
[14:45:04] [PASSED] 20.01 Xe2_HPG
[14:45:04] [PASSED] 20.02 Xe2_HPG
[14:45:04] [PASSED] 20.04 Xe2_LPG
[14:45:04] [PASSED] 30.00 Xe3_LPG
[14:45:04] [PASSED] 30.01 Xe3_LPG
[14:45:04] [PASSED] 30.03 Xe3_LPG
[14:45:04] [PASSED] 30.04 Xe3_LPG
[14:45:04] [PASSED] 30.05 Xe3_LPG
[14:45:04] [PASSED] 35.11 Xe3p_XPC
[14:45:04] ================ [PASSED] check_graphics_ip ================
[14:45:04] ===================== check_media_ip ======================
[14:45:04] [PASSED] 12.00 Xe_M
[14:45:04] [PASSED] 12.55 Xe_HPM
[14:45:04] [PASSED] 13.00 Xe_LPM+
[14:45:04] [PASSED] 13.01 Xe2_HPM
[14:45:04] [PASSED] 20.00 Xe2_LPM
[14:45:04] [PASSED] 30.00 Xe3_LPM
[14:45:04] [PASSED] 30.02 Xe3_LPM
[14:45:04] [PASSED] 35.00 Xe3p_LPM
[14:45:04] [PASSED] 35.03 Xe3p_HPM
[14:45:04] ================= [PASSED] check_media_ip ==================
[14:45:04] =================== check_platform_desc ===================
[14:45:04] [PASSED] 0x9A60 (TIGERLAKE)
[14:45:04] [PASSED] 0x9A68 (TIGERLAKE)
[14:45:04] [PASSED] 0x9A70 (TIGERLAKE)
[14:45:04] [PASSED] 0x9A40 (TIGERLAKE)
[14:45:04] [PASSED] 0x9A49 (TIGERLAKE)
[14:45:04] [PASSED] 0x9A59 (TIGERLAKE)
[14:45:04] [PASSED] 0x9A78 (TIGERLAKE)
[14:45:04] [PASSED] 0x9AC0 (TIGERLAKE)
[14:45:04] [PASSED] 0x9AC9 (TIGERLAKE)
[14:45:04] [PASSED] 0x9AD9 (TIGERLAKE)
[14:45:04] [PASSED] 0x9AF8 (TIGERLAKE)
[14:45:04] [PASSED] 0x4C80 (ROCKETLAKE)
[14:45:04] [PASSED] 0x4C8A (ROCKETLAKE)
[14:45:04] [PASSED] 0x4C8B (ROCKETLAKE)
[14:45:04] [PASSED] 0x4C8C (ROCKETLAKE)
[14:45:04] [PASSED] 0x4C90 (ROCKETLAKE)
[14:45:04] [PASSED] 0x4C9A (ROCKETLAKE)
[14:45:04] [PASSED] 0x4680 (ALDERLAKE_S)
[14:45:04] [PASSED] 0x4682 (ALDERLAKE_S)
[14:45:04] [PASSED] 0x4688 (ALDERLAKE_S)
[14:45:04] [PASSED] 0x468A (ALDERLAKE_S)
[14:45:04] [PASSED] 0x468B (ALDERLAKE_S)
[14:45:04] [PASSED] 0x4690 (ALDERLAKE_S)
[14:45:04] [PASSED] 0x4692 (ALDERLAKE_S)
[14:45:04] [PASSED] 0x4693 (ALDERLAKE_S)
[14:45:04] [PASSED] 0x46A0 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46A1 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46A2 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46A3 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46A6 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46A8 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46AA (ALDERLAKE_P)
[14:45:04] [PASSED] 0x462A (ALDERLAKE_P)
[14:45:04] [PASSED] 0x4626 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x4628 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[14:45:04] [PASSED] 0x46B1 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46B2 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46B3 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46C0 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46C1 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46C2 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46C3 (ALDERLAKE_P)
[14:45:04] [PASSED] 0x46D0 (ALDERLAKE_N)
[14:45:04] [PASSED] 0x46D1 (ALDERLAKE_N)
[14:45:04] [PASSED] 0x46D2 (ALDERLAKE_N)
[14:45:04] [PASSED] 0x46D3 (ALDERLAKE_N)
[14:45:04] [PASSED] 0x46D4 (ALDERLAKE_N)
[14:45:04] [PASSED] 0xA721 (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7A1 (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7A9 (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7AC (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7AD (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA720 (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7A0 (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7A8 (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7AA (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA7AB (ALDERLAKE_P)
[14:45:04] [PASSED] 0xA780 (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA781 (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA782 (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA783 (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA788 (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA789 (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA78A (ALDERLAKE_S)
[14:45:04] [PASSED] 0xA78B (ALDERLAKE_S)
[14:45:04] [PASSED] 0x4905 (DG1)
[14:45:04] [PASSED] 0x4906 (DG1)
[14:45:04] [PASSED] 0x4907 (DG1)
[14:45:04] [PASSED] 0x4908 (DG1)
[14:45:04] [PASSED] 0x4909 (DG1)
[14:45:04] [PASSED] 0x56C0 (DG2)
[14:45:04] [PASSED] 0x56C2 (DG2)
[14:45:04] [PASSED] 0x56C1 (DG2)
[14:45:04] [PASSED] 0x7D51 (METEORLAKE)
[14:45:04] [PASSED] 0x7DD1 (METEORLAKE)
[14:45:04] [PASSED] 0x7D41 (METEORLAKE)
[14:45:04] [PASSED] 0x7D67 (METEORLAKE)
[14:45:04] [PASSED] 0xB640 (METEORLAKE)
[14:45:04] [PASSED] 0x56A0 (DG2)
[14:45:04] [PASSED] 0x56A1 (DG2)
[14:45:04] [PASSED] 0x56A2 (DG2)
[14:45:04] [PASSED] 0x56BE (DG2)
[14:45:04] [PASSED] 0x56BF (DG2)
[14:45:04] [PASSED] 0x5690 (DG2)
[14:45:04] [PASSED] 0x5691 (DG2)
[14:45:04] [PASSED] 0x5692 (DG2)
[14:45:04] [PASSED] 0x56A5 (DG2)
[14:45:04] [PASSED] 0x56A6 (DG2)
[14:45:04] [PASSED] 0x56B0 (DG2)
[14:45:04] [PASSED] 0x56B1 (DG2)
[14:45:04] [PASSED] 0x56BA (DG2)
[14:45:04] [PASSED] 0x56BB (DG2)
[14:45:04] [PASSED] 0x56BC (DG2)
[14:45:04] [PASSED] 0x56BD (DG2)
[14:45:04] [PASSED] 0x5693 (DG2)
[14:45:04] [PASSED] 0x5694 (DG2)
[14:45:04] [PASSED] 0x5695 (DG2)
[14:45:04] [PASSED] 0x56A3 (DG2)
[14:45:04] [PASSED] 0x56A4 (DG2)
[14:45:04] [PASSED] 0x56B2 (DG2)
[14:45:04] [PASSED] 0x56B3 (DG2)
[14:45:04] [PASSED] 0x5696 (DG2)
[14:45:04] [PASSED] 0x5697 (DG2)
[14:45:04] [PASSED] 0xB69 (PVC)
[14:45:04] [PASSED] 0xB6E (PVC)
[14:45:04] [PASSED] 0xBD4 (PVC)
[14:45:04] [PASSED] 0xBD5 (PVC)
[14:45:04] [PASSED] 0xBD6 (PVC)
[14:45:04] [PASSED] 0xBD7 (PVC)
[14:45:04] [PASSED] 0xBD8 (PVC)
[14:45:04] [PASSED] 0xBD9 (PVC)
[14:45:04] [PASSED] 0xBDA (PVC)
[14:45:04] [PASSED] 0xBDB (PVC)
[14:45:04] [PASSED] 0xBE0 (PVC)
[14:45:04] [PASSED] 0xBE1 (PVC)
[14:45:04] [PASSED] 0xBE5 (PVC)
[14:45:04] [PASSED] 0x7D40 (METEORLAKE)
[14:45:04] [PASSED] 0x7D45 (METEORLAKE)
[14:45:04] [PASSED] 0x7D55 (METEORLAKE)
[14:45:04] [PASSED] 0x7D60 (METEORLAKE)
[14:45:04] [PASSED] 0x7DD5 (METEORLAKE)
[14:45:04] [PASSED] 0x6420 (LUNARLAKE)
[14:45:04] [PASSED] 0x64A0 (LUNARLAKE)
[14:45:04] [PASSED] 0x64B0 (LUNARLAKE)
[14:45:04] [PASSED] 0xE202 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE209 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE20B (BATTLEMAGE)
[14:45:04] [PASSED] 0xE20C (BATTLEMAGE)
[14:45:04] [PASSED] 0xE20D (BATTLEMAGE)
[14:45:04] [PASSED] 0xE210 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE211 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE212 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE216 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE220 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE221 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE222 (BATTLEMAGE)
[14:45:04] [PASSED] 0xE223 (BATTLEMAGE)
[14:45:04] [PASSED] 0xB080 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB081 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB082 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB083 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB084 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB085 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB086 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB087 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB08F (PANTHERLAKE)
[14:45:04] [PASSED] 0xB090 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB0A0 (PANTHERLAKE)
[14:45:04] [PASSED] 0xB0B0 (PANTHERLAKE)
[14:45:04] [PASSED] 0xD740 (NOVALAKE_S)
[14:45:04] [PASSED] 0xD741 (NOVALAKE_S)
[14:45:04] [PASSED] 0xD742 (NOVALAKE_S)
[14:45:04] [PASSED] 0xD743 (NOVALAKE_S)
[14:45:04] [PASSED] 0xD744 (NOVALAKE_S)
[14:45:04] [PASSED] 0xD745 (NOVALAKE_S)
[14:45:04] [PASSED] 0x674C (CRESCENTISLAND)
[14:45:04] [PASSED] 0xFD80 (PANTHERLAKE)
[14:45:04] [PASSED] 0xFD81 (PANTHERLAKE)
[14:45:04] =============== [PASSED] check_platform_desc ===============
[14:45:04] ===================== [PASSED] xe_pci ======================
[14:45:04] =================== xe_rtp (2 subtests) ====================
[14:45:04] =============== xe_rtp_process_to_sr_tests ================
[14:45:04] [PASSED] coalesce-same-reg
[14:45:04] [PASSED] no-match-no-add
[14:45:04] [PASSED] match-or
[14:45:04] [PASSED] match-or-xfail
[14:45:04] [PASSED] no-match-no-add-multiple-rules
[14:45:04] [PASSED] two-regs-two-entries
[14:45:04] [PASSED] clr-one-set-other
[14:45:04] [PASSED] set-field
[14:45:04] [PASSED] conflict-duplicate
[14:45:04] [PASSED] conflict-not-disjoint
[14:45:04] [PASSED] conflict-reg-type
[14:45:04] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[14:45:04] ================== xe_rtp_process_tests ===================
[14:45:04] [PASSED] active1
[14:45:04] [PASSED] active2
[14:45:04] [PASSED] active-inactive
[14:45:04] [PASSED] inactive-active
[14:45:04] [PASSED] inactive-1st_or_active-inactive
[14:45:04] [PASSED] inactive-2nd_or_active-inactive
[14:45:04] [PASSED] inactive-last_or_active-inactive
[14:45:04] [PASSED] inactive-no_or_active-inactive
[14:45:04] ============== [PASSED] xe_rtp_process_tests ===============
[14:45:04] ===================== [PASSED] xe_rtp ======================
[14:45:04] ==================== xe_wa (1 subtest) =====================
[14:45:04] ======================== xe_wa_gt =========================
[14:45:04] [PASSED] TIGERLAKE B0
[14:45:04] [PASSED] DG1 A0
[14:45:04] [PASSED] DG1 B0
[14:45:04] [PASSED] ALDERLAKE_S A0
[14:45:04] [PASSED] ALDERLAKE_S B0
[14:45:04] [PASSED] ALDERLAKE_S C0
[14:45:04] [PASSED] ALDERLAKE_S D0
[14:45:04] [PASSED] ALDERLAKE_P A0
[14:45:04] [PASSED] ALDERLAKE_P B0
[14:45:04] [PASSED] ALDERLAKE_P C0
[14:45:04] [PASSED] ALDERLAKE_S RPLS D0
[14:45:04] [PASSED] ALDERLAKE_P RPLU E0
[14:45:04] [PASSED] DG2 G10 C0
[14:45:04] [PASSED] DG2 G11 B1
[14:45:04] [PASSED] DG2 G12 A1
[14:45:04] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:45:04] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[14:45:04] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[14:45:04] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[14:45:04] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[14:45:04] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[14:45:04] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[14:45:04] ==================== [PASSED] xe_wa_gt =====================
[14:45:04] ====================== [PASSED] xe_wa ======================
[14:45:04] ============================================================
[14:45:04] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[14:45:04] Elapsed time: 42.510s total, 4.279s configuring, 37.714s building, 0.474s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[14:45:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:45:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:45:36] Starting KUnit Kernel (1/1)...
[14:45:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:45:36] ============ drm_test_pick_cmdline (2 subtests) ============
[14:45:36] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[14:45:36] =============== drm_test_pick_cmdline_named ===============
[14:45:36] [PASSED] NTSC
[14:45:36] [PASSED] NTSC-J
[14:45:36] [PASSED] PAL
[14:45:36] [PASSED] PAL-M
[14:45:36] =========== [PASSED] drm_test_pick_cmdline_named ===========
[14:45:36] ============== [PASSED] drm_test_pick_cmdline ==============
[14:45:36] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[14:45:36] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[14:45:36] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[14:45:36] =========== drm_validate_clone_mode (2 subtests) ===========
[14:45:36] ============== drm_test_check_in_clone_mode ===============
[14:45:36] [PASSED] in_clone_mode
[14:45:36] [PASSED] not_in_clone_mode
[14:45:36] ========== [PASSED] drm_test_check_in_clone_mode ===========
[14:45:36] =============== drm_test_check_valid_clones ===============
[14:45:36] [PASSED] not_in_clone_mode
[14:45:36] [PASSED] valid_clone
[14:45:36] [PASSED] invalid_clone
[14:45:36] =========== [PASSED] drm_test_check_valid_clones ===========
[14:45:36] ============= [PASSED] drm_validate_clone_mode =============
[14:45:36] ============= drm_validate_modeset (1 subtest) =============
[14:45:36] [PASSED] drm_test_check_connector_changed_modeset
[14:45:36] ============== [PASSED] drm_validate_modeset ===============
[14:45:36] ====== drm_test_bridge_get_current_state (2 subtests) ======
[14:45:36] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[14:45:36] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[14:45:36] ======== [PASSED] drm_test_bridge_get_current_state ========
[14:45:36] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[14:45:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[14:45:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[14:45:36] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[14:45:36] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[14:45:36] ============== drm_bridge_alloc (2 subtests) ===============
[14:45:36] [PASSED] drm_test_drm_bridge_alloc_basic
[14:45:36] [PASSED] drm_test_drm_bridge_alloc_get_put
[14:45:36] ================ [PASSED] drm_bridge_alloc =================
[14:45:36] ================== drm_buddy (8 subtests) ==================
[14:45:36] [PASSED] drm_test_buddy_alloc_limit
[14:45:36] [PASSED] drm_test_buddy_alloc_optimistic
[14:45:36] [PASSED] drm_test_buddy_alloc_pessimistic
[14:45:36] [PASSED] drm_test_buddy_alloc_pathological
[14:45:36] [PASSED] drm_test_buddy_alloc_contiguous
[14:45:36] [PASSED] drm_test_buddy_alloc_clear
[14:45:36] [PASSED] drm_test_buddy_alloc_range_bias
[14:45:36] [PASSED] drm_test_buddy_fragmentation_performance
[14:45:36] ==================== [PASSED] drm_buddy ====================
[14:45:36] ============= drm_cmdline_parser (40 subtests) =============
[14:45:36] [PASSED] drm_test_cmdline_force_d_only
[14:45:36] [PASSED] drm_test_cmdline_force_D_only_dvi
[14:45:36] [PASSED] drm_test_cmdline_force_D_only_hdmi
[14:45:36] [PASSED] drm_test_cmdline_force_D_only_not_digital
[14:45:36] [PASSED] drm_test_cmdline_force_e_only
[14:45:36] [PASSED] drm_test_cmdline_res
[14:45:36] [PASSED] drm_test_cmdline_res_vesa
[14:45:36] [PASSED] drm_test_cmdline_res_vesa_rblank
[14:45:36] [PASSED] drm_test_cmdline_res_rblank
[14:45:36] [PASSED] drm_test_cmdline_res_bpp
[14:45:36] [PASSED] drm_test_cmdline_res_refresh
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[14:45:36] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[14:45:36] [PASSED] drm_test_cmdline_res_margins_force_on
[14:45:36] [PASSED] drm_test_cmdline_res_vesa_margins
[14:45:36] [PASSED] drm_test_cmdline_name
[14:45:36] [PASSED] drm_test_cmdline_name_bpp
[14:45:36] [PASSED] drm_test_cmdline_name_option
[14:45:36] [PASSED] drm_test_cmdline_name_bpp_option
[14:45:36] [PASSED] drm_test_cmdline_rotate_0
[14:45:36] [PASSED] drm_test_cmdline_rotate_90
[14:45:36] [PASSED] drm_test_cmdline_rotate_180
[14:45:36] [PASSED] drm_test_cmdline_rotate_270
[14:45:36] [PASSED] drm_test_cmdline_hmirror
[14:45:36] [PASSED] drm_test_cmdline_vmirror
[14:45:36] [PASSED] drm_test_cmdline_margin_options
[14:45:36] [PASSED] drm_test_cmdline_multiple_options
[14:45:36] [PASSED] drm_test_cmdline_bpp_extra_and_option
[14:45:36] [PASSED] drm_test_cmdline_extra_and_option
[14:45:36] [PASSED] drm_test_cmdline_freestanding_options
[14:45:36] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[14:45:36] [PASSED] drm_test_cmdline_panel_orientation
[14:45:36] ================ drm_test_cmdline_invalid =================
[14:45:36] [PASSED] margin_only
[14:45:36] [PASSED] interlace_only
[14:45:36] [PASSED] res_missing_x
[14:45:36] [PASSED] res_missing_y
[14:45:36] [PASSED] res_bad_y
[14:45:36] [PASSED] res_missing_y_bpp
[14:45:36] [PASSED] res_bad_bpp
[14:45:36] [PASSED] res_bad_refresh
[14:45:36] [PASSED] res_bpp_refresh_force_on_off
[14:45:36] [PASSED] res_invalid_mode
[14:45:36] [PASSED] res_bpp_wrong_place_mode
[14:45:36] [PASSED] name_bpp_refresh
[14:45:36] [PASSED] name_refresh
[14:45:36] [PASSED] name_refresh_wrong_mode
[14:45:36] [PASSED] name_refresh_invalid_mode
[14:45:36] [PASSED] rotate_multiple
[14:45:36] [PASSED] rotate_invalid_val
[14:45:36] [PASSED] rotate_truncated
[14:45:36] [PASSED] invalid_option
[14:45:36] [PASSED] invalid_tv_option
[14:45:36] [PASSED] truncated_tv_option
[14:45:36] ============ [PASSED] drm_test_cmdline_invalid =============
[14:45:36] =============== drm_test_cmdline_tv_options ===============
[14:45:36] [PASSED] NTSC
[14:45:36] [PASSED] NTSC_443
[14:45:36] [PASSED] NTSC_J
[14:45:36] [PASSED] PAL
[14:45:36] [PASSED] PAL_M
[14:45:36] [PASSED] PAL_N
[14:45:36] [PASSED] SECAM
[14:45:36] [PASSED] MONO_525
[14:45:36] [PASSED] MONO_625
[14:45:36] =========== [PASSED] drm_test_cmdline_tv_options ===========
[14:45:36] =============== [PASSED] drm_cmdline_parser ================
[14:45:36] ========== drmm_connector_hdmi_init (20 subtests) ==========
[14:45:36] [PASSED] drm_test_connector_hdmi_init_valid
[14:45:36] [PASSED] drm_test_connector_hdmi_init_bpc_8
[14:45:36] [PASSED] drm_test_connector_hdmi_init_bpc_10
[14:45:36] [PASSED] drm_test_connector_hdmi_init_bpc_12
[14:45:36] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[14:45:36] [PASSED] drm_test_connector_hdmi_init_bpc_null
[14:45:36] [PASSED] drm_test_connector_hdmi_init_formats_empty
[14:45:36] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[14:45:36] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:45:36] [PASSED] supported_formats=0x9 yuv420_allowed=1
[14:45:36] [PASSED] supported_formats=0x9 yuv420_allowed=0
[14:45:36] [PASSED] supported_formats=0x3 yuv420_allowed=1
[14:45:36] [PASSED] supported_formats=0x3 yuv420_allowed=0
[14:45:36] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[14:45:36] [PASSED] drm_test_connector_hdmi_init_null_ddc
[14:45:36] [PASSED] drm_test_connector_hdmi_init_null_product
[14:45:36] [PASSED] drm_test_connector_hdmi_init_null_vendor
[14:45:36] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[14:45:36] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[14:45:36] [PASSED] drm_test_connector_hdmi_init_product_valid
[14:45:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[14:45:36] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[14:45:36] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[14:45:36] ========= drm_test_connector_hdmi_init_type_valid =========
[14:45:36] [PASSED] HDMI-A
[14:45:36] [PASSED] HDMI-B
[14:45:36] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[14:45:36] ======== drm_test_connector_hdmi_init_type_invalid ========
[14:45:36] [PASSED] Unknown
[14:45:36] [PASSED] VGA
[14:45:36] [PASSED] DVI-I
[14:45:36] [PASSED] DVI-D
[14:45:36] [PASSED] DVI-A
[14:45:36] [PASSED] Composite
[14:45:36] [PASSED] SVIDEO
[14:45:36] [PASSED] LVDS
[14:45:36] [PASSED] Component
[14:45:36] [PASSED] DIN
[14:45:36] [PASSED] DP
[14:45:36] [PASSED] TV
[14:45:36] [PASSED] eDP
[14:45:36] [PASSED] Virtual
[14:45:36] [PASSED] DSI
[14:45:36] [PASSED] DPI
[14:45:36] [PASSED] Writeback
[14:45:36] [PASSED] SPI
[14:45:36] [PASSED] USB
[14:45:36] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[14:45:36] ============ [PASSED] drmm_connector_hdmi_init =============
[14:45:36] ============= drmm_connector_init (3 subtests) =============
[14:45:36] [PASSED] drm_test_drmm_connector_init
[14:45:36] [PASSED] drm_test_drmm_connector_init_null_ddc
[14:45:36] ========= drm_test_drmm_connector_init_type_valid =========
[14:45:36] [PASSED] Unknown
[14:45:36] [PASSED] VGA
[14:45:36] [PASSED] DVI-I
[14:45:36] [PASSED] DVI-D
[14:45:36] [PASSED] DVI-A
[14:45:36] [PASSED] Composite
[14:45:36] [PASSED] SVIDEO
[14:45:36] [PASSED] LVDS
[14:45:36] [PASSED] Component
[14:45:36] [PASSED] DIN
[14:45:36] [PASSED] DP
[14:45:36] [PASSED] HDMI-A
[14:45:36] [PASSED] HDMI-B
[14:45:36] [PASSED] TV
[14:45:36] [PASSED] eDP
[14:45:36] [PASSED] Virtual
[14:45:36] [PASSED] DSI
[14:45:36] [PASSED] DPI
[14:45:36] [PASSED] Writeback
[14:45:36] [PASSED] SPI
[14:45:36] [PASSED] USB
[14:45:36] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[14:45:36] =============== [PASSED] drmm_connector_init ===============
[14:45:36] ========= drm_connector_dynamic_init (6 subtests) ==========
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_init
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_init_properties
[14:45:36] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[14:45:36] [PASSED] Unknown
[14:45:36] [PASSED] VGA
[14:45:36] [PASSED] DVI-I
[14:45:36] [PASSED] DVI-D
[14:45:36] [PASSED] DVI-A
[14:45:36] [PASSED] Composite
[14:45:36] [PASSED] SVIDEO
[14:45:36] [PASSED] LVDS
[14:45:36] [PASSED] Component
[14:45:36] [PASSED] DIN
[14:45:36] [PASSED] DP
[14:45:36] [PASSED] HDMI-A
[14:45:36] [PASSED] HDMI-B
[14:45:36] [PASSED] TV
[14:45:36] [PASSED] eDP
[14:45:36] [PASSED] Virtual
[14:45:36] [PASSED] DSI
[14:45:36] [PASSED] DPI
[14:45:36] [PASSED] Writeback
[14:45:36] [PASSED] SPI
[14:45:36] [PASSED] USB
[14:45:36] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[14:45:36] ======== drm_test_drm_connector_dynamic_init_name =========
[14:45:36] [PASSED] Unknown
[14:45:36] [PASSED] VGA
[14:45:36] [PASSED] DVI-I
[14:45:36] [PASSED] DVI-D
[14:45:36] [PASSED] DVI-A
[14:45:36] [PASSED] Composite
[14:45:36] [PASSED] SVIDEO
[14:45:36] [PASSED] LVDS
[14:45:36] [PASSED] Component
[14:45:36] [PASSED] DIN
[14:45:36] [PASSED] DP
[14:45:36] [PASSED] HDMI-A
[14:45:36] [PASSED] HDMI-B
[14:45:36] [PASSED] TV
[14:45:36] [PASSED] eDP
[14:45:36] [PASSED] Virtual
[14:45:36] [PASSED] DSI
[14:45:36] [PASSED] DPI
[14:45:36] [PASSED] Writeback
[14:45:36] [PASSED] SPI
[14:45:36] [PASSED] USB
[14:45:36] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[14:45:36] =========== [PASSED] drm_connector_dynamic_init ============
[14:45:36] ==== drm_connector_dynamic_register_early (4 subtests) =====
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[14:45:36] ====== [PASSED] drm_connector_dynamic_register_early =======
[14:45:36] ======= drm_connector_dynamic_register (7 subtests) ========
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[14:45:36] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[14:45:36] ========= [PASSED] drm_connector_dynamic_register ==========
[14:45:36] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[14:45:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[14:45:36] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[14:45:36] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[14:45:36] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[14:45:36] ========== drm_test_get_tv_mode_from_name_valid ===========
[14:45:36] [PASSED] NTSC
[14:45:36] [PASSED] NTSC-443
[14:45:36] [PASSED] NTSC-J
[14:45:36] [PASSED] PAL
[14:45:36] [PASSED] PAL-M
[14:45:36] [PASSED] PAL-N
[14:45:36] [PASSED] SECAM
[14:45:36] [PASSED] Mono
[14:45:36] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[14:45:36] [PASSED] drm_test_get_tv_mode_from_name_truncated
[14:45:36] ============ [PASSED] drm_get_tv_mode_from_name ============
[14:45:36] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[14:45:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[14:45:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[14:45:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[14:45:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[14:45:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[14:45:36] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[14:45:36] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[14:45:36] [PASSED] VIC 96
[14:45:36] [PASSED] VIC 97
[14:45:36] [PASSED] VIC 101
[14:45:36] [PASSED] VIC 102
[14:45:36] [PASSED] VIC 106
[14:45:36] [PASSED] VIC 107
[14:45:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[14:45:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[14:45:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[14:45:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[14:45:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[14:45:36] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[14:45:36] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[14:45:36] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[14:45:36] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[14:45:36] [PASSED] Automatic
[14:45:36] [PASSED] Full
[14:45:36] [PASSED] Limited 16:235
[14:45:36] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[14:45:36] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[14:45:36] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[14:45:36] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[14:45:36] === drm_test_drm_hdmi_connector_get_output_format_name ====
[14:45:36] [PASSED] RGB
[14:45:36] [PASSED] YUV 4:2:0
[14:45:36] [PASSED] YUV 4:2:2
[14:45:36] [PASSED] YUV 4:4:4
[14:45:36] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[14:45:36] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[14:45:36] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[14:45:36] ============= drm_damage_helper (21 subtests) ==============
[14:45:36] [PASSED] drm_test_damage_iter_no_damage
[14:45:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[14:45:36] [PASSED] drm_test_damage_iter_no_damage_src_moved
[14:45:36] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[14:45:36] [PASSED] drm_test_damage_iter_no_damage_not_visible
[14:45:36] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[14:45:36] [PASSED] drm_test_damage_iter_no_damage_no_fb
[14:45:36] [PASSED] drm_test_damage_iter_simple_damage
[14:45:36] [PASSED] drm_test_damage_iter_single_damage
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_outside_src
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_src_moved
[14:45:36] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[14:45:36] [PASSED] drm_test_damage_iter_damage
[14:45:36] [PASSED] drm_test_damage_iter_damage_one_intersect
[14:45:36] [PASSED] drm_test_damage_iter_damage_one_outside
[14:45:36] [PASSED] drm_test_damage_iter_damage_src_moved
[14:45:36] [PASSED] drm_test_damage_iter_damage_not_visible
[14:45:36] ================ [PASSED] drm_damage_helper ================
[14:45:36] ============== drm_dp_mst_helper (3 subtests) ==============
[14:45:36] ============== drm_test_dp_mst_calc_pbn_mode ==============
[14:45:36] [PASSED] Clock 154000 BPP 30 DSC disabled
[14:45:36] [PASSED] Clock 234000 BPP 30 DSC disabled
[14:45:36] [PASSED] Clock 297000 BPP 24 DSC disabled
[14:45:36] [PASSED] Clock 332880 BPP 24 DSC enabled
[14:45:36] [PASSED] Clock 324540 BPP 24 DSC enabled
[14:45:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[14:45:36] ============== drm_test_dp_mst_calc_pbn_div ===============
[14:45:36] [PASSED] Link rate 2000000 lane count 4
[14:45:36] [PASSED] Link rate 2000000 lane count 2
[14:45:36] [PASSED] Link rate 2000000 lane count 1
[14:45:36] [PASSED] Link rate 1350000 lane count 4
[14:45:36] [PASSED] Link rate 1350000 lane count 2
[14:45:36] [PASSED] Link rate 1350000 lane count 1
[14:45:36] [PASSED] Link rate 1000000 lane count 4
[14:45:36] [PASSED] Link rate 1000000 lane count 2
[14:45:36] [PASSED] Link rate 1000000 lane count 1
[14:45:36] [PASSED] Link rate 810000 lane count 4
[14:45:36] [PASSED] Link rate 810000 lane count 2
[14:45:36] [PASSED] Link rate 810000 lane count 1
[14:45:36] [PASSED] Link rate 540000 lane count 4
[14:45:36] [PASSED] Link rate 540000 lane count 2
[14:45:36] [PASSED] Link rate 540000 lane count 1
[14:45:36] [PASSED] Link rate 270000 lane count 4
[14:45:36] [PASSED] Link rate 270000 lane count 2
[14:45:36] [PASSED] Link rate 270000 lane count 1
[14:45:36] [PASSED] Link rate 162000 lane count 4
[14:45:36] [PASSED] Link rate 162000 lane count 2
[14:45:36] [PASSED] Link rate 162000 lane count 1
[14:45:36] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[14:45:36] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[14:45:36] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[14:45:36] [PASSED] DP_POWER_UP_PHY with port number
[14:45:36] [PASSED] DP_POWER_DOWN_PHY with port number
[14:45:36] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[14:45:36] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[14:45:36] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[14:45:36] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[14:45:36] [PASSED] DP_QUERY_PAYLOAD with port number
[14:45:36] [PASSED] DP_QUERY_PAYLOAD with VCPI
[14:45:36] [PASSED] DP_REMOTE_DPCD_READ with port number
[14:45:36] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[14:45:36] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[14:45:36] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[14:45:36] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[14:45:36] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[14:45:36] [PASSED] DP_REMOTE_I2C_READ with port number
[14:45:36] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[14:45:36] [PASSED] DP_REMOTE_I2C_READ with transactions array
[14:45:36] [PASSED] DP_REMOTE_I2C_WRITE with port number
[14:45:36] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[14:45:36] [PASSED] DP_REMOTE_I2C_WRITE with data array
[14:45:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[14:45:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[14:45:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[14:45:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[14:45:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[14:45:36] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[14:45:36] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[14:45:36] ================ [PASSED] drm_dp_mst_helper ================
[14:45:36] ================== drm_exec (7 subtests) ===================
[14:45:36] [PASSED] sanitycheck
[14:45:36] [PASSED] test_lock
[14:45:36] [PASSED] test_lock_unlock
[14:45:36] [PASSED] test_duplicates
[14:45:36] [PASSED] test_prepare
[14:45:36] [PASSED] test_prepare_array
[14:45:36] [PASSED] test_multiple_loops
[14:45:36] ==================== [PASSED] drm_exec =====================
[14:45:36] =========== drm_format_helper_test (17 subtests) ===========
[14:45:36] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[14:45:36] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[14:45:36] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[14:45:36] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[14:45:36] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[14:45:36] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[14:45:36] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[14:45:36] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[14:45:36] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[14:45:36] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[14:45:36] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[14:45:36] ============== drm_test_fb_xrgb8888_to_mono ===============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[14:45:36] ==================== drm_test_fb_swab =====================
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ================ [PASSED] drm_test_fb_swab =================
[14:45:36] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[14:45:36] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[14:45:36] [PASSED] single_pixel_source_buffer
[14:45:36] [PASSED] single_pixel_clip_rectangle
[14:45:36] [PASSED] well_known_colors
[14:45:36] [PASSED] destination_pitch
[14:45:36] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[14:45:36] ================= drm_test_fb_clip_offset =================
[14:45:36] [PASSED] pass through
[14:45:36] [PASSED] horizontal offset
[14:45:36] [PASSED] vertical offset
[14:45:36] [PASSED] horizontal and vertical offset
[14:45:36] [PASSED] horizontal offset (custom pitch)
[14:45:36] [PASSED] vertical offset (custom pitch)
[14:45:36] [PASSED] horizontal and vertical offset (custom pitch)
[14:45:36] ============= [PASSED] drm_test_fb_clip_offset =============
[14:45:36] =================== drm_test_fb_memcpy ====================
[14:45:36] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[14:45:36] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[14:45:36] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[14:45:36] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[14:45:36] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[14:45:36] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[14:45:36] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[14:45:36] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[14:45:36] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[14:45:36] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[14:45:36] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[14:45:36] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[14:45:36] =============== [PASSED] drm_test_fb_memcpy ================
[14:45:36] ============= [PASSED] drm_format_helper_test ==============
[14:45:36] ================= drm_format (18 subtests) =================
[14:45:36] [PASSED] drm_test_format_block_width_invalid
[14:45:36] [PASSED] drm_test_format_block_width_one_plane
[14:45:36] [PASSED] drm_test_format_block_width_two_plane
[14:45:36] [PASSED] drm_test_format_block_width_three_plane
[14:45:36] [PASSED] drm_test_format_block_width_tiled
[14:45:36] [PASSED] drm_test_format_block_height_invalid
[14:45:36] [PASSED] drm_test_format_block_height_one_plane
[14:45:36] [PASSED] drm_test_format_block_height_two_plane
[14:45:36] [PASSED] drm_test_format_block_height_three_plane
[14:45:36] [PASSED] drm_test_format_block_height_tiled
[14:45:36] [PASSED] drm_test_format_min_pitch_invalid
[14:45:36] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[14:45:36] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[14:45:36] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[14:45:36] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[14:45:36] [PASSED] drm_test_format_min_pitch_two_plane
[14:45:36] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[14:45:36] [PASSED] drm_test_format_min_pitch_tiled
[14:45:36] =================== [PASSED] drm_format ====================
[14:45:36] ============== drm_framebuffer (10 subtests) ===============
[14:45:36] ========== drm_test_framebuffer_check_src_coords ==========
[14:45:36] [PASSED] Success: source fits into fb
[14:45:36] [PASSED] Fail: overflowing fb with x-axis coordinate
[14:45:36] [PASSED] Fail: overflowing fb with y-axis coordinate
[14:45:36] [PASSED] Fail: overflowing fb with source width
[14:45:36] [PASSED] Fail: overflowing fb with source height
[14:45:36] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[14:45:36] [PASSED] drm_test_framebuffer_cleanup
[14:45:36] =============== drm_test_framebuffer_create ===============
[14:45:36] [PASSED] ABGR8888 normal sizes
[14:45:36] [PASSED] ABGR8888 max sizes
[14:45:36] [PASSED] ABGR8888 pitch greater than min required
[14:45:36] [PASSED] ABGR8888 pitch less than min required
[14:45:36] [PASSED] ABGR8888 Invalid width
[14:45:36] [PASSED] ABGR8888 Invalid buffer handle
[14:45:36] [PASSED] No pixel format
[14:45:36] [PASSED] ABGR8888 Width 0
[14:45:36] [PASSED] ABGR8888 Height 0
[14:45:36] [PASSED] ABGR8888 Out of bound height * pitch combination
[14:45:36] [PASSED] ABGR8888 Large buffer offset
[14:45:36] [PASSED] ABGR8888 Buffer offset for inexistent plane
[14:45:36] [PASSED] ABGR8888 Invalid flag
[14:45:36] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[14:45:36] [PASSED] ABGR8888 Valid buffer modifier
[14:45:36] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[14:45:36] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] NV12 Normal sizes
[14:45:36] [PASSED] NV12 Max sizes
[14:45:36] [PASSED] NV12 Invalid pitch
[14:45:36] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[14:45:36] [PASSED] NV12 different modifier per-plane
[14:45:36] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[14:45:36] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] NV12 Modifier for inexistent plane
[14:45:36] [PASSED] NV12 Handle for inexistent plane
[14:45:36] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[14:45:36] [PASSED] YVU420 Normal sizes
[14:45:36] [PASSED] YVU420 Max sizes
[14:45:36] [PASSED] YVU420 Invalid pitch
[14:45:36] [PASSED] YVU420 Different pitches
[14:45:36] [PASSED] YVU420 Different buffer offsets/pitches
[14:45:36] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[14:45:36] [PASSED] YVU420 Valid modifier
[14:45:36] [PASSED] YVU420 Different modifiers per plane
[14:45:36] [PASSED] YVU420 Modifier for inexistent plane
[14:45:36] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[14:45:36] [PASSED] X0L2 Normal sizes
[14:45:36] [PASSED] X0L2 Max sizes
[14:45:36] [PASSED] X0L2 Invalid pitch
[14:45:36] [PASSED] X0L2 Pitch greater than minimum required
[14:45:36] [PASSED] X0L2 Handle for inexistent plane
[14:45:36] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[14:45:36] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[14:45:36] [PASSED] X0L2 Valid modifier
[14:45:36] [PASSED] X0L2 Modifier for inexistent plane
[14:45:36] =========== [PASSED] drm_test_framebuffer_create ===========
[14:45:36] [PASSED] drm_test_framebuffer_free
[14:45:36] [PASSED] drm_test_framebuffer_init
[14:45:36] [PASSED] drm_test_framebuffer_init_bad_format
[14:45:36] [PASSED] drm_test_framebuffer_init_dev_mismatch
[14:45:36] [PASSED] drm_test_framebuffer_lookup
[14:45:36] [PASSED] drm_test_framebuffer_lookup_inexistent
[14:45:36] [PASSED] drm_test_framebuffer_modifiers_not_supported
[14:45:36] ================= [PASSED] drm_framebuffer =================
[14:45:36] ================ drm_gem_shmem (8 subtests) ================
[14:45:36] [PASSED] drm_gem_shmem_test_obj_create
[14:45:36] [PASSED] drm_gem_shmem_test_obj_create_private
[14:45:36] [PASSED] drm_gem_shmem_test_pin_pages
[14:45:36] [PASSED] drm_gem_shmem_test_vmap
[14:45:36] [PASSED] drm_gem_shmem_test_get_pages_sgt
[14:45:36] [PASSED] drm_gem_shmem_test_get_sg_table
[14:45:36] [PASSED] drm_gem_shmem_test_madvise
[14:45:36] [PASSED] drm_gem_shmem_test_purge
[14:45:36] ================== [PASSED] drm_gem_shmem ==================
[14:45:36] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[14:45:36] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[14:45:36] [PASSED] Automatic
[14:45:36] [PASSED] Full
[14:45:36] [PASSED] Limited 16:235
[14:45:36] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[14:45:36] [PASSED] drm_test_check_disable_connector
[14:45:36] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[14:45:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[14:45:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[14:45:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[14:45:36] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[14:45:36] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[14:45:36] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[14:45:36] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[14:45:36] [PASSED] drm_test_check_output_bpc_dvi
[14:45:36] [PASSED] drm_test_check_output_bpc_format_vic_1
[14:45:36] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[14:45:36] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[14:45:36] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[14:45:36] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[14:45:36] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[14:45:36] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[14:45:36] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[14:45:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[14:45:36] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[14:45:36] [PASSED] drm_test_check_broadcast_rgb_value
[14:45:36] [PASSED] drm_test_check_bpc_8_value
[14:45:36] [PASSED] drm_test_check_bpc_10_value
[14:45:36] [PASSED] drm_test_check_bpc_12_value
[14:45:36] [PASSED] drm_test_check_format_value
[14:45:36] [PASSED] drm_test_check_tmds_char_value
[14:45:36] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[14:45:36] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[14:45:36] [PASSED] drm_test_check_mode_valid
[14:45:36] [PASSED] drm_test_check_mode_valid_reject
[14:45:36] [PASSED] drm_test_check_mode_valid_reject_rate
[14:45:36] [PASSED] drm_test_check_mode_valid_reject_max_clock
[14:45:36] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[14:45:36] ================= drm_managed (2 subtests) =================
[14:45:36] [PASSED] drm_test_managed_release_action
[14:45:36] [PASSED] drm_test_managed_run_action
[14:45:36] =================== [PASSED] drm_managed ===================
[14:45:36] =================== drm_mm (6 subtests) ====================
[14:45:36] [PASSED] drm_test_mm_init
[14:45:36] [PASSED] drm_test_mm_debug
[14:45:36] [PASSED] drm_test_mm_align32
[14:45:36] [PASSED] drm_test_mm_align64
[14:45:36] [PASSED] drm_test_mm_lowest
[14:45:36] [PASSED] drm_test_mm_highest
[14:45:36] ===================== [PASSED] drm_mm ======================
[14:45:36] ============= drm_modes_analog_tv (5 subtests) =============
[14:45:36] [PASSED] drm_test_modes_analog_tv_mono_576i
[14:45:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[14:45:36] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[14:45:36] [PASSED] drm_test_modes_analog_tv_pal_576i
[14:45:36] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[14:45:36] =============== [PASSED] drm_modes_analog_tv ===============
[14:45:36] ============== drm_plane_helper (2 subtests) ===============
[14:45:36] =============== drm_test_check_plane_state ================
[14:45:36] [PASSED] clipping_simple
[14:45:36] [PASSED] clipping_rotate_reflect
[14:45:36] [PASSED] positioning_simple
[14:45:36] [PASSED] upscaling
[14:45:36] [PASSED] downscaling
[14:45:36] [PASSED] rounding1
[14:45:36] [PASSED] rounding2
[14:45:36] [PASSED] rounding3
[14:45:36] [PASSED] rounding4
[14:45:36] =========== [PASSED] drm_test_check_plane_state ============
[14:45:36] =========== drm_test_check_invalid_plane_state ============
[14:45:36] [PASSED] positioning_invalid
[14:45:36] [PASSED] upscaling_invalid
[14:45:36] [PASSED] downscaling_invalid
[14:45:36] ======= [PASSED] drm_test_check_invalid_plane_state ========
[14:45:36] ================ [PASSED] drm_plane_helper =================
[14:45:36] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[14:45:36] ====== drm_test_connector_helper_tv_get_modes_check =======
[14:45:36] [PASSED] None
[14:45:36] [PASSED] PAL
[14:45:36] [PASSED] NTSC
[14:45:36] [PASSED] Both, NTSC Default
[14:45:36] [PASSED] Both, PAL Default
[14:45:36] [PASSED] Both, NTSC Default, with PAL on command-line
[14:45:36] [PASSED] Both, PAL Default, with NTSC on command-line
[14:45:36] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[14:45:36] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[14:45:36] ================== drm_rect (9 subtests) ===================
[14:45:36] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[14:45:36] [PASSED] drm_test_rect_clip_scaled_not_clipped
[14:45:36] [PASSED] drm_test_rect_clip_scaled_clipped
[14:45:36] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[14:45:36] ================= drm_test_rect_intersect =================
[14:45:36] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[14:45:36] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[14:45:36] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[14:45:36] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[14:45:36] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[14:45:36] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[14:45:36] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[14:45:36] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[14:45:36] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[14:45:36] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[14:45:36] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[14:45:36] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[14:45:36] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[14:45:36] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[14:45:36] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[14:45:36] ============= [PASSED] drm_test_rect_intersect =============
[14:45:36] ================ drm_test_rect_calc_hscale ================
[14:45:36] [PASSED] normal use
[14:45:36] [PASSED] out of max range
[14:45:36] [PASSED] out of min range
[14:45:36] [PASSED] zero dst
[14:45:36] [PASSED] negative src
[14:45:36] [PASSED] negative dst
[14:45:36] ============ [PASSED] drm_test_rect_calc_hscale ============
[14:45:36] ================ drm_test_rect_calc_vscale ================
[14:45:36] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[14:45:36] [PASSED] out of max range
[14:45:36] [PASSED] out of min range
[14:45:36] [PASSED] zero dst
[14:45:36] [PASSED] negative src
[14:45:36] [PASSED] negative dst
[14:45:36] ============ [PASSED] drm_test_rect_calc_vscale ============
[14:45:36] ================== drm_test_rect_rotate ===================
[14:45:36] [PASSED] reflect-x
[14:45:36] [PASSED] reflect-y
[14:45:36] [PASSED] rotate-0
[14:45:36] [PASSED] rotate-90
[14:45:36] [PASSED] rotate-180
[14:45:36] [PASSED] rotate-270
[14:45:36] ============== [PASSED] drm_test_rect_rotate ===============
[14:45:36] ================ drm_test_rect_rotate_inv =================
[14:45:36] [PASSED] reflect-x
[14:45:36] [PASSED] reflect-y
[14:45:36] [PASSED] rotate-0
[14:45:36] [PASSED] rotate-90
[14:45:36] [PASSED] rotate-180
[14:45:36] [PASSED] rotate-270
[14:45:36] ============ [PASSED] drm_test_rect_rotate_inv =============
[14:45:36] ==================== [PASSED] drm_rect =====================
[14:45:36] ============ drm_sysfb_modeset_test (1 subtest) ============
[14:45:36] ============ drm_test_sysfb_build_fourcc_list =============
[14:45:36] [PASSED] no native formats
[14:45:36] [PASSED] XRGB8888 as native format
[14:45:36] [PASSED] remove duplicates
[14:45:36] [PASSED] convert alpha formats
[14:45:36] [PASSED] random formats
[14:45:36] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[14:45:36] ============= [PASSED] drm_sysfb_modeset_test ==============
[14:45:36] ================== drm_fixp (2 subtests) ===================
[14:45:36] [PASSED] drm_test_int2fixp
[14:45:36] [PASSED] drm_test_sm2fixp
[14:45:36] ==================== [PASSED] drm_fixp =====================
[14:45:36] ============================================================
[14:45:36] Testing complete. Ran 624 tests: passed: 624
[14:45:36] Elapsed time: 31.758s total, 1.611s configuring, 29.629s building, 0.459s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[14:45:36] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[14:45:38] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=25
[14:45:47] Starting KUnit Kernel (1/1)...
[14:45:47] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[14:45:47] ================= ttm_device (5 subtests) ==================
[14:45:47] [PASSED] ttm_device_init_basic
[14:45:47] [PASSED] ttm_device_init_multiple
[14:45:47] [PASSED] ttm_device_fini_basic
[14:45:47] [PASSED] ttm_device_init_no_vma_man
[14:45:47] ================== ttm_device_init_pools ==================
[14:45:47] [PASSED] No DMA allocations, no DMA32 required
[14:45:47] [PASSED] DMA allocations, DMA32 required
[14:45:47] [PASSED] No DMA allocations, DMA32 required
[14:45:47] [PASSED] DMA allocations, no DMA32 required
[14:45:47] ============== [PASSED] ttm_device_init_pools ==============
[14:45:47] =================== [PASSED] ttm_device ====================
[14:45:47] ================== ttm_pool (8 subtests) ===================
[14:45:47] ================== ttm_pool_alloc_basic ===================
[14:45:47] [PASSED] One page
[14:45:47] [PASSED] More than one page
[14:45:47] [PASSED] Above the allocation limit
[14:45:47] [PASSED] One page, with coherent DMA mappings enabled
[14:45:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:45:47] ============== [PASSED] ttm_pool_alloc_basic ===============
[14:45:47] ============== ttm_pool_alloc_basic_dma_addr ==============
[14:45:47] [PASSED] One page
[14:45:47] [PASSED] More than one page
[14:45:47] [PASSED] Above the allocation limit
[14:45:47] [PASSED] One page, with coherent DMA mappings enabled
[14:45:47] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[14:45:47] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[14:45:47] [PASSED] ttm_pool_alloc_order_caching_match
[14:45:47] [PASSED] ttm_pool_alloc_caching_mismatch
[14:45:47] [PASSED] ttm_pool_alloc_order_mismatch
[14:45:47] [PASSED] ttm_pool_free_dma_alloc
[14:45:47] [PASSED] ttm_pool_free_no_dma_alloc
[14:45:47] [PASSED] ttm_pool_fini_basic
[14:45:47] ==================== [PASSED] ttm_pool =====================
[14:45:47] ================ ttm_resource (8 subtests) =================
[14:45:47] ================= ttm_resource_init_basic =================
[14:45:47] [PASSED] Init resource in TTM_PL_SYSTEM
[14:45:47] [PASSED] Init resource in TTM_PL_VRAM
[14:45:47] [PASSED] Init resource in a private placement
[14:45:47] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[14:45:47] ============= [PASSED] ttm_resource_init_basic =============
[14:45:47] [PASSED] ttm_resource_init_pinned
[14:45:47] [PASSED] ttm_resource_fini_basic
[14:45:47] [PASSED] ttm_resource_manager_init_basic
[14:45:47] [PASSED] ttm_resource_manager_usage_basic
[14:45:47] [PASSED] ttm_resource_manager_set_used_basic
[14:45:47] [PASSED] ttm_sys_man_alloc_basic
[14:45:47] [PASSED] ttm_sys_man_free_basic
[14:45:47] ================== [PASSED] ttm_resource ===================
[14:45:47] =================== ttm_tt (15 subtests) ===================
[14:45:47] ==================== ttm_tt_init_basic ====================
[14:45:47] [PASSED] Page-aligned size
[14:45:47] [PASSED] Extra pages requested
[14:45:47] ================ [PASSED] ttm_tt_init_basic ================
[14:45:47] [PASSED] ttm_tt_init_misaligned
[14:45:47] [PASSED] ttm_tt_fini_basic
[14:45:47] [PASSED] ttm_tt_fini_sg
[14:45:47] [PASSED] ttm_tt_fini_shmem
[14:45:47] [PASSED] ttm_tt_create_basic
[14:45:47] [PASSED] ttm_tt_create_invalid_bo_type
[14:45:47] [PASSED] ttm_tt_create_ttm_exists
[14:45:47] [PASSED] ttm_tt_create_failed
[14:45:47] [PASSED] ttm_tt_destroy_basic
[14:45:47] [PASSED] ttm_tt_populate_null_ttm
[14:45:47] [PASSED] ttm_tt_populate_populated_ttm
[14:45:47] [PASSED] ttm_tt_unpopulate_basic
[14:45:47] [PASSED] ttm_tt_unpopulate_empty_ttm
[14:45:47] [PASSED] ttm_tt_swapin_basic
[14:45:47] ===================== [PASSED] ttm_tt ======================
[14:45:47] =================== ttm_bo (14 subtests) ===================
[14:45:47] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[14:45:47] [PASSED] Cannot be interrupted and sleeps
[14:45:47] [PASSED] Cannot be interrupted, locks straight away
[14:45:47] [PASSED] Can be interrupted, sleeps
[14:45:47] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[14:45:47] [PASSED] ttm_bo_reserve_locked_no_sleep
[14:45:47] [PASSED] ttm_bo_reserve_no_wait_ticket
[14:45:47] [PASSED] ttm_bo_reserve_double_resv
[14:45:47] [PASSED] ttm_bo_reserve_interrupted
[14:45:47] [PASSED] ttm_bo_reserve_deadlock
[14:45:47] [PASSED] ttm_bo_unreserve_basic
[14:45:47] [PASSED] ttm_bo_unreserve_pinned
[14:45:47] [PASSED] ttm_bo_unreserve_bulk
[14:45:47] [PASSED] ttm_bo_fini_basic
[14:45:47] [PASSED] ttm_bo_fini_shared_resv
[14:45:47] [PASSED] ttm_bo_pin_basic
[14:45:47] [PASSED] ttm_bo_pin_unpin_resource
[14:45:47] [PASSED] ttm_bo_multiple_pin_one_unpin
[14:45:47] ===================== [PASSED] ttm_bo ======================
[14:45:47] ============== ttm_bo_validate (21 subtests) ===============
[14:45:47] ============== ttm_bo_init_reserved_sys_man ===============
[14:45:47] [PASSED] Buffer object for userspace
[14:45:47] [PASSED] Kernel buffer object
[14:45:47] [PASSED] Shared buffer object
[14:45:47] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[14:45:47] ============== ttm_bo_init_reserved_mock_man ==============
[14:45:47] [PASSED] Buffer object for userspace
[14:45:47] [PASSED] Kernel buffer object
[14:45:47] [PASSED] Shared buffer object
[14:45:47] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[14:45:47] [PASSED] ttm_bo_init_reserved_resv
[14:45:47] ================== ttm_bo_validate_basic ==================
[14:45:47] [PASSED] Buffer object for userspace
[14:45:47] [PASSED] Kernel buffer object
[14:45:47] [PASSED] Shared buffer object
[14:45:47] ============== [PASSED] ttm_bo_validate_basic ==============
[14:45:47] [PASSED] ttm_bo_validate_invalid_placement
[14:45:47] ============= ttm_bo_validate_same_placement ==============
[14:45:47] [PASSED] System manager
[14:45:47] [PASSED] VRAM manager
[14:45:47] ========= [PASSED] ttm_bo_validate_same_placement ==========
[14:45:47] [PASSED] ttm_bo_validate_failed_alloc
[14:45:47] [PASSED] ttm_bo_validate_pinned
[14:45:47] [PASSED] ttm_bo_validate_busy_placement
[14:45:47] ================ ttm_bo_validate_multihop =================
[14:45:47] [PASSED] Buffer object for userspace
[14:45:47] [PASSED] Kernel buffer object
[14:45:47] [PASSED] Shared buffer object
[14:45:47] ============ [PASSED] ttm_bo_validate_multihop =============
[14:45:47] ========== ttm_bo_validate_no_placement_signaled ==========
[14:45:47] [PASSED] Buffer object in system domain, no page vector
[14:45:47] [PASSED] Buffer object in system domain with an existing page vector
[14:45:47] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[14:45:47] ======== ttm_bo_validate_no_placement_not_signaled ========
[14:45:47] [PASSED] Buffer object for userspace
[14:45:47] [PASSED] Kernel buffer object
[14:45:47] [PASSED] Shared buffer object
[14:45:47] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[14:45:47] [PASSED] ttm_bo_validate_move_fence_signaled
[14:45:47] ========= ttm_bo_validate_move_fence_not_signaled =========
[14:45:47] [PASSED] Waits for GPU
[14:45:47] [PASSED] Tries to lock straight away
[14:45:47] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[14:45:47] [PASSED] ttm_bo_validate_happy_evict
[14:45:47] [PASSED] ttm_bo_validate_all_pinned_evict
[14:45:47] [PASSED] ttm_bo_validate_allowed_only_evict
[14:45:47] [PASSED] ttm_bo_validate_deleted_evict
[14:45:47] [PASSED] ttm_bo_validate_busy_domain_evict
[14:45:47] [PASSED] ttm_bo_validate_evict_gutting
[14:45:47] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[14:45:47] ================= [PASSED] ttm_bo_validate =================
[14:45:47] ============================================================
[14:45:47] Testing complete. Ran 101 tests: passed: 101
[14:45:47] Elapsed time: 10.950s total, 1.641s configuring, 9.092s building, 0.183s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ CI.checksparse: warning for Selective Fetch and async flip (rev3)
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
` (3 preceding siblings ...)
2025-12-01 14:45 ` ✓ CI.KUnit: success for Selective Fetch and async flip (rev3) Patchwork
@ 2025-12-01 15:03 ` Patchwork
2025-12-01 15:27 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-01 17:25 ` ✗ Xe.CI.Full: failure " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-12-01 15:03 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
== Series Details ==
Series: Selective Fetch and async flip (rev3)
URL : https://patchwork.freedesktop.org/series/158002/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 4ee45005b5548f7cf1ab059413eaaa41dbd2ecf6
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✓ Xe.CI.BAT: success for Selective Fetch and async flip (rev3)
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
` (4 preceding siblings ...)
2025-12-01 15:03 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-12-01 15:27 ` Patchwork
2025-12-01 17:25 ` ✗ Xe.CI.Full: failure " Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-12-01 15:27 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 1854 bytes --]
== Series Details ==
Series: Selective Fetch and async flip (rev3)
URL : https://patchwork.freedesktop.org/series/158002/
State : success
== Summary ==
CI Bug Log - changes from xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c_BAT -> xe-pw-158002v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-158002v3_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_waitfence@engine:
- bat-dg2-oem2: [PASS][1] -> [FAIL][2] ([Intel XE#6519])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/bat-dg2-oem2/igt@xe_waitfence@engine.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/bat-dg2-oem2/igt@xe_waitfence@engine.html
#### Possible fixes ####
* igt@xe_waitfence@abstime:
- bat-dg2-oem2: [TIMEOUT][3] ([Intel XE#6506]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
[Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
Build changes
-------------
* Linux: xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c -> xe-pw-158002v3
IGT_8646: 8646
xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c: 7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c
xe-pw-158002v3: 158002v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/index.html
[-- Attachment #2: Type: text/html, Size: 2441 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* ✗ Xe.CI.Full: failure for Selective Fetch and async flip (rev3)
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
` (5 preceding siblings ...)
2025-12-01 15:27 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-12-01 17:25 ` Patchwork
6 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2025-12-01 17:25 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 49251 bytes --]
== Series Details ==
Series: Selective Fetch and async flip (rev3)
URL : https://patchwork.freedesktop.org/series/158002/
State : failure
== Summary ==
CI Bug Log - changes from xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c_FULL -> xe-pw-158002v3_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-158002v3_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-158002v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-158002v3_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_content_protection@dp-mst-suspend-resume:
- shard-bmg: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_content_protection@dp-mst-suspend-resume.html
Known issues
------------
Here are the changes found in xe-pw-158002v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-read:
- shard-adlp: NOTRUN -> [SKIP][2] ([Intel XE#1125] / [Intel XE#5574])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@intel_hwmon@hwmon-read.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-adlp: NOTRUN -> [SKIP][3] ([Intel XE#1124]) +2 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#2327])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-adlp: NOTRUN -> [SKIP][5] ([Intel XE#316])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: [PASS][6] -> [FAIL][7] ([Intel XE#1231])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +1 other test skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#607])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-adlp: NOTRUN -> [SKIP][10] ([Intel XE#2191])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2887]) +4 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
- shard-adlp: NOTRUN -> [SKIP][12] ([Intel XE#2907])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][13] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc:
- shard-lnl: NOTRUN -> [SKIP][14] ([Intel XE#2887])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-5/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2652] / [Intel XE#787]) +13 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][16] ([Intel XE#787]) +11 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_chamelium_color@ctm-max:
- shard-adlp: NOTRUN -> [SKIP][17] ([Intel XE#306])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2252]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@dp-hpd-for-each-pipe:
- shard-adlp: NOTRUN -> [SKIP][19] ([Intel XE#373]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_chamelium_hpd@dp-hpd-for-each-pipe.html
* igt@kms_chamelium_sharpness_filter@filter-basic:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#6507])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_chamelium_sharpness_filter@filter-basic.html
* igt@kms_colorop@plane-xr30-xr30-bypass:
- shard-adlp: NOTRUN -> [SKIP][21] ([Intel XE#6704]) +2 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_colorop@plane-xr30-xr30-bypass.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2390])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@legacy:
- shard-adlp: NOTRUN -> [SKIP][23] ([Intel XE#455])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@cursor-offscreen-32x32:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2320])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html
* igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1:
- shard-lnl: NOTRUN -> [ABORT][25] ([Intel XE#6675]) +1 other test abort
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-5/igt@kms_cursor_crc@cursor-suspend@pipe-a-edp-1.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-adlp: NOTRUN -> [SKIP][26] ([Intel XE#309])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2291])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-legacy:
- shard-bmg: [PASS][28] -> [SKIP][29] ([Intel XE#2291])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-7/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-bmg: [PASS][30] -> [FAIL][31] ([Intel XE#5299])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-adlp: NOTRUN -> [SKIP][32] ([Intel XE#4331])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2244]) +1 other test skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_feature_discovery@display-2x:
- shard-adlp: NOTRUN -> [SKIP][34] ([Intel XE#702])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_feature_discovery@display-2x.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2316])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-wf_vblank-ts-check:
- shard-adlp: NOTRUN -> [SKIP][36] ([Intel XE#310])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_flip@2x-wf_vblank-ts-check.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-bmg: [PASS][37] -> [SKIP][38] ([Intel XE#2316]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-7/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y:
- shard-adlp: [PASS][39] -> [FAIL][40] ([Intel XE#1874])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render:
- shard-adlp: NOTRUN -> [SKIP][41] ([Intel XE#651]) +3 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#4141]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
- shard-adlp: NOTRUN -> [SKIP][43] ([Intel XE#656]) +8 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcdrrs-suspend:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2311]) +5 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-adlp: NOTRUN -> [SKIP][45] ([Intel XE#653]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2313]) +5 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#2312]) +3 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-onoff.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-adlp: NOTRUN -> [SKIP][48] ([Intel XE#2925] / [Intel XE#346])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#4329])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a:
- shard-bmg: [PASS][50] -> [ABORT][51] ([Intel XE#6675])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a.html
* igt@kms_plane_lowres@tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#2393])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-bmg: [PASS][53] -> [SKIP][54] ([Intel XE#4596])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-x.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
- shard-adlp: NOTRUN -> [SKIP][56] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr@fbc-psr-primary-blt:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_psr@fbc-psr-primary-blt.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-adlp: NOTRUN -> [SKIP][59] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +2 other tests skip
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#1406] / [Intel XE#2414])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-adlp: NOTRUN -> [SKIP][61] ([Intel XE#1127])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#1435])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-system:
- shard-lnl: [PASS][64] -> [ABORT][65] ([Intel XE#6675]) +2 other tests abort
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-4/igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-system.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-1/igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-system.html
* igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-vram01:
- shard-bmg: NOTRUN -> [ABORT][66] ([Intel XE#6675]) +3 other tests abort
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@xe_ccs@suspend-resume@linear-compressed-compfmt0-system-vram01.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-adlp: NOTRUN -> [SKIP][67] ([Intel XE#6360])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_copy_basic@mem-set-linear-0x8fffe:
- shard-adlp: NOTRUN -> [SKIP][68] ([Intel XE#5503])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_copy_basic@mem-set-linear-0x8fffe.html
* igt@xe_create@multigpu-create-massive-size:
- shard-adlp: NOTRUN -> [SKIP][69] ([Intel XE#944]) +1 other test skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_eu_stall@invalid-event-report-count:
- shard-adlp: NOTRUN -> [SKIP][70] ([Intel XE#5626])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_eu_stall@invalid-event-report-count.html
* igt@xe_eudebug@basic-vm-access-parameters-faultable:
- shard-adlp: NOTRUN -> [SKIP][71] ([Intel XE#4837] / [Intel XE#5565]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_eudebug@basic-vm-access-parameters-faultable.html
* igt@xe_eudebug@basic-vm-bind-ufence-reconnect:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#4837]) +2 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@xe_eudebug@basic-vm-bind-ufence-reconnect.html
* igt@xe_eudebug_online@breakpoint-not-in-debug-mode:
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#4837])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-5/igt@xe_eudebug_online@breakpoint-not-in-debug-mode.html
* igt@xe_evict@evict-beng-threads-small-multi-vm:
- shard-adlp: NOTRUN -> [SKIP][74] ([Intel XE#261])
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_evict@evict-beng-threads-small-multi-vm.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-mmap:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2322])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-defer-mmap.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
- shard-adlp: NOTRUN -> [SKIP][76] ([Intel XE#1392] / [Intel XE#5575]) +2 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
* igt@xe_exec_fault_mode@many-invalid-userptr-fault:
- shard-adlp: NOTRUN -> [SKIP][77] ([Intel XE#288] / [Intel XE#5561]) +6 other tests skip
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_exec_fault_mode@many-invalid-userptr-fault.html
* igt@xe_exec_system_allocator@many-mmap-shared:
- shard-adlp: NOTRUN -> [SKIP][78] ([Intel XE#4915]) +76 other tests skip
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_exec_system_allocator@many-mmap-shared.html
* igt@xe_exec_system_allocator@many-stride-malloc-prefetch:
- shard-bmg: [PASS][79] -> [WARN][80] ([Intel XE#5786])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-5/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-7/igt@xe_exec_system_allocator@many-stride-malloc-prefetch.html
* igt@xe_exec_system_allocator@process-many-mmap-remap-ro-dontunmap:
- shard-bmg: [PASS][81] -> [ABORT][82] ([Intel XE#3970])
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-4/igt@xe_exec_system_allocator@process-many-mmap-remap-ro-dontunmap.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-5/igt@xe_exec_system_allocator@process-many-mmap-remap-ro-dontunmap.html
* igt@xe_exec_system_allocator@threads-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#4943]) +5 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@xe_exec_system_allocator@threads-many-stride-mmap-free-huge.html
* igt@xe_gt_freq@freq_fixed_idle:
- shard-dg2-set2: [PASS][84] -> [FAIL][85] ([Intel XE#6407])
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-dg2-466/igt@xe_gt_freq@freq_fixed_idle.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-dg2-432/igt@xe_gt_freq@freq_fixed_idle.html
* igt@xe_module_load@many-reload:
- shard-adlp: [PASS][86] -> [DMESG-WARN][87] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#5244])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@xe_module_load@many-reload.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-2/igt@xe_module_load@many-reload.html
* igt@xe_oa@non-system-wide-paranoid:
- shard-adlp: NOTRUN -> [SKIP][88] ([Intel XE#3573]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_oa@non-system-wide-paranoid.html
* igt@xe_pm@s2idle-vm-bind-unbind-all:
- shard-adlp: [PASS][89] -> [ABORT][90] ([Intel XE#6675]) +7 other tests abort
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-6/igt@xe_pm@s2idle-vm-bind-unbind-all.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-1/igt@xe_pm@s2idle-vm-bind-unbind-all.html
* igt@xe_pm@s3-vm-bind-unbind-all:
- shard-dg2-set2: [PASS][91] -> [ABORT][92] ([Intel XE#6675]) +2 other tests abort
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-dg2-463/igt@xe_pm@s3-vm-bind-unbind-all.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-dg2-466/igt@xe_pm@s3-vm-bind-unbind-all.html
* igt@xe_query@multigpu-query-engines:
- shard-bmg: NOTRUN -> [SKIP][93] ([Intel XE#944])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@xe_query@multigpu-query-engines.html
* igt@xe_render_copy@render-stress-1-copies:
- shard-adlp: NOTRUN -> [SKIP][94] ([Intel XE#4814] / [Intel XE#5614])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_render_copy@render-stress-1-copies.html
* igt@xe_sriov_vram@vf-access-after-resize-up:
- shard-adlp: NOTRUN -> [SKIP][95] ([Intel XE#6376])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_sriov_vram@vf-access-after-resize-up.html
#### Possible fixes ####
* igt@kms_async_flips@async-flip-dpms:
- shard-lnl: [FAIL][96] ([Intel XE#6676]) -> [PASS][97] +5 other tests pass
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-2/igt@kms_async_flips@async-flip-dpms.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-2/igt@kms_async_flips@async-flip-dpms.html
* igt@kms_async_flips@invalid-async-flip@pipe-b-edp-1:
- shard-lnl: [FAIL][98] ([Intel XE#6678]) -> [PASS][99] +5 other tests pass
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-5/igt@kms_async_flips@invalid-async-flip@pipe-b-edp-1.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-3/igt@kms_async_flips@invalid-async-flip@pipe-b-edp-1.html
* igt@kms_async_flips@test-time-stamp-atomic:
- shard-lnl: [FAIL][100] ([Intel XE#6677]) -> [PASS][101] +2 other tests pass
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-3/igt@kms_async_flips@test-time-stamp-atomic.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-8/igt@kms_async_flips@test-time-stamp-atomic.html
* igt@kms_cursor_crc@cursor-size-hints:
- shard-bmg: [INCOMPLETE][102] -> [PASS][103] +1 other test pass
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-3/igt@kms_cursor_crc@cursor-size-hints.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@kms_cursor_crc@cursor-size-hints.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-bmg: [SKIP][104] ([Intel XE#2291]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-bmg: [FAIL][106] ([Intel XE#6715]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [FAIL][108] ([Intel XE#301]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-lnl: [FAIL][110] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][111] +1 other test pass
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y:
- shard-adlp: [FAIL][112] ([Intel XE#1874]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html
* igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-edp-1:
- shard-lnl: [ABORT][114] ([Intel XE#6675]) -> [PASS][115] +2 other tests pass
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-4/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-edp-1.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-2/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-edp-1.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][116] ([Intel XE#6321] / [Intel XE#6606]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_module_load@load:
- shard-adlp: ([PASS][118], [PASS][119], [PASS][120], [PASS][121], [SKIP][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143]) ([Intel XE#378] / [Intel XE#5612]) -> ([PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151], [PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [PASS][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-2/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-2/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-9/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-9/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-3/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-8/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-8/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-4/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-9/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-3/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-3/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-4/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-4/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-8/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-6/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-2/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-1/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-2/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-8/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-6/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-6/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-9/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-4/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-4/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-1/igt@xe_module_load@load.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-1/igt@xe_module_load@load.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-9/igt@xe_module_load@load.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-2/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-2/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-4/igt@xe_module_load@load.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-4/igt@xe_module_load@load.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-1/igt@xe_module_load@load.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-9/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-9/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-6/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-6/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-6/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-8/igt@xe_module_load@load.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-8/igt@xe_module_load@load.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-8/igt@xe_module_load@load.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_module_load@load.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_module_load@load.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_module_load@load.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_module_load@load.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-8/igt@xe_module_load@load.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-2/igt@xe_module_load@load.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-2/igt@xe_module_load@load.html
* igt@xe_pm@s3-vm-bind-prefetch:
- shard-bmg: [ABORT][169] ([Intel XE#6675]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-2/igt@xe_pm@s3-vm-bind-prefetch.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@xe_pm@s3-vm-bind-prefetch.html
* igt@xe_pmu@engine-activity-suspend:
- shard-adlp: [ABORT][171] ([Intel XE#6675]) -> [PASS][172] +3 other tests pass
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-adlp-8/igt@xe_pmu@engine-activity-suspend.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-adlp-3/igt@xe_pmu@engine-activity-suspend.html
#### Warnings ####
* igt@kms_async_flips@async-flip-with-page-flip-events-linear:
- shard-lnl: [FAIL][173] ([Intel XE#5993] / [Intel XE#6676]) -> [FAIL][174] ([Intel XE#5993])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-b-edp-1:
- shard-lnl: [FAIL][175] ([Intel XE#6676]) -> [FAIL][176] ([Intel XE#5993]) +1 other test fail
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-lnl-3/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-b-edp-1.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-b-edp-1.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [INCOMPLETE][177] -> [SKIP][178] ([Intel XE#4302])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible:
- shard-bmg: [ABORT][179] ([Intel XE#6675]) -> [SKIP][180] ([Intel XE#2316])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-8/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_flip@2x-flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][181] ([Intel XE#2311]) -> [SKIP][182] ([Intel XE#2312]) +6 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][183] ([Intel XE#2312]) -> [SKIP][184] ([Intel XE#4141])
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][185] ([Intel XE#4141]) -> [SKIP][186] ([Intel XE#2312]) +4 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
- shard-bmg: [SKIP][187] ([Intel XE#2313]) -> [SKIP][188] ([Intel XE#2312]) +7 other tests skip
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render:
- shard-bmg: [SKIP][189] ([Intel XE#2312]) -> [SKIP][190] ([Intel XE#2313]) +4 other tests skip
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-render.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
[Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
[Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
[Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5244
[Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
[Intel XE#5503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5503
[Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
[Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
[Intel XE#5574]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5574
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5612]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5612
[Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
[Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
[Intel XE#5786]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5786
[Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
[Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
[Intel XE#6407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6407
[Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6606]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6606
[Intel XE#6675]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6675
[Intel XE#6676]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6676
[Intel XE#6677]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6677
[Intel XE#6678]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6678
[Intel XE#6704]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6704
[Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
[Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c -> xe-pw-158002v3
IGT_8646: 8646
xe-4173-7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c: 7f7b6cfa09ab1155b3e92ccfb7ae4bbfd41fec0c
xe-pw-158002v3: 158002v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158002v3/index.html
[-- Attachment #2: Type: text/html, Size: 55616 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR
2025-12-01 13:24 ` [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR Jouni Högander
@ 2025-12-03 13:15 ` Ville Syrjälä
2025-12-04 7:09 ` Hogander, Jouni
2025-12-16 8:38 ` Hogander, Jouni
0 siblings, 2 replies; 18+ messages in thread
From: Ville Syrjälä @ 2025-12-03 13:15 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Mon, Dec 01, 2025 at 03:24:55PM +0200, Jouni Högander wrote:
> Currently plane id bit is set in crtc_state->async_flip_planes only when
> async flip toggle workaround is needed. We want to utilize
> crtc_state->async_flip_planes further in Selective Fetch calculation.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
> index 7b7619d59251..de0a69c55582 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -603,8 +603,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
> if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
> new_crtc_state->do_async_flip = true;
> new_crtc_state->async_flip_planes |= BIT(plane->id);
> - } else if (plane->need_async_flip_toggle_wa &&
> - new_crtc_state->uapi.async_flip) {
> + } else if (new_crtc_state->uapi.async_flip) {
I'd get rid of the if-else construct here now, and just do something
like:
if (intel_plane_do_async_flip(...))
new_crtc_state->do_async_flip = true;
if (new_crtc_state->uapi.async_flip) {
/* ... */
new_crtc_state->async_flip_planes |= BIT(plane->id);
}
We should probably also move the plane->async_flip check
out from intel_plane_do_async_flip() and just make it a
drm_WARN_ON(..., uapi.async_flip && !plane->async_flip).
But that's probably better left for a separate patch.
> /*
> * On platforms with double buffered async flip bit we
> * set the bit already one frame early during the sync
> @@ -612,6 +611,13 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr
> * hardware will therefore be ready to perform a real
> * async flip during the next commit, without having
> * to wait yet another frame for the bit to latch.
> + *
> + * async_flip_planes bitmask is also used by selective
> + * fetch calculation to continue full frame updates as
> + * long as there may be pending async flip on any
> + * plane which is part of selective
> + * update. I.e. old_crtc_state->async_flip_planes &
> + * BIT(<plane in su area>->id).
> */
> new_crtc_state->async_flip_planes |= BIT(plane->id);
> }
> --
> 2.43.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-01 13:24 ` [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip Jouni Högander
@ 2025-12-03 13:22 ` Ville Syrjälä
2025-12-03 13:58 ` Hogander, Jouni
2025-12-04 7:10 ` Hogander, Jouni
0 siblings, 2 replies; 18+ messages in thread
From: Ville Syrjälä @ 2025-12-03 13:22 UTC (permalink / raw)
To: Jouni Högander; +Cc: intel-gfx, intel-xe
On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> According to bspec selective fetch is not supported with async flips and
> instructing full frame update on async flip.
>
> v3:
> - rebase
> - fix old_crtc_state->pipe_srcsz_early_tpt
> - fix using intel_atomic_get_new_crtc_state
> v2:
> - check also crtc_state->async_flip_planes in
> psr2_sel_fetch_plane_state_supported
>
> Bspec: 55229
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++----------
> 1 file changed, 41 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 15ef3b6caad6..53cf292247d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
> * Plane scaling and rotation is not supported by selective fetch and both
> * properties can change without a modeset, so need to be check at every
> * atomic commit.
> + *
> + * If plane was having async flip previously we can't use selective
> + * fetch as we don't know if the flip is completed.
> */
> -static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
> +static bool psr2_sel_fetch_plane_state_supported(const struct intel_crtc_state *old_crtc_state,
> + const struct intel_plane_state *plane_state)
> {
> + struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +
> if (plane_state->uapi.dst.y1 < 0 ||
> plane_state->uapi.dst.x1 < 0 ||
> plane_state->scaler_id >= 0 ||
> - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> + plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> + old_crtc_state->async_flip_planes & plane->id)
Why are you looking at the old crtc state? There should be nothing of
interest to us there.
> return false;
>
> return true;
> @@ -2749,7 +2756,8 @@ static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> */
> static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *crtc_state)
> {
> - if (crtc_state->scaler_state.scaler_id >= 0)
> + if (crtc_state->scaler_state.scaler_id >= 0 ||
> + crtc_state->uapi.async_flip)
I think just checking crtc_state->async_flip_planes!=0 here should be
sufficient. The rest of the patch seems unnecessary.
On a related note, someone should add a new igt that does async flips
while eg. the cursor is enabled and overlapping the plane doing the
async flips. That's basically how I noticed the problem in the first
place (with Xorg), so would be good to have an igt to make sure we
don't break this in the future.
> return false;
>
> return true;
> @@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct intel_display *display = to_intel_display(state);
> - struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> + struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_plane_state *new_plane_state, *old_plane_state;
> struct intel_plane *plane;
> bool full_update = false, cursor_in_su_area = false;
> int i, ret;
>
> - if (!crtc_state->enable_psr2_sel_fetch)
> + if (!new_crtc_state->enable_psr2_sel_fetch)
> return 0;
>
> - if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> + if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state)) {
> full_update = true;
> goto skip_sel_fetch_set_loop;
> }
>
> - crtc_state->psr2_su_area.x1 = 0;
> - crtc_state->psr2_su_area.y1 = -1;
> - crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src);
> - crtc_state->psr2_su_area.y2 = -1;
> + new_crtc_state->psr2_su_area.x1 = 0;
> + new_crtc_state->psr2_su_area.y1 = -1;
> + new_crtc_state->psr2_su_area.x2 = drm_rect_width(&new_crtc_state->pipe_src);
> + new_crtc_state->psr2_su_area.y2 = -1;
>
> /*
> * Calculate minimal selective fetch area of each plane and calculate
> @@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1,
> .x2 = INT_MAX };
>
> - if (new_plane_state->hw.crtc != crtc_state->uapi.crtc)
> + if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc)
> continue;
>
> if (!new_plane_state->uapi.visible &&
> !old_plane_state->uapi.visible)
> continue;
>
> - if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> + if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
> full_update = true;
> break;
> }
> @@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> if (old_plane_state->uapi.visible) {
> damaged_area.y1 = old_plane_state->uapi.dst.y1;
> damaged_area.y2 = old_plane_state->uapi.dst.y2;
> - clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
> - &crtc_state->pipe_src);
> + clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> + &new_crtc_state->pipe_src);
> }
>
> if (new_plane_state->uapi.visible) {
> damaged_area.y1 = new_plane_state->uapi.dst.y1;
> damaged_area.y2 = new_plane_state->uapi.dst.y2;
> - clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
> - &crtc_state->pipe_src);
> + clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> + &new_crtc_state->pipe_src);
> }
> continue;
> } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) {
> /* If alpha changed mark the whole plane area as damaged */
> damaged_area.y1 = new_plane_state->uapi.dst.y1;
> damaged_area.y2 = new_plane_state->uapi.dst.y2;
> - clip_area_update(&crtc_state->psr2_su_area, &damaged_area,
> - &crtc_state->pipe_src);
> + clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> + &new_crtc_state->pipe_src);
> continue;
> }
>
> @@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1;
> damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
>
> - clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
> + clip_area_update(&new_crtc_state->psr2_su_area, &damaged_area,
> + &new_crtc_state->pipe_src);
> }
>
> /*
> @@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> * should identify cases where this happens and fix the area
> * calculation for those.
> */
> - if (crtc_state->psr2_su_area.y1 == -1) {
> + if (new_crtc_state->psr2_su_area.y1 == -1) {
> drm_info_once(display->drm,
> "Selective fetch area calculation failed in pipe %c\n",
> pipe_name(crtc->pipe));
> @@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> if (full_update)
> goto skip_sel_fetch_set_loop;
>
> - intel_psr_apply_su_area_workarounds(crtc_state);
> + intel_psr_apply_su_area_workarounds(new_crtc_state);
>
> ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
> if (ret)
> @@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> */
> intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
>
> - intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> + intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
>
> /*
> * Now that we have the pipe damaged area check if it intersect with
> @@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> struct drm_rect *sel_fetch_area, inter;
> struct intel_plane *linked = new_plane_state->planar_linked_plane;
>
> - if (new_plane_state->hw.crtc != crtc_state->uapi.crtc ||
> + if (new_plane_state->hw.crtc != new_crtc_state->uapi.crtc ||
> !new_plane_state->uapi.visible)
> continue;
>
> - inter = crtc_state->psr2_su_area;
> + inter = new_crtc_state->psr2_su_area;
> sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
> if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) {
> sel_fetch_area->y1 = -1;
> @@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> * disable it
> */
> if (drm_rect_height(&old_plane_state->psr2_sel_fetch_area) > 0)
> - crtc_state->update_planes |= BIT(plane->id);
> + new_crtc_state->update_planes |= BIT(plane->id);
>
> continue;
> }
>
> - if (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> + if (!psr2_sel_fetch_plane_state_supported(old_crtc_state, new_plane_state)) {
> full_update = true;
> break;
> }
> @@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> sel_fetch_area = &new_plane_state->psr2_sel_fetch_area;
> sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1;
> sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1;
> - crtc_state->update_planes |= BIT(plane->id);
> + new_crtc_state->update_planes |= BIT(plane->id);
>
> /*
> * Sel_fetch_area is calculated for UV plane. Use
> @@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area;
> linked_sel_fetch_area->y1 = sel_fetch_area->y1;
> linked_sel_fetch_area->y2 = sel_fetch_area->y2;
> - crtc_state->update_planes |= BIT(linked->id);
> + new_crtc_state->update_planes |= BIT(linked->id);
> }
> }
>
> skip_sel_fetch_set_loop:
> - psr2_man_trk_ctl_calc(crtc_state, full_update);
> - crtc_state->pipe_srcsz_early_tpt =
> - psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
> + psr2_man_trk_ctl_calc(new_crtc_state, full_update);
> + new_crtc_state->pipe_srcsz_early_tpt =
> + psr2_pipe_srcsz_early_tpt_calc(new_crtc_state, full_update);
> return 0;
> }
>
> --
> 2.43.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-03 13:22 ` Ville Syrjälä
@ 2025-12-03 13:58 ` Hogander, Jouni
2025-12-03 15:08 ` Ville Syrjälä
2025-12-04 7:10 ` Hogander, Jouni
1 sibling, 1 reply; 18+ messages in thread
From: Hogander, Jouni @ 2025-12-03 13:58 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > According to bspec selective fetch is not supported with async
> > flips and
> > instructing full frame update on async flip.
> >
> > v3:
> > - rebase
> > - fix old_crtc_state->pipe_srcsz_early_tpt
> > - fix using intel_atomic_get_new_crtc_state
> > v2:
> > - check also crtc_state->async_flip_planes in
> > psr2_sel_fetch_plane_state_supported
> >
> > Bspec: 55229
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++------
> > ----
> > 1 file changed, 41 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 15ef3b6caad6..53cf292247d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct
> > intel_atomic_state *state,
> > * Plane scaling and rotation is not supported by selective fetch
> > and both
> > * properties can change without a modeset, so need to be check at
> > every
> > * atomic commit.
> > + *
> > + * If plane was having async flip previously we can't use
> > selective
> > + * fetch as we don't know if the flip is completed.
> > */
> > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_plane_state *plane_state)
> > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_crtc_state *old_crtc_state,
> > + const struct
> > intel_plane_state *plane_state)
> > {
> > + struct intel_plane *plane = to_intel_plane(plane_state-
> > >uapi.plane);
> > +
> > if (plane_state->uapi.dst.y1 < 0 ||
> > plane_state->uapi.dst.x1 < 0 ||
> > plane_state->scaler_id >= 0 ||
> > - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > + plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > + old_crtc_state->async_flip_planes & plane->id)
>
> Why are you looking at the old crtc state? There should be nothing of
> interest to us there.
To continue keeping CFF bit set if previous update was async flip. This
is how I understood it (please correct):
0. syncronous update
1. async_flip:
new_crtc_state->async_flip_planes != 0
old_crtc_state->async_flip_planes == 0
crtc_state->uapi.async_flip == true)
-> full frame update
2. async_flip:
new_crtc_state->async_flip_planes != 0
old_crtc_state->async_flip_planes != 0
crtc_state->uapi.async_flip == true
-> full frame update
3. syncronous update
new_crtc_state->async_flip_planes == 0
old_crtc_state->async_flip_planes != 0
crtc_state->uapi.async_flip == false
-> full frame update
4. syncronous update
new_crtc_state->async_flip_planes == 0
old_crtc_state->async_flip_planes == 0
crtc_state->uapi.async_flip == false
-> selective update
>
> > return false;
> >
> > return true;
> > @@ -2749,7 +2756,8 @@ static bool
> > psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> > */
> > static bool psr2_sel_fetch_pipe_state_supported(const struct
> > intel_crtc_state *crtc_state)
> > {
> > - if (crtc_state->scaler_state.scaler_id >= 0)
> > + if (crtc_state->scaler_state.scaler_id >= 0 ||
> > + crtc_state->uapi.async_flip)
>
> I think just checking crtc_state->async_flip_planes!=0 here should be
> sufficient.
I'm doing this to handle step 1. above. Alternatively I could check
both new_crtc_state->async_flip_planes and old_crtc_state-
>async_flip_planes. When using crtc_state->uapi.async_flip I can decide
earlier.
> The rest of the patch seems unnecessary.
No need to handle selective update where planes having pending async
flip are not involved?
BR,
Jouni Högander
>
> On a related note, someone should add a new igt that does async flips
> while eg. the cursor is enabled and overlapping the plane doing the
> async flips. That's basically how I noticed the problem in the first
> place (with Xorg), so would be good to have an igt to make sure we
> don't break this in the future.
>
> > return false;
> >
> > return true;
> > @@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > struct intel_display *display = to_intel_display(state);
> > - struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_crtc_state *old_crtc_state =
> > intel_atomic_get_old_crtc_state(state, crtc);
> > struct intel_plane_state *new_plane_state,
> > *old_plane_state;
> > struct intel_plane *plane;
> > bool full_update = false, cursor_in_su_area = false;
> > int i, ret;
> >
> > - if (!crtc_state->enable_psr2_sel_fetch)
> > + if (!new_crtc_state->enable_psr2_sel_fetch)
> > return 0;
> >
> > - if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> > + if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state))
> > {
> > full_update = true;
> > goto skip_sel_fetch_set_loop;
> > }
> >
> > - crtc_state->psr2_su_area.x1 = 0;
> > - crtc_state->psr2_su_area.y1 = -1;
> > - crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state-
> > >pipe_src);
> > - crtc_state->psr2_su_area.y2 = -1;
> > + new_crtc_state->psr2_su_area.x1 = 0;
> > + new_crtc_state->psr2_su_area.y1 = -1;
> > + new_crtc_state->psr2_su_area.x2 =
> > drm_rect_width(&new_crtc_state->pipe_src);
> > + new_crtc_state->psr2_su_area.y2 = -1;
> >
> > /*
> > * Calculate minimal selective fetch area of each plane
> > and calculate
> > @@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > struct drm_rect src, damaged_area = { .x1 = 0, .y1
> > = -1,
> > .x2 =
> > INT_MAX };
> >
> > - if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc)
> > + if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc)
> > continue;
> >
> > if (!new_plane_state->uapi.visible &&
> > !old_plane_state->uapi.visible)
> > continue;
> >
> > - if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > + if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> > full_update = true;
> > break;
> > }
> > @@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > if (old_plane_state->uapi.visible) {
> > damaged_area.y1 = old_plane_state-
> > >uapi.dst.y1;
> > damaged_area.y2 = old_plane_state-
> > >uapi.dst.y2;
> > - clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > - &crtc_state-
> > >pipe_src);
> > + clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > + &new_crtc_state-
> > >pipe_src);
> > }
> >
> > if (new_plane_state->uapi.visible) {
> > damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> > damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > - clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > - &crtc_state-
> > >pipe_src);
> > + clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > + &new_crtc_state-
> > >pipe_src);
> > }
> > continue;
> > } else if (new_plane_state->uapi.alpha !=
> > old_plane_state->uapi.alpha) {
> > /* If alpha changed mark the whole plane
> > area as damaged */
> > damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> > damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > - clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > - &crtc_state->pipe_src);
> > + clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > + &new_crtc_state-
> > >pipe_src);
> > continue;
> > }
> >
> > @@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > damaged_area.x1 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> > damaged_area.x2 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> >
> > - clip_area_update(&crtc_state->psr2_su_area,
> > &damaged_area, &crtc_state->pipe_src);
> > + clip_area_update(&new_crtc_state->psr2_su_area,
> > &damaged_area,
> > + &new_crtc_state->pipe_src);
> > }
> >
> > /*
> > @@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > * should identify cases where this happens and fix the
> > area
> > * calculation for those.
> > */
> > - if (crtc_state->psr2_su_area.y1 == -1) {
> > + if (new_crtc_state->psr2_su_area.y1 == -1) {
> > drm_info_once(display->drm,
> > "Selective fetch area calculation
> > failed in pipe %c\n",
> > pipe_name(crtc->pipe));
> > @@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > if (full_update)
> > goto skip_sel_fetch_set_loop;
> >
> > - intel_psr_apply_su_area_workarounds(crtc_state);
> > + intel_psr_apply_su_area_workarounds(new_crtc_state);
> >
> > ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > >base);
> > if (ret)
> > @@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > */
> > intel_psr2_sel_fetch_et_alignment(state, crtc,
> > &cursor_in_su_area);
> >
> > - intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> > + intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
> >
> > /*
> > * Now that we have the pipe damaged area check if it
> > intersect with
> > @@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > struct drm_rect *sel_fetch_area, inter;
> > struct intel_plane *linked = new_plane_state-
> > >planar_linked_plane;
> >
> > - if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc ||
> > + if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc ||
> > !new_plane_state->uapi.visible)
> > continue;
> >
> > - inter = crtc_state->psr2_su_area;
> > + inter = new_crtc_state->psr2_su_area;
> > sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> > if (!drm_rect_intersect(&inter, &new_plane_state-
> > >uapi.dst)) {
> > sel_fetch_area->y1 = -1;
> > @@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > * disable it
> > */
> > if (drm_rect_height(&old_plane_state-
> > >psr2_sel_fetch_area) > 0)
> > - crtc_state->update_planes |=
> > BIT(plane->id);
> > + new_crtc_state->update_planes |=
> > BIT(plane->id);
> >
> > continue;
> > }
> >
> > - if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > + if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> > full_update = true;
> > break;
> > }
> > @@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> > sel_fetch_area->y1 = inter.y1 - new_plane_state-
> > >uapi.dst.y1;
> > sel_fetch_area->y2 = inter.y2 - new_plane_state-
> > >uapi.dst.y1;
> > - crtc_state->update_planes |= BIT(plane->id);
> > + new_crtc_state->update_planes |= BIT(plane->id);
> >
> > /*
> > * Sel_fetch_area is calculated for UV plane. Use
> > @@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > linked_sel_fetch_area =
> > &linked_new_plane_state->psr2_sel_fetch_area;
> > linked_sel_fetch_area->y1 =
> > sel_fetch_area->y1;
> > linked_sel_fetch_area->y2 =
> > sel_fetch_area->y2;
> > - crtc_state->update_planes |= BIT(linked-
> > >id);
> > + new_crtc_state->update_planes |=
> > BIT(linked->id);
> > }
> > }
> >
> > skip_sel_fetch_set_loop:
> > - psr2_man_trk_ctl_calc(crtc_state, full_update);
> > - crtc_state->pipe_srcsz_early_tpt =
> > - psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);
> > + psr2_man_trk_ctl_calc(new_crtc_state, full_update);
> > + new_crtc_state->pipe_srcsz_early_tpt =
> > + psr2_pipe_srcsz_early_tpt_calc(new_crtc_state,
> > full_update);
> > return 0;
> > }
> >
> > --
> > 2.43.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-03 13:58 ` Hogander, Jouni
@ 2025-12-03 15:08 ` Ville Syrjälä
2025-12-03 15:13 ` Hogander, Jouni
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2025-12-03 15:08 UTC (permalink / raw)
To: Hogander, Jouni
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > > According to bspec selective fetch is not supported with async
> > > flips and
> > > instructing full frame update on async flip.
> > >
> > > v3:
> > > - rebase
> > > - fix old_crtc_state->pipe_srcsz_early_tpt
> > > - fix using intel_atomic_get_new_crtc_state
> > > v2:
> > > - check also crtc_state->async_flip_planes in
> > > psr2_sel_fetch_plane_state_supported
> > >
> > > Bspec: 55229
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++------
> > > ----
> > > 1 file changed, 41 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 15ef3b6caad6..53cf292247d7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct
> > > intel_atomic_state *state,
> > > * Plane scaling and rotation is not supported by selective fetch
> > > and both
> > > * properties can change without a modeset, so need to be check at
> > > every
> > > * atomic commit.
> > > + *
> > > + * If plane was having async flip previously we can't use
> > > selective
> > > + * fetch as we don't know if the flip is completed.
> > > */
> > > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > > intel_plane_state *plane_state)
> > > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > > intel_crtc_state *old_crtc_state,
> > > + const struct
> > > intel_plane_state *plane_state)
> > > {
> > > + struct intel_plane *plane = to_intel_plane(plane_state-
> > > >uapi.plane);
> > > +
> > > if (plane_state->uapi.dst.y1 < 0 ||
> > > plane_state->uapi.dst.x1 < 0 ||
> > > plane_state->scaler_id >= 0 ||
> > > - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > + plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > > + old_crtc_state->async_flip_planes & plane->id)
> >
> > Why are you looking at the old crtc state? There should be nothing of
> > interest to us there.
>
> To continue keeping CFF bit set if previous update was async flip. This
> is how I understood it (please correct):
>
> 0. syncronous update
>
> 1. async_flip:
> new_crtc_state->async_flip_planes != 0
> old_crtc_state->async_flip_planes == 0
> crtc_state->uapi.async_flip == true)
> -> full frame update
>
> 2. async_flip:
> new_crtc_state->async_flip_planes != 0
> old_crtc_state->async_flip_planes != 0
> crtc_state->uapi.async_flip == true
> -> full frame update
>
> 3. syncronous update
> new_crtc_state->async_flip_planes == 0
> old_crtc_state->async_flip_planes != 0
> crtc_state->uapi.async_flip == false
> -> full frame update
>
> 4. syncronous update
> new_crtc_state->async_flip_planes == 0
> old_crtc_state->async_flip_planes == 0
> crtc_state->uapi.async_flip == false
> -> selective update
>
> >
> > > return false;
> > >
> > > return true;
> > > @@ -2749,7 +2756,8 @@ static bool
> > > psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> > > */
> > > static bool psr2_sel_fetch_pipe_state_supported(const struct
> > > intel_crtc_state *crtc_state)
> > > {
> > > - if (crtc_state->scaler_state.scaler_id >= 0)
> > > + if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > + crtc_state->uapi.async_flip)
> >
> > I think just checking crtc_state->async_flip_planes!=0 here should be
> > sufficient.
>
> I'm doing this to handle step 1. above. Alternatively I could check
> both new_crtc_state->async_flip_planes and old_crtc_state-
> >async_flip_planes. When using crtc_state->uapi.async_flip I can decide
> earlier.
>
> > The rest of the patch seems unnecessary.
>
> No need to handle selective update where planes having pending async
> flip are not involved?
There won't be pending flips of any kind. We whole CRTC commit queue
is handled in a strict FIFO order (apart from the legacy cursor
special case).
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-03 15:08 ` Ville Syrjälä
@ 2025-12-03 15:13 ` Hogander, Jouni
2025-12-03 15:55 ` Ville Syrjälä
0 siblings, 1 reply; 18+ messages in thread
From: Hogander, Jouni @ 2025-12-03 15:13 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 17:08 +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> > On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > > > According to bspec selective fetch is not supported with async
> > > > flips and
> > > > instructing full frame update on async flip.
> > > >
> > > > v3:
> > > > - rebase
> > > > - fix old_crtc_state->pipe_srcsz_early_tpt
> > > > - fix using intel_atomic_get_new_crtc_state
> > > > v2:
> > > > - check also crtc_state->async_flip_planes in
> > > > psr2_sel_fetch_plane_state_supported
> > > >
> > > > Bspec: 55229
> > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++--
> > > > ----
> > > > ----
> > > > 1 file changed, 41 insertions(+), 31 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 15ef3b6caad6..53cf292247d7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -2728,13 +2728,20 @@
> > > > intel_psr2_sel_fetch_et_alignment(struct
> > > > intel_atomic_state *state,
> > > > * Plane scaling and rotation is not supported by selective
> > > > fetch
> > > > and both
> > > > * properties can change without a modeset, so need to be
> > > > check at
> > > > every
> > > > * atomic commit.
> > > > + *
> > > > + * If plane was having async flip previously we can't use
> > > > selective
> > > > + * fetch as we don't know if the flip is completed.
> > > > */
> > > > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > intel_plane_state *plane_state)
> > > > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > intel_crtc_state *old_crtc_state,
> > > > + const struct
> > > > intel_plane_state *plane_state)
> > > > {
> > > > + struct intel_plane *plane =
> > > > to_intel_plane(plane_state-
> > > > > uapi.plane);
> > > > +
> > > > if (plane_state->uapi.dst.y1 < 0 ||
> > > > plane_state->uapi.dst.x1 < 0 ||
> > > > plane_state->scaler_id >= 0 ||
> > > > - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > > + plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > > > + old_crtc_state->async_flip_planes & plane->id)
> > >
> > > Why are you looking at the old crtc state? There should be
> > > nothing of
> > > interest to us there.
> >
> > To continue keeping CFF bit set if previous update was async flip.
> > This
> > is how I understood it (please correct):
> >
> > 0. syncronous update
> >
> > 1. async_flip:
> > new_crtc_state->async_flip_planes != 0
> > old_crtc_state->async_flip_planes == 0
> > crtc_state->uapi.async_flip == true)
> > -> full frame update
> >
> > 2. async_flip:
> > new_crtc_state->async_flip_planes != 0
> > old_crtc_state->async_flip_planes != 0
> > crtc_state->uapi.async_flip == true
> > -> full frame update
> >
> > 3. syncronous update
> > new_crtc_state->async_flip_planes == 0
> > old_crtc_state->async_flip_planes != 0
> > crtc_state->uapi.async_flip == false
> > -> full frame update
> >
> > 4. syncronous update
> > new_crtc_state->async_flip_planes == 0
> > old_crtc_state->async_flip_planes == 0
> > crtc_state->uapi.async_flip == false
> > -> selective update
> >
> > >
> > > > return false;
> > > >
> > > > return true;
> > > > @@ -2749,7 +2756,8 @@ static bool
> > > > psr2_sel_fetch_plane_state_supported(const struct
> > > > intel_plane_state
> > > > */
> > > > static bool psr2_sel_fetch_pipe_state_supported(const struct
> > > > intel_crtc_state *crtc_state)
> > > > {
> > > > - if (crtc_state->scaler_state.scaler_id >= 0)
> > > > + if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > > + crtc_state->uapi.async_flip)
> > >
> > > I think just checking crtc_state->async_flip_planes!=0 here
> > > should be
> > > sufficient.
> >
> > I'm doing this to handle step 1. above. Alternatively I could check
> > both new_crtc_state->async_flip_planes and old_crtc_state-
> > > async_flip_planes. When using crtc_state->uapi.async_flip I can
> > > decide
> > earlier.
> >
> > > The rest of the patch seems unnecessary.
> >
> > No need to handle selective update where planes having pending
> > async
> > flip are not involved?
>
> There won't be pending flips of any kind. We whole CRTC commit queue
> is handled in a strict FIFO order (apart from the legacy cursor
> special case).
>
Ok, so it's not possible to take in new CRTC commit before async flip
is completed?
BR,
Jouni Högander
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-03 15:13 ` Hogander, Jouni
@ 2025-12-03 15:55 ` Ville Syrjälä
2025-12-04 5:49 ` Hogander, Jouni
0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2025-12-03 15:55 UTC (permalink / raw)
To: Hogander, Jouni
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, Dec 03, 2025 at 03:13:11PM +0000, Hogander, Jouni wrote:
> On Wed, 2025-12-03 at 17:08 +0200, Ville Syrjälä wrote:
> > On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> > > On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > > > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > > > > According to bspec selective fetch is not supported with async
> > > > > flips and
> > > > > instructing full frame update on async flip.
> > > > >
> > > > > v3:
> > > > > - rebase
> > > > > - fix old_crtc_state->pipe_srcsz_early_tpt
> > > > > - fix using intel_atomic_get_new_crtc_state
> > > > > v2:
> > > > > - check also crtc_state->async_flip_planes in
> > > > > psr2_sel_fetch_plane_state_supported
> > > > >
> > > > > Bspec: 55229
> > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++--
> > > > > ----
> > > > > ----
> > > > > 1 file changed, 41 insertions(+), 31 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 15ef3b6caad6..53cf292247d7 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -2728,13 +2728,20 @@
> > > > > intel_psr2_sel_fetch_et_alignment(struct
> > > > > intel_atomic_state *state,
> > > > > * Plane scaling and rotation is not supported by selective
> > > > > fetch
> > > > > and both
> > > > > * properties can change without a modeset, so need to be
> > > > > check at
> > > > > every
> > > > > * atomic commit.
> > > > > + *
> > > > > + * If plane was having async flip previously we can't use
> > > > > selective
> > > > > + * fetch as we don't know if the flip is completed.
> > > > > */
> > > > > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > > intel_plane_state *plane_state)
> > > > > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > > > > intel_crtc_state *old_crtc_state,
> > > > > + const struct
> > > > > intel_plane_state *plane_state)
> > > > > {
> > > > > + struct intel_plane *plane =
> > > > > to_intel_plane(plane_state-
> > > > > > uapi.plane);
> > > > > +
> > > > > if (plane_state->uapi.dst.y1 < 0 ||
> > > > > plane_state->uapi.dst.x1 < 0 ||
> > > > > plane_state->scaler_id >= 0 ||
> > > > > - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > > > + plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > > > > + old_crtc_state->async_flip_planes & plane->id)
> > > >
> > > > Why are you looking at the old crtc state? There should be
> > > > nothing of
> > > > interest to us there.
> > >
> > > To continue keeping CFF bit set if previous update was async flip.
> > > This
> > > is how I understood it (please correct):
> > >
> > > 0. syncronous update
> > >
> > > 1. async_flip:
> > > new_crtc_state->async_flip_planes != 0
> > > old_crtc_state->async_flip_planes == 0
> > > crtc_state->uapi.async_flip == true)
> > > -> full frame update
> > >
> > > 2. async_flip:
> > > new_crtc_state->async_flip_planes != 0
> > > old_crtc_state->async_flip_planes != 0
> > > crtc_state->uapi.async_flip == true
> > > -> full frame update
> > >
> > > 3. syncronous update
> > > new_crtc_state->async_flip_planes == 0
> > > old_crtc_state->async_flip_planes != 0
> > > crtc_state->uapi.async_flip == false
> > > -> full frame update
> > >
> > > 4. syncronous update
> > > new_crtc_state->async_flip_planes == 0
> > > old_crtc_state->async_flip_planes == 0
> > > crtc_state->uapi.async_flip == false
> > > -> selective update
> > >
> > > >
> > > > > return false;
> > > > >
> > > > > return true;
> > > > > @@ -2749,7 +2756,8 @@ static bool
> > > > > psr2_sel_fetch_plane_state_supported(const struct
> > > > > intel_plane_state
> > > > > */
> > > > > static bool psr2_sel_fetch_pipe_state_supported(const struct
> > > > > intel_crtc_state *crtc_state)
> > > > > {
> > > > > - if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > + if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > > > + crtc_state->uapi.async_flip)
> > > >
> > > > I think just checking crtc_state->async_flip_planes!=0 here
> > > > should be
> > > > sufficient.
> > >
> > > I'm doing this to handle step 1. above. Alternatively I could check
> > > both new_crtc_state->async_flip_planes and old_crtc_state-
> > > > async_flip_planes. When using crtc_state->uapi.async_flip I can
> > > > decide
> > > earlier.
> > >
> > > > The rest of the patch seems unnecessary.
> > >
> > > No need to handle selective update where planes having pending
> > > async
> > > flip are not involved?
> >
> > There won't be pending flips of any kind. We whole CRTC commit queue
> > is handled in a strict FIFO order (apart from the legacy cursor
> > special case).
> >
>
> Ok, so it's not possible to take in new CRTC commit before async flip
> is completed?
More or less. The new request can come in before that, but it won't
be commited to the hardware until the previous one has finished.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-03 15:55 ` Ville Syrjälä
@ 2025-12-04 5:49 ` Hogander, Jouni
0 siblings, 0 replies; 18+ messages in thread
From: Hogander, Jouni @ 2025-12-04 5:49 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 17:55 +0200, Ville Syrjälä wrote:
> On Wed, Dec 03, 2025 at 03:13:11PM +0000, Hogander, Jouni wrote:
> > On Wed, 2025-12-03 at 17:08 +0200, Ville Syrjälä wrote:
> > > On Wed, Dec 03, 2025 at 01:58:23PM +0000, Hogander, Jouni wrote:
> > > > On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> > > > > On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander
> > > > > wrote:
> > > > > > According to bspec selective fetch is not supported with
> > > > > > async
> > > > > > flips and
> > > > > > instructing full frame update on async flip.
> > > > > >
> > > > > > v3:
> > > > > > - rebase
> > > > > > - fix old_crtc_state->pipe_srcsz_early_tpt
> > > > > > - fix using intel_atomic_get_new_crtc_state
> > > > > > v2:
> > > > > > - check also crtc_state->async_flip_planes in
> > > > > > psr2_sel_fetch_plane_state_supported
> > > > > >
> > > > > > Bspec: 55229
> > > > > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_psr.c | 72
> > > > > > ++++++++++++++--
> > > > > > ----
> > > > > > ----
> > > > > > 1 file changed, 41 insertions(+), 31 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 15ef3b6caad6..53cf292247d7 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -2728,13 +2728,20 @@
> > > > > > intel_psr2_sel_fetch_et_alignment(struct
> > > > > > intel_atomic_state *state,
> > > > > > * Plane scaling and rotation is not supported by
> > > > > > selective
> > > > > > fetch
> > > > > > and both
> > > > > > * properties can change without a modeset, so need to be
> > > > > > check at
> > > > > > every
> > > > > > * atomic commit.
> > > > > > + *
> > > > > > + * If plane was having async flip previously we can't use
> > > > > > selective
> > > > > > + * fetch as we don't know if the flip is completed.
> > > > > > */
> > > > > > -static bool psr2_sel_fetch_plane_state_supported(const
> > > > > > struct
> > > > > > intel_plane_state *plane_state)
> > > > > > +static bool psr2_sel_fetch_plane_state_supported(const
> > > > > > struct
> > > > > > intel_crtc_state *old_crtc_state,
> > > > > > + const
> > > > > > struct
> > > > > > intel_plane_state *plane_state)
> > > > > > {
> > > > > > + struct intel_plane *plane =
> > > > > > to_intel_plane(plane_state-
> > > > > > > uapi.plane);
> > > > > > +
> > > > > > if (plane_state->uapi.dst.y1 < 0 ||
> > > > > > plane_state->uapi.dst.x1 < 0 ||
> > > > > > plane_state->scaler_id >= 0 ||
> > > > > > - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > > > > > + plane_state->hw.rotation != DRM_MODE_ROTATE_0
> > > > > > ||
> > > > > > + old_crtc_state->async_flip_planes & plane->id)
> > > > >
> > > > > Why are you looking at the old crtc state? There should be
> > > > > nothing of
> > > > > interest to us there.
> > > >
> > > > To continue keeping CFF bit set if previous update was async
> > > > flip.
> > > > This
> > > > is how I understood it (please correct):
> > > >
> > > > 0. syncronous update
> > > >
> > > > 1. async_flip:
> > > > new_crtc_state->async_flip_planes != 0
> > > > old_crtc_state->async_flip_planes == 0
> > > > crtc_state->uapi.async_flip == true)
> > > > -> full frame update
> > > >
> > > > 2. async_flip:
> > > > new_crtc_state->async_flip_planes != 0
> > > > old_crtc_state->async_flip_planes != 0
> > > > crtc_state->uapi.async_flip == true
> > > > -> full frame update
> > > >
> > > > 3. syncronous update
> > > > new_crtc_state->async_flip_planes == 0
> > > > old_crtc_state->async_flip_planes != 0
> > > > crtc_state->uapi.async_flip == false
> > > > -> full frame update
> > > >
> > > > 4. syncronous update
> > > > new_crtc_state->async_flip_planes == 0
> > > > old_crtc_state->async_flip_planes == 0
> > > > crtc_state->uapi.async_flip == false
> > > > -> selective update
> > > >
> > > > >
> > > > > > return false;
> > > > > >
> > > > > > return true;
> > > > > > @@ -2749,7 +2756,8 @@ static bool
> > > > > > psr2_sel_fetch_plane_state_supported(const struct
> > > > > > intel_plane_state
> > > > > > */
> > > > > > static bool psr2_sel_fetch_pipe_state_supported(const
> > > > > > struct
> > > > > > intel_crtc_state *crtc_state)
> > > > > > {
> > > > > > - if (crtc_state->scaler_state.scaler_id >= 0)
> > > > > > + if (crtc_state->scaler_state.scaler_id >= 0 ||
> > > > > > + crtc_state->uapi.async_flip)
> > > > >
> > > > > I think just checking crtc_state->async_flip_planes!=0 here
> > > > > should be
> > > > > sufficient.
> > > >
> > > > I'm doing this to handle step 1. above. Alternatively I could
> > > > check
> > > > both new_crtc_state->async_flip_planes and old_crtc_state-
> > > > > async_flip_planes. When using crtc_state->uapi.async_flip I
> > > > > can
> > > > > decide
> > > > earlier.
> > > >
> > > > > The rest of the patch seems unnecessary.
> > > >
> > > > No need to handle selective update where planes having pending
> > > > async
> > > > flip are not involved?
> > >
> > > There won't be pending flips of any kind. We whole CRTC commit
> > > queue
> > > is handled in a strict FIFO order (apart from the legacy cursor
> > > special case).
> > >
> >
> > Ok, so it's not possible to take in new CRTC commit before async
> > flip
> > is completed?
>
> More or less. The new request can come in before that, but it won't
> be commited to the hardware until the previous one has finished.
>
Ok, I misunderstood your original comment. I got impression it's
different for async flip.
BR,
Jouni Högander
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR
2025-12-03 13:15 ` Ville Syrjälä
@ 2025-12-04 7:09 ` Hogander, Jouni
2025-12-16 8:38 ` Hogander, Jouni
1 sibling, 0 replies; 18+ messages in thread
From: Hogander, Jouni @ 2025-12-04 7:09 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 15:15 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:55PM +0200, Jouni Högander wrote:
> > Currently plane id bit is set in crtc_state->async_flip_planes only
> > when
> > async flip toggle workaround is needed. We want to utilize
> > crtc_state->async_flip_planes further in Selective Fetch
> > calculation.
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> > b/drivers/gpu/drm/i915/display/intel_plane.c
> > index 7b7619d59251..de0a69c55582 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> > @@ -603,8 +603,7 @@ static int
> > intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_cr
> > if (intel_plane_do_async_flip(plane, old_crtc_state,
> > new_crtc_state)) {
> > new_crtc_state->do_async_flip = true;
> > new_crtc_state->async_flip_planes |= BIT(plane-
> > >id);
> > - } else if (plane->need_async_flip_toggle_wa &&
> > - new_crtc_state->uapi.async_flip) {
> > + } else if (new_crtc_state->uapi.async_flip) {
>
> I'd get rid of the if-else construct here now, and just do something
> like:
>
> if (intel_plane_do_async_flip(...))
> new_crtc_state->do_async_flip = true;
>
> if (new_crtc_state->uapi.async_flip) {
> /* ... */
> new_crtc_state->async_flip_planes |= BIT(plane->id);
> }
>
> We should probably also move the plane->async_flip check
> out from intel_plane_do_async_flip() and just make it a
> drm_WARN_ON(..., uapi.async_flip && !plane->async_flip).
> But that's probably better left for a separate patch.
Sent new version, please check. Left out this drm_WARN_ON change. I
will send it afterwards.
BR,
Jouni Högander
>
> > /*
> > * On platforms with double buffered async flip
> > bit we
> > * set the bit already one frame early during the
> > sync
> > @@ -612,6 +611,13 @@ static int
> > intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_cr
> > * hardware will therefore be ready to perform a
> > real
> > * async flip during the next commit, without
> > having
> > * to wait yet another frame for the bit to latch.
> > + *
> > + * async_flip_planes bitmask is also used by
> > selective
> > + * fetch calculation to continue full frame
> > updates as
> > + * long as there may be pending async flip on any
> > + * plane which is part of selective
> > + * update. I.e. old_crtc_state->async_flip_planes
> > &
> > + * BIT(<plane in su area>->id).
> > */
> > new_crtc_state->async_flip_planes |= BIT(plane-
> > >id);
> > }
> > --
> > 2.43.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip
2025-12-03 13:22 ` Ville Syrjälä
2025-12-03 13:58 ` Hogander, Jouni
@ 2025-12-04 7:10 ` Hogander, Jouni
1 sibling, 0 replies; 18+ messages in thread
From: Hogander, Jouni @ 2025-12-04 7:10 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 15:22 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:56PM +0200, Jouni Högander wrote:
> > According to bspec selective fetch is not supported with async
> > flips and
> > instructing full frame update on async flip.
> >
> > v3:
> > - rebase
> > - fix old_crtc_state->pipe_srcsz_early_tpt
> > - fix using intel_atomic_get_new_crtc_state
> > v2:
> > - check also crtc_state->async_flip_planes in
> > psr2_sel_fetch_plane_state_supported
> >
> > Bspec: 55229
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 72 ++++++++++++++------
> > ----
> > 1 file changed, 41 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 15ef3b6caad6..53cf292247d7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2728,13 +2728,20 @@ intel_psr2_sel_fetch_et_alignment(struct
> > intel_atomic_state *state,
> > * Plane scaling and rotation is not supported by selective fetch
> > and both
> > * properties can change without a modeset, so need to be check at
> > every
> > * atomic commit.
> > + *
> > + * If plane was having async flip previously we can't use
> > selective
> > + * fetch as we don't know if the flip is completed.
> > */
> > -static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_plane_state *plane_state)
> > +static bool psr2_sel_fetch_plane_state_supported(const struct
> > intel_crtc_state *old_crtc_state,
> > + const struct
> > intel_plane_state *plane_state)
> > {
> > + struct intel_plane *plane = to_intel_plane(plane_state-
> > >uapi.plane);
> > +
> > if (plane_state->uapi.dst.y1 < 0 ||
> > plane_state->uapi.dst.x1 < 0 ||
> > plane_state->scaler_id >= 0 ||
> > - plane_state->hw.rotation != DRM_MODE_ROTATE_0)
> > + plane_state->hw.rotation != DRM_MODE_ROTATE_0 ||
> > + old_crtc_state->async_flip_planes & plane->id)
>
> Why are you looking at the old crtc state? There should be nothing of
> interest to us there.
>
> > return false;
> >
> > return true;
> > @@ -2749,7 +2756,8 @@ static bool
> > psr2_sel_fetch_plane_state_supported(const struct intel_plane_state
> > */
> > static bool psr2_sel_fetch_pipe_state_supported(const struct
> > intel_crtc_state *crtc_state)
> > {
> > - if (crtc_state->scaler_state.scaler_id >= 0)
> > + if (crtc_state->scaler_state.scaler_id >= 0 ||
> > + crtc_state->uapi.async_flip)
>
> I think just checking crtc_state->async_flip_planes!=0 here should be
> sufficient. The rest of the patch seems unnecessary.
>
> On a related note, someone should add a new igt that does async flips
> while eg. the cursor is enabled and overlapping the plane doing the
> async flips. That's basically how I noticed the problem in the first
> place (with Xorg), so would be good to have an igt to make sure we
> don't break this in the future.
I will add ticket for this.
BR,
Jouni Högander
>
> > return false;
> >
> > return true;
> > @@ -2808,24 +2816,25 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > struct intel_display *display = to_intel_display(state);
> > - struct intel_crtc_state *crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > + struct intel_crtc_state *old_crtc_state =
> > intel_atomic_get_old_crtc_state(state, crtc);
> > struct intel_plane_state *new_plane_state,
> > *old_plane_state;
> > struct intel_plane *plane;
> > bool full_update = false, cursor_in_su_area = false;
> > int i, ret;
> >
> > - if (!crtc_state->enable_psr2_sel_fetch)
> > + if (!new_crtc_state->enable_psr2_sel_fetch)
> > return 0;
> >
> > - if (!psr2_sel_fetch_pipe_state_supported(crtc_state)) {
> > + if (!psr2_sel_fetch_pipe_state_supported(new_crtc_state))
> > {
> > full_update = true;
> > goto skip_sel_fetch_set_loop;
> > }
> >
> > - crtc_state->psr2_su_area.x1 = 0;
> > - crtc_state->psr2_su_area.y1 = -1;
> > - crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state-
> > >pipe_src);
> > - crtc_state->psr2_su_area.y2 = -1;
> > + new_crtc_state->psr2_su_area.x1 = 0;
> > + new_crtc_state->psr2_su_area.y1 = -1;
> > + new_crtc_state->psr2_su_area.x2 =
> > drm_rect_width(&new_crtc_state->pipe_src);
> > + new_crtc_state->psr2_su_area.y2 = -1;
> >
> > /*
> > * Calculate minimal selective fetch area of each plane
> > and calculate
> > @@ -2838,14 +2847,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > struct drm_rect src, damaged_area = { .x1 = 0, .y1
> > = -1,
> > .x2 =
> > INT_MAX };
> >
> > - if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc)
> > + if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc)
> > continue;
> >
> > if (!new_plane_state->uapi.visible &&
> > !old_plane_state->uapi.visible)
> > continue;
> >
> > - if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > + if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> > full_update = true;
> > break;
> > }
> > @@ -2861,23 +2870,23 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > if (old_plane_state->uapi.visible) {
> > damaged_area.y1 = old_plane_state-
> > >uapi.dst.y1;
> > damaged_area.y2 = old_plane_state-
> > >uapi.dst.y2;
> > - clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > - &crtc_state-
> > >pipe_src);
> > + clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > + &new_crtc_state-
> > >pipe_src);
> > }
> >
> > if (new_plane_state->uapi.visible) {
> > damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> > damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > - clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > - &crtc_state-
> > >pipe_src);
> > + clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > + &new_crtc_state-
> > >pipe_src);
> > }
> > continue;
> > } else if (new_plane_state->uapi.alpha !=
> > old_plane_state->uapi.alpha) {
> > /* If alpha changed mark the whole plane
> > area as damaged */
> > damaged_area.y1 = new_plane_state-
> > >uapi.dst.y1;
> > damaged_area.y2 = new_plane_state-
> > >uapi.dst.y2;
> > - clip_area_update(&crtc_state-
> > >psr2_su_area, &damaged_area,
> > - &crtc_state->pipe_src);
> > + clip_area_update(&new_crtc_state-
> > >psr2_su_area, &damaged_area,
> > + &new_crtc_state-
> > >pipe_src);
> > continue;
> > }
> >
> > @@ -2893,7 +2902,8 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > damaged_area.x1 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> > damaged_area.x2 += new_plane_state->uapi.dst.x1 -
> > src.x1;
> >
> > - clip_area_update(&crtc_state->psr2_su_area,
> > &damaged_area, &crtc_state->pipe_src);
> > + clip_area_update(&new_crtc_state->psr2_su_area,
> > &damaged_area,
> > + &new_crtc_state->pipe_src);
> > }
> >
> > /*
> > @@ -2902,7 +2912,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > * should identify cases where this happens and fix the
> > area
> > * calculation for those.
> > */
> > - if (crtc_state->psr2_su_area.y1 == -1) {
> > + if (new_crtc_state->psr2_su_area.y1 == -1) {
> > drm_info_once(display->drm,
> > "Selective fetch area calculation
> > failed in pipe %c\n",
> > pipe_name(crtc->pipe));
> > @@ -2912,7 +2922,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > if (full_update)
> > goto skip_sel_fetch_set_loop;
> >
> > - intel_psr_apply_su_area_workarounds(crtc_state);
> > + intel_psr_apply_su_area_workarounds(new_crtc_state);
> >
> > ret = drm_atomic_add_affected_planes(&state->base, &crtc-
> > >base);
> > if (ret)
> > @@ -2926,7 +2936,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > */
> > intel_psr2_sel_fetch_et_alignment(state, crtc,
> > &cursor_in_su_area);
> >
> > - intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> > + intel_psr2_sel_fetch_pipe_alignment(new_crtc_state);
> >
> > /*
> > * Now that we have the pipe damaged area check if it
> > intersect with
> > @@ -2937,11 +2947,11 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > struct drm_rect *sel_fetch_area, inter;
> > struct intel_plane *linked = new_plane_state-
> > >planar_linked_plane;
> >
> > - if (new_plane_state->hw.crtc != crtc_state-
> > >uapi.crtc ||
> > + if (new_plane_state->hw.crtc != new_crtc_state-
> > >uapi.crtc ||
> > !new_plane_state->uapi.visible)
> > continue;
> >
> > - inter = crtc_state->psr2_su_area;
> > + inter = new_crtc_state->psr2_su_area;
> > sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> > if (!drm_rect_intersect(&inter, &new_plane_state-
> > >uapi.dst)) {
> > sel_fetch_area->y1 = -1;
> > @@ -2951,12 +2961,12 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > * disable it
> > */
> > if (drm_rect_height(&old_plane_state-
> > >psr2_sel_fetch_area) > 0)
> > - crtc_state->update_planes |=
> > BIT(plane->id);
> > + new_crtc_state->update_planes |=
> > BIT(plane->id);
> >
> > continue;
> > }
> >
> > - if
> > (!psr2_sel_fetch_plane_state_supported(new_plane_state)) {
> > + if
> > (!psr2_sel_fetch_plane_state_supported(old_crtc_state,
> > new_plane_state)) {
> > full_update = true;
> > break;
> > }
> > @@ -2964,7 +2974,7 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > sel_fetch_area = &new_plane_state-
> > >psr2_sel_fetch_area;
> > sel_fetch_area->y1 = inter.y1 - new_plane_state-
> > >uapi.dst.y1;
> > sel_fetch_area->y2 = inter.y2 - new_plane_state-
> > >uapi.dst.y1;
> > - crtc_state->update_planes |= BIT(plane->id);
> > + new_crtc_state->update_planes |= BIT(plane->id);
> >
> > /*
> > * Sel_fetch_area is calculated for UV plane. Use
> > @@ -2981,14 +2991,14 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> > linked_sel_fetch_area =
> > &linked_new_plane_state->psr2_sel_fetch_area;
> > linked_sel_fetch_area->y1 =
> > sel_fetch_area->y1;
> > linked_sel_fetch_area->y2 =
> > sel_fetch_area->y2;
> > - crtc_state->update_planes |= BIT(linked-
> > >id);
> > + new_crtc_state->update_planes |=
> > BIT(linked->id);
> > }
> > }
> >
> > skip_sel_fetch_set_loop:
> > - psr2_man_trk_ctl_calc(crtc_state, full_update);
> > - crtc_state->pipe_srcsz_early_tpt =
> > - psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);
> > + psr2_man_trk_ctl_calc(new_crtc_state, full_update);
> > + new_crtc_state->pipe_srcsz_early_tpt =
> > + psr2_pipe_srcsz_early_tpt_calc(new_crtc_state,
> > full_update);
> > return 0;
> > }
> >
> > --
> > 2.43.0
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR
2025-12-03 13:15 ` Ville Syrjälä
2025-12-04 7:09 ` Hogander, Jouni
@ 2025-12-16 8:38 ` Hogander, Jouni
1 sibling, 0 replies; 18+ messages in thread
From: Hogander, Jouni @ 2025-12-16 8:38 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
On Wed, 2025-12-03 at 15:15 +0200, Ville Syrjälä wrote:
> On Mon, Dec 01, 2025 at 03:24:55PM +0200, Jouni Högander wrote:
> > Currently plane id bit is set in crtc_state->async_flip_planes only
> > when
> > async flip toggle workaround is needed. We want to utilize
> > crtc_state->async_flip_planes further in Selective Fetch
> > calculation.
> >
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_plane.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane.c
> > b/drivers/gpu/drm/i915/display/intel_plane.c
> > index 7b7619d59251..de0a69c55582 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> > @@ -603,8 +603,7 @@ static int
> > intel_plane_atomic_calc_changes(const struct intel_crtc_state
> > *old_cr
> > if (intel_plane_do_async_flip(plane, old_crtc_state,
> > new_crtc_state)) {
> > new_crtc_state->do_async_flip = true;
> > new_crtc_state->async_flip_planes |= BIT(plane-
> > >id);
> > - } else if (plane->need_async_flip_toggle_wa &&
> > - new_crtc_state->uapi.async_flip) {
> > + } else if (new_crtc_state->uapi.async_flip) {
>
> I'd get rid of the if-else construct here now, and just do something
> like:
>
> if (intel_plane_do_async_flip(...))
> new_crtc_state->do_async_flip = true;
>
> if (new_crtc_state->uapi.async_flip) {
> /* ... */
> new_crtc_state->async_flip_planes |= BIT(plane->id);
> }
>
> We should probably also move the plane->async_flip check
> out from intel_plane_do_async_flip() and just make it a
> drm_WARN_ON(..., uapi.async_flip && !plane->async_flip).
> But that's probably better left for a separate patch.
I have sent a patch for this:
https://patchwork.freedesktop.org/series/159086/
BR,
Jouni Högander
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2025-12-16 8:38 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-12-01 13:24 [PATCH v3 0/3] Selective Fetch and async flip Jouni Högander
2025-12-01 13:24 ` [PATCH v3 1/3] drm/i915/psr: Set plane id bit in crtc_state->async_flip_planes for PSR Jouni Högander
2025-12-03 13:15 ` Ville Syrjälä
2025-12-04 7:09 ` Hogander, Jouni
2025-12-16 8:38 ` Hogander, Jouni
2025-12-01 13:24 ` [PATCH v3 2/3] drm/i915/psr: Perform full frame update on async flip Jouni Högander
2025-12-03 13:22 ` Ville Syrjälä
2025-12-03 13:58 ` Hogander, Jouni
2025-12-03 15:08 ` Ville Syrjälä
2025-12-03 15:13 ` Hogander, Jouni
2025-12-03 15:55 ` Ville Syrjälä
2025-12-04 5:49 ` Hogander, Jouni
2025-12-04 7:10 ` Hogander, Jouni
2025-12-01 13:24 ` [PATCH v3 3/3] drm/i915/psr: Allow async flip when Selective Fetch enabled Jouni Högander
2025-12-01 14:45 ` ✓ CI.KUnit: success for Selective Fetch and async flip (rev3) Patchwork
2025-12-01 15:03 ` ✗ CI.checksparse: warning " Patchwork
2025-12-01 15:27 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-01 17:25 ` ✗ Xe.CI.Full: failure " Patchwork
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