Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org,
	intel-gvt-dev@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
Cc: jani.nikula@linux.intel.com,
	Ankit Nautiyal <ankit.k.nautiyal@intel.com>,
	Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH 2/7] drm/i915/display: Add APIs to be used by gvt to get the register offsets
Date: Thu, 18 Dec 2025 13:52:55 +0530	[thread overview]
Message-ID: <20251218082302.2327243-3-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20251218082302.2327243-1-ankit.k.nautiyal@intel.com>

GVT code uses macros for register offsets that require display internal
structures. This makes clean separation of display code and
modularization difficult.

Introduce APIs to abstract offset calculations:
- intel_display_device_pipe_offset()
- intel_display_device_trans_offset()
- intel_display_device_cursor_offset()
- intel_display_device_mmio_base()

These APIs return absolute base offsets for the respective register
groups, allowing GVT to compute MMIO addresses without using internal
macros or struct fields. This prepares the path to separate
display-dependent code from i915/gvt/*.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 .../drm/i915/display/intel_display_limits.c   |  0
 drivers/gpu/drm/i915/display/intel_gvt_api.c  | 34 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_gvt_api.h  | 20 +++++++++++
 4 files changed, 55 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_limits.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_gvt_api.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_gvt_api.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index f01b5d8a07c7..7974f017f263 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -360,6 +360,7 @@ i915-y += \
 	display/intel_dvo.o \
 	display/intel_encoder.o \
 	display/intel_gmbus.o \
+	display/intel_gvt_api.o \
 	display/intel_hdmi.o \
 	display/intel_lspcon.o \
 	display/intel_lt_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.c b/drivers/gpu/drm/i915/display/intel_display_limits.c
new file mode 100644
index 000000000000..e69de29bb2d1
diff --git a/drivers/gpu/drm/i915/display/intel_gvt_api.c b/drivers/gpu/drm/i915/display/intel_gvt_api.c
new file mode 100644
index 000000000000..8abea318fbc2
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_gvt_api.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/types.h>
+
+#include "intel_display_core.h"
+#include "intel_display_regs.h"
+#include "intel_gvt_api.h"
+
+u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe)
+{
+	return INTEL_DISPLAY_DEVICE_PIPE_OFFSET(display, pipe);
+}
+EXPORT_SYMBOL_GPL(intel_display_device_pipe_offset);
+
+u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans)
+{
+	return INTEL_DISPLAY_DEVICE_TRANS_OFFSET(display, trans);
+}
+EXPORT_SYMBOL_GPL(intel_display_device_trans_offset);
+
+u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe)
+{
+	return INTEL_DISPLAY_DEVICE_CURSOR_OFFSET(display, pipe);
+}
+EXPORT_SYMBOL_GPL(intel_display_device_cursor_offset);
+
+u32 intel_display_device_mmio_base(struct intel_display *display)
+{
+	return DISPLAY_MMIO_BASE(display);
+}
+EXPORT_SYMBOL_GPL(intel_display_device_mmio_base);
diff --git a/drivers/gpu/drm/i915/display/intel_gvt_api.h b/drivers/gpu/drm/i915/display/intel_gvt_api.h
new file mode 100644
index 000000000000..e9a1122a988d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_gvt_api.h
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_GVT_API_H__
+#define __INTEL_GVT_API_H__
+
+#include <linux/types.h>
+
+enum pipe;
+enum transcoder;
+struct intel_display;
+
+u32 intel_display_device_pipe_offset(struct intel_display *display, enum pipe pipe);
+u32 intel_display_device_trans_offset(struct intel_display *display, enum transcoder trans);
+u32 intel_display_device_cursor_offset(struct intel_display *display, enum pipe pipe);
+u32 intel_display_device_mmio_base(struct intel_display *display);
+
+#endif /* __INTEL_GVT_API_H__ */
-- 
2.45.2


  parent reply	other threads:[~2025-12-18  8:35 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-18  8:22 [PATCH 0/7] Prepare GVT for display modularization Ankit Nautiyal
2025-12-18  8:22 ` [PATCH 1/7] drm/i915/display: Abstract pipe/trans/cursor offset calculation Ankit Nautiyal
2025-12-18  8:22 ` Ankit Nautiyal [this message]
2025-12-18 10:32   ` [PATCH 2/7] drm/i915/display: Add APIs to be used by gvt to get the register offsets Jani Nikula
2025-12-18 12:09     ` Nautiyal, Ankit K
2025-12-18  8:22 ` [PATCH 3/7] drm/i915/gvt: Add header to use display offset functions in macros Ankit Nautiyal
2025-12-18 10:26   ` Jani Nikula
2025-12-18  8:22 ` [PATCH 4/7] drm/i915/gvt/display_helpers: Cast argument to enum pipe for pipe-offset macro Ankit Nautiyal
2025-12-18 10:25   ` Jani Nikula
2025-12-18 12:06     ` Nautiyal, Ankit K
2025-12-18  8:22 ` [PATCH 5/7] drm/i915/gvt: Change for_each_pipe to use pipe_valid API Ankit Nautiyal
2025-12-18 10:36   ` Jani Nikula
2025-12-18 11:57     ` Nautiyal, Ankit K
2025-12-18  8:22 ` [PATCH 6/7] drm/i915/gvt: Use the appropriate header for the DPLL macro Ankit Nautiyal
2025-12-18 10:36   ` Jani Nikula
2025-12-18  8:23 ` [PATCH 7/7] drm/i915/gvt/display_helper: Get rid of #ifdef/#undefs Ankit Nautiyal
2025-12-18 10:37   ` Jani Nikula
2025-12-18  8:43 ` ✗ CI.checkpatch: warning for Prepare GVT for display modularization (rev2) Patchwork
2025-12-18  8:44 ` ✓ CI.KUnit: success " Patchwork
2025-12-18  9:00 ` ✗ CI.checksparse: warning " Patchwork
2025-12-18  9:38 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-18 10:57 ` [PATCH 0/7] Prepare GVT for display modularization Jani Nikula
2025-12-18 12:05   ` Nautiyal, Ankit K
2025-12-19  4:17 ` ✗ Xe.CI.Full: failure for Prepare GVT for display modularization (rev2) Patchwork
2025-12-29 12:47 ` [PATCH 0/7] Prepare GVT for display modularization Nautiyal, Ankit K
2025-12-31 10:35   ` Jani Nikula
2026-01-02  6:15     ` Nautiyal, Ankit K
2026-01-02 11:24       ` Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251218082302.2327243-3-ankit.k.nautiyal@intel.com \
    --to=ankit.k.nautiyal@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-gvt-dev@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=jani.nikula@intel.com \
    --cc=jani.nikula@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox