[RFC PATCH 00/13] Fence deadlines in Xe

[RFC PATCH 00/13] Fence deadlines in Xe

[Matthew Brost]

Implement fence deadlines in Xe. The idea is that if a deadline is set
on a fence, we try hard to complete it within 3 ms of the deadline. This
means for queues tied to a fence with CAP_SYS_ADMIN, we bump the
priority, and for all queues tied to a fence, we ramp up the GPU
frequency. The expected use case is a compositor that needs a steady
frame rate but does not want to run at a higher priority than the
application rendering the frame.

Lightly tested; seems to be behaving as expected and not crashing.

Matt

Matthew Brost (13):
  drm/xe: Add dedicated message lock
  drm/xe: Add EXEC_QUEUE_FLAG_CAP_SYS_NICE
  drm/xe: Store exec queue in hardware fence
  drm/xe: Add deadline exec queue vfuncs
  drm/xe: Export to_xe_hw_fence
  drm/xe: Add deadline manager
  drm/xe: Add deadline manager to user exec queues
  drm/xe: Stub out execlists deadline vfuncs as NOPs
  drm/xe: Make scheduler message lock IRQ-safe
  drm/xe: Implement GuC submission backend ops for deadlines
  drm/xe: Enable deadlines on hardware fences
  drm/xe: Add CONFIG_DRM_XE_DEADLINE_WINDOW
  drm/xe: Add exec queue deadline trace points

 drivers/gpu/drm/xe/Kconfig.profile           |   6 +
 drivers/gpu/drm/xe/Makefile                  |   1 +
 drivers/gpu/drm/xe/xe_deadline_mgr.c         | 219 +++++++++++++++++++
 drivers/gpu/drm/xe/xe_deadline_mgr.h         |  26 +++
 drivers/gpu/drm/xe/xe_deadline_mgr_types.h   |  34 +++
 drivers/gpu/drm/xe/xe_exec_queue.c           |   7 +
 drivers/gpu/drm/xe/xe_exec_queue_types.h     |  15 ++
 drivers/gpu/drm/xe/xe_execlist.c             |  20 ++
 drivers/gpu/drm/xe/xe_gpu_scheduler.c        |  33 +--
 drivers/gpu/drm/xe/xe_gpu_scheduler.h        |  11 +-
 drivers/gpu/drm/xe/xe_gpu_scheduler_types.h  |   2 +
 drivers/gpu/drm/xe/xe_guc_exec_queue_types.h |   2 +-
 drivers/gpu/drm/xe/xe_guc_submit.c           | 137 ++++++++++--
 drivers/gpu/drm/xe/xe_hw_fence.c             |  29 ++-
 drivers/gpu/drm/xe/xe_hw_fence.h             |   5 +-
 drivers/gpu/drm/xe/xe_hw_fence_types.h       |  13 ++
 drivers/gpu/drm/xe/xe_lrc.c                  |   6 +-
 drivers/gpu/drm/xe/xe_lrc.h                  |   3 +-
 drivers/gpu/drm/xe/xe_sched_job.c            |   2 +-
 drivers/gpu/drm/xe/xe_trace.h                |  10 +
 20 files changed, 530 insertions(+), 51 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_deadline_mgr.c
 create mode 100644 drivers/gpu/drm/xe/xe_deadline_mgr.h
 create mode 100644 drivers/gpu/drm/xe/xe_deadline_mgr_types.h

-- 
2.34.1

[RFC PATCH 01/13] drm/xe: Add dedicated message lock

[Matthew Brost]

Stop abusing DRM scheduler job list lock for messages, add dedicated
message lock.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Acked-by: Philipp Stanner <phasta@kernel.org>
---
 drivers/gpu/drm/xe/xe_gpu_scheduler.c       | 5 +++--
 drivers/gpu/drm/xe/xe_gpu_scheduler.h       | 4 ++--
 drivers/gpu/drm/xe/xe_gpu_scheduler_types.h | 2 ++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler.c b/drivers/gpu/drm/xe/xe_gpu_scheduler.c
index f91e06d03511..f4f23317191f 100644
--- a/drivers/gpu/drm/xe/xe_gpu_scheduler.c
+++ b/drivers/gpu/drm/xe/xe_gpu_scheduler.c
@@ -77,6 +77,7 @@ int xe_sched_init(struct xe_gpu_scheduler *sched,
 	};
 
 	sched->ops = xe_ops;
+	spin_lock_init(&sched->msg_lock);
 	INIT_LIST_HEAD(&sched->msgs);
 	INIT_WORK(&sched->work_process_msg, xe_sched_process_msg_work);
 
@@ -117,7 +118,7 @@ void xe_sched_add_msg(struct xe_gpu_scheduler *sched,
 void xe_sched_add_msg_locked(struct xe_gpu_scheduler *sched,
 			     struct xe_sched_msg *msg)
 {
-	lockdep_assert_held(&sched->base.job_list_lock);
+	lockdep_assert_held(&sched->msg_lock);
 
 	list_add_tail(&msg->link, &sched->msgs);
 	xe_sched_process_msg_queue(sched);
@@ -131,7 +132,7 @@ void xe_sched_add_msg_locked(struct xe_gpu_scheduler *sched,
 void xe_sched_add_msg_head(struct xe_gpu_scheduler *sched,
 			   struct xe_sched_msg *msg)
 {
-	lockdep_assert_held(&sched->base.job_list_lock);
+	lockdep_assert_held(&sched->msg_lock);
 
 	list_add(&msg->link, &sched->msgs);
 	xe_sched_process_msg_queue(sched);
diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler.h b/drivers/gpu/drm/xe/xe_gpu_scheduler.h
index c7a77a3a9681..dceb2cd0ee5b 100644
--- a/drivers/gpu/drm/xe/xe_gpu_scheduler.h
+++ b/drivers/gpu/drm/xe/xe_gpu_scheduler.h
@@ -33,12 +33,12 @@ void xe_sched_add_msg_head(struct xe_gpu_scheduler *sched,
 
 static inline void xe_sched_msg_lock(struct xe_gpu_scheduler *sched)
 {
-	spin_lock(&sched->base.job_list_lock);
+	spin_lock(&sched->msg_lock);
 }
 
 static inline void xe_sched_msg_unlock(struct xe_gpu_scheduler *sched)
 {
-	spin_unlock(&sched->base.job_list_lock);
+	spin_unlock(&sched->msg_lock);
 }
 
 static inline void xe_sched_stop(struct xe_gpu_scheduler *sched)
diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h b/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h
index 6731b13da8bb..63d9bf92583c 100644
--- a/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h
+++ b/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h
@@ -47,6 +47,8 @@ struct xe_gpu_scheduler {
 	const struct xe_sched_backend_ops	*ops;
 	/** @msgs: list of messages to be processed in @work_process_msg */
 	struct list_head			msgs;
+	/** @msg_lock: Message lock */
+	spinlock_t				msg_lock;
 	/** @work_process_msg: processes messages */
 	struct work_struct		work_process_msg;
 };
-- 
2.34.1

[RFC PATCH 02/13] drm/xe: Add EXEC_QUEUE_FLAG_CAP_SYS_NICE

[Matthew Brost]

Store whether CAP_SYS_NICE is set on the user process that creates an
exec queue. This will indicate if the exec queue is eligible for higher
priority levels under deadline pressure.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_exec_queue.c       | 3 +++
 drivers/gpu/drm/xe/xe_exec_queue_types.h | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 0b9e074b022f..a9b981591773 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1158,6 +1158,9 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
 	if (args->flags & DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT)
 		flags |= EXEC_QUEUE_FLAG_LOW_LATENCY;
 
+	if (capable(CAP_SYS_NICE))
+		flags |= EXEC_QUEUE_FLAG_CAP_SYS_NICE;
+
 	if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) {
 		if (XE_IOCTL_DBG(xe, args->width != 1) ||
 		    XE_IOCTL_DBG(xe, args->num_placements != 1) ||
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 67ea5eebf70b..cd7a6571f5c6 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -128,6 +128,8 @@ struct xe_exec_queue {
 #define EXEC_QUEUE_FLAG_LOW_LATENCY		BIT(5)
 /* for migration (kernel copy, clear, bind) jobs */
 #define EXEC_QUEUE_FLAG_MIGRATE			BIT(6)
+/* for user queues, created in CAP_SYS_NICE context */
+#define EXEC_QUEUE_FLAG_CAP_SYS_NICE		BIT(7)
 
 	/**
 	 * @flags: flags for this exec queue, should statically setup aside from ban
-- 
2.34.1

[RFC PATCH 03/13] drm/xe: Store exec queue in hardware fence

[Matthew Brost]

Enable hardware fences to set deadlines for exec queues.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_fence.c       | 4 +++-
 drivers/gpu/drm/xe/xe_hw_fence.h       | 2 +-
 drivers/gpu/drm/xe/xe_hw_fence_types.h | 6 ++++++
 drivers/gpu/drm/xe/xe_lrc.c            | 6 ++++--
 drivers/gpu/drm/xe/xe_lrc.h            | 3 ++-
 drivers/gpu/drm/xe/xe_sched_job.c      | 2 +-
 6 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c
index f6057456e460..5995bf095843 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.c
+++ b/drivers/gpu/drm/xe/xe_hw_fence.c
@@ -242,6 +242,7 @@ void xe_hw_fence_free(struct dma_fence *fence)
  * xe_hw_fence_init() - Initialize an hw fence.
  * @fence: Pointer to the fence to initialize.
  * @ctx: Pointer to the struct xe_hw_fence_ctx fence context.
+ * @q: Pointer to exec queue tied to the fence.
  * @seqno_map: Pointer to the map into where the seqno is blitted.
  *
  * Initializes a pre-allocated hw fence.
@@ -249,12 +250,13 @@ void xe_hw_fence_free(struct dma_fence *fence)
  * dma-fence refcounting.
  */
 void xe_hw_fence_init(struct dma_fence *fence, struct xe_hw_fence_ctx *ctx,
-		      struct iosys_map seqno_map)
+		      struct xe_exec_queue *q, struct iosys_map seqno_map)
 {
 	struct  xe_hw_fence *hw_fence =
 		container_of(fence, typeof(*hw_fence), dma);
 
 	hw_fence->xe = gt_to_xe(ctx->gt);
+	hw_fence->q = q;
 	snprintf(hw_fence->name, sizeof(hw_fence->name), "%s", ctx->name);
 	hw_fence->seqno_map = seqno_map;
 	INIT_LIST_HEAD(&hw_fence->irq_link);
diff --git a/drivers/gpu/drm/xe/xe_hw_fence.h b/drivers/gpu/drm/xe/xe_hw_fence.h
index f13a1c4982c7..7a8678c881d8 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.h
+++ b/drivers/gpu/drm/xe/xe_hw_fence.h
@@ -29,5 +29,5 @@ struct dma_fence *xe_hw_fence_alloc(void);
 void xe_hw_fence_free(struct dma_fence *fence);
 
 void xe_hw_fence_init(struct dma_fence *fence, struct xe_hw_fence_ctx *ctx,
-		      struct iosys_map seqno_map);
+		      struct xe_exec_queue *q, struct iosys_map seqno_map);
 #endif
diff --git a/drivers/gpu/drm/xe/xe_hw_fence_types.h b/drivers/gpu/drm/xe/xe_hw_fence_types.h
index 58a8d09afe5c..052bbab1fad6 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence_types.h
+++ b/drivers/gpu/drm/xe/xe_hw_fence_types.h
@@ -13,6 +13,7 @@
 #include <linux/spinlock.h>
 
 struct xe_device;
+struct xe_exec_queue;
 struct xe_gt;
 
 /**
@@ -64,6 +65,11 @@ struct xe_hw_fence {
 	struct dma_fence dma;
 	/** @xe: Xe device for hw fence driver name */
 	struct xe_device *xe;
+	/**
+	 * @q: Exec queue which fence is tied too, not ref counted, lookup
+	 * protected by fence lock.
+	 */
+	struct xe_exec_queue *q;
 	/** @name: name of hardware fence context */
 	char name[MAX_FENCE_NAME_LEN];
 	/** @seqno_map: I/O map for seqno */
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 70eae7d03a27..fc4b21e3c00d 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1783,15 +1783,17 @@ void xe_lrc_free_seqno_fence(struct dma_fence *fence)
 /**
  * xe_lrc_init_seqno_fence() - Initialize an lrc seqno fence.
  * @lrc: Pointer to the lrc.
+ ( @q: Pointner to exec queue.
  * @fence: Pointer to the fence to initialize.
  *
  * Initializes a pre-allocated lrc seqno fence.
  * After initialization, the fence is subject to normal
  * dma-fence refcounting.
  */
-void xe_lrc_init_seqno_fence(struct xe_lrc *lrc, struct dma_fence *fence)
+void xe_lrc_init_seqno_fence(struct xe_lrc *lrc, struct xe_exec_queue *q,
+			     struct dma_fence *fence)
 {
-	xe_hw_fence_init(fence, &lrc->fence_ctx, __xe_lrc_seqno_map(lrc));
+	xe_hw_fence_init(fence, &lrc->fence_ctx, q, __xe_lrc_seqno_map(lrc));
 }
 
 s32 xe_lrc_seqno(struct xe_lrc *lrc)
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index 8acf85273c1a..3d72b4c0da8e 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -118,7 +118,8 @@ u64 xe_lrc_descriptor(struct xe_lrc *lrc);
 u32 xe_lrc_seqno_ggtt_addr(struct xe_lrc *lrc);
 struct dma_fence *xe_lrc_alloc_seqno_fence(void);
 void xe_lrc_free_seqno_fence(struct dma_fence *fence);
-void xe_lrc_init_seqno_fence(struct xe_lrc *lrc, struct dma_fence *fence);
+void xe_lrc_init_seqno_fence(struct xe_lrc *lrc, struct xe_exec_queue *q,
+			     struct dma_fence *fence);
 s32 xe_lrc_seqno(struct xe_lrc *lrc);
 
 u32 xe_lrc_start_seqno_ggtt_addr(struct xe_lrc *lrc);
diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c
index cb674a322113..6099b4445835 100644
--- a/drivers/gpu/drm/xe/xe_sched_job.c
+++ b/drivers/gpu/drm/xe/xe_sched_job.c
@@ -270,7 +270,7 @@ void xe_sched_job_arm(struct xe_sched_job *job)
 		struct dma_fence_chain *chain;
 
 		fence = job->ptrs[i].lrc_fence;
-		xe_lrc_init_seqno_fence(q->lrc[i], fence);
+		xe_lrc_init_seqno_fence(q->lrc[i], q, fence);
 		job->ptrs[i].lrc_fence = NULL;
 		if (!i) {
 			job->lrc_seqno = fence->seqno;
-- 
2.34.1

[RFC PATCH 04/13] drm/xe: Add deadline exec queue vfuncs

[Matthew Brost]

Add set_deadline, enter_deadline, and exit_deadline exec queue vfuncs
for deadline control.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_exec_queue_types.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index cd7a6571f5c6..ceb0dcea6dfc 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -301,6 +301,15 @@ struct xe_exec_queue_ops {
 	void (*resume)(struct xe_exec_queue *q);
 	/** @reset_status: check exec queue reset status */
 	bool (*reset_status)(struct xe_exec_queue *q);
+	/**
+	 * @set_deadline: Set deadline for on a queue for a fence.
+	 */
+	void (*set_deadline)(struct xe_exec_queue *q, struct dma_fence *fence,
+			     ktime_t deadline);
+	/** @enter_deadline: Enter a deadline */
+	void (*enter_deadline)(struct xe_exec_queue *q);
+	/** @exit_deadline: Enter a deadline */
+	void (*exit_deadline)(struct xe_exec_queue *q);
 };
 
 #endif
-- 
2.34.1

[RFC PATCH 05/13] drm/xe: Export to_xe_hw_fence

[Matthew Brost]

Allow other layers to operate on hardware fences.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_fence.c | 9 ++++++---
 drivers/gpu/drm/xe/xe_hw_fence.h | 3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c
index 5995bf095843..ec06b1eaf004 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.c
+++ b/drivers/gpu/drm/xe/xe_hw_fence.c
@@ -138,8 +138,6 @@ void xe_hw_fence_ctx_finish(struct xe_hw_fence_ctx *ctx)
 {
 }
 
-static struct xe_hw_fence *to_xe_hw_fence(struct dma_fence *fence);
-
 static struct xe_hw_fence_irq *xe_hw_fence_irq(struct xe_hw_fence *fence)
 {
 	return container_of(fence->dma.lock, struct xe_hw_fence_irq, lock);
@@ -200,7 +198,12 @@ static const struct dma_fence_ops xe_hw_fence_ops = {
 	.release = xe_hw_fence_release,
 };
 
-static struct xe_hw_fence *to_xe_hw_fence(struct dma_fence *fence)
+/**
+ * to_xe_hw_fence() - Convert dma-fence to Xe hardware fence
+ *
+ * Return: struct xe_hw_fence or NULL
+ */
+struct xe_hw_fence *to_xe_hw_fence(struct dma_fence *fence)
 {
 	if (XE_WARN_ON(fence->ops != &xe_hw_fence_ops))
 		return NULL;
diff --git a/drivers/gpu/drm/xe/xe_hw_fence.h b/drivers/gpu/drm/xe/xe_hw_fence.h
index 7a8678c881d8..4d5756681279 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.h
+++ b/drivers/gpu/drm/xe/xe_hw_fence.h
@@ -30,4 +30,7 @@ void xe_hw_fence_free(struct dma_fence *fence);
 
 void xe_hw_fence_init(struct dma_fence *fence, struct xe_hw_fence_ctx *ctx,
 		      struct xe_exec_queue *q, struct iosys_map seqno_map);
+
+struct xe_hw_fence *to_xe_hw_fence(struct dma_fence *fence);
+
 #endif
-- 
2.34.1

[RFC PATCH 06/13] drm/xe: Add deadline manager

[Matthew Brost]

Add a deadline manager that toggles the exec queue’s deadline state. It
is implemented using a list of deadlines (hardware fences) and an
hrtimer, which dynamically enters or exits the queue’s deadline state if
a deadline is within 3 ms of being missed. The intended usage is for
compositors to avoid missing page flips.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/Makefile                |   1 +
 drivers/gpu/drm/xe/xe_deadline_mgr.c       | 213 +++++++++++++++++++++
 drivers/gpu/drm/xe/xe_deadline_mgr.h       |  26 +++
 drivers/gpu/drm/xe/xe_deadline_mgr_types.h |  34 ++++
 drivers/gpu/drm/xe/xe_hw_fence.c           |   3 +
 drivers/gpu/drm/xe/xe_hw_fence_types.h     |   7 +
 6 files changed, 284 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_deadline_mgr.c
 create mode 100644 drivers/gpu/drm/xe/xe_deadline_mgr.h
 create mode 100644 drivers/gpu/drm/xe/xe_deadline_mgr_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 1d571cdbd6fa..4fbdf7f83f3a 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -35,6 +35,7 @@ $(obj)/generated/%_device_wa_oob.c $(obj)/generated/%_device_wa_oob.h: $(obj)/xe
 xe-y += xe_bb.o \
 	xe_bo.o \
 	xe_bo_evict.o \
+	xe_deadline_mgr.o \
 	xe_dep_scheduler.o \
 	xe_devcoredump.o \
 	xe_device.o \
diff --git a/drivers/gpu/drm/xe/xe_deadline_mgr.c b/drivers/gpu/drm/xe/xe_deadline_mgr.c
new file mode 100644
index 000000000000..5159ce35fdde
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_deadline_mgr.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/dma-fence-chain.h>
+
+#include "xe_deadline_mgr.h"
+#include "xe_deadline_mgr_types.h"
+#include "xe_exec_queue_types.h"
+#include "xe_gt.h"
+#include "xe_hw_fence.h"
+
+static void __xe_deadline_mgr_enter_deadline(struct xe_deadline_mgr *mgr)
+{
+	lockdep_assert_held(&mgr->lock);
+
+	if (!mgr->deadline_entered) {
+		mgr->deadline_entered = true;
+		mgr->q->ops->enter_deadline(mgr->q);
+	}
+}
+
+static void __xe_deadline_mgr_exit_deadline(struct xe_deadline_mgr *mgr)
+{
+	lockdep_assert_held(&mgr->lock);
+
+	if (mgr->deadline_entered) {
+		mgr->deadline_entered = false;
+		mgr->q->ops->exit_deadline(mgr->q);
+	}
+}
+
+static enum hrtimer_restart deadline_timer(struct hrtimer *t)
+{
+	struct xe_deadline_mgr *mgr = container_of(t, typeof(*mgr), timer);
+
+	guard(spinlock_irqsave)(&mgr->lock);
+	__xe_deadline_mgr_enter_deadline(mgr);
+
+	return HRTIMER_NORESTART;
+}
+
+/**
+ * xe_deadline_mgr_init() - Deadline manager initialize
+ * @mgr: Deadline manager object
+ * @q: Exec queue associated with deadline
+ */
+void xe_deadline_mgr_init(struct xe_deadline_mgr *mgr, struct xe_exec_queue *q)
+{
+	mgr->q = q;
+	INIT_LIST_HEAD(&mgr->deadlines);
+	spin_lock_init(&mgr->lock);
+	hrtimer_setup(&mgr->timer, deadline_timer, CLOCK_MONOTONIC,
+		      HRTIMER_MODE_ABS);
+	mgr->deadline = XE_DEADLINE_NONE;
+	mgr->deadline_entered = false;
+}
+
+/**
+ * xe_deadline_mgr_fini() - Deadline manager finalize
+ * @mgr: Deadline manager object
+ */
+void xe_deadline_mgr_fini(struct xe_deadline_mgr *mgr)
+{
+	xe_assert(gt_to_xe(mgr->q->gt), !mgr->deadline_entered);
+	xe_assert(gt_to_xe(mgr->q->gt), !hrtimer_cancel(&mgr->timer));
+	xe_assert(gt_to_xe(mgr->q->gt), list_empty(&mgr->deadlines));
+}
+
+static ktime_t __xe_deadline_mgr_new_deadline(struct xe_deadline_mgr *mgr)
+{
+	struct xe_hw_fence *hw_fence;
+
+	lockdep_assert_held(&mgr->lock);
+
+	hw_fence = list_first_entry_or_null(&mgr->deadlines,
+					    typeof(*hw_fence),
+					    deadline.link);
+	if (!hw_fence)
+		return XE_DEADLINE_NONE;
+	else
+		return hw_fence->deadline.time;
+
+}
+
+static void __xe_deadline_mgr_update_deadline(struct xe_deadline_mgr *mgr)
+{
+	ktime_t old_deadline = mgr->deadline;
+
+	lockdep_assert_held(&mgr->lock);
+
+	mgr->deadline = __xe_deadline_mgr_new_deadline(mgr);
+
+	if (old_deadline != mgr->deadline) {
+		hrtimer_cancel(&mgr->timer);
+
+		if (mgr->deadline != XE_DEADLINE_NONE) {
+			ktime_t deadline = ktime_sub(mgr->deadline,
+						     ms_to_ktime(3));
+			ktime_t now = ktime_get();
+
+			if (ktime_after(now, deadline)) {
+				__xe_deadline_mgr_enter_deadline(mgr);
+			} else {
+				__xe_deadline_mgr_exit_deadline(mgr);
+				hrtimer_start(&mgr->timer, deadline,
+					      HRTIMER_MODE_ABS);
+			}
+		} else {
+			__xe_deadline_mgr_exit_deadline(mgr);
+		}
+	}
+}
+
+static void __xe_deadline_mgr_remove_deadline(struct xe_deadline_mgr *mgr,
+					      struct xe_hw_fence *hw_fence)
+{
+	ktime_t old_deadline = hw_fence->deadline.time;
+
+	lockdep_assert_held(&mgr->lock);
+
+	hw_fence->deadline.time = XE_DEADLINE_DONE;
+	if (old_deadline == XE_DEADLINE_NONE)
+		return;
+
+	list_del_init(&hw_fence->deadline.link);
+	__xe_deadline_mgr_update_deadline(mgr);
+}
+
+
+static void __xe_deadline_mgr_add_deadline(struct xe_deadline_mgr *mgr,
+					   struct xe_hw_fence *hw_fence,
+					   ktime_t deadline)
+{
+	struct xe_hw_fence *pos;
+
+	lockdep_assert_held(&mgr->lock);
+
+	hw_fence->deadline.time = deadline;
+
+	list_for_each_entry(pos, &mgr->deadlines, deadline.link) {
+		if (pos->deadline.time >= hw_fence->deadline.time) {
+			list_add_tail(&hw_fence->deadline.link,
+				      &pos->deadline.link);
+			return;
+		}
+	}
+
+	list_add_tail(&hw_fence->deadline.link, &mgr->deadlines);
+}
+
+/**
+ * xe_deadline_mgr_add_deadline() - Add deadline
+ * @mgr: Deadline manager object
+ * @fence: Fence with deadline (must be struct xe_hw_fence)
+ * @deadline: Deadline for the fence
+ *
+ * Add a deadline for a fence. This may be called multiple times on a given
+ * fence. It assumes upper layers only call this function multiple times if the
+ * deadline is being reduced. If called after xe_deadline_mgr_remove_deadline,
+ * this function is a NOP.
+ */
+void xe_deadline_mgr_add_deadline(struct xe_deadline_mgr *mgr,
+				  struct dma_fence *fence,
+				  ktime_t deadline)
+{
+	struct xe_hw_fence *hw_fence = to_xe_hw_fence(fence);
+
+	guard(spinlock_irqsave)(&mgr->lock);
+
+	if (hw_fence->deadline.time == XE_DEADLINE_DONE)
+		return;
+
+	xe_assert(gt_to_xe(mgr->q->gt),
+		  hw_fence->deadline.time == XE_DEADLINE_NONE ||
+		  deadline < hw_fence->deadline.time);
+
+	__xe_deadline_mgr_remove_deadline(mgr, hw_fence);
+	__xe_deadline_mgr_add_deadline(mgr, hw_fence, deadline);
+	__xe_deadline_mgr_update_deadline(mgr);
+}
+
+/**
+ * xe_deadline_mgr_remove_deadline() - Remove deadline
+ * @mgr: Deadline manager object
+ * @fence: Fence with deadline (must be struct xe_hw_fence or chain of struct
+ * xe_hw_fence)
+ *
+ * Remove the deadline for a fence. This should be called exactly once after the
+ * fence is signaled. After this function is called, future
+ * xe_deadline_mgr_add_deadline calls are NOPs.
+ */
+void xe_deadline_mgr_remove_deadline(struct xe_deadline_mgr *mgr,
+				     struct dma_fence *fence)
+{
+	struct dma_fence *iter, *__fence;
+
+	guard(spinlock_irqsave)(&mgr->lock);
+
+	xe_assert(gt_to_xe(mgr->q->gt), dma_fence_is_signaled(fence));
+
+	if (!dma_fence_is_chain(fence)) {
+		__xe_deadline_mgr_remove_deadline(mgr, to_xe_hw_fence(fence));
+		return;
+	}
+
+	dma_fence_chain_for_each(iter, fence) {
+		__fence = dma_fence_chain_contained(iter);
+
+		__xe_deadline_mgr_remove_deadline(mgr, to_xe_hw_fence(__fence));
+	}
+}
diff --git a/drivers/gpu/drm/xe/xe_deadline_mgr.h b/drivers/gpu/drm/xe/xe_deadline_mgr.h
new file mode 100644
index 000000000000..80cce5930c4f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_deadline_mgr.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_EXEC_QUEUE_DEADLINE_MGR_H_
+#define _XE_EXEC_QUEUE_DEADLINE_MGR_H_
+
+#include <linux/types.h>
+
+struct dma_fence;
+struct xe_deadline_mgr;
+struct xe_exec_queue;
+
+void xe_deadline_mgr_init(struct xe_deadline_mgr *mgr, struct xe_exec_queue *q);
+
+void xe_deadline_mgr_fini(struct xe_deadline_mgr *mgr);
+
+void xe_deadline_mgr_add_deadline(struct xe_deadline_mgr *mgr,
+				  struct dma_fence *fence,
+				  ktime_t deadline);
+
+void xe_deadline_mgr_remove_deadline(struct xe_deadline_mgr *mgr,
+				     struct dma_fence *fence);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_deadline_mgr_types.h b/drivers/gpu/drm/xe/xe_deadline_mgr_types.h
new file mode 100644
index 000000000000..e743367647c5
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_deadline_mgr_types.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_DEADLINE_MGR_TYPES_H_
+#define _XE_DEADLINE_MGR_TYPES_H_
+
+#include <linux/hrtimer_types.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct xe_exec_queue;
+
+#define XE_DEADLINE_NONE	(-1)
+#define XE_DEADLINE_DONE	(-2)
+
+/** struct xe_deadline_mgr - Xe deadline manager */
+struct xe_deadline_mgr {
+	/** @q: Pointer to queue associated with deadline */
+	struct xe_exec_queue *q;
+	/** @deadlines: List storing deadline fences, protected by @lock */
+	struct list_head deadlines;
+	/** @timer: Timer to enter deadline mode, protected by @lock */
+	struct hrtimer timer;
+	/** @lock: Lock to protect deadlines */
+	spinlock_t lock;
+	/** @deadline: Current deadline, protected by @lock */
+	ktime_t deadline;
+	/** @deadline_entered: In deadline mode, protected by @lock */
+	bool deadline_entered;
+};
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c
index ec06b1eaf004..8b884691718f 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.c
+++ b/drivers/gpu/drm/xe/xe_hw_fence.c
@@ -9,6 +9,7 @@
 #include <linux/slab.h>
 
 #include "xe_bo.h"
+#include "xe_deadline_mgr_types.h"
 #include "xe_device.h"
 #include "xe_gt.h"
 #include "xe_hw_engine.h"
@@ -260,6 +261,8 @@ void xe_hw_fence_init(struct dma_fence *fence, struct xe_hw_fence_ctx *ctx,
 
 	hw_fence->xe = gt_to_xe(ctx->gt);
 	hw_fence->q = q;
+	hw_fence->deadline.time = XE_DEADLINE_NONE;
+	INIT_LIST_HEAD(&hw_fence->deadline.link);
 	snprintf(hw_fence->name, sizeof(hw_fence->name), "%s", ctx->name);
 	hw_fence->seqno_map = seqno_map;
 	INIT_LIST_HEAD(&hw_fence->irq_link);
diff --git a/drivers/gpu/drm/xe/xe_hw_fence_types.h b/drivers/gpu/drm/xe/xe_hw_fence_types.h
index 052bbab1fad6..8d035c52195c 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence_types.h
+++ b/drivers/gpu/drm/xe/xe_hw_fence_types.h
@@ -76,6 +76,13 @@ struct xe_hw_fence {
 	struct iosys_map seqno_map;
 	/** @irq_link: Link in struct xe_hw_fence_irq.pending */
 	struct list_head irq_link;
+	/** @deadline: Deadline info, protected by deadline manager lock */
+	struct {
+		/** @deadline.time: Deadline time */
+		ktime_t time;
+		/** @deadline.list: Deadline link */
+		struct list_head link;
+	} deadline;
 };
 
 #endif
-- 
2.34.1

[RFC PATCH 07/13] drm/xe: Add deadline manager to user exec queues

[Matthew Brost]

User exec queues can set deadlines in exported scheduler fences.
Initialize the deadline manager to facilitate this.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_exec_queue.c       | 4 ++++
 drivers/gpu/drm/xe/xe_exec_queue_types.h | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index a9b981591773..6015b2334a0f 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -14,6 +14,7 @@
 #include <uapi/drm/xe_drm.h>
 
 #include "xe_bo.h"
+#include "xe_deadline_mgr.h"
 #include "xe_dep_scheduler.h"
 #include "xe_device.h"
 #include "xe_gt.h"
@@ -266,6 +267,8 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
 		}
 	}
 
+	xe_deadline_mgr_init(&q->deadline_mgr, q);
+
 	return q;
 }
 
@@ -332,6 +335,7 @@ static void __xe_exec_queue_fini(struct xe_exec_queue *q)
 {
 	int i;
 
+	xe_deadline_mgr_fini(&q->deadline_mgr);
 	q->ops->fini(q);
 
 	for (i = 0; i < q->width; ++i)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index ceb0dcea6dfc..318c577786f7 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -10,6 +10,7 @@
 
 #include <drm/gpu_scheduler.h>
 
+#include "xe_deadline_mgr_types.h"
 #include "xe_gpu_scheduler_types.h"
 #include "xe_hw_engine_types.h"
 #include "xe_hw_fence_types.h"
@@ -219,6 +220,9 @@ struct xe_exec_queue {
 		struct list_head link;
 	} pxp;
 
+	/** @deadline_mgr: Deadline manager */
+	struct xe_deadline_mgr deadline_mgr;
+
 	/** @ufence_syncobj: User fence syncobj */
 	struct drm_syncobj *ufence_syncobj;
 
-- 
2.34.1

[RFC PATCH 08/13] drm/xe: Stub out execlists deadline vfuncs as NOPs

[Matthew Brost]

The execlists backend is non-functional but shouldn’t crash. Stub out
execlists deadline vfuncs as NOPs.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_execlist.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
index 46c17a18a3f4..1e9323fe19e3 100644
--- a/drivers/gpu/drm/xe/xe_execlist.c
+++ b/drivers/gpu/drm/xe/xe_execlist.c
@@ -469,6 +469,23 @@ static bool execlist_exec_queue_reset_status(struct xe_exec_queue *q)
 	return false;
 }
 
+static void execlist_exec_queue_set_deadline(struct xe_exec_queue *q,
+					     struct dma_fence *fence,
+					     ktime_t deadline)
+{
+	/* NIY */
+}
+
+static void execlist_exec_queue_enter_deadline(struct xe_exec_queue *q)
+{
+	/* NIY */
+}
+
+static void execlist_exec_queue_exit_deadline(struct xe_exec_queue *q)
+{
+	/* NIY */
+}
+
 static const struct xe_exec_queue_ops execlist_exec_queue_ops = {
 	.init = execlist_exec_queue_init,
 	.kill = execlist_exec_queue_kill,
@@ -481,6 +498,9 @@ static const struct xe_exec_queue_ops execlist_exec_queue_ops = {
 	.suspend_wait = execlist_exec_queue_suspend_wait,
 	.resume = execlist_exec_queue_resume,
 	.reset_status = execlist_exec_queue_reset_status,
+	.set_deadline = execlist_exec_queue_set_deadline,
+	.enter_deadline = execlist_exec_queue_enter_deadline,
+	.exit_deadline = execlist_exec_queue_exit_deadline,
 };
 
 int xe_execlist_init(struct xe_gt *gt)
-- 
2.34.1

[RFC PATCH 09/13] drm/xe: Make scheduler message lock IRQ-safe

[Matthew Brost]

It is legal to modify deadlines in IRQ contexts, and deadlines can add
messages. Therefore, the scheduler message lock needs to be IRQ-safe.
Change xe_sched_msg_lock to use scoped_guard, which is IRQ-safe.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_gpu_scheduler.c | 28 +++++++++++++--------------
 drivers/gpu/drm/xe/xe_gpu_scheduler.h | 11 ++---------
 drivers/gpu/drm/xe/xe_guc_submit.c    | 23 ++++++++++------------
 3 files changed, 26 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler.c b/drivers/gpu/drm/xe/xe_gpu_scheduler.c
index f4f23317191f..d0589cc333ac 100644
--- a/drivers/gpu/drm/xe/xe_gpu_scheduler.c
+++ b/drivers/gpu/drm/xe/xe_gpu_scheduler.c
@@ -15,11 +15,12 @@ static void xe_sched_process_msg_queue_if_ready(struct xe_gpu_scheduler *sched)
 {
 	struct xe_sched_msg *msg;
 
-	xe_sched_msg_lock(sched);
-	msg = list_first_entry_or_null(&sched->msgs, struct xe_sched_msg, link);
-	if (msg)
-		xe_sched_process_msg_queue(sched);
-	xe_sched_msg_unlock(sched);
+	xe_sched_msg_lock(sched) {
+		msg = list_first_entry_or_null(&sched->msgs,
+					       struct xe_sched_msg, link);
+		if (msg)
+			xe_sched_process_msg_queue(sched);
+	}
 }
 
 static struct xe_sched_msg *
@@ -27,12 +28,12 @@ xe_sched_get_msg(struct xe_gpu_scheduler *sched)
 {
 	struct xe_sched_msg *msg;
 
-	xe_sched_msg_lock(sched);
-	msg = list_first_entry_or_null(&sched->msgs,
-				       struct xe_sched_msg, link);
-	if (msg)
-		list_del_init(&msg->link);
-	xe_sched_msg_unlock(sched);
+	xe_sched_msg_lock(sched) {
+		msg = list_first_entry_or_null(&sched->msgs,
+					       struct xe_sched_msg, link);
+		if (msg)
+			list_del_init(&msg->link);
+	}
 
 	return msg;
 }
@@ -110,9 +111,8 @@ void xe_sched_submission_resume_tdr(struct xe_gpu_scheduler *sched)
 void xe_sched_add_msg(struct xe_gpu_scheduler *sched,
 		      struct xe_sched_msg *msg)
 {
-	xe_sched_msg_lock(sched);
-	xe_sched_add_msg_locked(sched, msg);
-	xe_sched_msg_unlock(sched);
+	xe_sched_msg_lock(sched)
+		xe_sched_add_msg_locked(sched, msg);
 }
 
 void xe_sched_add_msg_locked(struct xe_gpu_scheduler *sched,
diff --git a/drivers/gpu/drm/xe/xe_gpu_scheduler.h b/drivers/gpu/drm/xe/xe_gpu_scheduler.h
index dceb2cd0ee5b..b0918ea3adbd 100644
--- a/drivers/gpu/drm/xe/xe_gpu_scheduler.h
+++ b/drivers/gpu/drm/xe/xe_gpu_scheduler.h
@@ -31,15 +31,8 @@ void xe_sched_add_msg_locked(struct xe_gpu_scheduler *sched,
 void xe_sched_add_msg_head(struct xe_gpu_scheduler *sched,
 			   struct xe_sched_msg *msg);
 
-static inline void xe_sched_msg_lock(struct xe_gpu_scheduler *sched)
-{
-	spin_lock(&sched->msg_lock);
-}
-
-static inline void xe_sched_msg_unlock(struct xe_gpu_scheduler *sched)
-{
-	spin_unlock(&sched->msg_lock);
-}
+#define xe_sched_msg_lock(sched)	\
+	scoped_guard(spinlock_irqsave, &sched->msg_lock)
 
 static inline void xe_sched_stop(struct xe_gpu_scheduler *sched)
 {
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 7a4218f76024..76460b8ab407 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -2329,10 +2329,10 @@ static int guc_exec_queue_suspend(struct xe_exec_queue *q)
 	if (exec_queue_killed_or_banned_or_wedged(q))
 		return -EINVAL;
 
-	xe_sched_msg_lock(sched);
-	if (guc_exec_queue_try_add_msg(q, msg, SUSPEND))
-		q->guc->suspend_pending = true;
-	xe_sched_msg_unlock(sched);
+	xe_sched_msg_lock(sched) {
+		if (guc_exec_queue_try_add_msg(q, msg, SUSPEND))
+			q->guc->suspend_pending = true;
+	}
 
 	return 0;
 }
@@ -2388,9 +2388,8 @@ static void guc_exec_queue_resume(struct xe_exec_queue *q)
 
 	xe_gt_assert(guc_to_gt(guc), !q->guc->suspend_pending);
 
-	xe_sched_msg_lock(sched);
-	guc_exec_queue_try_add_msg(q, msg, RESUME);
-	xe_sched_msg_unlock(sched);
+	xe_sched_msg_lock(sched)
+		guc_exec_queue_try_add_msg(q, msg, RESUME);
 }
 
 static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)
@@ -2810,9 +2809,8 @@ static void guc_exec_queue_replay_pending_state_change(struct xe_exec_queue *q)
 	if (q->guc->needs_suspend) {
 		msg = q->guc->static_msgs + STATIC_MSG_SUSPEND;
 
-		xe_sched_msg_lock(sched);
-		guc_exec_queue_try_add_msg_head(q, msg, SUSPEND);
-		xe_sched_msg_unlock(sched);
+		xe_sched_msg_lock(sched)
+			guc_exec_queue_try_add_msg_head(q, msg, SUSPEND);
 
 		q->guc->needs_suspend = false;
 	}
@@ -2825,9 +2823,8 @@ static void guc_exec_queue_replay_pending_state_change(struct xe_exec_queue *q)
 	if (q->guc->needs_resume) {
 		msg = q->guc->static_msgs + STATIC_MSG_RESUME;
 
-		xe_sched_msg_lock(sched);
-		guc_exec_queue_try_add_msg_head(q, msg, RESUME);
-		xe_sched_msg_unlock(sched);
+		xe_sched_msg_lock(sched)
+			guc_exec_queue_try_add_msg_head(q, msg, RESUME);
 
 		q->guc->needs_resume = false;
 	}
-- 
2.34.1

[RFC PATCH 10/13] drm/xe: Implement GuC submission backend ops for deadlines

[Matthew Brost]

Implement GuC submission backend ops for deadlines, which dynamically
raise or lower the priority of user queues with CAP_SYS_NICE and adjust
queue frequency upon deadline entry or exit. The idea is that if a fence
on a queue is at risk of missing a deadline, we try to ensure this fence
completes as soon as possible.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_exec_queue_types.h |   2 +-
 drivers/gpu/drm/xe/xe_guc_submit.c           | 110 ++++++++++++++++++-
 2 files changed, 108 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
index a3b034e4b205..fcc7bca2405a 100644
--- a/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
@@ -31,7 +31,7 @@ struct xe_guc_exec_queue {
 	 * a message needs to sent through the GPU scheduler but memory
 	 * allocations are not allowed.
 	 */
-#define MAX_STATIC_MSG_TYPE	3
+#define MAX_STATIC_MSG_TYPE	5
 	struct xe_sched_msg static_msgs[MAX_STATIC_MSG_TYPE];
 	/** @lr_tdr: long running TDR worker */
 	struct work_struct lr_tdr;
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 76460b8ab407..791c64d6397f 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -20,6 +20,7 @@
 #include "regs/xe_lrc_layout.h"
 #include "xe_assert.h"
 #include "xe_bo.h"
+#include "xe_deadline_mgr.h"
 #include "xe_devcoredump.h"
 #include "xe_device.h"
 #include "xe_exec_queue.h"
@@ -552,6 +553,26 @@ static const int xe_exec_queue_prio_to_guc[] = {
 	[XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH,
 };
 
+static void deadline_policies(struct xe_guc *guc, struct xe_exec_queue *q)
+{
+	struct exec_queue_policy policy;
+	enum xe_exec_queue_priority prio =
+		q->flags & EXEC_QUEUE_FLAG_CAP_SYS_NICE ?
+		XE_EXEC_QUEUE_PRIORITY_HIGH : q->sched_props.priority;
+	u32 slpc_exec_queue_freq_req = SLPC_CTX_FREQ_REQ_IS_COMPUTE;
+
+	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q) &&
+		     !xe_exec_queue_is_multi_queue_secondary(q));
+
+	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
+	__guc_exec_queue_policy_add_priority(&policy, xe_exec_queue_prio_to_guc[prio]);
+	__guc_exec_queue_policy_add_slpc_exec_queue_freq_req(&policy,
+							     slpc_exec_queue_freq_req);
+
+	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
+		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
+}
+
 static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)
 {
 	struct exec_queue_policy policy;
@@ -1249,6 +1270,7 @@ static void guc_exec_queue_free_job(struct drm_sched_job *drm_job)
 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
 
 	trace_xe_sched_job_free(job);
+	xe_deadline_mgr_remove_deadline(&job->q->deadline_mgr, job->fence);
 	xe_sched_job_put(job);
 }
 
@@ -2037,11 +2059,39 @@ static void __guc_exec_queue_process_msg_set_multi_queue_priority(struct xe_sche
 	kfree(msg);
 }
 
+static void __guc_exec_queue_process_msg_enter_deadline(struct xe_sched_msg *msg)
+{
+	struct xe_exec_queue *q = msg->private_data;
+	struct xe_guc *guc = exec_queue_to_guc(q);
+
+	/* XXX: Rethink multi-q implementation */
+	if (xe_exec_queue_is_multi_queue_secondary(q))
+		q = xe_exec_queue_multi_queue_primary(q);
+
+	if (guc_exec_queue_allowed_to_change_state(q))
+		deadline_policies(guc, q);
+}
+
+static void __guc_exec_queue_process_msg_exit_deadline(struct xe_sched_msg *msg)
+{
+	struct xe_exec_queue *q = msg->private_data;
+	struct xe_guc *guc = exec_queue_to_guc(q);
+
+	/* XXX: Rethink multi-q implementation */
+	if (xe_exec_queue_is_multi_queue_secondary(q))
+		q = xe_exec_queue_multi_queue_primary(q);
+
+	if (guc_exec_queue_allowed_to_change_state(q))
+		init_policies(guc, q);
+}
+
 #define CLEANUP				1	/* Non-zero values to catch uninitialized msg */
 #define SET_SCHED_PROPS			2
 #define SUSPEND				3
 #define RESUME				4
 #define SET_MULTI_QUEUE_PRIORITY	5
+#define ENTER_DEADLINE			6
+#define EXIT_DEADLINE			7
 #define OPCODE_MASK	0xf
 #define MSG_LOCKED	BIT(8)
 #define MSG_HEAD	BIT(9)
@@ -2068,6 +2118,12 @@ static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
 	case SET_MULTI_QUEUE_PRIORITY:
 		__guc_exec_queue_process_msg_set_multi_queue_priority(msg);
 		break;
+	case ENTER_DEADLINE:
+		__guc_exec_queue_process_msg_enter_deadline(msg);
+		break;
+	case EXIT_DEADLINE:
+		__guc_exec_queue_process_msg_exit_deadline(msg);
+		break;
 	default:
 		XE_WARN_ON("Unknown message type");
 	}
@@ -2231,9 +2287,11 @@ static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
 	return true;
 }
 
-#define STATIC_MSG_CLEANUP	0
-#define STATIC_MSG_SUSPEND	1
-#define STATIC_MSG_RESUME	2
+#define STATIC_MSG_CLEANUP		0
+#define STATIC_MSG_SUSPEND		1
+#define STATIC_MSG_RESUME		2
+#define STATIC_MSG_ENTER_DEADLINE	3
+#define STATIC_MSG_EXIT_DEADLINE	4
 static void guc_exec_queue_destroy(struct xe_exec_queue *q)
 {
 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
@@ -2401,6 +2459,49 @@ static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)
 	return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q);
 }
 
+static void guc_exec_queue_set_deadline(struct xe_exec_queue *q,
+					struct dma_fence *fence,
+					ktime_t deadline)
+{
+	xe_deadline_mgr_add_deadline(&q->deadline_mgr, fence, deadline);
+}
+
+static void guc_exec_queue_enter_deadline(struct xe_exec_queue *q)
+{
+	struct xe_gpu_scheduler *sched = &q->guc->sched;
+	struct xe_sched_msg *msg = q->guc->static_msgs +
+		STATIC_MSG_ENTER_DEADLINE;
+
+	xe_sched_msg_lock(sched) {
+		if (!guc_exec_queue_try_add_msg(q, msg, ENTER_DEADLINE)) {
+			/*
+			 * Corner case where a deadline enter + exit are in
+			 * message list, delete the exit deadline message.
+			 */
+			msg = q->guc->static_msgs + STATIC_MSG_EXIT_DEADLINE;
+			list_del_init(&msg->link);
+		}
+	}
+}
+
+static void guc_exec_queue_exit_deadline(struct xe_exec_queue *q)
+{
+	struct xe_gpu_scheduler *sched = &q->guc->sched;
+	struct xe_sched_msg *msg = q->guc->static_msgs +
+		STATIC_MSG_EXIT_DEADLINE;
+
+	xe_sched_msg_lock(sched) {
+		if (!guc_exec_queue_try_add_msg(q, msg, EXIT_DEADLINE)) {
+			/*
+			 * Corner case where a deadline exit + enter are in
+			 * message list, delete the enter deadline message.
+			 */
+			msg = q->guc->static_msgs + STATIC_MSG_ENTER_DEADLINE;
+			list_del_init(&msg->link);
+		}
+	}
+}
+
 /*
  * All of these functions are an abstraction layer which other parts of Xe can
  * use to trap into the GuC backend. All of these functions, aside from init,
@@ -2420,6 +2521,9 @@ static const struct xe_exec_queue_ops guc_exec_queue_ops = {
 	.suspend_wait = guc_exec_queue_suspend_wait,
 	.resume = guc_exec_queue_resume,
 	.reset_status = guc_exec_queue_reset_status,
+	.set_deadline = guc_exec_queue_set_deadline,
+	.enter_deadline = guc_exec_queue_enter_deadline,
+	.exit_deadline = guc_exec_queue_exit_deadline,
 };
 
 static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)
-- 
2.34.1

[RFC PATCH 11/13] drm/xe: Enable deadlines on hardware fences

[Matthew Brost]

Implement the set_deadline vfunc on hardware fences, which, with GuC
submission, allows priority and frequency boosts for queues that have
fences at risk of missing a deadline.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_fence.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_hw_fence.c b/drivers/gpu/drm/xe/xe_hw_fence.c
index 8b884691718f..9452ea2be62f 100644
--- a/drivers/gpu/drm/xe/xe_hw_fence.c
+++ b/drivers/gpu/drm/xe/xe_hw_fence.c
@@ -66,6 +66,7 @@ static void hw_fence_irq_run_cb(struct irq_work *work)
 			if (dma_fence_is_signaled_locked(dma_fence)) {
 				trace_xe_hw_fence_signal(fence);
 				list_del_init(&fence->irq_link);
+				fence->q = NULL;
 				dma_fence_put(dma_fence);
 			}
 		}
@@ -93,6 +94,7 @@ void xe_hw_fence_irq_finish(struct xe_hw_fence_irq *irq)
 		spin_lock_irqsave(&irq->lock, flags);
 		list_for_each_entry_safe(fence, next, &irq->pending, irq_link) {
 			list_del_init(&fence->irq_link);
+			fence->q = NULL;
 			XE_WARN_ON(dma_fence_check_and_signal_locked(&fence->dma));
 			dma_fence_put(&fence->dma);
 		}
@@ -191,12 +193,23 @@ static void xe_hw_fence_release(struct dma_fence *dma_fence)
 	call_rcu(&dma_fence->rcu, fence_free);
 }
 
+static void xe_hw_fence_set_deadline(struct dma_fence *dma_fence,
+				     ktime_t deadline)
+{
+	struct xe_hw_fence *fence = to_xe_hw_fence(dma_fence);
+
+	guard(spinlock_irqsave)(dma_fence->lock);
+	if (fence->q)
+		fence->q->ops->set_deadline(fence->q, dma_fence, deadline);
+}
+
 static const struct dma_fence_ops xe_hw_fence_ops = {
 	.get_driver_name = xe_hw_fence_get_driver_name,
 	.get_timeline_name = xe_hw_fence_get_timeline_name,
 	.enable_signaling = xe_hw_fence_enable_signaling,
 	.signaled = xe_hw_fence_signaled,
 	.release = xe_hw_fence_release,
+	.set_deadline = xe_hw_fence_set_deadline,
 };
 
 /**
-- 
2.34.1

[RFC PATCH 12/13] drm/xe: Add CONFIG_DRM_XE_DEADLINE_WINDOW

[Matthew Brost]

Configures the deadline window. If a fence is not signaled within this
window before the set deadline, the deadline boost starts. The default
is 3 ms, but this allows OEMs to tune the deadline implementation.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/Kconfig.profile   |  6 ++++++
 drivers/gpu/drm/xe/xe_deadline_mgr.c | 10 ++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/Kconfig.profile b/drivers/gpu/drm/xe/Kconfig.profile
index 7530df998148..b17ca4c67b8a 100644
--- a/drivers/gpu/drm/xe/Kconfig.profile
+++ b/drivers/gpu/drm/xe/Kconfig.profile
@@ -53,3 +53,9 @@ config DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT
 	  to apply to applicable user. For elevated user, all above MIN
 	  and MAX values will apply when this configuration is enable to
 	  apply limitation. By default limitation is applied.
+config DRM_XE_DEADLINE_WINDOW
+	int "Default deadline window (ms)"
+	default 3 # milliseconds
+	help
+	  Configures the deadline window. If a fence is not signaled within this
+	  window before set deadline, the deadline boost starts.
diff --git a/drivers/gpu/drm/xe/xe_deadline_mgr.c b/drivers/gpu/drm/xe/xe_deadline_mgr.c
index 5159ce35fdde..80a1bb72ea56 100644
--- a/drivers/gpu/drm/xe/xe_deadline_mgr.c
+++ b/drivers/gpu/drm/xe/xe_deadline_mgr.c
@@ -11,6 +11,12 @@
 #include "xe_gt.h"
 #include "xe_hw_fence.h"
 
+#ifdef CONFIG_DRM_XE_DEADLINE_WINDOW
+#define XE_DEADLINE_WINDOW	CONFIG_DRM_XE_DEADLINE_WINDOW
+#else
+#define XE_DEADLINE_WINDOW	3
+#endif
+
 static void __xe_deadline_mgr_enter_deadline(struct xe_deadline_mgr *mgr)
 {
 	lockdep_assert_held(&mgr->lock);
@@ -96,8 +102,8 @@ static void __xe_deadline_mgr_update_deadline(struct xe_deadline_mgr *mgr)
 		hrtimer_cancel(&mgr->timer);
 
 		if (mgr->deadline != XE_DEADLINE_NONE) {
-			ktime_t deadline = ktime_sub(mgr->deadline,
-						     ms_to_ktime(3));
+			ktime_t sub = ms_to_ktime(XE_DEADLINE_WINDOW);
+			ktime_t deadline = ktime_sub(mgr->deadline, sub);
 			ktime_t now = ktime_get();
 
 			if (ktime_after(now, deadline)) {
-- 
2.34.1

[RFC PATCH 13/13] drm/xe: Add exec queue deadline trace points

[Matthew Brost]

Add exec queue deadline trace points to help debug and profile the
deadline implementation.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_submit.c |  4 ++++
 drivers/gpu/drm/xe/xe_trace.h      | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index 791c64d6397f..ab9450ca8559 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -2068,6 +2068,8 @@ static void __guc_exec_queue_process_msg_enter_deadline(struct xe_sched_msg *msg
 	if (xe_exec_queue_is_multi_queue_secondary(q))
 		q = xe_exec_queue_multi_queue_primary(q);
 
+	trace_xe_exec_queue_enter_deadline(q);
+
 	if (guc_exec_queue_allowed_to_change_state(q))
 		deadline_policies(guc, q);
 }
@@ -2081,6 +2083,8 @@ static void __guc_exec_queue_process_msg_exit_deadline(struct xe_sched_msg *msg)
 	if (xe_exec_queue_is_multi_queue_secondary(q))
 		q = xe_exec_queue_multi_queue_primary(q);
 
+	trace_xe_exec_queue_exit_deadline(q);
+
 	if (guc_exec_queue_allowed_to_change_state(q))
 		init_policies(guc, q);
 }
diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h
index 6d12fcc13f43..d40947a8e1fe 100644
--- a/drivers/gpu/drm/xe/xe_trace.h
+++ b/drivers/gpu/drm/xe/xe_trace.h
@@ -233,6 +233,16 @@ DEFINE_EVENT(xe_exec_queue, xe_exec_queue_lr_cleanup,
 	     TP_ARGS(q)
 );
 
+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_enter_deadline,
+	     TP_PROTO(struct xe_exec_queue *q),
+	     TP_ARGS(q)
+);
+
+DEFINE_EVENT(xe_exec_queue, xe_exec_queue_exit_deadline,
+	     TP_PROTO(struct xe_exec_queue *q),
+	     TP_ARGS(q)
+);
+
 DECLARE_EVENT_CLASS(xe_sched_job,
 		    TP_PROTO(struct xe_sched_job *job),
 		    TP_ARGS(job),
-- 
2.34.1

✗ CI.checkpatch: warning for Fence deadlines in Xe

[Patchwork]

== Series Details ==

Series: Fence deadlines in Xe
URL   : https://patchwork.freedesktop.org/series/159479/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99339247d1ae4378b24366da182e712bdc623311
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 57a616bdccfbb37cf2e5ee97369a498393dbf2d2
Author: Matthew Brost <matthew.brost@intel.com>
Date:   Wed Dec 24 17:17:34 2025 -0800

    drm/xe: Add exec queue deadline trace points
    
    Add exec queue deadline trace points to help debug and profile the
    deadline implementation.
    
    Signed-off-by: Matthew Brost <matthew.brost@intel.com>
+ /mt/dim checkpatch 5c680ac45628b1951d20a444f400c82242029031 drm-intel
c2c665d12514 drm/xe: Add dedicated message lock
0d853ea7942e drm/xe: Add EXEC_QUEUE_FLAG_CAP_SYS_NICE
373af0e47c0e drm/xe: Store exec queue in hardware fence
bfd1dcedf478 drm/xe: Add deadline exec queue vfuncs
8281afdd155f drm/xe: Export to_xe_hw_fence
27d2eb31dc5e drm/xe: Add deadline manager
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

-:119: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#119: FILE: drivers/gpu/drm/xe/xe_deadline_mgr.c:85:
+
+}

-:165: CHECK:LINE_SPACING: Please don't use multiple blank lines
#165: FILE: drivers/gpu/drm/xe/xe_deadline_mgr.c:131:
+
+

total: 0 errors, 1 warnings, 2 checks, 308 lines checked
482ae2e6dea1 drm/xe: Add deadline manager to user exec queues
819c1bd106be drm/xe: Stub out execlists deadline vfuncs as NOPs
a10c43abe6c5 drm/xe: Make scheduler message lock IRQ-safe
-:82: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'sched' may be better as '(sched)' to avoid precedence issues
#82: FILE: drivers/gpu/drm/xe/xe_gpu_scheduler.h:34:
+#define xe_sched_msg_lock(sched)	\
+	scoped_guard(spinlock_irqsave, &sched->msg_lock)

total: 0 errors, 0 warnings, 1 checks, 110 lines checked
91baa6abb5a6 drm/xe: Implement GuC submission backend ops for deadlines
6614fc118515 drm/xe: Enable deadlines on hardware fences
3066661b59d8 drm/xe: Add CONFIG_DRM_XE_DEADLINE_WINDOW
57a616bdccfb drm/xe: Add exec queue deadline trace points

✓ CI.KUnit: success for Fence deadlines in Xe

[Patchwork]

== Series Details ==

Series: Fence deadlines in Xe
URL   : https://patchwork.freedesktop.org/series/159479/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[01:25:21] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[01:25:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[01:25:57] Starting KUnit Kernel (1/1)...
[01:25:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[01:25:57] ================== guc_buf (11 subtests) ===================
[01:25:57] [PASSED] test_smallest
[01:25:57] [PASSED] test_largest
[01:25:57] [PASSED] test_granular
[01:25:57] [PASSED] test_unique
[01:25:57] [PASSED] test_overlap
[01:25:57] [PASSED] test_reusable
[01:25:57] [PASSED] test_too_big
[01:25:57] [PASSED] test_flush
[01:25:57] [PASSED] test_lookup
[01:25:57] [PASSED] test_data
[01:25:57] [PASSED] test_class
[01:25:57] ===================== [PASSED] guc_buf =====================
[01:25:57] =================== guc_dbm (7 subtests) ===================
[01:25:57] [PASSED] test_empty
[01:25:57] [PASSED] test_default
[01:25:57] ======================== test_size  ========================
[01:25:57] [PASSED] 4
[01:25:57] [PASSED] 8
[01:25:57] [PASSED] 32
[01:25:57] [PASSED] 256
[01:25:57] ==================== [PASSED] test_size ====================
[01:25:57] ======================= test_reuse  ========================
[01:25:57] [PASSED] 4
[01:25:57] [PASSED] 8
[01:25:57] [PASSED] 32
[01:25:57] [PASSED] 256
[01:25:57] =================== [PASSED] test_reuse ====================
[01:25:57] =================== test_range_overlap  ====================
[01:25:57] [PASSED] 4
[01:25:57] [PASSED] 8
[01:25:57] [PASSED] 32
[01:25:57] [PASSED] 256
[01:25:57] =============== [PASSED] test_range_overlap ================
[01:25:57] =================== test_range_compact  ====================
[01:25:57] [PASSED] 4
[01:25:57] [PASSED] 8
[01:25:57] [PASSED] 32
[01:25:57] [PASSED] 256
[01:25:57] =============== [PASSED] test_range_compact ================
[01:25:57] ==================== test_range_spare  =====================
[01:25:57] [PASSED] 4
[01:25:57] [PASSED] 8
[01:25:57] [PASSED] 32
[01:25:57] [PASSED] 256
[01:25:57] ================ [PASSED] test_range_spare =================
[01:25:57] ===================== [PASSED] guc_dbm =====================
[01:25:57] =================== guc_idm (6 subtests) ===================
[01:25:57] [PASSED] bad_init
[01:25:57] [PASSED] no_init
[01:25:57] [PASSED] init_fini
[01:25:57] [PASSED] check_used
[01:25:57] [PASSED] check_quota
[01:25:57] [PASSED] check_all
[01:25:57] ===================== [PASSED] guc_idm =====================
[01:25:57] ================== no_relay (3 subtests) ===================
[01:25:57] [PASSED] xe_drops_guc2pf_if_not_ready
[01:25:57] [PASSED] xe_drops_guc2vf_if_not_ready
[01:25:57] [PASSED] xe_rejects_send_if_not_ready
[01:25:57] ==================== [PASSED] no_relay =====================
[01:25:57] ================== pf_relay (14 subtests) ==================
[01:25:57] [PASSED] pf_rejects_guc2pf_too_short
[01:25:57] [PASSED] pf_rejects_guc2pf_too_long
[01:25:57] [PASSED] pf_rejects_guc2pf_no_payload
[01:25:57] [PASSED] pf_fails_no_payload
[01:25:57] [PASSED] pf_fails_bad_origin
[01:25:57] [PASSED] pf_fails_bad_type
[01:25:57] [PASSED] pf_txn_reports_error
[01:25:57] [PASSED] pf_txn_sends_pf2guc
[01:25:57] [PASSED] pf_sends_pf2guc
[01:25:57] [SKIPPED] pf_loopback_nop
[01:25:57] [SKIPPED] pf_loopback_echo
[01:25:57] [SKIPPED] pf_loopback_fail
[01:25:57] [SKIPPED] pf_loopback_busy
[01:25:57] [SKIPPED] pf_loopback_retry
[01:25:57] ==================== [PASSED] pf_relay =====================
[01:25:57] ================== vf_relay (3 subtests) ===================
[01:25:57] [PASSED] vf_rejects_guc2vf_too_short
[01:25:57] [PASSED] vf_rejects_guc2vf_too_long
[01:25:57] [PASSED] vf_rejects_guc2vf_no_payload
[01:25:57] ==================== [PASSED] vf_relay =====================
[01:25:57] ================ pf_gt_config (6 subtests) =================
[01:25:57] [PASSED] fair_contexts_1vf
[01:25:57] [PASSED] fair_doorbells_1vf
[01:25:57] [PASSED] fair_ggtt_1vf
[01:25:57] ====================== fair_contexts  ======================
[01:25:57] [PASSED] 1 VF
[01:25:57] [PASSED] 2 VFs
[01:25:57] [PASSED] 3 VFs
[01:25:57] [PASSED] 4 VFs
[01:25:57] [PASSED] 5 VFs
[01:25:57] [PASSED] 6 VFs
[01:25:57] [PASSED] 7 VFs
[01:25:57] [PASSED] 8 VFs
[01:25:57] [PASSED] 9 VFs
[01:25:57] [PASSED] 10 VFs
[01:25:57] [PASSED] 11 VFs
[01:25:57] [PASSED] 12 VFs
[01:25:57] [PASSED] 13 VFs
[01:25:57] [PASSED] 14 VFs
[01:25:57] [PASSED] 15 VFs
[01:25:57] [PASSED] 16 VFs
[01:25:57] [PASSED] 17 VFs
[01:25:57] [PASSED] 18 VFs
[01:25:57] [PASSED] 19 VFs
[01:25:57] [PASSED] 20 VFs
[01:25:57] [PASSED] 21 VFs
[01:25:57] [PASSED] 22 VFs
[01:25:57] [PASSED] 23 VFs
[01:25:57] [PASSED] 24 VFs
[01:25:57] [PASSED] 25 VFs
[01:25:57] [PASSED] 26 VFs
[01:25:57] [PASSED] 27 VFs
[01:25:57] [PASSED] 28 VFs
[01:25:57] [PASSED] 29 VFs
[01:25:57] [PASSED] 30 VFs
[01:25:57] [PASSED] 31 VFs
[01:25:57] [PASSED] 32 VFs
[01:25:57] [PASSED] 33 VFs
[01:25:57] [PASSED] 34 VFs
[01:25:57] [PASSED] 35 VFs
[01:25:57] [PASSED] 36 VFs
[01:25:57] [PASSED] 37 VFs
[01:25:57] [PASSED] 38 VFs
[01:25:57] [PASSED] 39 VFs
[01:25:57] [PASSED] 40 VFs
[01:25:57] [PASSED] 41 VFs
[01:25:57] [PASSED] 42 VFs
[01:25:57] [PASSED] 43 VFs
[01:25:57] [PASSED] 44 VFs
[01:25:57] [PASSED] 45 VFs
[01:25:57] [PASSED] 46 VFs
[01:25:57] [PASSED] 47 VFs
[01:25:57] [PASSED] 48 VFs
[01:25:57] [PASSED] 49 VFs
[01:25:57] [PASSED] 50 VFs
[01:25:57] [PASSED] 51 VFs
[01:25:57] [PASSED] 52 VFs
[01:25:57] [PASSED] 53 VFs
[01:25:57] [PASSED] 54 VFs
[01:25:57] [PASSED] 55 VFs
[01:25:57] [PASSED] 56 VFs
[01:25:57] [PASSED] 57 VFs
[01:25:57] [PASSED] 58 VFs
[01:25:57] [PASSED] 59 VFs
[01:25:57] [PASSED] 60 VFs
[01:25:57] [PASSED] 61 VFs
[01:25:57] [PASSED] 62 VFs
[01:25:57] [PASSED] 63 VFs
[01:25:57] ================== [PASSED] fair_contexts ==================
[01:25:57] ===================== fair_doorbells  ======================
[01:25:57] [PASSED] 1 VF
[01:25:57] [PASSED] 2 VFs
[01:25:57] [PASSED] 3 VFs
[01:25:57] [PASSED] 4 VFs
[01:25:57] [PASSED] 5 VFs
[01:25:57] [PASSED] 6 VFs
[01:25:57] [PASSED] 7 VFs
[01:25:57] [PASSED] 8 VFs
[01:25:57] [PASSED] 9 VFs
[01:25:57] [PASSED] 10 VFs
[01:25:57] [PASSED] 11 VFs
[01:25:57] [PASSED] 12 VFs
[01:25:57] [PASSED] 13 VFs
[01:25:57] [PASSED] 14 VFs
[01:25:57] [PASSED] 15 VFs
[01:25:57] [PASSED] 16 VFs
[01:25:57] [PASSED] 17 VFs
[01:25:57] [PASSED] 18 VFs
[01:25:57] [PASSED] 19 VFs
[01:25:57] [PASSED] 20 VFs
[01:25:57] [PASSED] 21 VFs
[01:25:57] [PASSED] 22 VFs
[01:25:57] [PASSED] 23 VFs
[01:25:57] [PASSED] 24 VFs
[01:25:57] [PASSED] 25 VFs
[01:25:57] [PASSED] 26 VFs
[01:25:57] [PASSED] 27 VFs
[01:25:57] [PASSED] 28 VFs
[01:25:57] [PASSED] 29 VFs
[01:25:57] [PASSED] 30 VFs
[01:25:57] [PASSED] 31 VFs
[01:25:57] [PASSED] 32 VFs
[01:25:57] [PASSED] 33 VFs
[01:25:57] [PASSED] 34 VFs
[01:25:57] [PASSED] 35 VFs
[01:25:57] [PASSED] 36 VFs
[01:25:57] [PASSED] 37 VFs
[01:25:57] [PASSED] 38 VFs
[01:25:57] [PASSED] 39 VFs
[01:25:57] [PASSED] 40 VFs
[01:25:57] [PASSED] 41 VFs
[01:25:57] [PASSED] 42 VFs
[01:25:57] [PASSED] 43 VFs
[01:25:57] [PASSED] 44 VFs
[01:25:57] [PASSED] 45 VFs
[01:25:57] [PASSED] 46 VFs
[01:25:57] [PASSED] 47 VFs
[01:25:57] [PASSED] 48 VFs
[01:25:57] [PASSED] 49 VFs
[01:25:57] [PASSED] 50 VFs
[01:25:57] [PASSED] 51 VFs
[01:25:57] [PASSED] 52 VFs
[01:25:57] [PASSED] 53 VFs
[01:25:57] [PASSED] 54 VFs
[01:25:57] [PASSED] 55 VFs
[01:25:57] [PASSED] 56 VFs
[01:25:57] [PASSED] 57 VFs
[01:25:57] [PASSED] 58 VFs
[01:25:57] [PASSED] 59 VFs
[01:25:57] [PASSED] 60 VFs
[01:25:57] [PASSED] 61 VFs
[01:25:57] [PASSED] 62 VFs
[01:25:57] [PASSED] 63 VFs
[01:25:57] ================= [PASSED] fair_doorbells ==================
[01:25:57] ======================== fair_ggtt  ========================
[01:25:57] [PASSED] 1 VF
[01:25:57] [PASSED] 2 VFs
[01:25:57] [PASSED] 3 VFs
[01:25:57] [PASSED] 4 VFs
[01:25:57] [PASSED] 5 VFs
[01:25:57] [PASSED] 6 VFs
[01:25:57] [PASSED] 7 VFs
[01:25:57] [PASSED] 8 VFs
[01:25:57] [PASSED] 9 VFs
[01:25:57] [PASSED] 10 VFs
[01:25:57] [PASSED] 11 VFs
[01:25:57] [PASSED] 12 VFs
[01:25:57] [PASSED] 13 VFs
[01:25:57] [PASSED] 14 VFs
[01:25:57] [PASSED] 15 VFs
[01:25:57] [PASSED] 16 VFs
[01:25:57] [PASSED] 17 VFs
[01:25:57] [PASSED] 18 VFs
[01:25:57] [PASSED] 19 VFs
[01:25:57] [PASSED] 20 VFs
[01:25:57] [PASSED] 21 VFs
[01:25:57] [PASSED] 22 VFs
[01:25:57] [PASSED] 23 VFs
[01:25:57] [PASSED] 24 VFs
[01:25:57] [PASSED] 25 VFs
[01:25:57] [PASSED] 26 VFs
[01:25:57] [PASSED] 27 VFs
[01:25:57] [PASSED] 28 VFs
[01:25:57] [PASSED] 29 VFs
[01:25:57] [PASSED] 30 VFs
[01:25:57] [PASSED] 31 VFs
[01:25:57] [PASSED] 32 VFs
[01:25:57] [PASSED] 33 VFs
[01:25:57] [PASSED] 34 VFs
[01:25:57] [PASSED] 35 VFs
[01:25:57] [PASSED] 36 VFs
[01:25:57] [PASSED] 37 VFs
[01:25:57] [PASSED] 38 VFs
[01:25:57] [PASSED] 39 VFs
[01:25:57] [PASSED] 40 VFs
[01:25:57] [PASSED] 41 VFs
[01:25:57] [PASSED] 42 VFs
[01:25:57] [PASSED] 43 VFs
[01:25:57] [PASSED] 44 VFs
[01:25:57] [PASSED] 45 VFs
[01:25:57] [PASSED] 46 VFs
[01:25:57] [PASSED] 47 VFs
[01:25:57] [PASSED] 48 VFs
[01:25:57] [PASSED] 49 VFs
[01:25:57] [PASSED] 50 VFs
[01:25:57] [PASSED] 51 VFs
[01:25:57] [PASSED] 52 VFs
[01:25:57] [PASSED] 53 VFs
[01:25:57] [PASSED] 54 VFs
[01:25:57] [PASSED] 55 VFs
[01:25:57] [PASSED] 56 VFs
[01:25:57] [PASSED] 57 VFs
[01:25:57] [PASSED] 58 VFs
[01:25:57] [PASSED] 59 VFs
[01:25:57] [PASSED] 60 VFs
[01:25:57] [PASSED] 61 VFs
[01:25:57] [PASSED] 62 VFs
[01:25:57] [PASSED] 63 VFs
[01:25:57] ==================== [PASSED] fair_ggtt ====================
[01:25:57] ================== [PASSED] pf_gt_config ===================
[01:25:57] ===================== lmtt (1 subtest) =====================
[01:25:57] ======================== test_ops  =========================
[01:25:57] [PASSED] 2-level
[01:25:57] [PASSED] multi-level
[01:25:57] ==================== [PASSED] test_ops =====================
[01:25:57] ====================== [PASSED] lmtt =======================
[01:25:57] ================= pf_service (11 subtests) =================
[01:25:57] [PASSED] pf_negotiate_any
[01:25:57] [PASSED] pf_negotiate_base_match
[01:25:57] [PASSED] pf_negotiate_base_newer
[01:25:57] [PASSED] pf_negotiate_base_next
[01:25:57] [SKIPPED] pf_negotiate_base_older
[01:25:57] [PASSED] pf_negotiate_base_prev
[01:25:57] [PASSED] pf_negotiate_latest_match
[01:25:57] [PASSED] pf_negotiate_latest_newer
[01:25:57] [PASSED] pf_negotiate_latest_next
[01:25:57] [SKIPPED] pf_negotiate_latest_older
[01:25:57] [SKIPPED] pf_negotiate_latest_prev
[01:25:57] =================== [PASSED] pf_service ====================
[01:25:57] ================= xe_guc_g2g (2 subtests) ==================
[01:25:57] ============== xe_live_guc_g2g_kunit_default  ==============
[01:25:57] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[01:25:57] ============== xe_live_guc_g2g_kunit_allmem  ===============
[01:25:57] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[01:25:57] =================== [SKIPPED] xe_guc_g2g ===================
[01:25:57] =================== xe_mocs (2 subtests) ===================
[01:25:57] ================ xe_live_mocs_kernel_kunit  ================
[01:25:57] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[01:25:57] ================ xe_live_mocs_reset_kunit  =================
[01:25:57] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[01:25:57] ==================== [SKIPPED] xe_mocs =====================
[01:25:57] ================= xe_migrate (2 subtests) ==================
[01:25:57] ================= xe_migrate_sanity_kunit  =================
[01:25:57] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[01:25:57] ================== xe_validate_ccs_kunit  ==================
[01:25:57] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[01:25:57] =================== [SKIPPED] xe_migrate ===================
[01:25:57] ================== xe_dma_buf (1 subtest) ==================
[01:25:57] ==================== xe_dma_buf_kunit  =====================
[01:25:57] ================ [SKIPPED] xe_dma_buf_kunit ================
[01:25:57] =================== [SKIPPED] xe_dma_buf ===================
[01:25:57] ================= xe_bo_shrink (1 subtest) =================
[01:25:57] =================== xe_bo_shrink_kunit  ====================
[01:25:57] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[01:25:57] ================== [SKIPPED] xe_bo_shrink ==================
[01:25:57] ==================== xe_bo (2 subtests) ====================
[01:25:57] ================== xe_ccs_migrate_kunit  ===================
[01:25:57] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[01:25:57] ==================== xe_bo_evict_kunit  ====================
[01:25:57] =============== [SKIPPED] xe_bo_evict_kunit ================
[01:25:57] ===================== [SKIPPED] xe_bo ======================
[01:25:57] ==================== args (13 subtests) ====================
[01:25:57] [PASSED] count_args_test
[01:25:57] [PASSED] call_args_example
[01:25:57] [PASSED] call_args_test
[01:25:57] [PASSED] drop_first_arg_example
[01:25:57] [PASSED] drop_first_arg_test
[01:25:57] [PASSED] first_arg_example
[01:25:57] [PASSED] first_arg_test
[01:25:57] [PASSED] last_arg_example
[01:25:57] [PASSED] last_arg_test
[01:25:57] [PASSED] pick_arg_example
[01:25:57] [PASSED] if_args_example
[01:25:57] [PASSED] if_args_test
[01:25:57] [PASSED] sep_comma_example
[01:25:57] ====================== [PASSED] args =======================
[01:25:57] =================== xe_pci (3 subtests) ====================
[01:25:57] ==================== check_graphics_ip  ====================
[01:25:57] [PASSED] 12.00 Xe_LP
[01:25:57] [PASSED] 12.10 Xe_LP+
[01:25:57] [PASSED] 12.55 Xe_HPG
[01:25:57] [PASSED] 12.60 Xe_HPC
[01:25:57] [PASSED] 12.70 Xe_LPG
[01:25:57] [PASSED] 12.71 Xe_LPG
[01:25:57] [PASSED] 12.74 Xe_LPG+
[01:25:57] [PASSED] 20.01 Xe2_HPG
[01:25:57] [PASSED] 20.02 Xe2_HPG
[01:25:57] [PASSED] 20.04 Xe2_LPG
[01:25:57] [PASSED] 30.00 Xe3_LPG
[01:25:57] [PASSED] 30.01 Xe3_LPG
[01:25:57] [PASSED] 30.03 Xe3_LPG
[01:25:57] [PASSED] 30.04 Xe3_LPG
[01:25:57] [PASSED] 30.05 Xe3_LPG
[01:25:57] [PASSED] 35.11 Xe3p_XPC
[01:25:57] ================ [PASSED] check_graphics_ip ================
[01:25:57] ===================== check_media_ip  ======================
[01:25:57] [PASSED] 12.00 Xe_M
[01:25:57] [PASSED] 12.55 Xe_HPM
[01:25:57] [PASSED] 13.00 Xe_LPM+
[01:25:57] [PASSED] 13.01 Xe2_HPM
[01:25:57] [PASSED] 20.00 Xe2_LPM
[01:25:57] [PASSED] 30.00 Xe3_LPM
[01:25:57] [PASSED] 30.02 Xe3_LPM
[01:25:57] [PASSED] 35.00 Xe3p_LPM
[01:25:57] [PASSED] 35.03 Xe3p_HPM
[01:25:57] ================= [PASSED] check_media_ip ==================
[01:25:57] =================== check_platform_desc  ===================
[01:25:57] [PASSED] 0x9A60 (TIGERLAKE)
[01:25:57] [PASSED] 0x9A68 (TIGERLAKE)
[01:25:57] [PASSED] 0x9A70 (TIGERLAKE)
[01:25:57] [PASSED] 0x9A40 (TIGERLAKE)
[01:25:57] [PASSED] 0x9A49 (TIGERLAKE)
[01:25:57] [PASSED] 0x9A59 (TIGERLAKE)
[01:25:57] [PASSED] 0x9A78 (TIGERLAKE)
[01:25:57] [PASSED] 0x9AC0 (TIGERLAKE)
[01:25:57] [PASSED] 0x9AC9 (TIGERLAKE)
[01:25:57] [PASSED] 0x9AD9 (TIGERLAKE)
[01:25:57] [PASSED] 0x9AF8 (TIGERLAKE)
[01:25:57] [PASSED] 0x4C80 (ROCKETLAKE)
[01:25:57] [PASSED] 0x4C8A (ROCKETLAKE)
[01:25:57] [PASSED] 0x4C8B (ROCKETLAKE)
[01:25:57] [PASSED] 0x4C8C (ROCKETLAKE)
[01:25:57] [PASSED] 0x4C90 (ROCKETLAKE)
[01:25:57] [PASSED] 0x4C9A (ROCKETLAKE)
[01:25:57] [PASSED] 0x4680 (ALDERLAKE_S)
[01:25:57] [PASSED] 0x4682 (ALDERLAKE_S)
[01:25:57] [PASSED] 0x4688 (ALDERLAKE_S)
[01:25:57] [PASSED] 0x468A (ALDERLAKE_S)
[01:25:57] [PASSED] 0x468B (ALDERLAKE_S)
[01:25:57] [PASSED] 0x4690 (ALDERLAKE_S)
[01:25:57] [PASSED] 0x4692 (ALDERLAKE_S)
[01:25:57] [PASSED] 0x4693 (ALDERLAKE_S)
[01:25:57] [PASSED] 0x46A0 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46A1 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46A2 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46A3 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46A6 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46A8 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46AA (ALDERLAKE_P)
[01:25:57] [PASSED] 0x462A (ALDERLAKE_P)
[01:25:57] [PASSED] 0x4626 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[01:25:57] [PASSED] 0x46B0 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46B1 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46B2 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46B3 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46C0 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46C1 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46C2 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46C3 (ALDERLAKE_P)
[01:25:57] [PASSED] 0x46D0 (ALDERLAKE_N)
[01:25:57] [PASSED] 0x46D1 (ALDERLAKE_N)
[01:25:57] [PASSED] 0x46D2 (ALDERLAKE_N)
[01:25:57] [PASSED] 0x46D3 (ALDERLAKE_N)
[01:25:57] [PASSED] 0x46D4 (ALDERLAKE_N)
[01:25:57] [PASSED] 0xA721 (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7A1 (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7A9 (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7AC (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7AD (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA720 (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7A0 (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7A8 (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7AA (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA7AB (ALDERLAKE_P)
[01:25:57] [PASSED] 0xA780 (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA781 (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA782 (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA783 (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA788 (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA789 (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA78A (ALDERLAKE_S)
[01:25:57] [PASSED] 0xA78B (ALDERLAKE_S)
[01:25:57] [PASSED] 0x4905 (DG1)
[01:25:57] [PASSED] 0x4906 (DG1)
[01:25:57] [PASSED] 0x4907 (DG1)
[01:25:57] [PASSED] 0x4908 (DG1)
[01:25:57] [PASSED] 0x4909 (DG1)
[01:25:57] [PASSED] 0x56C0 (DG2)
[01:25:57] [PASSED] 0x56C2 (DG2)
[01:25:57] [PASSED] 0x56C1 (DG2)
[01:25:57] [PASSED] 0x7D51 (METEORLAKE)
[01:25:57] [PASSED] 0x7DD1 (METEORLAKE)
[01:25:57] [PASSED] 0x7D41 (METEORLAKE)
[01:25:57] [PASSED] 0x7D67 (METEORLAKE)
[01:25:57] [PASSED] 0xB640 (METEORLAKE)
[01:25:57] [PASSED] 0x56A0 (DG2)
[01:25:57] [PASSED] 0x56A1 (DG2)
[01:25:57] [PASSED] 0x56A2 (DG2)
[01:25:57] [PASSED] 0x56BE (DG2)
[01:25:57] [PASSED] 0x56BF (DG2)
[01:25:57] [PASSED] 0x5690 (DG2)
[01:25:57] [PASSED] 0x5691 (DG2)
[01:25:57] [PASSED] 0x5692 (DG2)
[01:25:57] [PASSED] 0x56A5 (DG2)
[01:25:57] [PASSED] 0x56A6 (DG2)
[01:25:57] [PASSED] 0x56B0 (DG2)
[01:25:57] [PASSED] 0x56B1 (DG2)
[01:25:57] [PASSED] 0x56BA (DG2)
[01:25:57] [PASSED] 0x56BB (DG2)
[01:25:57] [PASSED] 0x56BC (DG2)
[01:25:57] [PASSED] 0x56BD (DG2)
[01:25:57] [PASSED] 0x5693 (DG2)
[01:25:57] [PASSED] 0x5694 (DG2)
[01:25:57] [PASSED] 0x5695 (DG2)
[01:25:57] [PASSED] 0x56A3 (DG2)
[01:25:57] [PASSED] 0x56A4 (DG2)
[01:25:57] [PASSED] 0x56B2 (DG2)
[01:25:57] [PASSED] 0x56B3 (DG2)
[01:25:57] [PASSED] 0x5696 (DG2)
[01:25:57] [PASSED] 0x5697 (DG2)
[01:25:57] [PASSED] 0xB69 (PVC)
[01:25:57] [PASSED] 0xB6E (PVC)
[01:25:57] [PASSED] 0xBD4 (PVC)
[01:25:57] [PASSED] 0xBD5 (PVC)
[01:25:57] [PASSED] 0xBD6 (PVC)
[01:25:57] [PASSED] 0xBD7 (PVC)
[01:25:57] [PASSED] 0xBD8 (PVC)
[01:25:57] [PASSED] 0xBD9 (PVC)
[01:25:57] [PASSED] 0xBDA (PVC)
[01:25:57] [PASSED] 0xBDB (PVC)
[01:25:57] [PASSED] 0xBE0 (PVC)
[01:25:57] [PASSED] 0xBE1 (PVC)
[01:25:57] [PASSED] 0xBE5 (PVC)
[01:25:57] [PASSED] 0x7D40 (METEORLAKE)
[01:25:57] [PASSED] 0x7D45 (METEORLAKE)
[01:25:57] [PASSED] 0x7D55 (METEORLAKE)
[01:25:57] [PASSED] 0x7D60 (METEORLAKE)
[01:25:57] [PASSED] 0x7DD5 (METEORLAKE)
[01:25:57] [PASSED] 0x6420 (LUNARLAKE)
[01:25:57] [PASSED] 0x64A0 (LUNARLAKE)
[01:25:57] [PASSED] 0x64B0 (LUNARLAKE)
[01:25:57] [PASSED] 0xE202 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE209 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE20B (BATTLEMAGE)
[01:25:57] [PASSED] 0xE20C (BATTLEMAGE)
[01:25:57] [PASSED] 0xE20D (BATTLEMAGE)
[01:25:57] [PASSED] 0xE210 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE211 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE212 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE216 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE220 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE221 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE222 (BATTLEMAGE)
[01:25:57] [PASSED] 0xE223 (BATTLEMAGE)
[01:25:57] [PASSED] 0xB080 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB081 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB082 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB083 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB084 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB085 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB086 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB087 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB08F (PANTHERLAKE)
[01:25:57] [PASSED] 0xB090 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB0A0 (PANTHERLAKE)
[01:25:57] [PASSED] 0xB0B0 (PANTHERLAKE)
[01:25:57] [PASSED] 0xFD80 (PANTHERLAKE)
[01:25:57] [PASSED] 0xFD81 (PANTHERLAKE)
[01:25:57] [PASSED] 0xD740 (NOVALAKE_S)
[01:25:57] [PASSED] 0xD741 (NOVALAKE_S)
[01:25:57] [PASSED] 0xD742 (NOVALAKE_S)
[01:25:57] [PASSED] 0xD743 (NOVALAKE_S)
[01:25:57] [PASSED] 0xD744 (NOVALAKE_S)
[01:25:57] [PASSED] 0xD745 (NOVALAKE_S)
[01:25:57] [PASSED] 0x674C (CRESCENTISLAND)
[01:25:57] =============== [PASSED] check_platform_desc ===============
[01:25:57] ===================== [PASSED] xe_pci ======================
[01:25:57] =================== xe_rtp (2 subtests) ====================
[01:25:57] =============== xe_rtp_process_to_sr_tests  ================
[01:25:57] [PASSED] coalesce-same-reg
[01:25:57] [PASSED] no-match-no-add
[01:25:57] [PASSED] match-or
[01:25:57] [PASSED] match-or-xfail
[01:25:57] [PASSED] no-match-no-add-multiple-rules
[01:25:57] [PASSED] two-regs-two-entries
[01:25:57] [PASSED] clr-one-set-other
[01:25:57] [PASSED] set-field
[01:25:57] [PASSED] conflict-duplicate
[01:25:57] [PASSED] conflict-not-disjoint
[01:25:57] [PASSED] conflict-reg-type
[01:25:57] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[01:25:57] ================== xe_rtp_process_tests  ===================
[01:25:57] [PASSED] active1
[01:25:57] [PASSED] active2
[01:25:57] [PASSED] active-inactive
[01:25:57] [PASSED] inactive-active
[01:25:57] [PASSED] inactive-1st_or_active-inactive
[01:25:57] [PASSED] inactive-2nd_or_active-inactive
[01:25:57] [PASSED] inactive-last_or_active-inactive
[01:25:57] [PASSED] inactive-no_or_active-inactive
[01:25:57] ============== [PASSED] xe_rtp_process_tests ===============
[01:25:57] ===================== [PASSED] xe_rtp ======================
[01:25:57] ==================== xe_wa (1 subtest) =====================
[01:25:57] ======================== xe_wa_gt  =========================
[01:25:57] [PASSED] TIGERLAKE B0
[01:25:57] [PASSED] DG1 A0
[01:25:57] [PASSED] DG1 B0
[01:25:57] [PASSED] ALDERLAKE_S A0
[01:25:57] [PASSED] ALDERLAKE_S B0
[01:25:57] [PASSED] ALDERLAKE_S C0
[01:25:57] [PASSED] ALDERLAKE_S D0
[01:25:57] [PASSED] ALDERLAKE_P A0
[01:25:57] [PASSED] ALDERLAKE_P B0
[01:25:57] [PASSED] ALDERLAKE_P C0
[01:25:57] [PASSED] ALDERLAKE_S RPLS D0
[01:25:57] [PASSED] ALDERLAKE_P RPLU E0
[01:25:57] [PASSED] DG2 G10 C0
[01:25:57] [PASSED] DG2 G11 B1
[01:25:57] [PASSED] DG2 G12 A1
[01:25:57] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[01:25:57] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[01:25:57] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[01:25:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[01:25:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[01:25:57] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[01:25:57] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[01:25:57] ==================== [PASSED] xe_wa_gt =====================
[01:25:57] ====================== [PASSED] xe_wa ======================
[01:25:57] ============================================================
[01:25:57] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[01:25:57] Elapsed time: 36.285s total, 4.227s configuring, 31.591s building, 0.457s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[01:25:57] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[01:25:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[01:26:24] Starting KUnit Kernel (1/1)...
[01:26:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[01:26:24] ============ drm_test_pick_cmdline (2 subtests) ============
[01:26:24] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[01:26:24] =============== drm_test_pick_cmdline_named  ===============
[01:26:24] [PASSED] NTSC
[01:26:24] [PASSED] NTSC-J
[01:26:24] [PASSED] PAL
[01:26:24] [PASSED] PAL-M
[01:26:24] =========== [PASSED] drm_test_pick_cmdline_named ===========
[01:26:24] ============== [PASSED] drm_test_pick_cmdline ==============
[01:26:24] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[01:26:24] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[01:26:24] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[01:26:24] =========== drm_validate_clone_mode (2 subtests) ===========
[01:26:24] ============== drm_test_check_in_clone_mode  ===============
[01:26:24] [PASSED] in_clone_mode
[01:26:24] [PASSED] not_in_clone_mode
[01:26:24] ========== [PASSED] drm_test_check_in_clone_mode ===========
[01:26:24] =============== drm_test_check_valid_clones  ===============
[01:26:24] [PASSED] not_in_clone_mode
[01:26:24] [PASSED] valid_clone
[01:26:24] [PASSED] invalid_clone
[01:26:24] =========== [PASSED] drm_test_check_valid_clones ===========
[01:26:24] ============= [PASSED] drm_validate_clone_mode =============
[01:26:24] ============= drm_validate_modeset (1 subtest) =============
[01:26:24] [PASSED] drm_test_check_connector_changed_modeset
[01:26:24] ============== [PASSED] drm_validate_modeset ===============
[01:26:24] ====== drm_test_bridge_get_current_state (2 subtests) ======
[01:26:24] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[01:26:24] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[01:26:24] ======== [PASSED] drm_test_bridge_get_current_state ========
[01:26:24] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[01:26:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[01:26:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[01:26:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[01:26:24] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[01:26:24] ============== drm_bridge_alloc (2 subtests) ===============
[01:26:24] [PASSED] drm_test_drm_bridge_alloc_basic
[01:26:24] [PASSED] drm_test_drm_bridge_alloc_get_put
[01:26:24] ================ [PASSED] drm_bridge_alloc =================
[01:26:24] ================== drm_buddy (8 subtests) ==================
[01:26:24] [PASSED] drm_test_buddy_alloc_limit
[01:26:24] [PASSED] drm_test_buddy_alloc_optimistic
[01:26:24] [PASSED] drm_test_buddy_alloc_pessimistic
[01:26:24] [PASSED] drm_test_buddy_alloc_pathological
[01:26:24] [PASSED] drm_test_buddy_alloc_contiguous
[01:26:24] [PASSED] drm_test_buddy_alloc_clear
[01:26:24] [PASSED] drm_test_buddy_alloc_range_bias
[01:26:25] [PASSED] drm_test_buddy_fragmentation_performance
[01:26:25] ==================== [PASSED] drm_buddy ====================
[01:26:25] ============= drm_cmdline_parser (40 subtests) =============
[01:26:25] [PASSED] drm_test_cmdline_force_d_only
[01:26:25] [PASSED] drm_test_cmdline_force_D_only_dvi
[01:26:25] [PASSED] drm_test_cmdline_force_D_only_hdmi
[01:26:25] [PASSED] drm_test_cmdline_force_D_only_not_digital
[01:26:25] [PASSED] drm_test_cmdline_force_e_only
[01:26:25] [PASSED] drm_test_cmdline_res
[01:26:25] [PASSED] drm_test_cmdline_res_vesa
[01:26:25] [PASSED] drm_test_cmdline_res_vesa_rblank
[01:26:25] [PASSED] drm_test_cmdline_res_rblank
[01:26:25] [PASSED] drm_test_cmdline_res_bpp
[01:26:25] [PASSED] drm_test_cmdline_res_refresh
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[01:26:25] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[01:26:25] [PASSED] drm_test_cmdline_res_margins_force_on
[01:26:25] [PASSED] drm_test_cmdline_res_vesa_margins
[01:26:25] [PASSED] drm_test_cmdline_name
[01:26:25] [PASSED] drm_test_cmdline_name_bpp
[01:26:25] [PASSED] drm_test_cmdline_name_option
[01:26:25] [PASSED] drm_test_cmdline_name_bpp_option
[01:26:25] [PASSED] drm_test_cmdline_rotate_0
[01:26:25] [PASSED] drm_test_cmdline_rotate_90
[01:26:25] [PASSED] drm_test_cmdline_rotate_180
[01:26:25] [PASSED] drm_test_cmdline_rotate_270
[01:26:25] [PASSED] drm_test_cmdline_hmirror
[01:26:25] [PASSED] drm_test_cmdline_vmirror
[01:26:25] [PASSED] drm_test_cmdline_margin_options
[01:26:25] [PASSED] drm_test_cmdline_multiple_options
[01:26:25] [PASSED] drm_test_cmdline_bpp_extra_and_option
[01:26:25] [PASSED] drm_test_cmdline_extra_and_option
[01:26:25] [PASSED] drm_test_cmdline_freestanding_options
[01:26:25] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[01:26:25] [PASSED] drm_test_cmdline_panel_orientation
[01:26:25] ================ drm_test_cmdline_invalid  =================
[01:26:25] [PASSED] margin_only
[01:26:25] [PASSED] interlace_only
[01:26:25] [PASSED] res_missing_x
[01:26:25] [PASSED] res_missing_y
[01:26:25] [PASSED] res_bad_y
[01:26:25] [PASSED] res_missing_y_bpp
[01:26:25] [PASSED] res_bad_bpp
[01:26:25] [PASSED] res_bad_refresh
[01:26:25] [PASSED] res_bpp_refresh_force_on_off
[01:26:25] [PASSED] res_invalid_mode
[01:26:25] [PASSED] res_bpp_wrong_place_mode
[01:26:25] [PASSED] name_bpp_refresh
[01:26:25] [PASSED] name_refresh
[01:26:25] [PASSED] name_refresh_wrong_mode
[01:26:25] [PASSED] name_refresh_invalid_mode
[01:26:25] [PASSED] rotate_multiple
[01:26:25] [PASSED] rotate_invalid_val
[01:26:25] [PASSED] rotate_truncated
[01:26:25] [PASSED] invalid_option
[01:26:25] [PASSED] invalid_tv_option
[01:26:25] [PASSED] truncated_tv_option
[01:26:25] ============ [PASSED] drm_test_cmdline_invalid =============
[01:26:25] =============== drm_test_cmdline_tv_options  ===============
[01:26:25] [PASSED] NTSC
[01:26:25] [PASSED] NTSC_443
[01:26:25] [PASSED] NTSC_J
[01:26:25] [PASSED] PAL
[01:26:25] [PASSED] PAL_M
[01:26:25] [PASSED] PAL_N
[01:26:25] [PASSED] SECAM
[01:26:25] [PASSED] MONO_525
[01:26:25] [PASSED] MONO_625
[01:26:25] =========== [PASSED] drm_test_cmdline_tv_options ===========
[01:26:25] =============== [PASSED] drm_cmdline_parser ================
[01:26:25] ========== drmm_connector_hdmi_init (20 subtests) ==========
[01:26:25] [PASSED] drm_test_connector_hdmi_init_valid
[01:26:25] [PASSED] drm_test_connector_hdmi_init_bpc_8
[01:26:25] [PASSED] drm_test_connector_hdmi_init_bpc_10
[01:26:25] [PASSED] drm_test_connector_hdmi_init_bpc_12
[01:26:25] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[01:26:25] [PASSED] drm_test_connector_hdmi_init_bpc_null
[01:26:25] [PASSED] drm_test_connector_hdmi_init_formats_empty
[01:26:25] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[01:26:25] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[01:26:25] [PASSED] supported_formats=0x9 yuv420_allowed=1
[01:26:25] [PASSED] supported_formats=0x9 yuv420_allowed=0
[01:26:25] [PASSED] supported_formats=0x3 yuv420_allowed=1
[01:26:25] [PASSED] supported_formats=0x3 yuv420_allowed=0
[01:26:25] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[01:26:25] [PASSED] drm_test_connector_hdmi_init_null_ddc
[01:26:25] [PASSED] drm_test_connector_hdmi_init_null_product
[01:26:25] [PASSED] drm_test_connector_hdmi_init_null_vendor
[01:26:25] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[01:26:25] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[01:26:25] [PASSED] drm_test_connector_hdmi_init_product_valid
[01:26:25] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[01:26:25] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[01:26:25] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[01:26:25] ========= drm_test_connector_hdmi_init_type_valid  =========
[01:26:25] [PASSED] HDMI-A
[01:26:25] [PASSED] HDMI-B
[01:26:25] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[01:26:25] ======== drm_test_connector_hdmi_init_type_invalid  ========
[01:26:25] [PASSED] Unknown
[01:26:25] [PASSED] VGA
[01:26:25] [PASSED] DVI-I
[01:26:25] [PASSED] DVI-D
[01:26:25] [PASSED] DVI-A
[01:26:25] [PASSED] Composite
[01:26:25] [PASSED] SVIDEO
[01:26:25] [PASSED] LVDS
[01:26:25] [PASSED] Component
[01:26:25] [PASSED] DIN
[01:26:25] [PASSED] DP
[01:26:25] [PASSED] TV
[01:26:25] [PASSED] eDP
[01:26:25] [PASSED] Virtual
[01:26:25] [PASSED] DSI
[01:26:25] [PASSED] DPI
[01:26:25] [PASSED] Writeback
[01:26:25] [PASSED] SPI
[01:26:25] [PASSED] USB
[01:26:25] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[01:26:25] ============ [PASSED] drmm_connector_hdmi_init =============
[01:26:25] ============= drmm_connector_init (3 subtests) =============
[01:26:25] [PASSED] drm_test_drmm_connector_init
[01:26:25] [PASSED] drm_test_drmm_connector_init_null_ddc
[01:26:25] ========= drm_test_drmm_connector_init_type_valid  =========
[01:26:25] [PASSED] Unknown
[01:26:25] [PASSED] VGA
[01:26:25] [PASSED] DVI-I
[01:26:25] [PASSED] DVI-D
[01:26:25] [PASSED] DVI-A
[01:26:25] [PASSED] Composite
[01:26:25] [PASSED] SVIDEO
[01:26:25] [PASSED] LVDS
[01:26:25] [PASSED] Component
[01:26:25] [PASSED] DIN
[01:26:25] [PASSED] DP
[01:26:25] [PASSED] HDMI-A
[01:26:25] [PASSED] HDMI-B
[01:26:25] [PASSED] TV
[01:26:25] [PASSED] eDP
[01:26:25] [PASSED] Virtual
[01:26:25] [PASSED] DSI
[01:26:25] [PASSED] DPI
[01:26:25] [PASSED] Writeback
[01:26:25] [PASSED] SPI
[01:26:25] [PASSED] USB
[01:26:25] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[01:26:25] =============== [PASSED] drmm_connector_init ===============
[01:26:25] ========= drm_connector_dynamic_init (6 subtests) ==========
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_init
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_init_properties
[01:26:25] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[01:26:25] [PASSED] Unknown
[01:26:25] [PASSED] VGA
[01:26:25] [PASSED] DVI-I
[01:26:25] [PASSED] DVI-D
[01:26:25] [PASSED] DVI-A
[01:26:25] [PASSED] Composite
[01:26:25] [PASSED] SVIDEO
[01:26:25] [PASSED] LVDS
[01:26:25] [PASSED] Component
[01:26:25] [PASSED] DIN
[01:26:25] [PASSED] DP
[01:26:25] [PASSED] HDMI-A
[01:26:25] [PASSED] HDMI-B
[01:26:25] [PASSED] TV
[01:26:25] [PASSED] eDP
[01:26:25] [PASSED] Virtual
[01:26:25] [PASSED] DSI
[01:26:25] [PASSED] DPI
[01:26:25] [PASSED] Writeback
[01:26:25] [PASSED] SPI
[01:26:25] [PASSED] USB
[01:26:25] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[01:26:25] ======== drm_test_drm_connector_dynamic_init_name  =========
[01:26:25] [PASSED] Unknown
[01:26:25] [PASSED] VGA
[01:26:25] [PASSED] DVI-I
[01:26:25] [PASSED] DVI-D
[01:26:25] [PASSED] DVI-A
[01:26:25] [PASSED] Composite
[01:26:25] [PASSED] SVIDEO
[01:26:25] [PASSED] LVDS
[01:26:25] [PASSED] Component
[01:26:25] [PASSED] DIN
[01:26:25] [PASSED] DP
[01:26:25] [PASSED] HDMI-A
[01:26:25] [PASSED] HDMI-B
[01:26:25] [PASSED] TV
[01:26:25] [PASSED] eDP
[01:26:25] [PASSED] Virtual
[01:26:25] [PASSED] DSI
[01:26:25] [PASSED] DPI
[01:26:25] [PASSED] Writeback
[01:26:25] [PASSED] SPI
[01:26:25] [PASSED] USB
[01:26:25] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[01:26:25] =========== [PASSED] drm_connector_dynamic_init ============
[01:26:25] ==== drm_connector_dynamic_register_early (4 subtests) =====
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[01:26:25] ====== [PASSED] drm_connector_dynamic_register_early =======
[01:26:25] ======= drm_connector_dynamic_register (7 subtests) ========
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[01:26:25] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[01:26:25] ========= [PASSED] drm_connector_dynamic_register ==========
[01:26:25] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[01:26:25] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[01:26:25] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[01:26:25] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[01:26:25] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[01:26:25] ========== drm_test_get_tv_mode_from_name_valid  ===========
[01:26:25] [PASSED] NTSC
[01:26:25] [PASSED] NTSC-443
[01:26:25] [PASSED] NTSC-J
[01:26:25] [PASSED] PAL
[01:26:25] [PASSED] PAL-M
[01:26:25] [PASSED] PAL-N
[01:26:25] [PASSED] SECAM
[01:26:25] [PASSED] Mono
[01:26:25] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[01:26:25] [PASSED] drm_test_get_tv_mode_from_name_truncated
[01:26:25] ============ [PASSED] drm_get_tv_mode_from_name ============
[01:26:25] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[01:26:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[01:26:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[01:26:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[01:26:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[01:26:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[01:26:25] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[01:26:25] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[01:26:25] [PASSED] VIC 96
[01:26:25] [PASSED] VIC 97
[01:26:25] [PASSED] VIC 101
[01:26:25] [PASSED] VIC 102
[01:26:25] [PASSED] VIC 106
[01:26:25] [PASSED] VIC 107
[01:26:25] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[01:26:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[01:26:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[01:26:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[01:26:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[01:26:25] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[01:26:25] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[01:26:25] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[01:26:25] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[01:26:25] [PASSED] Automatic
[01:26:25] [PASSED] Full
[01:26:25] [PASSED] Limited 16:235
[01:26:25] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[01:26:25] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[01:26:25] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[01:26:25] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[01:26:25] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[01:26:25] [PASSED] RGB
[01:26:25] [PASSED] YUV 4:2:0
[01:26:25] [PASSED] YUV 4:2:2
[01:26:25] [PASSED] YUV 4:4:4
[01:26:25] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[01:26:25] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[01:26:25] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[01:26:25] ============= drm_damage_helper (21 subtests) ==============
[01:26:25] [PASSED] drm_test_damage_iter_no_damage
[01:26:25] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[01:26:25] [PASSED] drm_test_damage_iter_no_damage_src_moved
[01:26:25] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[01:26:25] [PASSED] drm_test_damage_iter_no_damage_not_visible
[01:26:25] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[01:26:25] [PASSED] drm_test_damage_iter_no_damage_no_fb
[01:26:25] [PASSED] drm_test_damage_iter_simple_damage
[01:26:25] [PASSED] drm_test_damage_iter_single_damage
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_outside_src
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_src_moved
[01:26:25] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[01:26:25] [PASSED] drm_test_damage_iter_damage
[01:26:25] [PASSED] drm_test_damage_iter_damage_one_intersect
[01:26:25] [PASSED] drm_test_damage_iter_damage_one_outside
[01:26:25] [PASSED] drm_test_damage_iter_damage_src_moved
[01:26:25] [PASSED] drm_test_damage_iter_damage_not_visible
[01:26:25] ================ [PASSED] drm_damage_helper ================
[01:26:25] ============== drm_dp_mst_helper (3 subtests) ==============
[01:26:25] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[01:26:25] [PASSED] Clock 154000 BPP 30 DSC disabled
[01:26:25] [PASSED] Clock 234000 BPP 30 DSC disabled
[01:26:25] [PASSED] Clock 297000 BPP 24 DSC disabled
[01:26:25] [PASSED] Clock 332880 BPP 24 DSC enabled
[01:26:25] [PASSED] Clock 324540 BPP 24 DSC enabled
[01:26:25] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[01:26:25] ============== drm_test_dp_mst_calc_pbn_div  ===============
[01:26:25] [PASSED] Link rate 2000000 lane count 4
[01:26:25] [PASSED] Link rate 2000000 lane count 2
[01:26:25] [PASSED] Link rate 2000000 lane count 1
[01:26:25] [PASSED] Link rate 1350000 lane count 4
[01:26:25] [PASSED] Link rate 1350000 lane count 2
[01:26:25] [PASSED] Link rate 1350000 lane count 1
[01:26:25] [PASSED] Link rate 1000000 lane count 4
[01:26:25] [PASSED] Link rate 1000000 lane count 2
[01:26:25] [PASSED] Link rate 1000000 lane count 1
[01:26:25] [PASSED] Link rate 810000 lane count 4
[01:26:25] [PASSED] Link rate 810000 lane count 2
[01:26:25] [PASSED] Link rate 810000 lane count 1
[01:26:25] [PASSED] Link rate 540000 lane count 4
[01:26:25] [PASSED] Link rate 540000 lane count 2
[01:26:25] [PASSED] Link rate 540000 lane count 1
[01:26:25] [PASSED] Link rate 270000 lane count 4
[01:26:25] [PASSED] Link rate 270000 lane count 2
[01:26:25] [PASSED] Link rate 270000 lane count 1
[01:26:25] [PASSED] Link rate 162000 lane count 4
[01:26:25] [PASSED] Link rate 162000 lane count 2
[01:26:25] [PASSED] Link rate 162000 lane count 1
[01:26:25] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[01:26:25] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[01:26:25] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[01:26:25] [PASSED] DP_POWER_UP_PHY with port number
[01:26:25] [PASSED] DP_POWER_DOWN_PHY with port number
[01:26:25] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[01:26:25] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[01:26:25] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[01:26:25] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[01:26:25] [PASSED] DP_QUERY_PAYLOAD with port number
[01:26:25] [PASSED] DP_QUERY_PAYLOAD with VCPI
[01:26:25] [PASSED] DP_REMOTE_DPCD_READ with port number
[01:26:25] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[01:26:25] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[01:26:25] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[01:26:25] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[01:26:25] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[01:26:25] [PASSED] DP_REMOTE_I2C_READ with port number
[01:26:25] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[01:26:25] [PASSED] DP_REMOTE_I2C_READ with transactions array
[01:26:25] [PASSED] DP_REMOTE_I2C_WRITE with port number
[01:26:25] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[01:26:25] [PASSED] DP_REMOTE_I2C_WRITE with data array
[01:26:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[01:26:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[01:26:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[01:26:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[01:26:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[01:26:25] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[01:26:25] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[01:26:25] ================ [PASSED] drm_dp_mst_helper ================
[01:26:25] ================== drm_exec (7 subtests) ===================
[01:26:25] [PASSED] sanitycheck
[01:26:25] [PASSED] test_lock
[01:26:25] [PASSED] test_lock_unlock
[01:26:25] [PASSED] test_duplicates
[01:26:25] [PASSED] test_prepare
[01:26:25] [PASSED] test_prepare_array
[01:26:25] [PASSED] test_multiple_loops
[01:26:25] ==================== [PASSED] drm_exec =====================
[01:26:25] =========== drm_format_helper_test (17 subtests) ===========
[01:26:25] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[01:26:25] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[01:26:25] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[01:26:25] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[01:26:25] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[01:26:25] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[01:26:25] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[01:26:25] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[01:26:25] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[01:26:25] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[01:26:25] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[01:26:25] ============== drm_test_fb_xrgb8888_to_mono  ===============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[01:26:25] ==================== drm_test_fb_swab  =====================
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ================ [PASSED] drm_test_fb_swab =================
[01:26:25] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[01:26:25] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[01:26:25] [PASSED] single_pixel_source_buffer
[01:26:25] [PASSED] single_pixel_clip_rectangle
[01:26:25] [PASSED] well_known_colors
[01:26:25] [PASSED] destination_pitch
[01:26:25] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[01:26:25] ================= drm_test_fb_clip_offset  =================
[01:26:25] [PASSED] pass through
[01:26:25] [PASSED] horizontal offset
[01:26:25] [PASSED] vertical offset
[01:26:25] [PASSED] horizontal and vertical offset
[01:26:25] [PASSED] horizontal offset (custom pitch)
[01:26:25] [PASSED] vertical offset (custom pitch)
[01:26:25] [PASSED] horizontal and vertical offset (custom pitch)
[01:26:25] ============= [PASSED] drm_test_fb_clip_offset =============
[01:26:25] =================== drm_test_fb_memcpy  ====================
[01:26:25] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[01:26:25] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[01:26:25] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[01:26:25] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[01:26:25] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[01:26:25] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[01:26:25] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[01:26:25] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[01:26:25] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[01:26:25] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[01:26:25] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[01:26:25] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[01:26:25] =============== [PASSED] drm_test_fb_memcpy ================
[01:26:25] ============= [PASSED] drm_format_helper_test ==============
[01:26:25] ================= drm_format (18 subtests) =================
[01:26:25] [PASSED] drm_test_format_block_width_invalid
[01:26:25] [PASSED] drm_test_format_block_width_one_plane
[01:26:25] [PASSED] drm_test_format_block_width_two_plane
[01:26:25] [PASSED] drm_test_format_block_width_three_plane
[01:26:25] [PASSED] drm_test_format_block_width_tiled
[01:26:25] [PASSED] drm_test_format_block_height_invalid
[01:26:25] [PASSED] drm_test_format_block_height_one_plane
[01:26:25] [PASSED] drm_test_format_block_height_two_plane
[01:26:25] [PASSED] drm_test_format_block_height_three_plane
[01:26:25] [PASSED] drm_test_format_block_height_tiled
[01:26:25] [PASSED] drm_test_format_min_pitch_invalid
[01:26:25] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[01:26:25] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[01:26:25] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[01:26:25] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[01:26:25] [PASSED] drm_test_format_min_pitch_two_plane
[01:26:25] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[01:26:25] [PASSED] drm_test_format_min_pitch_tiled
[01:26:25] =================== [PASSED] drm_format ====================
[01:26:25] ============== drm_framebuffer (10 subtests) ===============
[01:26:25] ========== drm_test_framebuffer_check_src_coords  ==========
[01:26:25] [PASSED] Success: source fits into fb
[01:26:25] [PASSED] Fail: overflowing fb with x-axis coordinate
[01:26:25] [PASSED] Fail: overflowing fb with y-axis coordinate
[01:26:25] [PASSED] Fail: overflowing fb with source width
[01:26:25] [PASSED] Fail: overflowing fb with source height
[01:26:25] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[01:26:25] [PASSED] drm_test_framebuffer_cleanup
[01:26:25] =============== drm_test_framebuffer_create  ===============
[01:26:25] [PASSED] ABGR8888 normal sizes
[01:26:25] [PASSED] ABGR8888 max sizes
[01:26:25] [PASSED] ABGR8888 pitch greater than min required
[01:26:25] [PASSED] ABGR8888 pitch less than min required
[01:26:25] [PASSED] ABGR8888 Invalid width
[01:26:25] [PASSED] ABGR8888 Invalid buffer handle
[01:26:25] [PASSED] No pixel format
[01:26:25] [PASSED] ABGR8888 Width 0
[01:26:25] [PASSED] ABGR8888 Height 0
[01:26:25] [PASSED] ABGR8888 Out of bound height * pitch combination
[01:26:25] [PASSED] ABGR8888 Large buffer offset
[01:26:25] [PASSED] ABGR8888 Buffer offset for inexistent plane
[01:26:25] [PASSED] ABGR8888 Invalid flag
[01:26:25] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[01:26:25] [PASSED] ABGR8888 Valid buffer modifier
[01:26:25] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[01:26:25] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] NV12 Normal sizes
[01:26:25] [PASSED] NV12 Max sizes
[01:26:25] [PASSED] NV12 Invalid pitch
[01:26:25] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[01:26:25] [PASSED] NV12 different  modifier per-plane
[01:26:25] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[01:26:25] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] NV12 Modifier for inexistent plane
[01:26:25] [PASSED] NV12 Handle for inexistent plane
[01:26:25] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[01:26:25] [PASSED] YVU420 Normal sizes
[01:26:25] [PASSED] YVU420 Max sizes
[01:26:25] [PASSED] YVU420 Invalid pitch
[01:26:25] [PASSED] YVU420 Different pitches
[01:26:25] [PASSED] YVU420 Different buffer offsets/pitches
[01:26:25] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[01:26:25] [PASSED] YVU420 Valid modifier
[01:26:25] [PASSED] YVU420 Different modifiers per plane
[01:26:25] [PASSED] YVU420 Modifier for inexistent plane
[01:26:25] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[01:26:25] [PASSED] X0L2 Normal sizes
[01:26:25] [PASSED] X0L2 Max sizes
[01:26:25] [PASSED] X0L2 Invalid pitch
[01:26:25] [PASSED] X0L2 Pitch greater than minimum required
[01:26:25] [PASSED] X0L2 Handle for inexistent plane
[01:26:25] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[01:26:25] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[01:26:25] [PASSED] X0L2 Valid modifier
[01:26:25] [PASSED] X0L2 Modifier for inexistent plane
[01:26:25] =========== [PASSED] drm_test_framebuffer_create ===========
[01:26:25] [PASSED] drm_test_framebuffer_free
[01:26:25] [PASSED] drm_test_framebuffer_init
[01:26:25] [PASSED] drm_test_framebuffer_init_bad_format
[01:26:25] [PASSED] drm_test_framebuffer_init_dev_mismatch
[01:26:25] [PASSED] drm_test_framebuffer_lookup
[01:26:25] [PASSED] drm_test_framebuffer_lookup_inexistent
[01:26:25] [PASSED] drm_test_framebuffer_modifiers_not_supported
[01:26:25] ================= [PASSED] drm_framebuffer =================
[01:26:25] ================ drm_gem_shmem (8 subtests) ================
[01:26:25] [PASSED] drm_gem_shmem_test_obj_create
[01:26:25] [PASSED] drm_gem_shmem_test_obj_create_private
[01:26:25] [PASSED] drm_gem_shmem_test_pin_pages
[01:26:25] [PASSED] drm_gem_shmem_test_vmap
[01:26:25] [PASSED] drm_gem_shmem_test_get_sg_table
[01:26:25] [PASSED] drm_gem_shmem_test_get_pages_sgt
[01:26:25] [PASSED] drm_gem_shmem_test_madvise
[01:26:25] [PASSED] drm_gem_shmem_test_purge
[01:26:25] ================== [PASSED] drm_gem_shmem ==================
[01:26:25] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[01:26:25] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[01:26:25] [PASSED] Automatic
[01:26:25] [PASSED] Full
[01:26:25] [PASSED] Limited 16:235
[01:26:25] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[01:26:25] [PASSED] drm_test_check_disable_connector
[01:26:25] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[01:26:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[01:26:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[01:26:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[01:26:25] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[01:26:25] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[01:26:25] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[01:26:25] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[01:26:25] [PASSED] drm_test_check_output_bpc_dvi
[01:26:25] [PASSED] drm_test_check_output_bpc_format_vic_1
[01:26:25] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[01:26:25] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[01:26:25] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[01:26:25] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[01:26:25] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[01:26:25] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[01:26:25] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[01:26:25] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[01:26:25] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[01:26:25] [PASSED] drm_test_check_broadcast_rgb_value
[01:26:25] [PASSED] drm_test_check_bpc_8_value
[01:26:25] [PASSED] drm_test_check_bpc_10_value
[01:26:25] [PASSED] drm_test_check_bpc_12_value
[01:26:25] [PASSED] drm_test_check_format_value
[01:26:25] [PASSED] drm_test_check_tmds_char_value
[01:26:25] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[01:26:25] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[01:26:25] [PASSED] drm_test_check_mode_valid
[01:26:25] [PASSED] drm_test_check_mode_valid_reject
[01:26:25] [PASSED] drm_test_check_mode_valid_reject_rate
[01:26:25] [PASSED] drm_test_check_mode_valid_reject_max_clock
[01:26:25] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[01:26:25] ================= drm_managed (2 subtests) =================
[01:26:25] [PASSED] drm_test_managed_release_action
[01:26:25] [PASSED] drm_test_managed_run_action
[01:26:25] =================== [PASSED] drm_managed ===================
[01:26:25] =================== drm_mm (6 subtests) ====================
[01:26:25] [PASSED] drm_test_mm_init
[01:26:25] [PASSED] drm_test_mm_debug
[01:26:25] [PASSED] drm_test_mm_align32
[01:26:25] [PASSED] drm_test_mm_align64
[01:26:25] [PASSED] drm_test_mm_lowest
[01:26:25] [PASSED] drm_test_mm_highest
[01:26:25] ===================== [PASSED] drm_mm ======================
[01:26:25] ============= drm_modes_analog_tv (5 subtests) =============
[01:26:25] [PASSED] drm_test_modes_analog_tv_mono_576i
[01:26:25] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[01:26:25] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[01:26:25] [PASSED] drm_test_modes_analog_tv_pal_576i
[01:26:25] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[01:26:25] =============== [PASSED] drm_modes_analog_tv ===============
[01:26:25] ============== drm_plane_helper (2 subtests) ===============
[01:26:25] =============== drm_test_check_plane_state  ================
[01:26:25] [PASSED] clipping_simple
[01:26:25] [PASSED] clipping_rotate_reflect
[01:26:25] [PASSED] positioning_simple
[01:26:25] [PASSED] upscaling
[01:26:25] [PASSED] downscaling
[01:26:25] [PASSED] rounding1
[01:26:25] [PASSED] rounding2
[01:26:25] [PASSED] rounding3
[01:26:25] [PASSED] rounding4
[01:26:25] =========== [PASSED] drm_test_check_plane_state ============
[01:26:25] =========== drm_test_check_invalid_plane_state  ============
[01:26:25] [PASSED] positioning_invalid
[01:26:25] [PASSED] upscaling_invalid
[01:26:25] [PASSED] downscaling_invalid
[01:26:25] ======= [PASSED] drm_test_check_invalid_plane_state ========
[01:26:25] ================ [PASSED] drm_plane_helper =================
[01:26:25] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[01:26:25] ====== drm_test_connector_helper_tv_get_modes_check  =======
[01:26:25] [PASSED] None
[01:26:25] [PASSED] PAL
[01:26:25] [PASSED] NTSC
[01:26:25] [PASSED] Both, NTSC Default
[01:26:25] [PASSED] Both, PAL Default
[01:26:25] [PASSED] Both, NTSC Default, with PAL on command-line
[01:26:25] [PASSED] Both, PAL Default, with NTSC on command-line
[01:26:25] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[01:26:25] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[01:26:25] ================== drm_rect (9 subtests) ===================
[01:26:25] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[01:26:25] [PASSED] drm_test_rect_clip_scaled_not_clipped
[01:26:25] [PASSED] drm_test_rect_clip_scaled_clipped
[01:26:25] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[01:26:25] ================= drm_test_rect_intersect  =================
[01:26:25] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[01:26:25] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[01:26:25] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[01:26:25] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[01:26:25] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[01:26:25] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[01:26:25] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[01:26:25] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[01:26:25] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[01:26:25] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[01:26:25] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[01:26:25] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[01:26:25] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[01:26:25] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[01:26:25] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[01:26:25] ============= [PASSED] drm_test_rect_intersect =============
[01:26:25] ================ drm_test_rect_calc_hscale  ================
[01:26:25] [PASSED] normal use
[01:26:25] [PASSED] out of max range
[01:26:25] [PASSED] out of min range
[01:26:25] [PASSED] zero dst
[01:26:25] [PASSED] negative src
[01:26:25] [PASSED] negative dst
[01:26:25] ============ [PASSED] drm_test_rect_calc_hscale ============
[01:26:25] ================ drm_test_rect_calc_vscale  ================
[01:26:25] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[01:26:25] [PASSED] out of max range
[01:26:25] [PASSED] out of min range
[01:26:25] [PASSED] zero dst
[01:26:25] [PASSED] negative src
[01:26:25] [PASSED] negative dst
[01:26:25] ============ [PASSED] drm_test_rect_calc_vscale ============
[01:26:25] ================== drm_test_rect_rotate  ===================
[01:26:25] [PASSED] reflect-x
[01:26:25] [PASSED] reflect-y
[01:26:25] [PASSED] rotate-0
[01:26:25] [PASSED] rotate-90
[01:26:25] [PASSED] rotate-180
[01:26:25] [PASSED] rotate-270
[01:26:25] ============== [PASSED] drm_test_rect_rotate ===============
[01:26:25] ================ drm_test_rect_rotate_inv  =================
[01:26:25] [PASSED] reflect-x
[01:26:25] [PASSED] reflect-y
[01:26:25] [PASSED] rotate-0
[01:26:25] [PASSED] rotate-90
[01:26:25] [PASSED] rotate-180
[01:26:25] [PASSED] rotate-270
[01:26:25] ============ [PASSED] drm_test_rect_rotate_inv =============
[01:26:25] ==================== [PASSED] drm_rect =====================
[01:26:25] ============ drm_sysfb_modeset_test (1 subtest) ============
[01:26:25] ============ drm_test_sysfb_build_fourcc_list  =============
[01:26:25] [PASSED] no native formats
[01:26:25] [PASSED] XRGB8888 as native format
[01:26:25] [PASSED] remove duplicates
[01:26:25] [PASSED] convert alpha formats
[01:26:25] [PASSED] random formats
[01:26:25] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[01:26:25] ============= [PASSED] drm_sysfb_modeset_test ==============
[01:26:25] ================== drm_fixp (2 subtests) ===================
[01:26:25] [PASSED] drm_test_int2fixp
[01:26:25] [PASSED] drm_test_sm2fixp
[01:26:25] ==================== [PASSED] drm_fixp =====================
[01:26:25] ============================================================
[01:26:25] Testing complete. Ran 624 tests: passed: 624
[01:26:25] Elapsed time: 27.446s total, 1.669s configuring, 25.359s building, 0.379s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[01:26:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[01:26:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[01:26:36] Starting KUnit Kernel (1/1)...
[01:26:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[01:26:36] ================= ttm_device (5 subtests) ==================
[01:26:36] [PASSED] ttm_device_init_basic
[01:26:36] [PASSED] ttm_device_init_multiple
[01:26:36] [PASSED] ttm_device_fini_basic
[01:26:36] [PASSED] ttm_device_init_no_vma_man
[01:26:36] ================== ttm_device_init_pools  ==================
[01:26:36] [PASSED] No DMA allocations, no DMA32 required
[01:26:36] [PASSED] DMA allocations, DMA32 required
[01:26:36] [PASSED] No DMA allocations, DMA32 required
[01:26:36] [PASSED] DMA allocations, no DMA32 required
[01:26:36] ============== [PASSED] ttm_device_init_pools ==============
[01:26:36] =================== [PASSED] ttm_device ====================
[01:26:36] ================== ttm_pool (8 subtests) ===================
[01:26:36] ================== ttm_pool_alloc_basic  ===================
[01:26:36] [PASSED] One page
[01:26:36] [PASSED] More than one page
[01:26:36] [PASSED] Above the allocation limit
[01:26:36] [PASSED] One page, with coherent DMA mappings enabled
[01:26:36] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[01:26:36] ============== [PASSED] ttm_pool_alloc_basic ===============
[01:26:36] ============== ttm_pool_alloc_basic_dma_addr  ==============
[01:26:36] [PASSED] One page
[01:26:36] [PASSED] More than one page
[01:26:36] [PASSED] Above the allocation limit
[01:26:36] [PASSED] One page, with coherent DMA mappings enabled
[01:26:36] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[01:26:36] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[01:26:36] [PASSED] ttm_pool_alloc_order_caching_match
[01:26:36] [PASSED] ttm_pool_alloc_caching_mismatch
[01:26:36] [PASSED] ttm_pool_alloc_order_mismatch
[01:26:36] [PASSED] ttm_pool_free_dma_alloc
[01:26:36] [PASSED] ttm_pool_free_no_dma_alloc
[01:26:36] [PASSED] ttm_pool_fini_basic
[01:26:36] ==================== [PASSED] ttm_pool =====================
[01:26:36] ================ ttm_resource (8 subtests) =================
[01:26:36] ================= ttm_resource_init_basic  =================
[01:26:36] [PASSED] Init resource in TTM_PL_SYSTEM
[01:26:36] [PASSED] Init resource in TTM_PL_VRAM
[01:26:36] [PASSED] Init resource in a private placement
[01:26:36] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[01:26:36] ============= [PASSED] ttm_resource_init_basic =============
[01:26:36] [PASSED] ttm_resource_init_pinned
[01:26:36] [PASSED] ttm_resource_fini_basic
[01:26:36] [PASSED] ttm_resource_manager_init_basic
[01:26:36] [PASSED] ttm_resource_manager_usage_basic
[01:26:36] [PASSED] ttm_resource_manager_set_used_basic
[01:26:36] [PASSED] ttm_sys_man_alloc_basic
[01:26:36] [PASSED] ttm_sys_man_free_basic
[01:26:36] ================== [PASSED] ttm_resource ===================
[01:26:36] =================== ttm_tt (15 subtests) ===================
[01:26:36] ==================== ttm_tt_init_basic  ====================
[01:26:36] [PASSED] Page-aligned size
[01:26:36] [PASSED] Extra pages requested
[01:26:36] ================ [PASSED] ttm_tt_init_basic ================
[01:26:36] [PASSED] ttm_tt_init_misaligned
[01:26:36] [PASSED] ttm_tt_fini_basic
[01:26:36] [PASSED] ttm_tt_fini_sg
[01:26:36] [PASSED] ttm_tt_fini_shmem
[01:26:36] [PASSED] ttm_tt_create_basic
[01:26:36] [PASSED] ttm_tt_create_invalid_bo_type
[01:26:36] [PASSED] ttm_tt_create_ttm_exists
[01:26:36] [PASSED] ttm_tt_create_failed
[01:26:36] [PASSED] ttm_tt_destroy_basic
[01:26:36] [PASSED] ttm_tt_populate_null_ttm
[01:26:36] [PASSED] ttm_tt_populate_populated_ttm
[01:26:36] [PASSED] ttm_tt_unpopulate_basic
[01:26:36] [PASSED] ttm_tt_unpopulate_empty_ttm
[01:26:36] [PASSED] ttm_tt_swapin_basic
[01:26:36] ===================== [PASSED] ttm_tt ======================
[01:26:36] =================== ttm_bo (14 subtests) ===================
[01:26:36] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[01:26:36] [PASSED] Cannot be interrupted and sleeps
[01:26:36] [PASSED] Cannot be interrupted, locks straight away
[01:26:36] [PASSED] Can be interrupted, sleeps
[01:26:36] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[01:26:36] [PASSED] ttm_bo_reserve_locked_no_sleep
[01:26:36] [PASSED] ttm_bo_reserve_no_wait_ticket
[01:26:36] [PASSED] ttm_bo_reserve_double_resv
[01:26:36] [PASSED] ttm_bo_reserve_interrupted
[01:26:36] [PASSED] ttm_bo_reserve_deadlock
[01:26:36] [PASSED] ttm_bo_unreserve_basic
[01:26:36] [PASSED] ttm_bo_unreserve_pinned
[01:26:36] [PASSED] ttm_bo_unreserve_bulk
[01:26:36] [PASSED] ttm_bo_fini_basic
[01:26:36] [PASSED] ttm_bo_fini_shared_resv
[01:26:36] [PASSED] ttm_bo_pin_basic
[01:26:36] [PASSED] ttm_bo_pin_unpin_resource
[01:26:36] [PASSED] ttm_bo_multiple_pin_one_unpin
[01:26:36] ===================== [PASSED] ttm_bo ======================
[01:26:36] ============== ttm_bo_validate (21 subtests) ===============
[01:26:36] ============== ttm_bo_init_reserved_sys_man  ===============
[01:26:36] [PASSED] Buffer object for userspace
[01:26:36] [PASSED] Kernel buffer object
[01:26:36] [PASSED] Shared buffer object
[01:26:36] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[01:26:36] ============== ttm_bo_init_reserved_mock_man  ==============
[01:26:36] [PASSED] Buffer object for userspace
[01:26:36] [PASSED] Kernel buffer object
[01:26:36] [PASSED] Shared buffer object
[01:26:36] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[01:26:36] [PASSED] ttm_bo_init_reserved_resv
[01:26:36] ================== ttm_bo_validate_basic  ==================
[01:26:36] [PASSED] Buffer object for userspace
[01:26:36] [PASSED] Kernel buffer object
[01:26:36] [PASSED] Shared buffer object
[01:26:36] ============== [PASSED] ttm_bo_validate_basic ==============
[01:26:36] [PASSED] ttm_bo_validate_invalid_placement
[01:26:36] ============= ttm_bo_validate_same_placement  ==============
[01:26:36] [PASSED] System manager
[01:26:36] [PASSED] VRAM manager
[01:26:36] ========= [PASSED] ttm_bo_validate_same_placement ==========
[01:26:36] [PASSED] ttm_bo_validate_failed_alloc
[01:26:36] [PASSED] ttm_bo_validate_pinned
[01:26:36] [PASSED] ttm_bo_validate_busy_placement
[01:26:36] ================ ttm_bo_validate_multihop  =================
[01:26:36] [PASSED] Buffer object for userspace
[01:26:36] [PASSED] Kernel buffer object
[01:26:36] [PASSED] Shared buffer object
[01:26:36] ============ [PASSED] ttm_bo_validate_multihop =============
[01:26:36] ========== ttm_bo_validate_no_placement_signaled  ==========
[01:26:36] [PASSED] Buffer object in system domain, no page vector
[01:26:36] [PASSED] Buffer object in system domain with an existing page vector
[01:26:36] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[01:26:36] ======== ttm_bo_validate_no_placement_not_signaled  ========
[01:26:36] [PASSED] Buffer object for userspace
[01:26:36] [PASSED] Kernel buffer object
[01:26:36] [PASSED] Shared buffer object
[01:26:36] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[01:26:36] [PASSED] ttm_bo_validate_move_fence_signaled
[01:26:36] ========= ttm_bo_validate_move_fence_not_signaled  =========
[01:26:36] [PASSED] Waits for GPU
[01:26:36] [PASSED] Tries to lock straight away
[01:26:36] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[01:26:36] [PASSED] ttm_bo_validate_happy_evict
[01:26:36] [PASSED] ttm_bo_validate_all_pinned_evict
[01:26:36] [PASSED] ttm_bo_validate_allowed_only_evict
[01:26:36] [PASSED] ttm_bo_validate_deleted_evict
[01:26:36] [PASSED] ttm_bo_validate_busy_domain_evict
[01:26:36] [PASSED] ttm_bo_validate_evict_gutting
[01:26:36] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[01:26:36] ================= [PASSED] ttm_bo_validate =================
[01:26:36] ============================================================
[01:26:36] Testing complete. Ran 101 tests: passed: 101
[01:26:36] Elapsed time: 11.392s total, 1.731s configuring, 9.394s building, 0.225s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.BAT: failure for Fence deadlines in Xe

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2305 bytes --]

== Series Details ==

Series: Fence deadlines in Xe
URL   : https://patchwork.freedesktop.org/series/159479/
State : failure

== Summary ==

CI Bug Log - changes from xe-4302-5c680ac45628b1951d20a444f400c82242029031_BAT -> xe-pw-159479v1_BAT
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with xe-pw-159479v1_BAT need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-159479v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-159479v1_BAT:

### IGT changes ###

#### Warnings ####

  * igt@xe_module_load@load:
    - bat-bmg-1:          [ABORT][1] ([Intel XE#6922]) -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/bat-bmg-1/igt@xe_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/bat-bmg-1/igt@xe_module_load@load.html

  
Known issues
------------

  Here are the changes found in xe-pw-159479v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][3] ([Intel XE#6519]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519
  [Intel XE#6922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6922


Build changes
-------------

  * Linux: xe-4302-5c680ac45628b1951d20a444f400c82242029031 -> xe-pw-159479v1

  IGT_8677: 8677
  xe-4302-5c680ac45628b1951d20a444f400c82242029031: 5c680ac45628b1951d20a444f400c82242029031
  xe-pw-159479v1: 159479v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/index.html

[-- Attachment #2: Type: text/html, Size: 2904 bytes --]

✓ Xe.CI.Full: success for Fence deadlines in Xe

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11610 bytes --]

== Series Details ==

Series: Fence deadlines in Xe
URL   : https://patchwork.freedesktop.org/series/159479/
State : success

== Summary ==

CI Bug Log - changes from xe-4302-5c680ac45628b1951d20a444f400c82242029031_FULL -> xe-pw-159479v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-159479v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2887])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#2724])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2325])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][4] -> [FAIL][5] ([Intel XE#4633])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][6] -> [FAIL][7] ([Intel XE#5299])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2311]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2313]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch@pipe-a-dp-2:
    - shard-bmg:          [PASS][10] -> [ABORT][11] ([Intel XE#6740]) +1 other test abort
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-10/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-8/igt@kms_hdr@bpc-switch@pipe-a-dp-2.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#1406] / [Intel XE#1489])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@xe_eudebug_online@interrupt-all:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#4837] / [Intel XE#6665])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@xe_eudebug_online@interrupt-all.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][14] -> [INCOMPLETE][15] ([Intel XE#6321])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-8/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#6874])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-2/igt@xe_exec_multi_queue@few-execs-preempt-mode-close-fd.html

  * igt@xe_exec_system_allocator@twice-mmap-free-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#4943]) +3 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@xe_exec_system_allocator@twice-mmap-free-huge-nomemset.html

  * igt@xe_pmu@engine-activity-accuracy-50:
    - shard-lnl:          [PASS][18] -> [FAIL][19] ([Intel XE#6251]) +4 other tests fail
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-50.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-50.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-bmg:          NOTRUN -> [FAIL][20] ([Intel XE#6569])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@xe_sriov_flr@flr-each-isolation.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear:
    - shard-lnl:          [FAIL][21] ([Intel XE#5993]) -> [PASS][22] +3 other tests pass
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-toggle:
    - shard-bmg:          [SKIP][23] ([Intel XE#2291]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipa-toggle.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-bmg:          [SKIP][25] ([Intel XE#2316]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_vrr@flipline:
    - shard-lnl:          [FAIL][27] ([Intel XE#4227]) -> [PASS][28] +1 other test pass
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-lnl-4/igt@kms_vrr@flipline.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-lnl-3/igt@kms_vrr@flipline.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
    - shard-lnl:          [FAIL][29] ([Intel XE#5625]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [FAIL][31] ([Intel XE#6251]) -> [PASS][32] +1 other test pass
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-lnl-5/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][33] ([Intel XE#2312]) -> [SKIP][34] ([Intel XE#4141])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][35] ([Intel XE#2312]) -> [SKIP][36] ([Intel XE#2313])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [ABORT][37] ([Intel XE#6740]) -> [SKIP][38] ([Intel XE#1503])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4302-5c680ac45628b1951d20a444f400c82242029031/shard-bmg-7/igt@kms_hdr@invalid-hdr.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/shard-bmg-9/igt@kms_hdr@invalid-hdr.html

  
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874


Build changes
-------------

  * Linux: xe-4302-5c680ac45628b1951d20a444f400c82242029031 -> xe-pw-159479v1

  IGT_8677: 8677
  xe-4302-5c680ac45628b1951d20a444f400c82242029031: 5c680ac45628b1951d20a444f400c82242029031
  xe-pw-159479v1: 159479v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159479v1/index.html

[-- Attachment #2: Type: text/html, Size: 12972 bytes --]