[v2 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display

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From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: jani.nikula@intel.com, ville.syrjala@linux.intel.com,
	Uma Shankar <uma.shankar@intel.com>
Subject: [v2 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display
Date: Thu, 22 Jan 2026 04:53:59 +0530	[thread overview]
Message-ID: <20260121232414.707192-5-uma.shankar@intel.com> (raw)
In-Reply-To: <20260121232414.707192-1-uma.shankar@intel.com>

Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c free of i915_reg.h include.

v2: Drop common header in include and use display_regs.h (Jani)

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_gmbus.c    |  1 -
 drivers/gpu/drm/i915/i915_reg.h               | 50 -------------------
 3 files changed, 50 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 1f922d013cd3..5136b7166775 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -160,6 +160,47 @@
 
 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
 
+#define DSPCLK_GATE_D			_MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
+# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
+# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+/*
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
+
 /* Additional CHV pll/phy registers */
 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
 #define   DPLL_PORTD_READY_MASK		(0xf)
@@ -2926,6 +2967,15 @@ enum skl_power_gate {
 #define  LPT_PWM_GRANULARITY		(1 << 5)
 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
 
+#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
+#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
+#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
+#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
+#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
+#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
+#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
+
 /* Gen4+ Timestamp and Pipe Frame time stamp registers */
 #define GEN4_TIMESTAMP		_MMIO(0x2358)
 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2caff677600c..81b6c6991323 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -35,7 +35,6 @@
 #include <drm/drm_print.h>
 #include <drm/display/drm_hdcp_helper.h>
 
-#include "i915_reg.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5cd124083c17..dc13f9eb4cd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,47 +613,6 @@
 #define  DSTATE_GFX_CLOCK_GATING		(1 << 1)
 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
 
-#define DSPCLK_GATE_D			_MMIO(0x6200)
-#define VLV_DSPCLK_GATE_D		_MMIO(VLV_DISPLAY_BASE + 0x6200)
-# define DPUNIT_B_CLOCK_GATE_DISABLE		(1 << 30) /* 965 */
-# define VSUNIT_CLOCK_GATE_DISABLE		(1 << 29) /* 965 */
-# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* 965 */
-# define VRDUNIT_CLOCK_GATE_DISABLE		(1 << 27) /* 965 */
-# define AUDUNIT_CLOCK_GATE_DISABLE		(1 << 26) /* 965 */
-# define DPUNIT_A_CLOCK_GATE_DISABLE		(1 << 25) /* 965 */
-# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24) /* 965 */
-# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE	(1 << 24) /* pnv */
-# define TVRUNIT_CLOCK_GATE_DISABLE		(1 << 23) /* 915-945 */
-# define TVCUNIT_CLOCK_GATE_DISABLE		(1 << 22) /* 915-945 */
-# define TVFUNIT_CLOCK_GATE_DISABLE		(1 << 21) /* 915-945 */
-# define TVEUNIT_CLOCK_GATE_DISABLE		(1 << 20) /* 915-945 */
-# define DVSUNIT_CLOCK_GATE_DISABLE		(1 << 19) /* 915-945 */
-# define DSSUNIT_CLOCK_GATE_DISABLE		(1 << 18) /* 915-945 */
-# define DDBUNIT_CLOCK_GATE_DISABLE		(1 << 17) /* 915-945 */
-# define DPRUNIT_CLOCK_GATE_DISABLE		(1 << 16) /* 915-945 */
-# define DPFUNIT_CLOCK_GATE_DISABLE		(1 << 15) /* 915-945 */
-# define DPBMUNIT_CLOCK_GATE_DISABLE		(1 << 14) /* 915-945 */
-# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13) /* 915-945 */
-# define DPLUNIT_CLOCK_GATE_DISABLE		(1 << 12) /* 915-945 */
-# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
-# define DPBUNIT_CLOCK_GATE_DISABLE		(1 << 10)
-# define DCUNIT_CLOCK_GATE_DISABLE		(1 << 9)
-# define DPUNIT_CLOCK_GATE_DISABLE		(1 << 8)
-# define VRUNIT_CLOCK_GATE_DISABLE		(1 << 7) /* 915+: reserved */
-# define OVHUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 830-865 */
-# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
-# define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
-# define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
-/*
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
-# define OVRUNIT_CLOCK_GATE_DISABLE		(1 << 3)
-# define OVCUNIT_CLOCK_GATE_DISABLE		(1 << 2)
-# define OVUUNIT_CLOCK_GATE_DISABLE		(1 << 1)
-# define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
-# define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
-
 #define RENCLK_GATE_D1		_MMIO(0x6204)
 # define BLITTER_CLOCK_GATE_DISABLE		(1 << 13) /* 945GM only */
 # define MPEG_CLOCK_GATE_DISABLE		(1 << 12) /* 945GM only */
@@ -989,15 +948,6 @@
 #define   TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE	REG_BIT(10)
 #define   TRANS_CHICKEN1_DP0UNIT_GC_DISABLE	REG_BIT(4)
 
-#define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
-#define  PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
-#define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-#define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
-#define  PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
-#define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
-#define  CNP_PWM_CGE_GATING_DISABLE (1 << 13)
-#define  PCH_LP_PARTITION_LEVEL_DISABLE  (1 << 12)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
-- 
2.50.1

next prev parent reply	other threads:[~2026-01-21 23:08 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-21 23:23 [v2 00/19] Make Display free from i915_reg.h Uma Shankar
2026-01-21 23:23 ` [v2 01/19] drm/{i915, xe}: Extract display registers from i915_reg.h to display Uma Shankar
2026-01-22 11:16   ` Jani Nikula
2026-01-22 11:16   ` Jani Nikula
2026-01-23 10:38     ` Shankar, Uma
2026-01-21 23:23 ` [v2 02/19] drm/{i915, xe}: Extract South chicken " Uma Shankar
2026-01-22 11:26   ` Jani Nikula
2026-01-23 10:40     ` Shankar, Uma
2026-01-21 23:23 ` [v2 03/19] drm/{i915, xe}: Extract display interrupt definitions Uma Shankar
2026-01-22 11:29   ` Jani Nikula
2026-01-23 10:42     ` Shankar, Uma
2026-01-21 23:23 ` Uma Shankar [this message]
2026-01-22 11:31   ` [v2 04/19] drm/{i915, xe}: Extract DSPCLK_GATE_D from i915_reg to display Jani Nikula
2026-01-21 23:24 ` [v2 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
2026-01-22 11:40   ` Jani Nikula
2026-01-23 10:45     ` Shankar, Uma
2026-01-22 11:46   ` Jani Nikula
2026-01-23 10:46     ` Shankar, Uma
2026-01-21 23:24 ` [v2 06/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_device.c Uma Shankar
2026-01-22 11:36   ` Jani Nikula
2026-01-23 10:43     ` Shankar, Uma
2026-01-21 23:24 ` [v2 07/19] drm/{i915, xe}: Remove i915_reg.h from intel_dram.c Uma Shankar
2026-01-22 11:41   ` Jani Nikula
2026-01-23 10:45     ` Shankar, Uma
2026-01-21 23:24 ` [v2 08/19] drm/{i915, xe}: Removed i915_reg.h from intel_display.c Uma Shankar
2026-01-22 11:43   ` Jani Nikula
2026-01-21 23:24 ` [v2 09/19] drm/{i915, xe}: Remove i915_reg.h from intel_overlay.c Uma Shankar
2026-01-22 11:51   ` Jani Nikula
2026-01-23 10:47     ` Shankar, Uma
2026-01-21 23:24 ` [v2 10/19] drm/{i915, xe}: Remove i915_reg.h from g4x_dp.c Uma Shankar
2026-01-22 12:00   ` Jani Nikula
2026-01-23 10:48     ` Shankar, Uma
2026-01-21 23:24 ` [v2 11/19] drm/{i915, xe}: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2026-01-21 23:24 ` [v2 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
2026-01-22 12:08   ` Jani Nikula
2026-01-21 23:24 ` [v2 13/19] drm/{i915, xe}: Remove i915_reg.h from intel_rom.c Uma Shankar
2026-01-22 12:09   ` Jani Nikula
2026-01-21 23:24 ` [v2 14/19] drm/{i915, xe}: Remove i915_reg.h from intel_psr.c Uma Shankar
2026-01-22 12:10   ` Jani Nikula
2026-01-21 23:24 ` [v2 15/19] drm/{i915, xe}: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
2026-01-22 12:14   ` Jani Nikula
2026-01-23 10:49     ` Shankar, Uma
2026-01-21 23:24 ` [v2 16/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_irq.c Uma Shankar
2026-01-22 12:18   ` Jani Nikula
2026-01-23 10:49     ` Shankar, Uma
2026-01-21 23:24 ` [v2 17/19] drm/{i915, xe}: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2026-01-22 12:19   ` Jani Nikula
2026-01-23 10:50     ` Shankar, Uma
2026-01-21 23:24 ` [v2 18/19] drm/{i915, xe}: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
2026-01-22 12:21   ` Jani Nikula
2026-01-21 23:24 ` [v2 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
2026-01-22 12:20   ` Jani Nikula
2026-01-23 10:53     ` Shankar, Uma
2026-01-21 23:56 ` ✗ CI.checkpatch: warning for Make Display free from i915_reg.h (rev2) Patchwork
2026-01-21 23:58 ` ✓ CI.KUnit: success " Patchwork
2026-01-22  0:13 ` ✗ CI.checksparse: warning " Patchwork
2026-01-22  0:39 ` ✓ Xe.CI.BAT: success " Patchwork
2026-01-22 10:10 ` ✓ Xe.CI.Full: " Patchwork

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