[PATCH v3 0/3] dGPU memory optimizations

[Matthew Brost <matthew.brost@intel.com>]

Profiling has shown that reading from VRAM on BMG is very slow and
introduces significant latency in GuC CT operations. To address this,
CPU-side read buffers (G2H) are moved to system memory, and unnecessary
CPU reads of VRAM in H2G paths are removed. This results in roughly a
50× improvement in page-fault G2H read latency and a 10× improvement in
H2G send latency (observed in ftrace) These optimizations have produced
noticeable improvements in page-fault UMD benchmarks.

Also move the seqno LRC to system memory. The performance impact of this
has not been measured, but based on GuC behavior, the HW fence signaling
path should see a noticeable speedup.

Matt

v2:
 - Fix devcoredump explosion (Testing)
v3:
 - Drop fixes tags
 - Address Michal's comments
 - Fix H2G tracepoint to avoid unconditional VRAM read
 - Move LRC seqno to system memory

Matthew Brost (3):
  drm/xe: Split H2G and G2H into separate buffer objects
  drm/xe: Avoid unconditional VRAM reads in H2G path
  drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads

 drivers/gpu/drm/xe/xe_guc_ct.c       | 92 ++++++++++++++++++----------
 drivers/gpu/drm/xe/xe_guc_ct_types.h |  4 +-
 drivers/gpu/drm/xe/xe_lrc.c          | 57 ++++++++++-------
 drivers/gpu/drm/xe/xe_lrc_types.h    |  6 ++
 4 files changed, 105 insertions(+), 54 deletions(-)

-- 
2.34.1