From: Matthew Brost <matthew.brost@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: stuart.summers@intel.com, francois.dugast@intel.com,
daniele.ceraolospurio@intel.com, michal.wajdeczko@intel.com
Subject: [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path
Date: Tue, 17 Feb 2026 20:33:18 -0800 [thread overview]
Message-ID: <20260218043319.809548-3-matthew.brost@intel.com> (raw)
In-Reply-To: <20260218043319.809548-1-matthew.brost@intel.com>
desc_read() issues an VRAM read which serializes the CPU and drains
posted writes on dGPU platforms. The H2G tracepoint evaluated its
arguments unconditionally, so even with tracing disabled the submission
path paid the full VRAM readf latency. Guard the tracepoint with
trace_xe_guc_ctb_h2g_enabled().
Adso move the descriptor status verification under CONFIG_DRM_XE_DEBUG.
This removes another unnecessary VRAM read in non-debug builfds.
This results in ~10× faster H2G submission and significantly reduces
lock contention across the driver.
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_guc_ct.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index ea07a27757d5..37842c93e0ee 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
u32 full_len;
struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
tail * sizeof(u32));
- u32 desc_status;
full_len = len + GUC_CTB_HDR_LEN;
lockdep_assert_held(&ct->lock);
xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
- desc_status = desc_read(xe, h2g, status);
- if (desc_status) {
- xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
- goto corrupted;
- }
-
if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
u32 desc_tail = desc_read(xe, h2g, tail);
u32 desc_head = desc_read(xe, h2g, head);
+ u32 desc_status;
+
+ desc_status = desc_read(xe, h2g, status);
+ if (desc_status) {
+ xe_gt_err(gt, "CT write: non-zero status: %u\n", desc_status);
+ goto corrupted;
+ }
if (tail != desc_tail) {
desc_write(xe, h2g, status, desc_status | GUC_CTB_STATUS_MISMATCH);
@@ -1023,8 +1023,15 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len,
/* Update descriptor */
desc_write(xe, h2g, tail, h2g->info.tail);
- trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1), full_len,
- desc_read(xe, h2g, head), h2g->info.tail);
+ /*
+ * desc_read() performs an VRAM read which serializes the CPU and drains
+ * posted writes on dGPU platforms. Tracepoints evaluate arguments even
+ * when disabled, so guard the event to avoid adding µs-scale latency to
+ * the fast H2G submission path when tracing is not active.
+ */
+ if (trace_xe_guc_ctb_h2g_enabled())
+ trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1), full_len,
+ desc_read(xe, h2g, head), h2g->info.tail);
return 0;
--
2.34.1
next prev parent reply other threads:[~2026-02-18 4:33 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-18 4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
2026-02-18 4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
2026-02-18 23:12 ` Summers, Stuart
2026-02-19 3:46 ` Matthew Brost
2026-02-24 15:58 ` Thomas Hellström
2026-02-24 16:12 ` Matthew Brost
2026-02-25 10:55 ` Thomas Hellström
2026-02-25 18:08 ` Matthew Brost
2026-02-26 12:08 ` Thomas Hellström
2026-02-18 4:33 ` Matthew Brost [this message]
2026-02-18 23:20 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Summers, Stuart
2026-02-26 12:47 ` Thomas Hellström
2026-02-18 4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
2026-02-24 2:40 ` Matthew Brost
2026-02-26 12:25 ` Thomas Hellström
2026-02-26 17:11 ` Matthew Brost
2026-02-26 17:26 ` Matthew Brost
2026-02-26 17:56 ` Thomas Hellström
2026-02-26 12:43 ` Thomas Hellström
2026-02-26 16:55 ` Matthew Brost
2026-02-18 4:40 ` ✓ CI.KUnit: success for dGPU memory optimizations Patchwork
2026-02-18 5:23 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-18 6:15 ` ✗ Xe.CI.FULL: " Patchwork
2026-02-18 7:07 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev2) Patchwork
2026-02-18 7:36 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18 7:53 ` ✓ Xe.CI.FULL: " Patchwork
2026-02-18 12:29 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev3) Patchwork
2026-02-18 13:09 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18 14:08 ` ✗ Xe.CI.FULL: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260218043319.809548-3-matthew.brost@intel.com \
--to=matthew.brost@intel.com \
--cc=daniele.ceraolospurio@intel.com \
--cc=francois.dugast@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=michal.wajdeczko@intel.com \
--cc=stuart.summers@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox