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From: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
To: Matthew Brost <matthew.brost@intel.com>, intel-xe@lists.freedesktop.org
Cc: stuart.summers@intel.com, francois.dugast@intel.com,
	 daniele.ceraolospurio@intel.com, michal.wajdeczko@intel.com
Subject: Re: [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path
Date: Thu, 26 Feb 2026 13:47:42 +0100	[thread overview]
Message-ID: <5af82176a404fed45d84f727141db32ed05c73ae.camel@linux.intel.com> (raw)
In-Reply-To: <20260218043319.809548-3-matthew.brost@intel.com>

On Tue, 2026-02-17 at 20:33 -0800, Matthew Brost wrote:
> desc_read() issues an VRAM read which serializes the CPU and drains
> posted writes on dGPU platforms. The H2G tracepoint evaluated its
> arguments unconditionally, so even with tracing disabled the
> submission
> path paid the full VRAM readf latency. Guard the tracepoint with

s/readf/read/

> trace_xe_guc_ctb_h2g_enabled().
> 
> Adso move the descriptor status verification under

s/Adso/Also/

> CONFIG_DRM_XE_DEBUG.
> This removes another unnecessary VRAM read in non-debug builfds.

s/builfds/builds/

> 
> This results in ~10× faster H2G submission and significantly reduces
> lock contention across the driver.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ct.c | 25 ++++++++++++++++---------
>  1 file changed, 16 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c
> b/drivers/gpu/drm/xe/xe_guc_ct.c
> index ea07a27757d5..37842c93e0ee 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -939,22 +939,22 @@ static int h2g_write(struct xe_guc_ct *ct,
> const u32 *action, u32 len,
>  	u32 full_len;
>  	struct iosys_map map = IOSYS_MAP_INIT_OFFSET(&h2g->cmds,
>  							 tail *
> sizeof(u32));
> -	u32 desc_status;
>  
>  	full_len = len + GUC_CTB_HDR_LEN;
>  
>  	lockdep_assert_held(&ct->lock);
>  	xe_gt_assert(gt, full_len <= GUC_CTB_MSG_MAX_LEN);
>  
> -	desc_status = desc_read(xe, h2g, status);
> -	if (desc_status) {
> -		xe_gt_err(gt, "CT write: non-zero status: %u\n",
> desc_status);
> -		goto corrupted;
> -	}
> -
>  	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) {
>  		u32 desc_tail = desc_read(xe, h2g, tail);
>  		u32 desc_head = desc_read(xe, h2g, head);
> +		u32 desc_status;
> +
> +		desc_status = desc_read(xe, h2g, status);
> +		if (desc_status) {
> +			xe_gt_err(gt, "CT write: non-zero status:
> %u\n", desc_status);
> +			goto corrupted;
> +		}
>  
>  		if (tail != desc_tail) {
>  			desc_write(xe, h2g, status, desc_status |
> GUC_CTB_STATUS_MISMATCH);
> @@ -1023,8 +1023,15 @@ static int h2g_write(struct xe_guc_ct *ct,
> const u32 *action, u32 len,
>  	/* Update descriptor */
>  	desc_write(xe, h2g, tail, h2g->info.tail);
>  
> -	trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1),
> full_len,
> -			     desc_read(xe, h2g, head), h2g-
> >info.tail);
> +	/*
> +	 * desc_read() performs an VRAM read which serializes the
> CPU and drains
> +	 * posted writes on dGPU platforms. Tracepoints evaluate
> arguments even
> +	 * when disabled, so guard the event to avoid adding µs-
> scale latency to
> +	 * the fast H2G submission path when tracing is not active.
> +	 */
> +	if (trace_xe_guc_ctb_h2g_enabled())
> +		trace_xe_guc_ctb_h2g(xe, gt->info.id, *(action - 1),
> full_len,
> +				     desc_read(xe, h2g, head), h2g-
> >info.tail);
>  
>  	return 0;
>  
With the typos fixed,

Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>

  parent reply	other threads:[~2026-02-26 12:47 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-18  4:33 [PATCH v3 0/3] dGPU memory optimizations Matthew Brost
2026-02-18  4:33 ` [PATCH v3 1/3] drm/xe: Split H2G and G2H into separate buffer objects Matthew Brost
2026-02-18 23:12   ` Summers, Stuart
2026-02-19  3:46     ` Matthew Brost
2026-02-24 15:58   ` Thomas Hellström
2026-02-24 16:12     ` Matthew Brost
2026-02-25 10:55       ` Thomas Hellström
2026-02-25 18:08         ` Matthew Brost
2026-02-26 12:08       ` Thomas Hellström
2026-02-18  4:33 ` [PATCH v3 2/3] drm/xe: Avoid unconditional VRAM reads in H2G path Matthew Brost
2026-02-18 23:20   ` Summers, Stuart
2026-02-26 12:47   ` Thomas Hellström [this message]
2026-02-18  4:33 ` [PATCH v3 3/3] drm/xe: Move LRC seqno to system memory to avoid slow dGPU reads Matthew Brost
2026-02-24  2:40   ` Matthew Brost
2026-02-26 12:25   ` Thomas Hellström
2026-02-26 17:11     ` Matthew Brost
2026-02-26 17:26       ` Matthew Brost
2026-02-26 17:56         ` Thomas Hellström
2026-02-26 12:43   ` Thomas Hellström
2026-02-26 16:55     ` Matthew Brost
2026-02-18  4:40 ` ✓ CI.KUnit: success for dGPU memory optimizations Patchwork
2026-02-18  5:23 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-18  6:15 ` ✗ Xe.CI.FULL: " Patchwork
2026-02-18  7:07 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev2) Patchwork
2026-02-18  7:36 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18  7:53 ` ✓ Xe.CI.FULL: " Patchwork
2026-02-18 12:29 ` ✓ CI.KUnit: success for dGPU memory optimizations (rev3) Patchwork
2026-02-18 13:09 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-18 14:08 ` ✗ Xe.CI.FULL: failure " Patchwork

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