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* [PATCH] drm/xe: Reject coh_none PAT index for CPU cached memory in madvise
@ 2026-01-29  0:01 Jia Yao
  2026-01-29  0:09 ` ✓ CI.KUnit: success for " Patchwork
                   ` (27 more replies)
  0 siblings, 28 replies; 48+ messages in thread
From: Jia Yao @ 2026-01-29  0:01 UTC (permalink / raw)
  To: intel-xe; +Cc: Jia Yao

Add validation in xe_vm_madvise_ioctl() to reject PAT indices with
XE_COH_NONE coherency mode when applied to CPU cached memory.

Using coh_none with CPU cached buffers is a security issue. When the
kernel clears pages before reallocation, the clear operation stays in
CPU cache (dirty). GPU with coh_none can bypass CPU caches and read
stale sensitive data directly from DRAM, potentially leaking data from
previously freed pages of other processes.

This aligns with the existing validation in vm_bind path
(xe_vm_bind_ioctl_validate_bo).

Signed-off-by: Jia Yao <jia.yao@intel.com>
---
 drivers/gpu/drm/xe/xe_vm_madvise.c | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index add9a6ca2390..3fbaf7d1d662 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -352,6 +352,44 @@ static void xe_madvise_details_fini(struct xe_madvise_details *details)
 	drm_pagemap_put(details->dpagemap);
 }
 
+static bool check_pat_args_are_sane(struct xe_device *xe,
+				    struct xe_vmas_in_madvise_range *madvise_range,
+				    u16 pat_index)
+{
+	u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+	int i;
+
+	/*
+	 * Using coh_none with CPU cached buffers is not allowed.
+	 * Otherwise CPU page clearing can be bypassed, which is a
+	 * security issue. GPU can directly access system memory and
+	 * bypass CPU caches, potentially reading stale sensitive data
+	 * from previously freed pages.
+	 */
+	if (coh_mode != XE_COH_NONE)
+		return true;
+
+	for (i = 0; i < madvise_range->num_vmas; i++) {
+		struct xe_vma *vma = madvise_range->vmas[i];
+		struct xe_bo *bo = xe_vma_bo(vma);
+
+		if (bo) {
+			/* BO with WB caching + COH_NONE is not allowed */
+			if (XE_IOCTL_DBG(xe, bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB))
+				return false;
+			/* Imported dma-buf without caching info, assume cached */
+			if (XE_IOCTL_DBG(xe, !bo->cpu_caching))
+				return false;
+		} else if (xe_vma_is_cpu_addr_mirror(vma) || xe_vma_is_userptr(vma)) {
+			/* System memory (userptr/SVM) is always CPU cached */
+			if (XE_IOCTL_DBG(xe, true))
+				return false;
+		}
+	}
+
+	return true;
+}
+
 static bool check_bo_args_are_sane(struct xe_vm *vm, struct xe_vma **vmas,
 				   int num_vmas, u32 atomic_val)
 {
@@ -442,6 +480,14 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 	if (err || !madvise_range.num_vmas)
 		goto madv_fini;
 
+	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
+		if (!check_pat_args_are_sane(xe, &madvise_range,
+					     args->pat_index.val)) {
+			err = -EINVAL;
+			goto free_vmas;
+		}
+	}
+
 	if (madvise_range.has_bo_vmas) {
 		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
 			if (!check_bo_args_are_sane(vm, madvise_range.vmas,
@@ -485,6 +531,7 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 err_fini:
 	if (madvise_range.has_bo_vmas)
 		drm_exec_fini(&exec);
+free_vmas:
 	kfree(madvise_range.vmas);
 	madvise_range.vmas = NULL;
 madv_fini:
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 48+ messages in thread

end of thread, other threads:[~2026-04-15 12:15 UTC | newest]

Thread overview: 48+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-29  0:01 [PATCH] drm/xe: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-01-29  0:09 ` ✓ CI.KUnit: success for " Patchwork
2026-01-29  0:49 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-29  4:35 ` [PATCH] " Matthew Brost
2026-01-29  5:51 ` [PATCH v2] " Jia Yao
2026-01-29  9:58   ` Matthew Auld
2026-01-29  6:44 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev2) Patchwork
2026-01-29  7:24 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-30 22:07 ` [PATCH v3] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-02-03  2:54   ` Lin, Shuicheng
2026-02-04 15:13   ` Souza, Jose
2026-01-30 23:05 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev3) Patchwork
2026-01-30 23:44 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-03 15:48 ` [PATCH v4] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-02-03 16:38   ` Matthew Auld
2026-02-03 16:59     ` Yao, Jia
2026-03-10 14:50   ` Mrozek, Michal
2026-02-03 16:14 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev4) Patchwork
2026-02-03 17:07 ` ✗ Xe.CI.BAT: failure " Patchwork
2026-02-04  8:47 ` ✗ Xe.CI.FULL: " Patchwork
2026-02-04 21:13 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev5) Patchwork
2026-02-04 21:47 ` ✓ Xe.CI.BAT: " Patchwork
2026-02-05 10:35 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-16  7:22 ` [PATCH v5 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and Jia Yao
2026-03-16  7:22   ` [PATCH v5 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-16 10:59     ` Matthew Auld
2026-03-16 15:29       ` Lin, Shuicheng
2026-03-16  7:22   ` [PATCH v5 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-16 11:40     ` Matthew Auld
2026-03-16  7:29 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev6) Patchwork
2026-03-16  8:18 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-16 16:42 ` [PATCH v5 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and madvise Jia Yao
2026-03-16 16:42   ` [PATCH v6 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-16 16:42   ` [PATCH v6 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-17 10:45     ` Matthew Auld
2026-03-16 21:28 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev7) Patchwork
2026-03-16 22:03 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-17 21:17 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-03-19 11:58 ` [PATCH v7 0/2] drm/xe: PAT index validation for CPU_ADDR_MIRROR and madvise Jia Yao
2026-03-19 11:58   ` [PATCH v7 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-03-19 11:58   ` [PATCH v7 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-03-19 12:24 ` ✓ CI.KUnit: success for drm/xe: Reject coh_none PAT index for CPU cached memory in madvise (rev8) Patchwork
2026-03-19 13:12 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-20 14:04 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-04-15  6:19 ` [PATCH v8 0/2] drm/xe: Reject unsafe PAT indices for CPU cached memory Jia Yao
2026-04-15  6:19   ` [PATCH v8 1/2] drm/xe/uapi: Reject coh_none PAT index for CPU cached memory in madvise Jia Yao
2026-04-15  6:19   ` [PATCH v8 2/2] drm/xe: Reject coh_none PAT index for CPU_ADDR_MIRROR Jia Yao
2026-04-15 12:15     ` Matthew Auld

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