From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 9/9] drm/i915/wm: Include .min_ddb_alloc_uv in the wm dumps
Date: Thu, 19 Mar 2026 13:40:34 +0200 [thread overview]
Message-ID: <20260319114034.7093-10-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20260319114034.7093-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We include the Y/RGB .min_ddb_alloc in the wm state change dumps.
Do the same for .min_ddb_alloc_uv, on the platforms where it is
used.
Also adjust the whitespace in the other debug prints to keep
the values for each wm level lined up across all the lines.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 30 +++++++++++++++++---
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 345767349988..4725927acfd4 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2624,7 +2624,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
struct intel_display *display = to_intel_display(plane);
drm_dbg_kms(display->drm,
- "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
+ "[PLANE:%d:%s] level %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm"
" -> %cwm0,%cwm1,%cwm2,%cwm3,%cwm4,%cwm5,%cwm6,%cwm7,%ctwm,%cswm,%cstwm\n",
plane->base.base.id, plane->base.name,
enast(old_wm->wm[0].enable), enast(old_wm->wm[1].enable),
@@ -2643,7 +2643,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
enast(new_wm->sagv.trans_wm.enable));
drm_dbg_kms(display->drm,
- "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
+ "[PLANE:%d:%s] lines %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d"
" -> %c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%3d,%c%4d\n",
plane->base.base.id, plane->base.name,
enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].lines,
@@ -2670,7 +2670,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
enast(new_wm->sagv.trans_wm.ignore_lines), new_wm->sagv.trans_wm.lines);
drm_dbg_kms(display->drm,
- "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+ "[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
plane->base.base.id, plane->base.name,
old_wm->wm[0].blocks, old_wm->wm[1].blocks,
@@ -2689,7 +2689,7 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
new_wm->sagv.trans_wm.blocks);
drm_dbg_kms(display->drm,
- "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+ "[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
plane->base.base.id, plane->base.name,
old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
@@ -2706,6 +2706,28 @@ skl_print_plane_wm_changes(struct intel_plane *plane,
new_wm->trans_wm.min_ddb_alloc,
new_wm->sagv.wm0.min_ddb_alloc,
new_wm->sagv.trans_wm.min_ddb_alloc);
+
+ if (DISPLAY_VER(display) >= 11)
+ return;
+
+ drm_dbg_kms(display->drm,
+ "[PLANE:%d:%s] min_ddb_uv %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d"
+ " -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%5d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->wm[0].min_ddb_alloc_uv, old_wm->wm[1].min_ddb_alloc_uv,
+ old_wm->wm[2].min_ddb_alloc_uv, old_wm->wm[3].min_ddb_alloc_uv,
+ old_wm->wm[4].min_ddb_alloc_uv, old_wm->wm[5].min_ddb_alloc_uv,
+ old_wm->wm[6].min_ddb_alloc_uv, old_wm->wm[7].min_ddb_alloc_uv,
+ old_wm->trans_wm.min_ddb_alloc_uv,
+ old_wm->sagv.wm0.min_ddb_alloc_uv,
+ old_wm->sagv.trans_wm.min_ddb_alloc_uv,
+ new_wm->wm[0].min_ddb_alloc_uv, new_wm->wm[1].min_ddb_alloc_uv,
+ new_wm->wm[2].min_ddb_alloc_uv, new_wm->wm[3].min_ddb_alloc_uv,
+ new_wm->wm[4].min_ddb_alloc_uv, new_wm->wm[5].min_ddb_alloc_uv,
+ new_wm->wm[6].min_ddb_alloc_uv, new_wm->wm[7].min_ddb_alloc_uv,
+ new_wm->trans_wm.min_ddb_alloc_uv,
+ new_wm->sagv.wm0.min_ddb_alloc_uv,
+ new_wm->sagv.trans_wm.min_ddb_alloc_uv);
}
static void
--
2.52.0
next prev parent reply other threads:[~2026-03-19 11:41 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-19 11:40 [PATCH 0/9] drm/i915/wm: Clean up pre-icl NV12 watermarks Ville Syrjala
2026-03-19 11:40 ` [PATCH 1/9] drm/i915/wm: Nuke is_planar from skl+ wm structures Ville Syrjala
2026-03-19 12:27 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 2/9] drm/i915/wm: Reorder the arguments to skl_allocate_plane_ddb() Ville Syrjala
2026-03-19 12:28 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 3/9] drm/i915/wm: s/skl_check_nv12_wm_level()/skl_check_wm_level_nv12()/ Ville Syrjala
2026-03-19 13:07 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 4/9] drm/i915/wm: Extract skl_allocate_plane_ddb_nv12() Ville Syrjala
2026-03-19 13:21 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 5/9] drm/i915/wm: Nuke wm->uv_wm[] Ville Syrjala
2026-03-19 14:06 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 6/9] drm/i915/wm: s/skl_print_plane_changes()/skl_print_plane_wm_changes()/ Ville Syrjala
2026-03-19 13:36 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 7/9] drm/i915/wm: Extract skl_print_plane_ddb_changes() Ville Syrjala
2026-03-19 13:38 ` Jani Nikula
2026-03-19 11:40 ` [PATCH 8/9] drm/i915/wm: Include ddb_y in skl_print_wm_changes() on pre-icl Ville Syrjala
2026-03-19 13:44 ` Jani Nikula
2026-03-19 14:03 ` Ville Syrjälä
2026-03-19 11:40 ` Ville Syrjala [this message]
2026-03-19 14:01 ` [PATCH 9/9] drm/i915/wm: Include .min_ddb_alloc_uv in the wm dumps Jani Nikula
2026-03-19 11:48 ` ✓ CI.KUnit: success for drm/i915/wm: Clean up pre-icl NV12 watermarks Patchwork
2026-03-19 12:39 ` ✓ Xe.CI.BAT: " Patchwork
2026-03-20 13:27 ` ✓ Xe.CI.FULL: " Patchwork
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