Re: [PATCH 2/9] drm/i915/wm: Reorder the arguments to skl_allocate_plane_ddb()

[Jani Nikula <jani.nikula@linux.intel.com>]

On Thu, 19 Mar 2026, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Group the ddb and data_rate together in the skl_allocate_plane_ddb()
> arguments. Upcoming changes will adjust the UV plane handling and
> keeing the ddb allocation and the data rate used to calculate it
> together will help with clarity.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 15 +++++++--------
>  1 file changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 0f99a3264f05..1664b84d0387 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1391,9 +1391,8 @@ struct skl_plane_ddb_iter {
>  
>  static void
>  skl_allocate_plane_ddb(struct skl_plane_ddb_iter *iter,
> -		       struct skl_ddb_entry *ddb,
>  		       const struct skl_wm_level *wm,
> -		       u64 data_rate)
> +		       struct skl_ddb_entry *ddb, u64 data_rate)
>  {
>  	u16 size, extra = 0;
>  
> @@ -1523,13 +1522,13 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
>  
>  		if (DISPLAY_VER(display) < 11 &&
>  		    crtc_state->nv12_planes & BIT(plane_id)) {
> -			skl_allocate_plane_ddb(&iter, ddb_y, &wm->wm[level],
> -					       crtc_state->rel_data_rate_y[plane_id]);
> -			skl_allocate_plane_ddb(&iter, ddb, &wm->uv_wm[level],
> -					       crtc_state->rel_data_rate[plane_id]);
> +			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +					       ddb_y, crtc_state->rel_data_rate_y[plane_id]);
> +			skl_allocate_plane_ddb(&iter, &wm->uv_wm[level],
> +					       ddb, crtc_state->rel_data_rate[plane_id]);
>  		} else {
> -			skl_allocate_plane_ddb(&iter, ddb, &wm->wm[level],
> -					       crtc_state->rel_data_rate[plane_id]);
> +			skl_allocate_plane_ddb(&iter, &wm->wm[level],
> +					       ddb, crtc_state->rel_data_rate[plane_id]);
>  		}
>  
>  		if (DISPLAY_VER(display) >= 30) {

-- 
Jani Nikula, Intel