[PATCH v2 00/34] drm/i915/dp_link: Unify modeset/fallback config selection

[PATCH v2 00/34] drm/i915/dp_link: Unify modeset/fallback config selection

[Imre Deak]

This is v2 of the third part of patchset [1], unifying the link
configuration selection logic used during modeset state computation and
link training fallback selection, while also adding the corresponding
KUnit tests. This constitutes patches 58–108 of [1] and, once merged,
completes the original patchset. Due to the simplifications introduced
in this version explained below, several patches from the original
patchset have been dropped.

The patchset is based on the already merged first [2] and second [3]
part of patchset [1].

For the rationale of this patchset, please refer to the parts related to
link configuration selection in the cover letter of [1].

This v2 patchset version has the following changes:
- Track the state of link config iteration in an iteration object.
  (Jani)
- Use an opaque filter object for filtering the iterated configurations
  instead of exposing configuration indices via the API. (Jani)
- Remove all parts of the API accepting or returning a configuration
  index or position. (Jani)
- Use the config iterator for fallback selection. (Jani)
- Remove the change to track link configurations via a virtual indexing
  scheme. (Ville)
- Remove the functionality to merge new link configurations for a
  connected sink changing its capabilities, allowed by patchset [4]
  already merged. (Ville)
- Use the max BW link configuration during mode validation and TBT BW
  computation, instead of using the max link limits for these.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>

[1] https://lore.kernel.org/all/20260428125233.1664668-1-imre.deak@intel.com
[2] https://lore.kernel.org/all/20260601093836.3057345-1-imre.deak@intel.com
[3] https://lore.kernel.org/all/20260616200849.3534628-1-imre.deak@intel.com
[4] https://lore.kernel.org/all/20260522160514.2628249-1-imre.deak@intel.com

Imre Deak (34):
  drm/i915/doc: Document DP link capabilities
  drm/i915/dp_link_caps: Factor out helper to get link config by index
  drm/i915/dp_link_caps: Add support for link rate, lane count iteration
    orders
  drm/i915/dp_link_caps: Add link configuration iterator
  drm/i915/dp_link_caps: Add helper to get iteration order for a
    connector
  drm/i915/dp_link_caps: Validate max link limits
  drm/i915/dp_link_caps: Add filter for enabled link configurations
  drm/i915/dp_link_caps: Re-enable link configurations after a link
    reset
  drm/i915/dp_link_caps: Re-enable link configurations after sink caps
    change
  drm/i915/dp_link_caps: Drop noupdate postfix from max link limit set
    helpers
  drm/i915/dp_link_caps: Add debugfs entry showing allowed
    configurations
  drm/i915/dp: Add link configuration filter for modeset computation
  drm/i915/dp_link_caps: Add helper to query max BW link configuration
  drm/i915/dp: Query max BW config via link_caps during mode validation
  drm/i915/dp_tunnel: Query max BW config via link_caps for BW
    computation
  drm/i915/dp_test: Use link caps for compliance link configs
  drm/i915/dp: Iterate configurations via link_caps for SST non-DSC
  drm/i915/dp: Iterate configurations via link_caps for SST DSC
  drm/i915/dp: Use link caps for eDP DSC config selection
  drm/i915/dp_mst: Use link caps for non-DSC config selection
  drm/i915/dp_mst: Use link caps for MST DSC config selection
  drm/i915/dp: Remove min/max link config limits
  drm/i915/dp_link_training: Reset the max link limits in the fallback
    code
  drm/i915/dp_link_training: Use config iterator for fallback
  drm/i915/dp_link_training: Disable failed config during fallback
  drm/i915/kunit: Enable KUnit tests
  drm/i915/kunit: Add DP link test stub
  drm/xe/kunit: Add display test config
  drm/xe/kunit: Build DP link display tests
  drm/i915/kunit: Setup DP link test context
  drm/i915/kunit: Export link training and caps funcs for testing
  drm/i915/kunit: DP link: add baseline fixed table reference test
  drm/i915/kunit: DP link: add update config tests
  drm/i915/kunit: DP link: add fallback tests

 .../intel-display/dp-link-capabilities.rst    |   11 +
 Documentation/gpu/intel-display/index.rst     |    1 +
 drivers/gpu/drm/i915/.kunitconfig             |   12 +
 drivers/gpu/drm/i915/Kconfig.debug            |   12 +
 drivers/gpu/drm/i915/Makefile                 |    2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  291 ++--
 drivers/gpu/drm/i915/display/intel_dp.h       |   11 +-
 .../gpu/drm/i915/display/intel_dp_link_caps.c |  759 ++++++++-
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  172 +-
 .../drm/i915/display/intel_dp_link_training.c |  237 +--
 .../drm/i915/display/intel_dp_link_training.h |   31 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   72 +-
 drivers/gpu/drm/i915/display/intel_dp_test.c  |  107 +-
 drivers/gpu/drm/i915/display/intel_dp_test.h  |    3 +-
 .../gpu/drm/i915/display/intel_dp_tunnel.c    |    8 +-
 drivers/gpu/drm/i915/display/tests/Makefile   |    7 +
 .../i915/display/tests/intel_dp_link_test.c   | 1412 +++++++++++++++++
 drivers/gpu/drm/xe/.gitignore                 |    1 +
 drivers/gpu/drm/xe/.kunitconfig-display       |   11 +
 drivers/gpu/drm/xe/Makefile                   |    3 +
 drivers/gpu/drm/xe/display/tests/Makefile     |   11 +
 21 files changed, 2786 insertions(+), 388 deletions(-)
 create mode 100644 Documentation/gpu/intel-display/dp-link-capabilities.rst
 create mode 100644 drivers/gpu/drm/i915/.kunitconfig
 create mode 100644 drivers/gpu/drm/i915/display/tests/Makefile
 create mode 100644 drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
 create mode 100644 drivers/gpu/drm/xe/.kunitconfig-display
 create mode 100644 drivers/gpu/drm/xe/display/tests/Makefile

-- 
2.49.1

[PATCH v2 01/34] drm/i915/doc: Document DP link capabilities

[Imre Deak]

Add documentation for the DP link capabilities interface.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../intel-display/dp-link-capabilities.rst    | 11 +++
 Documentation/gpu/intel-display/index.rst     |  1 +
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 81 +++++++++++++++++++
 3 files changed, 93 insertions(+)
 create mode 100644 Documentation/gpu/intel-display/dp-link-capabilities.rst

diff --git a/Documentation/gpu/intel-display/dp-link-capabilities.rst b/Documentation/gpu/intel-display/dp-link-capabilities.rst
new file mode 100644
index 0000000000000..331cc69d13a04
--- /dev/null
+++ b/Documentation/gpu/intel-display/dp-link-capabilities.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: MIT
+.. Copyright © 2026 Intel Corporation
+
+DisplayPort Link Capabilities
+=============================
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+   :doc: DisplayPort link capabilities
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+   :internal:
diff --git a/Documentation/gpu/intel-display/index.rst b/Documentation/gpu/intel-display/index.rst
index 6fa929d82c38c..e81f49bf20df6 100644
--- a/Documentation/gpu/intel-display/index.rst
+++ b/Documentation/gpu/intel-display/index.rst
@@ -39,6 +39,7 @@ driver. The display driver isn't an independent driver in that sense.
    frontbuffer
    hotplug
    dp-link-training
+   dp-link-capabilities
    plane
    psr
    snps-phy
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 1c34ba6c49c35..2c656c2c036cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -19,6 +19,87 @@
 #include "intel_dp.h"
 #include "intel_dp_link_caps.h"
 
+/**
+ * DOC: DisplayPort link capabilities
+ *
+ * The Intel DP link caps API tracks the supported and allowed
+ * DisplayPort link configurations for a DP encoder and its attached
+ * connectors, and provides helpers to iterate over the allowed
+ * configurations and constrain them by filtering, disabling, or
+ * limiting them to maximum link parameters.
+ *
+ * Locking
+ * -------
+ *
+ * All accesses to this API must be serialized. The only exception
+ * is intel_dp_link_caps_get_max_limits(), which allow lockless
+ * lookup. Such lookups may observe an out-of-sync &struct
+ * intel_dp_link_config tuple, i.e. a rate from one state and a lane
+ * count from another.
+ *
+ * The Intel i915/xe drivers ensure the above serialization by holding
+ * &drm_mode_config.connection_mutex and, while holding the lock,
+ * waiting for any pending asynchronous atomic commits. This also allows
+ * use of the API from the tails of asynchronous atomic commits, which
+ * cannot hold the lock.
+ *
+ * Iterating and restricting link configurations
+ * ---------------------------------------------
+ *
+ * The link configuration iterators can iterate the ``allowed
+ * configurations`` during modeset configuration selection or link
+ * training fallback handling in a configurable order.
+ *
+ * The iteration order can depend on connector type (eDP, DP SST,
+ * DP MST) and modeset-specific conditions or driver policies, such
+ * as DSC vs. non-DSC modes, power saving vs. better user experience,
+ * or policy changes after a link training failure.
+ *
+ * The configurations exposed via the iterators can be additionally
+ * constrained in the following ways:
+ *
+ * - Filtered for a given modeset based on modeset-specific conditions.
+ *   Examples for such conditions include driver policies preferring
+ *   power saving or better user experience, post-link training failure
+ *   preference changes, or sink automated test requests limiting the
+ *   usable configurations.
+ *
+ * - Disabled permanently for the connected sink. Examples of reasons
+ *   to disable a configuration include a link training failure for a
+ *   given configuration or a driver workaround preventing the use of
+ *   a particular configuration.
+ *
+ * - Limited via a maximum link rate and lane count. For example, after
+ *   a link training failure, subsequent modesets may be limited to
+ *   configurations at or below the failed parameters.
+ *
+ *   This mechanism exists for backward compatibility only. Eventually,
+ *   it will be removed in favor of relying solely on individually
+ *   disabled configurations, as described above.
+ *
+ * Terminology
+ * -----------
+ *
+ * ``Common link capabilities`` (or ``common caps``) refer to the link
+ * rates and maximum lane count supported by both the source and the
+ * sink, i.e. the intersection of their respective capabilities.
+ *
+ * ``Supported configurations`` are all configurations defined by the
+ * ``Common link capabilities``' link rates and maximum lane count.
+ *
+ * ``Disabled configurations`` are ``Supported configurations`` disabled
+ * via this API.
+ *
+ * ``Enabled configurations`` are ``Supported configurations`` that are
+ * not disabled.
+ *
+ * ``Forced configurations`` are ``Enabled configurations`` forced via
+ * forced link parameter debugfs entries.
+ *
+ * ``Allowed configurations`` are the ``Enabled configurations``, or if
+ * forcing is in effect the ``Forced configurations``, constrained by a
+ * maximum rate and lane count set via the API.
+ */
 struct intel_dp_link_caps {
 	struct intel_dp *dp;
 
-- 
2.49.1

[PATCH v2 02/34] drm/i915/dp_link_caps: Factor out helper to get link config by index

[Imre Deak]

Factor out a helper that looks up a link configuration by index.
This provides the link configuration directly, avoiding the
indirect conversion via the packed config entry.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c  | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 2c656c2c036cc..d0a863b00b458 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -235,6 +235,16 @@ static int intel_dp_link_config_lane_count(const struct intel_dp_link_config_ent
 	return 1 << lce->lane_count_exp;
 }
 
+static void
+to_intel_dp_link_config(struct intel_dp_link_caps *link_caps,
+			int config_idx, struct intel_dp_link_config *config)
+{
+	const struct intel_dp_link_config_entry *lce = &link_caps->configs[config_idx];
+
+	config->rate = intel_dp_link_config_rate(link_caps, lce);
+	config->lane_count = intel_dp_link_config_lane_count(lce);
+}
+
 static void set_max_link_limits_no_update(struct intel_dp_link_caps *link_caps,
 					  const struct intel_dp_link_config *max_link_limits)
 {
@@ -401,15 +411,15 @@ void intel_dp_link_config_get(struct intel_dp_link_caps *link_caps,
 			      int idx, int *link_rate, int *lane_count)
 {
 	struct intel_display *display = to_intel_display(link_caps->dp);
-	const struct intel_dp_link_config_entry *lce;
+	struct intel_dp_link_config config;
 
 	if (drm_WARN_ON(display->drm, idx < 0 || idx >= link_caps->num_configs))
 		idx = 0;
 
-	lce = &link_caps->configs[idx];
+	to_intel_dp_link_config(link_caps, idx, &config);
 
-	*link_rate = intel_dp_link_config_rate(link_caps, lce);
-	*lane_count = intel_dp_link_config_lane_count(lce);
+	*link_rate = config.rate;
+	*lane_count = config.lane_count;
 }
 
 int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
-- 
2.49.1

[PATCH v2 03/34] drm/i915/dp_link_caps: Add support for link rate, lane count iteration orders

[Imre Deak]

Add support for iterating configurations in either link rate/lane count
or lane count/link rate order. Both orders are required for DP SST
connector types: the former for computing the connector state during a
modeset, and the latter for selecting a fallback configuration after a
link training failure.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index d0a863b00b458..fe5a11efbe67b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -122,6 +122,13 @@ struct intel_dp_link_caps {
 		u8 lane_count_exp:INTEL_DP_LANE_COUNT_EXP_BITS;
 	} configs[INTEL_DP_MAX_LINK_CONFIGS];
 
+	/*
+	 * Indices to intel_dp_link_caps::configs[] in rate/lane count,
+	 * lane_count/rate order.
+	 */
+	u8 rate_lane_map[INTEL_DP_MAX_LINK_CONFIGS];
+	u8 lane_rate_map[INTEL_DP_MAX_LINK_CONFIGS];
+
 	/*
 	 * Forced parameters requested via debugfs. Remains set across sink
 	 * disconnects.
@@ -350,6 +357,34 @@ static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
 	       intel_dp_link_config_rate(link_caps, lce_b);
 }
 
+static int link_config_cmp_by_rate_lane(const void *a, const void *b, const void *p)
+{
+	const struct intel_dp_link_caps *link_caps = p;
+	u8 *lce_a_idx = (u8 *)a;
+	u8 *lce_b_idx = (u8 *)b;
+	const struct intel_dp_link_config_entry *lce_a = &link_caps->configs[*lce_a_idx];
+	const struct intel_dp_link_config_entry *lce_b = &link_caps->configs[*lce_b_idx];
+
+	if (lce_a->link_rate_idx != lce_b->link_rate_idx)
+		return lce_a->link_rate_idx - lce_b->link_rate_idx;
+
+	return lce_a->lane_count_exp - lce_b->lane_count_exp;
+}
+
+static int link_config_cmp_by_lane_rate(const void *a, const void *b, const void *p)
+{
+	const struct intel_dp_link_caps *link_caps = p;
+	u8 *lce_a_idx = (u8 *)a;
+	u8 *lce_b_idx = (u8 *)b;
+	const struct intel_dp_link_config_entry *lce_a = &link_caps->configs[*lce_a_idx];
+	const struct intel_dp_link_config_entry *lce_b = &link_caps->configs[*lce_b_idx];
+
+	if (lce_a->lane_count_exp != lce_b->lane_count_exp)
+		return lce_a->lane_count_exp - lce_b->lane_count_exp;
+
+	return lce_a->link_rate_idx - lce_b->link_rate_idx;
+}
+
 /* Return %true if the supported link parameters have changed. */
 bool intel_dp_link_caps_update(struct intel_dp_link_caps *link_caps,
 			       const int *rates, int num_rates, int max_lane_count)
@@ -404,6 +439,21 @@ bool intel_dp_link_caps_update(struct intel_dp_link_caps *link_caps,
 	       link_config_cmp_by_bw, NULL,
 	       intel_dp);
 
+	for (i = 0; i < link_caps->num_configs; i++) {
+		link_caps->rate_lane_map[i] = i;
+		link_caps->lane_rate_map[i] = i;
+	}
+
+	sort_r(link_caps->rate_lane_map, link_caps->num_configs,
+	       sizeof(link_caps->rate_lane_map[0]),
+	       link_config_cmp_by_rate_lane, NULL,
+	       link_caps);
+
+	sort_r(link_caps->lane_rate_map, link_caps->num_configs,
+	       sizeof(link_caps->lane_rate_map[0]),
+	       link_config_cmp_by_lane_rate, NULL,
+	       link_caps);
+
 	return link_params_changed;
 }
 
-- 
2.49.1

[PATCH v2 04/34] drm/i915/dp_link_caps: Add link configuration iterator

[Imre Deak]

Add helpers to iterate over the allowed and optionally filtered set of
link configurations in a given order.

Taking into account disabled configurations will be added later when
adding support for disabling configurations.

Use the BW order in descending direction by default.

v2:
- Keep the iteration state in an iteration object. (Jani)
- Use a filter object instead of exposing configuration indices. (Jani)
- Move changes adding helpers required to setup the iteration object to
  this patch.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 213 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_dp_link_caps.h | 106 +++++++++
 2 files changed, 319 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index fe5a11efbe67b..d46b9d505a847 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -16,6 +16,7 @@
 
 #include "intel_display_core.h"
 #include "intel_display_types.h"
+#include "intel_display_utils.h"
 #include "intel_dp.h"
 #include "intel_dp_link_caps.h"
 
@@ -146,6 +147,18 @@ struct intel_dp_link_caps {
 	 */
 	struct intel_dp_link_config max_limits;
 };
+static_assert(BITS_PER_TYPE(((struct intel_dp_link_caps_filter *)NULL)->config_mask) >=
+	      ARRAY_SIZE(((struct intel_dp_link_caps *)NULL)->configs));
+
+static struct intel_dp_link_caps_order bw_desc_config_order(void)
+{
+	struct intel_dp_link_caps_order order = {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+
+	return order;
+}
 
 /* Get length of common rates array potentially limited by max_rate. */
 int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
@@ -252,6 +265,206 @@ to_intel_dp_link_config(struct intel_dp_link_caps *link_caps,
 	config->lane_count = intel_dp_link_config_lane_count(lce);
 }
 
+static int
+iter_pos_to_idx(struct intel_dp_link_caps *link_caps,
+		struct intel_dp_link_caps_order config_order,
+		int iter_pos)
+{
+	int config_idx;
+
+	if (!in_range(iter_pos, 0, link_caps->num_configs))
+		return -1;
+
+	switch (config_order.dir) {
+	case INTEL_DP_LINK_CAPS_ORDER_DIR_ASC:
+		break;
+	case INTEL_DP_LINK_CAPS_ORDER_DIR_DESC:
+		iter_pos = link_caps->num_configs - 1 - iter_pos;
+
+		break;
+	default:
+		MISSING_CASE(config_order.dir);
+
+		return -1;
+	}
+
+	switch (config_order.key) {
+	case INTEL_DP_LINK_CAPS_ORDER_KEY_BW:
+		config_idx = iter_pos;
+
+		break;
+	case INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE:
+		config_idx = link_caps->rate_lane_map[iter_pos];
+
+		break;
+	case INTEL_DP_LINK_CAPS_ORDER_KEY_LANE_RATE:
+		config_idx = link_caps->lane_rate_map[iter_pos];
+
+		break;
+	default:
+		MISSING_CASE(config_order.key);
+
+		return -1;
+	}
+
+	return config_idx;
+}
+
+static bool iter_get_next_config(struct intel_dp_link_caps_iter *iter,
+				 struct intel_dp_link_config *config)
+{
+	while (true) {
+		int config_idx;
+
+		iter->pos++;
+
+		config_idx = iter_pos_to_idx(iter->link_caps, iter->order, iter->pos);
+		if (config_idx < 0) {
+			iter->pos = -1;
+			*config = INTEL_DP_LINK_CONFIG_NULL;
+
+			break;
+		}
+
+		if (!(BIT(config_idx) & iter->filter.config_mask))
+			continue;
+
+		to_intel_dp_link_config(iter->link_caps, config_idx, config);
+
+		break;
+	}
+
+	return iter->pos >= 0;
+}
+
+static void iter_start(struct intel_dp_link_caps_iter *iter,
+		       struct intel_dp_link_caps *link_caps,
+		       struct intel_dp_link_caps_order order,
+		       struct intel_dp_link_caps_filter filter)
+{
+	iter->link_caps = link_caps;
+	iter->pos = -1;
+	iter->order = order;
+	iter->filter = filter;
+
+	iter->get_next_config = iter_get_next_config;
+}
+
+static struct intel_dp_link_caps_filter
+calc_allowed_config_filter(struct intel_dp_link_caps *link_caps,
+			   struct intel_dp_link_caps_filter enabled_configs,
+			   const struct intel_dp_link_config *max_limits,
+			   const struct intel_dp_link_config *forced_params)
+{
+	struct intel_dp_link_caps_filter allowed_configs = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	struct intel_dp_link_caps_order order = bw_desc_config_order();
+	struct intel_dp_link_caps_iter iter;
+	struct intel_dp_link_config config;
+
+	iter_start(&iter, link_caps, order, enabled_configs);
+	for_each_dp_link_config(&iter, &config) {
+		if (forced_params->rate &&
+		    forced_params->rate != config.rate)
+			continue;
+
+		if (forced_params->lane_count &&
+		    forced_params->lane_count != config.lane_count)
+			continue;
+
+		if (config.rate > max_limits->rate)
+			continue;
+
+		if (config.lane_count > max_limits->lane_count)
+			continue;
+
+		allowed_configs.config_mask |= BIT(iter_pos_to_idx(link_caps, order, iter.pos));
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return allowed_configs;
+}
+
+/*
+ * get_allowed_config_filter - get filter for the currently allowed configs
+ * @link_caps: link capabilities state
+ *
+ * Return:
+ * Filter of link configurations allowed after applying the current
+ * maximum link limits, and further narrowing them by removing any disabled
+ * configuration and limiting to forced link parameters.
+ *
+ * See also:
+ * - intel_dp_link_caps_get_max_limits()
+ * - intel_dp_link_caps_get_forced_params()
+ */
+static struct intel_dp_link_caps_filter
+get_allowed_config_filter(struct intel_dp_link_caps *link_caps)
+{
+	struct intel_dp_link_config forced_params;
+
+	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
+
+	/* TODO: Get filter for enabled configs. */
+	return calc_allowed_config_filter(link_caps, INTEL_DP_LINK_CAPS_FILTER_ALL,
+					  &link_caps->max_limits, &forced_params);
+}
+
+void intel_dp_link_caps_iter_start(struct intel_dp_link_caps_iter *iter,
+				   struct intel_dp_link_caps *link_caps,
+				   struct intel_dp_link_caps_order order,
+				   struct intel_dp_link_caps_filter filter)
+{
+	filter.config_mask &= get_allowed_config_filter(link_caps).config_mask;
+
+	iter_start(iter, link_caps, order, filter);
+}
+
+void intel_dp_link_caps_iter_end(struct intel_dp_link_caps_iter *iter)
+{
+	memset(iter, 0, sizeof(*iter));
+}
+
+static int find_config_idx(struct intel_dp_link_caps *link_caps,
+			   struct intel_dp_link_caps_filter filter,
+			   const struct intel_dp_link_config *link_config)
+{
+	struct intel_dp_link_caps_order order = bw_desc_config_order();
+	struct intel_dp_link_config iter_config;
+	struct intel_dp_link_caps_iter iter;
+	int pos = -1;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, filter);
+	for_each_dp_link_config(&iter, &iter_config) {
+		if (iter_config.rate == link_config->rate &&
+		    iter_config.lane_count == link_config->lane_count) {
+			pos = iter.pos;
+
+			break;
+		}
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (pos < 0)
+		return pos;
+
+	return iter_pos_to_idx(link_caps, order, pos);
+}
+
+bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
+				   struct intel_dp_link_caps_filter *filter,
+				   const struct intel_dp_link_config *config)
+{
+	int idx;
+
+	idx = find_config_idx(link_caps, get_allowed_config_filter(link_caps), config);
+	if (idx < 0)
+		return false;
+
+	filter->config_mask |= BIT(idx);
+
+	return true;
+}
+
 static void set_max_link_limits_no_update(struct intel_dp_link_caps *link_caps,
 					  const struct intel_dp_link_config *max_link_limits)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index af9028e7cb987..5ea87f112c13a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -4,6 +4,7 @@
 #ifndef __INTEL_DP_LINK_CAPS_H__
 #define __INTEL_DP_LINK_CAPS_H__
 
+#include <linux/bitops.h>
 #include <linux/types.h>
 
 struct intel_connector;
@@ -11,6 +12,107 @@ struct intel_dp;
 struct intel_dp_link_caps;
 struct intel_dp_link_config;
 
+/**
+ * enum intel_dp_link_caps_order_key - key used to order configurations
+ * @INTEL_DP_LINK_CAPS_ORDER_KEY_BW:
+ *   Order configurations by bandwidth, then by link rate.
+ * @INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE:
+ *   Order configurations by link rate, then by lane count.
+ * @INTEL_DP_LINK_CAPS_ORDER_KEY_LANE_RATE:
+ *   Order configurations by lane count, then by link rate.
+ * @INTEL_DP_LINK_CAPS_ORDER_KEY_NUM:
+ *   Number of ordering keys.
+ *
+ * Selects how a caller wants the configuration table to be ordered,
+ * together with an &enum intel_dp_link_caps_order_direction, for
+ * iteration queries.
+ *
+ * See also:
+ *  - &struct intel_dp_link_caps_order
+ */
+enum intel_dp_link_caps_order_key {
+	INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
+	INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+	INTEL_DP_LINK_CAPS_ORDER_KEY_LANE_RATE,
+
+	INTEL_DP_LINK_CAPS_ORDER_KEY_NUM
+};
+
+/**
+ * enum intel_dp_link_caps_order_direction - iteration direction
+ * @INTEL_DP_LINK_CAPS_ORDER_DIR_ASC:
+ *   Iterate in ascending order according to the selected ordering key.
+ * @INTEL_DP_LINK_CAPS_ORDER_DIR_DESC:
+ *   Iterate in descending order according to the selected ordering key.
+ * @INTEL_DP_LINK_CAPS_ORDER_DIR_NUM:
+ *   Number of ordering directions.
+ *
+ * Selects the direction associated with an
+ * &enum intel_dp_link_caps_order_key for iteration queries.
+ *
+ * See also:
+ *  - &struct intel_dp_link_caps_order
+ */
+enum intel_dp_link_caps_order_direction {
+	INTEL_DP_LINK_CAPS_ORDER_DIR_ASC,
+	INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+
+	INTEL_DP_LINK_CAPS_ORDER_DIR_NUM
+};
+
+/**
+ * struct intel_dp_link_caps_order - configuration ordering
+ * @key:
+ *   Key used to order configurations.
+ * @dir:
+ *   Direction of the selected ordering.
+ *
+ * Describes an iteration order for link configurations.
+ *
+ * See also:
+ *  - for_each_dp_link_config()
+ */
+struct intel_dp_link_caps_order {
+	enum intel_dp_link_caps_order_key key;
+	enum intel_dp_link_caps_order_direction dir;
+};
+
+struct intel_dp_link_caps_filter {
+	u32 config_mask;
+};
+
+#define INTEL_DP_LINK_CAPS_FILTER_NONE	\
+	((struct intel_dp_link_caps_filter){ .config_mask = 0 })
+#define INTEL_DP_LINK_CAPS_FILTER_ALL	\
+	((struct intel_dp_link_caps_filter){ .config_mask = (u32)-1 })
+
+struct intel_dp_link_caps_iter {
+	struct intel_dp_link_caps *link_caps;
+	int pos;
+	struct intel_dp_link_caps_order order;
+	struct intel_dp_link_caps_filter filter;
+
+	bool (*get_next_config)(struct intel_dp_link_caps_iter *iter,
+				struct intel_dp_link_config *config);
+};
+
+/**
+ * for_each_dp_link_config - iterate allowed link configurations
+ * @__iter:
+ *   &struct intel_dp_link_caps_iter being iterated
+ * @__config:
+ *   pointer to &struct intel_dp_link_config filled for each match
+ */
+#define for_each_dp_link_config(__iter, __config) \
+	while ((__iter)->get_next_config((__iter), (__config)))
+
+void intel_dp_link_caps_iter_start(struct intel_dp_link_caps_iter *iter,
+				   struct intel_dp_link_caps *link_caps,
+				   struct intel_dp_link_caps_order order,
+				   struct intel_dp_link_caps_filter filter);
+
+void intel_dp_link_caps_iter_end(struct intel_dp_link_caps_iter *iter);
+
 int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
 				   int max_rate);
 int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
@@ -29,6 +131,10 @@ int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
 void intel_dp_link_config_get(struct intel_dp_link_caps *link_caps,
 			      int idx, int *link_rate, int *lane_count);
 
+bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
+				   struct intel_dp_link_caps_filter *filter,
+				   const struct intel_dp_link_config *config);
+
 void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
 				       struct intel_dp_link_config *max_link_limits);
 bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
-- 
2.49.1

[PATCH v2 05/34] drm/i915/dp_link_caps: Add helper to get iteration order for a connector

[Imre Deak]

Add helper to select the link configuration iteration order for a
connector during state computation and fallback selection. This keeps
the connector-specific ordering policy in the link caps module.

v2: Add helper to get the order for fallback selection as well.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 50 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  5 ++
 2 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index d46b9d505a847..36895dd9d6c81 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -160,6 +160,56 @@ static struct intel_dp_link_caps_order bw_desc_config_order(void)
 	return order;
 }
 
+static enum intel_dp_link_caps_order_key
+connector_compute_order_key(bool is_mst)
+{
+	if (is_mst)
+		return INTEL_DP_LINK_CAPS_ORDER_KEY_BW;
+	else
+		return INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE;
+}
+
+static enum intel_dp_link_caps_order_key
+connector_fallback_order_key(bool is_mst)
+{
+	if (is_mst)
+		return INTEL_DP_LINK_CAPS_ORDER_KEY_BW;
+	else
+		return INTEL_DP_LINK_CAPS_ORDER_KEY_LANE_RATE;
+}
+
+static enum intel_dp_link_caps_order_direction
+connector_compute_order_dir(bool is_mst, bool use_max_params)
+{
+	if (is_mst || use_max_params)
+		return INTEL_DP_LINK_CAPS_ORDER_DIR_DESC;
+	else
+		return INTEL_DP_LINK_CAPS_ORDER_DIR_ASC;
+}
+
+struct intel_dp_link_caps_order
+intel_dp_link_caps_connector_compute_order(struct intel_connector *connector)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct intel_dp_link_caps_order order = {
+		.key = connector_compute_order_key(connector->mst.dp),
+		.dir = connector_compute_order_dir(connector->mst.dp, intel_dp->use_max_params)
+	};
+
+	return order;
+}
+
+struct intel_dp_link_caps_order
+intel_dp_link_caps_connector_fallback_order(bool is_mst)
+{
+	struct intel_dp_link_caps_order order = {
+		.key = connector_fallback_order_key(is_mst),
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	};
+
+	return order;
+}
+
 /* Get length of common rates array potentially limited by max_rate. */
 int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
 				   int max_rate)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 5ea87f112c13a..79aca74ad9eee 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -113,6 +113,11 @@ void intel_dp_link_caps_iter_start(struct intel_dp_link_caps_iter *iter,
 
 void intel_dp_link_caps_iter_end(struct intel_dp_link_caps_iter *iter);
 
+struct intel_dp_link_caps_order
+intel_dp_link_caps_connector_compute_order(struct intel_connector *connector);
+struct intel_dp_link_caps_order
+intel_dp_link_caps_connector_fallback_order(bool is_mst);
+
 int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
 				   int max_rate);
 int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
-- 
2.49.1

[PATCH v2 06/34] drm/i915/dp_link_caps: Validate max link limits

[Imre Deak]

Add validation in intel_dp_link_caps_set_max_limits() to ensure that
the new maximum rate and lane count leave at least one allowed
configuration.

The validation takes disabled configurations and active forced
parameters into account. Disabled configurations are not supported yet,
so that part has no effect for now.

At the moment this validation is also performed by the link training
fallback code, but that will be removed later, leaving only the link
caps module to perform the validation added in this patch.

v2: Rebase on changes using a filter object instead of a mask of
    configuration indices.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 28 ++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 36895dd9d6c81..5976e85bb2729 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -558,6 +558,26 @@ void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
 	*max_link_limits = link_caps->max_limits;
 }
 
+static bool max_link_limits_valid(struct intel_dp_link_caps *link_caps,
+				  const struct intel_dp_link_config *max_link_limits)
+{
+	struct intel_dp_link_caps_filter allowed_configs;
+	struct intel_dp_link_config forced_params;
+
+	if (max_link_limits->lane_count > INTEL_DP_MAX_LANE_COUNT ||
+	    !is_power_of_2(max_link_limits->lane_count))
+		return false;
+
+	/* TODO: Validate max_link_limits->rate against the source supported rates. */
+
+	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
+	/* TODO: Get filter for enabled configs. */
+	allowed_configs = calc_allowed_config_filter(link_caps, INTEL_DP_LINK_CAPS_FILTER_ALL,
+						     max_link_limits, &forced_params);
+
+	return allowed_configs.config_mask != 0;
+}
+
 /**
  * intel_dp_link_caps_set_max_limits - set the current maximum link limits
  * @link_caps: link capabilities state
@@ -566,6 +586,10 @@ void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
  * Set the current maximum rate and lane count limits to @max_link_limits,
  * constraining the set of allowed configurations.
  *
+ * The new limits must leave at least one configuration allowed: the limits
+ * must not be below the currently active forced parameters or below all the
+ * configurations that remain after disabled configurations are excluded.
+ *
  * Unlike intel_dp_link_caps_get_max_limits(), the caller must serialize
  * this call against concurrent queries and updates to @link_caps, in line
  * with the rest of the API.
@@ -578,9 +602,11 @@ void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
 bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
 				       const struct intel_dp_link_config *max_link_limits)
 {
+	if (!max_link_limits_valid(link_caps, max_link_limits))
+		return false;
+
 	set_max_link_limits_no_update(link_caps, max_link_limits);
 
-	/* TODO: validate max_link_limits */
 	return true;
 }
 
-- 
2.49.1

[PATCH v2 07/34] drm/i915/dp_link_caps: Add filter for enabled link configurations

[Imre Deak]

Add a filter for enabled link configurations to the link capability
state.

This allows fallback code to disable only the configuration that failed
link training, instead of constraining later modesets via maximum link
rate or lane count. The code only needs to exclude the failed
configuration from the allowed set; all other supported configurations
remain available.

Use the filter when computing the allowed configuration set and when
validating maximum link limits.

Follow-up changes will switch the fallback code to disable individual
configurations through this filter.

v2:
- Rebase on changes using a filter object instead of a mask of
  configuration indices.
- Track the enabled configurations instead of the disabled ones.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 38 +++++++++++++++++--
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 5976e85bb2729..03e40e8d24fb6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -130,6 +130,37 @@ struct intel_dp_link_caps {
 	u8 rate_lane_map[INTEL_DP_MAX_LINK_CONFIGS];
 	u8 lane_rate_map[INTEL_DP_MAX_LINK_CONFIGS];
 
+	/*
+	 * Filter of configurations enabled for the current sink
+	 * connection.
+	 *
+	 * Each bit in the filter's configuration mask corresponds to a
+	 * configuration index in the intel_dp_link_caps::configs[] array.
+	 *
+	 * All configurations start out enabled in the filter after a
+	 * new sink is connected. Users disable configurations afterwards
+	 * via the link caps API. All configurations get re-enabled
+	 * internally in the following cases:
+	 * - when forcing a link rate or lane count
+	 * - when intel_dp_link_caps_update(reset=true) is called after
+	 *   a new sink is connected
+	 * - when intel_dp_link_caps_update(reset=false) with changed
+	 *   link capabilities is called
+	 * - when intel_dp_link_caps_reset() is called after a new sink
+	 *   is connected
+	 */
+	struct intel_dp_link_caps_filter enabled_configs;
+
+	/*
+	 * Allowed configurations are the supported configurations defined by
+	 * config_table.rates and config_table.max_lane_count, constrained by
+	 * config_table.enabled_configs and the forced_params and
+	 * max_limits values below.
+	 *
+	 * See get_allowed_config_filter() for the filter of these
+	 * configurations.
+	 */
+
 	/*
 	 * Forced parameters requested via debugfs. Remains set across sink
 	 * disconnects.
@@ -454,8 +485,7 @@ get_allowed_config_filter(struct intel_dp_link_caps *link_caps)
 
 	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
 
-	/* TODO: Get filter for enabled configs. */
-	return calc_allowed_config_filter(link_caps, INTEL_DP_LINK_CAPS_FILTER_ALL,
+	return calc_allowed_config_filter(link_caps, link_caps->enabled_configs,
 					  &link_caps->max_limits, &forced_params);
 }
 
@@ -571,8 +601,7 @@ static bool max_link_limits_valid(struct intel_dp_link_caps *link_caps,
 	/* TODO: Validate max_link_limits->rate against the source supported rates. */
 
 	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
-	/* TODO: Get filter for enabled configs. */
-	allowed_configs = calc_allowed_config_filter(link_caps, INTEL_DP_LINK_CAPS_FILTER_ALL,
+	allowed_configs = calc_allowed_config_filter(link_caps, link_caps->enabled_configs,
 						     max_link_limits, &forced_params);
 
 	return allowed_configs.config_mask != 0;
@@ -1095,6 +1124,7 @@ struct intel_dp_link_caps *intel_dp_link_caps_init(struct intel_dp *intel_dp)
 		return NULL;
 
 	link_caps->dp = intel_dp;
+	link_caps->enabled_configs = INTEL_DP_LINK_CAPS_FILTER_ALL;
 
 	return link_caps;
 }
-- 
2.49.1

[PATCH v2 08/34] drm/i915/dp_link_caps: Re-enable link configurations after a link reset

[Imre Deak]

Re-enable link configurations after the link is reset via a call
to intel_dp_link_caps_reset(), allowing a subsequent modeset to
use all the link configurations of a sink newly connected or an already
connected sink changing its capabilities.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_caps.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 03e40e8d24fb6..667d2e55cea19 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -561,6 +561,12 @@ static void reset_max_link_limits_no_update(struct intel_dp_link_caps *link_caps
 	set_max_link_limits_no_update(link_caps, &max_link_limits);
 }
 
+static void reset_max_link_limits_reenable_all(struct intel_dp_link_caps *link_caps)
+{
+	link_caps->enabled_configs = INTEL_DP_LINK_CAPS_FILTER_ALL;
+	reset_max_link_limits_no_update(link_caps);
+}
+
 /**
  * intel_dp_link_caps_get_max_limits - get the current maximum link limits
  * @link_caps: link capabilities state
@@ -824,7 +830,7 @@ int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
 void intel_dp_link_caps_reset(struct intel_dp_link_caps *link_caps)
 {
 	/* TODO: Update the maximum link information. */
-	reset_max_link_limits_no_update(link_caps);
+	reset_max_link_limits_reenable_all(link_caps);
 }
 
 static int i915_dp_force_link_rate_show(struct seq_file *m, void *data)
-- 
2.49.1

[PATCH v2 09/34] drm/i915/dp_link_caps: Re-enable link configurations after sink caps change

[Imre Deak]

Re-enable link configurations after sink capabilities change or the link
got reset before updating the link capabilities (due to an RX_CAP_CHANGED
HPD IRQ for the currently connected sink, or a new sink getting
connected).

This makes resetting the link explicitly by calling
intel_dp_link_caps_reset() subsequently redundant; keep the existing
behavior wrt. this for now, adding only a TODO: to remove the explicit
reset.

While at it add documentation for intel_dp_link_caps_update().

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       |  8 +++-
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 37 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  3 +-
 3 files changed, 43 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6e3fa6662cbef..23001541283b4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -701,7 +701,8 @@ static bool intel_dp_set_common_link_params(struct intel_dp *intel_dp)
 	intel_dp_get_common_rates(intel_dp, common_rates, &num_common_rates);
 	if (intel_dp_link_caps_update(intel_dp->link.caps,
 				      common_rates, num_common_rates,
-				      intel_dp_get_max_common_lane_count(intel_dp)))
+				      intel_dp_get_max_common_lane_count(intel_dp),
+				      intel_dp->reset_link_params))
 		params_changed = true;
 
 	return params_changed;
@@ -3652,6 +3653,11 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp,
 
 void intel_dp_reset_link_params(struct intel_dp *intel_dp)
 {
+	/*
+	 * TODO: Remove the following reset of link capabilities, as
+	 * this isn't needed after intel_dp_link_caps_update(reset=true)
+	 * was called.
+	 */
 	intel_dp_link_caps_reset(intel_dp->link.caps);
 	intel_dp->link.mst_probed_lane_count = 0;
 	intel_dp->link.mst_probed_rate = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 667d2e55cea19..de520bd423d59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -709,14 +709,42 @@ static int link_config_cmp_by_lane_rate(const void *a, const void *b, const void
 	return lce_a->link_rate_idx - lce_b->link_rate_idx;
 }
 
-/* Return %true if the supported link parameters have changed. */
+/**
+ * intel_dp_link_caps_update - rebuild the supported link configuration state
+ * @link_caps: link capabilities state
+ * @rates: supported common link rates
+ * @num_rates: number of entries in @rates
+ * @max_lane_count: supported maximum lane count
+ * @reset: reset limits and disabled configs
+ *
+ * Rebuild the supported link configuration state from @rates and
+ * @max_lane_count.
+ *
+ * If @reset is %true, reset the maximum link limits to the maximum
+ * supported rate and lane count, and re-enable all configurations.
+ *
+ * This function is called regularly, at least after a sink is connected,
+ * but it may also be called later whenever the sink capabilities may have
+ * changed, for example in response to HPD IRQ / RX_CAP_CHANGED signaling.
+ *
+ * In the Intel driver this function is currently called whenever the
+ * connector detect handler runs, after reading the sink capabilities. This
+ * may change if those capabilities are cached until the sink is
+ * disconnected, or until RX_CAP_CHANGED is signaled. In any case, this
+ * function should be called whenever the sink capabilities were read out
+ * and may have changed.
+ *
+ * Returns:
+ * - %true if the link capabilities have changed, %false otherwise.
+ */
 bool intel_dp_link_caps_update(struct intel_dp_link_caps *link_caps,
-			       const int *rates, int num_rates, int max_lane_count)
+			       const int *rates, int num_rates, int max_lane_count,
+			       bool reset)
 {
 	struct intel_dp *intel_dp = link_caps->dp;
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_dp_link_config_entry *lce;
-	bool link_params_changed = false;
+	bool link_params_changed = reset;
 	int num_common_lane_configs;
 	int i;
 	int j;
@@ -778,6 +806,9 @@ bool intel_dp_link_caps_update(struct intel_dp_link_caps *link_caps,
 	       link_config_cmp_by_lane_rate, NULL,
 	       link_caps);
 
+	if (link_params_changed)
+		reset_max_link_limits_reenable_all(link_caps);
+
 	return link_params_changed;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 79aca74ad9eee..dcbde890809bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -147,7 +147,8 @@ bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
 void intel_dp_link_caps_reset_max_limits(struct intel_dp_link_caps *link_caps);
 
 bool intel_dp_link_caps_update(struct intel_dp_link_caps *link_caps,
-			       const int *rates, int num_rates, int max_lane_count);
+			       const int *rates, int num_rates, int max_lane_count,
+			       bool reset);
 void intel_dp_link_caps_reset(struct intel_dp_link_caps *link_caps);
 
 void intel_dp_link_caps_debugfs_add(struct intel_connector *connector);
-- 
2.49.1

[PATCH v2 10/34] drm/i915/dp_link_caps: Drop noupdate postfix from max link limit set helpers

[Imre Deak]

There is no need to update any maximum link information when updating
the max link limits, so drop the related noupdate postfix from the
helpers setting the max link limits.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_caps.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index de520bd423d59..3ef678d47c71b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -545,26 +545,26 @@ bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
 	return true;
 }
 
-static void set_max_link_limits_no_update(struct intel_dp_link_caps *link_caps,
-					  const struct intel_dp_link_config *max_link_limits)
+static void set_max_link_limits(struct intel_dp_link_caps *link_caps,
+				const struct intel_dp_link_config *max_link_limits)
 {
 	link_caps->max_limits = *max_link_limits;
 }
 
-static void reset_max_link_limits_no_update(struct intel_dp_link_caps *link_caps)
+static void reset_max_link_limits(struct intel_dp_link_caps *link_caps)
 {
 	struct intel_dp_link_config max_link_limits = {
 		.rate = intel_dp_max_common_rate(link_caps),
 		.lane_count = intel_dp_link_caps_max_common_lane_count(link_caps),
 	};
 
-	set_max_link_limits_no_update(link_caps, &max_link_limits);
+	set_max_link_limits(link_caps, &max_link_limits);
 }
 
 static void reset_max_link_limits_reenable_all(struct intel_dp_link_caps *link_caps)
 {
 	link_caps->enabled_configs = INTEL_DP_LINK_CAPS_FILTER_ALL;
-	reset_max_link_limits_no_update(link_caps);
+	reset_max_link_limits(link_caps);
 }
 
 /**
@@ -640,7 +640,7 @@ bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
 	if (!max_link_limits_valid(link_caps, max_link_limits))
 		return false;
 
-	set_max_link_limits_no_update(link_caps, max_link_limits);
+	set_max_link_limits(link_caps, max_link_limits);
 
 	return true;
 }
@@ -654,7 +654,7 @@ bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
  */
 void intel_dp_link_caps_reset_max_limits(struct intel_dp_link_caps *link_caps)
 {
-	reset_max_link_limits_no_update(link_caps);
+	reset_max_link_limits(link_caps);
 }
 
 static int intel_dp_link_config_bw(struct intel_dp_link_caps *link_caps,
@@ -860,7 +860,6 @@ int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
  */
 void intel_dp_link_caps_reset(struct intel_dp_link_caps *link_caps)
 {
-	/* TODO: Update the maximum link information. */
 	reset_max_link_limits_reenable_all(link_caps);
 }
 
-- 
2.49.1

[PATCH v2 11/34] drm/i915/dp_link_caps: Add debugfs entry showing allowed configurations

[Imre Deak]

Add a debugfs entry showing the currently allowed link configurations
in the connector's iteration order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 3ef678d47c71b..4482e1f9d6cd8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -1123,6 +1123,43 @@ static int i915_dp_max_lane_count_show(void *data, u64 *val)
 }
 DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n");
 
+static int intel_dp_allowed_link_configs_show(struct seq_file *m, void *data)
+{
+	struct intel_connector *connector = to_intel_connector(m->private);
+	struct intel_display *display = to_intel_display(connector);
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
+	int err;
+	int i;
+
+	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
+	if (err)
+		return err;
+
+	intel_dp_flush_connector_commits(connector);
+
+	i = 0;
+	intel_dp_link_caps_iter_start(&iter,
+				      link_caps,
+				      intel_dp_link_caps_connector_compute_order(connector),
+				      INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &link_config) {
+		seq_printf(m, "%s%dx%d",
+			   i ? " " : "",
+			   link_config.lane_count, link_config.rate);
+		i++;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
+
+	seq_putc(m, '\n');
+
+	return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(intel_dp_allowed_link_configs);
 
 /**
  * intel_dp_link_caps_debugfs_add - add link caps debugfs files for a connector
@@ -1149,6 +1186,9 @@ void intel_dp_link_caps_debugfs_add(struct intel_connector *connector)
 
 	debugfs_create_file("i915_dp_max_lane_count", 0444, root,
 			    connector, &i915_dp_max_lane_count_fops);
+
+	debugfs_create_file("intel_dp_allowed_link_configs", 0444, root,
+			    connector, &intel_dp_allowed_link_configs_fops);
 }
 
 struct intel_dp_link_caps *intel_dp_link_caps_init(struct intel_dp *intel_dp)
-- 
2.49.1

[PATCH v2 12/34] drm/i915/dp: Add link configuration filter for modeset computation

[Imre Deak]

Add link_config_filter to link_config_limits to track the set of valid
link configurations during modeset state computation. Keep the existing
min/max rate and lane count limits for now, until all users are
converted to use the configuration filter.

Add the helpers required to select the maximum configuration from the
currently allowed configuration set. This will be used by follow-up
changes as well to query the maximum link configuration without having
to iterate the configurations.

v2:
- Rebase on changes using a filter object instead of a mask of
  configuration indices.
- Rebase on changes using an iteration object.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 42 +++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dp.h       | 11 +++++
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 46 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  6 +++
 4 files changed, 102 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 23001541283b4..bc333bc9296b2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2577,6 +2577,20 @@ bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector,
 					       bw_overhead_flags);
 }
 
+bool
+intel_dp_get_connector_max_link_config(struct intel_connector *connector,
+				       const struct link_config_limits *limits,
+				       struct intel_dp_link_config *max_link_config)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+
+	return intel_dp_link_caps_get_max_config(link_caps, order.key, limits->link_config_filter,
+						 max_link_config);
+}
+
 /*
  * Calculate the output link min, max bpp values in limits based on the pipe bpp
  * range, crtc_state and dsc mode. Return true on success.
@@ -2593,6 +2607,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector,
 		&crtc_state->hw.adjusted_mode;
 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct intel_dp_link_config max_link_config;
 	int max_link_bpp_x16;
 
 	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
@@ -2622,14 +2637,17 @@ intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector,
 
 	limits->link.max_bpp_x16 = max_link_bpp_x16;
 
+	if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config))
+		return false;
+
 	drm_dbg_kms(display->drm,
-		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n",
+		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max link %dx%d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n",
 		    encoder->base.base.id, encoder->base.name,
 		    crtc->base.base.id, crtc->base.name,
 		    adjusted_mode->crtc_clock,
 		    str_on_off(dsc),
-		    limits->max_lane_count,
-		    limits->max_rate,
+		    max_link_config.lane_count,
+		    max_link_config.rate,
 		    limits->pipe.max_bpp,
 		    FXP_Q4_ARGS(limits->link.min_bpp_x16),
 		    FXP_Q4_ARGS(limits->link.max_bpp_x16));
@@ -2680,10 +2698,15 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			       struct link_config_limits *limits)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 
+	/*
+	 * Remove the following min/max rate and lane count setup, once
+	 * all users are converted to use link_config_mask instead.
+	 */
 	limits->min_rate = intel_dp_min_link_rate(intel_dp);
 	limits->max_rate = intel_dp_max_link_rate(intel_dp);
 
@@ -2692,6 +2715,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
 	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
 
+	limits->link_config_filter = INTEL_DP_LINK_CAPS_FILTER_ALL;
+
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
 		/*
@@ -2755,6 +2780,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 			    crtc_state->pipe_bpp, limits->pipe.max_bpp);
 
 	if (is_mst || intel_dp->use_max_params) {
+		struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+		struct intel_dp_link_config max_config;
+
 		/*
 		 * For MST we always configure max link bw - the spec doesn't
 		 * seem to suggest we should do otherwise.
@@ -2768,6 +2796,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		 */
 		limits->min_lane_count = limits->max_lane_count;
 		limits->min_rate = limits->max_rate;
+
+		if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config))
+			return false;
+
+		if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, &max_config))
+			return false;
+
+		limits->link_config_filter = new_filter;
 	}
 
 	intel_dp_test_compute_config(intel_dp, crtc_state, limits);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 02b691df67555..13872b8c4975e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -8,6 +8,8 @@
 
 #include <linux/types.h>
 
+#include "intel_dp_link_caps.h"
+
 enum intel_output_format;
 enum pipe;
 enum port;
@@ -22,11 +24,17 @@ struct intel_crtc_state;
 struct intel_digital_port;
 struct intel_display;
 struct intel_dp;
+struct intel_dp_link_config;
 struct intel_encoder;
 
 struct link_config_limits {
+	/*
+	 * TODO: Remove the following min/max rate and lane count limits
+	 * once all users are converted to use link_config_mask instead.
+	 */
 	int min_rate, max_rate;
 	int min_lane_count, max_lane_count;
+	struct intel_dp_link_caps_filter link_config_filter;
 	struct {
 		/* Uncompressed DSC input or link output bpp in 1 bpp units */
 		int min_bpp, max_bpp;
@@ -144,6 +152,9 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
 				 u8 dsc_max_bpc);
 int intel_dp_compute_min_compressed_bpp_x16(struct intel_connector *connector,
 					    enum intel_output_format output_format);
+bool intel_dp_get_connector_max_link_config(struct intel_connector *connector,
+					    const struct link_config_limits *limits,
+					    struct intel_dp_link_config *max_link_config);
 bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector,
 				  int link_clock, int lane_count,
 				  int mode_clock, int mode_hdisplay,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 4482e1f9d6cd8..d00bb8047de2f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -504,6 +504,52 @@ void intel_dp_link_caps_iter_end(struct intel_dp_link_caps_iter *iter)
 	memset(iter, 0, sizeof(*iter));
 }
 
+/**
+ * intel_dp_link_caps_get_max_config - get the maximum config in a given order
+ * @link_caps: link capabilities state
+ * @order_key: ordering key used to rank candidate configurations
+ * @filter: filter for candidate configurations
+ * @max_config: returned maximum link configuration
+ *
+ * Find the last configuration among the currently allowed
+ * configurations filtered by @filter in the iteration order
+ * selected by @order_key, and store it in @max_config.
+ *
+ * See also:
+ * - &enum intel_dp_link_caps_order_key
+ *
+ * Returns:
+ * %true if a maximum config is returned
+ * %false otherwise.
+ */
+bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
+				       enum intel_dp_link_caps_order_key order_key,
+				       struct intel_dp_link_caps_filter filter,
+				       struct intel_dp_link_config *max_config)
+{
+	struct intel_dp_link_caps_order order = {
+		.key = order_key,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC
+	};
+	struct intel_dp_link_config iter_config;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, filter);
+	for_each_dp_link_config(&iter, &iter_config) {
+		found = true;
+		break;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found)
+		return false;
+
+	*max_config = iter_config;
+
+	return true;
+}
+
 static int find_config_idx(struct intel_dp_link_caps *link_caps,
 			   struct intel_dp_link_caps_filter filter,
 			   const struct intel_dp_link_config *link_config)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index dcbde890809bc..6dd2ce64e24ed 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -29,6 +29,7 @@ struct intel_dp_link_config;
  *
  * See also:
  *  - &struct intel_dp_link_caps_order
+ *  - intel_dp_link_caps_get_max_config()
  */
 enum intel_dp_link_caps_order_key {
 	INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
@@ -140,6 +141,11 @@ bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
 				   struct intel_dp_link_caps_filter *filter,
 				   const struct intel_dp_link_config *config);
 
+bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
+				       enum intel_dp_link_caps_order_key order_key,
+				       struct intel_dp_link_caps_filter filter,
+				       struct intel_dp_link_config *max_config);
+
 void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
 				       struct intel_dp_link_config *max_link_limits);
 bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
-- 
2.49.1

[PATCH v2 13/34] drm/i915/dp_link_caps: Add helper to query max BW link configuration

[Imre Deak]

Add a helper to query the link configuration among the currently allowed
configurations with the maximum link BW.

This will be used by follow-up changes to unify the max BW link config
query during mode validation and TBT BW calculation.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c   | 17 +++++++++++++++++
 .../gpu/drm/i915/display/intel_dp_link_caps.h   |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index d00bb8047de2f..c209c8a935234 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -550,6 +550,23 @@ bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
 	return true;
 }
 
+/**
+ * intel_dp_link_caps_get_max_bw_config - get maximum BW link configuration
+ * @link_caps: link capabilities state
+ * @max_config: returned maximum link configuration
+ *
+ * Return the maximum BW link configuration among the currently
+ * allowed configurations.
+ */
+void intel_dp_link_caps_get_max_bw_config(struct intel_dp_link_caps *link_caps,
+					  struct intel_dp_link_config *max_config)
+{
+	if (!intel_dp_link_caps_get_max_config(link_caps,
+					       bw_desc_config_order().key, INTEL_DP_LINK_CAPS_FILTER_ALL,
+					       max_config))
+		*max_config = INTEL_DP_LINK_CONFIG_NULL;
+}
+
 static int find_config_idx(struct intel_dp_link_caps *link_caps,
 			   struct intel_dp_link_caps_filter filter,
 			   const struct intel_dp_link_config *link_config)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 6dd2ce64e24ed..667bd70b2396d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -146,6 +146,9 @@ bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
 				       struct intel_dp_link_caps_filter filter,
 				       struct intel_dp_link_config *max_config);
 
+void intel_dp_link_caps_get_max_bw_config(struct intel_dp_link_caps *link_caps,
+					  struct intel_dp_link_config *max_config);
+
 void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
 				       struct intel_dp_link_config *max_link_limits);
 bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
-- 
2.49.1

[PATCH v2 14/34] drm/i915/dp: Query max BW config via link_caps during mode validation

[Imre Deak]

Query the maximum link BW configuration during mode validation and MST
link probing directly from intel_dp_link_caps_get_max_bw_config(),
instead of using the intel_dp_max_link_rate() and
intel_dp_max_lane_count() helpers.

This makes the max BW link config query uniform across mode validation
and TBT BW calculation, and allows unexporting the
intel_dp_max_link_rate()/intel_dp_max_lane_count() helpers.

v2: Use the max BW link configuration, instead of the max link limits.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c     | 10 ++++++----
 drivers/gpu/drm/i915/display/intel_dp.h     |  2 --
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++++++----
 3 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index bc333bc9296b2..b10bbbf0f49bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -354,7 +354,7 @@ static int intel_dp_get_max_common_lane_count(struct intel_dp *intel_dp)
 	return min3(source_max, sink_max, lane_max);
 }
 
-int intel_dp_max_lane_count(struct intel_dp *intel_dp)
+static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 {
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	struct intel_dp_link_config max_link_limits;
@@ -1331,6 +1331,7 @@ intel_dp_mode_valid_format(struct intel_connector *connector,
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	enum intel_output_format output_format;
 	int max_rate, mode_rate, max_lanes, max_link_clock;
+	struct intel_dp_link_config max_bw_config;
 	u16 dsc_max_compressed_bpp = 0;
 	enum drm_mode_status status;
 	bool dsc = false;
@@ -1343,8 +1344,9 @@ intel_dp_mode_valid_format(struct intel_connector *connector,
 
 	output_format = intel_dp_output_format(connector, sink_format);
 
-	max_link_clock = intel_dp_max_link_rate(intel_dp);
-	max_lanes = intel_dp_max_lane_count(intel_dp);
+	intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config);
+	max_link_clock = max_bw_config.rate;
+	max_lanes = max_bw_config.lane_count;
 
 	max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
 
@@ -1538,7 +1540,7 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
 	intel_dp_link_caps_print_common_rates(intel_dp->link.caps);
 }
 
-int
+static int
 intel_dp_max_link_rate(struct intel_dp *intel_dp)
 {
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 13872b8c4975e..9564369ea4852 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -111,8 +111,6 @@ void intel_dp_mst_suspend(struct intel_display *display);
 void intel_dp_mst_resume(struct intel_display *display);
 int intel_dp_rate_limit_len(const int *rates, int len, int max_rate);
 int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
-int intel_dp_max_link_rate(struct intel_dp *intel_dp);
-int intel_dp_max_lane_count(struct intel_dp *intel_dp);
 int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
 int intel_dp_rate_index(const int *rates, int len, int rate);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index ecc90e8faee11..e113c9e60e67d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -47,6 +47,7 @@
 #include "intel_display_wa.h"
 #include "intel_dp.h"
 #include "intel_dp_hdcp.h"
+#include "intel_dp_link_caps.h"
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
 #include "intel_dp_test.h"
@@ -1476,6 +1477,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 	unsigned long bw_overhead_flags =
 		DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK;
 	int min_link_bpp_x16 = fxp_q4_from_int(18);
+	struct intel_dp_link_config max_bw_config;
 	static bool supports_dsc;
 	int ret;
 	bool dsc = false;
@@ -1508,8 +1510,9 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 		min_link_bpp_x16 = intel_dp_compute_min_compressed_bpp_x16(connector,
 									   INTEL_OUTPUT_FORMAT_RGB);
 
-	max_link_clock = intel_dp_max_link_rate(intel_dp);
-	max_lanes = intel_dp_max_lane_count(intel_dp);
+	intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config);
+	max_link_clock = max_bw_config.rate;
+	max_lanes = max_bw_config.lane_count;
 
 	max_rate = intel_dp_max_link_data_rate(intel_dp,
 					       max_link_clock, max_lanes);
@@ -2135,14 +2138,19 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
  */
 void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
 {
-	int link_rate = intel_dp_max_link_rate(intel_dp);
-	int lane_count = intel_dp_max_lane_count(intel_dp);
+	struct intel_dp_link_config max_bw_config;
+	int link_rate;
+	int lane_count;
 	u8 rate_select;
 	u8 link_bw;
 
 	if (intel_dp->link.active)
 		return;
 
+	intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config);
+	link_rate = max_bw_config.rate;
+	lane_count = max_bw_config.lane_count;
+
 	if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))
 		return;
 
-- 
2.49.1

[PATCH v2 15/34] drm/i915/dp_tunnel: Query max BW config via link_caps for BW computation

[Imre Deak]

Query the maximum link BW configuration via the link caps interface to
compute the available TBT bandwidth. Unlike the max common link params
used so far for this, the max BW config also accounts for any forced
link parameters.

This makes the max BW link config query uniform across mode validation
and TBT BW calculation, and allows unexporting the
intel_dp_link_caps_max_common_lane_count() helper.

v2: Use the max BW link configuration, instead of the max link limits.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_caps.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dp_link_caps.h | 1 -
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c    | 8 +++++---
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index c209c8a935234..8dfb7f4f703bc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -290,7 +290,7 @@ void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps)
 	drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
 }
 
-int intel_dp_link_caps_max_common_lane_count(struct intel_dp_link_caps *link_caps)
+static int intel_dp_link_caps_max_common_lane_count(struct intel_dp_link_caps *link_caps)
 {
 	return link_caps->max_lane_count;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 667bd70b2396d..07002d745d384 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -125,7 +125,6 @@ int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
 int intel_dp_link_caps_common_rate_idx(struct intel_dp_link_caps *link_caps, int rate);
 int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps);
 int intel_dp_link_caps_num_common_rates(struct intel_dp_link_caps *link_caps);
-int intel_dp_link_caps_max_common_lane_count(struct intel_dp_link_caps *link_caps);
 
 void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 76e9753766b9f..49fa4c9699b61 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -58,10 +58,12 @@ static int kbytes_to_mbits(int kbytes)
 static int get_current_link_bw(struct intel_dp *intel_dp)
 {
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	int rate = intel_dp_max_common_rate(link_caps);
-	int lane_count = intel_dp_link_caps_max_common_lane_count(link_caps);
+	struct intel_dp_link_config max_bw_config;
 
-	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
+	intel_dp_link_caps_get_max_bw_config(link_caps, &max_bw_config);
+
+	return intel_dp_max_link_data_rate(intel_dp, max_bw_config.rate,
+						     max_bw_config.lane_count);
 }
 
 static int __update_tunnel_state(struct intel_dp *intel_dp, bool force_sink_update)
-- 
2.49.1

[PATCH v2 16/34] drm/i915/dp_test: Use link caps for compliance link configs

[Imre Deak]

Use the link caps configuration mask when applying DP compliance test
link parameters during state computation.

Preserve the legacy behavior of falling back to all configurations with
the requested lane count if the requested rate and lane count pair is
not allowed.

In case no valid configuration is found fail the modeset.

v2:
- Rebase on changes using a filter object instead of a mask of
  configuration indices.
- Rebase on changes using an iteration object.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c      |  3 +-
 drivers/gpu/drm/i915/display/intel_dp_test.c | 96 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_test.h |  3 +-
 3 files changed, 99 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b10bbbf0f49bf..42bb1c7622525 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2808,7 +2808,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		limits->link_config_filter = new_filter;
 	}
 
-	intel_dp_test_compute_config(intel_dp, crtc_state, limits);
+	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
+		return false;
 
 	return intel_dp_compute_config_link_bpp_limits(connector,
 						       crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c
index da7632536dace..ec7fa690910bb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_test.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_test.c
@@ -28,11 +28,92 @@ void intel_dp_test_reset(struct intel_dp *intel_dp)
 	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
 }
 
+static bool set_filter_for_lane_count(struct intel_connector *connector,
+				      struct intel_dp_link_caps *link_caps,
+				      int lane_count,
+				      struct link_config_limits *limits)
+{
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+	struct intel_dp_link_caps_iter iter;
+	bool found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		if (link_config.lane_count != lane_count)
+			continue;
+
+		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
+		found = true;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	if (!found)
+		return false;
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
+static bool set_filter_for_link_config(struct intel_connector *connector,
+				       struct intel_dp_link_caps *link_caps,
+				       const struct intel_dp_link_config *link_params,
+				       struct link_config_limits *limits)
+{
+	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
+
+	if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, link_params))
+		return false;
+
+	limits->link_config_filter = new_filter;
+
+	return true;
+}
+
+static bool set_filter_for_link_params(struct intel_connector *connector,
+				       int link_rate, int lane_count,
+				       struct link_config_limits *limits)
+{
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
+	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_display *display = to_intel_display(intel_dp);
+	struct intel_dp_link_config requested_config;
+
+	requested_config.rate = link_rate;
+	requested_config.lane_count = lane_count;
+
+	if (set_filter_for_link_config(connector, link_caps, &requested_config, limits))
+		return true;
+
+	/*
+	 * Preserve the legacy behavior: if the requested (rate, lane_count)
+	 * combination is not an allowed config, fall back to all configs
+	 * matching the requested lane count.
+	 *
+	 * TODO: Recheck whether this behavior is actually correct.
+	 */
+	if (set_filter_for_lane_count(connector, link_caps, lane_count, limits))
+		return true;
+
+	drm_dbg_kms(display->drm,
+		    "[ENCODER:%d:%s] Invalid autotest link config parameters: %dx%d\n",
+		    encoder->base.base.id, encoder->base.name,
+		    requested_config.lane_count,
+		    requested_config.rate);
+
+	return false;
+}
+
 /* Adjust link config limits based on compliance test requests. */
-void intel_dp_test_compute_config(struct intel_dp *intel_dp,
+bool intel_dp_test_compute_config(struct intel_connector *connector,
 				  struct intel_crtc_state *pipe_config,
 				  struct link_config_limits *limits)
 {
+	struct intel_dp *intel_dp = intel_attached_dp(connector);
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	struct intel_display *display = to_intel_display(intel_dp);
 
@@ -51,6 +132,11 @@ void intel_dp_test_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
 		int index;
 
+		/*
+		 * TODO: Remove the following min/max link limit setup
+		 * after converting to use the link configuration filter
+		 * instead in limits.
+		 */
 		/* Validate the compliance test data since max values
 		 * might have changed due to link train fallback.
 		 */
@@ -65,7 +151,15 @@ void intel_dp_test_compute_config(struct intel_dp *intel_dp,
 			limits->min_lane_count = intel_dp->compliance.test_lane_count;
 			limits->max_lane_count = intel_dp->compliance.test_lane_count;
 		}
+
+		if (!set_filter_for_link_params(connector,
+						intel_dp->compliance.test_link_rate,
+						intel_dp->compliance.test_lane_count,
+						limits))
+			return false;
 	}
+
+	return true;
 }
 
 /* Compliance test status bits  */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.h b/drivers/gpu/drm/i915/display/intel_dp_test.h
index dcc167e4c7f65..a08f37a63dc9a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_test.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_test.h
@@ -6,6 +6,7 @@
 
 #include <linux/types.h>
 
+struct intel_connector;
 struct intel_crtc_state;
 struct intel_display;
 struct intel_dp;
@@ -13,7 +14,7 @@ struct link_config_limits;
 
 void intel_dp_test_reset(struct intel_dp *intel_dp);
 void intel_dp_test_request(struct intel_dp *intel_dp);
-void intel_dp_test_compute_config(struct intel_dp *intel_dp,
+bool intel_dp_test_compute_config(struct intel_connector *connector,
 				  struct intel_crtc_state *pipe_config,
 				  struct link_config_limits *limits);
 bool intel_dp_test_phy(struct intel_dp *intel_dp);
-- 
2.49.1

[PATCH v2 17/34] drm/i915/dp: Iterate configurations via link_caps for SST non-DSC

[Imre Deak]

Use the link caps configuration iterator for DP SST link configuration
computation for non-DSC mode. This is a step towards unifying
configuration selection and iteration across connector types and between
compute and fallback paths.

The iteration preserves the DP SST connector rate/lane ordering used by
the current code.

This also allows removing the now unused common rate count helper.

v2:
- Rebase on changes using a filter object instead of a mask of
  configuration indices.
- Rebase on changes using an iteration object.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 49 ++++++++++++-------------
 1 file changed, 24 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 42bb1c7622525..108298186d121 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1754,43 +1754,42 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 				  const struct drm_connector_state *conn_state,
 				  const struct link_config_limits *limits)
 {
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	int bpp, clock = intel_dp_mode_clock(pipe_config, conn_state);
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
-	int link_rate, link_avail;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	int link_avail;
 
 	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);
 	     bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);
 	     bpp -= 2 * 3) {
 		int link_bpp_x16 =
 			intel_dp_output_format_link_bpp_x16(pipe_config->output_format, bpp);
+		struct intel_dp_link_config link_config;
+		struct intel_dp_link_caps_iter iter;
 
-		for (i = 0; i < intel_dp_link_caps_num_common_rates(intel_dp->link.caps); i++) {
-			link_rate = intel_dp_common_rate(link_caps, i);
-			if (link_rate < limits->min_rate ||
-			    link_rate > limits->max_rate)
-				continue;
-
-			for (lane_count = limits->min_lane_count;
-			     lane_count <= limits->max_lane_count;
-			     lane_count <<= 1) {
-				const struct drm_display_mode *adjusted_mode =
+		intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+		for_each_dp_link_config(&iter, &link_config) {
+			const struct drm_display_mode *adjusted_mode =
 					&pipe_config->hw.adjusted_mode;
-				int mode_rate =
-					intel_dp_link_required(link_rate, lane_count,
-							       clock, adjusted_mode->hdisplay,
-							       link_bpp_x16, 0);
+			int mode_rate;
 
-				link_avail = intel_dp_max_link_data_rate(intel_dp,
-									 link_rate,
-									 lane_count);
+			mode_rate = intel_dp_link_required(link_config.rate,
+							   link_config.lane_count,
+							   clock, adjusted_mode->hdisplay,
+							   link_bpp_x16, 0);
 
-				if (mode_rate <= link_avail) {
-					pipe_config->lane_count = lane_count;
-					pipe_config->pipe_bpp = bpp;
-					pipe_config->port_clock = link_rate;
+			link_avail = intel_dp_max_link_data_rate(intel_dp,
+								 link_config.rate,
+								 link_config.lane_count);
 
-					return 0;
-				}
+			if (mode_rate <= link_avail) {
+				pipe_config->lane_count = link_config.lane_count;
+				pipe_config->pipe_bpp = bpp;
+				pipe_config->port_clock = link_config.rate;
+
+				return 0;
 			}
 		}
 	}
-- 
2.49.1

[PATCH v2 18/34] drm/i915/dp: Iterate configurations via link_caps for SST DSC

[Imre Deak]

Use the link caps configuration iterator for DP SST link configuration
computation for DSC mode. This is a step towards unifying configuration
selection and iteration across connector types and between compute and
fallback paths.

The iteration preserves the DP SST connector rate/lane ordering used by
the current code.

This also allows removing the now unused common rate count helper.

v2:
- Rebase on changes using a filter object instead of a mask of
  configuration indices.
- Rebase on changes using an iteration object.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 92 +++++++++----------
 .../gpu/drm/i915/display/intel_dp_link_caps.c |  5 -
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  1 -
 3 files changed, 44 insertions(+), 54 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 108298186d121..c6920afb50902 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1988,60 +1988,56 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp,
 				   const struct link_config_limits *limits,
 				   int dsc_bpp_x16)
 {
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
-	int link_rate, lane_count;
-	int i;
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_compute_order(connector);
+	struct intel_dp_link_config link_config;
+	struct intel_dp_link_caps_iter iter;
 
-	for (i = 0; i < intel_dp_link_caps_num_common_rates(intel_dp->link.caps); i++) {
-		link_rate = intel_dp_common_rate(link_caps, i);
-		if (link_rate < limits->min_rate || link_rate > limits->max_rate)
-			continue;
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
+	for_each_dp_link_config(&iter, &link_config) {
+		/*
+		 * FIXME: intel_dp_mtp_tu_compute_config() requires
+		 * ->lane_count and ->port_clock set before we know
+		 * they'll work. If we end up failing altogether,
+		 * they'll remain in crtc state. This shouldn't matter,
+		 * as we'd then bail out from compute config, but it's
+		 * just ugly.
+		 */
+		pipe_config->lane_count = link_config.lane_count;
+		pipe_config->port_clock = link_config.rate;
 
-		for (lane_count = limits->min_lane_count;
-		     lane_count <= limits->max_lane_count;
-		     lane_count <<= 1) {
+		if (drm_dp_is_uhbr_rate(link_config.rate)) {
+			int ret;
 
-			/*
-			 * FIXME: intel_dp_mtp_tu_compute_config() requires
-			 * ->lane_count and ->port_clock set before we know
-			 * they'll work. If we end up failing altogether,
-			 * they'll remain in crtc state. This shouldn't matter,
-			 * as we'd then bail out from compute config, but it's
-			 * just ugly.
-			 */
-			pipe_config->lane_count = lane_count;
-			pipe_config->port_clock = link_rate;
+			ret = intel_dp_mtp_tu_compute_config(intel_dp,
+							     pipe_config,
+							     conn_state,
+							     dsc_bpp_x16,
+							     dsc_bpp_x16,
+							     0, true);
+			if (ret)
+				continue;
+		} else {
+			unsigned long bw_overhead_flags =
+				pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
+			int line_slice_count =
+				intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);
 
-			if (drm_dp_is_uhbr_rate(link_rate)) {
-				int ret;
-
-				ret = intel_dp_mtp_tu_compute_config(intel_dp,
-								     pipe_config,
-								     conn_state,
-								     dsc_bpp_x16,
-								     dsc_bpp_x16,
-								     0, true);
-				if (ret)
-					continue;
-			} else {
-				unsigned long bw_overhead_flags =
-					pipe_config->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
-				int line_slice_count =
-					intel_dsc_line_slice_count(&pipe_config->dsc.slice_config);
-
-				if (!is_bw_sufficient_for_dsc_config(intel_dp,
-								     link_rate, lane_count,
-								     adjusted_mode->crtc_clock,
-								     adjusted_mode->hdisplay,
-								     line_slice_count,
-								     dsc_bpp_x16,
-								     bw_overhead_flags))
-					continue;
-			}
-
-			return 0;
+			if (!is_bw_sufficient_for_dsc_config(intel_dp,
+							     link_config.rate,
+							     link_config.lane_count,
+							     adjusted_mode->crtc_clock,
+							     adjusted_mode->hdisplay,
+							     line_slice_count,
+							     dsc_bpp_x16,
+							     bw_overhead_flags))
+				continue;
 		}
+
+		return 0;
 	}
 
 	return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 8dfb7f4f703bc..4ce35b76afee6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -273,11 +273,6 @@ int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps)
 	return intel_dp_common_rate(link_caps, link_caps->num_rates - 1);
 }
 
-int intel_dp_link_caps_num_common_rates(struct intel_dp_link_caps *link_caps)
-{
-	return link_caps->num_rates;
-}
-
 void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps)
 {
 	struct intel_display *display = to_intel_display(link_caps->dp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 07002d745d384..3c7e6c8d1ab1d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -124,7 +124,6 @@ int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
 int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
 int intel_dp_link_caps_common_rate_idx(struct intel_dp_link_caps *link_caps, int rate);
 int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps);
-int intel_dp_link_caps_num_common_rates(struct intel_dp_link_caps *link_caps);
 
 void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps);
 
-- 
2.49.1

[PATCH v2 19/34] drm/i915/dp: Use link caps for eDP DSC config selection

[Imre Deak]

Use the link caps helper to select the maximum eDP link configuration
for DSC computation, instead of using the separate max rate and lane
count limits, which may not form a valid configuration after individual
configs are disabled by fallback.

This is a step towards unifying configuration selection and iteration
across connector types and between compute and fallback paths.

The state computation should likely consider all allowed configurations,
as noted in the code comment; for now keep the existing eDP DSC behavior
of selecting the maximum configuration determined by the eDP connector
rate / lane config iteration order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c6920afb50902..79e3334d24332 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2248,7 +2248,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
 				      int pipe_bpp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	const struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	int min_bpp_x16, max_bpp_x16, bpp_step_x16;
 	int bpp_x16;
 	int ret;
@@ -2260,8 +2260,19 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
 	max_bpp_x16 = align_max_compressed_bpp_x16(connector, pipe_config->output_format,
 						   pipe_bpp, max_bpp_x16);
 	if (intel_dp_is_edp(intel_dp)) {
-		pipe_config->port_clock = limits->max_rate;
-		pipe_config->lane_count = limits->max_lane_count;
+		struct intel_dp_link_config max_link_config;
+
+		/*
+		 * FIXME: Clarify why eDP does not use the regular SST BW
+		 * check and instead always uses the maximum link config,
+		 * regardless of intel_dp::use_max_params. Then unify this eDP
+		 * path with the regular DP path.
+		 */
+		if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config))
+			return -EINVAL;
+
+		pipe_config->port_clock = max_link_config.rate;
+		pipe_config->lane_count = max_link_config.lane_count;
 
 		pipe_config->dsc.compressed_bpp_x16 = max_bpp_x16;
 
-- 
2.49.1

[PATCH v2 20/34] drm/i915/dp_mst: Use link caps for non-DSC config selection

[Imre Deak]

Use the link caps helper to select the maximum MST link configuration
for non-DSC computation, instead of using the separate max rate and lane
count limits, which may not form a valid configuration after individual
configs are disabled by fallback.

This is a step towards unifying configuration selection and iteration
across connector types and between compute and fallback paths.

In some cases all configurations should be considered, as noted in the
code comment; for now keep the existing behavior of selecting the
maximum bandwidth configuration as determined by the MST connector's BW
config iteration order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e113c9e60e67d..47b8563f85e4d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -445,8 +445,20 @@ static int mst_stream_compute_link_config(struct intel_dp *intel_dp,
 					  struct drm_connector_state *conn_state,
 					  const struct link_config_limits *limits)
 {
-	crtc_state->lane_count = limits->max_lane_count;
-	crtc_state->port_clock = limits->max_rate;
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_config max_link_config;
+
+	/*
+	 * FIXME: Use a proper iteration over the link configurations, instead
+	 * of using only the max BW config. For instance UHBR rate configs may
+	 * have additional limitations over non-UHBR ones, due to the DSC DPT
+	 * bpp maximum limit.
+	 */
+	if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config))
+		return -EINVAL;
+
+	crtc_state->port_clock = max_link_config.rate;
+	crtc_state->lane_count = max_link_config.lane_count;
 
 	/*
 	 * FIXME: allocate the BW according to link_bpp, which in the case of
-- 
2.49.1

[PATCH v2 21/34] drm/i915/dp_mst: Use link caps for MST DSC config selection

[Imre Deak]

Use the link caps helper to select the maximum DP MST link configuration
for DSC computation, instead of using the separate max rate and lane
count limits, which may not form a valid configuration after individual
configs are disabled by fallback.

Also look up the maximum rate for state computation via the configuration
mask when checking the DSC hblank expansion quirk.

This is a step towards unifying configuration selection and iteration
across connector types and between compute and fallback paths.

The state computation should likely consider all allowed configurations,
as noted in the code comment; for now keep the existing DP MST DSC
behavior of selecting the maximum BW configuration determined by the MST
connector BW config iteration order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 40 +++++++++++++++++----
 1 file changed, 33 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 47b8563f85e4d..df6e54508e5d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -477,6 +477,7 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct intel_dp_link_config max_link_config;
 
 	crtc_state->pipe_bpp = limits->pipe.max_bpp;
 
@@ -484,8 +485,17 @@ static int mst_stream_dsc_compute_link_config(struct intel_dp *intel_dp,
 		    "DSC Sink supported compressed min bpp " FXP_Q4_FMT " compressed max bpp " FXP_Q4_FMT "\n",
 		    FXP_Q4_ARGS(limits->link.min_bpp_x16), FXP_Q4_ARGS(limits->link.max_bpp_x16));
 
-	crtc_state->lane_count = limits->max_lane_count;
-	crtc_state->port_clock = limits->max_rate;
+	/*
+	 * FIXME: Use a proper iteration over the link configurations, instead
+	 * of using only the max BW config. For instance UHBR rate configs may
+	 * have additional limitations over non-UHBR ones, due to the DSC DPT
+	 * bpp maximum limit.
+	 */
+	if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config))
+		return -EINVAL;
+
+	crtc_state->port_clock = max_link_config.rate;
+	crtc_state->lane_count = max_link_config.lane_count;
 
 	return intel_dp_mtp_tu_compute_config(intel_dp, crtc_state, conn_state,
 					      limits->link.min_bpp_x16,
@@ -501,6 +511,20 @@ static int mode_hblank_period_ns(const struct drm_display_mode *mode)
 				     mode->crtc_clock);
 }
 
+static int get_connector_max_rate(const struct intel_connector *connector,
+				  const struct link_config_limits *limits)
+{
+	struct intel_dp *intel_dp = intel_attached_dp((struct intel_connector *)connector);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	struct intel_dp_link_config max_link_config;
+
+	intel_dp_link_caps_get_max_config(link_caps,
+					  INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+					  limits->link_config_filter, &max_link_config);
+
+	return max_link_config.rate;
+}
+
 static bool
 hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
 				 const struct intel_crtc_state *crtc_state,
@@ -511,11 +535,13 @@ hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
 	bool is_uhbr_sink = connector->mst.dp &&
 			    drm_dp_128b132b_supported(connector->mst.dp->dpcd);
 	int hblank_limit = is_uhbr_sink ? 500 : 300;
+	int max_rate;
 
 	if (!connector->dp.dsc_hblank_expansion_quirk)
 		return false;
 
-	if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
+	max_rate = get_connector_max_rate(connector, limits);
+	if (is_uhbr_sink && !drm_dp_is_uhbr_rate(max_rate))
 		return false;
 
 	if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
@@ -537,6 +563,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp,
 	struct intel_display *display = to_intel_display(connector);
 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	int min_bpp_x16 = limits->link.min_bpp_x16;
+	int max_rate;
 
 	if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
 		return true;
@@ -563,11 +590,10 @@ adjust_limits_for_dsc_hblank_expansion_quirk(struct intel_dp *intel_dp,
 		return true;
 	}
 
-	drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate);
-
-	if (limits->max_rate < 540000)
+	max_rate = get_connector_max_rate(connector, limits);
+	if (max_rate < 540000)
 		min_bpp_x16 = fxp_q4_from_int(13);
-	else if (limits->max_rate < 810000)
+	else if (max_rate < 810000)
 		min_bpp_x16 = fxp_q4_from_int(10);
 
 	if (limits->link.min_bpp_x16 >= min_bpp_x16)
-- 
2.49.1

[PATCH v2 22/34] drm/i915/dp: Remove min/max link config limits

[Imre Deak]

Remove the min/max rate and lane count fields from struct
link_config_limits after all state computation is converted to use the
configuration filter.

A simple min/max range cannot fully describe the valid configuration
set once individual configurations are disabled (for example by
fallback), as it may allow combinations that are not actually valid.
The configuration filter, on the other hand, always represents a
consistent set of valid configurations.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c       | 86 -------------------
 drivers/gpu/drm/i915/display/intel_dp.h       |  6 --
 .../gpu/drm/i915/display/intel_dp_link_caps.c |  4 +-
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  2 -
 drivers/gpu/drm/i915/display/intel_dp_test.c  | 23 -----
 5 files changed, 2 insertions(+), 119 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 79e3334d24332..16b3ab9732120 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -354,44 +354,6 @@ static int intel_dp_get_max_common_lane_count(struct intel_dp *intel_dp)
 	return min3(source_max, sink_max, lane_max);
 }
 
-static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
-{
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	struct intel_dp_link_config max_link_limits;
-	struct intel_dp_link_config forced_params;
-	int lane_count;
-
-	intel_dp_link_caps_get_max_limits(link_caps, &max_link_limits);
-	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
-
-	if (forced_params.lane_count)
-		lane_count = forced_params.lane_count;
-	else
-		lane_count = max_link_limits.lane_count;
-
-	switch (lane_count) {
-	case 1:
-	case 2:
-	case 4:
-		return lane_count;
-	default:
-		MISSING_CASE(lane_count);
-		return 1;
-	}
-}
-
-static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
-{
-	struct intel_dp_link_config forced_params;
-
-	intel_dp_link_caps_get_forced_params(intel_dp->link.caps, &forced_params);
-
-	if (forced_params.lane_count)
-		return forced_params.lane_count;
-
-	return 1;
-}
-
 int intel_dp_link_bw_overhead(int link_clock, int lane_count, int hdisplay,
 			      int dsc_slice_count, int bpp_x16, unsigned long flags)
 {
@@ -1540,39 +1502,6 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
 	intel_dp_link_caps_print_common_rates(intel_dp->link.caps);
 }
 
-static int
-intel_dp_max_link_rate(struct intel_dp *intel_dp)
-{
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	struct intel_dp_link_config max_link_limits;
-	struct intel_dp_link_config forced_params;
-	int len;
-
-	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
-
-	if (forced_params.rate)
-		return forced_params.rate;
-
-	intel_dp_link_caps_get_max_limits(link_caps, &max_link_limits);
-	len = intel_dp_common_len_rate_limit(link_caps, max_link_limits.rate);
-
-	return intel_dp_common_rate(link_caps, len - 1);
-}
-
-static int
-intel_dp_min_link_rate(struct intel_dp *intel_dp)
-{
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	struct intel_dp_link_config forced_params;
-
-	intel_dp_link_caps_get_forced_params(intel_dp->link.caps, &forced_params);
-
-	if (forced_params.rate)
-		return forced_params.rate;
-
-	return intel_dp_common_rate(link_caps, 0);
-}
-
 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
@@ -2711,18 +2640,6 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 
-	/*
-	 * Remove the following min/max rate and lane count setup, once
-	 * all users are converted to use link_config_mask instead.
-	 */
-	limits->min_rate = intel_dp_min_link_rate(intel_dp);
-	limits->max_rate = intel_dp_max_link_rate(intel_dp);
-
-	limits->min_rate = min(limits->min_rate, limits->max_rate);
-
-	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
-	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
-
 	limits->link_config_filter = INTEL_DP_LINK_CAPS_FILTER_ALL;
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
@@ -2802,9 +2719,6 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 		 * configuration, and typically on older panels these
 		 * values correspond to the native resolution of the panel.
 		 */
-		limits->min_lane_count = limits->max_lane_count;
-		limits->min_rate = limits->max_rate;
-
 		if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config))
 			return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 9564369ea4852..0ec519fa12368 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -28,12 +28,6 @@ struct intel_dp_link_config;
 struct intel_encoder;
 
 struct link_config_limits {
-	/*
-	 * TODO: Remove the following min/max rate and lane count limits
-	 * once all users are converted to use link_config_mask instead.
-	 */
-	int min_rate, max_rate;
-	int min_lane_count, max_lane_count;
 	struct intel_dp_link_caps_filter link_config_filter;
 	struct {
 		/* Uncompressed DSC input or link output bpp in 1 bpp units */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 4ce35b76afee6..766dc9a98e05a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -242,8 +242,8 @@ intel_dp_link_caps_connector_fallback_order(bool is_mst)
 }
 
 /* Get length of common rates array potentially limited by max_rate. */
-int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
-				   int max_rate)
+static int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
+					  int max_rate)
 {
 	return intel_dp_rate_limit_len(link_caps->rates,
 				       link_caps->num_rates, max_rate);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 3c7e6c8d1ab1d..bb785c15c91f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -119,8 +119,6 @@ intel_dp_link_caps_connector_compute_order(struct intel_connector *connector);
 struct intel_dp_link_caps_order
 intel_dp_link_caps_connector_fallback_order(bool is_mst);
 
-int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
-				   int max_rate);
 int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
 int intel_dp_link_caps_common_rate_idx(struct intel_dp_link_caps *link_caps, int rate);
 int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c
index ec7fa690910bb..0551a1ce60d39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_test.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_test.c
@@ -114,7 +114,6 @@ bool intel_dp_test_compute_config(struct intel_connector *connector,
 				  struct link_config_limits *limits)
 {
 	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	struct intel_display *display = to_intel_display(intel_dp);
 
 	/* For DP Compliance we override the computed bpp for the pipe */
@@ -130,28 +129,6 @@ bool intel_dp_test_compute_config(struct intel_connector *connector,
 
 	/* Use values requested by Compliance Test Request */
 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
-		int index;
-
-		/*
-		 * TODO: Remove the following min/max link limit setup
-		 * after converting to use the link configuration filter
-		 * instead in limits.
-		 */
-		/* Validate the compliance test data since max values
-		 * might have changed due to link train fallback.
-		 */
-		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
-					       intel_dp->compliance.test_lane_count)) {
-			index = intel_dp_link_caps_common_rate_idx(link_caps,
-								   intel_dp->compliance.test_link_rate);
-			if (index >= 0) {
-				limits->min_rate = intel_dp->compliance.test_link_rate;
-				limits->max_rate = intel_dp->compliance.test_link_rate;
-			}
-			limits->min_lane_count = intel_dp->compliance.test_lane_count;
-			limits->max_lane_count = intel_dp->compliance.test_lane_count;
-		}
-
 		if (!set_filter_for_link_params(connector,
 						intel_dp->compliance.test_link_rate,
 						intel_dp->compliance.test_lane_count,
-- 
2.49.1

[PATCH v2 23/34] drm/i915/dp_link_training: Reset the max link limits in the fallback code

[Imre Deak]

The target maximum rate/lane count selected by the fallback logic may
exceed the current link_caps max_limits' rate/lane count, the latter of
which are used as a limit by the lookup functions when filtering allowed
configurations. To ensure the fallback search finds all relevant
candidates, temporarily reset the link_caps max_limits to the maximum
common supported capabilities.

After the fallback search completes, set the link_caps max_limits to the
configuration selected by the fallback logic, as before, determining
the allowed configurations for a subsequent modeset.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../drm/i915/display/intel_dp_link_training.c | 39 ++++++++++++++++---
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index b521dd11b62a7..7fdcc299daea5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1960,10 +1960,12 @@ static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crt
 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 						   const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	struct intel_dp_link_config max_link_limits;
 	int new_link_rate;
 	int new_lane_count;
+	int err = -1;
 
 	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
 		lt_dbg(intel_dp, DP_PHY_DPRX,
@@ -1972,14 +1974,32 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 		return 0;
 	}
 
+	/*
+	 * Temporarily reset the max link limit before selecting the fallback
+	 * config.
+	 *
+	 * After fallback, the current logic narrows the allowed configurations
+	 * to the selected config's rate and lane count. That can make a later
+	 * fallback candidate fall outside the current max_limit, so reset it
+	 * before searching.
+	 *
+	 * TODO: Constrain the allowed configurations by only disabling individual
+	 * configurations and remove setting maximum link parameters.
+	 */
+	intel_dp_link_caps_get_max_limits(link_caps, &max_link_limits);
+	intel_dp_link_caps_reset_max_limits(link_caps);
+
 	if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
-		return -1;
+		goto out_restore_max_limits;
 
 	if (intel_dp_is_edp(intel_dp) &&
 	    !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) {
 		lt_dbg(intel_dp, DP_PHY_DPRX,
 		       "Retrying Link training for eDP with same parameters\n");
-		return 0;
+
+		err = 0;
+
+		goto out_restore_max_limits;
 	}
 
 	lt_dbg(intel_dp, DP_PHY_DPRX,
@@ -1990,10 +2010,19 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 	max_link_limits.rate = new_link_rate;
 	max_link_limits.lane_count = new_lane_count;
 
-	/* TODO: handle an update failure */
-	intel_dp_link_caps_set_max_limits(link_caps, &max_link_limits);
+	err = 0;
 
-	return 0;
+out_restore_max_limits:
+	/*
+	 * Shouldn't fail: setting max_limits can only fail if they drop below
+	 * the optionally forced rate/lane-count parameters, but the reduced
+	 * config was chosen to satisfy those constraints.
+	 */
+	if (drm_WARN_ON(display->drm,
+			!intel_dp_link_caps_set_max_limits(link_caps, &max_link_limits)))
+		err = -1;
+
+	return err;
 }
 
 static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,
-- 
2.49.1

[PATCH v2 24/34] drm/i915/dp_link_training: Use config iterator for fallback

[Imre Deak]

Switch the fallback loop to use the link configuration iterator to
select a fallback configuration.

This also allows unexporting and removing from the link caps interface
all the common link rate query helpers and the helpers that accept or
return a link configuration index.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c |  45 +-----
 .../gpu/drm/i915/display/intel_dp_link_caps.h |   9 --
 .../drm/i915/display/intel_dp_link_training.c | 143 +++++-------------
 3 files changed, 39 insertions(+), 158 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 766dc9a98e05a..c947e6511fbc5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -249,7 +249,7 @@ static int intel_dp_common_len_rate_limit(struct intel_dp_link_caps *link_caps,
 				       link_caps->num_rates, max_rate);
 }
 
-int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index)
+static int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index)
 {
 	struct intel_display *display = to_intel_display(link_caps->dp);
 
@@ -260,15 +260,8 @@ int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index)
 	return link_caps->rates[index];
 }
 
-int intel_dp_link_caps_common_rate_idx(struct intel_dp_link_caps *link_caps, int rate)
-{
-	return intel_dp_rate_index(link_caps->rates,
-				   link_caps->num_rates,
-				   rate);
-}
-
 /* Theoretical max between source and sink */
-int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps)
+static int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps)
 {
 	return intel_dp_common_rate(link_caps, link_caps->num_rates - 1);
 }
@@ -870,40 +863,6 @@ bool intel_dp_link_caps_update(struct intel_dp_link_caps *link_caps,
 	return link_params_changed;
 }
 
-void intel_dp_link_config_get(struct intel_dp_link_caps *link_caps,
-			      int idx, int *link_rate, int *lane_count)
-{
-	struct intel_display *display = to_intel_display(link_caps->dp);
-	struct intel_dp_link_config config;
-
-	if (drm_WARN_ON(display->drm, idx < 0 || idx >= link_caps->num_configs))
-		idx = 0;
-
-	to_intel_dp_link_config(link_caps, idx, &config);
-
-	*link_rate = config.rate;
-	*lane_count = config.lane_count;
-}
-
-int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
-			       int link_rate, int lane_count)
-{
-	int link_rate_idx = intel_dp_rate_index(link_caps->rates, link_caps->num_rates,
-						link_rate);
-	int lane_count_exp = ilog2(lane_count);
-	int i;
-
-	for (i = 0; i < link_caps->num_configs; i++) {
-		const struct intel_dp_link_config_entry *lce = &link_caps->configs[i];
-
-		if (lce->lane_count_exp == lane_count_exp &&
-		    lce->link_rate_idx == link_rate_idx)
-			return i;
-	}
-
-	return -1;
-}
-
 /**
  * intel_dp_link_caps_reset - reset link capability restrictions
  * @link_caps: link capabilities state
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index bb785c15c91f6..5c0d660062149 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -119,20 +119,11 @@ intel_dp_link_caps_connector_compute_order(struct intel_connector *connector);
 struct intel_dp_link_caps_order
 intel_dp_link_caps_connector_fallback_order(bool is_mst);
 
-int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
-int intel_dp_link_caps_common_rate_idx(struct intel_dp_link_caps *link_caps, int rate);
-int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps);
-
 void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps);
 
 void intel_dp_link_caps_get_forced_params(struct intel_dp_link_caps *link_caps,
 					  struct intel_dp_link_config *forced_params);
 
-int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
-			       int link_rate, int lane_count);
-void intel_dp_link_config_get(struct intel_dp_link_caps *link_caps,
-			      int idx, int *link_rate, int *lane_count);
-
 bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
 				   struct intel_dp_link_caps_filter *filter,
 				   const struct intel_dp_link_config *config);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 7fdcc299daea5..1c12503908d80 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1846,115 +1846,46 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 	return true;
 }
 
-static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,
-					   const struct intel_crtc_state *crtc_state,
-					   int *new_link_rate, int *new_lane_count)
-{
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	struct intel_dp_link_config forced_params;
-	int link_rate;
-	int lane_count;
-	int i;
-
-	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
-
-	i = intel_dp_link_config_index(intel_dp->link.caps,
-				       crtc_state->port_clock, crtc_state->lane_count);
-	for (i--; i >= 0; i--) {
-		intel_dp_link_config_get(intel_dp->link.caps, i, &link_rate, &lane_count);
-
-		if ((forced_params.rate &&
-		     forced_params.rate != link_rate) ||
-		    (forced_params.lane_count &&
-		     forced_params.lane_count != lane_count))
-			continue;
-
-		break;
-	}
-
-	if (i < 0)
-		return false;
-
-	*new_link_rate = link_rate;
-	*new_lane_count = lane_count;
-
-	return true;
-}
-
-static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)
-{
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	struct intel_dp_link_config forced_params;
-	int rate_index;
-	int new_rate;
-
-	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
-	if (forced_params.rate)
-		return -1;
-
-	rate_index = intel_dp_link_caps_common_rate_idx(link_caps,
-							current_rate);
-
-	if (rate_index <= 0)
-		return -1;
-
-	new_rate = intel_dp_common_rate(link_caps, rate_index - 1);
-
-	/* TODO: Make switching from UHBR to non-UHBR rates work. */
-	if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate))
-		return -1;
-
-	return new_rate;
-}
-
-static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)
-{
-	struct intel_dp_link_config forced_params;
-
-	intel_dp_link_caps_get_forced_params(intel_dp->link.caps, &forced_params);
-	if (forced_params.lane_count)
-		return -1;
-
-	if (current_lane_count == 1)
-		return -1;
-
-	return current_lane_count >> 1;
-}
-
-static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,
-						  const struct intel_crtc_state *crtc_state,
-						  int *new_link_rate, int *new_lane_count)
-{
-	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
-	int link_rate;
-	int lane_count;
-
-	lane_count = crtc_state->lane_count;
-	link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
-	if (link_rate < 0) {
-		lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);
-		link_rate = intel_dp_max_common_rate(link_caps);
-	}
-
-	if (lane_count < 0)
-		return false;
-
-	*new_link_rate = link_rate;
-	*new_lane_count = lane_count;
-
-	return true;
-}
-
 static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
 			       int *new_link_rate, int *new_lane_count)
 {
-	/* TODO: Use the same fallback logic on SST as on MST. */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
-		return reduce_link_params_in_bw_order(intel_dp, crtc_state,
-						      new_link_rate, new_lane_count);
-	else
-		return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,
-							     new_link_rate, new_lane_count);
+	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
+	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
+	struct intel_dp_link_caps_order order =
+		intel_dp_link_caps_connector_fallback_order(is_mst);
+	struct intel_dp_link_config old_config = {
+		.rate = crtc_state->port_clock,
+		.lane_count = crtc_state->lane_count,
+	};
+	struct intel_dp_link_caps_iter iter;
+	struct intel_dp_link_config config;
+	bool old_found = false;
+	bool new_found = false;
+
+	intel_dp_link_caps_iter_start(&iter, link_caps, order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &config) {
+		if (!old_found) {
+			if (config.rate == old_config.rate &&
+			    config.lane_count == old_config.lane_count)
+				old_found = true;
+
+			continue;
+		}
+
+		if (!is_mst &&
+		    drm_dp_is_uhbr_rate(config.rate) !=
+		    drm_dp_is_uhbr_rate(old_config.rate))
+			continue;
+
+		*new_link_rate = config.rate;
+		*new_lane_count = config.lane_count;
+		new_found = true;
+
+		break;
+	}
+	intel_dp_link_caps_iter_end(&iter);
+
+	return new_found;
 }
 
 static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
-- 
2.49.1

[PATCH v2 25/34] drm/i915/dp_link_training: Disable failed config during fallback

[Imre Deak]

Disable the link configuration that failed training when selecting
fallback parameters.

Fallback still selects the next configuration using the existing
fallback order, but now also removes the failed configuration from the
allowed set. Functionally, this only affects the case where an MST <-> SST
mode switch occurs on the same root connector: previously, a configuration
that failed training in one mode could be reused in the other mode due
to the differing config iteration orders.

The current fallback logic also sets a temporary maximum link limit
across the allowed configurations to constrain subsequent modesets. This
legacy behavior is preserved for now; it will be removed once the
fallback logic relies solely on the individually disabled configurations
to restrict the allowed set.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 55 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_dp_link_caps.h |  3 +
 .../drm/i915/display/intel_dp_link_training.c | 19 +++++++
 3 files changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index c947e6511fbc5..76b7c0fc90115 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -596,6 +596,21 @@ bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
 	return true;
 }
 
+static bool intel_dp_link_caps_filter_remove(struct intel_dp_link_caps *link_caps,
+					     struct intel_dp_link_caps_filter *filter,
+					     const struct intel_dp_link_config *config)
+{
+	int idx;
+
+	idx = find_config_idx(link_caps, get_allowed_config_filter(link_caps), config);
+	if (idx < 0)
+		return false;
+
+	filter->config_mask &= ~BIT(idx);
+
+	return true;
+}
+
 static void set_max_link_limits(struct intel_dp_link_caps *link_caps,
 				const struct intel_dp_link_config *max_link_limits)
 {
@@ -618,6 +633,46 @@ static void reset_max_link_limits_reenable_all(struct intel_dp_link_caps *link_c
 	reset_max_link_limits(link_caps);
 }
 
+/**
+ * intel_dp_link_caps_disable_config - disable a configuration
+ * @link_caps: link capabilities state
+ * @config: configuration to disable
+ *
+ * Disable the configuration identified by @config. This removes the
+ * configuration from the set of allowed configurations. The disabling
+ * shouldn't leave the remaining configuration set empty.
+ *
+ * The configuration remains disallowed until intel_dp_link_caps() with
+ * reset=%true or changed sink capabilities is called, or
+ * intel_dp_link_caps_reset() is called. Each of these happens after a
+ * new sink is connected or the currently connected sink changes its
+ * capabilities.
+ *
+ * Return:
+ * - %true  if @config was valid and the derived state was updated.
+ * - %false if @config was invalid or the remaining configuration set
+ *   would remain empty.
+ */
+bool intel_dp_link_caps_disable_config(struct intel_dp_link_caps *link_caps,
+				       const struct intel_dp_link_config *config)
+{
+	struct intel_dp_link_caps_filter enabled_configs = link_caps->enabled_configs;
+	struct intel_dp_link_config forced_params;
+
+	if (!intel_dp_link_caps_filter_remove(link_caps, &enabled_configs, config))
+		return false;
+
+	intel_dp_link_caps_get_forced_params(link_caps, &forced_params);
+
+	if (!calc_allowed_config_filter(link_caps, enabled_configs,
+					&link_caps->max_limits, &forced_params).config_mask)
+		return false;
+
+	link_caps->enabled_configs = enabled_configs;
+
+	return true;
+}
+
 /**
  * intel_dp_link_caps_get_max_limits - get the current maximum link limits
  * @link_caps: link capabilities state
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 5c0d660062149..56c585eb5a135 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -136,6 +136,9 @@ bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
 void intel_dp_link_caps_get_max_bw_config(struct intel_dp_link_caps *link_caps,
 					  struct intel_dp_link_config *max_config);
 
+bool intel_dp_link_caps_disable_config(struct intel_dp_link_caps *link_caps,
+				       const struct intel_dp_link_config *config);
+
 void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
 				       struct intel_dp_link_config *max_link_limits);
 bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1c12503908d80..a592bfab5ff0e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -1894,6 +1894,10 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
 	struct intel_dp_link_config max_link_limits;
+	struct intel_dp_link_config current_config = {
+		.rate = crtc_state->port_clock,
+		.lane_count = crtc_state->lane_count,
+	};
 	int new_link_rate;
 	int new_lane_count;
 	int err = -1;
@@ -1920,6 +1924,13 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 	intel_dp_link_caps_get_max_limits(link_caps, &max_link_limits);
 	intel_dp_link_caps_reset_max_limits(link_caps);
 
+	/*
+	 * TODO: Make fallback depend only on disabling the current config,
+	 * once max_limit no longer constrains the allowed config set. Then
+	 * disabling the current config will define the allowed configs for
+	 * the subsequent modeset, so there will be no need to select a
+	 * reduced config separately here.
+	 */
 	if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
 		goto out_restore_max_limits;
 
@@ -1933,6 +1944,14 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 		goto out_restore_max_limits;
 	}
 
+	/*
+	 * Shouldn't fail: the current config was enabled, and reducing the
+	 * link parameters should still leave the fallback config allowed.
+	 */
+	if (drm_WARN_ON(display->drm,
+			!intel_dp_link_caps_disable_config(link_caps, &current_config)))
+		return -1;
+
 	lt_dbg(intel_dp, DP_PHY_DPRX,
 	       "Reducing link parameters from %dx%d to %dx%d\n",
 	       crtc_state->lane_count, crtc_state->port_clock,
-- 
2.49.1

[PATCH v2 26/34] drm/i915/kunit: Enable KUnit tests

[Imre Deak]

Add KUnit configuration for i915 and a local .kunitconfig to run the
tests.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/.kunitconfig  | 12 ++++++++++++
 drivers/gpu/drm/i915/Kconfig.debug | 12 ++++++++++++
 2 files changed, 24 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/.kunitconfig

diff --git a/drivers/gpu/drm/i915/.kunitconfig b/drivers/gpu/drm/i915/.kunitconfig
new file mode 100644
index 0000000000000..70e55432bad64
--- /dev/null
+++ b/drivers/gpu/drm/i915/.kunitconfig
@@ -0,0 +1,12 @@
+CONFIG_EXPERT=y
+CONFIG_MODULES=y
+CONFIG_KUNIT=y
+CONFIG_PCI=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
+CONFIG_DRM=y
+CONFIG_DRM_I915=y
+CONFIG_DRM_I915_KUNIT_TEST=y
diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index 52a3a59b4ba2c..dc43dcfbadb6e 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -220,6 +220,18 @@ config DRM_I915_SELFTEST_BROKEN
 
 	  If in doubt, say "N".
 
+config DRM_I915_KUNIT_TEST
+	tristate "KUnit tests for the drm i915 driver" if !KUNIT_ALL_TESTS
+	depends on DRM_I915 && KUNIT && DEBUG_FS
+	default KUNIT_ALL_TESTS
+	help
+	  Choose this option to allow the driver to perform selftests under
+	  the kunit framework
+
+	  Recommended for driver developers only.
+
+	  If in doubt, say "N".
+
 config DRM_I915_LOW_LEVEL_TRACEPOINTS
 	bool "Enable low level request tracing events"
 	depends on DRM_I915
-- 
2.49.1

[PATCH v2 27/34] drm/i915/kunit: Add DP link test stub

[Imre Deak]

Add a Kunit stub test module for DP link test cases.

v2: Add missing module license.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  2 +
 drivers/gpu/drm/i915/display/tests/Makefile   |  7 +++
 .../i915/display/tests/intel_dp_link_test.c   | 47 +++++++++++++++++++
 3 files changed, 56 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/tests/Makefile
 create mode 100644 drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c4de717505d73..a83fa8be0aba1 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -386,6 +386,8 @@ i915-y += \
 i915-$(CONFIG_DRM_I915_DP_TUNNEL) += \
 	display/intel_dp_tunnel.o
 
+obj-$(CONFIG_DRM_I915_KUNIT_TEST) += display/tests/
+
 i915-$(CONFIG_DRM_I915_GVT) += \
 	display/intel_gvt_api.o
 
diff --git a/drivers/gpu/drm/i915/display/tests/Makefile b/drivers/gpu/drm/i915/display/tests/Makefile
new file mode 100644
index 0000000000000..ad250974160f6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/tests/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0
+
+subdir-ccflags-y += -I$(srctree)/drivers/gpu/drm/i915/display/
+
+obj-$(CONFIG_DRM_I915_KUNIT_TEST) += i915_display_test.o
+i915_display_test-y = \
+	intel_dp_link_test.o
diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
new file mode 100644
index 0000000000000..62e1844605ac5
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <kunit/test.h>
+
+struct test_ctx {
+};
+
+static struct kunit_case intel_dp_link_test_cases[] = {
+	{}
+};
+
+static struct test_ctx test_ctx;
+
+static int intel_dp_link_test_init(struct kunit *test)
+{
+	test->priv = &test_ctx;
+
+	return 0;
+}
+
+static void intel_dp_link_test_exit(struct kunit *test)
+{
+}
+
+static int intel_dp_link_test_suite_init(struct kunit_suite *test_suite)
+{
+	return 0;
+}
+
+static struct kunit_suite intel_dp_link_test_suite = {
+	.name = "intel_dp_link",
+	.suite_init = intel_dp_link_test_suite_init,
+	.init = intel_dp_link_test_init,
+	.exit = intel_dp_link_test_exit,
+	.test_cases = intel_dp_link_test_cases,
+};
+
+kunit_test_suites(&intel_dp_link_test_suite);
+
+MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING");
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL and additional rights");
+MODULE_DESCRIPTION("Intel DP link KUnit tests");
-- 
2.49.1

[PATCH v2 28/34] drm/xe/kunit: Add display test config

[Imre Deak]

Add a separate xe KUnit config for display tests.

The existing xe .kunitconfig builds xe statically, which is suitable for
non-display xe tests. The display code can only be enabled for xe when
xe is built as a module, so add a separate display config with DRM_XE=m
and DRM_XE_DISPLAY=y.

This can be folded back into the main xe KUnit config once the display
code becomes a separate module.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/xe/.gitignore           |  1 +
 drivers/gpu/drm/xe/.kunitconfig-display | 11 +++++++++++
 2 files changed, 12 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/.kunitconfig-display

diff --git a/drivers/gpu/drm/xe/.gitignore b/drivers/gpu/drm/xe/.gitignore
index 8778bf132674d..6dad8a5a21355 100644
--- a/drivers/gpu/drm/xe/.gitignore
+++ b/drivers/gpu/drm/xe/.gitignore
@@ -2,3 +2,4 @@
 *.hdrtest
 /generated
 /xe_gen_wa_oob
+!.kunitconfig-display
diff --git a/drivers/gpu/drm/xe/.kunitconfig-display b/drivers/gpu/drm/xe/.kunitconfig-display
new file mode 100644
index 0000000000000..17020aa4ded3a
--- /dev/null
+++ b/drivers/gpu/drm/xe/.kunitconfig-display
@@ -0,0 +1,11 @@
+CONFIG_EXPERT=y
+CONFIG_MODULES=y
+CONFIG_KUNIT=y
+CONFIG_PCI=y
+CONFIG_DEBUG_FS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DRM=m
+CONFIG_DRM_XE=m
+CONFIG_DRM_XE_DISPLAY=y
+CONFIG_DRM_XE_KUNIT_TEST=m
-- 
2.49.1

[PATCH v2 29/34] drm/xe/kunit: Build DP link display tests

[Imre Deak]

Hook the shared i915 display DP link KUnit tests into the xe display
test build.

Build the shared display test source from the i915 display test directory
when xe display support is enabled.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/xe/Makefile               |  3 +++
 drivers/gpu/drm/xe/display/tests/Makefile | 11 +++++++++++
 2 files changed, 14 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/display/tests/Makefile

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index e5a04253e73bf..3ff58186c7678 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -373,6 +373,9 @@ xe-$(CONFIG_DRM_XE_DP_TUNNEL) += \
 
 obj-$(CONFIG_DRM_XE) += xe.o
 obj-$(CONFIG_DRM_XE_KUNIT_TEST) += tests/
+ifeq ($(CONFIG_DRM_XE_DISPLAY),y)
+	obj-$(CONFIG_DRM_XE_KUNIT_TEST) += display/tests/
+endif
 
 # header test
 hdrtest_find_args := -not -path xe_rtp_helpers.h
diff --git a/drivers/gpu/drm/xe/display/tests/Makefile b/drivers/gpu/drm/xe/display/tests/Makefile
new file mode 100644
index 0000000000000..1a582febe17a6
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/tests/Makefile
@@ -0,0 +1,11 @@
+subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
+	-I$(srctree)/drivers/gpu/drm/i915/display/
+
+# Rule to build display code shared with i915
+$(obj)/i915-display/tests/%.o: $(srctree)/drivers/gpu/drm/i915/display/tests/%.c FORCE
+	$(call cmd,force_checksrc)
+	$(call if_changed_rule,cc_o_c)
+
+obj-$(CONFIG_DRM_XE_KUNIT_TEST) += xe_display_test.o
+xe_display_test-y = \
+		i915-display/tests/intel_dp_link_test.o
-- 
2.49.1

[PATCH v2 30/34] drm/i915/kunit: Setup DP link test context

[Imre Deak]

Initialize a reusable test context for DP link KUnit tests. Sets up
minimal device, connector, encoder, and DP structures, and seeds the
pseudo-random generator for deterministic test runs.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/tests/intel_dp_link_test.c   | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index 62e1844605ac5..aa5358c94839f 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -5,7 +5,32 @@
 
 #include <kunit/test.h>
 
+#include <linux/compiler.h>
+#include <linux/device.h>
+#include <linux/prandom.h>
+#include <linux/random.h>
+
+#include <drm/display/drm_dp_helper.h>
+
+#include <drm/intel/display_member.h>
+
+#include "intel_connector.h"
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+
 struct test_ctx {
+	struct {
+		struct intel_display display;
+		struct device device;
+		struct __intel_generic_device generic_device;
+
+		struct intel_connector connector;
+		struct intel_digital_port dig_port;
+
+		struct intel_crtc_state crtc_state;
+	} dev;
+
+	struct rnd_state rnd;
 };
 
 static struct kunit_case intel_dp_link_test_cases[] = {
@@ -16,6 +41,29 @@ static struct test_ctx test_ctx;
 
 static int intel_dp_link_test_init(struct kunit *test)
 {
+	struct intel_digital_port *dig_port;
+	struct intel_encoder *encoder;
+	struct intel_dp *intel_dp;
+
+	/* Reset the dev state for each test. */
+	memset(&test_ctx.dev, 0, sizeof(test_ctx.dev));
+
+	test_ctx.dev.generic_device.drm.dev = &test_ctx.dev.device;
+
+	test_ctx.dev.display.drm = &test_ctx.dev.generic_device.drm;
+	test_ctx.dev.generic_device.display = &test_ctx.dev.display;
+
+	encoder = &test_ctx.dev.dig_port.base;
+	encoder->base.dev = &test_ctx.dev.generic_device.drm;
+
+	dig_port = &test_ctx.dev.dig_port;
+	dig_port->base.type = INTEL_OUTPUT_DP;
+
+	test_ctx.dev.connector.encoder = encoder;
+
+	intel_dp = &dig_port->dp;
+	intel_dp->attached_connector = &test_ctx.dev.connector;
+
 	test->priv = &test_ctx;
 
 	return 0;
@@ -27,6 +75,8 @@ static void intel_dp_link_test_exit(struct kunit *test)
 
 static int intel_dp_link_test_suite_init(struct kunit_suite *test_suite)
 {
+	prandom_seed_state(&test_ctx.rnd, 0);
+
 	return 0;
 }
 
-- 
2.49.1

[PATCH v2 31/34] drm/i915/kunit: Export link training and caps funcs for testing

[Imre Deak]

Export the link caps and link training helpers needed by the DP link
KUnit tests.

Use test ops tables instead of exporting the helpers directly, avoiding
symbol name collisions between the i915 and xe builds of the shared
display code.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../gpu/drm/i915/display/intel_dp_link_caps.c | 29 +++++++++++++++
 .../gpu/drm/i915/display/intel_dp_link_caps.h | 37 +++++++++++++++++++
 .../drm/i915/display/intel_dp_link_training.c | 36 +++++++++++++++++-
 .../drm/i915/display/intel_dp_link_training.h | 31 ++++++++++++++++
 .../i915/display/tests/intel_dp_link_test.c   | 17 +++++++++
 5 files changed, 148 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
index 76b7c0fc90115..7b6cc6055da82 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
@@ -1281,3 +1281,32 @@ void intel_dp_link_caps_cleanup(struct intel_dp_link_caps *link_caps)
 {
 	kfree(link_caps);
 }
+
+#if IS_ENABLED(CONFIG_KUNIT)
+
+#define __INIT_MEMBER(__name, __fn) \
+	.__name = __fn,
+
+#define INTEL_DP_LINK_CAPS_TEST_OPS_INIT \
+	INTEL_DP_LINK_CAPS_TEST_OPS_MEMBERS(__INIT_MEMBER)
+
+#ifdef I915
+
+const struct intel_dp_link_caps_test_ops i915_display_dp_link_caps_test_ops = {
+	INTEL_DP_LINK_CAPS_TEST_OPS_INIT
+};
+EXPORT_SYMBOL(i915_display_dp_link_caps_test_ops);
+
+#else
+
+const struct intel_dp_link_caps_test_ops intel_display_dp_link_caps_test_ops = {
+	INTEL_DP_LINK_CAPS_TEST_OPS_INIT
+};
+EXPORT_SYMBOL(intel_display_dp_link_caps_test_ops);
+
+#endif	/* I915 */
+
+#undef INTEL_DP_LINK_CAPS_TEST_OPS_INIT
+#undef __INIT_MEMBER
+
+#endif	/* CONFIG_KUNIT */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
index 56c585eb5a135..a0a88efb95463 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
@@ -155,4 +155,41 @@ void intel_dp_link_caps_debugfs_add(struct intel_connector *connector);
 struct intel_dp_link_caps *intel_dp_link_caps_init(struct intel_dp *intel_dp);
 void intel_dp_link_caps_cleanup(struct intel_dp_link_caps *link_caps);
 
+#if IS_ENABLED(CONFIG_KUNIT)
+
+#define INTEL_DP_LINK_CAPS_TEST_OPS_MEMBERS(__X) \
+	__X(connector_compute_order,	intel_dp_link_caps_connector_compute_order) \
+	__X(connector_fallback_order,	intel_dp_link_caps_connector_fallback_order) \
+	__X(iter_start,			intel_dp_link_caps_iter_start) \
+	__X(iter_end,			intel_dp_link_caps_iter_end) \
+	__X(set_max_limits,		intel_dp_link_caps_set_max_limits) \
+	__X(get_max_limits,		intel_dp_link_caps_get_max_limits) \
+	__X(get_max_bw_config,		intel_dp_link_caps_get_max_bw_config) \
+	__X(reset_max_limits,		intel_dp_link_caps_reset_max_limits) \
+	__X(disable_config,		intel_dp_link_caps_disable_config) \
+	__X(update,			intel_dp_link_caps_update) \
+	__X(init,			intel_dp_link_caps_init) \
+	__X(cleanup,			intel_dp_link_caps_cleanup)
+
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;
+
+#define INTEL_DP_LINK_CAPS_TEST_OPS_DECLARE \
+	INTEL_DP_LINK_CAPS_TEST_OPS_MEMBERS(__DECLARE_MEMBER)
+
+struct intel_dp_link_caps_test_ops {
+	INTEL_DP_LINK_CAPS_TEST_OPS_DECLARE
+};
+
+#undef INTEL_DP_LINK_CAPS_TEST_OPS_DECLARE
+#undef __DECLARE_MEMBER
+
+#ifdef I915
+extern const struct intel_dp_link_caps_test_ops i915_display_dp_link_caps_test_ops;
+#else
+extern const struct intel_dp_link_caps_test_ops intel_display_dp_link_caps_test_ops;
+#endif	/* I915 */
+
+#endif	/* CONFIG_KUNIT */
+
 #endif /* __INTEL_DP_LINK_CAPS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index a592bfab5ff0e..fa55664c9d98e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -21,6 +21,8 @@
  * IN THE SOFTWARE.
  */
 
+#include <kunit/visibility.h>
+
 #include <linux/debugfs.h>
 #include <linux/iopoll.h>
 
@@ -1888,8 +1890,9 @@ static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crt
 	return new_found;
 }
 
-static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
-						   const struct intel_crtc_state *crtc_state)
+VISIBLE_IF_KUNIT
+int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
+					    const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
@@ -2813,3 +2816,32 @@ void intel_dp_link_training_cleanup(struct intel_dp_link_training *link_training
 {
 	kfree(link_training);
 }
+
+#if IS_ENABLED(CONFIG_KUNIT)
+
+#define __INIT_MEMBER(__name, __fn) \
+	.__name = __fn,
+
+#define INTEL_DP_LINK_TRAINING_TEST_OPS_INIT \
+	INTEL_DP_LINK_TRAINING_TEST_OPS_MEMBERS(__INIT_MEMBER)
+
+#ifdef I915
+
+const struct intel_dp_link_training_test_ops i915_display_dp_link_training_test_ops = {
+	INTEL_DP_LINK_TRAINING_TEST_OPS_INIT
+};
+EXPORT_SYMBOL(i915_display_dp_link_training_test_ops);
+
+#else
+
+const struct intel_dp_link_training_test_ops intel_display_dp_link_training_test_ops = {
+	INTEL_DP_LINK_TRAINING_TEST_OPS_INIT
+};
+EXPORT_SYMBOL(intel_display_dp_link_training_test_ops);
+
+#endif	/* I915 */
+
+#undef INTEL_DP_LINK_TRAINING_TEST_OPS_INIT
+#undef __INIT_MEMBER
+
+#endif	/* CONFIG_KUNIT */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
index ef16fcabd6da9..581f2361fdfd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
@@ -8,6 +8,8 @@
 
 #include <drm/display/drm_dp_helper.h>
 
+#include "intel_dp_link_caps.h"
+
 struct intel_atomic_state;
 struct intel_connector;
 struct intel_crtc_state;
@@ -71,4 +73,33 @@ void intel_dp_link_training_reset(struct intel_dp_link_training *link_training);
 struct intel_dp_link_training *intel_dp_link_training_init(struct intel_dp *intel_dp);
 void intel_dp_link_training_cleanup(struct intel_dp_link_training *link_training);
 
+#if IS_ENABLED(CONFIG_KUNIT)
+
+int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
+					    const struct intel_crtc_state *crtc_state);
+
+#define INTEL_DP_LINK_TRAINING_TEST_OPS_MEMBERS(__X) \
+	__X(get_fallback_values,	intel_dp_get_link_train_fallback_values)
+
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;
+
+#define INTEL_DP_LINK_TRAINING_TEST_OPS_DECLARE \
+	INTEL_DP_LINK_TRAINING_TEST_OPS_MEMBERS(__DECLARE_MEMBER)
+
+struct intel_dp_link_training_test_ops {
+	INTEL_DP_LINK_TRAINING_TEST_OPS_DECLARE
+};
+
+#undef INTEL_DP_LINK_TRAINING_TEST_OPS_DECLARE
+#undef __DECLARE_MEMBER
+
+#ifdef I915
+extern const struct intel_dp_link_training_test_ops i915_display_dp_link_training_test_ops;
+#else
+extern const struct intel_dp_link_training_test_ops intel_display_dp_link_training_test_ops;
+#endif	/* I915 */
+
+#endif	/* CONFIG_KUNIT */
+
 #endif /* __INTEL_DP_LINK_TRAINING_H__ */
diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index aa5358c94839f..b77472e9bbe12 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -17,6 +17,8 @@
 #include "intel_connector.h"
 #include "intel_display_core.h"
 #include "intel_display_types.h"
+#include "intel_dp_link_caps.h"
+#include "intel_dp_link_training.h"
 
 struct test_ctx {
 	struct {
@@ -30,6 +32,9 @@ struct test_ctx {
 		struct intel_crtc_state crtc_state;
 	} dev;
 
+	const struct intel_dp_link_caps_test_ops *link_caps_ops;
+	const struct intel_dp_link_training_test_ops *link_training_ops;
+
 	struct rnd_state rnd;
 };
 
@@ -64,6 +69,8 @@ static int intel_dp_link_test_init(struct kunit *test)
 	intel_dp = &dig_port->dp;
 	intel_dp->attached_connector = &test_ctx.dev.connector;
 
+	intel_dp->link.caps = test_ctx.link_caps_ops->init(intel_dp);
+
 	test->priv = &test_ctx;
 
 	return 0;
@@ -71,10 +78,20 @@ static int intel_dp_link_test_init(struct kunit *test)
 
 static void intel_dp_link_test_exit(struct kunit *test)
 {
+	struct test_ctx *ctx = test->priv;
+
+	ctx->link_caps_ops->cleanup(ctx->dev.dig_port.dp.link.caps);
 }
 
 static int intel_dp_link_test_suite_init(struct kunit_suite *test_suite)
 {
+#ifdef I915
+	test_ctx.link_caps_ops = &i915_display_dp_link_caps_test_ops;
+	test_ctx.link_training_ops = &i915_display_dp_link_training_test_ops;
+#else
+	test_ctx.link_caps_ops = &intel_display_dp_link_caps_test_ops;
+	test_ctx.link_training_ops = &intel_display_dp_link_training_test_ops;
+#endif
 	prandom_seed_state(&test_ctx.rnd, 0);
 
 	return 0;
-- 
2.49.1

[PATCH v2 32/34] drm/i915/kunit: DP link: add baseline fixed table reference test

[Imre Deak]

Add a simple baseline test for DP link caps iteration using a fixed
standard DP configuration table. This provides a minimal validity check,
independent of more complex test setups, verifying the iterator returns
expected configurations in ascending and descending order.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/tests/intel_dp_link_test.c   | 200 ++++++++++++++++++
 1 file changed, 200 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index b77472e9bbe12..1dc5bf6888990 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -7,6 +7,7 @@
 
 #include <linux/compiler.h>
 #include <linux/device.h>
+#include <linux/log2.h>
 #include <linux/prandom.h>
 #include <linux/random.h>
 
@@ -20,6 +21,18 @@
 #include "intel_dp_link_caps.h"
 #include "intel_dp_link_training.h"
 
+#define LINK_TEST_NUM_LANE_CONFIGS(__max_lane_count) \
+	(ilog2(__max_lane_count) + 1)
+
+#define LINK_TEST_NUM_CONFIGS(__num_rates, __max_lane_count) \
+	((__num_rates) * LINK_TEST_NUM_LANE_CONFIGS(__max_lane_count))
+
+#define LINK_TEST_MAX_LANE_COUNT		((u32)4)
+#define LINK_TEST_MAX_CONFIGS			LINK_TEST_NUM_CONFIGS(DP_MAX_SUPPORTED_RATES, \
+								      LINK_TEST_MAX_LANE_COUNT)
+
+#define LINK_TEST_NUM_RANDOM_ITERATIONS		50
+
 struct test_ctx {
 	struct {
 		struct intel_display display;
@@ -38,7 +51,194 @@ struct test_ctx {
 	struct rnd_state rnd;
 };
 
+struct link_rate_set {
+	const int *entries;
+	int size;
+};
+
+struct link_config_set {
+	struct intel_dp_link_config entries[LINK_TEST_MAX_CONFIGS];
+	int size;
+};
+
+static const int standard_dp_link_rates[] = {
+	162000, 270000, 540000, 810000, 1000000, 1350000, 2000000
+};
+
+#define LINK_TEST_NUM_STANDARD_RATES (ARRAY_SIZE(standard_dp_link_rates))
+
+static const struct link_config_set standard_dp_link_configs[] = {
+	[INTEL_DP_LINK_CAPS_ORDER_KEY_BW] = {                        /* MBps    PBN    */
+		.entries = {
+			{ .rate =  162000, .lane_count = 1 }, /*  162.0    3.00 */
+			{ .rate =  270000, .lane_count = 1 }, /*  270.0    5.00 */
+			{ .rate =  162000, .lane_count = 2 }, /*  324.0    6.00 */
+			{ .rate =  270000, .lane_count = 2 }, /*  540.0   10.00 */
+			{ .rate =  540000, .lane_count = 1 }, /*  540.0   10.00 */
+			{ .rate =  162000, .lane_count = 4 }, /*  648.0   12.00 */
+			{ .rate =  810000, .lane_count = 1 }, /*  810.0   15.00 */
+			{ .rate =  270000, .lane_count = 4 }, /* 1080.0   20.00 */
+			{ .rate =  540000, .lane_count = 2 }, /* 1080.0   20.00 */
+			{ .rate = 1000000, .lane_count = 1 }, /* 1208.9   22.39 */
+			{ .rate =  810000, .lane_count = 2 }, /* 1620.0   30.00 */
+			{ .rate = 1350000, .lane_count = 1 }, /* 1632.0   30.22 */
+			{ .rate =  540000, .lane_count = 4 }, /* 2160.0   40.00 */
+			{ .rate = 1000000, .lane_count = 2 }, /* 2417.8   44.77 */
+			{ .rate = 2000000, .lane_count = 1 }, /* 2417.8   44.77 */
+			{ .rate =  810000, .lane_count = 4 }, /* 3240.0   60.00 */
+			{ .rate = 1350000, .lane_count = 2 }, /* 3264.0   60.44 */
+			{ .rate = 1000000, .lane_count = 4 }, /* 4835.6   89.55 */
+			{ .rate = 2000000, .lane_count = 2 }, /* 4835.6   89.55 */
+			{ .rate = 1350000, .lane_count = 4 }, /* 6527.9  120.89 */
+			{ .rate = 2000000, .lane_count = 4 }, /* 9671.1  179.09 */
+		},
+		.size = LINK_TEST_NUM_CONFIGS(ARRAY_SIZE(standard_dp_link_rates),
+					      LINK_TEST_MAX_LANE_COUNT),
+	},
+	[INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE] = {
+		.entries = {
+			{ .rate = 162000,  .lane_count = 1 },
+			{ .rate = 162000,  .lane_count = 2 },
+			{ .rate = 162000,  .lane_count = 4 },
+
+			{ .rate = 270000,  .lane_count = 1 },
+			{ .rate = 270000,  .lane_count = 2 },
+			{ .rate = 270000,  .lane_count = 4 },
+
+			{ .rate = 540000,  .lane_count = 1 },
+			{ .rate = 540000,  .lane_count = 2 },
+			{ .rate = 540000,  .lane_count = 4 },
+
+			{ .rate = 810000,  .lane_count = 1 },
+			{ .rate = 810000,  .lane_count = 2 },
+			{ .rate = 810000,  .lane_count = 4 },
+
+			{ .rate = 1000000, .lane_count = 1 },
+			{ .rate = 1000000, .lane_count = 2 },
+			{ .rate = 1000000, .lane_count = 4 },
+
+			{ .rate = 1350000, .lane_count = 1 },
+			{ .rate = 1350000, .lane_count = 2 },
+			{ .rate = 1350000, .lane_count = 4 },
+
+			{ .rate = 2000000, .lane_count = 1 },
+			{ .rate = 2000000, .lane_count = 2 },
+			{ .rate = 2000000, .lane_count = 4 },
+		},
+		.size = LINK_TEST_NUM_CONFIGS(ARRAY_SIZE(standard_dp_link_rates),
+					      LINK_TEST_MAX_LANE_COUNT),
+	},
+	[INTEL_DP_LINK_CAPS_ORDER_KEY_LANE_RATE] = {
+		.entries = {
+			{ .rate = 162000,  .lane_count = 1 },
+			{ .rate = 270000,  .lane_count = 1 },
+			{ .rate = 540000,  .lane_count = 1 },
+			{ .rate = 810000,  .lane_count = 1 },
+			{ .rate = 1000000, .lane_count = 1 },
+			{ .rate = 1350000, .lane_count = 1 },
+			{ .rate = 2000000, .lane_count = 1 },
+
+			{ .rate = 162000,  .lane_count = 2 },
+			{ .rate = 270000,  .lane_count = 2 },
+			{ .rate = 540000,  .lane_count = 2 },
+			{ .rate = 810000,  .lane_count = 2 },
+			{ .rate = 1000000, .lane_count = 2 },
+			{ .rate = 1350000, .lane_count = 2 },
+			{ .rate = 2000000, .lane_count = 2 },
+
+			{ .rate = 162000,  .lane_count = 4 },
+			{ .rate = 270000,  .lane_count = 4 },
+			{ .rate = 540000,  .lane_count = 4 },
+			{ .rate = 810000,  .lane_count = 4 },
+			{ .rate = 1000000, .lane_count = 4 },
+			{ .rate = 1350000, .lane_count = 4 },
+			{ .rate = 2000000, .lane_count = 4 },
+		},
+		.size = LINK_TEST_NUM_CONFIGS(ARRAY_SIZE(standard_dp_link_rates),
+					      LINK_TEST_MAX_LANE_COUNT),
+	},
+};
+
+static bool link_configs_match(const struct intel_dp_link_config *a,
+			       const struct intel_dp_link_config *b)
+{
+	return a->rate == b->rate && a->lane_count == b->lane_count;
+}
+
+static const struct intel_dp_link_caps_order config_orders[] = {
+	{
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_ASC,
+	}, {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	}, {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_ASC,
+	}, {
+		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE,
+		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC,
+	}
+};
+
+static const struct link_config_set *
+link_caps_config_order_key_to_set(struct kunit *test, enum intel_dp_link_caps_order_key key)
+{
+	return &standard_dp_link_configs[key];
+}
+
+/*
+ * TEST: Baseline with fixed reference table
+ * -----------------------------------------
+ * Verify the link_caps config iterator using fixed standard DP config tables.
+ */
+static void baseline_test_for_order(struct kunit *test,
+				    struct intel_dp_link_caps *link_caps,
+				    struct intel_dp_link_caps_order config_order)
+{
+	struct test_ctx *ctx = test->priv;
+	const struct link_config_set *config_set =
+		link_caps_config_order_key_to_set(test, config_order.key);
+	const struct intel_dp_link_caps_test_ops *ops = ctx->link_caps_ops;
+	struct intel_dp_link_config iter_config;
+	struct intel_dp_link_caps_iter iter;
+	int pos = 0;
+
+	ops->iter_start(&iter, link_caps, config_order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &iter_config) {
+		int idx = pos;
+
+		if (config_order.dir == INTEL_DP_LINK_CAPS_ORDER_DIR_DESC)
+			idx = config_set->size - idx - 1;
+
+		KUNIT_EXPECT_TRUE(test, link_configs_match(&iter_config,
+							   &config_set->entries[idx]));
+
+		pos++;
+	}
+	ops->iter_end(&iter);
+}
+
+static void intel_dp_link_caps_test_baseline(struct kunit *test)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	const struct intel_dp_link_caps_test_ops *ops =
+		ctx->link_caps_ops;
+	int i;
+
+	ops->update(link_caps,
+		    standard_dp_link_rates, LINK_TEST_NUM_STANDARD_RATES,
+		    LINK_TEST_MAX_LANE_COUNT,
+		    true);
+
+	for (i = 0; i < ARRAY_SIZE(config_orders); i++)
+		baseline_test_for_order(test, link_caps, config_orders[i]);
+}
+
 static struct kunit_case intel_dp_link_test_cases[] = {
+	KUNIT_CASE(intel_dp_link_caps_test_baseline),
+
 	{}
 };
 
-- 
2.49.1

[PATCH v2 33/34] drm/i915/kunit: DP link: add update config tests

[Imre Deak]

Add KUnit tests for link_caps updates shrinking or expanding the
supported rates and lane counts.

The tests also cover updates with disabled configurations, including
random shrink and expand sequences, to verify that disabled state,
allowed configurations, ordering, and max limits stay consistent across
updates.

v2: Remove test cases for the now unused merge update mode.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/tests/intel_dp_link_test.c   | 780 ++++++++++++++++++
 1 file changed, 780 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index 1dc5bf6888990..43283245ad037 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -61,12 +61,29 @@ struct link_config_set {
 	int size;
 };
 
+struct test_config_table {
+	struct kunit *test;
+
+	struct link_rate_set rates;
+	int max_lane_count;
+	struct link_config_set disabled_configs;
+};
+
 static const int standard_dp_link_rates[] = {
 	162000, 270000, 540000, 810000, 1000000, 1350000, 2000000
 };
 
 #define LINK_TEST_NUM_STANDARD_RATES (ARRAY_SIZE(standard_dp_link_rates))
 
+#define INIT_STANDARD_TABLE(__test, __num_rates, __max_lane_count) { \
+	.test = (__test), \
+	.rates = { \
+		.entries = standard_dp_link_rates, \
+		.size = (__num_rates), \
+	}, \
+	.max_lane_count = (__max_lane_count), \
+}
+
 static const struct link_config_set standard_dp_link_configs[] = {
 	[INTEL_DP_LINK_CAPS_ORDER_KEY_BW] = {                        /* MBps    PBN    */
 		.entries = {
@@ -159,12 +176,56 @@ static const struct link_config_set standard_dp_link_configs[] = {
 	},
 };
 
+static int lookup_rate(const struct link_rate_set *rate_set, int rate)
+{
+	int i;
+
+	for (i = 0; i < rate_set->size; i++)
+		if (rate_set->entries[i] == rate)
+			return i;
+
+	return -1;
+}
+
+static bool has_rate(const struct link_rate_set *rate_set, int rate)
+{
+	return lookup_rate(rate_set, rate) >= 0;
+}
+
 static bool link_configs_match(const struct intel_dp_link_config *a,
 			       const struct intel_dp_link_config *b)
 {
 	return a->rate == b->rate && a->lane_count == b->lane_count;
 }
 
+static int lookup_config(const struct link_config_set *config_set,
+			 const struct intel_dp_link_config *config)
+{
+	int i;
+
+	for (i = 0; i < config_set->size; i++)
+		if (link_configs_match(&config_set->entries[i], config))
+			return i;
+
+	return -1;
+}
+
+static bool has_config(const struct link_config_set *config_set,
+		       const struct intel_dp_link_config *config)
+{
+	return lookup_config(config_set, config) >= 0;
+}
+
+static void add_config(struct kunit *test,
+		       struct link_config_set *config_set,
+		       const struct intel_dp_link_config *config)
+{
+	KUNIT_ASSERT_LT(test, config_set->size, ARRAY_SIZE(config_set->entries));
+
+	config_set->entries[config_set->size] = *config;
+	config_set->size++;
+}
+
 static const struct intel_dp_link_caps_order config_orders[] = {
 	{
 		.key = INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
@@ -236,9 +297,728 @@ static void intel_dp_link_caps_test_baseline(struct kunit *test)
 		baseline_test_for_order(test, link_caps, config_orders[i]);
 }
 
+static int get_num_configs(int num_rates, int max_lane_count)
+{
+	return num_rates * LINK_TEST_NUM_LANE_CONFIGS(max_lane_count);
+}
+
+static int rand_in_range(struct test_ctx *ctx, int min, int max)
+{
+	return min + (prandom_u32_state(&ctx->rnd) % (max - min + 1));
+}
+
+/*
+ * TEST: Update reset
+ * ------------------
+ * Verify that resetting link_caps with the DP standard rates/lane
+ * counts updates the configuration table accordingly for all
+ * combinations.
+ */
+static void verify_bw_asc_config_order(struct kunit *test,
+				       const struct intel_dp_link_config *last_config,
+				       const struct intel_dp_link_config *config)
+{
+	int config_bw = drm_dp_max_dprx_data_rate(config->rate,
+						  config->lane_count);
+	int last_config_bw = drm_dp_max_dprx_data_rate(last_config->rate,
+							  last_config->lane_count);
+
+	KUNIT_EXPECT_GE(test, config_bw, last_config_bw);
+	if (config_bw == last_config_bw)
+		KUNIT_EXPECT_GT(test, config->rate, last_config->rate);
+}
+
+static void verify_bw_desc_config_order(struct kunit *test,
+					const struct intel_dp_link_config *last_config,
+					const struct intel_dp_link_config *config)
+{
+	int config_bw = drm_dp_max_dprx_data_rate(config->rate,
+						  config->lane_count);
+	int last_config_bw = drm_dp_max_dprx_data_rate(last_config->rate,
+							  last_config->lane_count);
+
+	KUNIT_EXPECT_LE(test, config_bw, last_config_bw);
+	if (config_bw == last_config_bw)
+		KUNIT_EXPECT_LT(test, config->rate, last_config->rate);
+}
+
+static void verify_rate_lane_asc_config_order(struct kunit *test,
+					      const struct intel_dp_link_config *last_config,
+					      const struct intel_dp_link_config *config)
+{
+	KUNIT_EXPECT_GE(test, config->rate, last_config->rate);
+	if (config->rate == last_config->rate)
+		KUNIT_EXPECT_GT(test, config->lane_count, last_config->lane_count);
+}
+
+static void verify_rate_lane_desc_config_order(struct kunit *test,
+					       const struct intel_dp_link_config *last_config,
+					       const struct intel_dp_link_config *config)
+{
+	KUNIT_EXPECT_LE(test, config->rate, last_config->rate);
+	if (config->rate == last_config->rate)
+		KUNIT_EXPECT_LT(test, config->lane_count, last_config->lane_count);
+}
+
+static void verify_config_order(struct kunit *test,
+				struct intel_dp_link_caps_order config_order,
+				const struct intel_dp_link_config *last_config,
+				const struct intel_dp_link_config *config)
+{
+	switch (config_order.key) {
+	case INTEL_DP_LINK_CAPS_ORDER_KEY_BW:
+		if (config_order.dir == INTEL_DP_LINK_CAPS_ORDER_DIR_ASC)
+			verify_bw_asc_config_order(test, last_config, config);
+		else
+			verify_bw_desc_config_order(test, last_config, config);
+		break;
+	case INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE:
+		if (config_order.dir == INTEL_DP_LINK_CAPS_ORDER_DIR_ASC)
+			verify_rate_lane_asc_config_order(test, last_config, config);
+		else
+			verify_rate_lane_desc_config_order(test, last_config, config);
+		break;
+	default:
+		KUNIT_FAIL_AND_ABORT(test, "Missing order key: %d", config_order.key);
+	}
+}
+
+static int expected_num_configs(const struct test_config_table *expected_table,
+				const struct intel_dp_link_config *max_limits)
+{
+	int num_configs = 0;
+	int lane_count;
+	int rate_idx;
+
+	for (rate_idx = 0; rate_idx < expected_table->rates.size; rate_idx++) {
+		for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {
+			struct intel_dp_link_config config = {
+				.rate = expected_table->rates.entries[rate_idx],
+				.lane_count = lane_count,
+			};
+
+			if (config.rate > max_limits->rate ||
+			    config.lane_count > max_limits->lane_count)
+				continue;
+
+			if (has_config(&expected_table->disabled_configs, &config))
+				continue;
+
+			num_configs++;
+		}
+	}
+
+	return num_configs;
+}
+
+static void
+verify_link_caps_for_order(const struct test_config_table *expected_table,
+			   struct intel_dp_link_caps *link_caps,
+			   struct intel_dp_link_caps_order config_order,
+			   const struct intel_dp_link_config *max_limits)
+{
+	struct kunit *test = expected_table->test;
+	struct test_ctx *ctx = test->priv;
+	const struct intel_dp_link_caps_test_ops *ops =
+		ctx->link_caps_ops;
+	struct intel_dp_link_config expected_max_bw_config = {};
+	struct intel_dp_link_config actual_max_bw_config;
+	struct intel_dp_link_config last_config = {};
+	struct intel_dp_link_config old_max_limits;
+	struct intel_dp_link_config iter_config;
+	struct intel_dp_link_caps_iter iter;
+	int num_actual_configs = 0;
+	int max_bw = 0;
+
+	ops->get_max_limits(link_caps, &old_max_limits);
+	ops->set_max_limits(link_caps, max_limits);
+
+	ops->iter_start(&iter, link_caps, config_order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &iter_config) {
+		int bw;
+
+		KUNIT_EXPECT_LE(test, iter_config.rate, max_limits->rate);
+		KUNIT_EXPECT_LE(test, iter_config.lane_count, max_limits->lane_count);
+
+		num_actual_configs++;
+
+		/*
+		 * Verify the config's rate/lane-count values and its ordering relative
+		 * to the previous config.
+		 */
+		if (last_config.rate)
+			verify_config_order(test, config_order, &last_config, &iter_config);
+		last_config = iter_config;
+
+		KUNIT_EXPECT_TRUE(test, has_rate(&expected_table->rates,
+						 iter_config.rate));
+		KUNIT_EXPECT_LE(test, iter_config.lane_count,
+				      expected_table->max_lane_count);
+		KUNIT_EXPECT_TRUE(test, is_power_of_2(iter_config.lane_count));
+
+		/* Verify the config's disabled state */
+		KUNIT_EXPECT_FALSE(test, has_config(&expected_table->disabled_configs,
+						    &iter_config));
+
+		/*
+		 * Update the max limits for allowed configs, verified at the
+		 * end for the whole config table.
+		 */
+
+		bw = drm_dp_max_dprx_data_rate(iter_config.rate, iter_config.lane_count);
+		if (bw > max_bw ||
+		    (bw == max_bw && iter_config.rate > expected_max_bw_config.rate)) {
+			max_bw = bw;
+			expected_max_bw_config = iter_config;
+		}
+	}
+	ops->iter_end(&iter);
+
+	KUNIT_EXPECT_EQ(test, num_actual_configs, expected_num_configs(expected_table, max_limits));
+
+	ops->get_max_bw_config(link_caps, &actual_max_bw_config);
+	KUNIT_EXPECT_TRUE(test, link_configs_match(&expected_max_bw_config,
+						   &actual_max_bw_config));
+
+	KUNIT_ASSERT_TRUE(test, ops->set_max_limits(link_caps, &old_max_limits));
+}
+
+static bool max_limits_valid(const struct test_config_table *expected_table,
+			     const struct intel_dp_link_config *max_limits)
+{
+	int lane_count;
+	int rate_idx;
+
+	for (rate_idx = 0; rate_idx < expected_table->rates.size; rate_idx++) {
+		for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {
+			struct intel_dp_link_config config = {
+				.rate = expected_table->rates.entries[rate_idx],
+				.lane_count = lane_count,
+			};
+
+			if (has_config(&expected_table->disabled_configs, &config))
+				continue;
+
+			if (config.rate <= max_limits->rate &&
+			    config.lane_count <= max_limits->lane_count)
+				return true;
+		}
+	}
+
+	return false;
+}
+
+static void get_max_limits(const struct test_config_table *expected_table,
+			   struct intel_dp_link_config *max_limits)
+{
+	int lane_count;
+	int rate_idx;
+
+	max_limits->rate = 0;
+	max_limits->lane_count = 0;
+
+	for (rate_idx = 0; rate_idx < expected_table->rates.size; rate_idx++) {
+		for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {
+			struct intel_dp_link_config config = {
+				.rate = expected_table->rates.entries[rate_idx],
+				.lane_count = lane_count,
+			};
+
+			if (has_config(&expected_table->disabled_configs, &config))
+				continue;
+
+			max_limits->rate = max(max_limits->rate, config.rate);
+			max_limits->lane_count = max(max_limits->lane_count, config.lane_count);
+		}
+	}
+}
+
+static void verify_link_caps(const struct test_config_table *expected_table,
+			     struct intel_dp_link_caps *link_caps)
+{
+	struct kunit *test = expected_table->test;
+	struct test_ctx *ctx = test->priv;
+	const struct intel_dp_link_caps_test_ops *ops = ctx->link_caps_ops;
+	struct intel_dp_link_config max_limits;
+	int i;
+
+	get_max_limits(expected_table, &max_limits);
+
+	for (i = 0; i < ARRAY_SIZE(config_orders); i++) {
+		int lane_count;
+		int rate_idx;
+
+		verify_link_caps_for_order(expected_table, link_caps, config_orders[i], &max_limits);
+		/*
+		 * Verify iteration after setting the max limits to each
+		 * configurations.
+		 */
+		for (rate_idx = 0; rate_idx < expected_table->rates.size; rate_idx++) {
+			for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {
+				struct intel_dp_link_config config = {
+					.rate = expected_table->rates.entries[rate_idx],
+					.lane_count = lane_count,
+				};
+
+				if (!max_limits_valid(expected_table, &config)) {
+					/* Verify that invalid max limits are rejected. */
+					KUNIT_EXPECT_FALSE(test, ops->set_max_limits(link_caps, &config));
+
+					continue;
+				}
+
+				verify_link_caps_for_order(expected_table, link_caps, config_orders[i],
+							   &config);
+			}
+		}
+	}
+}
+
+static void update_link_caps_and_verify(struct test_config_table *expected_table,
+					struct intel_dp_link_caps *link_caps,
+					bool reset)
+{
+	struct kunit *test = expected_table->test;
+	struct test_ctx *ctx = test->priv;
+	const struct intel_dp_link_caps_test_ops *ops =
+		ctx->link_caps_ops;
+	bool link_params_changed;
+
+	link_params_changed = ops->update(link_caps,
+					  expected_table->rates.entries,
+					  expected_table->rates.size,
+					  expected_table->max_lane_count,
+					  reset);
+	KUNIT_EXPECT_TRUE(test, !reset || link_params_changed);
+
+	/*
+	 * ops->update() re-enables all configurations when called with
+	 * reset=true, or changed link parameters.
+	 */
+	if (link_params_changed)
+		expected_table->disabled_configs.size = 0;
+
+	verify_link_caps(expected_table, link_caps);
+}
+
+static void intel_dp_link_caps_test_update_reset(struct kunit *test)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	int max_lane_count;
+	int num_rates;
+
+	for (max_lane_count = 1;
+	     max_lane_count <= LINK_TEST_MAX_LANE_COUNT;
+	     max_lane_count <<= 1) {
+		for (num_rates = 1;
+		     num_rates <= LINK_TEST_NUM_STANDARD_RATES;
+		     num_rates++) {
+			struct test_config_table expected_table =
+				INIT_STANDARD_TABLE(test, num_rates,
+							     max_lane_count);
+
+			update_link_caps_and_verify(&expected_table, link_caps, true);
+		}
+	}
+}
+
+/*
+ * TEST: Update shrink and expand
+ * ------------------------------
+ * Verify that removing or adding supported rates/lane counts updates
+ * the configuration table accordingly.
+ */
+static void disable_configs_and_verify(struct kunit *test,
+				       struct intel_dp_link_caps *link_caps,
+				       struct test_config_table *expected_table,
+				       const struct link_config_set *config_set)
+{
+	struct test_ctx *ctx = test->priv;
+	const struct intel_dp_link_caps_test_ops *ops =
+		ctx->link_caps_ops;
+	int i;
+
+	for (i = 0; i < config_set->size; i++) {
+		KUNIT_ASSERT_FALSE(test, has_config(&expected_table->disabled_configs,
+						    &config_set->entries[i]));
+		add_config(test, &expected_table->disabled_configs, &config_set->entries[i]);
+
+		KUNIT_ASSERT_TRUE(test, ops->disable_config(link_caps, &config_set->entries[i]));
+
+		verify_link_caps(expected_table, link_caps);
+	}
+}
+
+static void disable_configs_for_shrink_and_verify(struct test_config_table *expected_table,
+						  struct intel_dp_link_caps *link_caps)
+{
+	struct kunit *test = expected_table->test;
+	struct link_config_set config_set = {};
+	struct intel_dp_link_config max_config;
+
+	/*
+	 * When configs shrink disable the config with the
+	 * second-highest rate,lane params, so the disabled config
+	 * stays around after the configs got shrunk.
+	 */
+	KUNIT_ASSERT_GE(test, expected_table->rates.size, 2);
+	KUNIT_ASSERT_GE(test, expected_table->max_lane_count, 2);
+
+	max_config.rate = expected_table->rates.entries[expected_table->rates.size - 2];
+	max_config.lane_count = expected_table->max_lane_count >> 1;
+
+	add_config(test, &config_set, &max_config);
+	disable_configs_and_verify(test, link_caps, expected_table,
+			&config_set);
+}
+
+static void disable_configs_for_expand_and_verify(struct test_config_table *expected_table,
+						  struct intel_dp_link_caps *link_caps)
+{
+	struct kunit *test = expected_table->test;
+	struct link_config_set config_set = {};
+	struct intel_dp_link_config max_config;
+
+	KUNIT_ASSERT_GE(test, expected_table->rates.size, 1);
+
+	max_config.rate = expected_table->rates.entries[expected_table->rates.size - 1];
+	max_config.lane_count = expected_table->max_lane_count;
+
+	add_config(test, &config_set, &max_config);
+	disable_configs_and_verify(test, link_caps, expected_table,
+				   &config_set);
+}
+
+static void get_nth_rate_lane_config(const struct test_config_table *expected_table, int n,
+				     struct intel_dp_link_config *config)
+{
+	int num_lane_configs = LINK_TEST_NUM_LANE_CONFIGS(expected_table->max_lane_count);
+	int rate_idx = n / num_lane_configs;
+	int lane_count_exp = n % num_lane_configs;
+
+	config->rate = expected_table->rates.entries[rate_idx];
+	config->lane_count = 1 << lane_count_exp;
+}
+
+static void test_update_rates_shrink(struct kunit *test, bool disable_configs)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	while (expected_table.rates.size > 1) {
+		if (disable_configs)
+			disable_configs_for_shrink_and_verify(&expected_table, link_caps);
+
+		expected_table.rates.size--;
+
+		update_link_caps_and_verify(&expected_table, link_caps, false);
+	}
+}
+
+static void intel_dp_link_caps_test_update_rates_shrink(struct kunit *test)
+{
+	test_update_rates_shrink(test, false);
+}
+
+static void intel_dp_link_caps_test_update_rates_shrink_disable(struct kunit *test)
+{
+	test_update_rates_shrink(test, true);
+}
+
+static void test_update_rates_expand(struct kunit *test, bool disable_configs)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, 1, LINK_TEST_MAX_LANE_COUNT);
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	while (expected_table.rates.size < LINK_TEST_NUM_STANDARD_RATES) {
+		if (disable_configs)
+			disable_configs_for_expand_and_verify(&expected_table, link_caps);
+
+		expected_table.rates.size++;
+
+		update_link_caps_and_verify(&expected_table, link_caps, false);
+	}
+}
+
+static void intel_dp_link_caps_test_update_rates_expand(struct kunit *test)
+{
+	test_update_rates_expand(test, false);
+}
+
+static void intel_dp_link_caps_test_update_rates_expand_disable(struct kunit *test)
+{
+	test_update_rates_expand(test, true);
+}
+
+static void test_update_lanes_shrink(struct kunit *test, bool disable_configs)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	while (expected_table.max_lane_count > 1) {
+		if (disable_configs)
+			disable_configs_for_shrink_and_verify(&expected_table, link_caps);
+
+		expected_table.max_lane_count >>= 1;
+
+		update_link_caps_and_verify(&expected_table, link_caps, false);
+	}
+}
+
+static void intel_dp_link_caps_test_update_lanes_shrink(struct kunit *test)
+{
+	test_update_lanes_shrink(test, false);
+}
+
+static void intel_dp_link_caps_test_update_lanes_shrink_disable(struct kunit *test)
+{
+	test_update_lanes_shrink(test, true);
+}
+
+static void test_update_lanes_expand(struct kunit *test, bool disable_configs)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES, 1);
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	while (expected_table.max_lane_count < LINK_TEST_MAX_LANE_COUNT) {
+		if (disable_configs)
+			disable_configs_for_expand_and_verify(&expected_table, link_caps);
+
+		expected_table.max_lane_count <<= 1;
+
+		update_link_caps_and_verify(&expected_table, link_caps, false);
+	}
+}
+
+static void intel_dp_link_caps_test_update_lanes_expand(struct kunit *test)
+{
+	test_update_lanes_expand(test, false);
+}
+
+static void intel_dp_link_caps_test_update_lanes_expand_disable(struct kunit *test)
+{
+	test_update_lanes_expand(test, true);
+}
+
+static void disable_random_configs_and_verify(struct test_config_table *expected_table,
+					      struct intel_dp_link_caps *link_caps)
+{
+	struct kunit *test = expected_table->test;
+	struct test_ctx *ctx = test->priv;
+	struct link_config_set config_set = {};
+	u32 disabled_config_mask;
+	int num_configs;
+	int i;
+
+	num_configs = get_num_configs(expected_table->rates.size,
+				      expected_table->max_lane_count);
+	disabled_config_mask = prandom_u32_state(&ctx->rnd) &
+			       GENMASK_U32(num_configs - 1, 0);
+
+	for (i = 0; i < num_configs; i++) {
+		struct intel_dp_link_config config;
+
+		/* At least one config must remain enabled. */
+		if (expected_table->disabled_configs.size +
+		    config_set.size + 1 >= num_configs)
+			break;
+
+		if (!(BIT(i) & disabled_config_mask))
+			continue;
+
+		get_nth_rate_lane_config(expected_table, i, &config);
+		/* Don't disable a config twice. */
+		if (has_config(&expected_table->disabled_configs, &config))
+			continue;
+
+		add_config(test, &config_set, &config);
+	}
+
+	disable_configs_and_verify(test, link_caps, expected_table,
+				   &config_set);
+}
+
+static void get_params_shrink_step(struct test_ctx *ctx,
+				   int num_rates, int max_lane_count,
+				   int *rates_step, int *lanes_step)
+{
+	int shrink_mask;
+
+	*rates_step = 0;
+	*lanes_step = 0;
+
+	if (num_rates == 1)
+		shrink_mask = BIT(0);				/* shrink only lanes */
+	else if (max_lane_count == 1)
+		shrink_mask = BIT(1);				/* shrink only rates */
+	else
+		shrink_mask = rand_in_range(ctx,
+					    BIT(0),
+					    BIT(0) | BIT(1));	/* shrink one or both params */
+
+	if (shrink_mask & BIT(1))
+		*rates_step = rand_in_range(ctx, 1, num_rates - 1);
+
+	if (shrink_mask & BIT(0))
+		*lanes_step = rand_in_range(ctx, 1, ilog2(max_lane_count));
+}
+
+static void get_params_expand_step(struct test_ctx *ctx,
+				   int max_num_rates, int num_rates,
+				   int max_supported_lane_count, int max_lane_count,
+				   int *rates_step, int *lanes_step)
+{
+	int expand_mask;
+
+	*rates_step = 0;
+	*lanes_step = 0;
+
+	if (num_rates == max_num_rates)
+		expand_mask = BIT(0);				/* expand only lanes */
+	else if (max_lane_count == max_supported_lane_count)
+		expand_mask = BIT(1);				/* expand only rates */
+	else
+		expand_mask = rand_in_range(ctx,
+					    BIT(0),
+					    BIT(0) | BIT(1));	/* expand one or both params */
+
+	if (expand_mask & BIT(1))
+		*rates_step = rand_in_range(ctx, 1, max_num_rates - num_rates);
+
+	if (expand_mask & BIT(0))
+		*lanes_step = rand_in_range(ctx, 1, ilog2(max_supported_lane_count /
+							  max_lane_count));
+}
+
+static void test_update_params_shrink_random(struct kunit *test, bool disable_configs)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+						   LINK_TEST_MAX_LANE_COUNT);
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	while (expected_table.rates.size > 1 || expected_table.max_lane_count > 1) {
+		int rates_step;
+		int lanes_step;
+
+		if (disable_configs)
+			disable_random_configs_and_verify(&expected_table, link_caps);
+
+		get_params_shrink_step(ctx,
+				       expected_table.rates.size,
+				       expected_table.max_lane_count,
+				       &rates_step, &lanes_step);
+
+		expected_table.rates.size -= rates_step;
+		expected_table.max_lane_count >>= lanes_step;
+
+		update_link_caps_and_verify(&expected_table, link_caps, false);
+	}
+}
+
+static void intel_dp_link_caps_test_update_params_shrink_random(struct kunit *test)
+{
+	int i;
+
+	for (i = 0; i < LINK_TEST_NUM_RANDOM_ITERATIONS; i++)
+		test_update_params_shrink_random(test, false);
+}
+
+static void intel_dp_link_caps_test_update_params_shrink_disable_random(struct kunit *test)
+{
+	int i;
+
+	for (i = 0; i < LINK_TEST_NUM_RANDOM_ITERATIONS; i++)
+		test_update_params_shrink_random(test, true);
+}
+
+static void test_update_params_expand_random(struct kunit *test, bool disable_configs)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, 1, 1);
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	while (expected_table.rates.size < LINK_TEST_NUM_STANDARD_RATES ||
+	       expected_table.max_lane_count < LINK_TEST_MAX_LANE_COUNT) {
+		int rates_step;
+		int lanes_step;
+
+		if (disable_configs)
+			disable_random_configs_and_verify(&expected_table, link_caps);
+
+		get_params_expand_step(ctx,
+				       LINK_TEST_NUM_STANDARD_RATES,
+				       expected_table.rates.size,
+				       LINK_TEST_MAX_LANE_COUNT,
+				       expected_table.max_lane_count,
+				       &rates_step, &lanes_step);
+
+		expected_table.rates.size += rates_step;
+		expected_table.max_lane_count <<= lanes_step;
+
+		update_link_caps_and_verify(&expected_table, link_caps, false);
+	}
+}
+
+static void intel_dp_link_caps_test_update_params_expand_random(struct kunit *test)
+{
+	int i;
+
+	for (i = 0; i < LINK_TEST_NUM_RANDOM_ITERATIONS; i++)
+		test_update_params_expand_random(test, false);
+}
+
+static void intel_dp_link_caps_test_update_params_expand_disable_random(struct kunit *test)
+{
+	int i;
+
+	for (i = 0; i < LINK_TEST_NUM_RANDOM_ITERATIONS; i++)
+		test_update_params_expand_random(test, true);
+}
+
 static struct kunit_case intel_dp_link_test_cases[] = {
 	KUNIT_CASE(intel_dp_link_caps_test_baseline),
 
+	KUNIT_CASE(intel_dp_link_caps_test_update_reset),
+
+	KUNIT_CASE(intel_dp_link_caps_test_update_rates_shrink),
+	KUNIT_CASE(intel_dp_link_caps_test_update_rates_shrink_disable),
+	KUNIT_CASE(intel_dp_link_caps_test_update_rates_expand),
+	KUNIT_CASE(intel_dp_link_caps_test_update_rates_expand_disable),
+	KUNIT_CASE(intel_dp_link_caps_test_update_lanes_shrink),
+	KUNIT_CASE(intel_dp_link_caps_test_update_lanes_shrink_disable),
+	KUNIT_CASE(intel_dp_link_caps_test_update_lanes_expand),
+	KUNIT_CASE(intel_dp_link_caps_test_update_lanes_expand_disable),
+	KUNIT_CASE(intel_dp_link_caps_test_update_params_shrink_random),
+	KUNIT_CASE(intel_dp_link_caps_test_update_params_shrink_disable_random),
+	KUNIT_CASE(intel_dp_link_caps_test_update_params_expand_random),
+	KUNIT_CASE(intel_dp_link_caps_test_update_params_expand_disable_random),
+
 	{}
 };
 
-- 
2.49.1

[PATCH v2 34/34] drm/i915/kunit: DP link: add fallback tests

[Imre Deak]

Add KUnit tests for DP link fallback selection across eDP, SST, and MST.
Verify that the fallback logic properly selects the maximum allowed
configuration, iterates through allowed configurations, and disables
failed configs as expected.

These tests include UHBR vs. non-UHBR conditions, MST vs. SST mode,
and validate that subsequent fallback selections respect the updated
allowed configuration mask.

v2:
- Rebase on changes using a filter object instead of a mask of
  configuration indices.
- Rebase on changes using an iteration object.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/tests/intel_dp_link_test.c   | 318 ++++++++++++++++++
 1 file changed, 318 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
index 43283245ad037..14d749962b0ed 100644
--- a/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
+++ b/drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c
@@ -1001,6 +1001,319 @@ static void intel_dp_link_caps_test_update_params_expand_disable_random(struct k
 		test_update_params_expand_random(test, true);
 }
 
+/*
+ * TEST: Fallback sequence
+ * -----------------------
+ * Verify the eDP fallback logic to set the maximum supported configuration
+ * as a preference.
+ *
+ * For DP SST and MST verify fallback selection from the connector's
+ * maximum configuration and iteration of the resulting allowed
+ * configurations.
+ */
+static void intel_dp_link_test_fallback_for_edp(struct kunit *test)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);
+	struct intel_digital_port *dig_port = &ctx->dev.dig_port;
+	const struct intel_dp_link_training_test_ops *lt_ops =
+		ctx->link_training_ops;
+	const struct intel_dp_link_caps_test_ops *lc_ops =
+		ctx->link_caps_ops;
+	struct intel_dp_link_config min_config = {
+		.rate = expected_table.rates.entries[0],
+		.lane_count = 1,
+	};
+	struct intel_dp_link_config max_config = {
+		.rate = expected_table.rates.entries[expected_table.rates.size - 1],
+		.lane_count = LINK_TEST_MAX_LANE_COUNT,
+	};
+	struct intel_dp_link_caps_order order;
+	struct intel_dp_link_config iter_config;
+	struct intel_dp_link_caps_iter iter;
+	int fallback_err;
+
+	dig_port->base.type = INTEL_OUTPUT_EDP;
+	ctx->dev.dig_port.dp.use_max_params = false;
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	order = lc_ops->connector_compute_order(&ctx->dev.connector);
+
+	lc_ops->iter_start(&iter, link_caps, order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &iter_config)
+		break;
+	lc_ops->iter_end(&iter);
+
+	KUNIT_EXPECT_FALSE(test, ctx->dev.dig_port.dp.use_max_params);
+	KUNIT_EXPECT_TRUE(test, link_configs_match(&iter_config, &min_config));
+
+	ctx->dev.crtc_state.output_types = BIT(dig_port->base.type);
+	ctx->dev.crtc_state.port_clock = min_config.rate;
+	ctx->dev.crtc_state.lane_count = min_config.lane_count;
+
+	fallback_err = lt_ops->get_fallback_values(&ctx->dev.dig_port.dp, &ctx->dev.crtc_state);
+	KUNIT_EXPECT_EQ(test, fallback_err, 0);
+
+	/* The fallback should've changed the order. */
+	order = lc_ops->connector_compute_order(&ctx->dev.connector);
+
+	lc_ops->iter_start(&iter, link_caps, order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &iter_config)
+		break;
+	lc_ops->iter_end(&iter);
+
+	KUNIT_EXPECT_TRUE(test, ctx->dev.dig_port.dp.use_max_params);
+	KUNIT_EXPECT_TRUE(test, link_configs_match(&iter_config, &max_config));
+}
+
+static bool test_fallback_from_target(struct test_config_table *expected_table,
+				      enum intel_output_type output_type, int max_rate,
+				      const struct intel_dp_link_config *expected_target_config,
+				      const struct intel_dp_link_config *expected_fallback_config)
+{
+	struct kunit *test = expected_table->test;
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct intel_dp_link_config iter_config;
+	const struct intel_dp_link_training_test_ops *lt_ops =
+		ctx->link_training_ops;
+	const struct intel_dp_link_caps_test_ops *lc_ops =
+		ctx->link_caps_ops;
+	/* Modify default order direction for max config lookup. */
+	struct intel_dp_link_caps_order fallback_order =
+		lc_ops->connector_fallback_order(ctx->dev.connector.mst.dp);
+	struct intel_dp_link_caps_iter iter;
+	int expected_fallback_err = 0;
+	int fallback_err;
+
+	/* Get the max connector config, optionally filtered to the max_rate limit. */
+	lc_ops->iter_start(&iter, link_caps, fallback_order, INTEL_DP_LINK_CAPS_FILTER_ALL);
+	for_each_dp_link_config(&iter, &iter_config)
+		if (max_rate == 0 || iter_config.rate <= max_rate)
+			break;
+	lc_ops->iter_end(&iter);
+
+	KUNIT_EXPECT_TRUE(test, link_configs_match(&iter_config,
+						   expected_target_config));
+	KUNIT_EXPECT_FALSE(test, link_configs_match(&iter_config,
+						    &INTEL_DP_LINK_CONFIG_NULL));
+
+	ctx->dev.crtc_state.output_types = BIT(output_type);
+	ctx->dev.crtc_state.port_clock = expected_target_config->rate;
+	ctx->dev.crtc_state.lane_count = expected_target_config->lane_count;
+
+	if (link_configs_match(expected_fallback_config, &INTEL_DP_LINK_CONFIG_NULL))
+		expected_fallback_err = -1;
+
+	fallback_err = lt_ops->get_fallback_values(&ctx->dev.dig_port.dp, &ctx->dev.crtc_state);
+	KUNIT_EXPECT_EQ(test, fallback_err, expected_fallback_err);
+
+	if (!fallback_err) {
+		/*
+		 * NOTE: This test does not verify any implied fallback
+		 * target selection.
+		 *
+		 * The current driver behavior may still select a fallback
+		 * configuration indirectly via max_limits, but that is an
+		 * implementation artifact rather than part of the intended
+		 * fallback API behavior, and is therefore not verified here.
+		 *
+		 * Instead, the effect of the fallback logic is verified by
+		 * checking that the failed target configuration is disabled.
+		 * Selecting the next target configuration from the remaining
+		 * allowed configurations belongs to the modeset link target
+		 * selection logic.
+		 */
+		add_config(test, &expected_table->disabled_configs,
+			   expected_target_config);
+	}
+
+	verify_link_caps(expected_table, link_caps);
+
+	return !fallback_err;
+}
+
+static const struct link_config_set *
+get_target_configs_for_output_type(struct kunit *test,
+				   enum intel_output_type output_type)
+{
+	switch (output_type) {
+	case INTEL_OUTPUT_DDI:
+	case INTEL_OUTPUT_DP:
+	case INTEL_OUTPUT_EDP:
+		return &standard_dp_link_configs[INTEL_DP_LINK_CAPS_ORDER_KEY_RATE_LANE];
+	case INTEL_OUTPUT_DP_MST:
+		return &standard_dp_link_configs[INTEL_DP_LINK_CAPS_ORDER_KEY_BW];
+	default:
+		KUNIT_FAIL_AND_ABORT(test, "Missing output type: %d", output_type);
+
+	}
+}
+
+static const struct link_config_set *
+get_fallback_configs_for_output_type(struct kunit *test,
+				     enum intel_output_type output_type)
+{
+	switch (output_type) {
+	case INTEL_OUTPUT_DDI:
+	case INTEL_OUTPUT_DP:
+	case INTEL_OUTPUT_EDP:
+		return &standard_dp_link_configs[INTEL_DP_LINK_CAPS_ORDER_KEY_LANE_RATE];
+	case INTEL_OUTPUT_DP_MST:
+		return &standard_dp_link_configs[INTEL_DP_LINK_CAPS_ORDER_KEY_BW];
+	default:
+		KUNIT_FAIL_AND_ABORT(test, "Missing output type: %d", output_type);
+
+	}
+}
+
+static bool output_type_allows_uhbr_fallback(enum intel_output_type output_type)
+{
+	return output_type == INTEL_OUTPUT_DP_MST;
+}
+
+static void assert_config_is_supported(const struct test_config_table *expected_table,
+				       const struct intel_dp_link_config *config)
+{
+	struct kunit *test = expected_table->test;
+
+	KUNIT_ASSERT_TRUE(test, has_rate(&expected_table->rates, config->rate));
+	KUNIT_ASSERT_LE(test, config->lane_count, expected_table->max_lane_count);
+}
+
+static bool get_fallback_config(const struct test_config_table *expected_table,
+				enum intel_output_type output_type,
+				const struct intel_dp_link_config *target_config,
+				struct intel_dp_link_config *fallback_config)
+{
+	struct kunit *test = expected_table->test;
+	const struct link_config_set *config_set =
+		get_fallback_configs_for_output_type(test, output_type);
+	int i;
+
+	i = lookup_config(config_set, target_config);
+	KUNIT_ASSERT_GE(test, i, 0);
+
+	for (i--; i >= 0; i--) {
+		const struct intel_dp_link_config *config =
+			&config_set->entries[i];
+
+		if (output_type_allows_uhbr_fallback(output_type) ||
+		    (drm_dp_is_uhbr_rate(target_config->rate) ==
+		     drm_dp_is_uhbr_rate(config->rate))) {
+			assert_config_is_supported(expected_table, config);
+			*fallback_config = *config;
+
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool get_target_config(const struct test_config_table *expected_table,
+			      enum intel_output_type output_type,
+			      int max_rate,
+			      struct intel_dp_link_config *target)
+{
+	struct kunit *test = expected_table->test;
+	const struct link_config_set *config_set =
+		get_target_configs_for_output_type(test, output_type);
+	int i;
+
+	for (i = config_set->size - 1; i >= 0; i--) {
+		const struct intel_dp_link_config *config =
+			&config_set->entries[i];
+
+		if (config->rate <= max_rate) {
+			assert_config_is_supported(expected_table, config);
+			*target = *config;
+
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static void test_fallback_seq(struct kunit *test,
+			      enum intel_output_type output_type,
+			      bool uhbr)
+{
+	struct test_ctx *ctx = test->priv;
+	struct intel_dp_link_caps *link_caps = ctx->dev.dig_port.dp.link.caps;
+	struct test_config_table expected_table =
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);
+	struct intel_digital_port *dig_port = &ctx->dev.dig_port;
+	struct intel_dp_link_config fallback_config = {};
+	struct intel_dp_link_config target_config;
+	int fallback_count = 0;
+	bool target_found;
+	int max_rate;
+
+	if (uhbr)
+		max_rate = expected_table.rates.entries[expected_table.rates.size - 1];
+	else
+		max_rate = 810000;
+
+	dig_port->base.type = output_type;
+	ctx->dev.dig_port.dp.use_max_params = false;
+
+	update_link_caps_and_verify(&expected_table, link_caps, true);
+
+	/* Get the initial target config. */
+	target_found = get_target_config(&expected_table, output_type,
+					 max_rate, &target_config);
+	KUNIT_ASSERT_TRUE(test, target_found);
+
+	for (;;) {
+		/* Also test the case where no fallback is available. */
+		if (!get_fallback_config(&expected_table, output_type,
+					 &target_config, &fallback_config))
+			fallback_config = INTEL_DP_LINK_CONFIG_NULL;
+
+		if (!test_fallback_from_target(&expected_table, output_type, max_rate,
+					       &target_config, &fallback_config))
+			break;
+
+		/*
+		 * The fallback changed the max rate allowed for the next
+		 * target.
+		 */
+		max_rate = fallback_config.rate;
+
+		/* Simply select the fallback config as the next target. */
+		target_config = fallback_config;
+
+		fallback_count++;
+		KUNIT_ASSERT_LT(test, fallback_count, LINK_TEST_MAX_CONFIGS);
+	}
+}
+
+static void intel_dp_link_test_fallback_for_sst_max_non_uhbr(struct kunit *test)
+{
+	test_fallback_seq(test, INTEL_OUTPUT_DP, false);
+}
+
+static void intel_dp_link_test_fallback_for_sst_max_uhbr(struct kunit *test)
+{
+	test_fallback_seq(test, INTEL_OUTPUT_DP, true);
+}
+
+static void intel_dp_link_test_fallback_for_mst(struct kunit *test)
+{
+	struct test_ctx *ctx = test->priv;
+
+	ctx->dev.connector.mst.dp = &ctx->dev.dig_port.dp;
+
+	test_fallback_seq(test, INTEL_OUTPUT_DP_MST, true);
+}
+
 static struct kunit_case intel_dp_link_test_cases[] = {
 	KUNIT_CASE(intel_dp_link_caps_test_baseline),
 
@@ -1019,6 +1332,11 @@ static struct kunit_case intel_dp_link_test_cases[] = {
 	KUNIT_CASE(intel_dp_link_caps_test_update_params_expand_random),
 	KUNIT_CASE(intel_dp_link_caps_test_update_params_expand_disable_random),
 
+	KUNIT_CASE(intel_dp_link_test_fallback_for_edp),
+	KUNIT_CASE(intel_dp_link_test_fallback_for_sst_max_non_uhbr),
+	KUNIT_CASE(intel_dp_link_test_fallback_for_sst_max_uhbr),
+	KUNIT_CASE(intel_dp_link_test_fallback_for_mst),
+
 	{}
 };
 
-- 
2.49.1

✗ CI.checkpatch: warning for drm/i915/dp_link: Unify modeset/fallback config selection

[Patchwork]

== Series Details ==

Series: drm/i915/dp_link: Unify modeset/fallback config selection
URL   : https://patchwork.freedesktop.org/series/169636/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 44e2734cd99d935b9c03fc727915b949b804b2b9
Author: Imre Deak <imre.deak@intel.com>
Date:   Wed Jul 1 18:32:03 2026 +0300

    drm/i915/kunit: DP link: add fallback tests
    
    Add KUnit tests for DP link fallback selection across eDP, SST, and MST.
    Verify that the fallback logic properly selects the maximum allowed
    configuration, iterates through allowed configurations, and disables
    failed configs as expected.
    
    These tests include UHBR vs. non-UHBR conditions, MST vs. SST mode,
    and validate that subsequent fallback selections respect the updated
    allowed configuration mask.
    
    v2:
    - Rebase on changes using a filter object instead of a mask of
      configuration indices.
    - Rebase on changes using an iteration object.
    
    Signed-off-by: Imre Deak <imre.deak@intel.com>
+ /mt/dim checkpatch f6157a5d128c8b41e39133ce58d1daf430d42bd5 drm-intel
3b29656d39be drm/i915/doc: Document DP link capabilities
-:11: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#11: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 105 lines checked
8546a53e3392 drm/i915/dp_link_caps: Factor out helper to get link config by index
461e4c3ccd54 drm/i915/dp_link_caps: Add support for link rate, lane count iteration orders
79277ca6491e drm/i915/dp_link_caps: Add link configuration iterator
-:38: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#38: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.c:150:
 };
+static_assert(BITS_PER_TYPE(((struct intel_dp_link_caps_filter *)NULL)->config_mask) >=

-:367: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#367: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:106:
+#define for_each_dp_link_config(__iter, __config) \
+	while ((__iter)->get_next_config((__iter), (__config)))

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:367: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__iter' - possible side-effects?
#367: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:106:
+#define for_each_dp_link_config(__iter, __config) \
+	while ((__iter)->get_next_config((__iter), (__config)))

total: 1 errors, 0 warnings, 2 checks, 355 lines checked
415db32698a3 drm/i915/dp_link_caps: Add helper to get iteration order for a connector
e8981adea808 drm/i915/dp_link_caps: Validate max link limits
1bc5984838d0 drm/i915/dp_link_caps: Add filter for enabled link configurations
29af679416f2 drm/i915/dp_link_caps: Re-enable link configurations after a link reset
5cb03e07c673 drm/i915/dp_link_caps: Re-enable link configurations after sink caps change
648dbe2bf0be drm/i915/dp_link_caps: Drop noupdate postfix from max link limit set helpers
2b37eda90efc drm/i915/dp_link_caps: Add debugfs entry showing allowed configurations
cc70387f1aed drm/i915/dp: Add link configuration filter for modeset computation
-:66: WARNING:LONG_LINE: line length of 181 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/intel_dp.c:2644:
+		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max link %dx%d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n",

total: 0 errors, 1 warnings, 0 checks, 197 lines checked
810bfb35f4df drm/i915/dp_link_caps: Add helper to query max BW link configuration
-:35: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.c:565:
+					       bw_desc_config_order().key, INTEL_DP_LINK_CAPS_FILTER_ALL,

total: 0 errors, 1 warnings, 0 checks, 32 lines checked
1b0c24af969f drm/i915/dp: Query max BW config via link_caps during mode validation
7762dc90e7dd drm/i915/dp_tunnel: Query max BW config via link_caps for BW computation
41bcc2a368d8 drm/i915/dp_test: Use link caps for compliance link configs
6ebde4237edb drm/i915/dp: Iterate configurations via link_caps for SST non-DSC
a602cd374ad8 drm/i915/dp: Iterate configurations via link_caps for SST DSC
1470e4998189 drm/i915/dp: Use link caps for eDP DSC config selection
ab613ab44f27 drm/i915/dp_mst: Use link caps for non-DSC config selection
8cd82db18cae drm/i915/dp_mst: Use link caps for MST DSC config selection
9ed53b82f904 drm/i915/dp: Remove min/max link config limits
f82cc26fc36d drm/i915/dp_link_training: Reset the max link limits in the fallback code
893b64e131b1 drm/i915/dp_link_training: Use config iterator for fallback
c2101ba51161 drm/i915/dp_link_training: Disable failed config during fallback
c8ac505c020a drm/i915/kunit: Enable KUnit tests
-:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 30 lines checked
0d940e721ea6 drm/i915/kunit: Add DP link test stub
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 62 lines checked
0e48fa5a6053 drm/xe/kunit: Add display test config
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 15 lines checked
edaf6a993148 drm/xe/kunit: Build DP link display tests
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 20 lines checked
3f41c914da1f drm/i915/kunit: Setup DP link test context
b6ce9ae083e2 drm/i915/kunit: Export link training and caps funcs for testing
-:63: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#63: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:160:
+#define INTEL_DP_LINK_CAPS_TEST_OPS_MEMBERS(__X) \
+	__X(connector_compute_order,	intel_dp_link_caps_connector_compute_order) \
+	__X(connector_fallback_order,	intel_dp_link_caps_connector_fallback_order) \
+	__X(iter_start,			intel_dp_link_caps_iter_start) \
+	__X(iter_end,			intel_dp_link_caps_iter_end) \
+	__X(set_max_limits,		intel_dp_link_caps_set_max_limits) \
+	__X(get_max_limits,		intel_dp_link_caps_get_max_limits) \
+	__X(get_max_bw_config,		intel_dp_link_caps_get_max_bw_config) \
+	__X(reset_max_limits,		intel_dp_link_caps_reset_max_limits) \
+	__X(disable_config,		intel_dp_link_caps_disable_config) \
+	__X(update,			intel_dp_link_caps_update) \
+	__X(init,			intel_dp_link_caps_init) \
+	__X(cleanup,			intel_dp_link_caps_cleanup)

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__X' - possible side-effects?
#63: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:160:
+#define INTEL_DP_LINK_CAPS_TEST_OPS_MEMBERS(__X) \
+	__X(connector_compute_order,	intel_dp_link_caps_connector_compute_order) \
+	__X(connector_fallback_order,	intel_dp_link_caps_connector_fallback_order) \
+	__X(iter_start,			intel_dp_link_caps_iter_start) \
+	__X(iter_end,			intel_dp_link_caps_iter_end) \
+	__X(set_max_limits,		intel_dp_link_caps_set_max_limits) \
+	__X(get_max_limits,		intel_dp_link_caps_get_max_limits) \
+	__X(get_max_bw_config,		intel_dp_link_caps_get_max_bw_config) \
+	__X(reset_max_limits,		intel_dp_link_caps_reset_max_limits) \
+	__X(disable_config,		intel_dp_link_caps_disable_config) \
+	__X(update,			intel_dp_link_caps_update) \
+	__X(init,			intel_dp_link_caps_init) \
+	__X(cleanup,			intel_dp_link_caps_cleanup)

-:77: WARNING:MULTISTATEMENT_MACRO_USE_DO_WHILE: Non-declarative macros with multiple statements should be enclosed in a do - while loop
#77: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:174:
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:77: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__name' may be better as '(__name)' to avoid precedence issues
#77: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:174:
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;

-:77: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#77: FILE: drivers/gpu/drm/i915/display/intel_dp_link_caps.h:174:
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;

-:182: WARNING:MULTISTATEMENT_MACRO_USE_DO_WHILE: Non-declarative macros with multiple statements should be enclosed in a do - while loop
#182: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.h:84:
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;

BUT SEE:

   do {} while (0) advice is over-stated in a few situations:

   The more obvious case is macros, like MODULE_PARM_DESC, invoked at
   file-scope, where C disallows code (it must be in functions).  See
   $exceptions if you have one to add by name.

   More troublesome is declarative macros used at top of new scope,
   like DECLARE_PER_CPU.  These might just compile with a do-while-0
   wrapper, but would be incorrect.  Most of these are handled by
   detecting struct,union,etc declaration primitives in $exceptions.

   Theres also macros called inside an if (block), which "return" an
   expression.  These cannot do-while, and need a ({}) wrapper.

   Enjoy this qualification while we work to improve our heuristics.

-:182: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__name' may be better as '(__name)' to avoid precedence issues
#182: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.h:84:
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;

-:182: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#182: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.h:84:
+#define __DECLARE_MEMBER(__name, __fn) \
+	typeof(__fn) *__name;

total: 1 errors, 4 warnings, 3 checks, 210 lines checked
e5a2b93c0378 drm/i915/kunit: DP link: add baseline fixed table reference test
b18b6b35706d drm/i915/kunit: DP link: add update config tests
-:207: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#207: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:394:
+		for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {

-:269: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#269: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:456:
+		KUNIT_EXPECT_LE(test, iter_config.lane_count,
+				      expected_table->max_lane_count);

-:306: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#306: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:493:
+		for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {

-:334: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#334: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:521:
+		for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {

-:364: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#364: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:551:
+		verify_link_caps_for_order(expected_table, link_caps, config_orders[i], &max_limits);

-:370: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#370: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:557:
+			for (lane_count = 1; lane_count <= expected_table->max_lane_count; lane_count <<= 1) {

-:378: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#378: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:565:
+					KUNIT_EXPECT_FALSE(test, ops->set_max_limits(link_caps, &config));

-:383: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#383: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:570:
+				verify_link_caps_for_order(expected_table, link_caps, config_orders[i],

-:432: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#432: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:619:
+				INIT_STANDARD_TABLE(test, num_rates,
+							     max_lane_count);

-:486: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#486: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:673:
+	disable_configs_and_verify(test, link_caps, expected_table,
+			&config_set);

-:523: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#523: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:710:
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);

-:582: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#582: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:769:
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);

-:731: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#731: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:918:
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+						   LINK_TEST_MAX_LANE_COUNT);

total: 0 errors, 7 warnings, 6 checks, 813 lines checked
44e2734cd99d drm/i915/kunit: DP link: add fallback tests
-:46: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#46: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:1020:
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);

-:180: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#180: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:1154:
+
+	}

-:197: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#197: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:1171:
+
+	}

-:277: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#277: FILE: drivers/gpu/drm/i915/display/tests/intel_dp_link_test.c:1251:
+		INIT_STANDARD_TABLE(test, LINK_TEST_NUM_STANDARD_RATES,
+					  LINK_TEST_MAX_LANE_COUNT);

total: 0 errors, 0 warnings, 4 checks, 330 lines checked

✓ CI.KUnit: success for drm/i915/dp_link: Unify modeset/fallback config selection

[Patchwork]

== Series Details ==

Series: drm/i915/dp_link: Unify modeset/fallback config selection
URL   : https://patchwork.freedesktop.org/series/169636/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:39:03] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:39:07] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
../drivers/gpu/drm/xe/xe_pt.c:1420:13: warning: ‘xe_pt_svm_userptr_notifier_lock’ defined but not used [-Wunused-function]
 1420 | static void xe_pt_svm_userptr_notifier_lock(struct xe_vm *vm)
      |             ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

[16:39:39] Starting KUnit Kernel (1/1)...
[16:39:39] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:39:39] ================== guc_buf (11 subtests) ===================
[16:39:39] [PASSED] test_smallest
[16:39:39] [PASSED] test_largest
[16:39:39] [PASSED] test_granular
[16:39:39] [PASSED] test_unique
[16:39:39] [PASSED] test_overlap
[16:39:39] [PASSED] test_reusable
[16:39:39] [PASSED] test_too_big
[16:39:39] [PASSED] test_flush
[16:39:39] [PASSED] test_lookup
[16:39:39] [PASSED] test_data
[16:39:39] [PASSED] test_class
[16:39:39] ===================== [PASSED] guc_buf =====================
[16:39:39] =================== guc_dbm (7 subtests) ===================
[16:39:39] [PASSED] test_empty
[16:39:39] [PASSED] test_default
[16:39:39] ======================== test_size  ========================
[16:39:39] [PASSED] 4
[16:39:39] [PASSED] 8
[16:39:39] [PASSED] 32
[16:39:39] [PASSED] 256
[16:39:39] ==================== [PASSED] test_size ====================
[16:39:39] ======================= test_reuse  ========================
[16:39:39] [PASSED] 4
[16:39:39] [PASSED] 8
[16:39:39] [PASSED] 32
[16:39:39] [PASSED] 256
[16:39:39] =================== [PASSED] test_reuse ====================
[16:39:39] =================== test_range_overlap  ====================
[16:39:39] [PASSED] 4
[16:39:39] [PASSED] 8
[16:39:39] [PASSED] 32
[16:39:39] [PASSED] 256
[16:39:39] =============== [PASSED] test_range_overlap ================
[16:39:39] =================== test_range_compact  ====================
[16:39:39] [PASSED] 4
[16:39:39] [PASSED] 8
[16:39:39] [PASSED] 32
[16:39:39] [PASSED] 256
[16:39:39] =============== [PASSED] test_range_compact ================
[16:39:39] ==================== test_range_spare  =====================
[16:39:39] [PASSED] 4
[16:39:39] [PASSED] 8
[16:39:39] [PASSED] 32
[16:39:39] [PASSED] 256
[16:39:39] ================ [PASSED] test_range_spare =================
[16:39:39] ===================== [PASSED] guc_dbm =====================
[16:39:39] =================== guc_idm (6 subtests) ===================
[16:39:39] [PASSED] bad_init
[16:39:39] [PASSED] no_init
[16:39:39] [PASSED] init_fini
[16:39:39] [PASSED] check_used
[16:39:39] [PASSED] check_quota
[16:39:39] [PASSED] check_all
[16:39:39] ===================== [PASSED] guc_idm =====================
[16:39:39] ================== no_relay (3 subtests) ===================
[16:39:39] [PASSED] xe_drops_guc2pf_if_not_ready
[16:39:39] [PASSED] xe_drops_guc2vf_if_not_ready
[16:39:39] [PASSED] xe_rejects_send_if_not_ready
[16:39:39] ==================== [PASSED] no_relay =====================
[16:39:39] ================== pf_relay (14 subtests) ==================
[16:39:39] [PASSED] pf_rejects_guc2pf_too_short
[16:39:39] [PASSED] pf_rejects_guc2pf_too_long
[16:39:39] [PASSED] pf_rejects_guc2pf_no_payload
[16:39:39] [PASSED] pf_fails_no_payload
[16:39:39] [PASSED] pf_fails_bad_origin
[16:39:39] [PASSED] pf_fails_bad_type
[16:39:39] [PASSED] pf_txn_reports_error
[16:39:39] [PASSED] pf_txn_sends_pf2guc
[16:39:39] [PASSED] pf_sends_pf2guc
[16:39:39] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[16:39:39] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[16:39:39] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[16:39:39] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[16:39:39] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[16:39:39] ==================== [PASSED] pf_relay =====================
[16:39:39] ================== vf_relay (3 subtests) ===================
[16:39:39] [PASSED] vf_rejects_guc2vf_too_short
[16:39:39] [PASSED] vf_rejects_guc2vf_too_long
[16:39:39] [PASSED] vf_rejects_guc2vf_no_payload
[16:39:39] ==================== [PASSED] vf_relay =====================
[16:39:39] ================ pf_gt_config (9 subtests) =================
[16:39:39] [PASSED] fair_contexts_1vf
[16:39:39] [PASSED] fair_doorbells_1vf
[16:39:39] [PASSED] fair_ggtt_1vf
[16:39:39] ====================== fair_vram_1vf  ======================
[16:39:39] [PASSED] 3.50 GiB
[16:39:39] [PASSED] 11.5 GiB
[16:39:39] [PASSED] 15.5 GiB
[16:39:39] [PASSED] 31.5 GiB
[16:39:39] [PASSED] 63.5 GiB
[16:39:39] [PASSED] 1.91 GiB
[16:39:39] ================== [PASSED] fair_vram_1vf ==================
[16:39:39] ================ fair_vram_1vf_admin_only  =================
[16:39:39] [PASSED] 3.50 GiB
[16:39:39] [PASSED] 11.5 GiB
[16:39:39] [PASSED] 15.5 GiB
[16:39:39] [PASSED] 31.5 GiB
[16:39:39] [PASSED] 63.5 GiB
[16:39:39] [PASSED] 1.91 GiB
[16:39:39] ============ [PASSED] fair_vram_1vf_admin_only =============
[16:39:39] ====================== fair_contexts  ======================
[16:39:39] [PASSED] 1 VF
[16:39:39] [PASSED] 2 VFs
[16:39:39] [PASSED] 3 VFs
[16:39:39] [PASSED] 4 VFs
[16:39:39] [PASSED] 5 VFs
[16:39:39] [PASSED] 6 VFs
[16:39:39] [PASSED] 7 VFs
[16:39:39] [PASSED] 8 VFs
[16:39:39] [PASSED] 9 VFs
[16:39:39] [PASSED] 10 VFs
[16:39:39] [PASSED] 11 VFs
[16:39:39] [PASSED] 12 VFs
[16:39:39] [PASSED] 13 VFs
[16:39:39] [PASSED] 14 VFs
[16:39:39] [PASSED] 15 VFs
[16:39:39] [PASSED] 16 VFs
[16:39:39] [PASSED] 17 VFs
[16:39:39] [PASSED] 18 VFs
[16:39:39] [PASSED] 19 VFs
[16:39:39] [PASSED] 20 VFs
[16:39:39] [PASSED] 21 VFs
[16:39:39] [PASSED] 22 VFs
[16:39:39] [PASSED] 23 VFs
[16:39:39] [PASSED] 24 VFs
[16:39:39] [PASSED] 25 VFs
[16:39:39] [PASSED] 26 VFs
[16:39:39] [PASSED] 27 VFs
[16:39:39] [PASSED] 28 VFs
[16:39:39] [PASSED] 29 VFs
[16:39:39] [PASSED] 30 VFs
[16:39:39] [PASSED] 31 VFs
[16:39:39] [PASSED] 32 VFs
[16:39:39] [PASSED] 33 VFs
[16:39:39] [PASSED] 34 VFs
[16:39:39] [PASSED] 35 VFs
[16:39:39] [PASSED] 36 VFs
[16:39:39] [PASSED] 37 VFs
[16:39:39] [PASSED] 38 VFs
[16:39:39] [PASSED] 39 VFs
[16:39:39] [PASSED] 40 VFs
[16:39:39] [PASSED] 41 VFs
[16:39:39] [PASSED] 42 VFs
[16:39:39] [PASSED] 43 VFs
[16:39:39] [PASSED] 44 VFs
[16:39:39] [PASSED] 45 VFs
[16:39:39] [PASSED] 46 VFs
[16:39:39] [PASSED] 47 VFs
[16:39:39] [PASSED] 48 VFs
[16:39:39] [PASSED] 49 VFs
[16:39:39] [PASSED] 50 VFs
[16:39:39] [PASSED] 51 VFs
[16:39:39] [PASSED] 52 VFs
[16:39:39] [PASSED] 53 VFs
[16:39:39] [PASSED] 54 VFs
[16:39:39] [PASSED] 55 VFs
[16:39:39] [PASSED] 56 VFs
[16:39:39] [PASSED] 57 VFs
[16:39:39] [PASSED] 58 VFs
[16:39:39] [PASSED] 59 VFs
[16:39:39] [PASSED] 60 VFs
[16:39:39] [PASSED] 61 VFs
[16:39:39] [PASSED] 62 VFs
[16:39:39] [PASSED] 63 VFs
[16:39:39] ================== [PASSED] fair_contexts ==================
[16:39:39] ===================== fair_doorbells  ======================
[16:39:39] [PASSED] 1 VF
[16:39:39] [PASSED] 2 VFs
[16:39:39] [PASSED] 3 VFs
[16:39:39] [PASSED] 4 VFs
[16:39:39] [PASSED] 5 VFs
[16:39:39] [PASSED] 6 VFs
[16:39:39] [PASSED] 7 VFs
[16:39:39] [PASSED] 8 VFs
[16:39:39] [PASSED] 9 VFs
[16:39:39] [PASSED] 10 VFs
[16:39:39] [PASSED] 11 VFs
[16:39:39] [PASSED] 12 VFs
[16:39:39] [PASSED] 13 VFs
[16:39:39] [PASSED] 14 VFs
[16:39:39] [PASSED] 15 VFs
[16:39:39] [PASSED] 16 VFs
[16:39:39] [PASSED] 17 VFs
[16:39:39] [PASSED] 18 VFs
[16:39:39] [PASSED] 19 VFs
[16:39:39] [PASSED] 20 VFs
[16:39:39] [PASSED] 21 VFs
[16:39:39] [PASSED] 22 VFs
[16:39:39] [PASSED] 23 VFs
[16:39:39] [PASSED] 24 VFs
[16:39:39] [PASSED] 25 VFs
[16:39:39] [PASSED] 26 VFs
[16:39:39] [PASSED] 27 VFs
[16:39:39] [PASSED] 28 VFs
[16:39:39] [PASSED] 29 VFs
[16:39:39] [PASSED] 30 VFs
[16:39:39] [PASSED] 31 VFs
[16:39:39] [PASSED] 32 VFs
[16:39:39] [PASSED] 33 VFs
[16:39:39] [PASSED] 34 VFs
[16:39:39] [PASSED] 35 VFs
[16:39:39] [PASSED] 36 VFs
[16:39:39] [PASSED] 37 VFs
[16:39:39] [PASSED] 38 VFs
[16:39:39] [PASSED] 39 VFs
[16:39:39] [PASSED] 40 VFs
[16:39:39] [PASSED] 41 VFs
[16:39:39] [PASSED] 42 VFs
[16:39:39] [PASSED] 43 VFs
[16:39:39] [PASSED] 44 VFs
[16:39:39] [PASSED] 45 VFs
[16:39:39] [PASSED] 46 VFs
[16:39:39] [PASSED] 47 VFs
[16:39:39] [PASSED] 48 VFs
[16:39:39] [PASSED] 49 VFs
[16:39:39] [PASSED] 50 VFs
[16:39:39] [PASSED] 51 VFs
[16:39:39] [PASSED] 52 VFs
[16:39:39] [PASSED] 53 VFs
[16:39:39] [PASSED] 54 VFs
[16:39:39] [PASSED] 55 VFs
[16:39:39] [PASSED] 56 VFs
[16:39:39] [PASSED] 57 VFs
[16:39:39] [PASSED] 58 VFs
[16:39:39] [PASSED] 59 VFs
[16:39:39] [PASSED] 60 VFs
[16:39:39] [PASSED] 61 VFs
[16:39:39] [PASSED] 62 VFs
[16:39:39] [PASSED] 63 VFs
[16:39:39] ================= [PASSED] fair_doorbells ==================
[16:39:39] ======================== fair_ggtt  ========================
[16:39:39] [PASSED] 1 VF
[16:39:39] [PASSED] 2 VFs
[16:39:39] [PASSED] 3 VFs
[16:39:39] [PASSED] 4 VFs
[16:39:39] [PASSED] 5 VFs
[16:39:39] [PASSED] 6 VFs
[16:39:39] [PASSED] 7 VFs
[16:39:39] [PASSED] 8 VFs
[16:39:39] [PASSED] 9 VFs
[16:39:39] [PASSED] 10 VFs
[16:39:39] [PASSED] 11 VFs
[16:39:39] [PASSED] 12 VFs
[16:39:39] [PASSED] 13 VFs
[16:39:39] [PASSED] 14 VFs
[16:39:39] [PASSED] 15 VFs
[16:39:39] [PASSED] 16 VFs
[16:39:39] [PASSED] 17 VFs
[16:39:39] [PASSED] 18 VFs
[16:39:39] [PASSED] 19 VFs
[16:39:39] [PASSED] 20 VFs
[16:39:39] [PASSED] 21 VFs
[16:39:39] [PASSED] 22 VFs
[16:39:39] [PASSED] 23 VFs
[16:39:39] [PASSED] 24 VFs
[16:39:39] [PASSED] 25 VFs
[16:39:40] [PASSED] 26 VFs
[16:39:40] [PASSED] 27 VFs
[16:39:40] [PASSED] 28 VFs
[16:39:40] [PASSED] 29 VFs
[16:39:40] [PASSED] 30 VFs
[16:39:40] [PASSED] 31 VFs
[16:39:40] [PASSED] 32 VFs
[16:39:40] [PASSED] 33 VFs
[16:39:40] [PASSED] 34 VFs
[16:39:40] [PASSED] 35 VFs
[16:39:40] [PASSED] 36 VFs
[16:39:40] [PASSED] 37 VFs
[16:39:40] [PASSED] 38 VFs
[16:39:40] [PASSED] 39 VFs
[16:39:40] [PASSED] 40 VFs
[16:39:40] [PASSED] 41 VFs
[16:39:40] [PASSED] 42 VFs
[16:39:40] [PASSED] 43 VFs
[16:39:40] [PASSED] 44 VFs
[16:39:40] [PASSED] 45 VFs
[16:39:40] [PASSED] 46 VFs
[16:39:40] [PASSED] 47 VFs
[16:39:40] [PASSED] 48 VFs
[16:39:40] [PASSED] 49 VFs
[16:39:40] [PASSED] 50 VFs
[16:39:40] [PASSED] 51 VFs
[16:39:40] [PASSED] 52 VFs
[16:39:40] [PASSED] 53 VFs
[16:39:40] [PASSED] 54 VFs
[16:39:40] [PASSED] 55 VFs
[16:39:40] [PASSED] 56 VFs
[16:39:40] [PASSED] 57 VFs
[16:39:40] [PASSED] 58 VFs
[16:39:40] [PASSED] 59 VFs
[16:39:40] [PASSED] 60 VFs
[16:39:40] [PASSED] 61 VFs
[16:39:40] [PASSED] 62 VFs
[16:39:40] [PASSED] 63 VFs
[16:39:40] ==================== [PASSED] fair_ggtt ====================
[16:39:40] ======================== fair_vram  ========================
[16:39:40] [PASSED] 1 VF
[16:39:40] [PASSED] 2 VFs
[16:39:40] [PASSED] 3 VFs
[16:39:40] [PASSED] 4 VFs
[16:39:40] [PASSED] 5 VFs
[16:39:40] [PASSED] 6 VFs
[16:39:40] [PASSED] 7 VFs
[16:39:40] [PASSED] 8 VFs
[16:39:40] [PASSED] 9 VFs
[16:39:40] [PASSED] 10 VFs
[16:39:40] [PASSED] 11 VFs
[16:39:40] [PASSED] 12 VFs
[16:39:40] [PASSED] 13 VFs
[16:39:40] [PASSED] 14 VFs
[16:39:40] [PASSED] 15 VFs
[16:39:40] [PASSED] 16 VFs
[16:39:40] [PASSED] 17 VFs
[16:39:40] [PASSED] 18 VFs
[16:39:40] [PASSED] 19 VFs
[16:39:40] [PASSED] 20 VFs
[16:39:40] [PASSED] 21 VFs
[16:39:40] [PASSED] 22 VFs
[16:39:40] [PASSED] 23 VFs
[16:39:40] [PASSED] 24 VFs
[16:39:40] [PASSED] 25 VFs
[16:39:40] [PASSED] 26 VFs
[16:39:40] [PASSED] 27 VFs
[16:39:40] [PASSED] 28 VFs
[16:39:40] [PASSED] 29 VFs
[16:39:40] [PASSED] 30 VFs
[16:39:40] [PASSED] 31 VFs
[16:39:40] [PASSED] 32 VFs
[16:39:40] [PASSED] 33 VFs
[16:39:40] [PASSED] 34 VFs
[16:39:40] [PASSED] 35 VFs
[16:39:40] [PASSED] 36 VFs
[16:39:40] [PASSED] 37 VFs
[16:39:40] [PASSED] 38 VFs
[16:39:40] [PASSED] 39 VFs
[16:39:40] [PASSED] 40 VFs
[16:39:40] [PASSED] 41 VFs
[16:39:40] [PASSED] 42 VFs
[16:39:40] [PASSED] 43 VFs
[16:39:40] [PASSED] 44 VFs
[16:39:40] [PASSED] 45 VFs
[16:39:40] [PASSED] 46 VFs
[16:39:40] [PASSED] 47 VFs
[16:39:40] [PASSED] 48 VFs
[16:39:40] [PASSED] 49 VFs
[16:39:40] [PASSED] 50 VFs
[16:39:40] [PASSED] 51 VFs
[16:39:40] [PASSED] 52 VFs
[16:39:40] [PASSED] 53 VFs
[16:39:40] [PASSED] 54 VFs
[16:39:40] [PASSED] 55 VFs
[16:39:40] [PASSED] 56 VFs
[16:39:40] [PASSED] 57 VFs
[16:39:40] [PASSED] 58 VFs
[16:39:40] [PASSED] 59 VFs
[16:39:40] [PASSED] 60 VFs
[16:39:40] [PASSED] 61 VFs
[16:39:40] [PASSED] 62 VFs
[16:39:40] [PASSED] 63 VFs
[16:39:40] ==================== [PASSED] fair_vram ====================
[16:39:40] ================== [PASSED] pf_gt_config ===================
[16:39:40] ===================== lmtt (1 subtest) =====================
[16:39:40] ======================== test_ops  =========================
[16:39:40] [PASSED] 2-level
[16:39:40] [PASSED] multi-level
[16:39:40] ==================== [PASSED] test_ops =====================
[16:39:40] ====================== [PASSED] lmtt =======================
[16:39:40] ================= pf_service (11 subtests) =================
[16:39:40] [PASSED] pf_negotiate_any
[16:39:40] [PASSED] pf_negotiate_base_match
[16:39:40] [PASSED] pf_negotiate_base_newer
[16:39:40] [PASSED] pf_negotiate_base_next
[16:39:40] [SKIPPED] pf_negotiate_base_older (no older minor)
[16:39:40] [PASSED] pf_negotiate_base_prev
[16:39:40] [PASSED] pf_negotiate_latest_match
[16:39:40] [PASSED] pf_negotiate_latest_newer
[16:39:40] [PASSED] pf_negotiate_latest_next
[16:39:40] [SKIPPED] pf_negotiate_latest_older (no older minor)
[16:39:40] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[16:39:40] =================== [PASSED] pf_service ====================
[16:39:40] ================= xe_guc_g2g (2 subtests) ==================
[16:39:40] ============== xe_live_guc_g2g_kunit_default  ==============
[16:39:40] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[16:39:40] ============== xe_live_guc_g2g_kunit_allmem  ===============
[16:39:40] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[16:39:40] =================== [SKIPPED] xe_guc_g2g ===================
[16:39:40] =================== xe_mocs (2 subtests) ===================
[16:39:40] ================ xe_live_mocs_kernel_kunit  ================
[16:39:40] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:39:40] ================ xe_live_mocs_reset_kunit  =================
[16:39:40] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:39:40] ==================== [SKIPPED] xe_mocs =====================
[16:39:40] ================= xe_migrate (2 subtests) ==================
[16:39:40] ================= xe_migrate_sanity_kunit  =================
[16:39:40] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:39:40] ================== xe_validate_ccs_kunit  ==================
[16:39:40] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:39:40] =================== [SKIPPED] xe_migrate ===================
[16:39:40] ================== xe_dma_buf (1 subtest) ==================
[16:39:40] ==================== xe_dma_buf_kunit  =====================
[16:39:40] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:39:40] =================== [SKIPPED] xe_dma_buf ===================
[16:39:40] ================= xe_bo_shrink (1 subtest) =================
[16:39:40] =================== xe_bo_shrink_kunit  ====================
[16:39:40] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:39:40] ================== [SKIPPED] xe_bo_shrink ==================
[16:39:40] ==================== xe_bo (2 subtests) ====================
[16:39:40] ================== xe_ccs_migrate_kunit  ===================
[16:39:40] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:39:40] ==================== xe_bo_evict_kunit  ====================
[16:39:40] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:39:40] ===================== [SKIPPED] xe_bo ======================
[16:39:40] ==================== args (13 subtests) ====================
[16:39:40] [PASSED] count_args_test
[16:39:40] [PASSED] call_args_example
[16:39:40] [PASSED] call_args_test
[16:39:40] [PASSED] drop_first_arg_example
[16:39:40] [PASSED] drop_first_arg_test
[16:39:40] [PASSED] first_arg_example
[16:39:40] [PASSED] first_arg_test
[16:39:40] [PASSED] last_arg_example
[16:39:40] [PASSED] last_arg_test
[16:39:40] [PASSED] pick_arg_example
[16:39:40] [PASSED] if_args_example
[16:39:40] [PASSED] if_args_test
[16:39:40] [PASSED] sep_comma_example
[16:39:40] ====================== [PASSED] args =======================
[16:39:40] =================== xe_pci (3 subtests) ====================
[16:39:40] ==================== check_graphics_ip  ====================
[16:39:40] [PASSED] 12.00 Xe_LP
[16:39:40] [PASSED] 12.10 Xe_LP+
[16:39:40] [PASSED] 12.55 Xe_HPG
[16:39:40] [PASSED] 12.60 Xe_HPC
[16:39:40] [PASSED] 12.70 Xe_LPG
[16:39:40] [PASSED] 12.71 Xe_LPG
[16:39:40] [PASSED] 12.74 Xe_LPG+
[16:39:40] [PASSED] 20.01 Xe2_HPG
[16:39:40] [PASSED] 20.02 Xe2_HPG
[16:39:40] [PASSED] 20.04 Xe2_LPG
[16:39:40] [PASSED] 30.00 Xe3_LPG
[16:39:40] [PASSED] 30.01 Xe3_LPG
[16:39:40] [PASSED] 30.03 Xe3_LPG
[16:39:40] [PASSED] 30.04 Xe3_LPG
[16:39:40] [PASSED] 30.05 Xe3_LPG
[16:39:40] [PASSED] 35.10 Xe3p_LPG
[16:39:40] [PASSED] 35.11 Xe3p_XPC
[16:39:40] ================ [PASSED] check_graphics_ip ================
[16:39:40] ===================== check_media_ip  ======================
[16:39:40] [PASSED] 12.00 Xe_M
[16:39:40] [PASSED] 12.55 Xe_HPM
[16:39:40] [PASSED] 13.00 Xe_LPM+
[16:39:40] [PASSED] 13.01 Xe2_HPM
[16:39:40] [PASSED] 20.00 Xe2_LPM
[16:39:40] [PASSED] 30.00 Xe3_LPM
[16:39:40] [PASSED] 30.02 Xe3_LPM
[16:39:40] [PASSED] 35.00 Xe3p_LPM
[16:39:40] [PASSED] 35.03 Xe3p_HPM
[16:39:40] ================= [PASSED] check_media_ip ==================
[16:39:40] =================== check_platform_desc  ===================
[16:39:40] [PASSED] 0x9A60 (TIGERLAKE)
[16:39:40] [PASSED] 0x9A68 (TIGERLAKE)
[16:39:40] [PASSED] 0x9A70 (TIGERLAKE)
[16:39:40] [PASSED] 0x9A40 (TIGERLAKE)
[16:39:40] [PASSED] 0x9A49 (TIGERLAKE)
[16:39:40] [PASSED] 0x9A59 (TIGERLAKE)
[16:39:40] [PASSED] 0x9A78 (TIGERLAKE)
[16:39:40] [PASSED] 0x9AC0 (TIGERLAKE)
[16:39:40] [PASSED] 0x9AC9 (TIGERLAKE)
[16:39:40] [PASSED] 0x9AD9 (TIGERLAKE)
[16:39:40] [PASSED] 0x9AF8 (TIGERLAKE)
[16:39:40] [PASSED] 0x4C80 (ROCKETLAKE)
[16:39:40] [PASSED] 0x4C8A (ROCKETLAKE)
[16:39:40] [PASSED] 0x4C8B (ROCKETLAKE)
[16:39:40] [PASSED] 0x4C8C (ROCKETLAKE)
[16:39:40] [PASSED] 0x4C90 (ROCKETLAKE)
[16:39:40] [PASSED] 0x4C9A (ROCKETLAKE)
[16:39:40] [PASSED] 0x4680 (ALDERLAKE_S)
[16:39:40] [PASSED] 0x4682 (ALDERLAKE_S)
[16:39:40] [PASSED] 0x4688 (ALDERLAKE_S)
[16:39:40] [PASSED] 0x468A (ALDERLAKE_S)
[16:39:40] [PASSED] 0x468B (ALDERLAKE_S)
[16:39:40] [PASSED] 0x4690 (ALDERLAKE_S)
[16:39:40] [PASSED] 0x4692 (ALDERLAKE_S)
[16:39:40] [PASSED] 0x4693 (ALDERLAKE_S)
[16:39:40] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46AA (ALDERLAKE_P)
[16:39:40] [PASSED] 0x462A (ALDERLAKE_P)
[16:39:40] [PASSED] 0x4626 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x4628 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:39:40] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:39:40] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:39:40] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:39:40] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:39:40] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:39:40] [PASSED] 0xA721 (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA720 (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:39:40] [PASSED] 0xA780 (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA781 (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA782 (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA783 (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA788 (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA789 (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA78A (ALDERLAKE_S)
[16:39:40] [PASSED] 0xA78B (ALDERLAKE_S)
[16:39:40] [PASSED] 0x4905 (DG1)
[16:39:40] [PASSED] 0x4906 (DG1)
[16:39:40] [PASSED] 0x4907 (DG1)
[16:39:40] [PASSED] 0x4908 (DG1)
[16:39:40] [PASSED] 0x4909 (DG1)
[16:39:40] [PASSED] 0x56C0 (DG2)
[16:39:40] [PASSED] 0x56C2 (DG2)
[16:39:40] [PASSED] 0x56C1 (DG2)
[16:39:40] [PASSED] 0x7D51 (METEORLAKE)
[16:39:40] [PASSED] 0x7DD1 (METEORLAKE)
[16:39:40] [PASSED] 0x7D41 (METEORLAKE)
[16:39:40] [PASSED] 0x7D67 (METEORLAKE)
[16:39:40] [PASSED] 0xB640 (METEORLAKE)
[16:39:40] [PASSED] 0x56A0 (DG2)
[16:39:40] [PASSED] 0x56A1 (DG2)
[16:39:40] [PASSED] 0x56A2 (DG2)
[16:39:40] [PASSED] 0x56BE (DG2)
[16:39:40] [PASSED] 0x56BF (DG2)
[16:39:40] [PASSED] 0x5690 (DG2)
[16:39:40] [PASSED] 0x5691 (DG2)
[16:39:40] [PASSED] 0x5692 (DG2)
[16:39:40] [PASSED] 0x56A5 (DG2)
[16:39:40] [PASSED] 0x56A6 (DG2)
[16:39:40] [PASSED] 0x56B0 (DG2)
[16:39:40] [PASSED] 0x56B1 (DG2)
[16:39:40] [PASSED] 0x56BA (DG2)
[16:39:40] [PASSED] 0x56BB (DG2)
[16:39:40] [PASSED] 0x56BC (DG2)
[16:39:40] [PASSED] 0x56BD (DG2)
[16:39:40] [PASSED] 0x5693 (DG2)
[16:39:40] [PASSED] 0x5694 (DG2)
[16:39:40] [PASSED] 0x5695 (DG2)
[16:39:40] [PASSED] 0x56A3 (DG2)
[16:39:40] [PASSED] 0x56A4 (DG2)
[16:39:40] [PASSED] 0x56B2 (DG2)
[16:39:40] [PASSED] 0x56B3 (DG2)
[16:39:40] [PASSED] 0x5696 (DG2)
[16:39:40] [PASSED] 0x5697 (DG2)
[16:39:40] [PASSED] 0xB69 (PVC)
[16:39:40] [PASSED] 0xB6E (PVC)
[16:39:40] [PASSED] 0xBD4 (PVC)
[16:39:40] [PASSED] 0xBD5 (PVC)
[16:39:40] [PASSED] 0xBD6 (PVC)
[16:39:40] [PASSED] 0xBD7 (PVC)
[16:39:40] [PASSED] 0xBD8 (PVC)
[16:39:40] [PASSED] 0xBD9 (PVC)
[16:39:40] [PASSED] 0xBDA (PVC)
[16:39:40] [PASSED] 0xBDB (PVC)
[16:39:40] [PASSED] 0xBE0 (PVC)
[16:39:40] [PASSED] 0xBE1 (PVC)
[16:39:40] [PASSED] 0xBE5 (PVC)
[16:39:40] [PASSED] 0x7D40 (METEORLAKE)
[16:39:40] [PASSED] 0x7D45 (METEORLAKE)
[16:39:40] [PASSED] 0x7D55 (METEORLAKE)
[16:39:40] [PASSED] 0x7D60 (METEORLAKE)
[16:39:40] [PASSED] 0x7DD5 (METEORLAKE)
[16:39:40] [PASSED] 0x6420 (LUNARLAKE)
[16:39:40] [PASSED] 0x64A0 (LUNARLAKE)
[16:39:40] [PASSED] 0x64B0 (LUNARLAKE)
[16:39:40] [PASSED] 0xE202 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE209 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE20B (BATTLEMAGE)
[16:39:40] [PASSED] 0xE20C (BATTLEMAGE)
[16:39:40] [PASSED] 0xE20D (BATTLEMAGE)
[16:39:40] [PASSED] 0xE210 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE211 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE212 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE216 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE220 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE221 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE222 (BATTLEMAGE)
[16:39:40] [PASSED] 0xE223 (BATTLEMAGE)
[16:39:40] [PASSED] 0xB080 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB081 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB082 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB083 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB084 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB085 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB086 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB087 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB08F (PANTHERLAKE)
[16:39:40] [PASSED] 0xB090 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:39:40] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:39:40] [PASSED] 0xFD80 (PANTHERLAKE)
[16:39:40] [PASSED] 0xFD81 (PANTHERLAKE)
[16:39:40] [PASSED] 0xD740 (NOVALAKE_S)
[16:39:40] [PASSED] 0xD741 (NOVALAKE_S)
[16:39:40] [PASSED] 0xD742 (NOVALAKE_S)
[16:39:40] [PASSED] 0xD743 (NOVALAKE_S)
[16:39:40] [PASSED] 0xD745 (NOVALAKE_S)
[16:39:40] [PASSED] 0xD74A (NOVALAKE_S)
[16:39:40] [PASSED] 0xD74B (NOVALAKE_S)
[16:39:40] [PASSED] 0x674C (CRESCENTISLAND)
[16:39:40] [PASSED] 0x674D (CRESCENTISLAND)
[16:39:40] [PASSED] 0x674E (CRESCENTISLAND)
[16:39:40] [PASSED] 0x674F (CRESCENTISLAND)
[16:39:40] [PASSED] 0x6750 (CRESCENTISLAND)
[16:39:40] [PASSED] 0xD750 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD751 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD752 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD753 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD754 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD755 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD756 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD757 (NOVALAKE_P)
[16:39:40] [PASSED] 0xD75F (NOVALAKE_P)
[16:39:40] =============== [PASSED] check_platform_desc ===============
[16:39:40] ===================== [PASSED] xe_pci ======================
[16:39:40] ============= xe_rtp_tables_test (5 subtests) ==============
[16:39:40] ================== xe_rtp_table_gt_test  ===================
[16:39:40] [PASSED] gt_was/14011060649
[16:39:40] [PASSED] gt_was/14011059788
[16:39:40] [PASSED] gt_was/14015795083
[16:39:40] [PASSED] gt_was/16021867713
[16:39:40] [PASSED] gt_was/14019449301
[16:39:40] [PASSED] gt_was/16028005424
[16:39:40] [PASSED] gt_was/14026578760
[16:39:40] [PASSED] gt_was/1409420604
[16:39:40] [PASSED] gt_was/1408615072
[16:39:40] [PASSED] gt_was/22010523718
[16:39:40] [PASSED] gt_was/14011006942
[16:39:40] [PASSED] gt_was/14014830051
[16:39:40] [PASSED] gt_was/18018781329
[16:39:40] [PASSED] gt_was/1509235366
[16:39:40] [PASSED] gt_was/18018781329
[16:39:40] [PASSED] gt_was/16016694945
[16:39:40] [PASSED] gt_was/14018575942
[16:39:40] [PASSED] gt_was/22016670082
[16:39:40] [PASSED] gt_was/22016670082
[16:39:40] [PASSED] gt_was/14017421178
[16:39:40] [PASSED] gt_was/16025250150
[16:39:40] [PASSED] gt_was/14021871409
[16:39:40] [PASSED] gt_was/16021865536
[16:39:40] [PASSED] gt_was/14021486841
[16:39:40] [PASSED] gt_was/14025160223
[16:39:40] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[16:39:40] [PASSED] gt_was/14025635424
[16:39:40] [PASSED] gt_was/16028005424
[16:39:40] ============== [PASSED] xe_rtp_table_gt_test ===============
[16:39:40] ================== xe_rtp_table_gt_test  ===================
[16:39:40] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[16:39:40] [PASSED] gt_tunings/Tuning: 32B Access Enable
[16:39:40] [PASSED] gt_tunings/Tuning: L3 cache
[16:39:40] [PASSED] gt_tunings/Tuning: L3 cache - media
[16:39:40] [PASSED] gt_tunings/Tuning: Compression Overfetch
[16:39:40] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[16:39:40] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[16:39:40] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[16:39:40] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[16:39:40] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[16:39:40] [PASSED] gt_tunings/Tuning: Stateless compression control
[16:39:40] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[16:39:40] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[16:39:40] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[16:39:40] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[16:39:40] ============== [PASSED] xe_rtp_table_gt_test ===============
[16:39:40] ================== xe_rtp_table_oob_test  ==================
[16:39:40] [PASSED] oob_was/1607983814
[16:39:40] [PASSED] oob_was/16010904313
[16:39:40] [PASSED] oob_was/18022495364
[16:39:40] [PASSED] oob_was/22012773006
[16:39:40] [PASSED] oob_was/14014475959
[16:39:40] [PASSED] oob_was/22011391025
[16:39:40] [PASSED] oob_was/22012727170
[16:39:40] [PASSED] oob_was/22012727685
[16:39:40] [PASSED] oob_was/22016596838
[16:39:40] [PASSED] oob_was/18020744125
[16:39:40] [PASSED] oob_was/1409600907
[16:39:40] [PASSED] oob_was/22014953428
[16:39:40] [PASSED] oob_was/16017236439
[16:39:40] [PASSED] oob_was/14019821291
[16:39:40] [PASSED] oob_was/14015076503
[16:39:40] [PASSED] oob_was/14018913170
[16:39:40] [PASSED] oob_was/14018094691
[16:39:40] [PASSED] oob_was/18024947630
[16:39:40] [PASSED] oob_was/16022287689
[16:39:40] [PASSED] oob_was/13011645652
[16:39:40] [PASSED] oob_was/14022293748
[16:39:40] [PASSED] oob_was/22019794406
[16:39:40] [PASSED] oob_was/22019338487
[16:39:40] [PASSED] oob_was/16023588340
[16:39:40] [PASSED] oob_was/14019789679
[16:39:40] [PASSED] oob_was/14022866841
[16:39:40] [PASSED] oob_was/16021333562
[16:39:40] [PASSED] oob_was/14016712196
[16:39:40] [PASSED] oob_was/14015568240
[16:39:40] [PASSED] oob_was/18013179988
[16:39:40] [PASSED] oob_was/1508761755
[16:39:40] [PASSED] oob_was/16023105232
[16:39:40] [PASSED] oob_was/16026508708
[16:39:40] [PASSED] oob_was/14020001231
[16:39:40] [PASSED] oob_was/16023683509
[16:39:40] [PASSED] oob_was/14025515070
[16:39:40] [PASSED] oob_was/15015404425_disable
[16:39:40] [PASSED] oob_was/16026007364
[16:39:40] [PASSED] oob_was/14020316580
[16:39:40] [PASSED] oob_was/14025883347
[16:39:40] [PASSED] oob_was/16029380221
[16:39:40] ============== [PASSED] xe_rtp_table_oob_test ==============
[16:39:40] ================ xe_rtp_table_dev_oob_test  ================
[16:39:40] [PASSED] device_oob_was/22010954014
[16:39:40] [PASSED] device_oob_was/15015404425
[16:39:40] [PASSED] device_oob_was/22019338487_display
[16:39:40] [PASSED] device_oob_was/14022085890
[16:39:40] [PASSED] device_oob_was/14026539277
[16:39:40] [PASSED] device_oob_was/14026633728
[16:39:40] [PASSED] device_oob_was/14026746987
[16:39:40] [PASSED] device_oob_was/14026779378
[16:39:40] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[16:39:40] ========== xe_rtp_table_missing_upper_bound_test  ==========
[16:39:40] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[16:39:40] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[16:39:40] [PASSED] register_whitelist/1806527549
[16:39:40] [PASSED] register_whitelist/allow_read_ctx_timestamp
[16:39:40] [PASSED] register_whitelist/allow_read_queue_timestamp
[16:39:40] [PASSED] register_whitelist/16014440446
[16:39:40] [PASSED] register_whitelist/16017236439
[16:39:40] [PASSED] register_whitelist/16020183090
[16:39:40] [PASSED] register_whitelist/14024997852
[16:39:40] [PASSED] register_whitelist/14024997852
[16:39:40] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[16:39:40] =============== [PASSED] xe_rtp_tables_test ================
[16:39:40] =================== xe_rtp (3 subtests) ====================
[16:39:40] =================== xe_rtp_rules_tests  ====================
[16:39:40] [PASSED] no
[16:39:40] [PASSED] yes
[16:39:40] [PASSED] no-and-no
[16:39:40] [PASSED] no-and-yes
[16:39:40] [PASSED] yes-and-no
[16:39:40] [PASSED] yes-and-yes
[16:39:40] [PASSED] no-or-no
[16:39:40] [PASSED] no-or-yes
[16:39:40] [PASSED] yes-or-no
[16:39:40] [PASSED] yes-or-yes
[16:39:40] [PASSED] no-yes-or-yes-no
[16:39:40] [PASSED] no-yes-or-yes-yes
[16:39:40] [PASSED] yes-yes-or-no-yes
[16:39:40] [PASSED] yes-yes-or-yes-yes
[16:39:40] [PASSED] no-no-or-yes-or-no
[16:39:40] [PASSED] or
[16:39:40] [PASSED] or-yes
[16:39:40] [PASSED] or-no
[16:39:40] [PASSED] yes-or
[16:39:40] [PASSED] no-or
[16:39:40] [PASSED] no-or-or-yes
[16:39:40] [PASSED] yes-or-or-no
[16:39:40] [PASSED] no-or-or-no
[16:39:40] [PASSED] missing-context-engine-class
[16:39:40] [PASSED] missing-context-engine-class-or-yes
[16:39:40] [PASSED] missing-context-engine-class-or-or-yes
[16:39:40] =============== [PASSED] xe_rtp_rules_tests ================
[16:39:40] =============== xe_rtp_process_to_sr_tests  ================
[16:39:40] [PASSED] coalesce-same-reg
[16:39:40] [PASSED] coalesce-same-reg-literal-and-func
[16:39:40] [PASSED] no-match-no-add
[16:39:40] [PASSED] two-regs-two-entries
[16:39:40] [PASSED] clr-one-set-other
[16:39:40] [PASSED] set-field
[16:39:40] [PASSED] conflict-duplicate
[16:39:40] [PASSED] conflict-not-disjoint
[16:39:40] [PASSED] conflict-not-disjoint-literal-and-func
[16:39:40] [PASSED] conflict-reg-type
[16:39:40] [PASSED] bad-mcr-reg-forced-to-regular
[16:39:40] [PASSED] bad-regular-reg-forced-to-mcr
[16:39:40] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:39:40] ================== xe_rtp_process_tests  ===================
[16:39:40] [PASSED] active1
[16:39:40] [PASSED] active2
[16:39:40] [PASSED] active-inactive
[16:39:40] [PASSED] inactive-active
[16:39:40] [PASSED] inactive-active-inactive
[16:39:40] [PASSED] inactive-inactive-inactive
[16:39:40] ============== [PASSED] xe_rtp_process_tests ===============
[16:39:40] ===================== [PASSED] xe_rtp ======================
[16:39:40] ==================== xe_wa (1 subtest) =====================
[16:39:40] ======================== xe_wa_gt  =========================
[16:39:40] [PASSED] TIGERLAKE B0
[16:39:40] [PASSED] DG1 A0
[16:39:40] [PASSED] DG1 B0
[16:39:40] [PASSED] ALDERLAKE_S A0
[16:39:40] [PASSED] ALDERLAKE_S B0
[16:39:40] [PASSED] ALDERLAKE_S C0
[16:39:40] [PASSED] ALDERLAKE_S D0
[16:39:40] [PASSED] ALDERLAKE_P A0
[16:39:40] [PASSED] ALDERLAKE_P B0
[16:39:40] [PASSED] ALDERLAKE_P C0
[16:39:40] [PASSED] ALDERLAKE_S RPLS D0
[16:39:40] [PASSED] ALDERLAKE_P RPLU E0
[16:39:40] [PASSED] DG2 G10 C0
[16:39:40] [PASSED] DG2 G11 B1
[16:39:40] [PASSED] DG2 G12 A1
[16:39:40] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:39:40] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[16:39:40] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[16:39:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[16:39:40] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[16:39:40] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[16:39:40] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[16:39:40] ==================== [PASSED] xe_wa_gt =====================
[16:39:40] ====================== [PASSED] xe_wa ======================
[16:39:40] ============================================================
[16:39:40] Testing complete. Ran 729 tests: passed: 711, skipped: 18
[16:39:40] Elapsed time: 36.809s total, 4.450s configuring, 31.693s building, 0.652s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:39:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:39:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:40:06] Starting KUnit Kernel (1/1)...
[16:40:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:40:06] ============ drm_test_pick_cmdline (2 subtests) ============
[16:40:06] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[16:40:06] =============== drm_test_pick_cmdline_named  ===============
[16:40:06] [PASSED] NTSC
[16:40:06] [PASSED] NTSC-J
[16:40:06] [PASSED] PAL
[16:40:06] [PASSED] PAL-M
[16:40:06] =========== [PASSED] drm_test_pick_cmdline_named ===========
[16:40:06] ============== [PASSED] drm_test_pick_cmdline ==============
[16:40:06] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:40:06] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:40:06] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:40:06] =========== drm_validate_clone_mode (2 subtests) ===========
[16:40:06] ============== drm_test_check_in_clone_mode  ===============
[16:40:06] [PASSED] in_clone_mode
[16:40:06] [PASSED] not_in_clone_mode
[16:40:06] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:40:06] =============== drm_test_check_valid_clones  ===============
[16:40:06] [PASSED] not_in_clone_mode
[16:40:06] [PASSED] valid_clone
[16:40:06] [PASSED] invalid_clone
[16:40:06] =========== [PASSED] drm_test_check_valid_clones ===========
[16:40:06] ============= [PASSED] drm_validate_clone_mode =============
[16:40:06] ============= drm_validate_modeset (1 subtest) =============
[16:40:06] [PASSED] drm_test_check_connector_changed_modeset
[16:40:06] ============== [PASSED] drm_validate_modeset ===============
[16:40:06] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:40:06] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:40:06] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:40:06] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:40:06] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[16:40:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:40:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:40:06] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:40:06] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[16:40:06] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:40:06] ============== drm_bridge_alloc (2 subtests) ===============
[16:40:06] [PASSED] drm_test_drm_bridge_alloc_basic
[16:40:06] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:40:06] ================ [PASSED] drm_bridge_alloc =================
[16:40:06] ============= drm_bridge_bus_fmt (5 subtests) ==============
[16:40:06] [PASSED] drm_test_bridge_rgb_yuv_rgb
[16:40:06] [PASSED] drm_test_bridge_must_convert_to_yuv444
[16:40:06] [PASSED] drm_test_bridge_hdmi_auto_rgb
[16:40:06] [PASSED] drm_test_bridge_auto_first
[16:40:06] [PASSED] drm_test_bridge_rgb_yuv_no_path
[16:40:06] =============== [PASSED] drm_bridge_bus_fmt ================
[16:40:06] ============= drm_cmdline_parser (40 subtests) =============
[16:40:06] [PASSED] drm_test_cmdline_force_d_only
[16:40:06] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:40:06] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:40:06] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:40:06] [PASSED] drm_test_cmdline_force_e_only
[16:40:06] [PASSED] drm_test_cmdline_res
[16:40:06] [PASSED] drm_test_cmdline_res_vesa
[16:40:06] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:40:06] [PASSED] drm_test_cmdline_res_rblank
[16:40:06] [PASSED] drm_test_cmdline_res_bpp
[16:40:06] [PASSED] drm_test_cmdline_res_refresh
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:40:06] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:40:06] [PASSED] drm_test_cmdline_res_margins_force_on
[16:40:06] [PASSED] drm_test_cmdline_res_vesa_margins
[16:40:06] [PASSED] drm_test_cmdline_name
[16:40:06] [PASSED] drm_test_cmdline_name_bpp
[16:40:06] [PASSED] drm_test_cmdline_name_option
[16:40:06] [PASSED] drm_test_cmdline_name_bpp_option
[16:40:06] [PASSED] drm_test_cmdline_rotate_0
[16:40:06] [PASSED] drm_test_cmdline_rotate_90
[16:40:06] [PASSED] drm_test_cmdline_rotate_180
[16:40:06] [PASSED] drm_test_cmdline_rotate_270
[16:40:06] [PASSED] drm_test_cmdline_hmirror
[16:40:06] [PASSED] drm_test_cmdline_vmirror
[16:40:06] [PASSED] drm_test_cmdline_margin_options
[16:40:06] [PASSED] drm_test_cmdline_multiple_options
[16:40:06] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:40:06] [PASSED] drm_test_cmdline_extra_and_option
[16:40:06] [PASSED] drm_test_cmdline_freestanding_options
[16:40:06] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:40:06] [PASSED] drm_test_cmdline_panel_orientation
[16:40:06] ================ drm_test_cmdline_invalid  =================
[16:40:06] [PASSED] margin_only
[16:40:06] [PASSED] interlace_only
[16:40:06] [PASSED] res_missing_x
[16:40:06] [PASSED] res_missing_y
[16:40:06] [PASSED] res_bad_y
[16:40:06] [PASSED] res_missing_y_bpp
[16:40:06] [PASSED] res_bad_bpp
[16:40:06] [PASSED] res_bad_refresh
[16:40:06] [PASSED] res_bpp_refresh_force_on_off
[16:40:06] [PASSED] res_invalid_mode
[16:40:06] [PASSED] res_bpp_wrong_place_mode
[16:40:06] [PASSED] name_bpp_refresh
[16:40:06] [PASSED] name_refresh
[16:40:06] [PASSED] name_refresh_wrong_mode
[16:40:06] [PASSED] name_refresh_invalid_mode
[16:40:06] [PASSED] rotate_multiple
[16:40:06] [PASSED] rotate_invalid_val
[16:40:06] [PASSED] rotate_truncated
[16:40:06] [PASSED] invalid_option
[16:40:06] [PASSED] invalid_tv_option
[16:40:06] [PASSED] truncated_tv_option
[16:40:06] ============ [PASSED] drm_test_cmdline_invalid =============
[16:40:06] =============== drm_test_cmdline_tv_options  ===============
[16:40:06] [PASSED] NTSC
[16:40:06] [PASSED] NTSC_443
[16:40:06] [PASSED] NTSC_J
[16:40:06] [PASSED] PAL
[16:40:06] [PASSED] PAL_M
[16:40:06] [PASSED] PAL_N
[16:40:06] [PASSED] SECAM
[16:40:06] [PASSED] MONO_525
[16:40:06] [PASSED] MONO_625
[16:40:06] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:40:06] =============== [PASSED] drm_cmdline_parser ================
[16:40:06] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:40:06] [PASSED] drm_test_connector_hdmi_init_valid
[16:40:06] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:40:06] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:40:06] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:40:06] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:40:06] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:40:06] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:40:06] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:40:06] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:40:06] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:40:06] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:40:06] [PASSED] supported_formats=0x5 yuv420_allowed=1
[16:40:06] [PASSED] supported_formats=0x5 yuv420_allowed=0
[16:40:06] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:40:06] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:40:06] [PASSED] drm_test_connector_hdmi_init_null_product
[16:40:06] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:40:06] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:40:06] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:40:06] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:40:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:40:06] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:40:06] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:40:06] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:40:06] [PASSED] HDMI-A
[16:40:06] [PASSED] HDMI-B
[16:40:06] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:40:06] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:40:06] [PASSED] Unknown
[16:40:06] [PASSED] VGA
[16:40:06] [PASSED] DVI-I
[16:40:06] [PASSED] DVI-D
[16:40:06] [PASSED] DVI-A
[16:40:06] [PASSED] Composite
[16:40:06] [PASSED] SVIDEO
[16:40:06] [PASSED] LVDS
[16:40:06] [PASSED] Component
[16:40:06] [PASSED] DIN
[16:40:06] [PASSED] DP
[16:40:06] [PASSED] TV
[16:40:06] [PASSED] eDP
[16:40:06] [PASSED] Virtual
[16:40:06] [PASSED] DSI
[16:40:06] [PASSED] DPI
[16:40:06] [PASSED] Writeback
[16:40:06] [PASSED] SPI
[16:40:06] [PASSED] USB
[16:40:06] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:40:06] ============ [PASSED] drmm_connector_hdmi_init =============
[16:40:06] ============= drmm_connector_init (3 subtests) =============
[16:40:06] [PASSED] drm_test_drmm_connector_init
[16:40:06] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:40:06] ========= drm_test_drmm_connector_init_type_valid  =========
[16:40:06] [PASSED] Unknown
[16:40:06] [PASSED] VGA
[16:40:06] [PASSED] DVI-I
[16:40:06] [PASSED] DVI-D
[16:40:06] [PASSED] DVI-A
[16:40:06] [PASSED] Composite
[16:40:06] [PASSED] SVIDEO
[16:40:06] [PASSED] LVDS
[16:40:06] [PASSED] Component
[16:40:06] [PASSED] DIN
[16:40:06] [PASSED] DP
[16:40:06] [PASSED] HDMI-A
[16:40:06] [PASSED] HDMI-B
[16:40:06] [PASSED] TV
[16:40:06] [PASSED] eDP
[16:40:06] [PASSED] Virtual
[16:40:06] [PASSED] DSI
[16:40:06] [PASSED] DPI
[16:40:06] [PASSED] Writeback
[16:40:06] [PASSED] SPI
[16:40:06] [PASSED] USB
[16:40:06] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:40:06] =============== [PASSED] drmm_connector_init ===============
[16:40:06] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_init
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:40:06] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:40:06] [PASSED] Unknown
[16:40:06] [PASSED] VGA
[16:40:06] [PASSED] DVI-I
[16:40:06] [PASSED] DVI-D
[16:40:06] [PASSED] DVI-A
[16:40:06] [PASSED] Composite
[16:40:06] [PASSED] SVIDEO
[16:40:06] [PASSED] LVDS
[16:40:06] [PASSED] Component
[16:40:06] [PASSED] DIN
[16:40:06] [PASSED] DP
[16:40:06] [PASSED] HDMI-A
[16:40:06] [PASSED] HDMI-B
[16:40:06] [PASSED] TV
[16:40:06] [PASSED] eDP
[16:40:06] [PASSED] Virtual
[16:40:06] [PASSED] DSI
[16:40:06] [PASSED] DPI
[16:40:06] [PASSED] Writeback
[16:40:06] [PASSED] SPI
[16:40:06] [PASSED] USB
[16:40:06] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:40:06] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:40:06] [PASSED] Unknown
[16:40:06] [PASSED] VGA
[16:40:06] [PASSED] DVI-I
[16:40:06] [PASSED] DVI-D
[16:40:06] [PASSED] DVI-A
[16:40:06] [PASSED] Composite
[16:40:06] [PASSED] SVIDEO
[16:40:06] [PASSED] LVDS
[16:40:06] [PASSED] Component
[16:40:06] [PASSED] DIN
[16:40:06] [PASSED] DP
[16:40:06] [PASSED] HDMI-A
[16:40:06] [PASSED] HDMI-B
[16:40:06] [PASSED] TV
[16:40:06] [PASSED] eDP
[16:40:06] [PASSED] Virtual
[16:40:06] [PASSED] DSI
[16:40:06] [PASSED] DPI
[16:40:06] [PASSED] Writeback
[16:40:06] [PASSED] SPI
[16:40:06] [PASSED] USB
[16:40:06] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:40:06] =========== [PASSED] drm_connector_dynamic_init ============
[16:40:06] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:40:06] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:40:06] ======= drm_connector_dynamic_register (7 subtests) ========
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:40:06] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:40:06] ========= [PASSED] drm_connector_dynamic_register ==========
[16:40:06] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:40:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:40:06] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:40:06] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:40:06] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:40:06] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:40:06] [PASSED] NTSC
[16:40:06] [PASSED] NTSC-443
[16:40:06] [PASSED] NTSC-J
[16:40:06] [PASSED] PAL
[16:40:06] [PASSED] PAL-M
[16:40:06] [PASSED] PAL-N
[16:40:06] [PASSED] SECAM
[16:40:06] [PASSED] Mono
[16:40:06] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:40:06] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:40:06] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:40:06] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:40:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:40:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:40:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:40:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:40:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:40:06] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:40:06] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:40:06] [PASSED] VIC 96
[16:40:06] [PASSED] VIC 97
[16:40:06] [PASSED] VIC 101
[16:40:06] [PASSED] VIC 102
[16:40:06] [PASSED] VIC 106
[16:40:06] [PASSED] VIC 107
[16:40:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:40:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:40:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:40:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:40:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:40:06] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:40:06] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:40:06] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:40:06] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:40:06] [PASSED] Automatic
[16:40:06] [PASSED] Full
[16:40:06] [PASSED] Limited 16:235
[16:40:06] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:40:06] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:40:06] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:40:06] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:40:06] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:40:06] [PASSED] RGB
[16:40:06] [PASSED] YUV 4:2:0
[16:40:06] [PASSED] YUV 4:2:2
[16:40:06] [PASSED] YUV 4:4:4
[16:40:06] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:40:06] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:40:06] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:40:06] ============= drm_damage_helper (21 subtests) ==============
[16:40:06] [PASSED] drm_test_damage_iter_no_damage
[16:40:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:40:06] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:40:06] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:40:06] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:40:06] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:40:06] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:40:06] [PASSED] drm_test_damage_iter_simple_damage
[16:40:06] [PASSED] drm_test_damage_iter_single_damage
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:40:06] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:40:06] [PASSED] drm_test_damage_iter_damage
[16:40:06] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:40:06] [PASSED] drm_test_damage_iter_damage_one_outside
[16:40:06] [PASSED] drm_test_damage_iter_damage_src_moved
[16:40:06] [PASSED] drm_test_damage_iter_damage_not_visible
[16:40:06] ================ [PASSED] drm_damage_helper ================
[16:40:06] ============== drm_dp_mst_helper (3 subtests) ==============
[16:40:06] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:40:06] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:40:06] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:40:06] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:40:06] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:40:06] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:40:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:40:06] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:40:06] [PASSED] Link rate 2000000 lane count 4
[16:40:06] [PASSED] Link rate 2000000 lane count 2
[16:40:06] [PASSED] Link rate 2000000 lane count 1
[16:40:06] [PASSED] Link rate 1350000 lane count 4
[16:40:06] [PASSED] Link rate 1350000 lane count 2
[16:40:06] [PASSED] Link rate 1350000 lane count 1
[16:40:06] [PASSED] Link rate 1000000 lane count 4
[16:40:06] [PASSED] Link rate 1000000 lane count 2
[16:40:06] [PASSED] Link rate 1000000 lane count 1
[16:40:06] [PASSED] Link rate 810000 lane count 4
[16:40:06] [PASSED] Link rate 810000 lane count 2
[16:40:06] [PASSED] Link rate 810000 lane count 1
[16:40:06] [PASSED] Link rate 540000 lane count 4
[16:40:06] [PASSED] Link rate 540000 lane count 2
[16:40:06] [PASSED] Link rate 540000 lane count 1
[16:40:06] [PASSED] Link rate 270000 lane count 4
[16:40:06] [PASSED] Link rate 270000 lane count 2
[16:40:06] [PASSED] Link rate 270000 lane count 1
[16:40:06] [PASSED] Link rate 162000 lane count 4
[16:40:06] [PASSED] Link rate 162000 lane count 2
[16:40:06] [PASSED] Link rate 162000 lane count 1
[16:40:06] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:40:06] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:40:06] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:40:06] [PASSED] DP_POWER_UP_PHY with port number
[16:40:06] [PASSED] DP_POWER_DOWN_PHY with port number
[16:40:06] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:40:06] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:40:06] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:40:06] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:40:06] [PASSED] DP_QUERY_PAYLOAD with port number
[16:40:06] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:40:06] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:40:06] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:40:06] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:40:06] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:40:06] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:40:06] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:40:06] [PASSED] DP_REMOTE_I2C_READ with port number
[16:40:06] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:40:06] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:40:06] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:40:06] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:40:06] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:40:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:40:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:40:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:40:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:40:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:40:06] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:40:06] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:40:06] ================ [PASSED] drm_dp_mst_helper ================
[16:40:06] ================== drm_exec (7 subtests) ===================
[16:40:06] [PASSED] sanitycheck
[16:40:06] [PASSED] test_lock
[16:40:06] [PASSED] test_lock_unlock
[16:40:06] [PASSED] test_duplicates
[16:40:06] [PASSED] test_prepare
[16:40:06] [PASSED] test_prepare_array
[16:40:06] [PASSED] test_multiple_loops
[16:40:06] ==================== [PASSED] drm_exec =====================
[16:40:06] =========== drm_format_helper_test (17 subtests) ===========
[16:40:06] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:40:06] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:40:06] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:40:06] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:40:06] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:40:06] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:40:06] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:40:06] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:40:06] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:40:06] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:40:06] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:40:06] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:40:06] ==================== drm_test_fb_swab  =====================
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ================ [PASSED] drm_test_fb_swab =================
[16:40:06] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:40:06] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:40:06] [PASSED] single_pixel_source_buffer
[16:40:06] [PASSED] single_pixel_clip_rectangle
[16:40:06] [PASSED] well_known_colors
[16:40:06] [PASSED] destination_pitch
[16:40:06] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:40:06] ================= drm_test_fb_clip_offset  =================
[16:40:06] [PASSED] pass through
[16:40:06] [PASSED] horizontal offset
[16:40:06] [PASSED] vertical offset
[16:40:06] [PASSED] horizontal and vertical offset
[16:40:06] [PASSED] horizontal offset (custom pitch)
[16:40:06] [PASSED] vertical offset (custom pitch)
[16:40:06] [PASSED] horizontal and vertical offset (custom pitch)
[16:40:06] ============= [PASSED] drm_test_fb_clip_offset =============
[16:40:06] =================== drm_test_fb_memcpy  ====================
[16:40:06] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:40:06] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:40:06] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:40:06] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:40:06] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:40:06] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:40:06] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:40:06] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:40:06] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:40:06] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:40:06] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:40:06] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:40:06] =============== [PASSED] drm_test_fb_memcpy ================
[16:40:06] ============= [PASSED] drm_format_helper_test ==============
[16:40:06] ================= drm_format (18 subtests) =================
[16:40:06] [PASSED] drm_test_format_block_width_invalid
[16:40:06] [PASSED] drm_test_format_block_width_one_plane
[16:40:06] [PASSED] drm_test_format_block_width_two_plane
[16:40:06] [PASSED] drm_test_format_block_width_three_plane
[16:40:06] [PASSED] drm_test_format_block_width_tiled
[16:40:06] [PASSED] drm_test_format_block_height_invalid
[16:40:06] [PASSED] drm_test_format_block_height_one_plane
[16:40:06] [PASSED] drm_test_format_block_height_two_plane
[16:40:06] [PASSED] drm_test_format_block_height_three_plane
[16:40:06] [PASSED] drm_test_format_block_height_tiled
[16:40:06] [PASSED] drm_test_format_min_pitch_invalid
[16:40:06] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:40:06] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:40:06] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:40:06] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:40:06] [PASSED] drm_test_format_min_pitch_two_plane
[16:40:06] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:40:06] [PASSED] drm_test_format_min_pitch_tiled
[16:40:06] =================== [PASSED] drm_format ====================
[16:40:06] ============== drm_framebuffer (10 subtests) ===============
[16:40:06] ========== drm_test_framebuffer_check_src_coords  ==========
[16:40:06] [PASSED] Success: source fits into fb
[16:40:06] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:40:06] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:40:06] [PASSED] Fail: overflowing fb with source width
[16:40:06] [PASSED] Fail: overflowing fb with source height
[16:40:06] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:40:06] [PASSED] drm_test_framebuffer_cleanup
[16:40:06] =============== drm_test_framebuffer_create  ===============
[16:40:06] [PASSED] ABGR8888 normal sizes
[16:40:06] [PASSED] ABGR8888 max sizes
[16:40:06] [PASSED] ABGR8888 pitch greater than min required
[16:40:06] [PASSED] ABGR8888 pitch less than min required
[16:40:06] [PASSED] ABGR8888 Invalid width
[16:40:06] [PASSED] ABGR8888 Invalid buffer handle
[16:40:06] [PASSED] No pixel format
[16:40:06] [PASSED] ABGR8888 Width 0
[16:40:06] [PASSED] ABGR8888 Height 0
[16:40:06] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:40:06] [PASSED] ABGR8888 Large buffer offset
[16:40:06] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:40:06] [PASSED] ABGR8888 Invalid flag
[16:40:06] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:40:06] [PASSED] ABGR8888 Valid buffer modifier
[16:40:06] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:40:06] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] NV12 Normal sizes
[16:40:06] [PASSED] NV12 Max sizes
[16:40:06] [PASSED] NV12 Invalid pitch
[16:40:06] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:40:06] [PASSED] NV12 different  modifier per-plane
[16:40:06] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:40:06] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] NV12 Modifier for inexistent plane
[16:40:06] [PASSED] NV12 Handle for inexistent plane
[16:40:06] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:40:06] [PASSED] YVU420 Normal sizes
[16:40:06] [PASSED] YVU420 Max sizes
[16:40:06] [PASSED] YVU420 Invalid pitch
[16:40:06] [PASSED] YVU420 Different pitches
[16:40:06] [PASSED] YVU420 Different buffer offsets/pitches
[16:40:06] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:40:06] [PASSED] YVU420 Valid modifier
[16:40:06] [PASSED] YVU420 Different modifiers per plane
[16:40:06] [PASSED] YVU420 Modifier for inexistent plane
[16:40:06] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:40:06] [PASSED] X0L2 Normal sizes
[16:40:06] [PASSED] X0L2 Max sizes
[16:40:06] [PASSED] X0L2 Invalid pitch
[16:40:06] [PASSED] X0L2 Pitch greater than minimum required
[16:40:06] [PASSED] X0L2 Handle for inexistent plane
[16:40:06] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:40:06] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:40:06] [PASSED] X0L2 Valid modifier
[16:40:06] [PASSED] X0L2 Modifier for inexistent plane
[16:40:06] =========== [PASSED] drm_test_framebuffer_create ===========
[16:40:06] [PASSED] drm_test_framebuffer_free
[16:40:06] [PASSED] drm_test_framebuffer_init
[16:40:06] [PASSED] drm_test_framebuffer_init_bad_format
[16:40:06] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:40:06] [PASSED] drm_test_framebuffer_lookup
[16:40:06] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:40:06] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:40:06] ================= [PASSED] drm_framebuffer =================
[16:40:06] ================ drm_gem_shmem (8 subtests) ================
[16:40:06] [PASSED] drm_gem_shmem_test_obj_create
[16:40:06] [PASSED] drm_gem_shmem_test_obj_create_private
[16:40:06] [PASSED] drm_gem_shmem_test_pin_pages
[16:40:06] [PASSED] drm_gem_shmem_test_vmap
[16:40:06] [PASSED] drm_gem_shmem_test_get_sg_table
[16:40:06] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:40:06] [PASSED] drm_gem_shmem_test_madvise
[16:40:06] [PASSED] drm_gem_shmem_test_purge
[16:40:06] ================== [PASSED] drm_gem_shmem ==================
[16:40:06] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:40:06] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:40:06] [PASSED] Automatic
[16:40:06] [PASSED] Full
[16:40:06] [PASSED] Limited 16:235
[16:40:06] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:40:06] [PASSED] drm_test_check_disable_connector
[16:40:06] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:40:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:40:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:40:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:40:06] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:40:06] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:40:06] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:40:06] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:40:06] [PASSED] drm_test_check_output_bpc_dvi
[16:40:06] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:40:06] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:40:06] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:40:06] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:40:06] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:40:06] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:40:06] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:40:06] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:40:06] ============ drm_test_check_hdmi_color_format  =============
[16:40:06] [PASSED] AUTO -> RGB
[16:40:06] [PASSED] YCBCR422 -> YUV422
[16:40:06] [PASSED] YCBCR420 -> YUV420
[16:40:06] [PASSED] YCBCR444 -> YUV444
[16:40:06] [PASSED] RGB -> RGB
[16:40:06] ======== [PASSED] drm_test_check_hdmi_color_format =========
[16:40:06] ======== drm_test_check_hdmi_color_format_420_only  ========
[16:40:06] [PASSED] RGB should fail
[16:40:06] [PASSED] YUV444 should fail
[16:40:06] [PASSED] YUV422 should fail
[16:40:06] [PASSED] YUV420 should work
[16:40:06] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[16:40:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:40:06] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:40:06] [PASSED] drm_test_check_broadcast_rgb_value
[16:40:06] [PASSED] drm_test_check_bpc_8_value
[16:40:06] [PASSED] drm_test_check_bpc_10_value
[16:40:06] [PASSED] drm_test_check_bpc_12_value
[16:40:06] [PASSED] drm_test_check_format_value
[16:40:06] [PASSED] drm_test_check_tmds_char_value
[16:40:06] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:40:06] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[16:40:06] [PASSED] drm_test_check_mode_valid
[16:40:06] [PASSED] drm_test_check_mode_valid_reject
[16:40:06] [PASSED] drm_test_check_mode_valid_reject_rate
[16:40:06] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:40:06] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[16:40:06] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[16:40:06] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[16:40:06] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:40:06] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[16:40:06] [PASSED] drm_test_check_infoframes
[16:40:06] [PASSED] drm_test_check_reject_avi_infoframe
[16:40:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[16:40:06] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[16:40:06] [PASSED] drm_test_check_reject_audio_infoframe
[16:40:06] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[16:40:06] ================= drm_managed (2 subtests) =================
[16:40:06] [PASSED] drm_test_managed_release_action
[16:40:06] [PASSED] drm_test_managed_run_action
[16:40:06] =================== [PASSED] drm_managed ===================
[16:40:06] =================== drm_mm (6 subtests) ====================
[16:40:06] [PASSED] drm_test_mm_init
[16:40:06] [PASSED] drm_test_mm_debug
[16:40:06] [PASSED] drm_test_mm_align32
[16:40:06] [PASSED] drm_test_mm_align64
[16:40:06] [PASSED] drm_test_mm_lowest
[16:40:06] [PASSED] drm_test_mm_highest
[16:40:06] ===================== [PASSED] drm_mm ======================
[16:40:06] ============= drm_modes_analog_tv (5 subtests) =============
[16:40:06] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:40:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:40:06] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:40:06] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:40:06] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:40:06] =============== [PASSED] drm_modes_analog_tv ===============
[16:40:06] ============== drm_plane_helper (2 subtests) ===============
[16:40:06] =============== drm_test_check_plane_state  ================
[16:40:06] [PASSED] clipping_simple
[16:40:06] [PASSED] clipping_rotate_reflect
[16:40:06] [PASSED] positioning_simple
[16:40:06] [PASSED] upscaling
[16:40:06] [PASSED] downscaling
[16:40:06] [PASSED] rounding1
[16:40:06] [PASSED] rounding2
[16:40:06] [PASSED] rounding3
[16:40:06] [PASSED] rounding4
[16:40:06] =========== [PASSED] drm_test_check_plane_state ============
[16:40:06] =========== drm_test_check_invalid_plane_state  ============
[16:40:06] [PASSED] positioning_invalid
[16:40:06] [PASSED] upscaling_invalid
[16:40:06] [PASSED] downscaling_invalid
[16:40:06] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:40:06] ================ [PASSED] drm_plane_helper =================
[16:40:06] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:40:06] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:40:06] [PASSED] None
[16:40:06] [PASSED] PAL
[16:40:06] [PASSED] NTSC
[16:40:06] [PASSED] Both, NTSC Default
[16:40:06] [PASSED] Both, PAL Default
[16:40:06] [PASSED] Both, NTSC Default, with PAL on command-line
[16:40:06] [PASSED] Both, PAL Default, with NTSC on command-line
[16:40:06] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:40:06] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:40:06] ================== drm_rect (9 subtests) ===================
[16:40:06] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:40:06] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:40:06] [PASSED] drm_test_rect_clip_scaled_clipped
[16:40:06] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:40:06] ================= drm_test_rect_intersect  =================
[16:40:06] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:40:06] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:40:06] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:40:06] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:40:06] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:40:06] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:40:06] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:40:06] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:40:06] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:40:06] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:40:06] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:40:06] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:40:06] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:40:06] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:40:06] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:40:06] ============= [PASSED] drm_test_rect_intersect =============
[16:40:06] ================ drm_test_rect_calc_hscale  ================
[16:40:06] [PASSED] normal use
[16:40:06] [PASSED] out of max range
[16:40:06] [PASSED] out of min range
[16:40:06] [PASSED] zero dst
[16:40:06] [PASSED] negative src
[16:40:06] [PASSED] negative dst
[16:40:06] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:40:06] ================ drm_test_rect_calc_vscale  ================
[16:40:06] [PASSED] normal use
[16:40:06] [PASSED] out of max range
[16:40:06] [PASSED] out of min range
[16:40:06] [PASSED] zero dst
[16:40:06] [PASSED] negative src
[16:40:06] [PASSED] negative dst
[16:40:06] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:40:06] ================== drm_test_rect_rotate  ===================
[16:40:06] [PASSED] reflect-x
[16:40:06] [PASSED] reflect-y
[16:40:06] [PASSED] rotate-0
[16:40:06] [PASSED] rotate-90
[16:40:06] [PASSED] rotate-180
[16:40:06] [PASSED] rotate-270
[16:40:06] ============== [PASSED] drm_test_rect_rotate ===============
[16:40:06] ================ drm_test_rect_rotate_inv  =================
[16:40:06] [PASSED] reflect-x
[16:40:06] [PASSED] reflect-y
[16:40:06] [PASSED] rotate-0
[16:40:06] [PASSED] rotate-90
[16:40:06] [PASSED] rotate-180
[16:40:06] [PASSED] rotate-270
[16:40:06] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:40:06] ==================== [PASSED] drm_rect =====================
[16:40:06] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:40:06] ============ drm_test_sysfb_build_fourcc_list  =============
[16:40:06] [PASSED] no native formats
[16:40:06] [PASSED] XRGB8888 as native format
[16:40:06] [PASSED] remove duplicates
[16:40:06] [PASSED] convert alpha formats
[16:40:06] [PASSED] random formats
[16:40:06] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:40:06] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:40:06] ================== drm_fixp (2 subtests) ===================
[16:40:06] [PASSED] drm_test_int2fixp
[16:40:06] [PASSED] drm_test_sm2fixp
[16:40:06] ==================== [PASSED] drm_fixp =====================
[16:40:06] ============================================================
[16:40:06] Testing complete. Ran 639 tests: passed: 639
[16:40:06] Elapsed time: 26.553s total, 1.782s configuring, 24.604s building, 0.154s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:40:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:40:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:40:18] Starting KUnit Kernel (1/1)...
[16:40:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:40:18] ================= ttm_device (5 subtests) ==================
[16:40:18] [PASSED] ttm_device_init_basic
[16:40:18] [PASSED] ttm_device_init_multiple
[16:40:18] [PASSED] ttm_device_fini_basic
[16:40:18] [PASSED] ttm_device_init_no_vma_man
[16:40:18] ================== ttm_device_init_pools  ==================
[16:40:18] [PASSED] No DMA allocations, no DMA32 required
[16:40:18] [PASSED] DMA allocations, DMA32 required
[16:40:18] [PASSED] No DMA allocations, DMA32 required
[16:40:18] [PASSED] DMA allocations, no DMA32 required
[16:40:18] ============== [PASSED] ttm_device_init_pools ==============
[16:40:18] =================== [PASSED] ttm_device ====================
[16:40:18] ================== ttm_pool (8 subtests) ===================
[16:40:18] ================== ttm_pool_alloc_basic  ===================
[16:40:18] [PASSED] One page
[16:40:18] [PASSED] More than one page
[16:40:18] [PASSED] Above the allocation limit
[16:40:18] [PASSED] One page, with coherent DMA mappings enabled
[16:40:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:40:18] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:40:18] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:40:18] [PASSED] One page
[16:40:18] [PASSED] More than one page
[16:40:18] [PASSED] Above the allocation limit
[16:40:18] [PASSED] One page, with coherent DMA mappings enabled
[16:40:18] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:40:18] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:40:18] [PASSED] ttm_pool_alloc_order_caching_match
[16:40:18] [PASSED] ttm_pool_alloc_caching_mismatch
[16:40:18] [PASSED] ttm_pool_alloc_order_mismatch
[16:40:18] [PASSED] ttm_pool_free_dma_alloc
[16:40:18] [PASSED] ttm_pool_free_no_dma_alloc
[16:40:18] [PASSED] ttm_pool_fini_basic
[16:40:18] ==================== [PASSED] ttm_pool =====================
[16:40:18] ================ ttm_resource (8 subtests) =================
[16:40:18] ================= ttm_resource_init_basic  =================
[16:40:18] [PASSED] Init resource in TTM_PL_SYSTEM
[16:40:18] [PASSED] Init resource in TTM_PL_VRAM
[16:40:18] [PASSED] Init resource in a private placement
[16:40:18] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:40:18] ============= [PASSED] ttm_resource_init_basic =============
[16:40:18] [PASSED] ttm_resource_init_pinned
[16:40:18] [PASSED] ttm_resource_fini_basic
[16:40:18] [PASSED] ttm_resource_manager_init_basic
[16:40:18] [PASSED] ttm_resource_manager_usage_basic
[16:40:18] [PASSED] ttm_resource_manager_set_used_basic
[16:40:18] [PASSED] ttm_sys_man_alloc_basic
[16:40:18] [PASSED] ttm_sys_man_free_basic
[16:40:18] ================== [PASSED] ttm_resource ===================
[16:40:18] =================== ttm_tt (15 subtests) ===================
[16:40:18] ==================== ttm_tt_init_basic  ====================
[16:40:18] [PASSED] Page-aligned size
[16:40:18] [PASSED] Extra pages requested
[16:40:18] ================ [PASSED] ttm_tt_init_basic ================
[16:40:18] [PASSED] ttm_tt_init_misaligned
[16:40:18] [PASSED] ttm_tt_fini_basic
[16:40:18] [PASSED] ttm_tt_fini_sg
[16:40:18] [PASSED] ttm_tt_fini_shmem
[16:40:18] [PASSED] ttm_tt_create_basic
[16:40:18] [PASSED] ttm_tt_create_invalid_bo_type
[16:40:18] [PASSED] ttm_tt_create_ttm_exists
[16:40:18] [PASSED] ttm_tt_create_failed
[16:40:18] [PASSED] ttm_tt_destroy_basic
[16:40:18] [PASSED] ttm_tt_populate_null_ttm
[16:40:18] [PASSED] ttm_tt_populate_populated_ttm
[16:40:18] [PASSED] ttm_tt_unpopulate_basic
[16:40:18] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:40:18] [PASSED] ttm_tt_swapin_basic
[16:40:18] ===================== [PASSED] ttm_tt ======================
[16:40:18] =================== ttm_bo (14 subtests) ===================
[16:40:18] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:40:18] [PASSED] Cannot be interrupted and sleeps
[16:40:18] [PASSED] Cannot be interrupted, locks straight away
[16:40:18] [PASSED] Can be interrupted, sleeps
[16:40:18] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:40:18] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:40:18] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:40:18] [PASSED] ttm_bo_reserve_double_resv
[16:40:18] [PASSED] ttm_bo_reserve_interrupted
[16:40:18] [PASSED] ttm_bo_reserve_deadlock
[16:40:18] [PASSED] ttm_bo_unreserve_basic
[16:40:18] [PASSED] ttm_bo_unreserve_pinned
[16:40:18] [PASSED] ttm_bo_unreserve_bulk
[16:40:18] [PASSED] ttm_bo_fini_basic
[16:40:18] [PASSED] ttm_bo_fini_shared_resv
[16:40:18] [PASSED] ttm_bo_pin_basic
[16:40:18] [PASSED] ttm_bo_pin_unpin_resource
[16:40:18] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:40:18] ===================== [PASSED] ttm_bo ======================
[16:40:18] ============== ttm_bo_validate (22 subtests) ===============
[16:40:18] ============== ttm_bo_init_reserved_sys_man  ===============
[16:40:18] [PASSED] Buffer object for userspace
[16:40:18] [PASSED] Kernel buffer object
[16:40:18] [PASSED] Shared buffer object
[16:40:18] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:40:18] ============== ttm_bo_init_reserved_mock_man  ==============
[16:40:18] [PASSED] Buffer object for userspace
[16:40:18] [PASSED] Kernel buffer object
[16:40:18] [PASSED] Shared buffer object
[16:40:18] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:40:18] [PASSED] ttm_bo_init_reserved_resv
[16:40:18] ================== ttm_bo_validate_basic  ==================
[16:40:18] [PASSED] Buffer object for userspace
[16:40:18] [PASSED] Kernel buffer object
[16:40:18] [PASSED] Shared buffer object
[16:40:18] ============== [PASSED] ttm_bo_validate_basic ==============
[16:40:18] [PASSED] ttm_bo_validate_invalid_placement
[16:40:18] ============= ttm_bo_validate_same_placement  ==============
[16:40:18] [PASSED] System manager
[16:40:18] [PASSED] VRAM manager
[16:40:18] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:40:18] [PASSED] ttm_bo_validate_failed_alloc
[16:40:18] [PASSED] ttm_bo_validate_pinned
[16:40:18] [PASSED] ttm_bo_validate_busy_placement
[16:40:18] ================ ttm_bo_validate_multihop  =================
[16:40:18] [PASSED] Buffer object for userspace
[16:40:18] [PASSED] Kernel buffer object
[16:40:18] [PASSED] Shared buffer object
[16:40:18] ============ [PASSED] ttm_bo_validate_multihop =============
[16:40:18] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:40:18] [PASSED] Buffer object in system domain, no page vector
[16:40:18] [PASSED] Buffer object in system domain with an existing page vector
[16:40:18] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:40:18] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:40:18] [PASSED] Buffer object for userspace
[16:40:18] [PASSED] Kernel buffer object
[16:40:18] [PASSED] Shared buffer object
[16:40:18] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:40:18] [PASSED] ttm_bo_validate_move_fence_signaled
[16:40:18] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:40:18] [PASSED] Waits for GPU
[16:40:18] [PASSED] Tries to lock straight away
[16:40:18] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:40:18] [PASSED] ttm_bo_validate_swapout
[16:40:18] [PASSED] ttm_bo_validate_happy_evict
[16:40:18] [PASSED] ttm_bo_validate_all_pinned_evict
[16:40:18] [PASSED] ttm_bo_validate_allowed_only_evict
[16:40:18] [PASSED] ttm_bo_validate_deleted_evict
[16:40:18] [PASSED] ttm_bo_validate_busy_domain_evict
[16:40:18] [PASSED] ttm_bo_validate_evict_gutting
[16:40:18] [PASSED] ttm_bo_validate_recrusive_evict
[16:40:18] ================= [PASSED] ttm_bo_validate =================
[16:40:18] ============================================================
[16:40:18] Testing complete. Ran 102 tests: passed: 102
[16:40:18] Elapsed time: 11.968s total, 1.812s configuring, 9.942s building, 0.184s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/dp_link: Unify modeset/fallback config selection

[Patchwork]

== Series Details ==

Series: drm/i915/dp_link: Unify modeset/fallback config selection
URL   : https://patchwork.freedesktop.org/series/169636/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast f6157a5d128c8b41e39133ce58d1daf430d42bd5
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+/kernel/Makefile:1280: C=1 specified, but sparse is not available or not up to date

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/dp_link: Unify modeset/fallback config selection

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 971 bytes --]

== Series Details ==

Series: drm/i915/dp_link: Unify modeset/fallback config selection
URL   : https://patchwork.freedesktop.org/series/169636/
State : success

== Summary ==

CI Bug Log - changes from xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d_BAT -> xe-pw-169636v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d -> xe-pw-169636v1

  IGT_8989: a8e2cbd2854d7980a9eccecc6e0c801d0824b88f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d: 1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d
  xe-pw-169636v1: 169636v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/index.html

[-- Attachment #2: Type: text/html, Size: 1519 bytes --]

RE: [PATCH v2 01/34] drm/i915/doc: Document DP link capabilities

[Kandpal, Suraj]

> Subject: [PATCH v2 01/34] drm/i915/doc: Document DP link capabilities
> 
> Add documentation for the DP link capabilities interface.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  .../intel-display/dp-link-capabilities.rst    | 11 +++
>  Documentation/gpu/intel-display/index.rst     |  1 +
>  .../gpu/drm/i915/display/intel_dp_link_caps.c | 81 +++++++++++++++++++
>  3 files changed, 93 insertions(+)
>  create mode 100644 Documentation/gpu/intel-display/dp-link-capabilities.rst
> 
> diff --git a/Documentation/gpu/intel-display/dp-link-capabilities.rst
> b/Documentation/gpu/intel-display/dp-link-capabilities.rst
> new file mode 100644
> index 0000000000000..331cc69d13a04
> --- /dev/null
> +++ b/Documentation/gpu/intel-display/dp-link-capabilities.rst
> @@ -0,0 +1,11 @@
> +.. SPDX-License-Identifier: MIT
> +.. Copyright © 2026 Intel Corporation
> +
> +DisplayPort Link Capabilities
> +=============================
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +   :doc: DisplayPort link capabilities
> +
> +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> +   :internal:
> diff --git a/Documentation/gpu/intel-display/index.rst
> b/Documentation/gpu/intel-display/index.rst
> index 6fa929d82c38c..e81f49bf20df6 100644
> --- a/Documentation/gpu/intel-display/index.rst
> +++ b/Documentation/gpu/intel-display/index.rst
> @@ -39,6 +39,7 @@ driver. The display driver isn't an independent driver in
> that sense.
>     frontbuffer
>     hotplug
>     dp-link-training
> +   dp-link-capabilities
>     plane
>     psr
>     snps-phy
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> index 1c34ba6c49c35..2c656c2c036cc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> @@ -19,6 +19,87 @@
>  #include "intel_dp.h"
>  #include "intel_dp_link_caps.h"
> 
> +/**
> + * DOC: DisplayPort link capabilities
> + *
> + * The Intel DP link caps API tracks the supported and allowed
> + * DisplayPort link configurations for a DP encoder and its attached
> + * connectors, and provides helpers to iterate over the allowed
> + * configurations and constrain them by filtering, disabling, or
> + * limiting them to maximum link parameters.
> + *
> + * Locking
> + * -------
> + *
> + * All accesses to this API must be serialized. The only exception
> + * is intel_dp_link_caps_get_max_limits(), which allow lockless
> + * lookup. Such lookups may observe an out-of-sync &struct
> + * intel_dp_link_config tuple, i.e. a rate from one state and a lane
> + * count from another.
> + *
> + * The Intel i915/xe drivers ensure the above serialization by holding
> + * &drm_mode_config.connection_mutex and, while holding the lock,
> + * waiting for any pending asynchronous atomic commits. This also allows
> + * use of the API from the tails of asynchronous atomic commits, which
> + * cannot hold the lock.
> + *
> + * Iterating and restricting link configurations
> + * ---------------------------------------------
> + *
> + * The link configuration iterators can iterate the ``allowed
> + * configurations`` during modeset configuration selection or link
> + * training fallback handling in a configurable order.
> + *
> + * The iteration order can depend on connector type (eDP, DP SST,
> + * DP MST) and modeset-specific conditions or driver policies, such
> + * as DSC vs. non-DSC modes, power saving vs. better user experience,
> + * or policy changes after a link training failure.
> + *
> + * The configurations exposed via the iterators can be additionally
> + * constrained in the following ways:
> + *
> + * - Filtered for a given modeset based on modeset-specific conditions.
> + *   Examples for such conditions include driver policies preferring
> + *   power saving or better user experience, post-link training failure
> + *   preference changes, or sink automated test requests limiting the
> + *   usable configurations.
> + *
> + * - Disabled permanently for the connected sink. Examples of reasons
> + *   to disable a configuration include a link training failure for a
> + *   given configuration or a driver workaround preventing the use of
> + *   a particular configuration.
> + *
> + * - Limited via a maximum link rate and lane count. For example, after
> + *   a link training failure, subsequent modesets may be limited to
> + *   configurations at or below the failed parameters.
> + *
> + *   This mechanism exists for backward compatibility only. Eventually,
> + *   it will be removed in favor of relying solely on individually
> + *   disabled configurations, as described above.
> + *
> + * Terminology
> + * -----------
> + *
> + * ``Common link capabilities`` (or ``common caps``) refer to the link
> + * rates and maximum lane count supported by both the source and the
> + * sink, i.e. the intersection of their respective capabilities.
> + *
> + * ``Supported configurations`` are all configurations defined by the
> + * ``Common link capabilities``' link rates and maximum lane count.
> + *
> + * ``Disabled configurations`` are ``Supported configurations`` disabled
> + * via this API.
> + *
> + * ``Enabled configurations`` are ``Supported configurations`` that are
> + * not disabled.
> + *
> + * ``Forced configurations`` are ``Enabled configurations`` forced via
> + * forced link parameter debugfs entries.
> + *
> + * ``Allowed configurations`` are the ``Enabled configurations``, or if
> + * forcing is in effect the ``Forced configurations``, constrained by a
> + * maximum rate and lane count set via the API.
> + */
>  struct intel_dp_link_caps {
>  	struct intel_dp *dp;
> 
> --
> 2.49.1

Re: [PATCH v2 11/34] drm/i915/dp_link_caps: Add debugfs entry showing allowed configurations

[Luca Coelho]

On Wed, 2026-07-01 at 18:31 +0300, Imre Deak wrote:
> Add a debugfs entry showing the currently allowed link configurations
> in the connector's iteration order.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_caps.c | 40 +++++++++++++++++++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> index 3ef678d47c71b..4482e1f9d6cd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> @@ -1123,6 +1123,43 @@ static int i915_dp_max_lane_count_show(void *data, u64 *val)
>  }
>  DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n");
>  
> +static int intel_dp_allowed_link_configs_show(struct seq_file *m, void *data)
> +{
> +	struct intel_connector *connector = to_intel_connector(m->private);
> +	struct intel_display *display = to_intel_display(connector);
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_iter iter;
> +	int err;
> +	int i;
> +
> +	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
> +	if (err)
> +		return err;
> +
> +	intel_dp_flush_connector_commits(connector);
> +
> +	i = 0;
> +	intel_dp_link_caps_iter_start(&iter,
> +				      link_caps,
> +				      intel_dp_link_caps_connector_compute_order(connector),
> +				      INTEL_DP_LINK_CAPS_FILTER_ALL);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		seq_printf(m, "%s%dx%d",
> +			   i ? " " : "",
> +			   link_config.lane_count, link_config.rate);
> +		i++;
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
> +
> +	seq_putc(m, '\n');
> +
> +	return 0;
> +}
> +DEFINE_SHOW_ATTRIBUTE(intel_dp_allowed_link_configs);
>  
>  /**
>   * intel_dp_link_caps_debugfs_add - add link caps debugfs files for a connector
> @@ -1149,6 +1186,9 @@ void intel_dp_link_caps_debugfs_add(struct intel_connector *connector)
>  
>  	debugfs_create_file("i915_dp_max_lane_count", 0444, root,
>  			    connector, &i915_dp_max_lane_count_fops);
> +
> +	debugfs_create_file("intel_dp_allowed_link_configs", 0444, root,
> +			    connector, &intel_dp_allowed_link_configs_fops);
>  }
>  
>  struct intel_dp_link_caps *intel_dp_link_caps_init(struct intel_dp *intel_dp)

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

--
Cheers,
Luca.

Re: [PATCH v2 12/34] drm/i915/dp: Add link configuration filter for modeset computation

[Luca Coelho]

On Wed, 2026-07-01 at 18:31 +0300, Imre Deak wrote:
> Add link_config_filter to link_config_limits to track the set of valid
> link configurations during modeset state computation. Keep the existing
> min/max rate and lane count limits for now, until all users are
> converted to use the configuration filter.
> 
> Add the helpers required to select the maximum configuration from the
> currently allowed configuration set. This will be used by follow-up
> changes as well to query the maximum link configuration without having
> to iterate the configurations.
> 
> v2:
> - Rebase on changes using a filter object instead of a mask of
>   configuration indices.
> - Rebase on changes using an iteration object.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c       | 42 +++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_dp.h       | 11 +++++
>  .../gpu/drm/i915/display/intel_dp_link_caps.c | 46 +++++++++++++++++++
>  .../gpu/drm/i915/display/intel_dp_link_caps.h |  6 +++
>  4 files changed, 102 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 23001541283b4..bc333bc9296b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2577,6 +2577,20 @@ bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector,
>  					       bw_overhead_flags);
>  }
>  
> +bool
> +intel_dp_get_connector_max_link_config(struct intel_connector *connector,
> +				       const struct link_config_limits *limits,
> +				       struct intel_dp_link_config *max_link_config)
> +{
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> +	struct intel_dp_link_caps_order order =
> +		intel_dp_link_caps_connector_compute_order(connector);
> +
> +	return intel_dp_link_caps_get_max_config(link_caps, order.key, limits->link_config_filter,
> +						 max_link_config);
> +}
> +
>  /*
>   * Calculate the output link min, max bpp values in limits based on the pipe bpp
>   * range, crtc_state and dsc mode. Return true on success.
> @@ -2593,6 +2607,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector,
>  		&crtc_state->hw.adjusted_mode;
>  	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	struct intel_dp_link_config max_link_config;
>  	int max_link_bpp_x16;
>  
>  	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
> @@ -2622,14 +2637,17 @@ intel_dp_compute_config_link_bpp_limits(struct intel_connector *connector,
>  
>  	limits->link.max_bpp_x16 = max_link_bpp_x16;
>  
> +	if (!intel_dp_get_connector_max_link_config(connector, limits, &max_link_config))
> +		return false;
> +
>  	drm_dbg_kms(display->drm,
> -		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n",
> +		    "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max link %dx%d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n",
>  		    encoder->base.base.id, encoder->base.name,
>  		    crtc->base.base.id, crtc->base.name,
>  		    adjusted_mode->crtc_clock,
>  		    str_on_off(dsc),
> -		    limits->max_lane_count,
> -		    limits->max_rate,
> +		    max_link_config.lane_count,
> +		    max_link_config.rate,
>  		    limits->pipe.max_bpp,
>  		    FXP_Q4_ARGS(limits->link.min_bpp_x16),
>  		    FXP_Q4_ARGS(limits->link.max_bpp_x16));
> @@ -2680,10 +2698,15 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  			       struct link_config_limits *limits)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
>  	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  
> +	/*
> +	 * Remove the following min/max rate and lane count setup, once
> +	 * all users are converted to use link_config_mask instead.
> +	 */

Should there be a "TODO" here to make it easier to grep for?


>  	limits->min_rate = intel_dp_min_link_rate(intel_dp);
>  	limits->max_rate = intel_dp_max_link_rate(intel_dp);
>  
> @@ -2692,6 +2715,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
>  	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> +	limits->link_config_filter = INTEL_DP_LINK_CAPS_FILTER_ALL;
> +
>  	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
>  	if (is_mst) {
>  		/*
> @@ -2755,6 +2780,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  			    crtc_state->pipe_bpp, limits->pipe.max_bpp);
>  
>  	if (is_mst || intel_dp->use_max_params) {
> +		struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
> +		struct intel_dp_link_config max_config;
> +
>  		/*
>  		 * For MST we always configure max link bw - the spec doesn't
>  		 * seem to suggest we should do otherwise.
> @@ -2768,6 +2796,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  		 */
>  		limits->min_lane_count = limits->max_lane_count;
>  		limits->min_rate = limits->max_rate;
> +
> +		if (!intel_dp_get_connector_max_link_config(connector, limits, &max_config))
> +			return false;
> +
> +		if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, &max_config))
> +			return false;
> +
> +		limits->link_config_filter = new_filter;
>  	}
>  
>  	intel_dp_test_compute_config(intel_dp, crtc_state, limits);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 02b691df67555..13872b8c4975e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -8,6 +8,8 @@
>  
>  #include <linux/types.h>
>  
> +#include "intel_dp_link_caps.h"
> +
>  enum intel_output_format;
>  enum pipe;
>  enum port;
> @@ -22,11 +24,17 @@ struct intel_crtc_state;
>  struct intel_digital_port;
>  struct intel_display;
>  struct intel_dp;
> +struct intel_dp_link_config;
>  struct intel_encoder;
>  
>  struct link_config_limits {
> +	/*
> +	 * TODO: Remove the following min/max rate and lane count limits
> +	 * once all users are converted to use link_config_mask instead.
> +	 */

...it would be consistent with this, at least.


>  	int min_rate, max_rate;
>  	int min_lane_count, max_lane_count;
> +	struct intel_dp_link_caps_filter link_config_filter;
>  	struct {
>  		/* Uncompressed DSC input or link output bpp in 1 bpp units */
>  		int min_bpp, max_bpp;
> @@ -144,6 +152,9 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
>  				 u8 dsc_max_bpc);
>  int intel_dp_compute_min_compressed_bpp_x16(struct intel_connector *connector,
>  					    enum intel_output_format output_format);
> +bool intel_dp_get_connector_max_link_config(struct intel_connector *connector,
> +					    const struct link_config_limits *limits,
> +					    struct intel_dp_link_config *max_link_config);
>  bool intel_dp_mode_valid_with_dsc(struct intel_connector *connector,
>  				  int link_clock, int lane_count,
>  				  int mode_clock, int mode_hdisplay,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> index 4482e1f9d6cd8..d00bb8047de2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> @@ -504,6 +504,52 @@ void intel_dp_link_caps_iter_end(struct intel_dp_link_caps_iter *iter)
>  	memset(iter, 0, sizeof(*iter));
>  }
>  
> +/**
> + * intel_dp_link_caps_get_max_config - get the maximum config in a given order
> + * @link_caps: link capabilities state
> + * @order_key: ordering key used to rank candidate configurations
> + * @filter: filter for candidate configurations
> + * @max_config: returned maximum link configuration
> + *
> + * Find the last configuration among the currently allowed
> + * configurations filtered by @filter in the iteration order
> + * selected by @order_key, and store it in @max_config.
> + *
> + * See also:
> + * - &enum intel_dp_link_caps_order_key
> + *
> + * Returns:
> + * %true if a maximum config is returned
> + * %false otherwise.
> + */
> +bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
> +				       enum intel_dp_link_caps_order_key order_key,
> +				       struct intel_dp_link_caps_filter filter,
> +				       struct intel_dp_link_config *max_config)
> +{
> +	struct intel_dp_link_caps_order order = {
> +		.key = order_key,
> +		.dir = INTEL_DP_LINK_CAPS_ORDER_DIR_DESC
> +	};
> +	struct intel_dp_link_config iter_config;
> +	struct intel_dp_link_caps_iter iter;
> +	bool found = false;
> +
> +	intel_dp_link_caps_iter_start(&iter, link_caps, order, filter);
> +	for_each_dp_link_config(&iter, &iter_config) {
> +		found = true;
> +		break;
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	if (!found)
> +		return false;
> +
> +	*max_config = iter_config;
> +
> +	return true;
> +}
> +
>  static int find_config_idx(struct intel_dp_link_caps *link_caps,
>  			   struct intel_dp_link_caps_filter filter,
>  			   const struct intel_dp_link_config *link_config)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> index dcbde890809bc..6dd2ce64e24ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> @@ -29,6 +29,7 @@ struct intel_dp_link_config;
>   *
>   * See also:
>   *  - &struct intel_dp_link_caps_order
> + *  - intel_dp_link_caps_get_max_config()
>   */
>  enum intel_dp_link_caps_order_key {
>  	INTEL_DP_LINK_CAPS_ORDER_KEY_BW,
> @@ -140,6 +141,11 @@ bool intel_dp_link_caps_filter_add(struct intel_dp_link_caps *link_caps,
>  				   struct intel_dp_link_caps_filter *filter,
>  				   const struct intel_dp_link_config *config);
>  
> +bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
> +				       enum intel_dp_link_caps_order_key order_key,
> +				       struct intel_dp_link_caps_filter filter,
> +				       struct intel_dp_link_config *max_config);
> +
>  void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
>  				       struct intel_dp_link_config *max_link_limits);
>  bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,

Small nit, but regardless:

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

--
Cheers,
Luca.

Re: [PATCH v2 13/34] drm/i915/dp_link_caps: Add helper to query max BW link configuration

[Luca Coelho]

On Wed, 2026-07-01 at 18:31 +0300, Imre Deak wrote:
> Add a helper to query the link configuration among the currently allowed
> configurations with the maximum link BW.
> 
> This will be used by follow-up changes to unify the max BW link config
> query during mode validation and TBT BW calculation.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_dp_link_caps.c   | 17 +++++++++++++++++
>  .../gpu/drm/i915/display/intel_dp_link_caps.h   |  3 +++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> index d00bb8047de2f..c209c8a935234 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> @@ -550,6 +550,23 @@ bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
>  	return true;
>  }
>  
> +/**
> + * intel_dp_link_caps_get_max_bw_config - get maximum BW link configuration
> + * @link_caps: link capabilities state
> + * @max_config: returned maximum link configuration
> + *
> + * Return the maximum BW link configuration among the currently
> + * allowed configurations.
> + */
> +void intel_dp_link_caps_get_max_bw_config(struct intel_dp_link_caps *link_caps,
> +					  struct intel_dp_link_config *max_config)
> +{
> +	if (!intel_dp_link_caps_get_max_config(link_caps,
> +					       bw_desc_config_order().key, INTEL_DP_LINK_CAPS_FILTER_ALL,
> +					       max_config))
> +		*max_config = INTEL_DP_LINK_CONFIG_NULL;
> +}
> +
>  static int find_config_idx(struct intel_dp_link_caps *link_caps,
>  			   struct intel_dp_link_caps_filter filter,
>  			   const struct intel_dp_link_config *link_config)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> index 6dd2ce64e24ed..667bd70b2396d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> @@ -146,6 +146,9 @@ bool intel_dp_link_caps_get_max_config(struct intel_dp_link_caps *link_caps,
>  				       struct intel_dp_link_caps_filter filter,
>  				       struct intel_dp_link_config *max_config);
>  
> +void intel_dp_link_caps_get_max_bw_config(struct intel_dp_link_caps *link_caps,
> +					  struct intel_dp_link_config *max_config);
> +
>  void intel_dp_link_caps_get_max_limits(struct intel_dp_link_caps *link_caps,
>  				       struct intel_dp_link_config *max_link_limits);
>  bool intel_dp_link_caps_set_max_limits(struct intel_dp_link_caps *link_caps,

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

--
Cheers,
Luca.

Re: [PATCH v2 14/34] drm/i915/dp: Query max BW config via link_caps during mode validation

[Luca Coelho]

On Wed, 2026-07-01 at 18:31 +0300, Imre Deak wrote:
> Query the maximum link BW configuration during mode validation and MST
> link probing directly from intel_dp_link_caps_get_max_bw_config(),
> instead of using the intel_dp_max_link_rate() and
> intel_dp_max_lane_count() helpers.
> 
> This makes the max BW link config query uniform across mode validation
> and TBT BW calculation, and allows unexporting the
> intel_dp_max_link_rate()/intel_dp_max_lane_count() helpers.
> 
> v2: Use the max BW link configuration, instead of the max link limits.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c     | 10 ++++++----
>  drivers/gpu/drm/i915/display/intel_dp.h     |  2 --
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++++++++++++----
>  3 files changed, 18 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index bc333bc9296b2..b10bbbf0f49bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -354,7 +354,7 @@ static int intel_dp_get_max_common_lane_count(struct intel_dp *intel_dp)
>  	return min3(source_max, sink_max, lane_max);
>  }
>  
> -int intel_dp_max_lane_count(struct intel_dp *intel_dp)
> +static int intel_dp_max_lane_count(struct intel_dp *intel_dp)
>  {
>  	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
>  	struct intel_dp_link_config max_link_limits;
> @@ -1331,6 +1331,7 @@ intel_dp_mode_valid_format(struct intel_connector *connector,
>  	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  	enum intel_output_format output_format;
>  	int max_rate, mode_rate, max_lanes, max_link_clock;
> +	struct intel_dp_link_config max_bw_config;
>  	u16 dsc_max_compressed_bpp = 0;
>  	enum drm_mode_status status;
>  	bool dsc = false;
> @@ -1343,8 +1344,9 @@ intel_dp_mode_valid_format(struct intel_connector *connector,
>  
>  	output_format = intel_dp_output_format(connector, sink_format);
>  
> -	max_link_clock = intel_dp_max_link_rate(intel_dp);
> -	max_lanes = intel_dp_max_lane_count(intel_dp);
> +	intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config);
> +	max_link_clock = max_bw_config.rate;
> +	max_lanes = max_bw_config.lane_count;
>  
>  	max_rate = intel_dp_max_link_data_rate(intel_dp, max_link_clock, max_lanes);
>  
> @@ -1538,7 +1540,7 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp)
>  	intel_dp_link_caps_print_common_rates(intel_dp->link.caps);
>  }
>  
> -int
> +static int
>  intel_dp_max_link_rate(struct intel_dp *intel_dp)
>  {
>  	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 13872b8c4975e..9564369ea4852 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -111,8 +111,6 @@ void intel_dp_mst_suspend(struct intel_display *display);
>  void intel_dp_mst_resume(struct intel_display *display);
>  int intel_dp_rate_limit_len(const int *rates, int len, int max_rate);
>  int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port);
> -int intel_dp_max_link_rate(struct intel_dp *intel_dp);
> -int intel_dp_max_lane_count(struct intel_dp *intel_dp);
>  int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state);
>  int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
>  int intel_dp_rate_index(const int *rates, int len, int rate);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index ecc90e8faee11..e113c9e60e67d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -47,6 +47,7 @@
>  #include "intel_display_wa.h"
>  #include "intel_dp.h"
>  #include "intel_dp_hdcp.h"
> +#include "intel_dp_link_caps.h"
>  #include "intel_dp_link_training.h"
>  #include "intel_dp_mst.h"
>  #include "intel_dp_test.h"
> @@ -1476,6 +1477,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  	unsigned long bw_overhead_flags =
>  		DRM_DP_BW_OVERHEAD_MST | DRM_DP_BW_OVERHEAD_SSC_REF_CLK;
>  	int min_link_bpp_x16 = fxp_q4_from_int(18);
> +	struct intel_dp_link_config max_bw_config;
>  	static bool supports_dsc;
>  	int ret;
>  	bool dsc = false;
> @@ -1508,8 +1510,9 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
>  		min_link_bpp_x16 = intel_dp_compute_min_compressed_bpp_x16(connector,
>  									   INTEL_OUTPUT_FORMAT_RGB);
>  
> -	max_link_clock = intel_dp_max_link_rate(intel_dp);
> -	max_lanes = intel_dp_max_lane_count(intel_dp);
> +	intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config);
> +	max_link_clock = max_bw_config.rate;
> +	max_lanes = max_bw_config.lane_count;
>  
>  	max_rate = intel_dp_max_link_data_rate(intel_dp,
>  					       max_link_clock, max_lanes);
> @@ -2135,14 +2138,19 @@ bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
>   */
>  void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp)
>  {
> -	int link_rate = intel_dp_max_link_rate(intel_dp);
> -	int lane_count = intel_dp_max_lane_count(intel_dp);
> +	struct intel_dp_link_config max_bw_config;
> +	int link_rate;
> +	int lane_count;
>  	u8 rate_select;
>  	u8 link_bw;
>  
>  	if (intel_dp->link.active)
>  		return;
>  
> +	intel_dp_link_caps_get_max_bw_config(intel_dp->link.caps, &max_bw_config);
> +	link_rate = max_bw_config.rate;
> +	lane_count = max_bw_config.lane_count;
> +
>  	if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count))
>  		return;
>  

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

--
Cheers,
Luca.

Re: [PATCH v2 15/34] drm/i915/dp_tunnel: Query max BW config via link_caps for BW computation

[Luca Coelho]

On Wed, 2026-07-01 at 18:31 +0300, Imre Deak wrote:
> Query the maximum link BW configuration via the link caps interface to
> compute the available TBT bandwidth. Unlike the max common link params
> used so far for this, the max BW config also accounts for any forced
> link parameters.
> 
> This makes the max BW link config query uniform across mode validation
> and TBT BW calculation, and allows unexporting the
> intel_dp_link_caps_max_common_lane_count() helper.
> 
> v2: Use the max BW link configuration, instead of the max link limits.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp_link_caps.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_dp_link_caps.h | 1 -
>  drivers/gpu/drm/i915/display/intel_dp_tunnel.c    | 8 +++++---
>  3 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> index c209c8a935234..8dfb7f4f703bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> @@ -290,7 +290,7 @@ void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps)
>  	drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
>  }
>  
> -int intel_dp_link_caps_max_common_lane_count(struct intel_dp_link_caps *link_caps)
> +static int intel_dp_link_caps_max_common_lane_count(struct intel_dp_link_caps *link_caps)
>  {
>  	return link_caps->max_lane_count;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> index 667bd70b2396d..07002d745d384 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.h
> @@ -125,7 +125,6 @@ int intel_dp_common_rate(struct intel_dp_link_caps *link_caps, int index);
>  int intel_dp_link_caps_common_rate_idx(struct intel_dp_link_caps *link_caps, int rate);
>  int intel_dp_max_common_rate(struct intel_dp_link_caps *link_caps);
>  int intel_dp_link_caps_num_common_rates(struct intel_dp_link_caps *link_caps);
> -int intel_dp_link_caps_max_common_lane_count(struct intel_dp_link_caps *link_caps);
>  
>  void intel_dp_link_caps_print_common_rates(struct intel_dp_link_caps *link_caps);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> index 76e9753766b9f..49fa4c9699b61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> @@ -58,10 +58,12 @@ static int kbytes_to_mbits(int kbytes)
>  static int get_current_link_bw(struct intel_dp *intel_dp)
>  {
>  	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> -	int rate = intel_dp_max_common_rate(link_caps);
> -	int lane_count = intel_dp_link_caps_max_common_lane_count(link_caps);
> +	struct intel_dp_link_config max_bw_config;
>  
> -	return intel_dp_max_link_data_rate(intel_dp, rate, lane_count);
> +	intel_dp_link_caps_get_max_bw_config(link_caps, &max_bw_config);
> +
> +	return intel_dp_max_link_data_rate(intel_dp, max_bw_config.rate,
> +						     max_bw_config.lane_count);
>  }
>  
>  static int __update_tunnel_state(struct intel_dp *intel_dp, bool force_sink_update)

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

--
Cheers,
Luca.

✓ Xe.CI.FULL: success for drm/i915/dp_link: Unify modeset/fallback config selection

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 40030 bytes --]

== Series Details ==

Series: drm/i915/dp_link: Unify modeset/fallback config selection
URL   : https://patchwork.freedesktop.org/series/169636/
State : success

== Summary ==

CI Bug Log - changes from xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d_FULL -> xe-pw-169636v1_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-169636v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-bmg:          [PASS][1] -> [ABORT][2] ([Intel XE#8007])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-1/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-9/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#3157])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_big_fb@y-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][6] ([Intel XE#1124]) +7 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-1920x1080p:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#7679])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_bw@connected-linear-tiling-3-displays-target-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#8365]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_bw@linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-4-displays-target-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#367])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_bw@linear-tiling-4-displays-target-2560x1440p.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#2887]) +7 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4-lut1d:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#7358])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4-lut1d.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2252])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#373]) +4 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_content_protection@lic-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#7642])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_content_protection@lic-type-1.html
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#7642])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_content_protection@lic-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#1424]) +4 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#2321] / [Intel XE#7355])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2321] / [Intel XE#7355])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2320])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][21] -> [FAIL][22] ([Intel XE#7571])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-8/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#4354] / [Intel XE#5882])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-with-bpc-bigjoiner:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#8265])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_dsc@dsc-with-bpc-bigjoiner.html

  * igt@kms_dsc@dsc-with-formats-ultrajoiner:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#8265]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_dsc@dsc-with-formats-ultrajoiner.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-bmg:          [PASS][26] -> [FAIL][27] ([Intel XE#3149] / [Intel XE#5408] / [Intel XE#6266]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-2/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#1421]) +4 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [PASS][29] -> [FAIL][30] ([Intel XE#3321]) +1 other test fail
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank@b-edp1:
    - shard-lnl:          [PASS][31] -> [FAIL][32] ([Intel XE#301])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#7178] / [Intel XE#7349])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1397] / [Intel XE#7385])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][36] ([Intel XE#7178] / [Intel XE#7351]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7178] / [Intel XE#7351])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_force_connector_basic@force-edid:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#352])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7061] / [Intel XE#7356])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-slowdraw:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#2311]) +8 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrshdr-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#4141]) +1 other test skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#6312] / [Intel XE#651]) +8 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#6312]) +11 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#2313]) +6 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#7865]) +19 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#7061])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][47] ([Intel XE#7905]) +25 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#656] / [Intel XE#7905]) +19 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#7061] / [Intel XE#7356]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-abgr161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#7061]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psrhdr-abgr161616f-draw-render.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#6900] / [Intel XE#7362])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#7283]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#7283])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#3307])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          NOTRUN -> [FAIL][56] ([Intel XE#2029] / [Intel XE#7395])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][59] ([Intel XE#4608])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#4608] / [Intel XE#7304])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#2893] / [Intel XE#7304]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#1489])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1128] / [Intel XE#7413]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-bmg:          NOTRUN -> [SKIP][64] ([Intel XE#2387] / [Intel XE#7429])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr2-cursor-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#1406] / [Intel XE#7345]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_psr@fbc-psr2-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr2-dpms@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#1406] / [Intel XE#4609]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_psr@fbc-psr2-dpms@edp-1.html

  * igt@kms_psr@pr-no-drrs:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#1406]) +1 other test skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@psr-no-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][68] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_psr@psr-no-drrs.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][69] ([Intel XE#2234])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1127] / [Intel XE#5813])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1435])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor:
    - shard-bmg:          NOTRUN -> [SKIP][73] ([Intel XE#6503])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-nearest-neighbor.html

  * igt@xe_compute@eu-busy-10s:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#6592] / [Intel XE#6645] / [Intel XE#7391])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_compute@eu-busy-10s.html

  * igt@xe_eudebug@basic-vm-access-faultable:
    - shard-lnl:          NOTRUN -> [SKIP][75] ([Intel XE#7636]) +8 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_eudebug@basic-vm-access-faultable.html

  * igt@xe_eudebug@basic-vm-access-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#7636]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_eudebug@basic-vm-access-userptr.html

  * igt@xe_evict@evict-beng-mixed-many-threads-large:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#6540] / [Intel XE#688]) +5 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_evict@evict-beng-mixed-many-threads-large.html

  * igt@xe_exec_balancer@many-parallel-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#7482]) +9 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_exec_balancer@many-parallel-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#1392]) +4 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#8374]) +7 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_exec_fault_mode@many-execqueues-multi-queue-prefetch.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-imm:
    - shard-bmg:          NOTRUN -> [SKIP][82] ([Intel XE#8374])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_exec_fault_mode@many-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-queues-dyn-priority-smem:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#8364]) +4 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-dyn-priority-smem.html

  * igt@xe_exec_multi_queue@one-queue-basic:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#8364]) +20 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_exec_multi_queue@one-queue-basic.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-basic:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#8378])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-mixed-fd-basic.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#8378]) +5 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-rebind.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_device_create:
    - shard-lnl:          [PASS][87] -> [ABORT][88] ([Intel XE#8007])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-lnl-3/igt@xe_fault_injection@inject-fault-probe-function-xe_device_create.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-4/igt@xe_fault_injection@inject-fault-probe-function-xe_device_create.html

  * igt@xe_madvise@atomic-device:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#7980])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_madvise@atomic-device.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#6964]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_multigpu_svm@mgpu-pagefault-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][91] ([Intel XE#6964])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_multigpu_svm@mgpu-pagefault-prefetch.html

  * igt@xe_page_reclaim@prl-max-entries:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#7793]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@xe_page_reclaim@prl-max-entries.html
    - shard-bmg:          NOTRUN -> [SKIP][93] ([Intel XE#7793])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_page_reclaim@prl-max-entries.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#7590] / [Intel XE#979])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][95] ([Intel XE#7599])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-2/igt@xe_prefetch_fault@prefetch-fault-svm.html
    - shard-lnl:          NOTRUN -> [SKIP][96] ([Intel XE#7599])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_query@multigpu-query-config:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#944])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_query@multigpu-query-config.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#4130] / [Intel XE#7366])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-2/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-reduce-numvfs.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#3342])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_sriov_flr@flr-twice:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#4273])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_sriov_flr@flr-twice.html

  * igt@xe_sriov_scheduling@equal-throughput-normal-priority:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#8339])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_sriov_scheduling@equal-throughput-normal-priority.html

  * igt@xe_sriov_vfio@region-info:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#7724]) +1 other test skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-7/igt@xe_sriov_vfio@region-info.html

  * igt@xe_vm@overcommit-fault-vram-lr-no-overcommit:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#7892])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_vm@overcommit-fault-vram-lr-no-overcommit.html

  
#### Possible fixes ####

  * igt@kms_flip@2x-flip-vs-expired-vblank@bc-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][104] ([Intel XE#3321]) -> [PASS][105] +1 other test pass
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank@bc-dp2-hdmi-a3.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-9/igt@kms_flip@2x-flip-vs-expired-vblank@bc-dp2-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          [FAIL][106] ([Intel XE#301]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@xe_exec_reset@long-spin-many-preempt-gt1-threads:
    - shard-bmg:          [FAIL][108] ([Intel XE#7956]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-1/igt@xe_exec_reset@long-spin-many-preempt-gt1-threads.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-8/igt@xe_exec_reset@long-spin-many-preempt-gt1-threads.html

  * igt@xe_survivability@runtime-survivability:
    - shard-bmg:          [DMESG-WARN][110] ([Intel XE#6627] / [Intel XE#7419]) -> [PASS][111]
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-7/igt@xe_survivability@runtime-survivability.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-10/igt@xe_survivability@runtime-survivability.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-lnl:          [ABORT][112] ([Intel XE#8007]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-lnl-8/igt@xe_wedged@wedged-mode-toggle.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-3/igt@xe_wedged@wedged-mode-toggle.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][114] ([Intel XE#309] / [Intel XE#7343]) -> [SKIP][115] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-lnl-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][116] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][117] ([Intel XE#1729] / [Intel XE#7424])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][118] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][119] ([Intel XE#2509] / [Intel XE#7437])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#3307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3307
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/352
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#5408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5408
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5882
  [Intel XE#6266]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6266
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6592]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6592
  [Intel XE#6627]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6627
  [Intel XE#6645]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6645
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7362
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7391
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7419]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7419
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7724
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#7956]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7956
  [Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8365
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d -> xe-pw-169636v1

  IGT_8989: a8e2cbd2854d7980a9eccecc6e0c801d0824b88f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5323-1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d: 1fbbf91a9b037639c3c7ffa4f92abb3e701bbf3d
  xe-pw-169636v1: 169636v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169636v1/index.html

[-- Attachment #2: Type: text/html, Size: 45570 bytes --]

Re: [PATCH v2 16/34] drm/i915/dp_test: Use link caps for compliance link configs

[Luca Coelho]

On Wed, 2026-07-01 at 18:31 +0300, Imre Deak wrote:
> Use the link caps configuration mask when applying DP compliance test
> link parameters during state computation.
> 
> Preserve the legacy behavior of falling back to all configurations with
> the requested lane count if the requested rate and lane count pair is
> not allowed.
> 
> In case no valid configuration is found fail the modeset.
> 
> v2:
> - Rebase on changes using a filter object instead of a mask of
>   configuration indices.
> - Rebase on changes using an iteration object.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c      |  3 +-
>  drivers/gpu/drm/i915/display/intel_dp_test.c | 96 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dp_test.h |  3 +-
>  3 files changed, 99 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b10bbbf0f49bf..42bb1c7622525 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2808,7 +2808,8 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  		limits->link_config_filter = new_filter;
>  	}
>  
> -	intel_dp_test_compute_config(intel_dp, crtc_state, limits);
> +	if (!intel_dp_test_compute_config(connector, crtc_state, limits))
> +		return false;
>  
>  	return intel_dp_compute_config_link_bpp_limits(connector,
>  						       crtc_state,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.c b/drivers/gpu/drm/i915/display/intel_dp_test.c
> index da7632536dace..ec7fa690910bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_test.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_test.c
> @@ -28,11 +28,92 @@ void intel_dp_test_reset(struct intel_dp *intel_dp)
>  	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
>  }
>  
> +static bool set_filter_for_lane_count(struct intel_connector *connector,
> +				      struct intel_dp_link_caps *link_caps,
> +				      int lane_count,
> +				      struct link_config_limits *limits)
> +{
> +	struct intel_dp_link_config link_config;
> +	struct intel_dp_link_caps_order order =
> +		intel_dp_link_caps_connector_compute_order(connector);
> +	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
> +	struct intel_dp_link_caps_iter iter;
> +	bool found = false;
> +
> +	intel_dp_link_caps_iter_start(&iter, link_caps, order, limits->link_config_filter);
> +	for_each_dp_link_config(&iter, &link_config) {
> +		if (link_config.lane_count != lane_count)
> +			continue;
> +
> +		intel_dp_link_caps_filter_add(link_caps, &new_filter, &link_config);
> +		found = true;
> +	}
> +	intel_dp_link_caps_iter_end(&iter);
> +
> +	if (!found)
> +		return false;
> +
> +	limits->link_config_filter = new_filter;
> +
> +	return true;
> +}
> +
> +static bool set_filter_for_link_config(struct intel_connector *connector,
> +				       struct intel_dp_link_caps *link_caps,
> +				       const struct intel_dp_link_config *link_params,
> +				       struct link_config_limits *limits)
> +{
> +	struct intel_dp_link_caps_filter new_filter = INTEL_DP_LINK_CAPS_FILTER_NONE;
> +
> +	if (!intel_dp_link_caps_filter_add(link_caps, &new_filter, link_params))
> +		return false;
> +
> +	limits->link_config_filter = new_filter;
> +
> +	return true;
> +}
> +
> +static bool set_filter_for_link_params(struct intel_connector *connector,
> +				       int link_rate, int lane_count,
> +				       struct link_config_limits *limits)
> +{
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
> +	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> +	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
> +	struct intel_display *display = to_intel_display(intel_dp);
> +	struct intel_dp_link_config requested_config;
> +
> +	requested_config.rate = link_rate;
> +	requested_config.lane_count = lane_count;
> +
> +	if (set_filter_for_link_config(connector, link_caps, &requested_config, limits))
> +		return true;
> +
> +	/*
> +	 * Preserve the legacy behavior: if the requested (rate, lane_count)
> +	 * combination is not an allowed config, fall back to all configs
> +	 * matching the requested lane count.
> +	 *
> +	 * TODO: Recheck whether this behavior is actually correct.
> +	 */
> +	if (set_filter_for_lane_count(connector, link_caps, lane_count, limits))
> +		return true;
> +
> +	drm_dbg_kms(display->drm,
> +		    "[ENCODER:%d:%s] Invalid autotest link config parameters: %dx%d\n",
> +		    encoder->base.base.id, encoder->base.name,
> +		    requested_config.lane_count,
> +		    requested_config.rate);
> +
> +	return false;
> +}
> +
>  /* Adjust link config limits based on compliance test requests. */
> -void intel_dp_test_compute_config(struct intel_dp *intel_dp,
> +bool intel_dp_test_compute_config(struct intel_connector *connector,
>  				  struct intel_crtc_state *pipe_config,
>  				  struct link_config_limits *limits)
>  {
> +	struct intel_dp *intel_dp = intel_attached_dp(connector);
>  	struct intel_dp_link_caps *link_caps = intel_dp->link.caps;
>  	struct intel_display *display = to_intel_display(intel_dp);
>  
> @@ -51,6 +132,11 @@ void intel_dp_test_compute_config(struct intel_dp *intel_dp,
>  	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
>  		int index;
>  
> +		/*
> +		 * TODO: Remove the following min/max link limit setup
> +		 * after converting to use the link configuration filter
> +		 * instead in limits.
> +		 */
>  		/* Validate the compliance test data since max values
>  		 * might have changed due to link train fallback.
>  		 */
> @@ -65,7 +151,15 @@ void intel_dp_test_compute_config(struct intel_dp *intel_dp,
>  			limits->min_lane_count = intel_dp->compliance.test_lane_count;
>  			limits->max_lane_count = intel_dp->compliance.test_lane_count;
>  		}
> +
> +		if (!set_filter_for_link_params(connector,
> +						intel_dp->compliance.test_link_rate,
> +						intel_dp->compliance.test_lane_count,
> +						limits))
> +			return false;
>  	}
> +
> +	return true;
>  }
>  
>  /* Compliance test status bits  */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_test.h b/drivers/gpu/drm/i915/display/intel_dp_test.h
> index dcc167e4c7f65..a08f37a63dc9a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_test.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_test.h
> @@ -6,6 +6,7 @@
>  
>  #include <linux/types.h>
>  
> +struct intel_connector;
>  struct intel_crtc_state;
>  struct intel_display;
>  struct intel_dp;
> @@ -13,7 +14,7 @@ struct link_config_limits;
>  
>  void intel_dp_test_reset(struct intel_dp *intel_dp);
>  void intel_dp_test_request(struct intel_dp *intel_dp);
> -void intel_dp_test_compute_config(struct intel_dp *intel_dp,
> +bool intel_dp_test_compute_config(struct intel_connector *connector,
>  				  struct intel_crtc_state *pipe_config,
>  				  struct link_config_limits *limits);
>  bool intel_dp_test_phy(struct intel_dp *intel_dp);

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>

--
Cheers,
Luca.

RE: [PATCH v2 02/34] drm/i915/dp_link_caps: Factor out helper to get link config by index

[Kandpal, Suraj]

> Subject: [PATCH v2 02/34] drm/i915/dp_link_caps: Factor out helper to get link
> config by index
> 
> Factor out a helper that looks up a link configuration by index.
> This provides the link configuration directly, avoiding the indirect conversion
> via the packed config entry.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_dp_link_caps.c  | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> index 2c656c2c036cc..d0a863b00b458 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_caps.c
> @@ -235,6 +235,16 @@ static int intel_dp_link_config_lane_count(const struct
> intel_dp_link_config_ent
>  	return 1 << lce->lane_count_exp;
>  }
> 
> +static void
> +to_intel_dp_link_config(struct intel_dp_link_caps *link_caps,
> +			int config_idx, struct intel_dp_link_config *config) {
> +	const struct intel_dp_link_config_entry *lce =
> +&link_caps->configs[config_idx];
> +
> +	config->rate = intel_dp_link_config_rate(link_caps, lce);
> +	config->lane_count = intel_dp_link_config_lane_count(lce);
> +}
> +
>  static void set_max_link_limits_no_update(struct intel_dp_link_caps
> *link_caps,
>  					  const struct intel_dp_link_config
> *max_link_limits)  { @@ -401,15 +411,15 @@ void
> intel_dp_link_config_get(struct intel_dp_link_caps *link_caps,
>  			      int idx, int *link_rate, int *lane_count)  {
>  	struct intel_display *display = to_intel_display(link_caps->dp);
> -	const struct intel_dp_link_config_entry *lce;
> +	struct intel_dp_link_config config;
> 
>  	if (drm_WARN_ON(display->drm, idx < 0 || idx >= link_caps-
> >num_configs))
>  		idx = 0;
> 
> -	lce = &link_caps->configs[idx];
> +	to_intel_dp_link_config(link_caps, idx, &config);
> 
> -	*link_rate = intel_dp_link_config_rate(link_caps, lce);
> -	*lane_count = intel_dp_link_config_lane_count(lce);
> +	*link_rate = config.rate;
> +	*lane_count = config.lane_count;
>  }
> 
>  int intel_dp_link_config_index(struct intel_dp_link_caps *link_caps,
> --
> 2.49.1