From: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: himal.prasad.ghimiray@intel.com,
Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
Subject: [PATCH 1/6] drm/xe/pci: log ATS/PASID enablement state at probe
Date: Wed, 21 Oct 2026 09:41:12 +0530 [thread overview]
Message-ID: <20261021041117.1774877-2-naresh.kumar.g@intel.com> (raw)
In-Reply-To: <20261021041117.1774877-1-naresh.kumar.g@intel.com>
Add debug logging in xe_pci_probe() for ATS and PASID enablement state
when the corresponding capabilities are present.
This makes platform and IOMMU related bring up issues easier to diagnose.
Also add a small helper to report weather ATS and PASID are both enabled,
for use follow up checks that depend on both features.
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 7 +++++++
drivers/gpu/drm/xe/xe_pci.h | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e44b74b9aa27..40c0f4c42ed3 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -1275,6 +1275,13 @@ static int __xe_pci_probe(struct pci_dev *pdev, const struct xe_device_desc *des
xe_step_name(xe->info.step.media),
xe_step_name(xe->info.step.basedie));
+ if (pdev->ats_cap)
+ drm_dbg(&xe->drm, "Arch ATS = %s",
+ str_enabled_disabled(pdev->ats_enabled));
+ if (pdev->pasid_cap)
+ drm_dbg(&xe->drm, "Arch PASID = %s",
+ str_enabled_disabled(pdev->pasid_enabled));
+
drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
str_yes_no(xe_device_has_sriov(xe)),
xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
diff --git a/drivers/gpu/drm/xe/xe_pci.h b/drivers/gpu/drm/xe/xe_pci.h
index 11bcc5fe2c5b..5f784229a5ec 100644
--- a/drivers/gpu/drm/xe/xe_pci.h
+++ b/drivers/gpu/drm/xe/xe_pci.h
@@ -5,6 +5,7 @@
#ifndef _XE_PCI_H_
#define _XE_PCI_H_
+#include <linux/pci.h>
struct pci_dev;
@@ -12,4 +13,9 @@ int xe_register_pci_driver(void);
void xe_unregister_pci_driver(void);
struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev);
+static inline bool xe_pci_ats_pasid_enabled(struct pci_dev *pdev)
+{
+ return pdev->ats_enabled && pdev->pasid_enabled;
+}
+
#endif
--
2.43.0
next prev parent reply other threads:[~2026-10-21 4:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 4:11 [PATCH 0/6] ATS/PASID SVA support and PRI-less fault servicing Nareshkumar Gollakoti
2026-10-21 4:11 ` Nareshkumar Gollakoti [this message]
2026-10-21 4:32 ` [PATCH 1/6] drm/xe/pci: log ATS/PASID enablement state at probe sashiko-bot
2026-10-21 4:11 ` [PATCH 2/6] drm/xe/vm: Setup SVA infrastructure for PASID support Nareshkumar Gollakoti
2026-10-21 4:30 ` sashiko-bot
2026-10-21 4:11 ` [PATCH 3/6] drm/xe/vm: add helper to retrieve VM SVA PASID Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 4/6] drm/xe/lrc: program CTX_SYS_PASID for ATS/PASID-enabled contexts Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 5/6] drm/xe/pci: add helper for ATS/PASID without PRI Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 6/6] drm/xe/pagefault: add CPU mirror VMA for SVA faults " Nareshkumar Gollakoti
2026-10-21 4:35 ` sashiko-bot
2026-10-21 4:21 ` ✗ CI.KUnit: failure for ATS/PASID SVA support and PRI-less fault servicing Patchwork
2026-10-21 15:25 ` [PATCH 0/6] " Thomas Hellström
2026-10-22 6:30 ` Kumar G, Naresh
2026-10-22 11:12 ` Thomas Hellström
2026-10-21 21:24 ` Matthew Brost
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