[PATCH 4/6] drm/xe/lrc: program CTX_SYS_PASID for ATS/PASID-enabled contexts

[Nareshkumar Gollakoti <naresh.kumar.g@intel.com>]

Add CTX_SYS_PASID definitions to the LRC layout and program the field
during LRC context initialization when ATS and PASID are both enabled on
the PCI device.

When ATS/PASID support is available, fetch the VM SVA PASID and write it
to CTX_SYS_PASID together with the ATS enable and PASID valid bits. This
ensures the GPU context carries the system PASID state required for
address translation services.

Bspec: 67168

Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_lrc_layout.h |  6 ++++
 drivers/gpu/drm/xe/xe_lrc.c             | 37 +++++++++++++++++++++++++
 2 files changed, 43 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
index 6f7abc0181b5..9394e3d5aecb 100644
--- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
+++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
@@ -18,6 +18,7 @@
 #define CTX_TIMESTAMP_UDW		(0x24 + 1)
 #define CTX_INDIRECT_RING_STATE		(0x26 + 1)
 #define CTX_ACC_CTR_THOLD		(0x2a + 1)
+#define CTX_SYS_PASID			(0x2c + 1)
 #define CTX_ASID			(0x2e + 1)
 #define CTX_PDP0_UDW			(0x30 + 1)
 #define CTX_PDP0_LDW			(0x32 + 1)
@@ -45,4 +46,9 @@
 #define INDIRECT_CTX_RING_START_UDW	(0x08 + 1)
 #define INDIRECT_CTX_RING_CTL		(0x0a + 1)
 
+/* Fields for CTX_SYS_PASID */
+#define CTX_SYS_ATS_ENABLED                    REG_BIT(31)
+#define CTX_SYS_PASID_VALID                    REG_BIT(30)
+#define CTX_SYS_SYSTEM_PASID_MASK	       REG_GENMASK(19, 0)
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index de9a9560ecf3..a4f7f0492262 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -9,6 +9,7 @@
 
 #include <linux/ascii85.h>
 #include <linux/panic.h>
+#include <linux/pci.h>
 
 #include "instructions/xe_mi_commands.h"
 #include "instructions/xe_gfxpipe_commands.h"
@@ -35,6 +36,7 @@
 #include "xe_trace_lrc.h"
 #include "xe_vm.h"
 #include "xe_wa.h"
+#include "xe_pci.h"
 
 #define LRC_VALID				BIT_ULL(0)
 #define LRC_PRIVILEGE				BIT_ULL(8)
@@ -998,6 +1000,16 @@ void xe_lrc_write_ctx_reg(struct xe_lrc *lrc, int reg_nr, u32 val)
 	xe_map_write32(xe, &map, val);
 }
 
+static void xe_lrc_rmw_ctx_reg(struct xe_lrc *lrc,
+			       int reg_nr, u32 mask, u32 val)
+{
+	u32 oldval = xe_lrc_read_ctx_reg(lrc, reg_nr);
+	u32 newval = (oldval & ~mask) | (val & mask);
+
+	if (newval != oldval)
+		xe_lrc_write_ctx_reg(lrc, reg_nr, newval);
+}
+
 static void *empty_lrc_data(struct xe_hw_engine *hwe)
 {
 	struct xe_gt *gt = hwe->gt;
@@ -1493,6 +1505,26 @@ static u8 xe_multi_queue_prio_to_lrc(struct xe_lrc *lrc, enum xe_multi_queue_pri
 	return priority;
 }
 
+static void xe_lrc_program_ctx_sys_pasid(struct xe_lrc *lrc, struct xe_vm *vm)
+{
+	int pasid;
+	u32 mask = CTX_SYS_ATS_ENABLED | CTX_SYS_PASID_VALID |
+		   CTX_SYS_SYSTEM_PASID_MASK;
+	struct xe_device *xe = lrc_to_xe(lrc);
+
+	pasid = xe_vm_get_sva_pasid(vm);
+	/* PASID 0 is reserved by the IOMMU for non-PASID-capable devices. */
+	if (pasid <= 0)
+		return;
+
+	xe_lrc_rmw_ctx_reg(lrc, CTX_SYS_PASID, mask,
+			   CTX_SYS_ATS_ENABLED |
+			   CTX_SYS_PASID_VALID |
+			   (pasid & CTX_SYS_SYSTEM_PASID_MASK));
+	drm_dbg(&xe->drm, "LRC: context enabled with ATS and PASID=%d for VM %p and lrc %p\n",
+		pasid, vm, lrc);
+}
+
 /**
  * xe_lrc_set_multi_queue_priority() - Set multi queue priority in LRC
  * @lrc: Logical Ring Context
@@ -1542,6 +1574,7 @@ static int xe_lrc_ctx_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct
 	struct xe_gt *gt = hwe->gt;
 	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_device *xe = gt_to_xe(gt);
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	struct iosys_map map;
 	u32 arb_enable;
 	u32 state_cache_perf_fix[3];
@@ -1642,6 +1675,10 @@ static int xe_lrc_ctx_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct
 	if (GRAPHICS_VER(xe) >= 20 && hwe->class == XE_ENGINE_CLASS_RENDER)
 		xe_lrc_set_gpgpu_preemption_level(lrc, gt);
 
+	/* Program CTX_SYS_PASID when ATS and PASID is supported. */
+	if (xe_pci_ats_pasid_enabled(pdev))
+		xe_lrc_program_ctx_sys_pasid(lrc, vm);
+
 	lrc->desc = LRC_VALID;
 	lrc->desc |= FIELD_PREP(LRC_ADDRESSING_MODE, LRC_LEGACY_64B_CONTEXT);
 	/* TODO: Priority */
-- 
2.43.0