From: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: himal.prasad.ghimiray@intel.com,
Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
Subject: [PATCH 2/6] drm/xe/vm: Setup SVA infrastructure for PASID support
Date: Wed, 21 Oct 2026 09:41:13 +0530 [thread overview]
Message-ID: <20261021041117.1774877-3-naresh.kumar.g@intel.com> (raw)
In-Reply-To: <20261021041117.1774877-1-naresh.kumar.g@intel.com>
From: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Add sva_handle to struct xe_vm to represent the device-mm bond
established via iommu_sva_bind_device(). This handle will be used to
retrieve the PASID for SVM-enabled VMs
Introduce xe_vm_sva_bind() to bind the VM to the current process
address space using Shared Virtual Addressing(SVA) when ATS and
PASID are enabled on the device. This allows the GPU to shate the
same virtual address space as the CPU.
If sva binding fails, the VM continues without PASID support.
Also introduce a cleanup helper to unbind during VM teardown.
Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Signed-off-by: Nareshkumar Gollakoti <naresh.kumar.g@intel.com>
---
drivers/gpu/drm/xe/xe_vm.c | 40 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_vm_types.h | 6 +++++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 761bc136145f..b1d37e5a673f 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -45,6 +45,7 @@
#include "xe_trace_bo.h"
#include "xe_vm_madvise.h"
#include "xe_wa.h"
+#include "xe_pci.h"
static struct drm_gem_object *xe_vm_obj(struct xe_vm *vm)
{
@@ -1648,6 +1649,41 @@ static void xe_vm_init_prove_locking(struct xe_device *xe, struct xe_vm *vm)
up_read(&vm->exec_queues.lock);
}
+static void xe_vm_sva_handle_init(struct xe_vm *vm)
+{
+ struct device *dev = vm->xe->drm.dev;
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct iommu_sva *sva_handle;
+
+ /*
+ * Assumes the IOMMU driver has already decided and latched the
+ * device's ATS/PASID enablement by the time any VM is created (true
+ * for Intel VT-d, which enables both eagerly at IOMMU probe). If a
+ * backend instead enables them lazily on first SVA bind, this check
+ * will never see them set and SVA/PASID support is silently skipped.
+ */
+ if (!xe_pci_ats_pasid_enabled(pdev))
+ return;
+
+ sva_handle = iommu_sva_bind_device(dev, current->mm);
+ if (IS_ERR(sva_handle)) {
+ drm_err(&vm->xe->drm, "SVA binding failed, preventing PASID creation.\n");
+ return;
+ }
+
+ vm->sva_handle = sva_handle;
+}
+
+static void xe_vm_sva_handle_fini(struct xe_vm *vm)
+{
+ xe_assert(vm->xe, xe_vm_is_closed(vm));
+ if (!vm->sva_handle)
+ return;
+
+ iommu_sva_unbind_device(vm->sva_handle);
+ vm->sva_handle = NULL;
+}
+
struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
{
struct drm_gem_object *vm_resv_obj;
@@ -1994,6 +2030,7 @@ void xe_vm_close_and_put(struct xe_vm *vm)
xe_svm_fini(vm);
+ xe_vm_sva_handle_fini(vm);
up_write(&vm->lock);
down_write(&xe->usm.lock);
@@ -2159,6 +2196,9 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
if (IS_ERR(vm))
return PTR_ERR(vm);
+ if (flags & XE_VM_FLAG_FAULT_MODE)
+ xe_vm_sva_handle_init(vm);
+
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
/* Warning: Security issue - never enable by default */
args->reserved[0] = xe_bo_main_addr(vm->pt_root[0]->bo, XE_PAGE_SIZE);
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index fb9305124679..113807fa4ea0 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -11,6 +11,7 @@
#include <drm/drm_pagemap_util.h>
#include <linux/dma-resv.h>
+#include <linux/iommu.h>
#include <linux/kref.h>
#include <linux/mmu_notifier.h>
#include <linux/scatterlist.h>
@@ -423,6 +424,11 @@ struct xe_vm {
bool batch_invalidate_tlb;
/** @xef: Xe file handle for tracking this VM's drm client */
struct xe_file *xef;
+ /**
+ * @sva_handle: the sva_handle to a device-mm bond, populated using
+ * iommu_sva_bind_device(). To be used to determine pasid in case of svm vm.
+ */
+ struct iommu_sva *sva_handle;
};
/** struct xe_vma_op_map - VMA map operation */
--
2.43.0
next prev parent reply other threads:[~2026-10-21 4:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 4:11 [PATCH 0/6] ATS/PASID SVA support and PRI-less fault servicing Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 1/6] drm/xe/pci: log ATS/PASID enablement state at probe Nareshkumar Gollakoti
2026-10-21 4:32 ` sashiko-bot
2026-10-21 4:11 ` Nareshkumar Gollakoti [this message]
2026-10-21 4:30 ` [PATCH 2/6] drm/xe/vm: Setup SVA infrastructure for PASID support sashiko-bot
2026-10-21 4:11 ` [PATCH 3/6] drm/xe/vm: add helper to retrieve VM SVA PASID Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 4/6] drm/xe/lrc: program CTX_SYS_PASID for ATS/PASID-enabled contexts Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 5/6] drm/xe/pci: add helper for ATS/PASID without PRI Nareshkumar Gollakoti
2026-10-21 4:11 ` [PATCH 6/6] drm/xe/pagefault: add CPU mirror VMA for SVA faults " Nareshkumar Gollakoti
2026-10-21 4:35 ` sashiko-bot
2026-10-21 4:21 ` ✗ CI.KUnit: failure for ATS/PASID SVA support and PRI-less fault servicing Patchwork
2026-10-21 15:25 ` [PATCH 0/6] " Thomas Hellström
2026-10-22 6:30 ` Kumar G, Naresh
2026-10-22 11:12 ` Thomas Hellström
2026-10-21 21:24 ` Matthew Brost
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