Re: [PATCH 0/6] ATS/PASID SVA support and PRI-less fault servicing

["Thomas Hellström" <thomas.hellstrom@linux.intel.com>]

Hi!

On Wed, 2026-10-21 at 09:41 +0530, Nareshkumar Gollakoti wrote:
> This series adds initial Shared Virtual Addressing (SVA) support for
> xe
> on platforms where ATS and PASID are available but PRI is not enabled
> or
> not supported.
> 
> For SVA, the device must be able to issue memory transactions tagged
> with a PASID so that address translation is performed in the process
> address space rather than in a driver owned address space. This
> series
> adds the xe side infrastructure needed for that flow: VM support for
> SVA
> PASID state, PASID retriveal helpers, and programming of
> CTX_SYS_PASID
> for ATS and PASID enabled contexts.
> 
> On systems with PRI, device page faults can be surfaced and resolved
> through the hardware page request interface, so the driver does not
> need
> to implement a separate fault servicing path for SVA.
> On non PRI systems, that hardware assisted fault path is
> unavailable.In
> that case, the driver still needs a way to resolve faults against the
> backing process address space so execution can proceed.
> 
> To support that case, this series introduces a CPU mirror VMA and
> uses
> it as part of a driver managed SVM path for SVA faults without
> PRI.The
> purpose of the CPU mirror VMA is to provide a CPU side VMA
> representation for the address range being accesses through SVA,so
> the
> driver can rely on the kernel MM/VMA machinery to validate mappings
> and
> resolve backing pages for fault handling in the absence of PRI.In
> other words, since the device cannot issue PRI requests, the driver
> needs a CPU visible VMA context that mirrors the GPU SVA range
> closely
> enough to let faults be service through normal MM paths.
> 
> At a high level, this series does the following:
> 
>  1. log ATS/PASID enablement state during probe,
>  2. add VM infrastructure needed for SVA PASID support,
>  3. add a helper to retrieve the VM SVA PASID,
>  4. program CTX_SYS_PASID for ATS/PASID-enabled contexts,
>  5. add a PCI helper for ATS/PASID operation without PRI,
>  6. add a CPU mirror VMA for handling SVA faults on non PRI platforms
> 
> Patches 1-5 provide the ATS/PASID and VM/context plumbing needed for
> this flow and have been validated internally.Patch 6 adds the non PRI
> fault servicing path, and feedback on that overall approach would be
> especially appreciated.

I was under the impression that we'd integrate this with current SVM so
that we can still migrate to VRAM and use page-table mirroring or keep
data in system memory and use SVA page-table sharing *OR* page-table-
mirroring depending on user-space's wish?

Thanks,
Thomas


> 
> Himal Prasad Ghimiray (1):
>   drm/xe/vm: Setup SVA infrastructure for PASID support
> 
> Nareshkumar Gollakoti (5):
>   drm/xe/pci: log ATS/PASID enablement state at probe
>   drm/xe/vm: add helper to retrieve VM SVA PASID
>   drm/xe/lrc: program CTX_SYS_PASID for ATS/PASID-enabled contexts
>   drm/xe/pci: add helper for ATS/PASID without PRI
>   drm/xe/pagefault: add CPU mirror VMA for SVA faults without PRI
> 
>  drivers/gpu/drm/xe/regs/xe_lrc_layout.h |  6 +++
>  drivers/gpu/drm/xe/xe_lrc.c             | 37 ++++++++++++++++
>  drivers/gpu/drm/xe/xe_pagefault.c       | 49 ++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_pagefault_types.h |  6 +++
>  drivers/gpu/drm/xe/xe_pci.c             |  7 ++++
>  drivers/gpu/drm/xe/xe_pci.h             | 15 +++++++
>  drivers/gpu/drm/xe/xe_vm.c              | 56
> +++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_vm.h              |  2 +
>  drivers/gpu/drm/xe/xe_vm_types.h        |  6 +++
>  9 files changed, 184 insertions(+)