* [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface
@ 2026-01-15 11:33 Jani Nikula
2026-01-15 11:39 ` ✗ CI.checkpatch: warning for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2) Patchwork
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Jani Nikula @ 2026-01-15 11:33 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
Call the parent driver pcode functions through the parent interface
function pointers instead of expecting both to have functions of the
same name.
In i915, add the interface to existing intel_pcode.[ch], while in xe
move them to new display/xe_display_pcode.[ch] and build it only for
CONFIG_DRM_XE_DISPLAY=y.
Do not add separate write and write_timeout calls in the
interface. Instead, handle the default 1 ms timeout in the
intel_parent.c glue layer.
This drops the last intel_pcode.h includes from display, and allows us
to remove the corresponding xe compat header.
v2: initialize .pcode in i915
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 8 +--
drivers/gpu/drm/i915/display/intel_bw.c | 22 ++++----
drivers/gpu/drm/i915/display/intel_cdclk.c | 54 +++++++++----------
.../drm/i915/display/intel_display_power.c | 3 +-
.../i915/display/intel_display_power_well.c | 5 +-
drivers/gpu/drm/i915/display/intel_dram.c | 6 +--
drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
drivers/gpu/drm/i915/display/intel_parent.c | 22 ++++++++
drivers/gpu/drm/i915/display/intel_parent.h | 7 +++
drivers/gpu/drm/i915/display/skl_watermark.c | 21 ++++----
drivers/gpu/drm/i915/i915_driver.c | 1 +
drivers/gpu/drm/i915/intel_pcode.c | 16 ++++--
drivers/gpu/drm/i915/intel_pcode.h | 9 +---
drivers/gpu/drm/xe/Makefile | 1 +
| 11 ----
drivers/gpu/drm/xe/display/xe_display.c | 2 +
drivers/gpu/drm/xe/display/xe_display_pcode.c | 38 +++++++++++++
drivers/gpu/drm/xe/display/xe_display_pcode.h | 9 ++++
drivers/gpu/drm/xe/xe_pcode.c | 30 -----------
drivers/gpu/drm/xe/xe_pcode.h | 8 ---
include/drm/intel/display_parent_interface.h | 10 ++++
21 files changed, 161 insertions(+), 125 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
create mode 100644 drivers/gpu/drm/xe/display/xe_display_pcode.c
create mode 100644 drivers/gpu/drm/xe/display/xe_display_pcode.h
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 008d339d5c21..0caaea2e64e1 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -14,7 +14,7 @@
#include "intel_display_regs.h"
#include "intel_display_rpm.h"
#include "intel_display_types.h"
-#include "intel_pcode.h"
+#include "intel_parent.h"
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
{
@@ -39,8 +39,8 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
if (display->platform.broadwell) {
drm_WARN_ON(display->drm,
- intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,
- val | IPS_PCODE_CONTROL));
+ intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL,
+ val | IPS_PCODE_CONTROL));
/*
* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
@@ -72,7 +72,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
if (display->platform.broadwell) {
drm_WARN_ON(display->drm,
- intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));
+ intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 4ee3f5172f4e..8d84445c69f1 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -15,7 +15,7 @@
#include "intel_display_utils.h"
#include "intel_dram.h"
#include "intel_mchbar_regs.h"
-#include "intel_pcode.h"
+#include "intel_parent.h"
#include "intel_uncore.h"
#include "skl_watermark.h"
@@ -114,9 +114,9 @@ static int icl_pcode_read_qgv_point_info(struct intel_display *display,
u16 dclk;
int ret;
- ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
- &val, &val2);
+ ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
+ &val, &val2);
if (ret)
return ret;
@@ -141,8 +141,8 @@ static int adls_pcode_read_psf_gv_point_info(struct intel_display *display,
int ret;
int i;
- ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
+ ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
if (ret)
return ret;
@@ -189,11 +189,11 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display,
return 0;
/* bspec says to keep retrying for at least 1 ms */
- ret = intel_pcode_request(display->drm, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
- points_mask,
- ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
- ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
- 1);
+ ret = intel_parent_pcode_request(display, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
+ ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
+ 1);
if (ret < 0) {
drm_err(display->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9bfbfbf34dc0..9217050a76e0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -42,8 +42,8 @@
#include "intel_display_wa.h"
#include "intel_dram.h"
#include "intel_mchbar_regs.h"
+#include "intel_parent.h"
#include "intel_pci_config.h"
-#include "intel_pcode.h"
#include "intel_plane.h"
#include "intel_psr.h"
#include "intel_step.h"
@@ -888,7 +888,7 @@ static void bdw_set_cdclk(struct intel_display *display,
"trying to change cdclk frequency with cdclk not enabled\n"))
return;
- ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
+ ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
if (ret) {
drm_err(display->drm,
"failed to inform pcode about cdclk change\n");
@@ -918,8 +918,8 @@ static void bdw_set_cdclk(struct intel_display *display,
if (ret)
drm_err(display->drm, "Switching back to LCPLL failed\n");
- intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_config->voltage_level);
+ intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_config->voltage_level);
intel_de_write(display, CDCLK_FREQ,
DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1175,10 +1175,10 @@ static void skl_set_cdclk(struct intel_display *display,
drm_WARN_ON_ONCE(display->drm,
display->platform.skylake && vco == 8640000);
- ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
+ ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
if (ret) {
drm_err(display->drm,
"Failed to inform PCU about cdclk change (%d)\n", ret);
@@ -1221,8 +1221,8 @@ static void skl_set_cdclk(struct intel_display *display,
intel_de_posting_read(display, CDCLK_CTL);
/* inform PCU of the change */
- intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
- cdclk_config->voltage_level);
+ intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_config->voltage_level);
intel_update_cdclk(display);
}
@@ -2247,18 +2247,18 @@ static void bxt_set_cdclk(struct intel_display *display,
if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
; /* NOOP */
else if (DISPLAY_VER(display) >= 11)
- ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
+ ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
else
/*
* BSpec requires us to wait up to 150usec, but that leads to
* timeouts; the 2ms used here is based on experiment.
*/
- ret = intel_pcode_write_timeout(display->drm,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- 0x80000000, 2);
+ ret = intel_parent_pcode_write_timeout(display,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ 0x80000000, 2);
if (ret) {
drm_err(display->drm,
@@ -2287,8 +2287,8 @@ static void bxt_set_cdclk(struct intel_display *display,
* Display versions 14 and beyond
*/;
else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
- ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
- cdclk_config->voltage_level);
+ ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
+ cdclk_config->voltage_level);
if (DISPLAY_VER(display) < 11) {
/*
* The timeout isn't specified, the 2ms used here is based on
@@ -2296,9 +2296,9 @@ static void bxt_set_cdclk(struct intel_display *display,
* FIXME: Waiting for the request completion could be delayed
* until the next PCODE request based on BSpec.
*/
- ret = intel_pcode_write_timeout(display->drm,
- HSW_PCODE_DE_WRITE_FREQ_REQ,
- cdclk_config->voltage_level, 2);
+ ret = intel_parent_pcode_write_timeout(display,
+ HSW_PCODE_DE_WRITE_FREQ_REQ,
+ cdclk_config->voltage_level, 2);
}
if (ret) {
drm_err(display->drm,
@@ -2598,11 +2598,11 @@ static void intel_pcode_notify(struct intel_display *display,
if (pipe_count_update_valid)
update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
- ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE |
- update_mask,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
+ ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
+ SKL_CDCLK_PREPARE_FOR_CHANGE |
+ update_mask,
+ SKL_CDCLK_READY_FOR_CHANGE,
+ SKL_CDCLK_READY_FOR_CHANGE, 3);
if (ret)
drm_err(display->drm,
"Failed to inform PCU about display config (err %d)\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d27397f43863..06adf6afbec0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -26,7 +26,6 @@
#include "intel_mchbar_regs.h"
#include "intel_parent.h"
#include "intel_pch_refclk.h"
-#include "intel_pcode.h"
#include "intel_pmdemand.h"
#include "intel_pps_regs.h"
#include "intel_snps_phy.h"
@@ -1260,7 +1259,7 @@ static u32 hsw_read_dcomp(struct intel_display *display)
static void hsw_write_dcomp(struct intel_display *display, u32 val)
{
if (display->platform.haswell) {
- if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val))
+ if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val))
drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
} else {
intel_de_write(display, D_COMP_BDW, val);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index db185a859133..b01dda67986a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -27,7 +27,6 @@
#include "intel_dpll.h"
#include "intel_hotplug.h"
#include "intel_parent.h"
-#include "intel_pcode.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_tc.h"
@@ -522,7 +521,7 @@ static void icl_tc_cold_exit(struct intel_display *display)
int ret, tries = 0;
while (1) {
- ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0);
+ ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0);
if (ret != -EAGAIN || ++tries == 3)
break;
msleep(1);
@@ -1795,7 +1794,7 @@ tgl_tc_cold_request(struct intel_display *display, bool block)
* Spec states that we should timeout the request after 200us
* but the function below will timeout after 500us
*/
- ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val);
+ ret = intel_parent_pcode_read(display, TGL_PCODE_TCCOLD, &low_val, &high_val);
if (ret == 0) {
if (block &&
(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 170de304fe96..3b9879714ea9 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -13,7 +13,7 @@
#include "intel_display_utils.h"
#include "intel_dram.h"
#include "intel_mchbar_regs.h"
-#include "intel_pcode.h"
+#include "intel_parent.h"
#include "intel_uncore.h"
#include "vlv_iosf_sb.h"
@@ -692,8 +692,8 @@ static int icl_pcode_read_mem_global_info(struct intel_display *display,
u32 val = 0;
int ret;
- ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
- ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
+ ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
+ ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 7114fc405c29..8d3137067bf6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -33,7 +33,6 @@
#include "intel_hdcp_regs.h"
#include "intel_hdcp_shim.h"
#include "intel_parent.h"
-#include "intel_pcode.h"
#include "intel_step.h"
#define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14)
@@ -398,7 +397,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
* Mailbox interface.
*/
if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
- ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1);
+ ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1);
if (ret) {
drm_err(display->drm,
"Failed to initiate HDCP key load (%d)\n",
diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
index 72ae553f79a4..7f73695a0444 100644
--- a/drivers/gpu/drm/i915/display/intel_parent.c
+++ b/drivers/gpu/drm/i915/display/intel_parent.c
@@ -92,6 +92,28 @@ void intel_parent_pc8_unblock(struct intel_display *display)
display->parent->pc8->unblock(display->drm);
}
+/* pcode */
+int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1)
+{
+ return display->parent->pcode->read(display->drm, mbox, val, val1);
+}
+
+int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms)
+{
+ return display->parent->pcode->write(display->drm, mbox, val, timeout_ms);
+}
+
+int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val)
+{
+ return intel_parent_pcode_write_timeout(display, mbox, val, 1);
+}
+
+int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms)
+{
+ return display->parent->pcode->request(display->drm, mbox, request, reply_mask, reply, timeout_base_ms);
+}
+
/* rps */
bool intel_parent_rps_available(struct intel_display *display)
{
diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
index 47cdc14f9aa2..04782bb26b61 100644
--- a/drivers/gpu/drm/i915/display/intel_parent.h
+++ b/drivers/gpu/drm/i915/display/intel_parent.h
@@ -36,6 +36,13 @@ void intel_parent_panic_finish(struct intel_display *display, struct intel_panic
void intel_parent_pc8_block(struct intel_display *display);
void intel_parent_pc8_unblock(struct intel_display *display);
+/* pcode */
+int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1);
+int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms);
+int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val);
+int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms);
+
/* rps */
bool intel_parent_rps_available(struct intel_display *display);
void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index a6aab79812e5..b41da10f0f85 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -26,7 +26,7 @@
#include "intel_fb.h"
#include "intel_fixed.h"
#include "intel_flipq.h"
-#include "intel_pcode.h"
+#include "intel_parent.h"
#include "intel_plane.h"
#include "intel_vblank.h"
#include "intel_wm.h"
@@ -115,9 +115,8 @@ intel_sagv_block_time(struct intel_display *display)
u32 val = 0;
int ret;
- ret = intel_pcode_read(display->drm,
- GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
- &val, NULL);
+ ret = intel_parent_pcode_read(display, GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+ &val, NULL);
if (ret) {
drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n");
return 0;
@@ -184,8 +183,8 @@ static void skl_sagv_enable(struct intel_display *display)
return;
drm_dbg_kms(display->drm, "Enabling SAGV\n");
- ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL,
- GEN9_SAGV_ENABLE);
+ ret = intel_parent_pcode_write(display, GEN9_PCODE_SAGV_CONTROL,
+ GEN9_SAGV_ENABLE);
/* We don't need to wait for SAGV when enabling */
@@ -217,9 +216,9 @@ static void skl_sagv_disable(struct intel_display *display)
drm_dbg_kms(display->drm, "Disabling SAGV\n");
/* bspec says to keep retrying for at least 1 ms */
- ret = intel_pcode_request(display->drm, GEN9_PCODE_SAGV_CONTROL,
- GEN9_SAGV_DISABLE,
- GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1);
+ ret = intel_parent_pcode_request(display, GEN9_PCODE_SAGV_CONTROL,
+ GEN9_SAGV_DISABLE,
+ GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1);
/*
* Some skl systems, pre-release machines in particular,
* don't actually have SAGV.
@@ -3283,7 +3282,7 @@ static void skl_read_wm_latency(struct intel_display *display)
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
- ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
+ ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
if (ret) {
drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
return;
@@ -3296,7 +3295,7 @@ static void skl_read_wm_latency(struct intel_display *display)
/* read the second set of memory latencies[4:7] */
val = 1; /* data0 to be programmed to 1 for second set */
- ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
+ ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
if (ret) {
drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
return;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f0105c5b49a7..b01d8fdea548 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -769,6 +769,7 @@ static const struct intel_display_parent_interface parent = {
.irq = &i915_display_irq_interface,
.panic = &i915_display_panic_interface,
.pc8 = &i915_display_pc8_interface,
+ .pcode = &i915_display_pcode_interface,
.rpm = &i915_display_rpm_interface,
.rps = &i915_display_rps_interface,
.stolen = &i915_display_stolen_interface,
diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
index 756652b8ec97..76c5916b28f4 100644
--- a/drivers/gpu/drm/i915/intel_pcode.c
+++ b/drivers/gpu/drm/i915/intel_pcode.c
@@ -4,6 +4,7 @@
*/
#include <drm/drm_print.h>
+#include <drm/intel/display_parent_interface.h>
#include "i915_drv.h"
#include "i915_reg.h"
@@ -276,26 +277,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
return err;
}
-/* Helpers with drm device */
-int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
+static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
{
struct drm_i915_private *i915 = to_i915(drm);
return snb_pcode_read(&i915->uncore, mbox, val, val1);
}
-int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
+static int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
{
struct drm_i915_private *i915 = to_i915(drm);
return snb_pcode_write_timeout(&i915->uncore, mbox, val, timeout_ms);
}
-int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms)
+static int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms)
{
struct drm_i915_private *i915 = to_i915(drm);
return skl_pcode_request(&i915->uncore, mbox, request, reply_mask, reply,
timeout_base_ms);
}
+
+const struct intel_display_pcode_interface i915_display_pcode_interface = {
+ .read = intel_pcode_read,
+ .write = intel_pcode_write_timeout,
+ .request = intel_pcode_request,
+};
diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
index c91a821a88d4..19795ea8172e 100644
--- a/drivers/gpu/drm/i915/intel_pcode.h
+++ b/drivers/gpu/drm/i915/intel_pcode.h
@@ -27,13 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
-/* Helpers with drm device */
-int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
-int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
-#define intel_pcode_write(drm, mbox, val) \
- intel_pcode_write_timeout((drm), (mbox), (val), 1)
-
-int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms);
+extern const struct intel_display_pcode_interface i915_display_pcode_interface;
#endif /* _INTEL_PCODE_H */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b39cbb756232..51a9a531fb7e 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -213,6 +213,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
display/intel_fb_bo.o \
display/intel_fbdev_fb.o \
display/xe_display.o \
+ display/xe_display_pcode.o \
display/xe_display_rpm.o \
display/xe_display_wa.o \
display/xe_dsb_buffer.o \
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
deleted file mode 100644
index 4fcd3bf6b76f..000000000000
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef __INTEL_PCODE_H__
-#define __INTEL_PCODE_H__
-
-#include "xe_pcode.h"
-
-#endif /* __INTEL_PCODE_H__ */
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index f8a831b5dc7d..182facce30ab 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -35,6 +35,7 @@
#include "intel_hotplug.h"
#include "intel_opregion.h"
#include "skl_watermark.h"
+#include "xe_display_pcode.h"
#include "xe_display_rpm.h"
#include "xe_hdcp_gsc.h"
#include "xe_initial_plane.h"
@@ -542,6 +543,7 @@ static const struct intel_display_parent_interface parent = {
.initial_plane = &xe_display_initial_plane_interface,
.irq = &xe_display_irq_interface,
.panic = &xe_display_panic_interface,
+ .pcode = &xe_display_pcode_interface,
.rpm = &xe_display_rpm_interface,
.stolen = &xe_display_stolen_interface,
};
diff --git a/drivers/gpu/drm/xe/display/xe_display_pcode.c b/drivers/gpu/drm/xe/display/xe_display_pcode.c
new file mode 100644
index 000000000000..f6820ef7e666
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/xe_display_pcode.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: MIT
+/* Copyright © 2026 Intel Corporation */
+
+#include <drm/intel/display_parent_interface.h>
+
+#include "xe_device.h"
+#include "xe_pcode.h"
+
+static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
+{
+ struct xe_device *xe = to_xe_device(drm);
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
+
+ return xe_pcode_read(tile, mbox, val, val1);
+}
+
+static int xe_display_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
+{
+ struct xe_device *xe = to_xe_device(drm);
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
+
+ return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);
+}
+
+static int xe_display_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms)
+{
+ struct xe_device *xe = to_xe_device(drm);
+ struct xe_tile *tile = xe_device_get_root_tile(xe);
+
+ return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);
+}
+
+const struct intel_display_pcode_interface xe_display_pcode_interface = {
+ .read = xe_display_pcode_read,
+ .write = xe_display_pcode_write_timeout,
+ .request = xe_display_pcode_request,
+};
diff --git a/drivers/gpu/drm/xe/display/xe_display_pcode.h b/drivers/gpu/drm/xe/display/xe_display_pcode.h
new file mode 100644
index 000000000000..58bd2fb7fb79
--- /dev/null
+++ b/drivers/gpu/drm/xe/display/xe_display_pcode.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef __XE_DISPLAY_PCODE_H__
+#define __XE_DISPLAY_PCODE_H__
+
+extern const struct intel_display_pcode_interface xe_display_pcode_interface;
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
index 0d33c14ea0cf..dc66d0c7ee06 100644
--- a/drivers/gpu/drm/xe/xe_pcode.c
+++ b/drivers/gpu/drm/xe/xe_pcode.c
@@ -348,33 +348,3 @@ int xe_pcode_probe_early(struct xe_device *xe)
return xe_pcode_ready(xe, false);
}
ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */
-
-/* Helpers with drm device. These should only be called by the display side */
-#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
-
-int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
-{
- struct xe_device *xe = to_xe_device(drm);
- struct xe_tile *tile = xe_device_get_root_tile(xe);
-
- return xe_pcode_read(tile, mbox, val, val1);
-}
-
-int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
-{
- struct xe_device *xe = to_xe_device(drm);
- struct xe_tile *tile = xe_device_get_root_tile(xe);
-
- return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);
-}
-
-int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms)
-{
- struct xe_device *xe = to_xe_device(drm);
- struct xe_tile *tile = xe_device_get_root_tile(xe);
-
- return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);
-}
-
-#endif
diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h
index a5584c1c75f9..490e4f269607 100644
--- a/drivers/gpu/drm/xe/xe_pcode.h
+++ b/drivers/gpu/drm/xe/xe_pcode.h
@@ -34,12 +34,4 @@ int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
| FIELD_PREP(PCODE_MB_PARAM1, param1)\
| FIELD_PREP(PCODE_MB_PARAM2, param2))
-/* Helpers with drm device */
-int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
-int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
-#define intel_pcode_write(drm, mbox, val) \
- intel_pcode_write_timeout((drm), (mbox), (val), 1)
-int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms);
-
#endif
diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h
index ce946859a3a9..78f4e6744f18 100644
--- a/include/drm/intel/display_parent_interface.h
+++ b/include/drm/intel/display_parent_interface.h
@@ -55,6 +55,13 @@ struct intel_display_pc8_interface {
void (*unblock)(struct drm_device *drm);
};
+struct intel_display_pcode_interface {
+ int (*read)(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
+ int (*write)(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
+ int (*request)(struct drm_device *drm, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms);
+};
+
struct intel_display_rpm_interface {
struct ref_tracker *(*get)(const struct drm_device *drm);
struct ref_tracker *(*get_raw)(const struct drm_device *drm);
@@ -121,6 +128,9 @@ struct intel_display_parent_interface {
/** @pc8: PC8 interface. Optional. */
const struct intel_display_pc8_interface *pc8;
+ /** @pcode: Pcode interface */
+ const struct intel_display_pcode_interface *pcode;
+
/** @rpm: Runtime PM functions */
const struct intel_display_rpm_interface *rpm;
--
2.47.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ CI.checkpatch: warning for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
2026-01-15 11:33 [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Jani Nikula
@ 2026-01-15 11:39 ` Patchwork
2026-01-15 11:40 ` ✓ CI.KUnit: success " Patchwork
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-01-15 11:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
URL : https://patchwork.freedesktop.org/series/159877/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
ee83616c430ce70bd254bd2774d143a5733c8666
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 3c39cdd074034ba6f5494370750cf6020f3a41ce
Author: Jani Nikula <jani.nikula@intel.com>
Date: Thu Jan 15 13:33:37 2026 +0200
drm/{i915, xe}/pcode: move display pcode calls to parent interface
Call the parent driver pcode functions through the parent interface
function pointers instead of expecting both to have functions of the
same name.
In i915, add the interface to existing intel_pcode.[ch], while in xe
move them to new display/xe_display_pcode.[ch] and build it only for
CONFIG_DRM_XE_DISPLAY=y.
Do not add separate write and write_timeout calls in the
interface. Instead, handle the default 1 ms timeout in the
intel_parent.c glue layer.
This drops the last intel_pcode.h includes from display, and allows us
to remove the corresponding xe compat header.
v2: initialize .pcode in i915
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 733664f1edf3c01cc68e6dd0bbdb135158a98a1d drm-intel
3c39cdd07403 drm/{i915, xe}/pcode: move display pcode calls to parent interface
-:350: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#350: FILE: drivers/gpu/drm/i915/display/intel_parent.c:101:
+int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms)
-:363: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#363: FILE: drivers/gpu/drm/i915/display/intel_parent.c:114:
+ return display->parent->pcode->request(display->drm, mbox, request, reply_mask, reply, timeout_base_ms);
-:379: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#379: FILE: drivers/gpu/drm/i915/display/intel_parent.h:41:
+int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms);
-:547: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#547:
deleted file mode 100644
total: 0 errors, 4 warnings, 0 checks, 524 lines checked
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ CI.KUnit: success for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
2026-01-15 11:33 [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Jani Nikula
2026-01-15 11:39 ` ✗ CI.checkpatch: warning for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2) Patchwork
@ 2026-01-15 11:40 ` Patchwork
2026-01-15 12:15 ` ✓ Xe.CI.BAT: " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-01-15 11:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
URL : https://patchwork.freedesktop.org/series/159877/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:39:12] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:39:48] Starting KUnit Kernel (1/1)...
[11:39:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:39:48] ================== guc_buf (11 subtests) ===================
[11:39:48] [PASSED] test_smallest
[11:39:48] [PASSED] test_largest
[11:39:48] [PASSED] test_granular
[11:39:48] [PASSED] test_unique
[11:39:48] [PASSED] test_overlap
[11:39:48] [PASSED] test_reusable
[11:39:48] [PASSED] test_too_big
[11:39:48] [PASSED] test_flush
[11:39:48] [PASSED] test_lookup
[11:39:48] [PASSED] test_data
[11:39:48] [PASSED] test_class
[11:39:48] ===================== [PASSED] guc_buf =====================
[11:39:48] =================== guc_dbm (7 subtests) ===================
[11:39:48] [PASSED] test_empty
[11:39:48] [PASSED] test_default
[11:39:48] ======================== test_size ========================
[11:39:48] [PASSED] 4
[11:39:48] [PASSED] 8
[11:39:48] [PASSED] 32
[11:39:48] [PASSED] 256
[11:39:48] ==================== [PASSED] test_size ====================
[11:39:48] ======================= test_reuse ========================
[11:39:48] [PASSED] 4
[11:39:48] [PASSED] 8
[11:39:48] [PASSED] 32
[11:39:48] [PASSED] 256
[11:39:48] =================== [PASSED] test_reuse ====================
[11:39:48] =================== test_range_overlap ====================
[11:39:48] [PASSED] 4
[11:39:48] [PASSED] 8
[11:39:48] [PASSED] 32
[11:39:48] [PASSED] 256
[11:39:48] =============== [PASSED] test_range_overlap ================
[11:39:48] =================== test_range_compact ====================
[11:39:48] [PASSED] 4
[11:39:48] [PASSED] 8
[11:39:48] [PASSED] 32
[11:39:48] [PASSED] 256
[11:39:48] =============== [PASSED] test_range_compact ================
[11:39:48] ==================== test_range_spare =====================
[11:39:48] [PASSED] 4
[11:39:48] [PASSED] 8
[11:39:48] [PASSED] 32
[11:39:48] [PASSED] 256
[11:39:48] ================ [PASSED] test_range_spare =================
[11:39:48] ===================== [PASSED] guc_dbm =====================
[11:39:48] =================== guc_idm (6 subtests) ===================
[11:39:48] [PASSED] bad_init
[11:39:48] [PASSED] no_init
[11:39:48] [PASSED] init_fini
[11:39:48] [PASSED] check_used
[11:39:48] [PASSED] check_quota
[11:39:48] [PASSED] check_all
[11:39:48] ===================== [PASSED] guc_idm =====================
[11:39:48] ================== no_relay (3 subtests) ===================
[11:39:48] [PASSED] xe_drops_guc2pf_if_not_ready
[11:39:48] [PASSED] xe_drops_guc2vf_if_not_ready
[11:39:48] [PASSED] xe_rejects_send_if_not_ready
[11:39:48] ==================== [PASSED] no_relay =====================
[11:39:48] ================== pf_relay (14 subtests) ==================
[11:39:48] [PASSED] pf_rejects_guc2pf_too_short
[11:39:48] [PASSED] pf_rejects_guc2pf_too_long
[11:39:48] [PASSED] pf_rejects_guc2pf_no_payload
[11:39:48] [PASSED] pf_fails_no_payload
[11:39:48] [PASSED] pf_fails_bad_origin
[11:39:48] [PASSED] pf_fails_bad_type
[11:39:48] [PASSED] pf_txn_reports_error
[11:39:48] [PASSED] pf_txn_sends_pf2guc
[11:39:48] [PASSED] pf_sends_pf2guc
[11:39:48] [SKIPPED] pf_loopback_nop
[11:39:48] [SKIPPED] pf_loopback_echo
[11:39:48] [SKIPPED] pf_loopback_fail
[11:39:48] [SKIPPED] pf_loopback_busy
[11:39:48] [SKIPPED] pf_loopback_retry
[11:39:48] ==================== [PASSED] pf_relay =====================
[11:39:48] ================== vf_relay (3 subtests) ===================
[11:39:48] [PASSED] vf_rejects_guc2vf_too_short
[11:39:48] [PASSED] vf_rejects_guc2vf_too_long
[11:39:48] [PASSED] vf_rejects_guc2vf_no_payload
[11:39:48] ==================== [PASSED] vf_relay =====================
[11:39:48] ================ pf_gt_config (6 subtests) =================
[11:39:48] [PASSED] fair_contexts_1vf
[11:39:48] [PASSED] fair_doorbells_1vf
[11:39:48] [PASSED] fair_ggtt_1vf
[11:39:48] ====================== fair_contexts ======================
[11:39:48] [PASSED] 1 VF
[11:39:48] [PASSED] 2 VFs
[11:39:48] [PASSED] 3 VFs
[11:39:48] [PASSED] 4 VFs
[11:39:48] [PASSED] 5 VFs
[11:39:48] [PASSED] 6 VFs
[11:39:48] [PASSED] 7 VFs
[11:39:48] [PASSED] 8 VFs
[11:39:48] [PASSED] 9 VFs
[11:39:48] [PASSED] 10 VFs
[11:39:48] [PASSED] 11 VFs
[11:39:48] [PASSED] 12 VFs
[11:39:48] [PASSED] 13 VFs
[11:39:48] [PASSED] 14 VFs
[11:39:48] [PASSED] 15 VFs
[11:39:48] [PASSED] 16 VFs
[11:39:48] [PASSED] 17 VFs
[11:39:48] [PASSED] 18 VFs
[11:39:48] [PASSED] 19 VFs
[11:39:48] [PASSED] 20 VFs
[11:39:48] [PASSED] 21 VFs
[11:39:48] [PASSED] 22 VFs
[11:39:48] [PASSED] 23 VFs
[11:39:48] [PASSED] 24 VFs
[11:39:48] [PASSED] 25 VFs
[11:39:48] [PASSED] 26 VFs
[11:39:48] [PASSED] 27 VFs
[11:39:48] [PASSED] 28 VFs
[11:39:48] [PASSED] 29 VFs
[11:39:48] [PASSED] 30 VFs
[11:39:48] [PASSED] 31 VFs
[11:39:48] [PASSED] 32 VFs
[11:39:48] [PASSED] 33 VFs
[11:39:48] [PASSED] 34 VFs
[11:39:48] [PASSED] 35 VFs
[11:39:48] [PASSED] 36 VFs
[11:39:48] [PASSED] 37 VFs
[11:39:48] [PASSED] 38 VFs
[11:39:48] [PASSED] 39 VFs
[11:39:48] [PASSED] 40 VFs
[11:39:48] [PASSED] 41 VFs
[11:39:48] [PASSED] 42 VFs
[11:39:48] [PASSED] 43 VFs
[11:39:48] [PASSED] 44 VFs
[11:39:48] [PASSED] 45 VFs
[11:39:48] [PASSED] 46 VFs
[11:39:48] [PASSED] 47 VFs
[11:39:48] [PASSED] 48 VFs
[11:39:48] [PASSED] 49 VFs
[11:39:48] [PASSED] 50 VFs
[11:39:48] [PASSED] 51 VFs
[11:39:48] [PASSED] 52 VFs
[11:39:48] [PASSED] 53 VFs
[11:39:48] [PASSED] 54 VFs
[11:39:48] [PASSED] 55 VFs
[11:39:48] [PASSED] 56 VFs
[11:39:48] [PASSED] 57 VFs
[11:39:48] [PASSED] 58 VFs
[11:39:48] [PASSED] 59 VFs
[11:39:48] [PASSED] 60 VFs
[11:39:48] [PASSED] 61 VFs
[11:39:48] [PASSED] 62 VFs
[11:39:48] [PASSED] 63 VFs
[11:39:48] ================== [PASSED] fair_contexts ==================
[11:39:48] ===================== fair_doorbells ======================
[11:39:48] [PASSED] 1 VF
[11:39:48] [PASSED] 2 VFs
[11:39:48] [PASSED] 3 VFs
[11:39:48] [PASSED] 4 VFs
[11:39:48] [PASSED] 5 VFs
[11:39:48] [PASSED] 6 VFs
[11:39:48] [PASSED] 7 VFs
[11:39:48] [PASSED] 8 VFs
[11:39:48] [PASSED] 9 VFs
[11:39:48] [PASSED] 10 VFs
[11:39:48] [PASSED] 11 VFs
[11:39:48] [PASSED] 12 VFs
[11:39:48] [PASSED] 13 VFs
[11:39:48] [PASSED] 14 VFs
[11:39:48] [PASSED] 15 VFs
[11:39:48] [PASSED] 16 VFs
[11:39:48] [PASSED] 17 VFs
[11:39:48] [PASSED] 18 VFs
[11:39:48] [PASSED] 19 VFs
[11:39:48] [PASSED] 20 VFs
[11:39:48] [PASSED] 21 VFs
[11:39:48] [PASSED] 22 VFs
[11:39:48] [PASSED] 23 VFs
[11:39:48] [PASSED] 24 VFs
[11:39:48] [PASSED] 25 VFs
[11:39:48] [PASSED] 26 VFs
[11:39:48] [PASSED] 27 VFs
[11:39:48] [PASSED] 28 VFs
[11:39:48] [PASSED] 29 VFs
[11:39:48] [PASSED] 30 VFs
[11:39:48] [PASSED] 31 VFs
[11:39:48] [PASSED] 32 VFs
[11:39:48] [PASSED] 33 VFs
[11:39:48] [PASSED] 34 VFs
[11:39:48] [PASSED] 35 VFs
[11:39:48] [PASSED] 36 VFs
[11:39:48] [PASSED] 37 VFs
[11:39:48] [PASSED] 38 VFs
[11:39:48] [PASSED] 39 VFs
[11:39:48] [PASSED] 40 VFs
[11:39:48] [PASSED] 41 VFs
[11:39:48] [PASSED] 42 VFs
[11:39:48] [PASSED] 43 VFs
[11:39:48] [PASSED] 44 VFs
[11:39:48] [PASSED] 45 VFs
[11:39:48] [PASSED] 46 VFs
[11:39:48] [PASSED] 47 VFs
[11:39:48] [PASSED] 48 VFs
[11:39:48] [PASSED] 49 VFs
[11:39:48] [PASSED] 50 VFs
[11:39:48] [PASSED] 51 VFs
[11:39:48] [PASSED] 52 VFs
[11:39:48] [PASSED] 53 VFs
[11:39:48] [PASSED] 54 VFs
[11:39:48] [PASSED] 55 VFs
[11:39:48] [PASSED] 56 VFs
[11:39:48] [PASSED] 57 VFs
[11:39:48] [PASSED] 58 VFs
[11:39:48] [PASSED] 59 VFs
[11:39:48] [PASSED] 60 VFs
[11:39:48] [PASSED] 61 VFs
[11:39:48] [PASSED] 62 VFs
[11:39:48] [PASSED] 63 VFs
[11:39:48] ================= [PASSED] fair_doorbells ==================
[11:39:48] ======================== fair_ggtt ========================
[11:39:48] [PASSED] 1 VF
[11:39:48] [PASSED] 2 VFs
[11:39:48] [PASSED] 3 VFs
[11:39:48] [PASSED] 4 VFs
[11:39:48] [PASSED] 5 VFs
[11:39:48] [PASSED] 6 VFs
[11:39:48] [PASSED] 7 VFs
[11:39:48] [PASSED] 8 VFs
[11:39:48] [PASSED] 9 VFs
[11:39:48] [PASSED] 10 VFs
[11:39:48] [PASSED] 11 VFs
[11:39:48] [PASSED] 12 VFs
[11:39:48] [PASSED] 13 VFs
[11:39:48] [PASSED] 14 VFs
[11:39:48] [PASSED] 15 VFs
[11:39:48] [PASSED] 16 VFs
[11:39:48] [PASSED] 17 VFs
[11:39:48] [PASSED] 18 VFs
[11:39:48] [PASSED] 19 VFs
[11:39:48] [PASSED] 20 VFs
[11:39:48] [PASSED] 21 VFs
[11:39:48] [PASSED] 22 VFs
[11:39:48] [PASSED] 23 VFs
[11:39:48] [PASSED] 24 VFs
[11:39:48] [PASSED] 25 VFs
[11:39:48] [PASSED] 26 VFs
[11:39:48] [PASSED] 27 VFs
[11:39:48] [PASSED] 28 VFs
[11:39:48] [PASSED] 29 VFs
[11:39:48] [PASSED] 30 VFs
[11:39:48] [PASSED] 31 VFs
[11:39:48] [PASSED] 32 VFs
[11:39:48] [PASSED] 33 VFs
[11:39:48] [PASSED] 34 VFs
[11:39:48] [PASSED] 35 VFs
[11:39:48] [PASSED] 36 VFs
[11:39:48] [PASSED] 37 VFs
[11:39:48] [PASSED] 38 VFs
[11:39:48] [PASSED] 39 VFs
[11:39:48] [PASSED] 40 VFs
[11:39:48] [PASSED] 41 VFs
[11:39:48] [PASSED] 42 VFs
[11:39:48] [PASSED] 43 VFs
[11:39:48] [PASSED] 44 VFs
[11:39:48] [PASSED] 45 VFs
[11:39:48] [PASSED] 46 VFs
[11:39:48] [PASSED] 47 VFs
[11:39:48] [PASSED] 48 VFs
[11:39:48] [PASSED] 49 VFs
[11:39:48] [PASSED] 50 VFs
[11:39:48] [PASSED] 51 VFs
[11:39:48] [PASSED] 52 VFs
[11:39:48] [PASSED] 53 VFs
[11:39:48] [PASSED] 54 VFs
[11:39:48] [PASSED] 55 VFs
[11:39:48] [PASSED] 56 VFs
[11:39:48] [PASSED] 57 VFs
[11:39:48] [PASSED] 58 VFs
[11:39:48] [PASSED] 59 VFs
[11:39:48] [PASSED] 60 VFs
[11:39:48] [PASSED] 61 VFs
[11:39:48] [PASSED] 62 VFs
[11:39:48] [PASSED] 63 VFs
[11:39:48] ==================== [PASSED] fair_ggtt ====================
[11:39:48] ================== [PASSED] pf_gt_config ===================
[11:39:48] ===================== lmtt (1 subtest) =====================
[11:39:48] ======================== test_ops =========================
[11:39:48] [PASSED] 2-level
[11:39:48] [PASSED] multi-level
[11:39:48] ==================== [PASSED] test_ops =====================
[11:39:48] ====================== [PASSED] lmtt =======================
[11:39:48] ================= pf_service (11 subtests) =================
[11:39:48] [PASSED] pf_negotiate_any
[11:39:48] [PASSED] pf_negotiate_base_match
[11:39:48] [PASSED] pf_negotiate_base_newer
[11:39:48] [PASSED] pf_negotiate_base_next
[11:39:48] [SKIPPED] pf_negotiate_base_older
[11:39:48] [PASSED] pf_negotiate_base_prev
[11:39:48] [PASSED] pf_negotiate_latest_match
[11:39:48] [PASSED] pf_negotiate_latest_newer
[11:39:48] [PASSED] pf_negotiate_latest_next
[11:39:48] [SKIPPED] pf_negotiate_latest_older
[11:39:48] [SKIPPED] pf_negotiate_latest_prev
[11:39:48] =================== [PASSED] pf_service ====================
[11:39:48] ================= xe_guc_g2g (2 subtests) ==================
[11:39:48] ============== xe_live_guc_g2g_kunit_default ==============
[11:39:48] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:39:48] ============== xe_live_guc_g2g_kunit_allmem ===============
[11:39:48] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:39:48] =================== [SKIPPED] xe_guc_g2g ===================
[11:39:48] =================== xe_mocs (2 subtests) ===================
[11:39:48] ================ xe_live_mocs_kernel_kunit ================
[11:39:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:39:48] ================ xe_live_mocs_reset_kunit =================
[11:39:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:39:48] ==================== [SKIPPED] xe_mocs =====================
[11:39:48] ================= xe_migrate (2 subtests) ==================
[11:39:48] ================= xe_migrate_sanity_kunit =================
[11:39:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:39:48] ================== xe_validate_ccs_kunit ==================
[11:39:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:39:48] =================== [SKIPPED] xe_migrate ===================
[11:39:48] ================== xe_dma_buf (1 subtest) ==================
[11:39:48] ==================== xe_dma_buf_kunit =====================
[11:39:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:39:48] =================== [SKIPPED] xe_dma_buf ===================
[11:39:48] ================= xe_bo_shrink (1 subtest) =================
[11:39:48] =================== xe_bo_shrink_kunit ====================
[11:39:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:39:48] ================== [SKIPPED] xe_bo_shrink ==================
[11:39:48] ==================== xe_bo (2 subtests) ====================
[11:39:48] ================== xe_ccs_migrate_kunit ===================
[11:39:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:39:48] ==================== xe_bo_evict_kunit ====================
[11:39:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:39:48] ===================== [SKIPPED] xe_bo ======================
[11:39:48] ==================== args (13 subtests) ====================
[11:39:48] [PASSED] count_args_test
[11:39:48] [PASSED] call_args_example
[11:39:48] [PASSED] call_args_test
[11:39:48] [PASSED] drop_first_arg_example
[11:39:48] [PASSED] drop_first_arg_test
[11:39:48] [PASSED] first_arg_example
[11:39:48] [PASSED] first_arg_test
[11:39:48] [PASSED] last_arg_example
[11:39:48] [PASSED] last_arg_test
[11:39:48] [PASSED] pick_arg_example
[11:39:48] [PASSED] if_args_example
[11:39:48] [PASSED] if_args_test
[11:39:48] [PASSED] sep_comma_example
[11:39:48] ====================== [PASSED] args =======================
[11:39:48] =================== xe_pci (3 subtests) ====================
[11:39:48] ==================== check_graphics_ip ====================
[11:39:48] [PASSED] 12.00 Xe_LP
[11:39:48] [PASSED] 12.10 Xe_LP+
[11:39:48] [PASSED] 12.55 Xe_HPG
[11:39:48] [PASSED] 12.60 Xe_HPC
[11:39:48] [PASSED] 12.70 Xe_LPG
[11:39:48] [PASSED] 12.71 Xe_LPG
[11:39:48] [PASSED] 12.74 Xe_LPG+
[11:39:48] [PASSED] 20.01 Xe2_HPG
[11:39:48] [PASSED] 20.02 Xe2_HPG
[11:39:48] [PASSED] 20.04 Xe2_LPG
[11:39:48] [PASSED] 30.00 Xe3_LPG
[11:39:48] [PASSED] 30.01 Xe3_LPG
[11:39:48] [PASSED] 30.03 Xe3_LPG
[11:39:48] [PASSED] 30.04 Xe3_LPG
[11:39:48] [PASSED] 30.05 Xe3_LPG
[11:39:48] [PASSED] 35.11 Xe3p_XPC
[11:39:48] ================ [PASSED] check_graphics_ip ================
[11:39:48] ===================== check_media_ip ======================
[11:39:48] [PASSED] 12.00 Xe_M
[11:39:48] [PASSED] 12.55 Xe_HPM
[11:39:48] [PASSED] 13.00 Xe_LPM+
[11:39:48] [PASSED] 13.01 Xe2_HPM
[11:39:48] [PASSED] 20.00 Xe2_LPM
[11:39:48] [PASSED] 30.00 Xe3_LPM
[11:39:48] [PASSED] 30.02 Xe3_LPM
[11:39:48] [PASSED] 35.00 Xe3p_LPM
[11:39:48] [PASSED] 35.03 Xe3p_HPM
[11:39:48] ================= [PASSED] check_media_ip ==================
[11:39:48] =================== check_platform_desc ===================
[11:39:48] [PASSED] 0x9A60 (TIGERLAKE)
[11:39:48] [PASSED] 0x9A68 (TIGERLAKE)
[11:39:48] [PASSED] 0x9A70 (TIGERLAKE)
[11:39:48] [PASSED] 0x9A40 (TIGERLAKE)
[11:39:48] [PASSED] 0x9A49 (TIGERLAKE)
[11:39:48] [PASSED] 0x9A59 (TIGERLAKE)
[11:39:48] [PASSED] 0x9A78 (TIGERLAKE)
[11:39:48] [PASSED] 0x9AC0 (TIGERLAKE)
[11:39:48] [PASSED] 0x9AC9 (TIGERLAKE)
[11:39:48] [PASSED] 0x9AD9 (TIGERLAKE)
[11:39:48] [PASSED] 0x9AF8 (TIGERLAKE)
[11:39:48] [PASSED] 0x4C80 (ROCKETLAKE)
[11:39:48] [PASSED] 0x4C8A (ROCKETLAKE)
[11:39:48] [PASSED] 0x4C8B (ROCKETLAKE)
[11:39:48] [PASSED] 0x4C8C (ROCKETLAKE)
[11:39:48] [PASSED] 0x4C90 (ROCKETLAKE)
[11:39:48] [PASSED] 0x4C9A (ROCKETLAKE)
[11:39:48] [PASSED] 0x4680 (ALDERLAKE_S)
[11:39:48] [PASSED] 0x4682 (ALDERLAKE_S)
[11:39:48] [PASSED] 0x4688 (ALDERLAKE_S)
[11:39:48] [PASSED] 0x468A (ALDERLAKE_S)
[11:39:48] [PASSED] 0x468B (ALDERLAKE_S)
[11:39:48] [PASSED] 0x4690 (ALDERLAKE_S)
[11:39:48] [PASSED] 0x4692 (ALDERLAKE_S)
[11:39:48] [PASSED] 0x4693 (ALDERLAKE_S)
[11:39:48] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46AA (ALDERLAKE_P)
[11:39:48] [PASSED] 0x462A (ALDERLAKE_P)
[11:39:48] [PASSED] 0x4626 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[11:39:48] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:39:48] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:39:48] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:39:48] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:39:48] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:39:48] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:39:48] [PASSED] 0xA721 (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA720 (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:39:48] [PASSED] 0xA780 (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA781 (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA782 (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA783 (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA788 (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA789 (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA78A (ALDERLAKE_S)
[11:39:48] [PASSED] 0xA78B (ALDERLAKE_S)
[11:39:48] [PASSED] 0x4905 (DG1)
[11:39:48] [PASSED] 0x4906 (DG1)
[11:39:48] [PASSED] 0x4907 (DG1)
[11:39:48] [PASSED] 0x4908 (DG1)
[11:39:48] [PASSED] 0x4909 (DG1)
[11:39:48] [PASSED] 0x56C0 (DG2)
[11:39:48] [PASSED] 0x56C2 (DG2)
[11:39:48] [PASSED] 0x56C1 (DG2)
[11:39:48] [PASSED] 0x7D51 (METEORLAKE)
[11:39:48] [PASSED] 0x7DD1 (METEORLAKE)
[11:39:48] [PASSED] 0x7D41 (METEORLAKE)
[11:39:48] [PASSED] 0x7D67 (METEORLAKE)
[11:39:48] [PASSED] 0xB640 (METEORLAKE)
[11:39:48] [PASSED] 0x56A0 (DG2)
[11:39:48] [PASSED] 0x56A1 (DG2)
[11:39:48] [PASSED] 0x56A2 (DG2)
[11:39:48] [PASSED] 0x56BE (DG2)
[11:39:48] [PASSED] 0x56BF (DG2)
[11:39:48] [PASSED] 0x5690 (DG2)
[11:39:48] [PASSED] 0x5691 (DG2)
[11:39:48] [PASSED] 0x5692 (DG2)
[11:39:48] [PASSED] 0x56A5 (DG2)
[11:39:48] [PASSED] 0x56A6 (DG2)
[11:39:48] [PASSED] 0x56B0 (DG2)
[11:39:48] [PASSED] 0x56B1 (DG2)
[11:39:48] [PASSED] 0x56BA (DG2)
[11:39:48] [PASSED] 0x56BB (DG2)
[11:39:48] [PASSED] 0x56BC (DG2)
[11:39:48] [PASSED] 0x56BD (DG2)
[11:39:48] [PASSED] 0x5693 (DG2)
[11:39:48] [PASSED] 0x5694 (DG2)
[11:39:48] [PASSED] 0x5695 (DG2)
[11:39:48] [PASSED] 0x56A3 (DG2)
[11:39:48] [PASSED] 0x56A4 (DG2)
[11:39:48] [PASSED] 0x56B2 (DG2)
[11:39:48] [PASSED] 0x56B3 (DG2)
[11:39:48] [PASSED] 0x5696 (DG2)
[11:39:48] [PASSED] 0x5697 (DG2)
[11:39:48] [PASSED] 0xB69 (PVC)
[11:39:48] [PASSED] 0xB6E (PVC)
[11:39:48] [PASSED] 0xBD4 (PVC)
[11:39:48] [PASSED] 0xBD5 (PVC)
[11:39:48] [PASSED] 0xBD6 (PVC)
[11:39:48] [PASSED] 0xBD7 (PVC)
[11:39:48] [PASSED] 0xBD8 (PVC)
[11:39:48] [PASSED] 0xBD9 (PVC)
[11:39:48] [PASSED] 0xBDA (PVC)
[11:39:48] [PASSED] 0xBDB (PVC)
[11:39:48] [PASSED] 0xBE0 (PVC)
[11:39:48] [PASSED] 0xBE1 (PVC)
[11:39:48] [PASSED] 0xBE5 (PVC)
[11:39:48] [PASSED] 0x7D40 (METEORLAKE)
[11:39:48] [PASSED] 0x7D45 (METEORLAKE)
[11:39:48] [PASSED] 0x7D55 (METEORLAKE)
[11:39:48] [PASSED] 0x7D60 (METEORLAKE)
[11:39:48] [PASSED] 0x7DD5 (METEORLAKE)
[11:39:48] [PASSED] 0x6420 (LUNARLAKE)
[11:39:48] [PASSED] 0x64A0 (LUNARLAKE)
[11:39:48] [PASSED] 0x64B0 (LUNARLAKE)
[11:39:48] [PASSED] 0xE202 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE209 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE20B (BATTLEMAGE)
[11:39:48] [PASSED] 0xE20C (BATTLEMAGE)
[11:39:48] [PASSED] 0xE20D (BATTLEMAGE)
[11:39:48] [PASSED] 0xE210 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE211 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE212 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE216 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE220 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE221 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE222 (BATTLEMAGE)
[11:39:48] [PASSED] 0xE223 (BATTLEMAGE)
[11:39:48] [PASSED] 0xB080 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB081 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB082 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB083 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB084 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB085 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB086 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB087 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB08F (PANTHERLAKE)
[11:39:48] [PASSED] 0xB090 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:39:48] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:39:48] [PASSED] 0xFD80 (PANTHERLAKE)
[11:39:48] [PASSED] 0xFD81 (PANTHERLAKE)
[11:39:48] [PASSED] 0xD740 (NOVALAKE_S)
[11:39:48] [PASSED] 0xD741 (NOVALAKE_S)
[11:39:48] [PASSED] 0xD742 (NOVALAKE_S)
[11:39:48] [PASSED] 0xD743 (NOVALAKE_S)
[11:39:48] [PASSED] 0xD744 (NOVALAKE_S)
[11:39:48] [PASSED] 0xD745 (NOVALAKE_S)
[11:39:48] [PASSED] 0x674C (CRESCENTISLAND)
[11:39:48] =============== [PASSED] check_platform_desc ===============
[11:39:48] ===================== [PASSED] xe_pci ======================
[11:39:48] =================== xe_rtp (2 subtests) ====================
[11:39:48] =============== xe_rtp_process_to_sr_tests ================
[11:39:48] [PASSED] coalesce-same-reg
[11:39:48] [PASSED] no-match-no-add
[11:39:48] [PASSED] match-or
[11:39:48] [PASSED] match-or-xfail
[11:39:48] [PASSED] no-match-no-add-multiple-rules
[11:39:48] [PASSED] two-regs-two-entries
[11:39:48] [PASSED] clr-one-set-other
[11:39:48] [PASSED] set-field
[11:39:48] [PASSED] conflict-duplicate
[11:39:48] [PASSED] conflict-not-disjoint
[11:39:48] [PASSED] conflict-reg-type
[11:39:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:39:48] ================== xe_rtp_process_tests ===================
[11:39:48] [PASSED] active1
[11:39:48] [PASSED] active2
[11:39:48] [PASSED] active-inactive
[11:39:48] [PASSED] inactive-active
[11:39:48] [PASSED] inactive-1st_or_active-inactive
[11:39:48] [PASSED] inactive-2nd_or_active-inactive
[11:39:48] [PASSED] inactive-last_or_active-inactive
[11:39:48] [PASSED] inactive-no_or_active-inactive
[11:39:48] ============== [PASSED] xe_rtp_process_tests ===============
[11:39:48] ===================== [PASSED] xe_rtp ======================
[11:39:48] ==================== xe_wa (1 subtest) =====================
[11:39:48] ======================== xe_wa_gt =========================
[11:39:48] [PASSED] TIGERLAKE B0
[11:39:48] [PASSED] DG1 A0
[11:39:48] [PASSED] DG1 B0
[11:39:48] [PASSED] ALDERLAKE_S A0
[11:39:48] [PASSED] ALDERLAKE_S B0
[11:39:48] [PASSED] ALDERLAKE_S C0
[11:39:48] [PASSED] ALDERLAKE_S D0
[11:39:48] [PASSED] ALDERLAKE_P A0
[11:39:48] [PASSED] ALDERLAKE_P B0
[11:39:48] [PASSED] ALDERLAKE_P C0
[11:39:48] [PASSED] ALDERLAKE_S RPLS D0
[11:39:48] [PASSED] ALDERLAKE_P RPLU E0
[11:39:48] [PASSED] DG2 G10 C0
[11:39:48] [PASSED] DG2 G11 B1
[11:39:48] [PASSED] DG2 G12 A1
[11:39:48] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:39:48] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:39:48] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:39:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:39:48] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:39:48] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:39:48] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:39:48] ==================== [PASSED] xe_wa_gt =====================
[11:39:48] ====================== [PASSED] xe_wa ======================
[11:39:48] ============================================================
[11:39:48] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[11:39:48] Elapsed time: 36.425s total, 4.274s configuring, 31.679s building, 0.459s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:39:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:39:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:40:16] Starting KUnit Kernel (1/1)...
[11:40:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:40:16] ============ drm_test_pick_cmdline (2 subtests) ============
[11:40:16] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:40:16] =============== drm_test_pick_cmdline_named ===============
[11:40:16] [PASSED] NTSC
[11:40:16] [PASSED] NTSC-J
[11:40:16] [PASSED] PAL
[11:40:16] [PASSED] PAL-M
[11:40:16] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:40:16] ============== [PASSED] drm_test_pick_cmdline ==============
[11:40:16] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:40:16] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:40:16] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:40:16] =========== drm_validate_clone_mode (2 subtests) ===========
[11:40:16] ============== drm_test_check_in_clone_mode ===============
[11:40:16] [PASSED] in_clone_mode
[11:40:16] [PASSED] not_in_clone_mode
[11:40:16] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:40:16] =============== drm_test_check_valid_clones ===============
[11:40:16] [PASSED] not_in_clone_mode
[11:40:16] [PASSED] valid_clone
[11:40:16] [PASSED] invalid_clone
[11:40:16] =========== [PASSED] drm_test_check_valid_clones ===========
[11:40:16] ============= [PASSED] drm_validate_clone_mode =============
[11:40:16] ============= drm_validate_modeset (1 subtest) =============
[11:40:16] [PASSED] drm_test_check_connector_changed_modeset
[11:40:16] ============== [PASSED] drm_validate_modeset ===============
[11:40:16] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:40:16] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:40:16] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:40:16] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:40:16] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:40:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:40:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:40:16] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:40:16] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:40:16] ============== drm_bridge_alloc (2 subtests) ===============
[11:40:16] [PASSED] drm_test_drm_bridge_alloc_basic
[11:40:16] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:40:16] ================ [PASSED] drm_bridge_alloc =================
[11:40:16] ================== drm_buddy (8 subtests) ==================
[11:40:16] [PASSED] drm_test_buddy_alloc_limit
[11:40:16] [PASSED] drm_test_buddy_alloc_optimistic
[11:40:16] [PASSED] drm_test_buddy_alloc_pessimistic
[11:40:16] [PASSED] drm_test_buddy_alloc_pathological
[11:40:16] [PASSED] drm_test_buddy_alloc_contiguous
[11:40:16] [PASSED] drm_test_buddy_alloc_clear
[11:40:16] [PASSED] drm_test_buddy_alloc_range_bias
[11:40:16] [PASSED] drm_test_buddy_fragmentation_performance
[11:40:16] ==================== [PASSED] drm_buddy ====================
[11:40:16] ============= drm_cmdline_parser (40 subtests) =============
[11:40:16] [PASSED] drm_test_cmdline_force_d_only
[11:40:16] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:40:16] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:40:16] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:40:16] [PASSED] drm_test_cmdline_force_e_only
[11:40:16] [PASSED] drm_test_cmdline_res
[11:40:16] [PASSED] drm_test_cmdline_res_vesa
[11:40:16] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:40:16] [PASSED] drm_test_cmdline_res_rblank
[11:40:16] [PASSED] drm_test_cmdline_res_bpp
[11:40:16] [PASSED] drm_test_cmdline_res_refresh
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:40:16] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:40:16] [PASSED] drm_test_cmdline_res_margins_force_on
[11:40:16] [PASSED] drm_test_cmdline_res_vesa_margins
[11:40:16] [PASSED] drm_test_cmdline_name
[11:40:16] [PASSED] drm_test_cmdline_name_bpp
[11:40:16] [PASSED] drm_test_cmdline_name_option
[11:40:16] [PASSED] drm_test_cmdline_name_bpp_option
[11:40:16] [PASSED] drm_test_cmdline_rotate_0
[11:40:16] [PASSED] drm_test_cmdline_rotate_90
[11:40:16] [PASSED] drm_test_cmdline_rotate_180
[11:40:16] [PASSED] drm_test_cmdline_rotate_270
[11:40:16] [PASSED] drm_test_cmdline_hmirror
[11:40:16] [PASSED] drm_test_cmdline_vmirror
[11:40:16] [PASSED] drm_test_cmdline_margin_options
[11:40:16] [PASSED] drm_test_cmdline_multiple_options
[11:40:16] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:40:16] [PASSED] drm_test_cmdline_extra_and_option
[11:40:16] [PASSED] drm_test_cmdline_freestanding_options
[11:40:16] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:40:16] [PASSED] drm_test_cmdline_panel_orientation
[11:40:16] ================ drm_test_cmdline_invalid =================
[11:40:16] [PASSED] margin_only
[11:40:16] [PASSED] interlace_only
[11:40:16] [PASSED] res_missing_x
[11:40:16] [PASSED] res_missing_y
[11:40:16] [PASSED] res_bad_y
[11:40:16] [PASSED] res_missing_y_bpp
[11:40:16] [PASSED] res_bad_bpp
[11:40:16] [PASSED] res_bad_refresh
[11:40:16] [PASSED] res_bpp_refresh_force_on_off
[11:40:16] [PASSED] res_invalid_mode
[11:40:16] [PASSED] res_bpp_wrong_place_mode
[11:40:16] [PASSED] name_bpp_refresh
[11:40:16] [PASSED] name_refresh
[11:40:16] [PASSED] name_refresh_wrong_mode
[11:40:16] [PASSED] name_refresh_invalid_mode
[11:40:16] [PASSED] rotate_multiple
[11:40:16] [PASSED] rotate_invalid_val
[11:40:16] [PASSED] rotate_truncated
[11:40:16] [PASSED] invalid_option
[11:40:16] [PASSED] invalid_tv_option
[11:40:16] [PASSED] truncated_tv_option
[11:40:16] ============ [PASSED] drm_test_cmdline_invalid =============
[11:40:16] =============== drm_test_cmdline_tv_options ===============
[11:40:16] [PASSED] NTSC
[11:40:16] [PASSED] NTSC_443
[11:40:16] [PASSED] NTSC_J
[11:40:16] [PASSED] PAL
[11:40:16] [PASSED] PAL_M
[11:40:16] [PASSED] PAL_N
[11:40:16] [PASSED] SECAM
[11:40:16] [PASSED] MONO_525
[11:40:16] [PASSED] MONO_625
[11:40:16] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:40:16] =============== [PASSED] drm_cmdline_parser ================
[11:40:16] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:40:16] [PASSED] drm_test_connector_hdmi_init_valid
[11:40:16] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:40:16] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:40:16] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:40:16] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:40:16] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:40:16] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:40:16] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:40:16] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:40:16] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:40:16] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:40:16] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:40:16] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:40:16] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:40:16] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:40:16] [PASSED] drm_test_connector_hdmi_init_null_product
[11:40:16] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:40:16] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:40:16] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:40:16] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:40:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:40:16] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:40:16] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:40:16] ========= drm_test_connector_hdmi_init_type_valid =========
[11:40:16] [PASSED] HDMI-A
[11:40:16] [PASSED] HDMI-B
[11:40:16] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:40:16] ======== drm_test_connector_hdmi_init_type_invalid ========
[11:40:16] [PASSED] Unknown
[11:40:16] [PASSED] VGA
[11:40:16] [PASSED] DVI-I
[11:40:16] [PASSED] DVI-D
[11:40:16] [PASSED] DVI-A
[11:40:16] [PASSED] Composite
[11:40:16] [PASSED] SVIDEO
[11:40:16] [PASSED] LVDS
[11:40:16] [PASSED] Component
[11:40:16] [PASSED] DIN
[11:40:16] [PASSED] DP
[11:40:16] [PASSED] TV
[11:40:16] [PASSED] eDP
[11:40:16] [PASSED] Virtual
[11:40:16] [PASSED] DSI
[11:40:16] [PASSED] DPI
[11:40:16] [PASSED] Writeback
[11:40:16] [PASSED] SPI
[11:40:16] [PASSED] USB
[11:40:16] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:40:16] ============ [PASSED] drmm_connector_hdmi_init =============
[11:40:16] ============= drmm_connector_init (3 subtests) =============
[11:40:16] [PASSED] drm_test_drmm_connector_init
[11:40:16] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:40:16] ========= drm_test_drmm_connector_init_type_valid =========
[11:40:16] [PASSED] Unknown
[11:40:16] [PASSED] VGA
[11:40:16] [PASSED] DVI-I
[11:40:16] [PASSED] DVI-D
[11:40:16] [PASSED] DVI-A
[11:40:16] [PASSED] Composite
[11:40:16] [PASSED] SVIDEO
[11:40:16] [PASSED] LVDS
[11:40:16] [PASSED] Component
[11:40:16] [PASSED] DIN
[11:40:16] [PASSED] DP
[11:40:16] [PASSED] HDMI-A
[11:40:16] [PASSED] HDMI-B
[11:40:16] [PASSED] TV
[11:40:16] [PASSED] eDP
[11:40:16] [PASSED] Virtual
[11:40:16] [PASSED] DSI
[11:40:16] [PASSED] DPI
[11:40:16] [PASSED] Writeback
[11:40:16] [PASSED] SPI
[11:40:16] [PASSED] USB
[11:40:16] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:40:16] =============== [PASSED] drmm_connector_init ===============
[11:40:16] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_init
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:40:16] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[11:40:16] [PASSED] Unknown
[11:40:16] [PASSED] VGA
[11:40:16] [PASSED] DVI-I
[11:40:16] [PASSED] DVI-D
[11:40:16] [PASSED] DVI-A
[11:40:16] [PASSED] Composite
[11:40:16] [PASSED] SVIDEO
[11:40:16] [PASSED] LVDS
[11:40:16] [PASSED] Component
[11:40:16] [PASSED] DIN
[11:40:16] [PASSED] DP
[11:40:16] [PASSED] HDMI-A
[11:40:16] [PASSED] HDMI-B
[11:40:16] [PASSED] TV
[11:40:16] [PASSED] eDP
[11:40:16] [PASSED] Virtual
[11:40:16] [PASSED] DSI
[11:40:16] [PASSED] DPI
[11:40:16] [PASSED] Writeback
[11:40:16] [PASSED] SPI
[11:40:16] [PASSED] USB
[11:40:16] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:40:16] ======== drm_test_drm_connector_dynamic_init_name =========
[11:40:16] [PASSED] Unknown
[11:40:16] [PASSED] VGA
[11:40:16] [PASSED] DVI-I
[11:40:16] [PASSED] DVI-D
[11:40:16] [PASSED] DVI-A
[11:40:16] [PASSED] Composite
[11:40:16] [PASSED] SVIDEO
[11:40:16] [PASSED] LVDS
[11:40:16] [PASSED] Component
[11:40:16] [PASSED] DIN
[11:40:16] [PASSED] DP
[11:40:16] [PASSED] HDMI-A
[11:40:16] [PASSED] HDMI-B
[11:40:16] [PASSED] TV
[11:40:16] [PASSED] eDP
[11:40:16] [PASSED] Virtual
[11:40:16] [PASSED] DSI
[11:40:16] [PASSED] DPI
[11:40:16] [PASSED] Writeback
[11:40:16] [PASSED] SPI
[11:40:16] [PASSED] USB
[11:40:16] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:40:16] =========== [PASSED] drm_connector_dynamic_init ============
[11:40:16] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:40:16] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:40:16] ======= drm_connector_dynamic_register (7 subtests) ========
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:40:16] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:40:16] ========= [PASSED] drm_connector_dynamic_register ==========
[11:40:16] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:40:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:40:16] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:40:16] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:40:16] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:40:16] ========== drm_test_get_tv_mode_from_name_valid ===========
[11:40:16] [PASSED] NTSC
[11:40:16] [PASSED] NTSC-443
[11:40:16] [PASSED] NTSC-J
[11:40:16] [PASSED] PAL
[11:40:16] [PASSED] PAL-M
[11:40:16] [PASSED] PAL-N
[11:40:16] [PASSED] SECAM
[11:40:16] [PASSED] Mono
[11:40:16] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:40:16] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:40:16] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:40:16] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:40:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:40:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:40:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:40:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:40:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:40:16] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:40:16] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[11:40:16] [PASSED] VIC 96
[11:40:16] [PASSED] VIC 97
[11:40:16] [PASSED] VIC 101
[11:40:16] [PASSED] VIC 102
[11:40:16] [PASSED] VIC 106
[11:40:16] [PASSED] VIC 107
[11:40:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:40:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:40:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:40:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:40:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:40:16] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:40:16] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:40:16] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:40:16] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[11:40:16] [PASSED] Automatic
[11:40:16] [PASSED] Full
[11:40:16] [PASSED] Limited 16:235
[11:40:16] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:40:16] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:40:16] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:40:16] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:40:16] === drm_test_drm_hdmi_connector_get_output_format_name ====
[11:40:16] [PASSED] RGB
[11:40:16] [PASSED] YUV 4:2:0
[11:40:16] [PASSED] YUV 4:2:2
[11:40:16] [PASSED] YUV 4:4:4
[11:40:16] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:40:16] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:40:16] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:40:16] ============= drm_damage_helper (21 subtests) ==============
[11:40:16] [PASSED] drm_test_damage_iter_no_damage
[11:40:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:40:16] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:40:16] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:40:16] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:40:16] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:40:16] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:40:16] [PASSED] drm_test_damage_iter_simple_damage
[11:40:16] [PASSED] drm_test_damage_iter_single_damage
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:40:16] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:40:16] [PASSED] drm_test_damage_iter_damage
[11:40:16] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:40:16] [PASSED] drm_test_damage_iter_damage_one_outside
[11:40:16] [PASSED] drm_test_damage_iter_damage_src_moved
[11:40:16] [PASSED] drm_test_damage_iter_damage_not_visible
[11:40:16] ================ [PASSED] drm_damage_helper ================
[11:40:16] ============== drm_dp_mst_helper (3 subtests) ==============
[11:40:16] ============== drm_test_dp_mst_calc_pbn_mode ==============
[11:40:16] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:40:16] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:40:16] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:40:16] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:40:16] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:40:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:40:16] ============== drm_test_dp_mst_calc_pbn_div ===============
[11:40:16] [PASSED] Link rate 2000000 lane count 4
[11:40:16] [PASSED] Link rate 2000000 lane count 2
[11:40:16] [PASSED] Link rate 2000000 lane count 1
[11:40:16] [PASSED] Link rate 1350000 lane count 4
[11:40:16] [PASSED] Link rate 1350000 lane count 2
[11:40:16] [PASSED] Link rate 1350000 lane count 1
[11:40:16] [PASSED] Link rate 1000000 lane count 4
[11:40:16] [PASSED] Link rate 1000000 lane count 2
[11:40:16] [PASSED] Link rate 1000000 lane count 1
[11:40:16] [PASSED] Link rate 810000 lane count 4
[11:40:16] [PASSED] Link rate 810000 lane count 2
[11:40:16] [PASSED] Link rate 810000 lane count 1
[11:40:16] [PASSED] Link rate 540000 lane count 4
[11:40:16] [PASSED] Link rate 540000 lane count 2
[11:40:16] [PASSED] Link rate 540000 lane count 1
[11:40:16] [PASSED] Link rate 270000 lane count 4
[11:40:16] [PASSED] Link rate 270000 lane count 2
[11:40:16] [PASSED] Link rate 270000 lane count 1
[11:40:16] [PASSED] Link rate 162000 lane count 4
[11:40:16] [PASSED] Link rate 162000 lane count 2
[11:40:16] [PASSED] Link rate 162000 lane count 1
[11:40:16] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:40:16] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[11:40:16] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:40:16] [PASSED] DP_POWER_UP_PHY with port number
[11:40:16] [PASSED] DP_POWER_DOWN_PHY with port number
[11:40:16] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:40:16] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:40:16] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:40:16] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:40:16] [PASSED] DP_QUERY_PAYLOAD with port number
[11:40:16] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:40:16] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:40:16] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:40:16] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:40:16] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:40:16] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:40:16] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:40:16] [PASSED] DP_REMOTE_I2C_READ with port number
[11:40:16] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:40:16] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:40:16] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:40:16] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:40:16] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:40:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:40:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:40:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:40:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:40:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:40:16] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:40:16] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:40:16] ================ [PASSED] drm_dp_mst_helper ================
[11:40:16] ================== drm_exec (7 subtests) ===================
[11:40:16] [PASSED] sanitycheck
[11:40:16] [PASSED] test_lock
[11:40:16] [PASSED] test_lock_unlock
[11:40:16] [PASSED] test_duplicates
[11:40:16] [PASSED] test_prepare
[11:40:16] [PASSED] test_prepare_array
[11:40:16] [PASSED] test_multiple_loops
[11:40:16] ==================== [PASSED] drm_exec =====================
[11:40:16] =========== drm_format_helper_test (17 subtests) ===========
[11:40:16] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:40:16] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:40:16] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:40:16] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:40:16] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:40:16] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:40:16] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:40:16] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:40:16] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:40:16] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:40:16] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:40:16] ============== drm_test_fb_xrgb8888_to_mono ===============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:40:16] ==================== drm_test_fb_swab =====================
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ================ [PASSED] drm_test_fb_swab =================
[11:40:16] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:40:16] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[11:40:16] [PASSED] single_pixel_source_buffer
[11:40:16] [PASSED] single_pixel_clip_rectangle
[11:40:16] [PASSED] well_known_colors
[11:40:16] [PASSED] destination_pitch
[11:40:16] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:40:16] ================= drm_test_fb_clip_offset =================
[11:40:16] [PASSED] pass through
[11:40:16] [PASSED] horizontal offset
[11:40:16] [PASSED] vertical offset
[11:40:16] [PASSED] horizontal and vertical offset
[11:40:16] [PASSED] horizontal offset (custom pitch)
[11:40:16] [PASSED] vertical offset (custom pitch)
[11:40:16] [PASSED] horizontal and vertical offset (custom pitch)
[11:40:16] ============= [PASSED] drm_test_fb_clip_offset =============
[11:40:16] =================== drm_test_fb_memcpy ====================
[11:40:16] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:40:16] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:40:16] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:40:16] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:40:16] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:40:16] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:40:16] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:40:16] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:40:16] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:40:16] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:40:16] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:40:16] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:40:16] =============== [PASSED] drm_test_fb_memcpy ================
[11:40:16] ============= [PASSED] drm_format_helper_test ==============
[11:40:16] ================= drm_format (18 subtests) =================
[11:40:16] [PASSED] drm_test_format_block_width_invalid
[11:40:16] [PASSED] drm_test_format_block_width_one_plane
[11:40:16] [PASSED] drm_test_format_block_width_two_plane
[11:40:16] [PASSED] drm_test_format_block_width_three_plane
[11:40:16] [PASSED] drm_test_format_block_width_tiled
[11:40:16] [PASSED] drm_test_format_block_height_invalid
[11:40:16] [PASSED] drm_test_format_block_height_one_plane
[11:40:16] [PASSED] drm_test_format_block_height_two_plane
[11:40:16] [PASSED] drm_test_format_block_height_three_plane
[11:40:16] [PASSED] drm_test_format_block_height_tiled
[11:40:16] [PASSED] drm_test_format_min_pitch_invalid
[11:40:16] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:40:16] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:40:16] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:40:16] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:40:16] [PASSED] drm_test_format_min_pitch_two_plane
[11:40:16] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:40:16] [PASSED] drm_test_format_min_pitch_tiled
[11:40:16] =================== [PASSED] drm_format ====================
[11:40:16] ============== drm_framebuffer (10 subtests) ===============
[11:40:16] ========== drm_test_framebuffer_check_src_coords ==========
[11:40:16] [PASSED] Success: source fits into fb
[11:40:16] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:40:16] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:40:16] [PASSED] Fail: overflowing fb with source width
[11:40:16] [PASSED] Fail: overflowing fb with source height
[11:40:16] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:40:16] [PASSED] drm_test_framebuffer_cleanup
[11:40:16] =============== drm_test_framebuffer_create ===============
[11:40:16] [PASSED] ABGR8888 normal sizes
[11:40:16] [PASSED] ABGR8888 max sizes
[11:40:16] [PASSED] ABGR8888 pitch greater than min required
[11:40:16] [PASSED] ABGR8888 pitch less than min required
[11:40:16] [PASSED] ABGR8888 Invalid width
[11:40:16] [PASSED] ABGR8888 Invalid buffer handle
[11:40:16] [PASSED] No pixel format
[11:40:16] [PASSED] ABGR8888 Width 0
[11:40:16] [PASSED] ABGR8888 Height 0
[11:40:16] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:40:16] [PASSED] ABGR8888 Large buffer offset
[11:40:16] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:40:16] [PASSED] ABGR8888 Invalid flag
[11:40:16] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:40:16] [PASSED] ABGR8888 Valid buffer modifier
[11:40:16] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:40:16] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] NV12 Normal sizes
[11:40:16] [PASSED] NV12 Max sizes
[11:40:16] [PASSED] NV12 Invalid pitch
[11:40:16] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:40:16] [PASSED] NV12 different modifier per-plane
[11:40:16] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:40:16] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] NV12 Modifier for inexistent plane
[11:40:16] [PASSED] NV12 Handle for inexistent plane
[11:40:16] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:40:16] [PASSED] YVU420 Normal sizes
[11:40:16] [PASSED] YVU420 Max sizes
[11:40:16] [PASSED] YVU420 Invalid pitch
[11:40:16] [PASSED] YVU420 Different pitches
[11:40:16] [PASSED] YVU420 Different buffer offsets/pitches
[11:40:16] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:40:16] [PASSED] YVU420 Valid modifier
[11:40:16] [PASSED] YVU420 Different modifiers per plane
[11:40:16] [PASSED] YVU420 Modifier for inexistent plane
[11:40:16] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:40:16] [PASSED] X0L2 Normal sizes
[11:40:16] [PASSED] X0L2 Max sizes
[11:40:16] [PASSED] X0L2 Invalid pitch
[11:40:16] [PASSED] X0L2 Pitch greater than minimum required
[11:40:16] [PASSED] X0L2 Handle for inexistent plane
[11:40:16] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:40:16] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:40:16] [PASSED] X0L2 Valid modifier
[11:40:16] [PASSED] X0L2 Modifier for inexistent plane
[11:40:16] =========== [PASSED] drm_test_framebuffer_create ===========
[11:40:16] [PASSED] drm_test_framebuffer_free
[11:40:16] [PASSED] drm_test_framebuffer_init
[11:40:16] [PASSED] drm_test_framebuffer_init_bad_format
[11:40:16] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:40:16] [PASSED] drm_test_framebuffer_lookup
[11:40:16] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:40:16] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:40:16] ================= [PASSED] drm_framebuffer =================
[11:40:16] ================ drm_gem_shmem (8 subtests) ================
[11:40:16] [PASSED] drm_gem_shmem_test_obj_create
[11:40:16] [PASSED] drm_gem_shmem_test_obj_create_private
[11:40:16] [PASSED] drm_gem_shmem_test_pin_pages
[11:40:16] [PASSED] drm_gem_shmem_test_vmap
[11:40:16] [PASSED] drm_gem_shmem_test_get_sg_table
[11:40:16] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:40:16] [PASSED] drm_gem_shmem_test_madvise
[11:40:16] [PASSED] drm_gem_shmem_test_purge
[11:40:16] ================== [PASSED] drm_gem_shmem ==================
[11:40:16] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:40:16] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[11:40:16] [PASSED] Automatic
[11:40:16] [PASSED] Full
[11:40:16] [PASSED] Limited 16:235
[11:40:16] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:40:16] [PASSED] drm_test_check_disable_connector
[11:40:16] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:40:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:40:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:40:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:40:16] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:40:16] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:40:16] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:40:16] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:40:16] [PASSED] drm_test_check_output_bpc_dvi
[11:40:16] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:40:16] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:40:16] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:40:16] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:40:16] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:40:16] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:40:16] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:40:16] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:40:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:40:16] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:40:16] [PASSED] drm_test_check_broadcast_rgb_value
[11:40:16] [PASSED] drm_test_check_bpc_8_value
[11:40:16] [PASSED] drm_test_check_bpc_10_value
[11:40:16] [PASSED] drm_test_check_bpc_12_value
[11:40:16] [PASSED] drm_test_check_format_value
[11:40:16] [PASSED] drm_test_check_tmds_char_value
[11:40:16] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:40:16] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:40:16] [PASSED] drm_test_check_mode_valid
[11:40:16] [PASSED] drm_test_check_mode_valid_reject
[11:40:16] [PASSED] drm_test_check_mode_valid_reject_rate
[11:40:16] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:40:16] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:40:16] ================= drm_managed (2 subtests) =================
[11:40:16] [PASSED] drm_test_managed_release_action
[11:40:16] [PASSED] drm_test_managed_run_action
[11:40:16] =================== [PASSED] drm_managed ===================
[11:40:16] =================== drm_mm (6 subtests) ====================
[11:40:16] [PASSED] drm_test_mm_init
[11:40:16] [PASSED] drm_test_mm_debug
[11:40:16] [PASSED] drm_test_mm_align32
[11:40:16] [PASSED] drm_test_mm_align64
[11:40:16] [PASSED] drm_test_mm_lowest
[11:40:16] [PASSED] drm_test_mm_highest
[11:40:16] ===================== [PASSED] drm_mm ======================
[11:40:16] ============= drm_modes_analog_tv (5 subtests) =============
[11:40:16] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:40:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:40:16] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:40:16] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:40:16] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:40:16] =============== [PASSED] drm_modes_analog_tv ===============
[11:40:16] ============== drm_plane_helper (2 subtests) ===============
[11:40:16] =============== drm_test_check_plane_state ================
[11:40:16] [PASSED] clipping_simple
[11:40:16] [PASSED] clipping_rotate_reflect
[11:40:16] [PASSED] positioning_simple
[11:40:16] [PASSED] upscaling
[11:40:16] [PASSED] downscaling
[11:40:16] [PASSED] rounding1
[11:40:16] [PASSED] rounding2
[11:40:16] [PASSED] rounding3
[11:40:16] [PASSED] rounding4
[11:40:16] =========== [PASSED] drm_test_check_plane_state ============
[11:40:16] =========== drm_test_check_invalid_plane_state ============
[11:40:16] [PASSED] positioning_invalid
[11:40:16] [PASSED] upscaling_invalid
[11:40:16] [PASSED] downscaling_invalid
[11:40:16] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:40:16] ================ [PASSED] drm_plane_helper =================
[11:40:16] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:40:16] ====== drm_test_connector_helper_tv_get_modes_check =======
[11:40:16] [PASSED] None
[11:40:16] [PASSED] PAL
[11:40:16] [PASSED] NTSC
[11:40:16] [PASSED] Both, NTSC Default
[11:40:16] [PASSED] Both, PAL Default
[11:40:16] [PASSED] Both, NTSC Default, with PAL on command-line
[11:40:16] [PASSED] Both, PAL Default, with NTSC on command-line
[11:40:16] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:40:16] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:40:16] ================== drm_rect (9 subtests) ===================
[11:40:16] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:40:16] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:40:16] [PASSED] drm_test_rect_clip_scaled_clipped
[11:40:16] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:40:16] ================= drm_test_rect_intersect =================
[11:40:16] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:40:16] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:40:16] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:40:16] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:40:16] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:40:16] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:40:16] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:40:16] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:40:16] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:40:16] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:40:16] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:40:16] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:40:16] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:40:16] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:40:16] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:40:16] ============= [PASSED] drm_test_rect_intersect =============
[11:40:16] ================ drm_test_rect_calc_hscale ================
[11:40:16] [PASSED] normal use
[11:40:16] [PASSED] out of max range
[11:40:16] [PASSED] out of min range
[11:40:16] [PASSED] zero dst
[11:40:16] [PASSED] negative src
[11:40:16] [PASSED] negative dst
[11:40:16] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:40:16] ================ drm_test_rect_calc_vscale ================
[11:40:16] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[11:40:16] [PASSED] out of max range
[11:40:16] [PASSED] out of min range
[11:40:16] [PASSED] zero dst
[11:40:16] [PASSED] negative src
[11:40:16] [PASSED] negative dst
[11:40:16] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:40:16] ================== drm_test_rect_rotate ===================
[11:40:16] [PASSED] reflect-x
[11:40:16] [PASSED] reflect-y
[11:40:16] [PASSED] rotate-0
[11:40:16] [PASSED] rotate-90
[11:40:16] [PASSED] rotate-180
[11:40:16] [PASSED] rotate-270
[11:40:16] ============== [PASSED] drm_test_rect_rotate ===============
[11:40:16] ================ drm_test_rect_rotate_inv =================
[11:40:16] [PASSED] reflect-x
[11:40:16] [PASSED] reflect-y
[11:40:16] [PASSED] rotate-0
[11:40:16] [PASSED] rotate-90
[11:40:16] [PASSED] rotate-180
[11:40:16] [PASSED] rotate-270
[11:40:16] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:40:16] ==================== [PASSED] drm_rect =====================
[11:40:16] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:40:16] ============ drm_test_sysfb_build_fourcc_list =============
[11:40:16] [PASSED] no native formats
[11:40:16] [PASSED] XRGB8888 as native format
[11:40:16] [PASSED] remove duplicates
[11:40:16] [PASSED] convert alpha formats
[11:40:16] [PASSED] random formats
[11:40:16] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:40:16] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:40:16] ================== drm_fixp (2 subtests) ===================
[11:40:16] [PASSED] drm_test_int2fixp
[11:40:16] [PASSED] drm_test_sm2fixp
[11:40:16] ==================== [PASSED] drm_fixp =====================
[11:40:16] ============================================================
[11:40:16] Testing complete. Ran 624 tests: passed: 624
[11:40:16] Elapsed time: 27.510s total, 1.726s configuring, 25.365s building, 0.382s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:40:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:40:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:40:27] Starting KUnit Kernel (1/1)...
[11:40:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:40:27] ================= ttm_device (5 subtests) ==================
[11:40:27] [PASSED] ttm_device_init_basic
[11:40:27] [PASSED] ttm_device_init_multiple
[11:40:27] [PASSED] ttm_device_fini_basic
[11:40:27] [PASSED] ttm_device_init_no_vma_man
[11:40:27] ================== ttm_device_init_pools ==================
[11:40:27] [PASSED] No DMA allocations, no DMA32 required
[11:40:27] [PASSED] DMA allocations, DMA32 required
[11:40:27] [PASSED] No DMA allocations, DMA32 required
[11:40:27] [PASSED] DMA allocations, no DMA32 required
[11:40:27] ============== [PASSED] ttm_device_init_pools ==============
[11:40:27] =================== [PASSED] ttm_device ====================
[11:40:27] ================== ttm_pool (8 subtests) ===================
[11:40:27] ================== ttm_pool_alloc_basic ===================
[11:40:27] [PASSED] One page
[11:40:27] [PASSED] More than one page
[11:40:27] [PASSED] Above the allocation limit
[11:40:27] [PASSED] One page, with coherent DMA mappings enabled
[11:40:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:40:27] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:40:27] ============== ttm_pool_alloc_basic_dma_addr ==============
[11:40:27] [PASSED] One page
[11:40:27] [PASSED] More than one page
[11:40:27] [PASSED] Above the allocation limit
[11:40:27] [PASSED] One page, with coherent DMA mappings enabled
[11:40:27] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:40:27] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:40:27] [PASSED] ttm_pool_alloc_order_caching_match
[11:40:27] [PASSED] ttm_pool_alloc_caching_mismatch
[11:40:27] [PASSED] ttm_pool_alloc_order_mismatch
[11:40:27] [PASSED] ttm_pool_free_dma_alloc
[11:40:27] [PASSED] ttm_pool_free_no_dma_alloc
[11:40:27] [PASSED] ttm_pool_fini_basic
[11:40:27] ==================== [PASSED] ttm_pool =====================
[11:40:27] ================ ttm_resource (8 subtests) =================
[11:40:27] ================= ttm_resource_init_basic =================
[11:40:27] [PASSED] Init resource in TTM_PL_SYSTEM
[11:40:27] [PASSED] Init resource in TTM_PL_VRAM
[11:40:27] [PASSED] Init resource in a private placement
[11:40:27] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:40:27] ============= [PASSED] ttm_resource_init_basic =============
[11:40:27] [PASSED] ttm_resource_init_pinned
[11:40:27] [PASSED] ttm_resource_fini_basic
[11:40:27] [PASSED] ttm_resource_manager_init_basic
[11:40:27] [PASSED] ttm_resource_manager_usage_basic
[11:40:27] [PASSED] ttm_resource_manager_set_used_basic
[11:40:27] [PASSED] ttm_sys_man_alloc_basic
[11:40:27] [PASSED] ttm_sys_man_free_basic
[11:40:27] ================== [PASSED] ttm_resource ===================
[11:40:27] =================== ttm_tt (15 subtests) ===================
[11:40:27] ==================== ttm_tt_init_basic ====================
[11:40:27] [PASSED] Page-aligned size
[11:40:27] [PASSED] Extra pages requested
[11:40:27] ================ [PASSED] ttm_tt_init_basic ================
[11:40:27] [PASSED] ttm_tt_init_misaligned
[11:40:27] [PASSED] ttm_tt_fini_basic
[11:40:27] [PASSED] ttm_tt_fini_sg
[11:40:27] [PASSED] ttm_tt_fini_shmem
[11:40:27] [PASSED] ttm_tt_create_basic
[11:40:27] [PASSED] ttm_tt_create_invalid_bo_type
[11:40:27] [PASSED] ttm_tt_create_ttm_exists
[11:40:27] [PASSED] ttm_tt_create_failed
[11:40:27] [PASSED] ttm_tt_destroy_basic
[11:40:27] [PASSED] ttm_tt_populate_null_ttm
[11:40:27] [PASSED] ttm_tt_populate_populated_ttm
[11:40:27] [PASSED] ttm_tt_unpopulate_basic
[11:40:27] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:40:27] [PASSED] ttm_tt_swapin_basic
[11:40:27] ===================== [PASSED] ttm_tt ======================
[11:40:27] =================== ttm_bo (14 subtests) ===================
[11:40:27] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[11:40:27] [PASSED] Cannot be interrupted and sleeps
[11:40:27] [PASSED] Cannot be interrupted, locks straight away
[11:40:27] [PASSED] Can be interrupted, sleeps
[11:40:27] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:40:27] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:40:27] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:40:27] [PASSED] ttm_bo_reserve_double_resv
[11:40:27] [PASSED] ttm_bo_reserve_interrupted
[11:40:27] [PASSED] ttm_bo_reserve_deadlock
[11:40:27] [PASSED] ttm_bo_unreserve_basic
[11:40:27] [PASSED] ttm_bo_unreserve_pinned
[11:40:27] [PASSED] ttm_bo_unreserve_bulk
[11:40:27] [PASSED] ttm_bo_fini_basic
[11:40:27] [PASSED] ttm_bo_fini_shared_resv
[11:40:27] [PASSED] ttm_bo_pin_basic
[11:40:27] [PASSED] ttm_bo_pin_unpin_resource
[11:40:27] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:40:27] ===================== [PASSED] ttm_bo ======================
[11:40:27] ============== ttm_bo_validate (21 subtests) ===============
[11:40:27] ============== ttm_bo_init_reserved_sys_man ===============
[11:40:27] [PASSED] Buffer object for userspace
[11:40:27] [PASSED] Kernel buffer object
[11:40:27] [PASSED] Shared buffer object
[11:40:27] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:40:27] ============== ttm_bo_init_reserved_mock_man ==============
[11:40:27] [PASSED] Buffer object for userspace
[11:40:27] [PASSED] Kernel buffer object
[11:40:27] [PASSED] Shared buffer object
[11:40:27] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:40:27] [PASSED] ttm_bo_init_reserved_resv
[11:40:27] ================== ttm_bo_validate_basic ==================
[11:40:27] [PASSED] Buffer object for userspace
[11:40:27] [PASSED] Kernel buffer object
[11:40:27] [PASSED] Shared buffer object
[11:40:27] ============== [PASSED] ttm_bo_validate_basic ==============
[11:40:27] [PASSED] ttm_bo_validate_invalid_placement
[11:40:27] ============= ttm_bo_validate_same_placement ==============
[11:40:27] [PASSED] System manager
[11:40:27] [PASSED] VRAM manager
[11:40:27] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:40:27] [PASSED] ttm_bo_validate_failed_alloc
[11:40:27] [PASSED] ttm_bo_validate_pinned
[11:40:27] [PASSED] ttm_bo_validate_busy_placement
[11:40:27] ================ ttm_bo_validate_multihop =================
[11:40:27] [PASSED] Buffer object for userspace
[11:40:27] [PASSED] Kernel buffer object
[11:40:27] [PASSED] Shared buffer object
[11:40:27] ============ [PASSED] ttm_bo_validate_multihop =============
[11:40:27] ========== ttm_bo_validate_no_placement_signaled ==========
[11:40:27] [PASSED] Buffer object in system domain, no page vector
[11:40:27] [PASSED] Buffer object in system domain with an existing page vector
[11:40:27] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:40:27] ======== ttm_bo_validate_no_placement_not_signaled ========
[11:40:27] [PASSED] Buffer object for userspace
[11:40:27] [PASSED] Kernel buffer object
[11:40:27] [PASSED] Shared buffer object
[11:40:27] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:40:27] [PASSED] ttm_bo_validate_move_fence_signaled
[11:40:28] ========= ttm_bo_validate_move_fence_not_signaled =========
[11:40:28] [PASSED] Waits for GPU
[11:40:28] [PASSED] Tries to lock straight away
[11:40:28] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:40:28] [PASSED] ttm_bo_validate_happy_evict
[11:40:28] [PASSED] ttm_bo_validate_all_pinned_evict
[11:40:28] [PASSED] ttm_bo_validate_allowed_only_evict
[11:40:28] [PASSED] ttm_bo_validate_deleted_evict
[11:40:28] [PASSED] ttm_bo_validate_busy_domain_evict
[11:40:28] [PASSED] ttm_bo_validate_evict_gutting
[11:40:28] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:40:28] ================= [PASSED] ttm_bo_validate =================
[11:40:28] ============================================================
[11:40:28] Testing complete. Ran 101 tests: passed: 101
[11:40:28] Elapsed time: 11.374s total, 1.639s configuring, 9.519s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Xe.CI.BAT: success for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
2026-01-15 11:33 [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Jani Nikula
2026-01-15 11:39 ` ✗ CI.checkpatch: warning for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2) Patchwork
2026-01-15 11:40 ` ✓ CI.KUnit: success " Patchwork
@ 2026-01-15 12:15 ` Patchwork
2026-01-15 13:20 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-16 17:38 ` [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Michał Grzelak
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-01-15 12:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2207 bytes --]
== Series Details ==
Series: drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
URL : https://patchwork.freedesktop.org/series/159877/
State : success
== Summary ==
CI Bug Log - changes from xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d_BAT -> xe-pw-159877v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-159877v2_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@xe_waitfence@abstime:
- bat-bmg-2: [PASS][1] -> [TIMEOUT][2] ([Intel XE#6506])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/bat-bmg-2/igt@xe_waitfence@abstime.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/bat-bmg-2/igt@xe_waitfence@abstime.html
- bat-dg2-oem2: [PASS][3] -> [TIMEOUT][4] ([Intel XE#6506])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/bat-dg2-oem2/igt@xe_waitfence@abstime.html
#### Possible fixes ####
* igt@xe_waitfence@reltime:
- bat-dg2-oem2: [FAIL][5] ([Intel XE#6520]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/bat-dg2-oem2/igt@xe_waitfence@reltime.html
[Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
[Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520
Build changes
-------------
* Linux: xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d -> xe-pw-159877v2
IGT_8701: 8701
xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d: 733664f1edf3c01cc68e6dd0bbdb135158a98a1d
xe-pw-159877v2: 159877v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/index.html
[-- Attachment #2: Type: text/html, Size: 2871 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Xe.CI.Full: failure for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
2026-01-15 11:33 [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Jani Nikula
` (2 preceding siblings ...)
2026-01-15 12:15 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-01-15 13:20 ` Patchwork
2026-01-16 17:38 ` [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Michał Grzelak
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2026-01-15 13:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 35256 bytes --]
== Series Details ==
Series: drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2)
URL : https://patchwork.freedesktop.org/series/159877/
State : failure
== Summary ==
CI Bug Log - changes from xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d_FULL -> xe-pw-159877v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-159877v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-159877v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-159877v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@cursor-sliding-256x256:
- shard-bmg: [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-256x256.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-256x256.html
#### Warnings ####
* igt@xe_exec_system_allocator@process-many-mmap-file-mlock-nomemset:
- shard-lnl: [DMESG-WARN][3] ([Intel XE#4537]) -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-lnl-3/igt@xe_exec_system_allocator@process-many-mmap-file-mlock-nomemset.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-5/igt@xe_exec_system_allocator@process-many-mmap-file-mlock-nomemset.html
Known issues
------------
Here are the changes found in xe-pw-159877v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_3d@basic:
- shard-lnl: NOTRUN -> [SKIP][5] ([Intel XE#6011])
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-3/igt@kms_3d@basic.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#2370])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#2327]) +4 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][8] ([Intel XE#1407])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-3/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#7059])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#610])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#1124]) +10 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#2314] / [Intel XE#2894])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-3840x2160p:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#367]) +5 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#3432])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#2887]) +14 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_cdclk@plane-scaling:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2724])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_color@ctm-negative:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2325]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_chamelium_color@ctm-negative.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2252]) +8 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_content_protection@atomic:
- shard-bmg: NOTRUN -> [FAIL][20] ([Intel XE#1178] / [Intel XE#3304]) +5 other tests fail
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-0:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2390] / [Intel XE#6974])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_content_protection@dp-mst-lic-type-0.html
* igt@kms_content_protection@dp-mst-type-0-hdcp14:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#6974])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
* igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][23] ([Intel XE#3304]) +3 other tests fail
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-offscreen-512x170:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2321])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2320]) +3 other tests skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#1340])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#4331])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2244])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#776])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [PASS][30] -> [FAIL][31] ([Intel XE#301]) +1 other test fail
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#2293] / [Intel XE#2380]) +5 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#2293]) +5 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
- shard-lnl: NOTRUN -> [SKIP][34] ([Intel XE#651])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt:
- shard-lnl: NOTRUN -> [SKIP][35] ([Intel XE#656])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#4141]) +13 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#7061]) +6 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#2311]) +31 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#2313]) +33 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2:
- shard-bmg: [PASS][40] -> [ABORT][41] ([Intel XE#6740]) +1 other test abort
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-2/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-9/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-2.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-bmg: NOTRUN -> [ABORT][42] ([Intel XE#6740]) +1 other test abort
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#3544])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_joiner@basic-max-non-joiner:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#4298])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_joiner@basic-max-non-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2925])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2501])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_panel_fitting@legacy:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#2486])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_panel_fitting@legacy.html
* igt@kms_plane_multiple@tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#5020])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836]) +1 other test skip
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@package-g7:
- shard-bmg: NOTRUN -> [SKIP][50] ([Intel XE#6814])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_pm_rpm@package-g7.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#1406] / [Intel XE#1489]) +5 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-bmg: NOTRUN -> [SKIP][52] ([Intel XE#1406] / [Intel XE#2387]) +1 other test skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-psr2-cursor-plane-move:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +12 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_psr@fbc-psr2-cursor-plane-move.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#2414])
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2330])
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#3414] / [Intel XE#3904])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2413])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_sharpness_filter@invalid-filter-with-scaler:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#6503]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_sharpness_filter@invalid-filter-with-scaler.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: NOTRUN -> [SKIP][59] ([Intel XE#2426])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_vrr@flip-suspend:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#1499])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@kms_vrr@flip-suspend.html
* igt@kms_vrr@lobf:
- shard-bmg: NOTRUN -> [SKIP][61] ([Intel XE#2168])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@kms_vrr@lobf.html
* igt@xe_eudebug@vma-ufence:
- shard-bmg: NOTRUN -> [SKIP][62] ([Intel XE#4837]) +6 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_eudebug@vma-ufence.html
* igt@xe_eudebug_online@pagefault-read-stress:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#6665] / [Intel XE#6681])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_eudebug_online@pagefault-read-stress.html
* igt@xe_eudebug_online@stopped-thread:
- shard-bmg: NOTRUN -> [SKIP][64] ([Intel XE#4837] / [Intel XE#6665]) +6 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_eudebug_online@stopped-thread.html
* igt@xe_eudebug_sriov@deny-sriov:
- shard-bmg: NOTRUN -> [SKIP][65] ([Intel XE#5793])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_eudebug_sriov@deny-sriov.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#2322]) +11 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue.html
* igt@xe_exec_multi_queue@two-queues-priority:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#6874]) +30 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_exec_multi_queue@two-queues-priority.html
* igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#5007])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#4943]) +27 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-mmap-free-huge.html
* igt@xe_multigpu_svm@mgpu-concurrent-access-prefetch:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#6964]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@xe_multigpu_svm@mgpu-concurrent-access-prefetch.html
* igt@xe_pat@pat-index-xehpc:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#1420])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_pat@pat-index-xehpc.html
* igt@xe_pm@d3cold-i2c:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#5694])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_pm@d3cold-i2c.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-bmg: NOTRUN -> [SKIP][73] ([Intel XE#2284]) +1 other test skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#4733]) +2 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#944]) +3 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_query@multigpu-query-mem-usage.html
* igt@xe_sriov_flr@flr-vf1-clear:
- shard-bmg: NOTRUN -> [FAIL][76] ([Intel XE#5937])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@xe_sriov_flr@flr-vf1-clear.html
#### Possible fixes ####
* igt@xe_compute@loop-duration-2s:
- shard-bmg: [FAIL][77] ([Intel XE#7076]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-10/igt@xe_compute@loop-duration-2s.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-8/igt@xe_compute@loop-duration-2s.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][79] ([Intel XE#6321]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-8/igt@xe_evict@evict-mixed-many-threads-small.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_exec_reset@gt-reset-stress:
- shard-lnl: [DMESG-WARN][81] ([Intel XE#7023]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-lnl-4/igt@xe_exec_reset@gt-reset-stress.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-lnl-7/igt@xe_exec_reset@gt-reset-stress.html
#### Warnings ####
* igt@xe_module_load@load:
- shard-bmg: ([PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [SKIP][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [ABORT][100], [ABORT][101], [ABORT][102], [ABORT][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107]) ([Intel XE#2457]) -> ([PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [PASS][115], [PASS][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [SKIP][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132]) ([Intel XE#2457])
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-8/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-8/igt@xe_module_load@load.html
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-3/igt@xe_module_load@load.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-3/igt@xe_module_load@load.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-10/igt@xe_module_load@load.html
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-10/igt@xe_module_load@load.html
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-1/igt@xe_module_load@load.html
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-1/igt@xe_module_load@load.html
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-1/igt@xe_module_load@load.html
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-1/igt@xe_module_load@load.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-7/igt@xe_module_load@load.html
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-7/igt@xe_module_load@load.html
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-7/igt@xe_module_load@load.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-6/igt@xe_module_load@load.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-6/igt@xe_module_load@load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-9/igt@xe_module_load@load.html
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-9/igt@xe_module_load@load.html
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-4/igt@xe_module_load@load.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-4/igt@xe_module_load@load.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-4/igt@xe_module_load@load.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-4/igt@xe_module_load@load.html
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-9/igt@xe_module_load@load.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-2/igt@xe_module_load@load.html
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-2/igt@xe_module_load@load.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d/shard-bmg-2/igt@xe_module_load@load.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-8/igt@xe_module_load@load.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_module_load@load.html
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-2/igt@xe_module_load@load.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-2/igt@xe_module_load@load.html
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-6/igt@xe_module_load@load.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_module_load@load.html
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-8/igt@xe_module_load@load.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-10/igt@xe_module_load@load.html
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@xe_module_load@load.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-8/igt@xe_module_load@load.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-9/igt@xe_module_load@load.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-9/igt@xe_module_load@load.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@xe_module_load@load.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-3/igt@xe_module_load@load.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_module_load@load.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_module_load@load.html
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-1/igt@xe_module_load@load.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-1/igt@xe_module_load@load.html
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-1/igt@xe_module_load@load.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-1/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-1/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-7/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-9/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/shard-bmg-9/igt@xe_module_load@load.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
[Intel XE#2370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2370
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2486
[Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
[Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
[Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
[Intel XE#5793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5793
[Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
[Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6681]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6681
[Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
[Intel XE#6814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6814
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7023]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7023
[Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7076]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7076
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d -> xe-pw-159877v2
IGT_8701: 8701
xe-4384-733664f1edf3c01cc68e6dd0bbdb135158a98a1d: 733664f1edf3c01cc68e6dd0bbdb135158a98a1d
xe-pw-159877v2: 159877v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159877v2/index.html
[-- Attachment #2: Type: text/html, Size: 38561 bytes --]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface
2026-01-15 11:33 [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Jani Nikula
` (3 preceding siblings ...)
2026-01-15 13:20 ` ✗ Xe.CI.Full: failure " Patchwork
@ 2026-01-16 17:38 ` Michał Grzelak
2026-01-19 10:14 ` Jani Nikula
4 siblings, 1 reply; 8+ messages in thread
From: Michał Grzelak @ 2026-01-16 17:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
[-- Attachment #1: Type: text/plain, Size: 31321 bytes --]
On Thu, 15 Jan 2026, Jani Nikula wrote:
> Call the parent driver pcode functions through the parent interface
> function pointers instead of expecting both to have functions of the
> same name.
>
> In i915, add the interface to existing intel_pcode.[ch], while in xe
> move them to new display/xe_display_pcode.[ch] and build it only for
> CONFIG_DRM_XE_DISPLAY=y.
>
> Do not add separate write and write_timeout calls in the
> interface. Instead, handle the default 1 ms timeout in the
> intel_parent.c glue layer.
>
> This drops the last intel_pcode.h includes from display, and allows us
> to remove the corresponding xe compat header.
>
> v2: initialize .pcode in i915
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c | 8 +--
> drivers/gpu/drm/i915/display/intel_bw.c | 22 ++++----
> drivers/gpu/drm/i915/display/intel_cdclk.c | 54 +++++++++----------
> .../drm/i915/display/intel_display_power.c | 3 +-
> .../i915/display/intel_display_power_well.c | 5 +-
> drivers/gpu/drm/i915/display/intel_dram.c | 6 +--
> drivers/gpu/drm/i915/display/intel_hdcp.c | 3 +-
> drivers/gpu/drm/i915/display/intel_parent.c | 22 ++++++++
> drivers/gpu/drm/i915/display/intel_parent.h | 7 +++
> drivers/gpu/drm/i915/display/skl_watermark.c | 21 ++++----
> drivers/gpu/drm/i915/i915_driver.c | 1 +
> drivers/gpu/drm/i915/intel_pcode.c | 16 ++++--
> drivers/gpu/drm/i915/intel_pcode.h | 9 +---
> drivers/gpu/drm/xe/Makefile | 1 +
> .../drm/xe/compat-i915-headers/intel_pcode.h | 11 ----
> drivers/gpu/drm/xe/display/xe_display.c | 2 +
> drivers/gpu/drm/xe/display/xe_display_pcode.c | 38 +++++++++++++
> drivers/gpu/drm/xe/display/xe_display_pcode.h | 9 ++++
> drivers/gpu/drm/xe/xe_pcode.c | 30 -----------
> drivers/gpu/drm/xe/xe_pcode.h | 8 ---
> include/drm/intel/display_parent_interface.h | 10 ++++
> 21 files changed, 161 insertions(+), 125 deletions(-)
> delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
> create mode 100644 drivers/gpu/drm/xe/display/xe_display_pcode.c
> create mode 100644 drivers/gpu/drm/xe/display/xe_display_pcode.h
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 008d339d5c21..0caaea2e64e1 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -14,7 +14,7 @@
> #include "intel_display_regs.h"
> #include "intel_display_rpm.h"
> #include "intel_display_types.h"
> -#include "intel_pcode.h"
> +#include "intel_parent.h"
>
> static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> {
> @@ -39,8 +39,8 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
>
> if (display->platform.broadwell) {
> drm_WARN_ON(display->drm,
> - intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,
> - val | IPS_PCODE_CONTROL));
> + intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL,
> + val | IPS_PCODE_CONTROL));
> /*
> * Quoting Art Runyan: "its not safe to expect any particular
> * value in IPS_CTL bit 31 after enabling IPS through the
> @@ -72,7 +72,7 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
>
> if (display->platform.broadwell) {
> drm_WARN_ON(display->drm,
> - intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));
> + intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL, 0));
> /*
> * Wait for PCODE to finish disabling IPS. The BSpec specified
> * 42ms timeout value leads to occasional timeouts so use 100ms
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 4ee3f5172f4e..8d84445c69f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -15,7 +15,7 @@
> #include "intel_display_utils.h"
> #include "intel_dram.h"
> #include "intel_mchbar_regs.h"
> -#include "intel_pcode.h"
> +#include "intel_parent.h"
> #include "intel_uncore.h"
> #include "skl_watermark.h"
>
> @@ -114,9 +114,9 @@ static int icl_pcode_read_qgv_point_info(struct intel_display *display,
> u16 dclk;
> int ret;
>
> - ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
> - &val, &val2);
> + ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
> + &val, &val2);
> if (ret)
> return ret;
>
> @@ -141,8 +141,8 @@ static int adls_pcode_read_psf_gv_point_info(struct intel_display *display,
> int ret;
> int i;
>
> - ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
> + ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
> if (ret)
> return ret;
>
> @@ -189,11 +189,11 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display,
> return 0;
>
> /* bspec says to keep retrying for at least 1 ms */
> - ret = intel_pcode_request(display->drm, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> - points_mask,
> - ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
> - ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
> - 1);
> + ret = intel_parent_pcode_request(display, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> + points_mask,
> + ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
> + ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
> + 1);
>
> if (ret < 0) {
> drm_err(display->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9bfbfbf34dc0..9217050a76e0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -42,8 +42,8 @@
> #include "intel_display_wa.h"
> #include "intel_dram.h"
> #include "intel_mchbar_regs.h"
> +#include "intel_parent.h"
> #include "intel_pci_config.h"
> -#include "intel_pcode.h"
> #include "intel_plane.h"
> #include "intel_psr.h"
> #include "intel_step.h"
> @@ -888,7 +888,7 @@ static void bdw_set_cdclk(struct intel_display *display,
> "trying to change cdclk frequency with cdclk not enabled\n"))
> return;
>
> - ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> + ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
> if (ret) {
> drm_err(display->drm,
> "failed to inform pcode about cdclk change\n");
> @@ -918,8 +918,8 @@ static void bdw_set_cdclk(struct intel_display *display,
> if (ret)
> drm_err(display->drm, "Switching back to LCPLL failed\n");
>
> - intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
> - cdclk_config->voltage_level);
> + intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
> + cdclk_config->voltage_level);
>
> intel_de_write(display, CDCLK_FREQ,
> DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
> @@ -1175,10 +1175,10 @@ static void skl_set_cdclk(struct intel_display *display,
> drm_WARN_ON_ONCE(display->drm,
> display->platform.skylake && vco == 8640000);
>
> - ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> + ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> if (ret) {
> drm_err(display->drm,
> "Failed to inform PCU about cdclk change (%d)\n", ret);
> @@ -1221,8 +1221,8 @@ static void skl_set_cdclk(struct intel_display *display,
> intel_de_posting_read(display, CDCLK_CTL);
>
> /* inform PCU of the change */
> - intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
> - cdclk_config->voltage_level);
> + intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> + cdclk_config->voltage_level);
>
> intel_update_cdclk(display);
> }
> @@ -2247,18 +2247,18 @@ static void bxt_set_cdclk(struct intel_display *display,
> if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> ; /* NOOP */
> else if (DISPLAY_VER(display) >= 11)
> - ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> + ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> else
> /*
> * BSpec requires us to wait up to 150usec, but that leads to
> * timeouts; the 2ms used here is based on experiment.
> */
> - ret = intel_pcode_write_timeout(display->drm,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - 0x80000000, 2);
> + ret = intel_parent_pcode_write_timeout(display,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + 0x80000000, 2);
>
> if (ret) {
> drm_err(display->drm,
> @@ -2287,8 +2287,8 @@ static void bxt_set_cdclk(struct intel_display *display,
> * Display versions 14 and beyond
> */;
> else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
> - ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
> - cdclk_config->voltage_level);
> + ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
> + cdclk_config->voltage_level);
> if (DISPLAY_VER(display) < 11) {
> /*
> * The timeout isn't specified, the 2ms used here is based on
> @@ -2296,9 +2296,9 @@ static void bxt_set_cdclk(struct intel_display *display,
> * FIXME: Waiting for the request completion could be delayed
> * until the next PCODE request based on BSpec.
> */
> - ret = intel_pcode_write_timeout(display->drm,
> - HSW_PCODE_DE_WRITE_FREQ_REQ,
> - cdclk_config->voltage_level, 2);
> + ret = intel_parent_pcode_write_timeout(display,
> + HSW_PCODE_DE_WRITE_FREQ_REQ,
> + cdclk_config->voltage_level, 2);
> }
> if (ret) {
> drm_err(display->drm,
> @@ -2598,11 +2598,11 @@ static void intel_pcode_notify(struct intel_display *display,
> if (pipe_count_update_valid)
> update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
>
> - ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
> - SKL_CDCLK_PREPARE_FOR_CHANGE |
> - update_mask,
> - SKL_CDCLK_READY_FOR_CHANGE,
> - SKL_CDCLK_READY_FOR_CHANGE, 3);
> + ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
> + SKL_CDCLK_PREPARE_FOR_CHANGE |
> + update_mask,
> + SKL_CDCLK_READY_FOR_CHANGE,
> + SKL_CDCLK_READY_FOR_CHANGE, 3);
> if (ret)
> drm_err(display->drm,
> "Failed to inform PCU about display config (err %d)\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d27397f43863..06adf6afbec0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -26,7 +26,6 @@
> #include "intel_mchbar_regs.h"
> #include "intel_parent.h"
> #include "intel_pch_refclk.h"
> -#include "intel_pcode.h"
> #include "intel_pmdemand.h"
> #include "intel_pps_regs.h"
> #include "intel_snps_phy.h"
> @@ -1260,7 +1259,7 @@ static u32 hsw_read_dcomp(struct intel_display *display)
> static void hsw_write_dcomp(struct intel_display *display, u32 val)
> {
> if (display->platform.haswell) {
> - if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val))
> + if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val))
> drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
> } else {
> intel_de_write(display, D_COMP_BDW, val);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index db185a859133..b01dda67986a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -27,7 +27,6 @@
> #include "intel_dpll.h"
> #include "intel_hotplug.h"
> #include "intel_parent.h"
> -#include "intel_pcode.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_tc.h"
> @@ -522,7 +521,7 @@ static void icl_tc_cold_exit(struct intel_display *display)
> int ret, tries = 0;
>
> while (1) {
> - ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0);
> + ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0);
> if (ret != -EAGAIN || ++tries == 3)
> break;
> msleep(1);
> @@ -1795,7 +1794,7 @@ tgl_tc_cold_request(struct intel_display *display, bool block)
> * Spec states that we should timeout the request after 200us
> * but the function below will timeout after 500us
> */
> - ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val);
> + ret = intel_parent_pcode_read(display, TGL_PCODE_TCCOLD, &low_val, &high_val);
> if (ret == 0) {
> if (block &&
> (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
> index 170de304fe96..3b9879714ea9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dram.c
> +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> @@ -13,7 +13,7 @@
> #include "intel_display_utils.h"
> #include "intel_dram.h"
> #include "intel_mchbar_regs.h"
> -#include "intel_pcode.h"
> +#include "intel_parent.h"
> #include "intel_uncore.h"
> #include "vlv_iosf_sb.h"
>
> @@ -692,8 +692,8 @@ static int icl_pcode_read_mem_global_info(struct intel_display *display,
> u32 val = 0;
> int ret;
>
> - ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> - ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
> + ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
> + ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index 7114fc405c29..8d3137067bf6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -33,7 +33,6 @@
> #include "intel_hdcp_regs.h"
> #include "intel_hdcp_shim.h"
> #include "intel_parent.h"
> -#include "intel_pcode.h"
> #include "intel_step.h"
>
> #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14)
> @@ -398,7 +397,7 @@ static int intel_hdcp_load_keys(struct intel_display *display)
> * Mailbox interface.
> */
> if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
> - ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1);
> + ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1);
> if (ret) {
> drm_err(display->drm,
> "Failed to initiate HDCP key load (%d)\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
> index 72ae553f79a4..7f73695a0444 100644
> --- a/drivers/gpu/drm/i915/display/intel_parent.c
> +++ b/drivers/gpu/drm/i915/display/intel_parent.c
> @@ -92,6 +92,28 @@ void intel_parent_pc8_unblock(struct intel_display *display)
> display->parent->pc8->unblock(display->drm);
> }
>
> +/* pcode */
> +int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1)
> +{
> + return display->parent->pcode->read(display->drm, mbox, val, val1);
> +}
> +
While moving the code, should we rename val & val1 into val1 & val2 (or
val2 & val1)? I think even renaming val -> val0 would suffice.
Or (if the comment is valid) should I send it as a separate patch?
> +int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms)
> +{
> + return display->parent->pcode->write(display->drm, mbox, val, timeout_ms);
> +}
> +
> +int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val)
> +{
> + return intel_parent_pcode_write_timeout(display, mbox, val, 1);
> +}
> +
> +int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms)
> +{
> + return display->parent->pcode->request(display->drm, mbox, request, reply_mask, reply, timeout_base_ms);
> +}
> +
> /* rps */
> bool intel_parent_rps_available(struct intel_display *display)
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
> index 47cdc14f9aa2..04782bb26b61 100644
> --- a/drivers/gpu/drm/i915/display/intel_parent.h
> +++ b/drivers/gpu/drm/i915/display/intel_parent.h
> @@ -36,6 +36,13 @@ void intel_parent_panic_finish(struct intel_display *display, struct intel_panic
> void intel_parent_pc8_block(struct intel_display *display);
> void intel_parent_pc8_unblock(struct intel_display *display);
>
> +/* pcode */
> +int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1);
If the comment above is valid, same would apply here.
> +int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms);
> +int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val);
> +int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms);
> +
> /* rps */
> bool intel_parent_rps_available(struct intel_display *display);
> void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence);
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index a6aab79812e5..b41da10f0f85 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -26,7 +26,7 @@
> #include "intel_fb.h"
> #include "intel_fixed.h"
> #include "intel_flipq.h"
> -#include "intel_pcode.h"
> +#include "intel_parent.h"
> #include "intel_plane.h"
> #include "intel_vblank.h"
> #include "intel_wm.h"
> @@ -115,9 +115,8 @@ intel_sagv_block_time(struct intel_display *display)
> u32 val = 0;
> int ret;
>
> - ret = intel_pcode_read(display->drm,
> - GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> - &val, NULL);
> + ret = intel_parent_pcode_read(display, GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> + &val, NULL);
> if (ret) {
> drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n");
> return 0;
> @@ -184,8 +183,8 @@ static void skl_sagv_enable(struct intel_display *display)
> return;
>
> drm_dbg_kms(display->drm, "Enabling SAGV\n");
> - ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL,
> - GEN9_SAGV_ENABLE);
> + ret = intel_parent_pcode_write(display, GEN9_PCODE_SAGV_CONTROL,
> + GEN9_SAGV_ENABLE);
>
> /* We don't need to wait for SAGV when enabling */
>
> @@ -217,9 +216,9 @@ static void skl_sagv_disable(struct intel_display *display)
>
> drm_dbg_kms(display->drm, "Disabling SAGV\n");
> /* bspec says to keep retrying for at least 1 ms */
> - ret = intel_pcode_request(display->drm, GEN9_PCODE_SAGV_CONTROL,
> - GEN9_SAGV_DISABLE,
> - GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1);
> + ret = intel_parent_pcode_request(display, GEN9_PCODE_SAGV_CONTROL,
> + GEN9_SAGV_DISABLE,
> + GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1);
> /*
> * Some skl systems, pre-release machines in particular,
> * don't actually have SAGV.
> @@ -3283,7 +3282,7 @@ static void skl_read_wm_latency(struct intel_display *display)
>
> /* read the first set of memory latencies[0:3] */
> val = 0; /* data0 to be programmed to 0 for first set */
> - ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
> + ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
> if (ret) {
> drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
> return;
> @@ -3296,7 +3295,7 @@ static void skl_read_wm_latency(struct intel_display *display)
>
> /* read the second set of memory latencies[4:7] */
> val = 1; /* data0 to be programmed to 1 for second set */
> - ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
> + ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
> if (ret) {
> drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
> return;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index f0105c5b49a7..b01d8fdea548 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -769,6 +769,7 @@ static const struct intel_display_parent_interface parent = {
> .irq = &i915_display_irq_interface,
> .panic = &i915_display_panic_interface,
> .pc8 = &i915_display_pc8_interface,
> + .pcode = &i915_display_pcode_interface,
> .rpm = &i915_display_rpm_interface,
> .rps = &i915_display_rps_interface,
> .stolen = &i915_display_stolen_interface,
> diff --git a/drivers/gpu/drm/i915/intel_pcode.c b/drivers/gpu/drm/i915/intel_pcode.c
> index 756652b8ec97..76c5916b28f4 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.c
> +++ b/drivers/gpu/drm/i915/intel_pcode.c
> @@ -4,6 +4,7 @@
> */
>
> #include <drm/drm_print.h>
> +#include <drm/intel/display_parent_interface.h>
>
> #include "i915_drv.h"
> #include "i915_reg.h"
> @@ -276,26 +277,31 @@ int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u3
> return err;
> }
>
> -/* Helpers with drm device */
> -int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
> +static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
Likewise, same would apply here.
> {
> struct drm_i915_private *i915 = to_i915(drm);
>
> return snb_pcode_read(&i915->uncore, mbox, val, val1);
And same would apply here.
> }
>
> -int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
> +static int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
> {
> struct drm_i915_private *i915 = to_i915(drm);
>
> return snb_pcode_write_timeout(&i915->uncore, mbox, val, timeout_ms);
> }
>
> -int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
> - u32 reply_mask, u32 reply, int timeout_base_ms)
> +static int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms)
> {
> struct drm_i915_private *i915 = to_i915(drm);
>
> return skl_pcode_request(&i915->uncore, mbox, request, reply_mask, reply,
> timeout_base_ms);
> }
> +
> +const struct intel_display_pcode_interface i915_display_pcode_interface = {
> + .read = intel_pcode_read,
> + .write = intel_pcode_write_timeout,
> + .request = intel_pcode_request,
> +};
> diff --git a/drivers/gpu/drm/i915/intel_pcode.h b/drivers/gpu/drm/i915/intel_pcode.h
> index c91a821a88d4..19795ea8172e 100644
> --- a/drivers/gpu/drm/i915/intel_pcode.h
> +++ b/drivers/gpu/drm/i915/intel_pcode.h
> @@ -27,13 +27,6 @@ int intel_pcode_init(struct intel_uncore *uncore);
> int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
> int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
>
> -/* Helpers with drm device */
> -int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
> -int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
> -#define intel_pcode_write(drm, mbox, val) \
> - intel_pcode_write_timeout((drm), (mbox), (val), 1)
> -
> -int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
> - u32 reply_mask, u32 reply, int timeout_base_ms);
> +extern const struct intel_display_pcode_interface i915_display_pcode_interface;
>
> #endif /* _INTEL_PCODE_H */
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index b39cbb756232..51a9a531fb7e 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -213,6 +213,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
> display/intel_fb_bo.o \
> display/intel_fbdev_fb.o \
> display/xe_display.o \
> + display/xe_display_pcode.o \
> display/xe_display_rpm.o \
> display/xe_display_wa.o \
> display/xe_dsb_buffer.o \
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
> deleted file mode 100644
> index 4fcd3bf6b76f..000000000000
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
> +++ /dev/null
> @@ -1,11 +0,0 @@
> -/* SPDX-License-Identifier: MIT */
> -/*
> - * Copyright © 2023 Intel Corporation
> - */
> -
> -#ifndef __INTEL_PCODE_H__
> -#define __INTEL_PCODE_H__
> -
> -#include "xe_pcode.h"
> -
> -#endif /* __INTEL_PCODE_H__ */
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index f8a831b5dc7d..182facce30ab 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -35,6 +35,7 @@
> #include "intel_hotplug.h"
> #include "intel_opregion.h"
> #include "skl_watermark.h"
> +#include "xe_display_pcode.h"
> #include "xe_display_rpm.h"
> #include "xe_hdcp_gsc.h"
> #include "xe_initial_plane.h"
> @@ -542,6 +543,7 @@ static const struct intel_display_parent_interface parent = {
> .initial_plane = &xe_display_initial_plane_interface,
> .irq = &xe_display_irq_interface,
> .panic = &xe_display_panic_interface,
> + .pcode = &xe_display_pcode_interface,
> .rpm = &xe_display_rpm_interface,
> .stolen = &xe_display_stolen_interface,
> };
> diff --git a/drivers/gpu/drm/xe/display/xe_display_pcode.c b/drivers/gpu/drm/xe/display/xe_display_pcode.c
> new file mode 100644
> index 000000000000..f6820ef7e666
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/display/xe_display_pcode.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: MIT
> +/* Copyright © 2026 Intel Corporation */
> +
> +#include <drm/intel/display_parent_interface.h>
> +
> +#include "xe_device.h"
> +#include "xe_pcode.h"
> +
> +static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
And same for here.
> +{
> + struct xe_device *xe = to_xe_device(drm);
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> +
> + return xe_pcode_read(tile, mbox, val, val1);
And same for here.
> +}
> +
> +static int xe_display_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
> +{
> + struct xe_device *xe = to_xe_device(drm);
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> +
> + return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);
> +}
> +
> +static int xe_display_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms)
> +{
> + struct xe_device *xe = to_xe_device(drm);
> + struct xe_tile *tile = xe_device_get_root_tile(xe);
> +
> + return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);
> +}
> +
> +const struct intel_display_pcode_interface xe_display_pcode_interface = {
> + .read = xe_display_pcode_read,
> + .write = xe_display_pcode_write_timeout,
> + .request = xe_display_pcode_request,
> +};
> diff --git a/drivers/gpu/drm/xe/display/xe_display_pcode.h b/drivers/gpu/drm/xe/display/xe_display_pcode.h
> new file mode 100644
> index 000000000000..58bd2fb7fb79
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/display/xe_display_pcode.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef __XE_DISPLAY_PCODE_H__
> +#define __XE_DISPLAY_PCODE_H__
> +
> +extern const struct intel_display_pcode_interface xe_display_pcode_interface;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_pcode.c b/drivers/gpu/drm/xe/xe_pcode.c
> index 0d33c14ea0cf..dc66d0c7ee06 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.c
> +++ b/drivers/gpu/drm/xe/xe_pcode.c
> @@ -348,33 +348,3 @@ int xe_pcode_probe_early(struct xe_device *xe)
> return xe_pcode_ready(xe, false);
> }
> ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */
> -
> -/* Helpers with drm device. These should only be called by the display side */
> -#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> -
> -int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
> -{
> - struct xe_device *xe = to_xe_device(drm);
> - struct xe_tile *tile = xe_device_get_root_tile(xe);
> -
> - return xe_pcode_read(tile, mbox, val, val1);
> -}
> -
> -int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
> -{
> - struct xe_device *xe = to_xe_device(drm);
> - struct xe_tile *tile = xe_device_get_root_tile(xe);
> -
> - return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);
> -}
> -
> -int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
> - u32 reply_mask, u32 reply, int timeout_base_ms)
> -{
> - struct xe_device *xe = to_xe_device(drm);
> - struct xe_tile *tile = xe_device_get_root_tile(xe);
> -
> - return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);
> -}
> -
> -#endif
> diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h
> index a5584c1c75f9..490e4f269607 100644
> --- a/drivers/gpu/drm/xe/xe_pcode.h
> +++ b/drivers/gpu/drm/xe/xe_pcode.h
> @@ -34,12 +34,4 @@ int xe_pcode_request(struct xe_tile *tile, u32 mbox, u32 request,
> | FIELD_PREP(PCODE_MB_PARAM1, param1)\
> | FIELD_PREP(PCODE_MB_PARAM2, param2))
>
> -/* Helpers with drm device */
> -int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
> -int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
> -#define intel_pcode_write(drm, mbox, val) \
> - intel_pcode_write_timeout((drm), (mbox), (val), 1)
> -int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
> - u32 reply_mask, u32 reply, int timeout_base_ms);
> -
> #endif
> diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h
> index ce946859a3a9..78f4e6744f18 100644
> --- a/include/drm/intel/display_parent_interface.h
> +++ b/include/drm/intel/display_parent_interface.h
> @@ -55,6 +55,13 @@ struct intel_display_pc8_interface {
> void (*unblock)(struct drm_device *drm);
> };
>
> +struct intel_display_pcode_interface {
> + int (*read)(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
And same for here.
Otherwise,
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
BR,
Michał
> + int (*write)(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
> + int (*request)(struct drm_device *drm, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms);
> +};
> +
> struct intel_display_rpm_interface {
> struct ref_tracker *(*get)(const struct drm_device *drm);
> struct ref_tracker *(*get_raw)(const struct drm_device *drm);
> @@ -121,6 +128,9 @@ struct intel_display_parent_interface {
> /** @pc8: PC8 interface. Optional. */
> const struct intel_display_pc8_interface *pc8;
>
> + /** @pcode: Pcode interface */
> + const struct intel_display_pcode_interface *pcode;
> +
> /** @rpm: Runtime PM functions */
> const struct intel_display_rpm_interface *rpm;
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface
2026-01-16 17:38 ` [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Michał Grzelak
@ 2026-01-19 10:14 ` Jani Nikula
2026-01-19 22:57 ` Michał Grzelak
0 siblings, 1 reply; 8+ messages in thread
From: Jani Nikula @ 2026-01-19 10:14 UTC (permalink / raw)
To: Michał Grzelak; +Cc: intel-gfx, intel-xe
On Fri, 16 Jan 2026, Michał Grzelak <michal.grzelak@intel.com> wrote:
> While moving the code, should we rename val & val1 into val1 & val2 (or
> val2 & val1)? I think even renaming val -> val0 would suffice.
The variable naming matches the register macro naming. Historically,
there was only GEN6_PCODE_DATA, and GEN6_PCODE_DATA1 was added
afterwards. Hence val and val1.
Nowadays the spec has DATA0 and DATA1, so renaming both the register
macro and the variable to DATA0 and val0, respectively, would be fine.
Just not in this patch. Generally, only do one thing at a time.
> Or (if the comment is valid) should I send it as a separate patch?
The latter.
> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Thanks,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface
2026-01-19 10:14 ` Jani Nikula
@ 2026-01-19 22:57 ` Michał Grzelak
0 siblings, 0 replies; 8+ messages in thread
From: Michał Grzelak @ 2026-01-19 22:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: Michał Grzelak, intel-gfx, intel-xe
[-- Attachment #1: Type: text/plain, Size: 1182 bytes --]
On Mon, 19 Jan 2026, Jani Nikula wrote:
> On Fri, 16 Jan 2026, Michał Grzelak <michal.grzelak@intel.com> wrote:
>> While moving the code, should we rename val & val1 into val1 & val2 (or
>> val2 & val1)? I think even renaming val -> val0 would suffice.
>
> The variable naming matches the register macro naming. Historically,
> there was only GEN6_PCODE_DATA, and GEN6_PCODE_DATA1 was added
> afterwards. Hence val and val1.
>
> Nowadays the spec has DATA0 and DATA1, so renaming both the register
> macro and the variable to DATA0 and val0, respectively, would be fine.
One question though: should the renaming include also variable from
functions which take only val as argument instead of val & val1?
E.g. should we rename val->val0 from snb_pcode_write_timeout() or
is it unnecessary?
Asking since unsure if the argument consistenly references generic
variable name or former register macro.
BR,
Michał
>
> Just not in this patch. Generally, only do one thing at a time.
>
>> Or (if the comment is valid) should I send it as a separate patch?
>
> The latter.
>
>> Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
>
> Thanks,
> Jani.
>
>
> --
> Jani Nikula, Intel
>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-01-19 22:57 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-15 11:33 [PATCH v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Jani Nikula
2026-01-15 11:39 ` ✗ CI.checkpatch: warning for drm/{i915, xe}/pcode: move display pcode calls to parent interface (rev2) Patchwork
2026-01-15 11:40 ` ✓ CI.KUnit: success " Patchwork
2026-01-15 12:15 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-15 13:20 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-16 17:38 ` [v2] drm/{i915, xe}/pcode: move display pcode calls to parent interface Michał Grzelak
2026-01-19 10:14 ` Jani Nikula
2026-01-19 22:57 ` Michał Grzelak
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox