From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
<intel-gfx@lists.freedesktop.org>
Cc: <intel-xe@lists.freedesktop.org>, <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH v9 09/17] drm/i915/display: Add DC Balance flip count operations
Date: Fri, 28 Nov 2025 19:02:58 +0530 [thread overview]
Message-ID: <41b8f2f1-39a8-44a4-a298-58e76bf07331@intel.com> (raw)
In-Reply-To: <20251127091614.648791-10-mitulkumar.ajitkumar.golani@intel.com>
On 11/27/2025 2:46 PM, Mitul Golani wrote:
> Track dc balance flip count with params per crtc. Increment
> DC Balance Flip count before every flip to indicate DMC
> firmware about new flip occurrence which needs to be adjusted
> for dc balancing. This is tracked separately from legacy
> FLIP_COUNT register also Reset DC balance flip count value
> while disabling VRR adaptive mode, this is to start with
> fresh counts when VRR adaptive refresh mode is triggered again.
>
> --v2:
> - Call during intel_update_crtc.(Ankit)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 +++
> .../gpu/drm/i915/display/intel_display_types.h | 4 ++++
> drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++++
> drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++
> 4 files changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d41ab965c013..1269f841d48b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6863,6 +6863,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_crtc_update_active_timings(new_crtc_state,
> new_crtc_state->vrr.enable);
>
> + if (new_crtc_state->vrr.dc_balance.enable)
> + intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc);
> +
> /*
> * We usually enable FIFO underrun interrupts as part of the
> * CRTC enable sequence during modesets. But when we inherit a
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 8eb0ace7d918..740c5fc9fe1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1501,6 +1501,10 @@ struct intel_crtc {
> struct intel_link_m_n m_n, m2_n2;
> } drrs;
>
> + struct {
> + u64 flip_count;
> + } dc_balance;
> +
> int scanline_offset;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index ff65c1167e1b..411ae5da3824 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -632,6 +632,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
> EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> }
>
> +void
> +intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
> + struct intel_crtc *crtc)
> +{
> + struct intel_display *display = to_intel_display(crtc_state);
> + enum pipe pipe = crtc->pipe;
> +
> + if (!crtc_state->vrr.dc_balance.enable)
> + return;
> +
> + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe),
> + ++crtc->dc_balance.flip_count);
> +}
> +
> void
> intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
> struct intel_crtc *crtc)
> @@ -642,6 +656,7 @@ intel_vrr_dcb_reset(const struct intel_crtc_state *old_crtc_state,
> if (!old_crtc_state->vrr.dc_balance.enable)
> return;
>
> + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0);
> intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index d40ed5504180..bedcc8c4bff2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -29,6 +29,8 @@ void intel_vrr_send_push(struct intel_dsb *dsb,
> const struct intel_crtc_state *crtc_state);
> void intel_vrr_check_push_sent(struct intel_dsb *dsb,
> const struct intel_crtc_state *crtc_state);
> +void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state,
> + struct intel_crtc *crtc);
> bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state);
> void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
> void intel_vrr_get_config(struct intel_crtc_state *crtc_state);
next prev parent reply other threads:[~2025-11-28 13:33 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-27 9:15 [PATCH v9 00/17] Enable/Disable DC balance along with VRR DSB Mitul Golani
2025-11-27 9:15 ` [PATCH v9 01/17] drm/i915/display: Add source param for dc balance Mitul Golani
2025-11-28 13:10 ` Nautiyal, Ankit K
2025-11-27 9:15 ` [PATCH v9 02/17] drm/i915/dmc: Add pipe dmc registers and bits for DC Balance Mitul Golani
2025-11-27 9:16 ` [PATCH v9 03/17] drm/i915/vrr: Add VRR DC balance registers Mitul Golani
2025-11-27 9:16 ` [PATCH v9 04/17] drm/i915/vrr: Add functions to read out vmin/vmax stuff Mitul Golani
2025-11-27 10:48 ` Jani Nikula
2025-12-02 7:30 ` Golani, Mitulkumar Ajitkumar
2025-11-27 9:16 ` [PATCH v9 05/17] drm/i915/vrr: Add DC Balance params to crtc_state Mitul Golani
2025-11-27 9:16 ` [PATCH v9 06/17] drm/i915/vrr: Add state dump for DC Balance params Mitul Golani
2025-11-27 9:16 ` [PATCH v9 07/17] drm/i915/vrr: Add compute config " Mitul Golani
2025-11-28 13:10 ` Nautiyal, Ankit K
2025-11-28 13:30 ` Nautiyal, Ankit K
2025-12-02 7:32 ` Golani, Mitulkumar Ajitkumar
2025-11-27 9:16 ` [PATCH v9 08/17] drm/i915/vrr: Add function to reset DC balance accumulated params Mitul Golani
2025-11-28 13:31 ` Nautiyal, Ankit K
2025-11-27 9:16 ` [PATCH v9 09/17] drm/i915/display: Add DC Balance flip count operations Mitul Golani
2025-11-28 13:32 ` Nautiyal, Ankit K [this message]
2025-11-27 9:16 ` [PATCH v9 10/17] drm/i915/vrr: Write DC balance params to hw registers Mitul Golani
2025-11-28 13:34 ` Nautiyal, Ankit K
2025-11-28 13:35 ` Nautiyal, Ankit K
2025-11-27 9:16 ` [PATCH v9 11/17] drm/i915/vblank: Extract vrr_vblank_start() Mitul Golani
2025-11-27 9:16 ` [PATCH v9 12/17] drm/i915/vrr: Implement vblank evasion with DC balancing Mitul Golani
2025-11-27 9:16 ` [PATCH v9 13/17] drm/i915/display: Wait for VRR PUSH status update Mitul Golani
2025-11-28 13:22 ` Nautiyal, Ankit K
2025-12-02 7:35 ` Golani, Mitulkumar Ajitkumar
2025-11-27 9:16 ` [PATCH v9 14/17] drm/i915/dsb: Add pipedmc dc balance enable/disable Mitul Golani
2025-11-27 9:16 ` [PATCH v9 15/17] drm/i915/vrr: Pause DC Balancing for DSB commits Mitul Golani
2025-11-27 9:16 ` [PATCH v9 16/17] drm/i915/display: Add function to configure event for dc balance Mitul Golani
2025-11-27 10:57 ` Jani Nikula
2025-12-02 7:33 ` Golani, Mitulkumar Ajitkumar
2025-11-27 9:16 ` [PATCH v9 17/17] drm/i915/vrr: Enable DC Balance Mitul Golani
2025-11-27 9:22 ` ✗ CI.checkpatch: warning for Enable/Disable DC balance along with VRR DSB Patchwork
2025-11-27 9:23 ` ✓ CI.KUnit: success " Patchwork
2025-11-27 9:38 ` ✗ CI.checksparse: warning " Patchwork
2025-11-27 10:26 ` ✓ Xe.CI.BAT: success " Patchwork
2025-11-27 11:14 ` ✓ Xe.CI.Full: " Patchwork
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