[PATCH v8 00/10] Enable CMRR in fixed-RR VRR path

[PATCH v8 00/10] Enable CMRR in fixed-RR VRR path

[Mitul Golani]

The existing CMRR fractional-timing code was permanently
disabled (if (!HAS_CMRR || true)), eDP-only, and relied
on a heuristic to guess when the fractional path was needed.
This series reworks it into a generic, debugfs-driven feature,
which later will be controlled via userspace when respective
uapi will be in-palce.

Mitul Golani (10):
  drm/i915/psr: Do not enable PSR2 when CMRR is enabled
  drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default
    platforms
  drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control
  drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config
    request
  drm/i915/display: Move CMRR crtc_state members under VRR
  drm/i915/vrr: Compute CMRR fractional timings generically
  drm/i915/vrr: Latch CMRR ratio via atomic commit on debugfs write
  drm/i915/vrr: Program CMRR enable/disable from transcoder timings
  drm/i915/vrr: Dump CMRR state in the crtc state dump
  drm/i915/vrr: Enable cmrr

 drivers/gpu/drm/i915/display/intel_cmtg.c     |   2 +-
 .../drm/i915/display/intel_crtc_state_dump.c  |   3 +
 drivers/gpu/drm/i915/display/intel_display.c  |  10 +-
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |  17 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   9 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |   6 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 393 ++++++++++++++----
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 9 files changed, 345 insertions(+), 99 deletions(-)

-- 
2.48.1

[PATCH v8 01/10] drm/i915/psr: Do not enable PSR2 when CMRR is enabled

[Mitul Golani]

CMRR is mutually exclusive to PSR2, do not enable PSR2 when CMRR is
enabled.

--v2:
- Restrict selective update config check (Ankit)
- Commit message change

--v3:
- Commit changes

--v4:
- Add check to psr2_config_valid (Jouni)

--v5:
- Correct debug message

--v6:
- Commit message update

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 40e3d7095996..410778e73a2d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1491,6 +1491,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 
+	if (crtc_state->cmrr.enable) {
+		drm_dbg_kms(display->drm,
+			    "PSR2 cannot be enabled when CMRR is enabled\n");
+		return false;
+	}
+
 	if (!connector->dp.psr_caps.su_support || display->params.enable_psr == 1)
 		return false;
 
-- 
2.48.1

[PATCH v8 02/10] drm/i915/vrr: Restrict CMRR enable condition to VRR-TG-default platforms

[Mitul Golani]

CMRR is currently advertised on all HAS_CMRR platforms, but it depends
on the VRR timing generator being the default timing generator, which
currently only applies to DISPLAY_VER >= 30.

Gate the CMRR enable condition and readout accordingly so CMRR is only
reported on supported platforms.

No functional change.

--v2:
- Create a separate function to check if CMRR possible

--v3:
- Simplify commit message (Chaitanya)
- Remove redundant outer parenthesis (Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..b0c9101e6ed3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -187,15 +187,21 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_vmax_vtotal(crtc_state) - crtc_state->vrr.guardband;
 }
 
+static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display);
+}
+
 static bool
 is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	/* Avoid CMRR for now till we have VRR with fixed timings working */
-	if (!HAS_CMRR(display) || true)
+	if (!intel_vrr_cmrr_possible(crtc_state) || true)
 		return false;
 
 	actual_refresh_k =
@@ -1066,7 +1072,7 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 	trans_vrr_ctl = intel_de_read(display,
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
-	if (HAS_CMRR(display))
+	if (intel_vrr_cmrr_possible(crtc_state))
 		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
 
 	if (crtc_state->cmrr.enable) {
-- 
2.48.1

[PATCH v8 03/10] drm/i915/vrr: Add per-CRTC vrr/cmrr debugfs control

[Mitul Golani]

Add a per-CRTC debugfs file 'intel_vrr_target_refresh_rate' that lets
the user force a CMRR target refresh rate and video-mode requirement.

The file uses a "numerator/denominator" format:
  - numerator:   requested refresh rate in milli-Hz
                 (refresh rate in Hz * 1000, e.g. 60000 for 60 Hz)
  - denominator: 1000 for a 1:1 ratio (no video timing) or
                 1001 for the 1000/1001 video timing

Reading the file reports the currently stored values; writing updates
them. The file is created only on platforms with VRR and CMRR support.

--v2:
- Drop the "vrr" debugfs subdirectory and expose a single flat,
  intel_-prefixed "intel_vrr_cmrr" file (Jani, Nikula)
- Rename struct intel_crtc.cmrr to force_cmrr to make its purpose
  explicit (Chaitanya)
- Fix parse comment: numerator unit is milli-Hz, not KHz (Chaitanya)
- Add debugfs/intel_ prefixes to the debugfs handler functions (Chaitanya)
- Expand commit message with debugfs entry semantics (Chaitanya)

--v3:
- Rename debugfs function and file name (Chaitanya)
- Remove railing new line at EOF (Chaitanya)
- Update CMRR guard conditions (Chaitanya)
- Add 0/0 default case. (Ramanaidu)

--v4:
- Correct CMRR guard check while creating debugfs

--v5:
- Commit message update (Chaitanya)
- Add support for 0/0 writing (Validation)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |   2 +
 .../drm/i915/display/intel_display_types.h    |   5 +
 drivers/gpu/drm/i915/display/intel_vrr.c      | 112 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.h      |   2 +
 4 files changed, 121 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3f02868ef105..2bbf4760dc30 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -49,6 +49,7 @@
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
 #include "intel_vdsc.h"
+#include "intel_vrr.h"
 #include "intel_wm.h"
 #include "intel_tc.h"
 
@@ -1395,6 +1396,7 @@ void intel_crtc_debugfs_add(struct intel_crtc *crtc)
 	intel_drrs_crtc_debugfs_add(crtc);
 	intel_fbc_crtc_debugfs_add(crtc);
 	hsw_ips_crtc_debugfs_add(crtc);
+	intel_vrr_crtc_debugfs_add(crtc);
 
 	debugfs_create_file("i915_current_bpc", 0444, root, crtc,
 			    &i915_current_bpc_fops);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..46dd980b315a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1553,6 +1553,11 @@ struct intel_crtc {
 		u64 flip_count;
 	} dc_balance;
 
+	struct {
+		u32 numerator;
+		u32 denominator;
+	} force_cmrr;
+
 	int scanline_offset;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index b0c9101e6ed3..615c8fa8c063 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -4,6 +4,10 @@
  *
  */
 
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/string.h>
+
 #include <drm/drm_print.h>
 #include <drm/intel/step.h>
 
@@ -1237,3 +1241,111 @@ int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_st
 
 	return intel_vrr_vblank_start(crtc_state, VRR_DCB_VMAX(tmp) + 1);
 }
+
+static
+int intel_vrr_cmrr_parse_ratio(char *str, u32 *numerator, u32 *denominator)
+{
+	char *sep;
+	int ret;
+
+	/*
+	 * Parse a "numerator/denominator" CMRR ratio string. The numerator
+	 * is the requested refresh rate in milli-Hz (refresh rate in Hz * 1000)
+	 * and the denominator selects the timing: 1000 for a 1:1 ratio
+	 * (no video timing) or 1001 for the 1000/1001 video timing.
+	 */
+
+	sep = strchr(str, '/');
+	if (!sep)
+		return -EINVAL;
+
+	*sep = '\0';
+
+	ret = kstrtou32(strim(str), 10, numerator);
+	if (ret)
+		return ret;
+
+	ret = kstrtou32(strim(sep + 1), 10, denominator);
+	if (ret)
+		return ret;
+	/*
+	 * "0/0" clears any previously configured CMRR override.
+	 * A zero numerator already means "CMRR not requested" in
+	 * intel_vrr_cmrr_compute_config(), so just let it through.
+	 */
+	if (*numerator == 0 && *denominator == 0)
+		return 0;
+
+	if (*numerator == 0)
+		return -EINVAL;
+
+	if (*denominator != 1000 && *denominator != 1001)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int intel_vrr_debugfs_target_rr_show(struct seq_file *m, void *data)
+{
+	struct intel_crtc *crtc = m->private;
+
+	seq_printf(m, "%u/%u\n", crtc->force_cmrr.numerator, crtc->force_cmrr.denominator);
+
+	return 0;
+}
+
+static int intel_vrr_debugfs_target_rr_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, intel_vrr_debugfs_target_rr_show, inode->i_private);
+}
+
+static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char __user *ubuf,
+						 size_t len, loff_t *offp)
+{
+	struct seq_file *m = file->private_data;
+	struct intel_crtc *crtc = m->private;
+	u32 numerator, denominator;
+	char kbuf[32];
+	int ret;
+
+	if (len >= sizeof(kbuf))
+		return -EINVAL;
+
+	if (copy_from_user(kbuf, ubuf, len))
+		return -EFAULT;
+
+	kbuf[len] = '\0';
+
+	ret = intel_vrr_cmrr_parse_ratio(kbuf, &numerator, &denominator);
+	if (ret)
+		return ret;
+
+	if (crtc->force_cmrr.numerator == numerator &&
+	    crtc->force_cmrr.denominator == denominator)
+		return len;
+
+	crtc->force_cmrr.numerator = numerator;
+	crtc->force_cmrr.denominator = denominator;
+
+	return len;
+}
+
+static const struct file_operations intel_vrr_debugfs_target_rr_fops = {
+	.owner = THIS_MODULE,
+	.open = intel_vrr_debugfs_target_rr_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+	.write = intel_vrr_debugfs_target_rr_write,
+};
+
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc)
+{
+	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
+
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
+
+	debugfs_create_file("intel_vrr_target_refresh_rate", 0600, crtc->base.debugfs_entry,
+			    crtc, &intel_vrr_debugfs_target_rr_fops);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 55e9c429f579..19c7990be1b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -56,4 +56,6 @@ int intel_vrr_dcb_vmax_vblank_start_next(const struct intel_crtc_state *crtc_sta
 int intel_vrr_dcb_vmin_vblank_start_final(const struct intel_crtc_state *crtc_state);
 int intel_vrr_dcb_vmax_vblank_start_final(const struct intel_crtc_state *crtc_state);
 
+void intel_vrr_crtc_debugfs_add(struct intel_crtc *crtc);
+
 #endif /* __INTEL_VRR_H__ */
-- 
2.48.1

[PATCH v8 04/10] drm/i915/vrr: Update AS_SDP target_rr_divider based on CMRR config request

[Mitul Golani]

Compute AS_SDP target_rr_divider based on actual CMRR request
requirement.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 113d767e62e9..9e2db310b7d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3125,6 +3125,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	/*
 	 * #FIXME: SDP/infoframe updates aren’t truly atomic, and with the new
@@ -3145,7 +3146,11 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	if (crtc_state->cmrr.enable) {
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
-		as_sdp->target_rr_divider = true;
+
+		if (crtc->force_cmrr.denominator == 1001)
+			as_sdp->target_rr_divider = true;
+		else
+			as_sdp->target_rr_divider = false;
 	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
 	} else {
-- 
2.48.1

[PATCH v8 05/10] drm/i915/display: Move CMRR crtc_state members under VRR

[Mitul Golani]

Move CMRR crtc state members under VRR infrastructure as
it is enabled during fixed-refresh-rate VRR timing generator
is enabled.

--v2:
- Move cmrr structure under vrr umbrella.
- Remove dups. (Jani)

--v3:
- Update commit message

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_display.c  | 10 +++----
 .../drm/i915/display/intel_display_types.h    | 12 ++++----
 drivers/gpu/drm/i915/display/intel_dp.c       |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 30 +++++++++----------
 6 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c8e0f90af910..3c0f5b2fb2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -326,7 +326,7 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
 
 	/* TODO: The code below may need to be revisited once CMRR is enabled */
-	if (crtc_state->cmrr.enable)
+	if (crtc_state->vrr.cmrr.enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cmtg_transcoder), vrr_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9dfd095f325f..8ce762188665 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -950,8 +950,8 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 				const struct intel_crtc_state *new_crtc_state)
 {
-	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
-		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+	return old_crtc_state->vrr.cmrr.cmrr_m != new_crtc_state->vrr.cmrr.cmrr_m ||
+		old_crtc_state->vrr.cmrr.cmrr_n != new_crtc_state->vrr.cmrr.cmrr_n;
 }
 
 static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
@@ -5536,9 +5536,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.flipline);
 		PIPE_CONF_CHECK_I(vrr.vsync_start);
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
-		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
-		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
-		PIPE_CONF_CHECK_BOOL(cmrr.enable);
+		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_m);
+		PIPE_CONF_CHECK_LLI(vrr.cmrr.cmrr_n);
+		PIPE_CONF_CHECK_BOOL(vrr.cmrr.enable);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
 		PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 46dd980b315a..20a07ea06b5e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1408,13 +1408,13 @@ struct intel_crtc_state {
 			u16 max_increase, max_decrease;
 			u16 vblank_target;
 		} dc_balance;
-	} vrr;
 
-	/* Content Match Refresh Rate state */
-	struct {
-		bool enable;
-		u64 cmrr_n, cmrr_m;
-	} cmrr;
+		/* Content Match Refresh Rate state */
+		struct {
+			bool enable;
+			u64 cmrr_n, cmrr_m;
+		} cmrr;
+	} vrr;
 
 	/* Stream Splitter for eDP MSO */
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9e2db310b7d8..7f13595f40c1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3143,7 +3143,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	as_sdp->revision = 0x2;
 	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 410778e73a2d..52836496040f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1491,7 +1491,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay;
 	int psr_max_h = 0, psr_max_v = 0, max_bpp = 0;
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		drm_dbg_kms(display->drm,
 			    "PSR2 cannot be enabled when CMRR is enabled\n");
 		return false;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 615c8fa8c063..6d3333fd5281 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -235,12 +235,12 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
 		multiplier_n = 1000;
 	}
 
-	crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-					      multiplier_n);
+	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
+						  multiplier_n);
 	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->cmrr.cmrr_n);
+				  crtc_state->vrr.cmrr.cmrr_n);
 	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n);
+	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
 
 	return vtotal;
 }
@@ -258,7 +258,7 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
 	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
 	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
 
-	crtc_state->cmrr.enable = true;
+	crtc_state->vrr.cmrr.enable = true;
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
 
@@ -651,15 +651,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->cmrr.enable) {
+	if (crtc_state->vrr.cmrr.enable) {
 		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
 		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
 	}
 
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
@@ -980,7 +980,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
+		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1077,12 +1077,12 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 				      TRANS_VRR_CTL(display, cpu_transcoder));
 
 	if (intel_vrr_cmrr_possible(crtc_state))
-		crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
+		crtc_state->vrr.cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE);
 
-	if (crtc_state->cmrr.enable) {
-		crtc_state->cmrr.cmrr_n =
+	if (crtc_state->vrr.cmrr.enable) {
+		crtc_state->vrr.cmrr.cmrr_n =
 			intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder));
-		crtc_state->cmrr.cmrr_m =
+		crtc_state->vrr.cmrr.cmrr_m =
 			intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder));
 	}
 
-- 
2.48.1

[PATCH v8 06/10] drm/i915/vrr: Compute CMRR fractional timings generically

[Mitul Golani]

Rework the fractional CMRR computation into a generic,
transcoder-agnostic helper driven by an explicit per-CRTC debugfs
target, replacing the previous disabled, eDP-only code path. Compute
CMRR_M and CMRR_N timings based on the video mode requirements. A 1:1
ratio (denominator == 1000) means no video timing is required. Note
that the CMRR enable path is wired up separately; this patch only lays
down the generic computation.

Remove computation of mode_flags, I915_MODE_FLAG_VRR, as CMRR is
being moved to the fixed refresh rate path. Also return early from
the CMRR computation if the existing computation is already sufficient.

--v2:
- Derive video_mode locally instead of caching it in the persistent
  struct intel_crtc state (Jani, Chaitanya)
- Fix numerator unit in comment: milli-Hz, not kHz (Chaitanya)
- Fix "requirement" typo and clarify that CMRR is not yet enabled in
  the commit message (Chaitanya)
- Fix precision issue while computing the M/N ratio (Chaitanya)
- Rename multiplier_m and multiplier_n to improve readability
  (Chaitanya)
- Compute vtotal as it is required for dithering as per the algorithm
  implementation (Chaitanya)
- Replace the misleading adjusted_pixel_rate with dividend, which is
  more descriptive

--v3:
- Mention the rationale for not computing I915_MODE_FLAG_VRR
  (Chaitanya)
- Remove the redundant return statement at the end of the CMRR
  computation (Chaitanya)
- Correct cmrr_n calculation (Chaitanya)
- Add an early return if the current computation is already sufficient
  to drive the mode without CMRR (Chaitanya)
- Round up requested_refresh_rate (Validation)
- Fix integer overflow

--v4:
- Update cmrr_n calculation to avoid aggressive dithering
- Use div64_u64 to truncate to the floor value instead of
  DIV_ROUND_UP_ULL, which rounds up to the ceiling value
- Add a TODO comment to the cmrr_n calculation
- Add a condition for custom refresh rate requests
- Update the CMRR computation comment block in compute_config

--v5:
- Simplify computation
- Correct typo in commit message (Chaitanya)
- Compute early return condition (Chaitanya)

--v6:
- Simplify commit message
- Simplify video timing requirement compute function (Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 135 ++++++++++++-----------
 1 file changed, 70 insertions(+), 65 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6d3333fd5281..f406f34b816e 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -27,9 +27,6 @@
 #include "skl_prefill.h"
 #include "skl_watermark.h"
 
-#define FIXED_POINT_PRECISION		100
-#define CMRR_PRECISION_TOLERANCE	10
-
 /*
  * Tunable parameters for DC Balance correction.
  * These are captured based on experimentations.
@@ -198,68 +195,78 @@ static bool intel_vrr_cmrr_possible(const struct intel_crtc_state *crtc_state)
 	return HAS_CMRR(display) && intel_vrr_always_use_vrr_tg(display);
 }
 
-static bool
-is_cmrr_frac_required(struct intel_crtc_state *crtc_state)
+static void
+intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 {
-	int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line;
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	u64 dividend;
+	u32 mode_rate_mhz;
+	u32 requested_rate_mhz = crtc->force_cmrr.numerator;
+	bool video_mode = crtc->force_cmrr.denominator != 1000;
+	int rr_multiplier = video_mode ? 1000 : 1;
+	int rr_divider = video_mode ? 1001 : 1;
 
-	/* Avoid CMRR for now till we have VRR with fixed timings working */
-	if (!intel_vrr_cmrr_possible(crtc_state) || true)
-		return false;
-
-	actual_refresh_k =
-		drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION;
-	pixel_clock_per_line =
-		adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal;
-	calculated_refresh_k =
-		pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal;
-
-	if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE)
-		return false;
-
-	return true;
-}
-
-static unsigned int
-cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required)
-{
-	int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate;
-	u64 adjusted_pixel_rate;
-	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
 
-	desired_refresh_rate = drm_mode_vrefresh(adjusted_mode);
+	/* No CMRR ratio configured through debugfs */
+	if (!requested_rate_mhz)
+		return;
 
-	if (video_mode_required) {
-		multiplier_m = 1001;
-		multiplier_n = 1000;
+	/* Requested rate must match the mode's nominal (integer) refresh rate */
+	if (DIV_ROUND_CLOSEST(requested_rate_mhz, 1000) !=
+			drm_mode_vrefresh(adjusted_mode)) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] CMRR requested %u.%03u Hz doesn't match mode %d Hz\n",
+			    crtc->base.base.id, crtc->base.name,
+			    requested_rate_mhz / 1000, requested_rate_mhz % 1000,
+			    drm_mode_vrefresh(adjusted_mode));
+		return;
 	}
 
-	crtc_state->vrr.cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal,
-						  multiplier_n);
-	vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n),
-				  crtc_state->vrr.cmrr.cmrr_n);
-	adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m);
-	crtc_state->vrr.cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->vrr.cmrr.cmrr_n);
-
-	return vtotal;
-}
+	/* Actual rate produced by the current timings, in milli-Hz */
+	mode_rate_mhz =
+		DIV_ROUND_CLOSEST_ULL((u64)adjusted_mode->crtc_clock * 1000 * 1000,
+				      adjusted_mode->crtc_vtotal *
+				      adjusted_mode->crtc_htotal);
 
-static
-void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state)
-{
 	/*
-	 * TODO: Compute precise target refresh rate to determine
-	 * if video_mode_required should be true. Currently set to
-	 * false due to uncertainty about the precise target
-	 * refresh Rate.
+	 * 1:1 request already satisfied by the mode -> CMRR not needed.
 	 */
-	crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false);
-	crtc_state->vrr.vmin = crtc_state->vrr.vmax;
-	crtc_state->vrr.flipline = crtc_state->vrr.vmin;
+	if (!video_mode && DIV_ROUND_CLOSEST(mode_rate_mhz, 10) ==
+	    DIV_ROUND_CLOSEST(requested_rate_mhz, 10)) {
+		drm_dbg_kms(display->drm,
+			    "[CRTC:%d:%s] %u.%03u Hz can be driven without CMRR\n",
+			    crtc->base.base.id, crtc->base.name,
+			    requested_rate_mhz / 1000, requested_rate_mhz % 1000);
+		return;
+	}
 
-	crtc_state->vrr.cmrr.enable = true;
-	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+	/*
+	 * Let pixel_clock_hz = adjusted_mode->crtc_clock * 1000.
+	 *
+	 * cmrr_n = (requested_rate_mhz x htotal x rr_multiplier) / 1000
+	 * cmrr_m = (pixel_clock_hz x rr_divider) % cmrr_n
+	 *
+	 * where requested_rate_mhz is the requested refresh rate in milli-Hz
+	 * and rr_multiplier/rr_divider = 1000/1001 when the video timing
+	 * is required, else 1/1. The integer vtotal term is tracked in SW
+	 * (it is the programmed mode vtotal) while the fractional part
+	 * represented by cmrr_m/cmrr_n is tracked in HW.
+	 *
+	 * TODO: Using the actual desired rate for cmrr_n in video
+	 * mode produces more aggressive vtotal dithering than
+	 * expected; revisit once the Bspec algorithm is clarified.
+	 */
+	crtc_state->vrr.cmrr.cmrr_n =
+		div64_u64((u64)requested_rate_mhz *
+			  adjusted_mode->crtc_htotal * rr_multiplier, 1000);
+	dividend = (u64)adjusted_mode->crtc_clock * rr_divider * 1000;
+	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
+						   crtc_state->vrr.cmrr.cmrr_n,
+						   &crtc_state->vrr.cmrr.cmrr_m);
 }
 
 static
@@ -435,8 +442,6 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
-	struct intel_dp *intel_dp = intel_attached_dp(connector);
-	bool is_edp = intel_dp_is_edp(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int vmin, vmax;
 
@@ -470,12 +475,17 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		vmax = vmin;
 	}
 
-	if (crtc_state->uapi.vrr_enabled && vmin < vmax)
+	if (crtc_state->uapi.vrr_enabled && vmin < vmax) {
 		intel_vrr_compute_vrr_timings(crtc_state, vmin, vmax);
-	else if (is_cmrr_frac_required(crtc_state) && is_edp)
-		intel_vrr_compute_cmrr_timings(crtc_state);
-	else
+	} else {
+		/*
+		 * CMRR is a fixed average Vtotal mode and is only computed on
+		 * the fixed refresh rate path. It is generic across transcoders
+		 * and gated on platform support and a valid debugfs ratio.
+		 */
+		intel_vrr_cmrr_compute_config(crtc_state);
 		intel_vrr_compute_fixed_rr_timings(crtc_state);
+	}
 
 	if (HAS_AS_SDP(display)) {
 		crtc_state->vrr.vsync_start =
@@ -1142,11 +1152,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	intel_vrr_get_dc_balance_config(crtc_state);
 
-	/*
-	 * #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for mode_flags.
-	 * Since CMRR is currently disabled, set this flag for VRR for now.
-	 * Need to keep this in mind while re-enabling CMRR.
-	 */
 	if (crtc_state->vrr.enable)
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 
-- 
2.48.1

[PATCH v8 07/10] drm/i915/vrr: Latch CMRR ratio via atomic commit on debugfs write

[Mitul Golani]

Writing the per-CRTC "intel_vrr_target_refresh_rate" debugfs file only
updates crtc->force_cmrr, a side channel that is not tracked by the
atomic state. The requested ratio therefore does not reach the hardware
until some unrelated commit recomputes the pipe config.

Kick an internal atomic commit for the CRTC from the debugfs write and
mark the CRTC mode as changed so the pipe config is recomputed.

Note that this commit may or may not be downgraded to a fastset,
depending on whether the computed vblank value (with LRR disabled)
changes, so it is not characterised as a fastset.

If the commit fails, restore the previous numerator/denominator so that
force_cmrr does not hold on to bad values, which would otherwise make
all subsequent commits fail.

--v2:
- Commit message and code comment update (Chaitanya)
- Commit header update
- Restore to old known debugfs values when commit fails
(Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 77 ++++++++++++++++++++++++
 1 file changed, 77 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index f406f34b816e..3463533b1ea1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -8,10 +8,12 @@
 #include <linux/seq_file.h>
 #include <linux/string.h>
 
+#include <drm/drm_atomic.h>
 #include <drm/drm_print.h>
 #include <drm/intel/step.h>
 
 #include "intel_alpm.h"
+#include "intel_atomic.h"
 #include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
@@ -1304,12 +1306,67 @@ static int intel_vrr_debugfs_target_rr_open(struct inode *inode, struct file *fi
 	return single_open(file, intel_vrr_debugfs_target_rr_show, inode->i_private);
 }
 
+/*
+ * Force an internal commit on @crtc so that a CMRR ratio programmed
+ * via debugfs gets recomputed and latched into hardware.
+ *
+ * CMRR only alters the (average) vtotal. Depending on whether the
+ * computed vblank value (with LRR disabled) changes, this commit may or
+ * may not be downgraded to a fastset.
+ */
+static int intel_vrr_cmrr_commit_force(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct drm_modeset_acquire_ctx ctx;
+	struct drm_atomic_commit *state;
+	struct intel_crtc_state *crtc_state;
+	int ret = 0;
+
+	state = drm_atomic_commit_alloc(display->drm);
+	if (!state)
+		return -ENOMEM;
+
+	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
+
+	state->acquire_ctx = &ctx;
+	to_intel_atomic_state(state)->internal = true;
+
+retry:
+	crtc_state = intel_atomic_get_crtc_state(state, crtc);
+	if (IS_ERR(crtc_state)) {
+		ret = PTR_ERR(crtc_state);
+		goto out;
+	}
+
+	if (!crtc_state->hw.active)
+		goto out;
+
+	/* Mark mode as changed to trigger a pipe recompute + update() */
+	crtc_state->uapi.mode_changed = true;
+
+	ret = drm_atomic_commit(state);
+out:
+	if (ret == -EDEADLK) {
+		drm_atomic_commit_clear(state);
+		ret = drm_modeset_backoff(&ctx);
+		if (!ret)
+			goto retry;
+	}
+
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+	drm_atomic_commit_put(state);
+
+	return ret;
+}
+
 static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char __user *ubuf,
 						 size_t len, loff_t *offp)
 {
 	struct seq_file *m = file->private_data;
 	struct intel_crtc *crtc = m->private;
 	u32 numerator, denominator;
+	u32 old_numerator, old_denominator;
 	char kbuf[32];
 	int ret;
 
@@ -1329,9 +1386,29 @@ static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char _
 	    crtc->force_cmrr.denominator == denominator)
 		return len;
 
+	old_numerator = crtc->force_cmrr.numerator;
+	old_denominator = crtc->force_cmrr.denominator;
+
 	crtc->force_cmrr.numerator = numerator;
 	crtc->force_cmrr.denominator = denominator;
 
+	/*
+	 * The debugfs value is a side channel that is not tracked by the atomic
+	 * state, so kick an internal commit to recompute and latch the
+	 * new CMRR parameters.
+	 */
+	ret = intel_vrr_cmrr_commit_force(crtc);
+	if (ret) {
+		/*
+		 * Restore the last known good ratio so that force_cmrr does not
+		 * hold on to bad values, which would make all subsequent commits
+		 * fail.
+		 */
+		crtc->force_cmrr.numerator = old_numerator;
+		crtc->force_cmrr.denominator = old_denominator;
+		return ret;
+	}
+
 	return len;
 }
 
-- 
2.48.1

[PATCH v8 08/10] drm/i915/vrr: Program CMRR enable/disable from transcoder timings

[Mitul Golani]

Move the CMRR M/N register writes into a new
intel_vrr_set_cmrr_timings() helper called from
intel_vrr_set_fixed_rr_timings(), so CMRR is programmed together with
the fixed rr timings for both the CMTG and CPU transcoder, instead of
being open-coded in intel_vrr_set_transcoder_timings(). Drop the
now-unused cmrr_enable argument to intel_vrr_tg_enable().

No functional change intended for non-CMRR configurations.

--v2:
- Commit message changes.
- Added Simplified enable/disable sequence. (Chaitanya)

--v3:
- Guard CMRR enable condition (Chaitanya)
- Comment changes updated (Chaitanya)
- Squash register write commits together and
avoid double writing issue. (Chaitanya)

--v4:
- Guard CMRR enable/disable with platform check

--v5:
- Update CMRR in enable/disable path

--v6:
- Simplify enable/disable calls (Chaitanya)
- Make function usable for common cmtg and cpu transcoder
(Chaitanya)

--v7:
- Update commit message (Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Assisted-by: Claude:claude-opus-4-8
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 59 ++++++++++++++++--------
 1 file changed, 40 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 3463533b1ea1..653581ed4e90 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -344,6 +344,36 @@ int intel_vrr_fixed_rr_hw_flipline(const struct intel_crtc_state *crtc_state)
 	return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
 }
 
+static void
+intel_vrr_set_cmrr_timings(const struct intel_crtc_state *crtc_state,
+			   enum transcoder transcoder)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!intel_vrr_cmrr_possible(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_CMRR_M_HI(display, transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_M_LO(display, transcoder),
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+	intel_de_write(display, TRANS_CMRR_N_LO(display, transcoder),
+		       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+	intel_de_write(display, TRANS_CMRR_N_HI(display, transcoder),
+		       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+
+	/*
+	 * On always-VRR-TG platforms the fastset path does not rewrite the
+	 * whole TRANS_VRR_CTL, so RMW only the CMRR enable bit here. On a
+	 * modeset the authoritative writes (intel_vrr_tg_enable(),
+	 * intel_cmtg_set_vrr_ctl()) carry the same bit, so this stays
+	 * consistent.
+	 */
+	intel_de_rmw(display, TRANS_VRR_CTL(display, transcoder),
+		     VRR_CTL_CMRR_ENABLE,
+		     crtc_state->vrr.cmrr.enable ? VRR_CTL_CMRR_ENABLE : 0);
+}
+
 void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
 				    enum transcoder transcoder)
 {
@@ -352,6 +382,8 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
+	intel_vrr_set_cmrr_timings(crtc_state, transcoder);
+
 	intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
 		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
@@ -663,17 +695,6 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
-	if (crtc_state->vrr.cmrr.enable) {
-		intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
-		intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
-			       upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-		intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
-			       lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
-	}
-
 	intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
 	intel_cmtg_set_vrr_timings(crtc_state);
 
@@ -939,8 +960,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
-static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
-				bool cmrr_enable)
+static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -952,11 +972,12 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
 	/*
-	 * FIXME this might be broken as bspec seems to imply that
-	 * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
-	 * when enabling CMRR (but not when disabling CMRR?).
+	 * This full TRANS_VRR_CTL write is the authoritative one, so it must
+	 * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing TRANS_CMRR_N_HI
+	 * arms the bit in hardware, but this later write would otherwise clear
+	 * it again.
 	 */
-	if (cmrr_enable)
+	if (crtc_state->vrr.cmrr.enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
@@ -992,7 +1013,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 	intel_vrr_enable_dc_balancing(crtc_state);
 
 	if (!intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
+		intel_vrr_tg_enable(crtc_state);
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1019,7 +1040,7 @@ void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state)
 		return;
 
 	if (intel_vrr_always_use_vrr_tg(display))
-		intel_vrr_tg_enable(crtc_state, false);
+		intel_vrr_tg_enable(crtc_state);
 }
 
 void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.48.1

[PATCH v8 09/10] drm/i915/vrr: Dump CMRR state in the crtc state dump

[Mitul Golani]

Add crtc state dump for CMRR.

--v2:
- Remove video mode state checker.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4493483f10a9..ad4f362e0c09 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -311,6 +311,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->vrr.dc_balance.max_increase,
 		   pipe_config->vrr.dc_balance.max_decrease,
 		   pipe_config->vrr.dc_balance.vblank_target);
+	drm_printf(&p, "cmrr: %s, cmrr_m: %llu, cmrr_n: %llu\n",
+		   str_yes_no(pipe_config->vrr.cmrr.enable),
+		   pipe_config->vrr.cmrr.cmrr_m, pipe_config->vrr.cmrr.cmrr_n);
 
 	drm_printf(&p, "requested mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.mode));
-- 
2.48.1

[PATCH v8 10/10] drm/i915/vrr: Enable cmrr

[Mitul Golani]

Set crtc_state->vrr.cmrr.enable at the end of
intel_vrr_cmrr_compute_config() so that CMRR is actually enabled once
the M/N parameters have been computed. This is the final step that
turns on CMRR, with all the parameter computation handled in the
earlier patches.

--v2:
- Everything else except enable compute to handle before this patch
(Chaitanya)

--v3:
- Remove redundant return from compute config

--v4:
- Update CMRR commit message (Chaitanya)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 653581ed4e90..e36db1174440 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -269,6 +269,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
 	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
 						   crtc_state->vrr.cmrr.cmrr_n,
 						   &crtc_state->vrr.cmrr.cmrr_m);
+
+	crtc_state->vrr.cmrr.enable = true;
 }
 
 static
-- 
2.48.1

✓ CI.KUnit: success for Enable CMRR in fixed-RR VRR path (rev8)

[Patchwork]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev8)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:56:51] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:56:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:57:27] Starting KUnit Kernel (1/1)...
[11:57:27] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:57:27] ================== guc_buf (11 subtests) ===================
[11:57:27] [PASSED] test_smallest
[11:57:27] [PASSED] test_largest
[11:57:27] [PASSED] test_granular
[11:57:27] [PASSED] test_unique
[11:57:27] [PASSED] test_overlap
[11:57:27] [PASSED] test_reusable
[11:57:27] [PASSED] test_too_big
[11:57:27] [PASSED] test_flush
[11:57:27] [PASSED] test_lookup
[11:57:27] [PASSED] test_data
[11:57:27] [PASSED] test_class
[11:57:27] ===================== [PASSED] guc_buf =====================
[11:57:27] =================== guc_dbm (7 subtests) ===================
[11:57:27] [PASSED] test_empty
[11:57:27] [PASSED] test_default
[11:57:27] ======================== test_size  ========================
[11:57:27] [PASSED] 4
[11:57:27] [PASSED] 8
[11:57:27] [PASSED] 32
[11:57:27] [PASSED] 256
[11:57:27] ==================== [PASSED] test_size ====================
[11:57:27] ======================= test_reuse  ========================
[11:57:27] [PASSED] 4
[11:57:27] [PASSED] 8
[11:57:27] [PASSED] 32
[11:57:27] [PASSED] 256
[11:57:27] =================== [PASSED] test_reuse ====================
[11:57:27] =================== test_range_overlap  ====================
[11:57:27] [PASSED] 4
[11:57:27] [PASSED] 8
[11:57:27] [PASSED] 32
[11:57:27] [PASSED] 256
[11:57:27] =============== [PASSED] test_range_overlap ================
[11:57:27] =================== test_range_compact  ====================
[11:57:27] [PASSED] 4
[11:57:27] [PASSED] 8
[11:57:27] [PASSED] 32
[11:57:27] [PASSED] 256
[11:57:27] =============== [PASSED] test_range_compact ================
[11:57:27] ==================== test_range_spare  =====================
[11:57:27] [PASSED] 4
[11:57:27] [PASSED] 8
[11:57:27] [PASSED] 32
[11:57:27] [PASSED] 256
[11:57:27] ================ [PASSED] test_range_spare =================
[11:57:27] ===================== [PASSED] guc_dbm =====================
[11:57:27] =================== guc_idm (6 subtests) ===================
[11:57:27] [PASSED] bad_init
[11:57:27] [PASSED] no_init
[11:57:27] [PASSED] init_fini
[11:57:27] [PASSED] check_used
[11:57:27] [PASSED] check_quota
[11:57:27] [PASSED] check_all
[11:57:27] ===================== [PASSED] guc_idm =====================
[11:57:27] =============== guc_klv_helpers (9 subtests) ===============
[11:57:27] [PASSED] test_count
[11:57:27] [PASSED] test_encode_u32
[11:57:27] [PASSED] test_encode_u64
[11:57:27] [PASSED] test_encode_string
[11:57:27] [PASSED] test_encode_object_raw
[11:57:27] [PASSED] test_encode_object_klv
[11:57:27] [PASSED] test_encode_object_nested
[11:57:27] [PASSED] test_encode_object_basic
[11:57:27] [PASSED] test_print
[11:57:27] ================= [PASSED] guc_klv_helpers =================
[11:57:27] ================== no_relay (3 subtests) ===================
[11:57:27] [PASSED] xe_drops_guc2pf_if_not_ready
[11:57:27] [PASSED] xe_drops_guc2vf_if_not_ready
[11:57:27] [PASSED] xe_rejects_send_if_not_ready
[11:57:27] ==================== [PASSED] no_relay =====================
[11:57:27] ================== pf_relay (14 subtests) ==================
[11:57:27] [PASSED] pf_rejects_guc2pf_too_short
[11:57:27] [PASSED] pf_rejects_guc2pf_too_long
[11:57:27] [PASSED] pf_rejects_guc2pf_no_payload
[11:57:27] [PASSED] pf_fails_no_payload
[11:57:27] [PASSED] pf_fails_bad_origin
[11:57:27] [PASSED] pf_fails_bad_type
[11:57:27] [PASSED] pf_txn_reports_error
[11:57:27] [PASSED] pf_txn_sends_pf2guc
[11:57:27] [PASSED] pf_sends_pf2guc
[11:57:27] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:57:27] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:57:27] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:57:27] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:57:27] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[11:57:27] ==================== [PASSED] pf_relay =====================
[11:57:27] ================== vf_relay (3 subtests) ===================
[11:57:27] [PASSED] vf_rejects_guc2vf_too_short
[11:57:27] [PASSED] vf_rejects_guc2vf_too_long
[11:57:27] [PASSED] vf_rejects_guc2vf_no_payload
[11:57:27] ==================== [PASSED] vf_relay =====================
[11:57:27] ================ pf_gt_config (9 subtests) =================
[11:57:27] [PASSED] fair_contexts_1vf
[11:57:27] [PASSED] fair_doorbells_1vf
[11:57:27] [PASSED] fair_ggtt_1vf
[11:57:27] ====================== fair_vram_1vf  ======================
[11:57:27] [PASSED] 3.50 GiB
[11:57:27] [PASSED] 11.5 GiB
[11:57:27] [PASSED] 15.5 GiB
[11:57:27] [PASSED] 31.5 GiB
[11:57:27] [PASSED] 63.5 GiB
[11:57:27] [PASSED] 1.91 GiB
[11:57:27] ================== [PASSED] fair_vram_1vf ==================
[11:57:27] ================ fair_vram_1vf_admin_only  =================
[11:57:27] [PASSED] 3.50 GiB
[11:57:27] [PASSED] 11.5 GiB
[11:57:27] [PASSED] 15.5 GiB
[11:57:27] [PASSED] 31.5 GiB
[11:57:27] [PASSED] 63.5 GiB
[11:57:27] [PASSED] 1.91 GiB
[11:57:27] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:57:27] ====================== fair_contexts  ======================
[11:57:27] [PASSED] 1 VF
[11:57:27] [PASSED] 2 VFs
[11:57:27] [PASSED] 3 VFs
[11:57:27] [PASSED] 4 VFs
[11:57:27] [PASSED] 5 VFs
[11:57:27] [PASSED] 6 VFs
[11:57:27] [PASSED] 7 VFs
[11:57:27] [PASSED] 8 VFs
[11:57:27] [PASSED] 9 VFs
[11:57:27] [PASSED] 10 VFs
[11:57:27] [PASSED] 11 VFs
[11:57:27] [PASSED] 12 VFs
[11:57:27] [PASSED] 13 VFs
[11:57:27] [PASSED] 14 VFs
[11:57:27] [PASSED] 15 VFs
[11:57:27] [PASSED] 16 VFs
[11:57:27] [PASSED] 17 VFs
[11:57:27] [PASSED] 18 VFs
[11:57:27] [PASSED] 19 VFs
[11:57:27] [PASSED] 20 VFs
[11:57:27] [PASSED] 21 VFs
[11:57:27] [PASSED] 22 VFs
[11:57:27] [PASSED] 23 VFs
[11:57:27] [PASSED] 24 VFs
[11:57:27] [PASSED] 25 VFs
[11:57:27] [PASSED] 26 VFs
[11:57:27] [PASSED] 27 VFs
[11:57:27] [PASSED] 28 VFs
[11:57:27] [PASSED] 29 VFs
[11:57:27] [PASSED] 30 VFs
[11:57:27] [PASSED] 31 VFs
[11:57:27] [PASSED] 32 VFs
[11:57:27] [PASSED] 33 VFs
[11:57:27] [PASSED] 34 VFs
[11:57:27] [PASSED] 35 VFs
[11:57:27] [PASSED] 36 VFs
[11:57:27] [PASSED] 37 VFs
[11:57:27] [PASSED] 38 VFs
[11:57:27] [PASSED] 39 VFs
[11:57:27] [PASSED] 40 VFs
[11:57:27] [PASSED] 41 VFs
[11:57:27] [PASSED] 42 VFs
[11:57:27] [PASSED] 43 VFs
[11:57:27] [PASSED] 44 VFs
[11:57:27] [PASSED] 45 VFs
[11:57:27] [PASSED] 46 VFs
[11:57:27] [PASSED] 47 VFs
[11:57:27] [PASSED] 48 VFs
[11:57:27] [PASSED] 49 VFs
[11:57:27] [PASSED] 50 VFs
[11:57:27] [PASSED] 51 VFs
[11:57:27] [PASSED] 52 VFs
[11:57:27] [PASSED] 53 VFs
[11:57:27] [PASSED] 54 VFs
[11:57:27] [PASSED] 55 VFs
[11:57:27] [PASSED] 56 VFs
[11:57:27] [PASSED] 57 VFs
[11:57:27] [PASSED] 58 VFs
[11:57:27] [PASSED] 59 VFs
[11:57:27] [PASSED] 60 VFs
[11:57:27] [PASSED] 61 VFs
[11:57:27] [PASSED] 62 VFs
[11:57:27] [PASSED] 63 VFs
[11:57:27] ================== [PASSED] fair_contexts ==================
[11:57:27] ===================== fair_doorbells  ======================
[11:57:27] [PASSED] 1 VF
[11:57:27] [PASSED] 2 VFs
[11:57:27] [PASSED] 3 VFs
[11:57:27] [PASSED] 4 VFs
[11:57:27] [PASSED] 5 VFs
[11:57:27] [PASSED] 6 VFs
[11:57:27] [PASSED] 7 VFs
[11:57:27] [PASSED] 8 VFs
[11:57:27] [PASSED] 9 VFs
[11:57:27] [PASSED] 10 VFs
[11:57:27] [PASSED] 11 VFs
[11:57:27] [PASSED] 12 VFs
[11:57:27] [PASSED] 13 VFs
[11:57:27] [PASSED] 14 VFs
[11:57:27] [PASSED] 15 VFs
[11:57:27] [PASSED] 16 VFs
[11:57:27] [PASSED] 17 VFs
[11:57:27] [PASSED] 18 VFs
[11:57:27] [PASSED] 19 VFs
[11:57:27] [PASSED] 20 VFs
[11:57:27] [PASSED] 21 VFs
[11:57:27] [PASSED] 22 VFs
[11:57:27] [PASSED] 23 VFs
[11:57:27] [PASSED] 24 VFs
[11:57:27] [PASSED] 25 VFs
[11:57:27] [PASSED] 26 VFs
[11:57:27] [PASSED] 27 VFs
[11:57:27] [PASSED] 28 VFs
[11:57:27] [PASSED] 29 VFs
[11:57:27] [PASSED] 30 VFs
[11:57:27] [PASSED] 31 VFs
[11:57:27] [PASSED] 32 VFs
[11:57:27] [PASSED] 33 VFs
[11:57:27] [PASSED] 34 VFs
[11:57:27] [PASSED] 35 VFs
[11:57:27] [PASSED] 36 VFs
[11:57:27] [PASSED] 37 VFs
[11:57:27] [PASSED] 38 VFs
[11:57:27] [PASSED] 39 VFs
[11:57:27] [PASSED] 40 VFs
[11:57:27] [PASSED] 41 VFs
[11:57:27] [PASSED] 42 VFs
[11:57:27] [PASSED] 43 VFs
[11:57:27] [PASSED] 44 VFs
[11:57:27] [PASSED] 45 VFs
[11:57:27] [PASSED] 46 VFs
[11:57:27] [PASSED] 47 VFs
[11:57:27] [PASSED] 48 VFs
[11:57:27] [PASSED] 49 VFs
[11:57:27] [PASSED] 50 VFs
[11:57:27] [PASSED] 51 VFs
[11:57:27] [PASSED] 52 VFs
[11:57:27] [PASSED] 53 VFs
[11:57:27] [PASSED] 54 VFs
[11:57:27] [PASSED] 55 VFs
[11:57:27] [PASSED] 56 VFs
[11:57:27] [PASSED] 57 VFs
[11:57:27] [PASSED] 58 VFs
[11:57:27] [PASSED] 59 VFs
[11:57:27] [PASSED] 60 VFs
[11:57:27] [PASSED] 61 VFs
[11:57:27] [PASSED] 62 VFs
[11:57:27] [PASSED] 63 VFs
[11:57:27] ================= [PASSED] fair_doorbells ==================
[11:57:27] ======================== fair_ggtt  ========================
[11:57:27] [PASSED] 1 VF
[11:57:27] [PASSED] 2 VFs
[11:57:27] [PASSED] 3 VFs
[11:57:27] [PASSED] 4 VFs
[11:57:27] [PASSED] 5 VFs
[11:57:27] [PASSED] 6 VFs
[11:57:27] [PASSED] 7 VFs
[11:57:27] [PASSED] 8 VFs
[11:57:27] [PASSED] 9 VFs
[11:57:27] [PASSED] 10 VFs
[11:57:27] [PASSED] 11 VFs
[11:57:27] [PASSED] 12 VFs
[11:57:27] [PASSED] 13 VFs
[11:57:27] [PASSED] 14 VFs
[11:57:27] [PASSED] 15 VFs
[11:57:27] [PASSED] 16 VFs
[11:57:27] [PASSED] 17 VFs
[11:57:27] [PASSED] 18 VFs
[11:57:27] [PASSED] 19 VFs
[11:57:27] [PASSED] 20 VFs
[11:57:27] [PASSED] 21 VFs
[11:57:27] [PASSED] 22 VFs
[11:57:27] [PASSED] 23 VFs
[11:57:27] [PASSED] 24 VFs
[11:57:27] [PASSED] 25 VFs
[11:57:27] [PASSED] 26 VFs
[11:57:27] [PASSED] 27 VFs
[11:57:27] [PASSED] 28 VFs
[11:57:27] [PASSED] 29 VFs
[11:57:27] [PASSED] 30 VFs
[11:57:27] [PASSED] 31 VFs
[11:57:27] [PASSED] 32 VFs
[11:57:27] [PASSED] 33 VFs
[11:57:27] [PASSED] 34 VFs
[11:57:27] [PASSED] 35 VFs
[11:57:27] [PASSED] 36 VFs
[11:57:27] [PASSED] 37 VFs
[11:57:27] [PASSED] 38 VFs
[11:57:27] [PASSED] 39 VFs
[11:57:27] [PASSED] 40 VFs
[11:57:27] [PASSED] 41 VFs
[11:57:27] [PASSED] 42 VFs
[11:57:27] [PASSED] 43 VFs
[11:57:27] [PASSED] 44 VFs
[11:57:27] [PASSED] 45 VFs
[11:57:27] [PASSED] 46 VFs
[11:57:27] [PASSED] 47 VFs
[11:57:27] [PASSED] 48 VFs
[11:57:27] [PASSED] 49 VFs
[11:57:27] [PASSED] 50 VFs
[11:57:27] [PASSED] 51 VFs
[11:57:27] [PASSED] 52 VFs
[11:57:27] [PASSED] 53 VFs
[11:57:27] [PASSED] 54 VFs
[11:57:27] [PASSED] 55 VFs
[11:57:27] [PASSED] 56 VFs
[11:57:27] [PASSED] 57 VFs
[11:57:27] [PASSED] 58 VFs
[11:57:27] [PASSED] 59 VFs
[11:57:27] [PASSED] 60 VFs
[11:57:27] [PASSED] 61 VFs
[11:57:27] [PASSED] 62 VFs
[11:57:27] [PASSED] 63 VFs
[11:57:27] ==================== [PASSED] fair_ggtt ====================
[11:57:27] ======================== fair_vram  ========================
[11:57:27] [PASSED] 1 VF
[11:57:27] [PASSED] 2 VFs
[11:57:27] [PASSED] 3 VFs
[11:57:27] [PASSED] 4 VFs
[11:57:27] [PASSED] 5 VFs
[11:57:27] [PASSED] 6 VFs
[11:57:27] [PASSED] 7 VFs
[11:57:27] [PASSED] 8 VFs
[11:57:27] [PASSED] 9 VFs
[11:57:27] [PASSED] 10 VFs
[11:57:28] [PASSED] 11 VFs
[11:57:28] [PASSED] 12 VFs
[11:57:28] [PASSED] 13 VFs
[11:57:28] [PASSED] 14 VFs
[11:57:28] [PASSED] 15 VFs
[11:57:28] [PASSED] 16 VFs
[11:57:28] [PASSED] 17 VFs
[11:57:28] [PASSED] 18 VFs
[11:57:28] [PASSED] 19 VFs
[11:57:28] [PASSED] 20 VFs
[11:57:28] [PASSED] 21 VFs
[11:57:28] [PASSED] 22 VFs
[11:57:28] [PASSED] 23 VFs
[11:57:28] [PASSED] 24 VFs
[11:57:28] [PASSED] 25 VFs
[11:57:28] [PASSED] 26 VFs
[11:57:28] [PASSED] 27 VFs
[11:57:28] [PASSED] 28 VFs
[11:57:28] [PASSED] 29 VFs
[11:57:28] [PASSED] 30 VFs
[11:57:28] [PASSED] 31 VFs
[11:57:28] [PASSED] 32 VFs
[11:57:28] [PASSED] 33 VFs
[11:57:28] [PASSED] 34 VFs
[11:57:28] [PASSED] 35 VFs
[11:57:28] [PASSED] 36 VFs
[11:57:28] [PASSED] 37 VFs
[11:57:28] [PASSED] 38 VFs
[11:57:28] [PASSED] 39 VFs
[11:57:28] [PASSED] 40 VFs
[11:57:28] [PASSED] 41 VFs
[11:57:28] [PASSED] 42 VFs
[11:57:28] [PASSED] 43 VFs
[11:57:28] [PASSED] 44 VFs
[11:57:28] [PASSED] 45 VFs
[11:57:28] [PASSED] 46 VFs
[11:57:28] [PASSED] 47 VFs
[11:57:28] [PASSED] 48 VFs
[11:57:28] [PASSED] 49 VFs
[11:57:28] [PASSED] 50 VFs
[11:57:28] [PASSED] 51 VFs
[11:57:28] [PASSED] 52 VFs
[11:57:28] [PASSED] 53 VFs
[11:57:28] [PASSED] 54 VFs
[11:57:28] [PASSED] 55 VFs
[11:57:28] [PASSED] 56 VFs
[11:57:28] [PASSED] 57 VFs
[11:57:28] [PASSED] 58 VFs
[11:57:28] [PASSED] 59 VFs
[11:57:28] [PASSED] 60 VFs
[11:57:28] [PASSED] 61 VFs
[11:57:28] [PASSED] 62 VFs
[11:57:28] [PASSED] 63 VFs
[11:57:28] ==================== [PASSED] fair_vram ====================
[11:57:28] ================== [PASSED] pf_gt_config ===================
[11:57:28] ===================== lmtt (1 subtest) =====================
[11:57:28] ======================== test_ops  =========================
[11:57:28] [PASSED] 2-level
[11:57:28] [PASSED] multi-level
[11:57:28] ==================== [PASSED] test_ops =====================
[11:57:28] ====================== [PASSED] lmtt =======================
[11:57:28] ================= sriov_packet (1 subtest) =================
[11:57:28] [PASSED] test_descriptor_init
[11:57:28] ================== [PASSED] sriov_packet ===================
[11:57:28] ================= pf_service (11 subtests) =================
[11:57:28] [PASSED] pf_negotiate_any
[11:57:28] [PASSED] pf_negotiate_base_match
[11:57:28] [PASSED] pf_negotiate_base_newer
[11:57:28] [PASSED] pf_negotiate_base_next
[11:57:28] [SKIPPED] pf_negotiate_base_older (no older minor)
[11:57:28] [PASSED] pf_negotiate_base_prev
[11:57:28] [PASSED] pf_negotiate_latest_match
[11:57:28] [PASSED] pf_negotiate_latest_newer
[11:57:28] [PASSED] pf_negotiate_latest_next
[11:57:28] [SKIPPED] pf_negotiate_latest_older (no older minor)
[11:57:28] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[11:57:28] =================== [PASSED] pf_service ====================
[11:57:28] ================= xe_guc_g2g (2 subtests) ==================
[11:57:28] ============== xe_live_guc_g2g_kunit_default  ==============
[11:57:28] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:57:28] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:57:28] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:57:28] =================== [SKIPPED] xe_guc_g2g ===================
[11:57:28] =================== xe_mocs (2 subtests) ===================
[11:57:28] ================ xe_live_mocs_kernel_kunit  ================
[11:57:28] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:57:28] ================ xe_live_mocs_reset_kunit  =================
[11:57:28] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:57:28] ==================== [SKIPPED] xe_mocs =====================
[11:57:28] ================= xe_migrate (2 subtests) ==================
[11:57:28] ================= xe_migrate_sanity_kunit  =================
[11:57:28] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:57:28] ================== xe_validate_ccs_kunit  ==================
[11:57:28] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:57:28] =================== [SKIPPED] xe_migrate ===================
[11:57:28] ================== xe_dma_buf (1 subtest) ==================
[11:57:28] ==================== xe_dma_buf_kunit  =====================
[11:57:28] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:57:28] =================== [SKIPPED] xe_dma_buf ===================
[11:57:28] ================= xe_bo_shrink (1 subtest) =================
[11:57:28] =================== xe_bo_shrink_kunit  ====================
[11:57:28] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:57:28] ================== [SKIPPED] xe_bo_shrink ==================
[11:57:28] ==================== xe_bo (2 subtests) ====================
[11:57:28] ================== xe_ccs_migrate_kunit  ===================
[11:57:28] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:57:28] ==================== xe_bo_evict_kunit  ====================
[11:57:28] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:57:28] ===================== [SKIPPED] xe_bo ======================
[11:57:28] ==================== args (13 subtests) ====================
[11:57:28] [PASSED] count_args_test
[11:57:28] [PASSED] call_args_example
[11:57:28] [PASSED] call_args_test
[11:57:28] [PASSED] drop_first_arg_example
[11:57:28] [PASSED] drop_first_arg_test
[11:57:28] [PASSED] first_arg_example
[11:57:28] [PASSED] first_arg_test
[11:57:28] [PASSED] last_arg_example
[11:57:28] [PASSED] last_arg_test
[11:57:28] [PASSED] pick_arg_example
[11:57:28] [PASSED] if_args_example
[11:57:28] [PASSED] if_args_test
[11:57:28] [PASSED] sep_comma_example
[11:57:28] ====================== [PASSED] args =======================
[11:57:28] =================== xe_pci (3 subtests) ====================
[11:57:28] ==================== check_graphics_ip  ====================
[11:57:28] [PASSED] 12.00 Xe_LP
[11:57:28] [PASSED] 12.10 Xe_LP+
[11:57:28] [PASSED] 12.55 Xe_HPG
[11:57:28] [PASSED] 12.60 Xe_HPC
[11:57:28] [PASSED] 12.70 Xe_LPG
[11:57:28] [PASSED] 12.71 Xe_LPG
[11:57:28] [PASSED] 12.74 Xe_LPG+
[11:57:28] [PASSED] 20.01 Xe2_HPG
[11:57:28] [PASSED] 20.02 Xe2_HPG
[11:57:28] [PASSED] 20.04 Xe2_LPG
[11:57:28] [PASSED] 30.00 Xe3_LPG
[11:57:28] [PASSED] 30.01 Xe3_LPG
[11:57:28] [PASSED] 30.03 Xe3_LPG
[11:57:28] [PASSED] 30.04 Xe3_LPG
[11:57:28] [PASSED] 30.05 Xe3_LPG
[11:57:28] [PASSED] 35.10 Xe3p_LPG
[11:57:28] [PASSED] 35.11 Xe3p_XPC
[11:57:28] ================ [PASSED] check_graphics_ip ================
[11:57:28] ===================== check_media_ip  ======================
[11:57:28] [PASSED] 12.00 Xe_M
[11:57:28] [PASSED] 12.55 Xe_HPM
[11:57:28] [PASSED] 13.00 Xe_LPM+
[11:57:28] [PASSED] 13.01 Xe2_HPM
[11:57:28] [PASSED] 20.00 Xe2_LPM
[11:57:28] [PASSED] 30.00 Xe3_LPM
[11:57:28] [PASSED] 30.02 Xe3_LPM
[11:57:28] [PASSED] 35.00 Xe3p_LPM
[11:57:28] [PASSED] 35.03 Xe3p_HPM
[11:57:28] ================= [PASSED] check_media_ip ==================
[11:57:28] =================== check_platform_desc  ===================
[11:57:28] [PASSED] 0x9A60 (TIGERLAKE)
[11:57:28] [PASSED] 0x9A68 (TIGERLAKE)
[11:57:28] [PASSED] 0x9A70 (TIGERLAKE)
[11:57:28] [PASSED] 0x9A40 (TIGERLAKE)
[11:57:28] [PASSED] 0x9A49 (TIGERLAKE)
[11:57:28] [PASSED] 0x9A59 (TIGERLAKE)
[11:57:28] [PASSED] 0x9A78 (TIGERLAKE)
[11:57:28] [PASSED] 0x9AC0 (TIGERLAKE)
[11:57:28] [PASSED] 0x9AC9 (TIGERLAKE)
[11:57:28] [PASSED] 0x9AD9 (TIGERLAKE)
[11:57:28] [PASSED] 0x9AF8 (TIGERLAKE)
[11:57:28] [PASSED] 0x4C80 (ROCKETLAKE)
[11:57:28] [PASSED] 0x4C8A (ROCKETLAKE)
[11:57:28] [PASSED] 0x4C8B (ROCKETLAKE)
[11:57:28] [PASSED] 0x4C8C (ROCKETLAKE)
[11:57:28] [PASSED] 0x4C90 (ROCKETLAKE)
[11:57:28] [PASSED] 0x4C9A (ROCKETLAKE)
[11:57:28] [PASSED] 0x4680 (ALDERLAKE_S)
[11:57:28] [PASSED] 0x4682 (ALDERLAKE_S)
[11:57:28] [PASSED] 0x4688 (ALDERLAKE_S)
[11:57:28] [PASSED] 0x468A (ALDERLAKE_S)
[11:57:28] [PASSED] 0x468B (ALDERLAKE_S)
[11:57:28] [PASSED] 0x4690 (ALDERLAKE_S)
[11:57:28] [PASSED] 0x4692 (ALDERLAKE_S)
[11:57:28] [PASSED] 0x4693 (ALDERLAKE_S)
[11:57:28] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46AA (ALDERLAKE_P)
[11:57:28] [PASSED] 0x462A (ALDERLAKE_P)
[11:57:28] [PASSED] 0x4626 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x4628 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:57:28] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:57:28] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:57:28] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:57:28] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:57:28] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:57:28] [PASSED] 0xA721 (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA720 (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:57:28] [PASSED] 0xA780 (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA781 (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA782 (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA783 (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA788 (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA789 (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA78A (ALDERLAKE_S)
[11:57:28] [PASSED] 0xA78B (ALDERLAKE_S)
[11:57:28] [PASSED] 0x4905 (DG1)
[11:57:28] [PASSED] 0x4906 (DG1)
[11:57:28] [PASSED] 0x4907 (DG1)
[11:57:28] [PASSED] 0x4908 (DG1)
[11:57:28] [PASSED] 0x4909 (DG1)
[11:57:28] [PASSED] 0x56C0 (DG2)
[11:57:28] [PASSED] 0x56C2 (DG2)
[11:57:28] [PASSED] 0x56C1 (DG2)
[11:57:28] [PASSED] 0x7D51 (METEORLAKE)
[11:57:28] [PASSED] 0x7DD1 (METEORLAKE)
[11:57:28] [PASSED] 0x7D41 (METEORLAKE)
[11:57:28] [PASSED] 0x7D67 (METEORLAKE)
[11:57:28] [PASSED] 0xB640 (METEORLAKE)
[11:57:28] [PASSED] 0x56A0 (DG2)
[11:57:28] [PASSED] 0x56A1 (DG2)
[11:57:28] [PASSED] 0x56A2 (DG2)
[11:57:28] [PASSED] 0x56BE (DG2)
[11:57:28] [PASSED] 0x56BF (DG2)
[11:57:28] [PASSED] 0x5690 (DG2)
[11:57:28] [PASSED] 0x5691 (DG2)
[11:57:28] [PASSED] 0x5692 (DG2)
[11:57:28] [PASSED] 0x56A5 (DG2)
[11:57:28] [PASSED] 0x56A6 (DG2)
[11:57:28] [PASSED] 0x56B0 (DG2)
[11:57:28] [PASSED] 0x56B1 (DG2)
[11:57:28] [PASSED] 0x56BA (DG2)
[11:57:28] [PASSED] 0x56BB (DG2)
[11:57:28] [PASSED] 0x56BC (DG2)
[11:57:28] [PASSED] 0x56BD (DG2)
[11:57:28] [PASSED] 0x5693 (DG2)
[11:57:28] [PASSED] 0x5694 (DG2)
[11:57:28] [PASSED] 0x5695 (DG2)
[11:57:28] [PASSED] 0x56A3 (DG2)
[11:57:28] [PASSED] 0x56A4 (DG2)
[11:57:28] [PASSED] 0x56B2 (DG2)
[11:57:28] [PASSED] 0x56B3 (DG2)
[11:57:28] [PASSED] 0x5696 (DG2)
[11:57:28] [PASSED] 0x5697 (DG2)
[11:57:28] [PASSED] 0xB69 (PVC)
[11:57:28] [PASSED] 0xB6E (PVC)
[11:57:28] [PASSED] 0xBD4 (PVC)
[11:57:28] [PASSED] 0xBD5 (PVC)
[11:57:28] [PASSED] 0xBD6 (PVC)
[11:57:28] [PASSED] 0xBD7 (PVC)
[11:57:28] [PASSED] 0xBD8 (PVC)
[11:57:28] [PASSED] 0xBD9 (PVC)
[11:57:28] [PASSED] 0xBDA (PVC)
[11:57:28] [PASSED] 0xBDB (PVC)
[11:57:28] [PASSED] 0xBE0 (PVC)
[11:57:28] [PASSED] 0xBE1 (PVC)
[11:57:28] [PASSED] 0xBE5 (PVC)
[11:57:28] [PASSED] 0x7D40 (METEORLAKE)
[11:57:28] [PASSED] 0x7D45 (METEORLAKE)
[11:57:28] [PASSED] 0x7D55 (METEORLAKE)
[11:57:28] [PASSED] 0x7D60 (METEORLAKE)
[11:57:28] [PASSED] 0x7DD5 (METEORLAKE)
[11:57:28] [PASSED] 0x6420 (LUNARLAKE)
[11:57:28] [PASSED] 0x64A0 (LUNARLAKE)
[11:57:28] [PASSED] 0x64B0 (LUNARLAKE)
[11:57:28] [PASSED] 0xE202 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE209 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE20B (BATTLEMAGE)
[11:57:28] [PASSED] 0xE20C (BATTLEMAGE)
[11:57:28] [PASSED] 0xE20D (BATTLEMAGE)
[11:57:28] [PASSED] 0xE210 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE211 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE212 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE216 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE220 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE221 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE222 (BATTLEMAGE)
[11:57:28] [PASSED] 0xE223 (BATTLEMAGE)
[11:57:28] [PASSED] 0xB080 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB081 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB082 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB083 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB084 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB085 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB086 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB087 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB08F (PANTHERLAKE)
[11:57:28] [PASSED] 0xB090 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:57:28] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:57:28] [PASSED] 0xFD80 (PANTHERLAKE)
[11:57:28] [PASSED] 0xFD81 (PANTHERLAKE)
[11:57:28] [PASSED] 0xD740 (NOVALAKE_S)
[11:57:28] [PASSED] 0xD741 (NOVALAKE_S)
[11:57:28] [PASSED] 0xD742 (NOVALAKE_S)
[11:57:28] [PASSED] 0xD743 (NOVALAKE_S)
[11:57:28] [PASSED] 0xD745 (NOVALAKE_S)
[11:57:28] [PASSED] 0xD74A (NOVALAKE_S)
[11:57:28] [PASSED] 0xD74B (NOVALAKE_S)
[11:57:28] [PASSED] 0x674C (CRESCENTISLAND)
[11:57:28] [PASSED] 0x674D (CRESCENTISLAND)
[11:57:28] [PASSED] 0x674E (CRESCENTISLAND)
[11:57:28] [PASSED] 0x674F (CRESCENTISLAND)
[11:57:28] [PASSED] 0x6750 (CRESCENTISLAND)
[11:57:28] [PASSED] 0xD750 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD751 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD752 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD753 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD754 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD755 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD756 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD757 (NOVALAKE_P)
[11:57:28] [PASSED] 0xD75F (NOVALAKE_P)
[11:57:28] =============== [PASSED] check_platform_desc ===============
[11:57:28] ===================== [PASSED] xe_pci ======================
[11:57:28] ============= xe_rtp_tables_test (5 subtests) ==============
[11:57:28] ================== xe_rtp_table_gt_test  ===================
[11:57:28] [PASSED] gt_was/14011060649
[11:57:28] [PASSED] gt_was/14011059788
[11:57:28] [PASSED] gt_was/14015795083
[11:57:28] [PASSED] gt_was/16021867713
[11:57:28] [PASSED] gt_was/14019449301
[11:57:28] [PASSED] gt_was/16028005424
[11:57:28] [PASSED] gt_was/14026578760
[11:57:28] [PASSED] gt_was/1409420604
[11:57:28] [PASSED] gt_was/1408615072
[11:57:28] [PASSED] gt_was/22010523718
[11:57:28] [PASSED] gt_was/14011006942
[11:57:28] [PASSED] gt_was/14014830051
[11:57:28] [PASSED] gt_was/18018781329
[11:57:28] [PASSED] gt_was/1509235366
[11:57:28] [PASSED] gt_was/18018781329
[11:57:28] [PASSED] gt_was/16016694945
[11:57:28] [PASSED] gt_was/14018575942
[11:57:28] [PASSED] gt_was/22016670082
[11:57:28] [PASSED] gt_was/22016670082
[11:57:28] [PASSED] gt_was/14017421178
[11:57:28] [PASSED] gt_was/16025250150
[11:57:28] [PASSED] gt_was/14021871409
[11:57:28] [PASSED] gt_was/16021865536
[11:57:28] [PASSED] gt_was/14021486841
[11:57:28] [PASSED] gt_was/14025160223
[11:57:28] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[11:57:28] [PASSED] gt_was/14025635424
[11:57:28] [PASSED] gt_was/16028005424
[11:57:28] ============== [PASSED] xe_rtp_table_gt_test ===============
[11:57:28] ================== xe_rtp_table_gt_test  ===================
[11:57:28] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[11:57:28] [PASSED] gt_tunings/Tuning: 32B Access Enable
[11:57:28] [PASSED] gt_tunings/Tuning: L3 cache
[11:57:28] [PASSED] gt_tunings/Tuning: L3 cache - media
[11:57:28] [PASSED] gt_tunings/Tuning: Compression Overfetch
[11:57:28] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[11:57:28] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[11:57:28] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[11:57:28] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[11:57:28] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[11:57:28] [PASSED] gt_tunings/Tuning: Stateless compression control
[11:57:28] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[11:57:28] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[11:57:28] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[11:57:28] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[11:57:28] ============== [PASSED] xe_rtp_table_gt_test ===============
[11:57:28] ================== xe_rtp_table_oob_test  ==================
[11:57:28] [PASSED] oob_was/1607983814
[11:57:28] [PASSED] oob_was/16010904313
[11:57:28] [PASSED] oob_was/18022495364
[11:57:28] [PASSED] oob_was/22012773006
[11:57:28] [PASSED] oob_was/14014475959
[11:57:28] [PASSED] oob_was/22011391025
[11:57:28] [PASSED] oob_was/22012727170
[11:57:28] [PASSED] oob_was/22012727685
[11:57:28] [PASSED] oob_was/22016596838
[11:57:28] [PASSED] oob_was/18020744125
[11:57:28] [PASSED] oob_was/1409600907
[11:57:28] [PASSED] oob_was/22014953428
[11:57:28] [PASSED] oob_was/16017236439
[11:57:28] [PASSED] oob_was/14019821291
[11:57:28] [PASSED] oob_was/14015076503
[11:57:28] [PASSED] oob_was/14018913170
[11:57:28] [PASSED] oob_was/14018094691
[11:57:28] [PASSED] oob_was/18024947630
[11:57:28] [PASSED] oob_was/16022287689
[11:57:28] [PASSED] oob_was/13011645652
[11:57:28] [PASSED] oob_was/14022293748
[11:57:28] [PASSED] oob_was/22019794406
[11:57:28] [PASSED] oob_was/22019338487
[11:57:28] [PASSED] oob_was/16023588340
[11:57:28] [PASSED] oob_was/14019789679
[11:57:28] [PASSED] oob_was/14022866841
[11:57:28] [PASSED] oob_was/16021333562
[11:57:28] [PASSED] oob_was/14016712196
[11:57:28] [PASSED] oob_was/14015568240
[11:57:28] [PASSED] oob_was/18013179988
[11:57:28] [PASSED] oob_was/1508761755
[11:57:28] [PASSED] oob_was/16023105232
[11:57:28] [PASSED] oob_was/16026508708
[11:57:28] [PASSED] oob_was/14020001231
[11:57:28] [PASSED] oob_was/16023683509
[11:57:28] [PASSED] oob_was/14025515070
[11:57:28] [PASSED] oob_was/15015404425_disable
[11:57:28] [PASSED] oob_was/16026007364
[11:57:28] [PASSED] oob_was/14020316580
[11:57:28] [PASSED] oob_was/14025883347
[11:57:28] [PASSED] oob_was/16029380221
[11:57:28] [PASSED] oob_was/22022079272
[11:57:28] [PASSED] oob_was/16029897822
[11:57:28] [PASSED] oob_was/14027054324
[11:57:28] ============== [PASSED] xe_rtp_table_oob_test ==============
[11:57:28] ================ xe_rtp_table_dev_oob_test  ================
[11:57:28] [PASSED] device_oob_was/22010954014
[11:57:28] [PASSED] device_oob_was/15015404425
[11:57:28] [PASSED] device_oob_was/22019338487_display
[11:57:28] [PASSED] device_oob_was/14022085890
[11:57:28] [PASSED] device_oob_was/14026539277
[11:57:28] [PASSED] device_oob_was/14026633728
[11:57:28] [PASSED] device_oob_was/14026746987
[11:57:28] [PASSED] device_oob_was/14026779378
[11:57:28] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[11:57:28] ========== xe_rtp_table_missing_upper_bound_test  ==========
[11:57:28] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[11:57:28] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[11:57:28] [PASSED] register_whitelist/1806527549
[11:57:28] [PASSED] register_whitelist/allow_read_ctx_timestamp
[11:57:28] [PASSED] register_whitelist/allow_read_queue_timestamp
[11:57:28] [PASSED] register_whitelist/16014440446
[11:57:28] [PASSED] register_whitelist/16017236439
[11:57:28] [PASSED] register_whitelist/16020183090
[11:57:28] [PASSED] register_whitelist/14024997852
[11:57:28] [PASSED] register_whitelist/14024997852
[11:57:28] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[11:57:28] =============== [PASSED] xe_rtp_tables_test ================
[11:57:28] =================== xe_rtp (3 subtests) ====================
[11:57:28] =================== xe_rtp_rules_tests  ====================
[11:57:28] [PASSED] no
[11:57:28] [PASSED] yes
[11:57:28] [PASSED] no-and-no
[11:57:28] [PASSED] no-and-yes
[11:57:28] [PASSED] yes-and-no
[11:57:28] [PASSED] yes-and-yes
[11:57:28] [PASSED] no-or-no
[11:57:28] [PASSED] no-or-yes
[11:57:28] [PASSED] yes-or-no
[11:57:28] [PASSED] yes-or-yes
[11:57:28] [PASSED] no-yes-or-yes-no
[11:57:28] [PASSED] no-yes-or-yes-yes
[11:57:28] [PASSED] yes-yes-or-no-yes
[11:57:28] [PASSED] yes-yes-or-yes-yes
[11:57:28] [PASSED] no-no-or-yes-or-no
[11:57:28] [PASSED] or
[11:57:28] [PASSED] or-yes
[11:57:28] [PASSED] or-no
[11:57:28] [PASSED] yes-or
[11:57:28] [PASSED] no-or
[11:57:28] [PASSED] no-or-or-yes
[11:57:28] [PASSED] yes-or-or-no
[11:57:28] [PASSED] no-or-or-no
[11:57:28] [PASSED] missing-context-engine-class
[11:57:28] [PASSED] missing-context-engine-class-or-yes
[11:57:28] [PASSED] missing-context-engine-class-or-or-yes
[11:57:28] =============== [PASSED] xe_rtp_rules_tests ================
[11:57:28] =============== xe_rtp_process_to_sr_tests  ================
[11:57:28] [PASSED] coalesce-same-reg
[11:57:28] [PASSED] coalesce-same-reg-literal-and-func
[11:57:28] [PASSED] no-match-no-add
[11:57:28] [PASSED] two-regs-two-entries
[11:57:28] [PASSED] clr-one-set-other
[11:57:28] [PASSED] set-field
[11:57:28] [PASSED] conflict-duplicate
[11:57:28] [PASSED] conflict-not-disjoint
[11:57:28] [PASSED] conflict-not-disjoint-literal-and-func
[11:57:28] [PASSED] conflict-reg-type
[11:57:28] [PASSED] bad-mcr-reg-forced-to-regular
[11:57:28] [PASSED] bad-regular-reg-forced-to-mcr
[11:57:28] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:57:28] ================== xe_rtp_process_tests  ===================
[11:57:28] [PASSED] active1
[11:57:28] [PASSED] active2
[11:57:28] [PASSED] active-inactive
[11:57:28] [PASSED] inactive-active
[11:57:28] [PASSED] inactive-active-inactive
[11:57:28] [PASSED] inactive-inactive-inactive
[11:57:28] ============== [PASSED] xe_rtp_process_tests ===============
[11:57:28] ===================== [PASSED] xe_rtp ======================
[11:57:28] ==================== xe_wa (1 subtest) =====================
[11:57:28] ======================== xe_wa_gt  =========================
[11:57:28] [PASSED] TIGERLAKE B0
[11:57:28] [PASSED] DG1 A0
[11:57:28] [PASSED] DG1 B0
[11:57:28] [PASSED] ALDERLAKE_S A0
[11:57:28] [PASSED] ALDERLAKE_S B0
[11:57:28] [PASSED] ALDERLAKE_S C0
[11:57:28] [PASSED] ALDERLAKE_S D0
[11:57:28] [PASSED] ALDERLAKE_P A0
[11:57:28] [PASSED] ALDERLAKE_P B0
[11:57:28] [PASSED] ALDERLAKE_P C0
[11:57:28] [PASSED] ALDERLAKE_S RPLS D0
[11:57:28] [PASSED] ALDERLAKE_P RPLU E0
[11:57:28] [PASSED] DG2 G10 C0
[11:57:28] [PASSED] DG2 G11 B1
[11:57:28] [PASSED] DG2 G12 A1
[11:57:28] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:57:28] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:57:28] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:57:28] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:57:28] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:57:28] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:57:28] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:57:28] ==================== [PASSED] xe_wa_gt =====================
[11:57:28] ====================== [PASSED] xe_wa ======================
[11:57:28] ============================================================
[11:57:28] Testing complete. Ran 742 tests: passed: 724, skipped: 18
[11:57:28] Elapsed time: 36.673s total, 4.347s configuring, 31.660s building, 0.630s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:57:28] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:57:30] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:57:54] Starting KUnit Kernel (1/1)...
[11:57:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:57:54] ============ drm_test_pick_cmdline (2 subtests) ============
[11:57:54] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:57:54] =============== drm_test_pick_cmdline_named  ===============
[11:57:54] [PASSED] NTSC
[11:57:54] [PASSED] NTSC-J
[11:57:54] [PASSED] PAL
[11:57:54] [PASSED] PAL-M
[11:57:54] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:57:54] ============== [PASSED] drm_test_pick_cmdline ==============
[11:57:54] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:57:54] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:57:54] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:57:54] =========== drm_validate_clone_mode (2 subtests) ===========
[11:57:54] ============== drm_test_check_in_clone_mode  ===============
[11:57:54] [PASSED] in_clone_mode
[11:57:54] [PASSED] not_in_clone_mode
[11:57:54] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:57:54] =============== drm_test_check_valid_clones  ===============
[11:57:54] [PASSED] not_in_clone_mode
[11:57:54] [PASSED] valid_clone
[11:57:54] [PASSED] invalid_clone
[11:57:54] =========== [PASSED] drm_test_check_valid_clones ===========
[11:57:54] ============= [PASSED] drm_validate_clone_mode =============
[11:57:54] ============= drm_validate_modeset (1 subtest) =============
[11:57:54] [PASSED] drm_test_check_connector_changed_modeset
[11:57:54] ============== [PASSED] drm_validate_modeset ===============
[11:57:54] ====== drm_test_bridge_get_current_state (1 subtest) =======
[11:57:54] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:57:54] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:57:54] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:57:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:57:54] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:57:54] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[11:57:54] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:57:54] ============== drm_bridge_alloc (2 subtests) ===============
[11:57:54] [PASSED] drm_test_drm_bridge_alloc_basic
[11:57:54] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:57:54] ================ [PASSED] drm_bridge_alloc =================
[11:57:54] ============= drm_bridge_bus_fmt (5 subtests) ==============
[11:57:54] [PASSED] drm_test_bridge_rgb_yuv_rgb
[11:57:54] [PASSED] drm_test_bridge_must_convert_to_yuv444
[11:57:54] [PASSED] drm_test_bridge_hdmi_auto_rgb
[11:57:54] [PASSED] drm_test_bridge_auto_first
[11:57:54] [PASSED] drm_test_bridge_rgb_yuv_no_path
[11:57:54] =============== [PASSED] drm_bridge_bus_fmt ================
[11:57:54] ============= drm_cmdline_parser (40 subtests) =============
[11:57:54] [PASSED] drm_test_cmdline_force_d_only
[11:57:54] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:57:54] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:57:54] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:57:54] [PASSED] drm_test_cmdline_force_e_only
[11:57:54] [PASSED] drm_test_cmdline_res
[11:57:54] [PASSED] drm_test_cmdline_res_vesa
[11:57:54] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:57:54] [PASSED] drm_test_cmdline_res_rblank
[11:57:54] [PASSED] drm_test_cmdline_res_bpp
[11:57:54] [PASSED] drm_test_cmdline_res_refresh
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:57:54] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:57:54] [PASSED] drm_test_cmdline_res_margins_force_on
[11:57:54] [PASSED] drm_test_cmdline_res_vesa_margins
[11:57:54] [PASSED] drm_test_cmdline_name
[11:57:54] [PASSED] drm_test_cmdline_name_bpp
[11:57:54] [PASSED] drm_test_cmdline_name_option
[11:57:54] [PASSED] drm_test_cmdline_name_bpp_option
[11:57:54] [PASSED] drm_test_cmdline_rotate_0
[11:57:54] [PASSED] drm_test_cmdline_rotate_90
[11:57:54] [PASSED] drm_test_cmdline_rotate_180
[11:57:54] [PASSED] drm_test_cmdline_rotate_270
[11:57:54] [PASSED] drm_test_cmdline_hmirror
[11:57:54] [PASSED] drm_test_cmdline_vmirror
[11:57:54] [PASSED] drm_test_cmdline_margin_options
[11:57:54] [PASSED] drm_test_cmdline_multiple_options
[11:57:54] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:57:54] [PASSED] drm_test_cmdline_extra_and_option
[11:57:54] [PASSED] drm_test_cmdline_freestanding_options
[11:57:54] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:57:54] [PASSED] drm_test_cmdline_panel_orientation
[11:57:54] ================ drm_test_cmdline_invalid  =================
[11:57:54] [PASSED] margin_only
[11:57:54] [PASSED] interlace_only
[11:57:54] [PASSED] res_missing_x
[11:57:54] [PASSED] res_missing_y
[11:57:54] [PASSED] res_bad_y
[11:57:54] [PASSED] res_missing_y_bpp
[11:57:54] [PASSED] res_bad_bpp
[11:57:54] [PASSED] res_bad_refresh
[11:57:54] [PASSED] res_bpp_refresh_force_on_off
[11:57:54] [PASSED] res_invalid_mode
[11:57:54] [PASSED] res_bpp_wrong_place_mode
[11:57:54] [PASSED] name_bpp_refresh
[11:57:54] [PASSED] name_refresh
[11:57:54] [PASSED] name_refresh_wrong_mode
[11:57:54] [PASSED] name_refresh_invalid_mode
[11:57:54] [PASSED] rotate_multiple
[11:57:54] [PASSED] rotate_invalid_val
[11:57:54] [PASSED] rotate_truncated
[11:57:54] [PASSED] invalid_option
[11:57:54] [PASSED] invalid_tv_option
[11:57:54] [PASSED] truncated_tv_option
[11:57:54] ============ [PASSED] drm_test_cmdline_invalid =============
[11:57:54] =============== drm_test_cmdline_tv_options  ===============
[11:57:54] [PASSED] NTSC
[11:57:54] [PASSED] NTSC_443
[11:57:54] [PASSED] NTSC_J
[11:57:54] [PASSED] PAL
[11:57:54] [PASSED] PAL_M
[11:57:54] [PASSED] PAL_N
[11:57:54] [PASSED] SECAM
[11:57:54] [PASSED] MONO_525
[11:57:54] [PASSED] MONO_625
[11:57:54] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:57:54] =============== [PASSED] drm_cmdline_parser ================
[11:57:54] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:57:54] [PASSED] drm_test_connector_hdmi_init_valid
[11:57:54] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:57:54] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:57:54] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:57:54] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:57:54] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:57:54] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:57:54] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:57:54] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:57:54] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:57:54] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:57:54] [PASSED] supported_formats=0x5 yuv420_allowed=1
[11:57:54] [PASSED] supported_formats=0x5 yuv420_allowed=0
[11:57:54] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:57:54] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:57:54] [PASSED] drm_test_connector_hdmi_init_null_product
[11:57:54] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:57:54] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:57:54] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:57:54] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:57:54] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:57:54] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:57:54] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:57:54] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:57:54] [PASSED] HDMI-A
[11:57:54] [PASSED] HDMI-B
[11:57:54] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:57:54] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:57:54] [PASSED] Unknown
[11:57:54] [PASSED] VGA
[11:57:54] [PASSED] DVI-I
[11:57:54] [PASSED] DVI-D
[11:57:54] [PASSED] DVI-A
[11:57:54] [PASSED] Composite
[11:57:54] [PASSED] SVIDEO
[11:57:54] [PASSED] LVDS
[11:57:54] [PASSED] Component
[11:57:54] [PASSED] DIN
[11:57:54] [PASSED] DP
[11:57:54] [PASSED] TV
[11:57:54] [PASSED] eDP
[11:57:54] [PASSED] Virtual
[11:57:54] [PASSED] DSI
[11:57:54] [PASSED] DPI
[11:57:54] [PASSED] Writeback
[11:57:54] [PASSED] SPI
[11:57:54] [PASSED] USB
[11:57:54] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:57:54] ============ [PASSED] drmm_connector_hdmi_init =============
[11:57:54] ============= drmm_connector_init (3 subtests) =============
[11:57:54] [PASSED] drm_test_drmm_connector_init
[11:57:54] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:57:54] ========= drm_test_drmm_connector_init_type_valid  =========
[11:57:54] [PASSED] Unknown
[11:57:54] [PASSED] VGA
[11:57:54] [PASSED] DVI-I
[11:57:54] [PASSED] DVI-D
[11:57:54] [PASSED] DVI-A
[11:57:54] [PASSED] Composite
[11:57:54] [PASSED] SVIDEO
[11:57:54] [PASSED] LVDS
[11:57:54] [PASSED] Component
[11:57:54] [PASSED] DIN
[11:57:54] [PASSED] DP
[11:57:54] [PASSED] HDMI-A
[11:57:54] [PASSED] HDMI-B
[11:57:54] [PASSED] TV
[11:57:54] [PASSED] eDP
[11:57:54] [PASSED] Virtual
[11:57:54] [PASSED] DSI
[11:57:54] [PASSED] DPI
[11:57:54] [PASSED] Writeback
[11:57:54] [PASSED] SPI
[11:57:54] [PASSED] USB
[11:57:54] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:57:54] =============== [PASSED] drmm_connector_init ===============
[11:57:54] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_init
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:57:54] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:57:54] [PASSED] Unknown
[11:57:54] [PASSED] VGA
[11:57:54] [PASSED] DVI-I
[11:57:54] [PASSED] DVI-D
[11:57:54] [PASSED] DVI-A
[11:57:54] [PASSED] Composite
[11:57:54] [PASSED] SVIDEO
[11:57:54] [PASSED] LVDS
[11:57:54] [PASSED] Component
[11:57:54] [PASSED] DIN
[11:57:54] [PASSED] DP
[11:57:54] [PASSED] HDMI-A
[11:57:54] [PASSED] HDMI-B
[11:57:54] [PASSED] TV
[11:57:54] [PASSED] eDP
[11:57:54] [PASSED] Virtual
[11:57:54] [PASSED] DSI
[11:57:54] [PASSED] DPI
[11:57:54] [PASSED] Writeback
[11:57:54] [PASSED] SPI
[11:57:54] [PASSED] USB
[11:57:54] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:57:54] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:57:54] [PASSED] Unknown
[11:57:54] [PASSED] VGA
[11:57:54] [PASSED] DVI-I
[11:57:54] [PASSED] DVI-D
[11:57:54] [PASSED] DVI-A
[11:57:54] [PASSED] Composite
[11:57:54] [PASSED] SVIDEO
[11:57:54] [PASSED] LVDS
[11:57:54] [PASSED] Component
[11:57:54] [PASSED] DIN
[11:57:54] [PASSED] DP
[11:57:54] [PASSED] HDMI-A
[11:57:54] [PASSED] HDMI-B
[11:57:54] [PASSED] TV
[11:57:54] [PASSED] eDP
[11:57:54] [PASSED] Virtual
[11:57:54] [PASSED] DSI
[11:57:54] [PASSED] DPI
[11:57:54] [PASSED] Writeback
[11:57:54] [PASSED] SPI
[11:57:54] [PASSED] USB
[11:57:54] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:57:54] =========== [PASSED] drm_connector_dynamic_init ============
[11:57:54] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:57:54] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:57:54] ======= drm_connector_dynamic_register (7 subtests) ========
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:57:54] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:57:54] ========= [PASSED] drm_connector_dynamic_register ==========
[11:57:54] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:57:54] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:57:54] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:57:54] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:57:54] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:57:54] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:57:54] [PASSED] NTSC
[11:57:54] [PASSED] NTSC-443
[11:57:54] [PASSED] NTSC-J
[11:57:54] [PASSED] PAL
[11:57:54] [PASSED] PAL-M
[11:57:54] [PASSED] PAL-N
[11:57:54] [PASSED] SECAM
[11:57:54] [PASSED] Mono
[11:57:54] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:57:54] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:57:54] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:57:54] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:57:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:57:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:57:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:57:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:57:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:57:54] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:57:54] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:57:54] [PASSED] VIC 96
[11:57:54] [PASSED] VIC 97
[11:57:54] [PASSED] VIC 101
[11:57:54] [PASSED] VIC 102
[11:57:54] [PASSED] VIC 106
[11:57:54] [PASSED] VIC 107
[11:57:54] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:57:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:57:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:57:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:57:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:57:54] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:57:54] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:57:54] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:57:54] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:57:54] [PASSED] Automatic
[11:57:54] [PASSED] Full
[11:57:54] [PASSED] Limited 16:235
[11:57:54] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:57:54] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:57:54] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:57:54] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:57:54] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:57:54] [PASSED] RGB
[11:57:54] [PASSED] YUV 4:2:0
[11:57:54] [PASSED] YUV 4:2:2
[11:57:54] [PASSED] YUV 4:4:4
[11:57:54] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:57:54] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:57:54] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:57:54] ============= drm_damage_helper (21 subtests) ==============
[11:57:54] [PASSED] drm_test_damage_iter_no_damage
[11:57:54] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:57:54] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:57:54] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:57:54] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:57:54] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:57:54] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:57:54] [PASSED] drm_test_damage_iter_simple_damage
[11:57:54] [PASSED] drm_test_damage_iter_single_damage
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:57:54] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:57:54] [PASSED] drm_test_damage_iter_damage
[11:57:54] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:57:54] [PASSED] drm_test_damage_iter_damage_one_outside
[11:57:54] [PASSED] drm_test_damage_iter_damage_src_moved
[11:57:54] [PASSED] drm_test_damage_iter_damage_not_visible
[11:57:54] ================ [PASSED] drm_damage_helper ================
[11:57:54] ============== drm_dp_mst_helper (3 subtests) ==============
[11:57:54] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:57:54] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:57:54] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:57:54] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:57:54] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:57:54] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:57:54] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:57:54] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:57:54] [PASSED] Link rate 2000000 lane count 4
[11:57:54] [PASSED] Link rate 2000000 lane count 2
[11:57:54] [PASSED] Link rate 2000000 lane count 1
[11:57:54] [PASSED] Link rate 1350000 lane count 4
[11:57:54] [PASSED] Link rate 1350000 lane count 2
[11:57:54] [PASSED] Link rate 1350000 lane count 1
[11:57:54] [PASSED] Link rate 1000000 lane count 4
[11:57:54] [PASSED] Link rate 1000000 lane count 2
[11:57:54] [PASSED] Link rate 1000000 lane count 1
[11:57:54] [PASSED] Link rate 810000 lane count 4
[11:57:54] [PASSED] Link rate 810000 lane count 2
[11:57:54] [PASSED] Link rate 810000 lane count 1
[11:57:54] [PASSED] Link rate 540000 lane count 4
[11:57:54] [PASSED] Link rate 540000 lane count 2
[11:57:54] [PASSED] Link rate 540000 lane count 1
[11:57:54] [PASSED] Link rate 270000 lane count 4
[11:57:54] [PASSED] Link rate 270000 lane count 2
[11:57:54] [PASSED] Link rate 270000 lane count 1
[11:57:54] [PASSED] Link rate 162000 lane count 4
[11:57:54] [PASSED] Link rate 162000 lane count 2
[11:57:54] [PASSED] Link rate 162000 lane count 1
[11:57:54] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:57:54] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:57:54] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:57:54] [PASSED] DP_POWER_UP_PHY with port number
[11:57:54] [PASSED] DP_POWER_DOWN_PHY with port number
[11:57:54] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:57:54] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:57:54] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:57:54] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:57:54] [PASSED] DP_QUERY_PAYLOAD with port number
[11:57:54] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:57:54] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:57:54] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:57:54] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:57:54] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:57:54] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:57:54] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:57:54] [PASSED] DP_REMOTE_I2C_READ with port number
[11:57:54] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:57:54] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:57:54] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:57:54] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:57:54] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:57:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:57:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:57:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:57:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:57:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:57:54] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:57:54] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:57:54] ================ [PASSED] drm_dp_mst_helper ================
[11:57:54] ================== drm_exec (7 subtests) ===================
[11:57:54] [PASSED] sanitycheck
[11:57:54] [PASSED] test_lock
[11:57:54] [PASSED] test_lock_unlock
[11:57:54] [PASSED] test_duplicates
[11:57:54] [PASSED] test_prepare
[11:57:54] [PASSED] test_prepare_array
[11:57:54] [PASSED] test_multiple_loops
[11:57:54] ==================== [PASSED] drm_exec =====================
[11:57:54] =========== drm_format_helper_test (17 subtests) ===========
[11:57:54] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:57:54] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:57:54] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:57:54] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:57:54] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:57:54] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:57:54] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:57:54] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:57:54] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:57:54] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:57:54] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:57:54] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:57:54] ==================== drm_test_fb_swab  =====================
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ================ [PASSED] drm_test_fb_swab =================
[11:57:54] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:57:54] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:57:54] [PASSED] single_pixel_source_buffer
[11:57:54] [PASSED] single_pixel_clip_rectangle
[11:57:54] [PASSED] well_known_colors
[11:57:54] [PASSED] destination_pitch
[11:57:54] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:57:54] ================= drm_test_fb_clip_offset  =================
[11:57:54] [PASSED] pass through
[11:57:54] [PASSED] horizontal offset
[11:57:54] [PASSED] vertical offset
[11:57:54] [PASSED] horizontal and vertical offset
[11:57:54] [PASSED] horizontal offset (custom pitch)
[11:57:54] [PASSED] vertical offset (custom pitch)
[11:57:54] [PASSED] horizontal and vertical offset (custom pitch)
[11:57:54] ============= [PASSED] drm_test_fb_clip_offset =============
[11:57:54] =================== drm_test_fb_memcpy  ====================
[11:57:54] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:57:54] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:57:54] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:57:54] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:57:54] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:57:54] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:57:54] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:57:54] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:57:54] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:57:54] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:57:54] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:57:54] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:57:54] =============== [PASSED] drm_test_fb_memcpy ================
[11:57:54] ============= [PASSED] drm_format_helper_test ==============
[11:57:54] ================= drm_format (18 subtests) =================
[11:57:54] [PASSED] drm_test_format_block_width_invalid
[11:57:54] [PASSED] drm_test_format_block_width_one_plane
[11:57:54] [PASSED] drm_test_format_block_width_two_plane
[11:57:54] [PASSED] drm_test_format_block_width_three_plane
[11:57:54] [PASSED] drm_test_format_block_width_tiled
[11:57:54] [PASSED] drm_test_format_block_height_invalid
[11:57:54] [PASSED] drm_test_format_block_height_one_plane
[11:57:54] [PASSED] drm_test_format_block_height_two_plane
[11:57:54] [PASSED] drm_test_format_block_height_three_plane
[11:57:54] [PASSED] drm_test_format_block_height_tiled
[11:57:54] [PASSED] drm_test_format_min_pitch_invalid
[11:57:54] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:57:54] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:57:54] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:57:54] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:57:54] [PASSED] drm_test_format_min_pitch_two_plane
[11:57:54] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:57:54] [PASSED] drm_test_format_min_pitch_tiled
[11:57:54] =================== [PASSED] drm_format ====================
[11:57:54] ============== drm_framebuffer (10 subtests) ===============
[11:57:54] ========== drm_test_framebuffer_check_src_coords  ==========
[11:57:54] [PASSED] Success: source fits into fb
[11:57:54] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:57:54] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:57:54] [PASSED] Fail: overflowing fb with source width
[11:57:54] [PASSED] Fail: overflowing fb with source height
[11:57:54] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:57:54] [PASSED] drm_test_framebuffer_cleanup
[11:57:54] =============== drm_test_framebuffer_create  ===============
[11:57:54] [PASSED] ABGR8888 normal sizes
[11:57:54] [PASSED] ABGR8888 max sizes
[11:57:54] [PASSED] ABGR8888 pitch greater than min required
[11:57:54] [PASSED] ABGR8888 pitch less than min required
[11:57:54] [PASSED] ABGR8888 Invalid width
[11:57:54] [PASSED] ABGR8888 Invalid buffer handle
[11:57:54] [PASSED] No pixel format
[11:57:54] [PASSED] ABGR8888 Width 0
[11:57:54] [PASSED] ABGR8888 Height 0
[11:57:54] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:57:54] [PASSED] ABGR8888 Large buffer offset
[11:57:54] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:57:54] [PASSED] ABGR8888 Invalid flag
[11:57:54] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:57:54] [PASSED] ABGR8888 Valid buffer modifier
[11:57:54] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:57:54] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] NV12 Normal sizes
[11:57:54] [PASSED] NV12 Max sizes
[11:57:54] [PASSED] NV12 Invalid pitch
[11:57:54] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:57:54] [PASSED] NV12 different  modifier per-plane
[11:57:54] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:57:54] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] NV12 Modifier for inexistent plane
[11:57:54] [PASSED] NV12 Handle for inexistent plane
[11:57:54] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:57:54] [PASSED] YVU420 Normal sizes
[11:57:54] [PASSED] YVU420 Max sizes
[11:57:54] [PASSED] YVU420 Invalid pitch
[11:57:54] [PASSED] YVU420 Different pitches
[11:57:54] [PASSED] YVU420 Different buffer offsets/pitches
[11:57:54] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:57:54] [PASSED] YVU420 Valid modifier
[11:57:54] [PASSED] YVU420 Different modifiers per plane
[11:57:54] [PASSED] YVU420 Modifier for inexistent plane
[11:57:54] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:57:54] [PASSED] X0L2 Normal sizes
[11:57:54] [PASSED] X0L2 Max sizes
[11:57:54] [PASSED] X0L2 Invalid pitch
[11:57:54] [PASSED] X0L2 Pitch greater than minimum required
[11:57:54] [PASSED] X0L2 Handle for inexistent plane
[11:57:54] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:57:54] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:57:54] [PASSED] X0L2 Valid modifier
[11:57:54] [PASSED] X0L2 Modifier for inexistent plane
[11:57:54] =========== [PASSED] drm_test_framebuffer_create ===========
[11:57:54] [PASSED] drm_test_framebuffer_free
[11:57:54] [PASSED] drm_test_framebuffer_init
[11:57:54] [PASSED] drm_test_framebuffer_init_bad_format
[11:57:54] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:57:54] [PASSED] drm_test_framebuffer_lookup
[11:57:54] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:57:54] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:57:54] ================= [PASSED] drm_framebuffer =================
[11:57:54] ================ drm_gem_shmem (8 subtests) ================
[11:57:54] [PASSED] drm_gem_shmem_test_obj_create
[11:57:54] [PASSED] drm_gem_shmem_test_obj_create_private
[11:57:54] [PASSED] drm_gem_shmem_test_pin_pages
[11:57:54] [PASSED] drm_gem_shmem_test_vmap
[11:57:54] [PASSED] drm_gem_shmem_test_get_sg_table
[11:57:54] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:57:54] [PASSED] drm_gem_shmem_test_madvise
[11:57:54] [PASSED] drm_gem_shmem_test_purge
[11:57:54] ================== [PASSED] drm_gem_shmem ==================
[11:57:54] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:57:54] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:57:54] [PASSED] Automatic
[11:57:54] [PASSED] Full
[11:57:54] [PASSED] Limited 16:235
[11:57:54] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:57:54] [PASSED] drm_test_check_disable_connector
[11:57:54] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:57:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:57:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:57:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:57:54] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:57:54] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:57:54] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:57:54] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:57:54] [PASSED] drm_test_check_output_bpc_dvi
[11:57:54] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:57:54] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:57:54] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:57:54] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:57:54] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:57:54] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:57:54] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:57:54] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:57:54] ============ drm_test_check_hdmi_color_format  =============
[11:57:54] [PASSED] AUTO -> RGB
[11:57:54] [PASSED] YCBCR422 -> YUV422
[11:57:54] [PASSED] YCBCR420 -> YUV420
[11:57:54] [PASSED] YCBCR444 -> YUV444
[11:57:54] [PASSED] RGB -> RGB
[11:57:54] ======== [PASSED] drm_test_check_hdmi_color_format =========
[11:57:54] ======== drm_test_check_hdmi_color_format_420_only  ========
[11:57:54] [PASSED] RGB should fail
[11:57:54] [PASSED] YUV444 should fail
[11:57:54] [PASSED] YUV422 should fail
[11:57:54] [PASSED] YUV420 should work
[11:57:54] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[11:57:54] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:57:54] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:57:54] [PASSED] drm_test_check_broadcast_rgb_value
[11:57:54] [PASSED] drm_test_check_bpc_8_value
[11:57:54] [PASSED] drm_test_check_bpc_10_value
[11:57:54] [PASSED] drm_test_check_bpc_12_value
[11:57:54] [PASSED] drm_test_check_format_value
[11:57:54] [PASSED] drm_test_check_tmds_char_value
[11:57:54] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:57:54] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[11:57:54] [PASSED] drm_test_check_mode_valid
[11:57:54] [PASSED] drm_test_check_mode_valid_reject
[11:57:54] [PASSED] drm_test_check_mode_valid_reject_rate
[11:57:54] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:57:54] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[11:57:54] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[11:57:54] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[11:57:54] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:57:54] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:57:54] [PASSED] drm_test_check_infoframes
[11:57:54] [PASSED] drm_test_check_reject_avi_infoframe
[11:57:54] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:57:54] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:57:54] [PASSED] drm_test_check_reject_audio_infoframe
[11:57:54] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:57:54] ================= drm_managed (2 subtests) =================
[11:57:54] [PASSED] drm_test_managed_release_action
[11:57:54] [PASSED] drm_test_managed_run_action
[11:57:54] =================== [PASSED] drm_managed ===================
[11:57:54] =================== drm_mm (6 subtests) ====================
[11:57:54] [PASSED] drm_test_mm_init
[11:57:54] [PASSED] drm_test_mm_debug
[11:57:54] [PASSED] drm_test_mm_align32
[11:57:54] [PASSED] drm_test_mm_align64
[11:57:54] [PASSED] drm_test_mm_lowest
[11:57:54] [PASSED] drm_test_mm_highest
[11:57:54] ===================== [PASSED] drm_mm ======================
[11:57:54] ============= drm_modes_analog_tv (5 subtests) =============
[11:57:54] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:57:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:57:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:57:54] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:57:54] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:57:54] =============== [PASSED] drm_modes_analog_tv ===============
[11:57:54] ============== drm_plane_helper (2 subtests) ===============
[11:57:54] =============== drm_test_check_plane_state  ================
[11:57:54] [PASSED] clipping_simple
[11:57:54] [PASSED] clipping_rotate_reflect
[11:57:54] [PASSED] positioning_simple
[11:57:54] [PASSED] upscaling
[11:57:54] [PASSED] downscaling
[11:57:54] [PASSED] rounding1
[11:57:54] [PASSED] rounding2
[11:57:54] [PASSED] rounding3
[11:57:54] [PASSED] rounding4
[11:57:54] =========== [PASSED] drm_test_check_plane_state ============
[11:57:54] =========== drm_test_check_invalid_plane_state  ============
[11:57:54] [PASSED] positioning_invalid
[11:57:54] [PASSED] upscaling_invalid
[11:57:54] [PASSED] downscaling_invalid
[11:57:54] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:57:54] ================ [PASSED] drm_plane_helper =================
[11:57:54] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:57:54] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:57:54] [PASSED] None
[11:57:54] [PASSED] PAL
[11:57:54] [PASSED] NTSC
[11:57:54] [PASSED] Both, NTSC Default
[11:57:54] [PASSED] Both, PAL Default
[11:57:54] [PASSED] Both, NTSC Default, with PAL on command-line
[11:57:54] [PASSED] Both, PAL Default, with NTSC on command-line
[11:57:54] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:57:54] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:57:54] ================== drm_rect (9 subtests) ===================
[11:57:54] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:57:54] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:57:54] [PASSED] drm_test_rect_clip_scaled_clipped
[11:57:54] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:57:54] ================= drm_test_rect_intersect  =================
[11:57:54] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:57:54] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:57:54] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:57:54] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:57:54] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:57:54] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:57:54] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:57:54] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:57:54] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:57:54] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:57:54] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:57:54] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:57:54] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:57:54] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:57:54] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:57:54] ============= [PASSED] drm_test_rect_intersect =============
[11:57:54] ================ drm_test_rect_calc_hscale  ================
[11:57:54] [PASSED] normal use
[11:57:54] [PASSED] out of max range
[11:57:54] [PASSED] out of min range
[11:57:54] [PASSED] zero dst
[11:57:54] [PASSED] negative src
[11:57:54] [PASSED] negative dst
[11:57:54] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:57:54] ================ drm_test_rect_calc_vscale  ================
[11:57:54] [PASSED] normal use
[11:57:54] [PASSED] out of max range
[11:57:54] [PASSED] out of min range
[11:57:54] [PASSED] zero dst
[11:57:54] [PASSED] negative src
[11:57:54] [PASSED] negative dst
[11:57:54] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:57:54] ================== drm_test_rect_rotate  ===================
[11:57:54] [PASSED] reflect-x
[11:57:54] [PASSED] reflect-y
[11:57:54] [PASSED] rotate-0
[11:57:54] [PASSED] rotate-90
[11:57:54] [PASSED] rotate-180
[11:57:54] [PASSED] rotate-270
[11:57:54] ============== [PASSED] drm_test_rect_rotate ===============
[11:57:54] ================ drm_test_rect_rotate_inv  =================
[11:57:54] [PASSED] reflect-x
[11:57:54] [PASSED] reflect-y
[11:57:54] [PASSED] rotate-0
[11:57:54] [PASSED] rotate-90
[11:57:54] [PASSED] rotate-180
[11:57:54] [PASSED] rotate-270
[11:57:54] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:57:54] ==================== [PASSED] drm_rect =====================
[11:57:54] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:57:54] ============ drm_test_sysfb_build_fourcc_list  =============
[11:57:54] [PASSED] no native formats
[11:57:54] [PASSED] XRGB8888 as native format
[11:57:54] [PASSED] remove duplicates
[11:57:54] [PASSED] convert alpha formats
[11:57:54] [PASSED] random formats
[11:57:54] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:57:54] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:57:54] ================== drm_fixp (2 subtests) ===================
[11:57:54] [PASSED] drm_test_int2fixp
[11:57:54] [PASSED] drm_test_sm2fixp
[11:57:54] ==================== [PASSED] drm_fixp =====================
[11:57:54] ============================================================
[11:57:54] Testing complete. Ran 637 tests: passed: 637
[11:57:54] Elapsed time: 26.630s total, 1.739s configuring, 24.720s building, 0.153s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:57:55] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:57:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:58:06] Starting KUnit Kernel (1/1)...
[11:58:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:58:06] ================= ttm_device (5 subtests) ==================
[11:58:06] [PASSED] ttm_device_init_basic
[11:58:06] [PASSED] ttm_device_init_multiple
[11:58:06] [PASSED] ttm_device_fini_basic
[11:58:06] [PASSED] ttm_device_init_no_vma_man
[11:58:06] ================== ttm_device_init_pools  ==================
[11:58:06] [PASSED] No DMA allocations, no DMA32 required
[11:58:06] [PASSED] DMA allocations, DMA32 required
[11:58:06] [PASSED] No DMA allocations, DMA32 required
[11:58:06] [PASSED] DMA allocations, no DMA32 required
[11:58:06] ============== [PASSED] ttm_device_init_pools ==============
[11:58:06] =================== [PASSED] ttm_device ====================
[11:58:06] ================== ttm_pool (8 subtests) ===================
[11:58:06] ================== ttm_pool_alloc_basic  ===================
[11:58:06] [PASSED] One page
[11:58:06] [PASSED] More than one page
[11:58:06] [PASSED] Above the allocation limit
[11:58:06] [PASSED] One page, with coherent DMA mappings enabled
[11:58:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:58:06] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:58:06] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:58:06] [PASSED] One page
[11:58:06] [PASSED] More than one page
[11:58:06] [PASSED] Above the allocation limit
[11:58:06] [PASSED] One page, with coherent DMA mappings enabled
[11:58:06] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:58:06] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:58:06] [PASSED] ttm_pool_alloc_order_caching_match
[11:58:06] [PASSED] ttm_pool_alloc_caching_mismatch
[11:58:06] [PASSED] ttm_pool_alloc_order_mismatch
[11:58:06] [PASSED] ttm_pool_free_dma_alloc
[11:58:06] [PASSED] ttm_pool_free_no_dma_alloc
[11:58:06] [PASSED] ttm_pool_fini_basic
[11:58:06] ==================== [PASSED] ttm_pool =====================
[11:58:06] ================ ttm_resource (8 subtests) =================
[11:58:06] ================= ttm_resource_init_basic  =================
[11:58:06] [PASSED] Init resource in TTM_PL_SYSTEM
[11:58:06] [PASSED] Init resource in TTM_PL_VRAM
[11:58:06] [PASSED] Init resource in a private placement
[11:58:06] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:58:06] ============= [PASSED] ttm_resource_init_basic =============
[11:58:06] [PASSED] ttm_resource_init_pinned
[11:58:06] [PASSED] ttm_resource_fini_basic
[11:58:06] [PASSED] ttm_resource_manager_init_basic
[11:58:06] [PASSED] ttm_resource_manager_usage_basic
[11:58:06] [PASSED] ttm_resource_manager_set_used_basic
[11:58:06] [PASSED] ttm_sys_man_alloc_basic
[11:58:06] [PASSED] ttm_sys_man_free_basic
[11:58:06] ================== [PASSED] ttm_resource ===================
[11:58:06] =================== ttm_tt (15 subtests) ===================
[11:58:06] ==================== ttm_tt_init_basic  ====================
[11:58:06] [PASSED] Page-aligned size
[11:58:06] [PASSED] Extra pages requested
[11:58:06] ================ [PASSED] ttm_tt_init_basic ================
[11:58:06] [PASSED] ttm_tt_init_misaligned
[11:58:06] [PASSED] ttm_tt_fini_basic
[11:58:06] [PASSED] ttm_tt_fini_sg
[11:58:06] [PASSED] ttm_tt_fini_shmem
[11:58:06] [PASSED] ttm_tt_create_basic
[11:58:06] [PASSED] ttm_tt_create_invalid_bo_type
[11:58:06] [PASSED] ttm_tt_create_ttm_exists
[11:58:06] [PASSED] ttm_tt_create_failed
[11:58:06] [PASSED] ttm_tt_destroy_basic
[11:58:06] [PASSED] ttm_tt_populate_null_ttm
[11:58:06] [PASSED] ttm_tt_populate_populated_ttm
[11:58:06] [PASSED] ttm_tt_unpopulate_basic
[11:58:06] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:58:06] [PASSED] ttm_tt_swapin_basic
[11:58:06] ===================== [PASSED] ttm_tt ======================
[11:58:06] =================== ttm_bo (14 subtests) ===================
[11:58:06] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:58:06] [PASSED] Cannot be interrupted and sleeps
[11:58:06] [PASSED] Cannot be interrupted, locks straight away
[11:58:06] [PASSED] Can be interrupted, sleeps
[11:58:06] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:58:06] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:58:06] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:58:07] [PASSED] ttm_bo_reserve_double_resv
[11:58:07] [PASSED] ttm_bo_reserve_interrupted
[11:58:07] [PASSED] ttm_bo_reserve_deadlock
[11:58:07] [PASSED] ttm_bo_unreserve_basic
[11:58:07] [PASSED] ttm_bo_unreserve_pinned
[11:58:07] [PASSED] ttm_bo_unreserve_bulk
[11:58:07] [PASSED] ttm_bo_fini_basic
[11:58:07] [PASSED] ttm_bo_fini_shared_resv
[11:58:07] [PASSED] ttm_bo_pin_basic
[11:58:07] [PASSED] ttm_bo_pin_unpin_resource
[11:58:07] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:58:07] ===================== [PASSED] ttm_bo ======================
[11:58:07] ============== ttm_bo_validate (22 subtests) ===============
[11:58:07] ============== ttm_bo_init_reserved_sys_man  ===============
[11:58:07] [PASSED] Buffer object for userspace
[11:58:07] [PASSED] Kernel buffer object
[11:58:07] [PASSED] Shared buffer object
[11:58:07] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:58:07] ============== ttm_bo_init_reserved_mock_man  ==============
[11:58:07] [PASSED] Buffer object for userspace
[11:58:07] [PASSED] Kernel buffer object
[11:58:07] [PASSED] Shared buffer object
[11:58:07] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:58:07] [PASSED] ttm_bo_init_reserved_resv
[11:58:07] ================== ttm_bo_validate_basic  ==================
[11:58:07] [PASSED] Buffer object for userspace
[11:58:07] [PASSED] Kernel buffer object
[11:58:07] [PASSED] Shared buffer object
[11:58:07] ============== [PASSED] ttm_bo_validate_basic ==============
[11:58:07] [PASSED] ttm_bo_validate_invalid_placement
[11:58:07] ============= ttm_bo_validate_same_placement  ==============
[11:58:07] [PASSED] System manager
[11:58:07] [PASSED] VRAM manager
[11:58:07] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:58:07] [PASSED] ttm_bo_validate_failed_alloc
[11:58:07] [PASSED] ttm_bo_validate_pinned
[11:58:07] [PASSED] ttm_bo_validate_busy_placement
[11:58:07] ================ ttm_bo_validate_multihop  =================
[11:58:07] [PASSED] Buffer object for userspace
[11:58:07] [PASSED] Kernel buffer object
[11:58:07] [PASSED] Shared buffer object
[11:58:07] ============ [PASSED] ttm_bo_validate_multihop =============
[11:58:07] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:58:07] [PASSED] Buffer object in system domain, no page vector
[11:58:07] [PASSED] Buffer object in system domain with an existing page vector
[11:58:07] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:58:07] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:58:07] [PASSED] Buffer object for userspace
[11:58:07] [PASSED] Kernel buffer object
[11:58:07] [PASSED] Shared buffer object
[11:58:07] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:58:07] [PASSED] ttm_bo_validate_move_fence_signaled
[11:58:07] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:58:07] [PASSED] Waits for GPU
[11:58:07] [PASSED] Tries to lock straight away
[11:58:07] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:58:07] [PASSED] ttm_bo_validate_swapout
[11:58:07] [PASSED] ttm_bo_validate_happy_evict
[11:58:07] [PASSED] ttm_bo_validate_all_pinned_evict
[11:58:07] [PASSED] ttm_bo_validate_allowed_only_evict
[11:58:07] [PASSED] ttm_bo_validate_deleted_evict
[11:58:07] [PASSED] ttm_bo_validate_busy_domain_evict
[11:58:07] [PASSED] ttm_bo_validate_evict_gutting
[11:58:07] [PASSED] ttm_bo_validate_recrusive_evict
[11:58:07] ================= [PASSED] ttm_bo_validate =================
[11:58:07] ============================================================
[11:58:07] Testing complete. Ran 102 tests: passed: 102
[11:58:07] Elapsed time: 12.051s total, 1.762s configuring, 10.074s building, 0.185s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable CMRR in fixed-RR VRR path (rev8)

[Patchwork]

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== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev8)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

CI Bug Log - changes from xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd_BAT -> xe-pw-168613v8_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd -> xe-pw-168613v8

  IGT_9034: be1d1af352dbd4ca4557202a8ed0d6d60f95e0bf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd: 5e24f68d311764bf343f9def49b752b509dfd5fd
  xe-pw-168613v8: 168613v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/index.html

[-- Attachment #2: Type: text/html, Size: 1501 bytes --]

✓ Xe.CI.FULL: success for Enable CMRR in fixed-RR VRR path (rev8)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 46519 bytes --]

== Series Details ==

Series: Enable CMRR in fixed-RR VRR path (rev8)
URL   : https://patchwork.freedesktop.org/series/168613/
State : success

== Summary ==

CI Bug Log - changes from xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd_FULL -> xe-pw-168613v8_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-168613v8_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2652]) +7 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][2] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [PASS][3] -> [FAIL][4] ([Intel XE#301])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][5] -> [FAIL][6] ([Intel XE#301] / [Intel XE#3149])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_pm_dc@dc3co-vpb-simulation@pr-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#8395] / [Intel XE#8396])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_pm_dc@dc3co-vpb-simulation@pr-xrgb8888.html

  * igt@kms_pm_dc@dc3co-vpb-simulation@psr2-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#8396]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_pm_dc@dc3co-vpb-simulation@psr2-xrgb8888.html

  * igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#8714]) +237 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_balancer@many-execqueues-cm-virtual-userptr-rebind.html

  * igt@xe_exec_reset@long-spin-many-preempt-gt0-threads:
    - shard-bmg:          [PASS][10] -> [FAIL][11] ([Intel XE#7956])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-2/igt@xe_exec_reset@long-spin-many-preempt-gt0-threads.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-2/igt@xe_exec_reset@long-spin-many-preempt-gt0-threads.html

  * igt@xe_exec_system_allocator@many-large-mmap-shared-remap-dontunmap-eocheck:
    - shard-bmg:          [PASS][12] -> [SKIP][13] ([Intel XE#8714]) +172 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_exec_system_allocator@many-large-mmap-shared-remap-dontunmap-eocheck.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_system_allocator@many-large-mmap-shared-remap-dontunmap-eocheck.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#6964] / [Intel XE#8714])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_multigpu_svm@mgpu-xgpu-access-prefetch.html

  
#### Possible fixes ####

  * igt@core_setmaster@master-drop-set-user:
    - shard-bmg:          [FAIL][15] ([Intel XE#8599] / [Intel XE#8714]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@core_setmaster@master-drop-set-user.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@core_setmaster@master-drop-set-user.html

  * igt@fbdev@write:
    - shard-bmg:          [SKIP][17] ([Intel XE#2134]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@fbdev@write.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@fbdev@write.html

  * igt@kms_pm_rpm@legacy-planes-dpms:
    - shard-bmg:          [SKIP][19] ([Intel XE#8710] / [Intel XE#8714]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_pm_rpm@legacy-planes-dpms.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_pm_rpm@legacy-planes-dpms.html

  * igt@xe_exec_reset@long-spin-reuse-many-preempt-gt1-threads:
    - shard-bmg:          [FAIL][21] ([Intel XE#7850]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-8/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt1-threads.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-1/igt@xe_exec_reset@long-spin-reuse-many-preempt-gt1-threads.html

  * igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset:
    - shard-bmg:          [SKIP][23] ([Intel XE#8714]) -> [PASS][24] +235 other tests pass
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@xe_exec_system_allocator@many-large-execqueues-new-race-nomemset.html

  
#### Warnings ####

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-bmg:          [SKIP][25] ([Intel XE#2327]) -> [SKIP][26] ([Intel XE#8714]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-bmg:          [SKIP][27] ([Intel XE#8714]) -> [SKIP][28] ([Intel XE#2327])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-bmg:          [SKIP][29] ([Intel XE#1124]) -> [SKIP][30] ([Intel XE#8714]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-4/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-bmg:          [SKIP][31] ([Intel XE#8714]) -> [SKIP][32] ([Intel XE#1124]) +5 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-1-displays-target-2160x1440p:
    - shard-bmg:          [SKIP][33] ([Intel XE#367]) -> [SKIP][34] ([Intel XE#8714])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_bw@linear-tiling-1-displays-target-2160x1440p.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-1-displays-target-2560x1440p:
    - shard-bmg:          [SKIP][35] ([Intel XE#8714]) -> [SKIP][36] ([Intel XE#367])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_bw@linear-tiling-1-displays-target-2560x1440p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs:
    - shard-bmg:          [SKIP][37] ([Intel XE#2887]) -> [SKIP][38] ([Intel XE#8714]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][39] ([Intel XE#2652]) -> [SKIP][40] ([Intel XE#8714])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs:
    - shard-bmg:          [SKIP][41] ([Intel XE#8714]) -> [SKIP][42] ([Intel XE#2887]) +4 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][43] ([Intel XE#8714]) -> [SKIP][44] ([Intel XE#2652])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-bmg:          [SKIP][45] ([Intel XE#2724] / [Intel XE#7449]) -> [SKIP][46] ([Intel XE#8714])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_cdclk@mode-transition.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-bmg:          [SKIP][47] ([Intel XE#2325] / [Intel XE#7358]) -> [SKIP][48] ([Intel XE#8714])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_chamelium_color@ctm-blue-to-red.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-bmg:          [SKIP][49] ([Intel XE#8714]) -> [SKIP][50] ([Intel XE#2325] / [Intel XE#7358]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_chamelium_color@ctm-red-to-blue.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-bmg:          [SKIP][51] ([Intel XE#2252]) -> [SKIP][52] ([Intel XE#8714])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-bmg:          [SKIP][53] ([Intel XE#8714]) -> [SKIP][54] ([Intel XE#2252]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-bmg:          [FAIL][55] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][56] ([Intel XE#8714])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_content_protection@atomic-hdcp14.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-bmg:          [SKIP][57] ([Intel XE#8714]) -> [SKIP][58] ([Intel XE#2390] / [Intel XE#6974])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_content_protection@dp-mst-lic-type-0.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-bmg:          [SKIP][59] ([Intel XE#6974]) -> [SKIP][60] ([Intel XE#8714])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][61] ([Intel XE#8714]) -> [FAIL][62] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_content_protection@srm.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-bmg:          [SKIP][63] ([Intel XE#2321] / [Intel XE#7355]) -> [SKIP][64] ([Intel XE#8714])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-bmg:          [SKIP][65] ([Intel XE#8714]) -> [SKIP][66] ([Intel XE#2320])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_cursor_crc@cursor-random-128x42.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-bmg:          [SKIP][67] ([Intel XE#2320]) -> [SKIP][68] ([Intel XE#8714])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][69] ([Intel XE#2286] / [Intel XE#6035]) -> [SKIP][70] ([Intel XE#8714])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-bmg:          [SKIP][71] ([Intel XE#8714]) -> [SKIP][72] ([Intel XE#8265]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@psr2:
    - shard-bmg:          [SKIP][73] ([Intel XE#2374] / [Intel XE#6128]) -> [SKIP][74] ([Intel XE#8714])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_feature_discovery@psr2.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][75] ([Intel XE#301]) -> [FAIL][76] ([Intel XE#301] / [Intel XE#3149])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-bmg:          [SKIP][77] ([Intel XE#8714]) -> [SKIP][78] ([Intel XE#7178] / [Intel XE#7349])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-bmg:          [SKIP][79] ([Intel XE#8714]) -> [SKIP][80] ([Intel XE#2311]) +20 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][81] ([Intel XE#4141]) -> [SKIP][82] ([Intel XE#8714]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][83] ([Intel XE#8714]) -> [SKIP][84] ([Intel XE#4141]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][85] ([Intel XE#2311]) -> [SKIP][86] ([Intel XE#8714]) +15 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-move.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrshdr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-blt:
    - shard-bmg:          [SKIP][87] ([Intel XE#7061]) -> [SKIP][88] ([Intel XE#8714]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-blt.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_frontbuffer_tracking@fbchdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][89] ([Intel XE#8714]) -> [SKIP][90] ([Intel XE#2313]) +22 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt:
    - shard-bmg:          [SKIP][91] ([Intel XE#8714]) -> [SKIP][92] ([Intel XE#7061]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][93] ([Intel XE#2313]) -> [SKIP][94] ([Intel XE#8714]) +15 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt:
    - shard-bmg:          [SKIP][95] ([Intel XE#7061] / [Intel XE#7356]) -> [SKIP][96] ([Intel XE#8714]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-argb161616f-draw-render:
    - shard-bmg:          [SKIP][97] ([Intel XE#8714]) -> [SKIP][98] ([Intel XE#7061] / [Intel XE#7356])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-render.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-bmg:          [SKIP][99] ([Intel XE#7308]) -> [SKIP][100] ([Intel XE#8714])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_hdmi_inject@inject-audio.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-bmg:          [SKIP][101] ([Intel XE#8714]) -> [SKIP][102] ([Intel XE#7283])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          [SKIP][103] ([Intel XE#7283]) -> [SKIP][104] ([Intel XE#8714]) +2 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
    - shard-bmg:          [SKIP][105] ([Intel XE#2763] / [Intel XE#6886]) -> [SKIP][106] ([Intel XE#8714])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-bmg:          [SKIP][107] ([Intel XE#8714]) -> [SKIP][108] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_pm_backlight@fade-with-dpms.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-bmg:          [SKIP][109] ([Intel XE#8714]) -> [SKIP][110] ([Intel XE#8395] / [Intel XE#8396])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-bmg:          [SKIP][111] ([Intel XE#8714]) -> [SKIP][112] ([Intel XE#1489]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          [SKIP][113] ([Intel XE#1489]) -> [SKIP][114] ([Intel XE#8714]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          [SKIP][115] ([Intel XE#8714]) -> [SKIP][116] ([Intel XE#2387] / [Intel XE#7429])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          [SKIP][117] ([Intel XE#8714]) -> [SKIP][118] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_psr@fbc-psr2-cursor-plane-move.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@psr-primary-blt:
    - shard-bmg:          [SKIP][119] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][120] ([Intel XE#8714]) +2 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_psr@psr-primary-blt.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_psr@psr-primary-blt.html

  * igt@kms_psr@psr2-primary-render:
    - shard-bmg:          [SKIP][121] ([Intel XE#8714]) -> [SKIP][122] ([Intel XE#2234])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_psr@psr2-primary-render.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_psr@psr2-primary-render.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-bmg:          [SKIP][123] ([Intel XE#3904] / [Intel XE#7342]) -> [SKIP][124] ([Intel XE#8714])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@kms_rotation_crc@bad-tiling.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          [SKIP][125] ([Intel XE#8714]) -> [SKIP][126] ([Intel XE#3904] / [Intel XE#7342])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_rotation_crc@primary-rotation-90.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-bmg:          [SKIP][127] ([Intel XE#8714]) -> [SKIP][128] ([Intel XE#2413])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_scaling_modes@scaling-mode-full-aspect.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-bmg:          [SKIP][129] ([Intel XE#8714]) -> [SKIP][130] ([Intel XE#1435] / [Intel XE#8695])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_setmode@invalid-clone-exclusive-crtc.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sharpness_filter@filter-dpms:
    - shard-bmg:          [SKIP][131] ([Intel XE#8714]) -> [SKIP][132] ([Intel XE#6503])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@kms_sharpness_filter@filter-dpms.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@kms_sharpness_filter@filter-dpms.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][133] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][134] ([Intel XE#2426] / [Intel XE#5848])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_compute@ccs-mode-compute-kernel:
    - shard-bmg:          [SKIP][135] ([Intel XE#8714]) -> [SKIP][136] ([Intel XE#6599])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_compute@ccs-mode-compute-kernel.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_compute@ccs-mode-compute-kernel.html

  * igt@xe_configfs@engines-allowed-invalid:
    - shard-bmg:          [ABORT][137] ([Intel XE#8007]) -> [SKIP][138] ([Intel XE#8714])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-4/igt@xe_configfs@engines-allowed-invalid.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_configfs@engines-allowed-invalid.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-bmg:          [SKIP][139] ([Intel XE#2322] / [Intel XE#7372]) -> [SKIP][140] ([Intel XE#8714]) +2 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind:
    - shard-bmg:          [SKIP][141] ([Intel XE#8714]) -> [SKIP][142] ([Intel XE#2322] / [Intel XE#7372]) +3 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-multi-queue-invalid-userptr-fault:
    - shard-bmg:          [SKIP][143] ([Intel XE#8714]) -> [SKIP][144] ([Intel XE#8374]) +4 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_exec_fault_mode@many-multi-queue-invalid-userptr-fault.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@xe_exec_fault_mode@many-multi-queue-invalid-userptr-fault.html

  * igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch:
    - shard-bmg:          [SKIP][145] ([Intel XE#8374]) -> [SKIP][146] ([Intel XE#8714]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem:
    - shard-bmg:          [SKIP][147] ([Intel XE#8364]) -> [SKIP][148] ([Intel XE#8714]) +5 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_multi_queue@one-queue-preempt-mode-close-fd-smem.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr:
    - shard-bmg:          [SKIP][149] ([Intel XE#8714]) -> [SKIP][150] ([Intel XE#8364]) +8 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr.html

  * igt@xe_exec_reset@cm-multi-queue-close-execqueues:
    - shard-bmg:          [SKIP][151] ([Intel XE#8714]) -> [SKIP][152] ([Intel XE#8369])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_exec_reset@cm-multi-queue-close-execqueues.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_exec_reset@cm-multi-queue-close-execqueues.html

  * igt@xe_exec_reset@multi-queue-close-execqueues:
    - shard-bmg:          [SKIP][153] ([Intel XE#8369]) -> [SKIP][154] ([Intel XE#8714]) +1 other test skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_exec_reset@multi-queue-close-execqueues.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_reset@multi-queue-close-execqueues.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind:
    - shard-bmg:          [SKIP][155] ([Intel XE#8714]) -> [SKIP][156] ([Intel XE#8378]) +2 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind.html

  * igt@xe_exec_threads@threads-multi-queue-userptr:
    - shard-bmg:          [SKIP][157] ([Intel XE#8378]) -> [SKIP][158] ([Intel XE#8714]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_exec_threads@threads-multi-queue-userptr.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_exec_threads@threads-multi-queue-userptr.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          [SKIP][159] ([Intel XE#586] / [Intel XE#7323] / [Intel XE#7384]) -> [SKIP][160] ([Intel XE#8714])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_mmap@small-bar.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_mmap@small-bar.html

  * igt@xe_module_load@force-load:
    - shard-bmg:          [FAIL][161] ([Intel XE#8714]) -> [ABORT][162] ([Intel XE#8007])
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_module_load@force-load.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@xe_module_load@force-load.html

  * igt@xe_multigpu_svm@mgpu-xgpu-access-basic:
    - shard-bmg:          [SKIP][163] ([Intel XE#6964]) -> [SKIP][164] ([Intel XE#6964] / [Intel XE#8714])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-3/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-7/igt@xe_multigpu_svm@mgpu-xgpu-access-basic.html

  * igt@xe_pat@pat-index-xehpc:
    - shard-bmg:          [SKIP][165] ([Intel XE#8714]) -> [SKIP][166] ([Intel XE#1420] / [Intel XE#7590])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_pat@pat-index-xehpc.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@xe_pat@pat-index-xehpc.html

  * igt@xe_pm@d3cold-i2c:
    - shard-bmg:          [SKIP][167] ([Intel XE#8714]) -> [SKIP][168] ([Intel XE#5694] / [Intel XE#7370])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_pm@d3cold-i2c.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pxp@pxp-optout:
    - shard-bmg:          [SKIP][169] ([Intel XE#8714]) -> [SKIP][170] ([Intel XE#4733] / [Intel XE#7417])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_pxp@pxp-optout.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-9/igt@xe_pxp@pxp-optout.html

  * igt@xe_query@multigpu-query-invalid-size:
    - shard-bmg:          [SKIP][171] ([Intel XE#8714]) -> [SKIP][172] ([Intel XE#944]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd/shard-bmg-7/igt@xe_query@multigpu-query-invalid-size.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/shard-bmg-5/igt@xe_query@multigpu-query-invalid-size.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1420]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1420
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2134]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2134
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2286]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2286
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6128
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
  [Intel XE#7323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7323
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7384]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7384
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7449]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7449
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7850
  [Intel XE#7956]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7956
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
  [Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
  [Intel XE#8599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8599
  [Intel XE#8695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8695
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8710]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8710
  [Intel XE#8714]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8714
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd -> xe-pw-168613v8

  IGT_9034: be1d1af352dbd4ca4557202a8ed0d6d60f95e0bf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-5508-5e24f68d311764bf343f9def49b752b509dfd5fd: 5e24f68d311764bf343f9def49b752b509dfd5fd
  xe-pw-168613v8: 168613v8

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-168613v8/index.html

[-- Attachment #2: Type: text/html, Size: 57440 bytes --]

Re: [PATCH v8 07/10] drm/i915/vrr: Latch CMRR ratio via atomic commit on debugfs write

[Borah, Chaitanya Kumar]

On 7/30/2026 4:29 PM, Mitul Golani wrote:
> Writing the per-CRTC "intel_vrr_target_refresh_rate" debugfs file only
> updates crtc->force_cmrr, a side channel that is not tracked by the
> atomic state. The requested ratio therefore does not reach the hardware
> until some unrelated commit recomputes the pipe config.
> 
> Kick an internal atomic commit for the CRTC from the debugfs write and
> mark the CRTC mode as changed so the pipe config is recomputed.
> 
> Note that this commit may or may not be downgraded to a fastset,
> depending on whether the computed vblank value (with LRR disabled)
> changes, so it is not characterised as a fastset.
> 
> If the commit fails, restore the previous numerator/denominator so that
> force_cmrr does not hold on to bad values, which would otherwise make
> all subsequent commits fail.
> 
> --v2:
> - Commit message and code comment update (Chaitanya)
> - Commit header update
> - Restore to old known debugfs values when commit fails
> (Chaitanya)
> 

LGTM,

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 77 ++++++++++++++++++++++++
>   1 file changed, 77 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index f406f34b816e..3463533b1ea1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -8,10 +8,12 @@
>   #include <linux/seq_file.h>
>   #include <linux/string.h>
>   
> +#include <drm/drm_atomic.h>
>   #include <drm/drm_print.h>
>   #include <drm/intel/step.h>
>   
>   #include "intel_alpm.h"
> +#include "intel_atomic.h"
>   #include "intel_cmtg.h"
>   #include "intel_crtc.h"
>   #include "intel_de.h"
> @@ -1304,12 +1306,67 @@ static int intel_vrr_debugfs_target_rr_open(struct inode *inode, struct file *fi
>   	return single_open(file, intel_vrr_debugfs_target_rr_show, inode->i_private);
>   }
>   
> +/*
> + * Force an internal commit on @crtc so that a CMRR ratio programmed
> + * via debugfs gets recomputed and latched into hardware.
> + *
> + * CMRR only alters the (average) vtotal. Depending on whether the
> + * computed vblank value (with LRR disabled) changes, this commit may or
> + * may not be downgraded to a fastset.
> + */
> +static int intel_vrr_cmrr_commit_force(struct intel_crtc *crtc)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct drm_modeset_acquire_ctx ctx;
> +	struct drm_atomic_commit *state;
> +	struct intel_crtc_state *crtc_state;
> +	int ret = 0;
> +
> +	state = drm_atomic_commit_alloc(display->drm);
> +	if (!state)
> +		return -ENOMEM;
> +
> +	drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
> +
> +	state->acquire_ctx = &ctx;
> +	to_intel_atomic_state(state)->internal = true;
> +
> +retry:
> +	crtc_state = intel_atomic_get_crtc_state(state, crtc);
> +	if (IS_ERR(crtc_state)) {
> +		ret = PTR_ERR(crtc_state);
> +		goto out;
> +	}
> +
> +	if (!crtc_state->hw.active)
> +		goto out;
> +
> +	/* Mark mode as changed to trigger a pipe recompute + update() */
> +	crtc_state->uapi.mode_changed = true;
> +
> +	ret = drm_atomic_commit(state);
> +out:
> +	if (ret == -EDEADLK) {
> +		drm_atomic_commit_clear(state);
> +		ret = drm_modeset_backoff(&ctx);
> +		if (!ret)
> +			goto retry;
> +	}
> +
> +	drm_modeset_drop_locks(&ctx);
> +	drm_modeset_acquire_fini(&ctx);
> +	drm_atomic_commit_put(state);
> +
> +	return ret;
> +}
> +
>   static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char __user *ubuf,
>   						 size_t len, loff_t *offp)
>   {
>   	struct seq_file *m = file->private_data;
>   	struct intel_crtc *crtc = m->private;
>   	u32 numerator, denominator;
> +	u32 old_numerator, old_denominator;
>   	char kbuf[32];
>   	int ret;
>   
> @@ -1329,9 +1386,29 @@ static ssize_t intel_vrr_debugfs_target_rr_write(struct file *file, const char _
>   	    crtc->force_cmrr.denominator == denominator)
>   		return len;
>   
> +	old_numerator = crtc->force_cmrr.numerator;
> +	old_denominator = crtc->force_cmrr.denominator;
> +
>   	crtc->force_cmrr.numerator = numerator;
>   	crtc->force_cmrr.denominator = denominator;
>   
> +	/*
> +	 * The debugfs value is a side channel that is not tracked by the atomic
> +	 * state, so kick an internal commit to recompute and latch the
> +	 * new CMRR parameters.
> +	 */
> +	ret = intel_vrr_cmrr_commit_force(crtc);
> +	if (ret) {
> +		/*
> +		 * Restore the last known good ratio so that force_cmrr does not
> +		 * hold on to bad values, which would make all subsequent commits
> +		 * fail.
> +		 */
> +		crtc->force_cmrr.numerator = old_numerator;
> +		crtc->force_cmrr.denominator = old_denominator;
> +		return ret;
> +	}
> +
>   	return len;
>   }
>   

Re: [PATCH v8 10/10] drm/i915/vrr: Enable cmrr

[Borah, Chaitanya Kumar]

On 7/30/2026 4:29 PM, Mitul Golani wrote:
> Set crtc_state->vrr.cmrr.enable at the end of
> intel_vrr_cmrr_compute_config() so that CMRR is actually enabled once
> the M/N parameters have been computed. This is the final step that
> turns on CMRR, with all the parameter computation handled in the
> earlier patches.
> 
> --v2:
> - Everything else except enable compute to handle before this patch
> (Chaitanya)
> 
> --v3:
> - Remove redundant return from compute config
> 
> --v4:
> - Update CMRR commit message (Chaitanya)
> 

LGTM,

Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vrr.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 653581ed4e90..e36db1174440 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -269,6 +269,8 @@ intel_vrr_cmrr_compute_config(struct intel_crtc_state *crtc_state)
>   	adjusted_mode->crtc_vtotal = div64_u64_rem(dividend,
>   						   crtc_state->vrr.cmrr.cmrr_n,
>   						   &crtc_state->vrr.cmrr.cmrr_m);
> +
> +	crtc_state->vrr.cmrr.enable = true;
>   }
>   
>   static