[PATCH v4 0/8] drm/i915: move more display dependencies from i915

[PATCH v4 0/8] drm/i915: move more display dependencies from i915

[Luca Coelho]

This series continues my work of refactoring the clock gating
initialization, so that i915 doesn't do display-specific stuff.

With this, all register dependencies should be gone.

Changes in v4:
	* Explain why HAS_LLC() is not needed anymore (Jani);
	* Replace intel_display_core.h include with intel_pch.h (Jani);

Please review.

Cheers,
Luca.


Luca Coelho (8):
  drm/i915: move SKL clock gating init to display
  drm/i915: move KBL clock gating init to display
  drm/i915/display: move CFL clock gating init to display
  drm/i915/display: move BXT clock gating init to display
  drm/i915/display: move GLK clock gating init to display
  drm/i915/display: move HSW and BDW clock gating init to display
  drm/i915/display: move pre-HSW clock gating init to display
  drm/i915: remove HAS_PCH_NOP() dependency from clock gating

 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../i915/display/intel_display_clock_gating.c | 255 ++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  27 ++
 .../gpu/drm/i915/display/intel_display_regs.h |  31 +++
 drivers/gpu/drm/i915/i915_reg.h               |  31 ---
 drivers/gpu/drm/i915/intel_clock_gating.c     | 226 ++--------------
 6 files changed, 331 insertions(+), 240 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

-- 
2.53.0

[PATCH v4 1/8] drm/i915: move SKL clock gating init to display

[Luca Coelho]

Move the SKL-specific display clock gating programming into a new file
inside display.

This removes dependency from intel_clock_gating.c to the display's
intel_pch.h file, so we can remove the include statement.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 .../i915/display/intel_display_clock_gating.c | 19 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_clock_gating.c     |  8 ++------
 4 files changed, 35 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index fa632f4e505c..07802a7f4ce5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -256,6 +256,7 @@ i915-y += \
 	display/intel_cursor.o \
 	display/intel_dbuf_bw.o \
 	display/intel_de.o \
+	display/intel_display_clock_gating.o \
 	display/intel_display.o \
 	display/intel_display_conversion.o \
 	display/intel_display_driver.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
new file mode 100644
index 000000000000..4a94593335e0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright 2026 Intel Corporation
+ */
+
+#include <drm/intel/intel_gmd_misc_regs.h>
+
+#include "intel_de.h"
+#include "intel_display_clock_gating.h"
+#include "intel_display_regs.h"
+
+void intel_display_skl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:skl
+	 * Display WA #0562: skl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
new file mode 100644
index 000000000000..00f416db7f47
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_CLOCK_GATING_H__
+#define __INTEL_DISPLAY_CLOCK_GATING_H__
+
+struct intel_display;
+
+void intel_display_skl_init_clock_gating(struct intel_display *display);
+
+#endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 515f83c82abc..ad28ceee012b 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -32,9 +32,9 @@
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"
+#include "display/intel_display_clock_gating.h"
 #include "display/intel_display_core.h"
 #include "display/intel_display_regs.h"
-#include "display/intel_pch.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -349,11 +349,7 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
 	/* WAC6entrylatency:skl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:skl
-	 * Display WA #0562: skl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_skl_init_clock_gating(i915->display);
 }
 
 static void bdw_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v4 2/8] drm/i915: move KBL clock gating init to display

[Luca Coelho]

Move the KBL-specific display clock gating programming into a
display intel_display_clock_gating.c, to remove more dependencies from
i915 to display registers.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../gpu/drm/i915/display/intel_display_clock_gating.c    | 9 +++++++++
 .../gpu/drm/i915/display/intel_display_clock_gating.h    | 1 +
 drivers/gpu/drm/i915/intel_clock_gating.c                | 6 +-----
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 4a94593335e0..508735212d6b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -17,3 +17,12 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_kbl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:kbl
+	 * Display WA #0562: kbl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 00f416db7f47..8c21217de66a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -9,5 +9,6 @@
 struct intel_display;
 
 void intel_display_skl_init_clock_gating(struct intel_display *display);
+void intel_display_kbl_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index ad28ceee012b..c446e4ac92f1 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -331,11 +331,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 		intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
 				 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:kbl
-	 * Display WA #0562: kbl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_kbl_init_clock_gating(i915->display);
 }
 
 static void skl_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v4 3/8] drm/i915/display: move CFL clock gating init to display

[Luca Coelho]

Move the CFL/CML-specific display clock gating programming into
display intel_display_clock_gating.c, to remove more dependencies from
i915 to display registers.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../gpu/drm/i915/display/intel_display_clock_gating.c    | 9 +++++++++
 .../gpu/drm/i915/display/intel_display_clock_gating.h    | 1 +
 drivers/gpu/drm/i915/intel_clock_gating.c                | 6 +-----
 3 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 508735212d6b..82ea21d7377d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -26,3 +26,12 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_cfl_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * WaFbcTurnOffFbcWatermark:cfl
+	 * Display WA #0562: cfl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 8c21217de66a..63960f1e80fc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -10,5 +10,6 @@ struct intel_display;
 
 void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
+void intel_display_cfl_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index c446e4ac92f1..80d7f057cb81 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -307,11 +307,7 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
 	/* WAC6entrylatency:cfl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
-	/*
-	 * WaFbcTurnOffFbcWatermark:cfl
-	 * Display WA #0562: cfl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_cfl_init_clock_gating(i915->display);
 }
 
 static void kbl_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v4 4/8] drm/i915/display: move BXT clock gating init to display

[Luca Coelho]

Move the BXT-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 25 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  1 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 22 +---------------
 3 files changed, 27 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 82ea21d7377d..59041c807d6d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -35,3 +35,28 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_bxt_init_clock_gating(struct intel_display *display)
+{
+	/*
+	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
+	 * to stay fully on.
+	 */
+	intel_de_write(display, GEN9_CLKGATE_DIS_0,
+		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
+		       PWM1_GATING_DIS | PWM2_GATING_DIS);
+
+	/*
+	 * Lower the display internal timeout.
+	 * This is needed to avoid any hard hangs when DSI port PLL
+	 * is off and a MMIO access is attempted by any privilege
+	 * application, using batch buffers or any other means.
+	 */
+	intel_de_write(display, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+
+	/*
+	 * WaFbcTurnOffFbcWatermark:bxt
+	 * Display WA #0562: bxt
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 63960f1e80fc..6bc84a9a4342 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -11,5 +11,6 @@ struct intel_display;
 void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
+void intel_display_bxt_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 80d7f057cb81..a9efa5ce8f6a 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -88,27 +88,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
 	 */
 	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
 
-	/*
-	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
-	 * to stay fully on.
-	 */
-	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
-			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
-			   PWM1_GATING_DIS | PWM2_GATING_DIS);
-
-	/*
-	 * Lower the display internal timeout.
-	 * This is needed to avoid any hard hangs when DSI port PLL
-	 * is off and a MMIO access is attempted by any privilege
-	 * application, using batch buffers or any other means.
-	 */
-	intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
-
-	/*
-	 * WaFbcTurnOffFbcWatermark:bxt
-	 * Display WA #0562: bxt
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+	intel_display_bxt_init_clock_gating(i915->display);
 }
 
 static void glk_init_clock_gating(struct drm_i915_private *i915)
-- 
2.53.0

[PATCH v4 5/8] drm/i915/display: move GLK clock gating init to display

[Luca Coelho]

Move the GLK-specific display clock gating programming into display
intel_display_clock_gating.c, to remove more dependencies from i915 to
display registers.

Now that all remaining Gen9-family callers moved into display, we can
move the shared Gen9 display clock gating helper into display and
remove the old local helper from intel_clock_gating.c.

Additionally, the SKL_DE_COMPRESSED_HASH_MODE programming was
protected by HAS_LLC(), but that's incidental, because in Gen9
platforms, only SKL and KBL, for which this workaround applies, have
LLC().  In order not to use HAS_LLC() in display code, we can simply
remove this check from the generic Gen9 function and move the
SKL_DE_COMPRESSED_HASH_MODE programming to the KBL and SKL specific
functions.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 57 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  1 +
 drivers/gpu/drm/i915/intel_clock_gating.c     | 44 +-------------
 3 files changed, 59 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 59041c807d6d..b2cb18478577 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -6,11 +6,39 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "intel_de.h"
+#include "intel_display.h"
 #include "intel_display_clock_gating.h"
+#include "intel_display_core.h"
 #include "intel_display_regs.h"
 
+static void intel_display_gen9_init_clock_gating(struct intel_display *display)
+{
+	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
+
+	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
+	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
+
+	/*
+	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
+	 * Display WA #0859: skl,bxt,kbl,glk,cfl
+	 */
+	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
+}
+
 void intel_display_skl_init_clock_gating(struct intel_display *display)
 {
+	/*
+	 * WaCompressedResourceDisplayNewHashMode:skl,kbl
+	 * Display WA #0390: skl,kbl
+	 *
+	 * Must match Sampler, Pixel Back End, and Media. See
+	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
+	 */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
+
+	intel_display_gen9_init_clock_gating(display);
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:skl
 	 * Display WA #0562: skl
@@ -20,6 +48,17 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
 
 void intel_display_kbl_init_clock_gating(struct intel_display *display)
 {
+	/*
+	 * WaCompressedResourceDisplayNewHashMode:skl,kbl
+	 * Display WA #0390: skl,kbl
+	 *
+	 * Must match Sampler, Pixel Back End, and Media. See
+	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
+	 */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
+
+	intel_display_gen9_init_clock_gating(display);
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:kbl
 	 * Display WA #0562: kbl
@@ -29,6 +68,8 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
 
 void intel_display_cfl_init_clock_gating(struct intel_display *display)
 {
+	intel_display_gen9_init_clock_gating(display);
+
 	/*
 	 * WaFbcTurnOffFbcWatermark:cfl
 	 * Display WA #0562: cfl
@@ -38,6 +79,8 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
 
 void intel_display_bxt_init_clock_gating(struct intel_display *display)
 {
+	intel_display_gen9_init_clock_gating(display);
+
 	/*
 	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
 	 * to stay fully on.
@@ -60,3 +103,17 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
 	 */
 	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
 }
+
+void intel_display_glk_init_clock_gating(struct intel_display *display)
+{
+	intel_display_gen9_init_clock_gating(display);
+
+	/*
+	 * WaDisablePWMClockGating:glk
+	 * Backlight PWM may stop in the asserted state, causing backlight
+	 * to stay fully on.
+	 */
+	intel_de_write(display, GEN9_CLKGATE_DIS_0,
+		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
+		       PWM1_GATING_DIS | PWM2_GATING_DIS);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index 6bc84a9a4342..a7784db9d97a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -12,5 +12,6 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
 void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
 void intel_display_bxt_init_clock_gating(struct intel_display *display);
+void intel_display_glk_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index a9efa5ce8f6a..96fe16753e58 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
 	void (*init_clock_gating)(struct drm_i915_private *i915);
 };
 
-static void gen9_init_clock_gating(struct drm_i915_private *i915)
-{
-	if (HAS_LLC(i915)) {
-		/*
-		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
-		 * Display WA #0390: skl,kbl
-		 *
-		 * Must match Sampler, Pixel Back End, and Media. See
-		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
-		 */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
-	}
-
-	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
-
-	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
-	intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
-
-	/*
-	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
-	 * Display WA #0859: skl,bxt,kbl,glk,cfl
-	 */
-	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
-}
-
 static void bxt_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WaDisableSDEUnitClockGating:bxt */
 	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
@@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
 
 static void glk_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
-	/*
-	 * WaDisablePWMClockGating:glk
-	 * Backlight PWM may stop in the asserted state, causing backlight
-	 * to stay fully on.
-	 */
-	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
-			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
-			   PWM1_GATING_DIS | PWM2_GATING_DIS);
+	intel_display_glk_init_clock_gating(i915->display);
 }
 
 static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
@@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
 static void cfl_init_clock_gating(struct drm_i915_private *i915)
 {
 	intel_pch_init_clock_gating(i915->display);
-	gen9_init_clock_gating(i915);
 
 	/* WAC6entrylatency:cfl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
@@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
 
 static void kbl_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WAC6entrylatency:kbl */
 	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
 
@@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
 
 static void skl_init_clock_gating(struct drm_i915_private *i915)
 {
-	gen9_init_clock_gating(i915);
-
 	/* WaDisableDopClockGating:skl */
 	intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
 			 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
-- 
2.53.0

[PATCH v4 6/8] drm/i915/display: move HSW and BDW clock gating init to display

[Luca Coelho]

Move the HSW and BDW display clock gating programming into the display
code.  In this case we need two different helpers, because the common
code between these two is split in the middle.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c | 44 +++++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |  4 ++
 .../gpu/drm/i915/display/intel_display_regs.h |  3 ++
 drivers/gpu/drm/i915/i915_reg.h               |  3 --
 drivers/gpu/drm/i915/intel_clock_gating.c     | 34 ++------------
 5 files changed, 55 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index b2cb18478577..6ba65f6cbeae 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -117,3 +117,47 @@ void intel_display_glk_init_clock_gating(struct intel_display *display)
 		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
 		       PWM1_GATING_DIS | PWM2_GATING_DIS);
 }
+
+void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display)
+{
+	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
+	intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+}
+
+void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	/* WaPsrDPAMaskVBlankInSRD:hsw */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
+
+	for_each_pipe(display, pipe) {
+		/* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */
+		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0,
+			     BDW_UNMASK_VBL_TO_REGS_IN_SRD);
+	}
+}
+
+void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display)
+{
+	/* WaKVMNotificationOnConfigChange:bdw */
+	intel_de_rmw(display, CHICKEN_PAR2_1, 0,
+		     KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+}
+
+void intel_display_hsw_init_clock_gating(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
+	intel_de_rmw(display, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+
+	/* WaPsrDPAMaskVBlankInSRD:hsw */
+	intel_de_rmw(display, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
+
+	for_each_pipe(display, pipe) {
+		/* WaPsrDPRSUnmaskVBlankInSRD:hsw,bdw */
+		intel_de_rmw(display, CHICKEN_PIPESL_1(pipe), 0,
+			     HSW_UNMASK_VBL_TO_REGS_IN_SRD);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index a7784db9d97a..e0300dc8b041 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -13,5 +13,9 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display);
 void intel_display_cfl_init_clock_gating(struct intel_display *display);
 void intel_display_bxt_init_clock_gating(struct intel_display *display);
 void intel_display_glk_init_clock_gating(struct intel_display *display);
+void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
+void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
+void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
+void intel_display_hsw_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dada8dc27ea4..1cb87ba0ebeb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -405,6 +405,9 @@
 #define   SKL_EDP_PSR_FIX_RDWRAP	REG_BIT(3)
 #define   IGNORE_PSR2_HW_TRACKING	REG_BIT(1)
 
+#define CHICKEN_PAR2_1		_MMIO(0x42090)
+#define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
+
 /*
  * GEN9 clock gating regs
  */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d99b99b0c57..e9d7f1c3a288 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -717,9 +717,6 @@
 #define   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	REG_BIT(5)
 #define   CHICKEN3_DGMG_DONE_FIX_DISABLE	REG_BIT(2)
 
-#define CHICKEN_PAR2_1		_MMIO(0x42090)
-#define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	REG_BIT(14)
-
 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
 
 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 96fe16753e58..10aa00e003be 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -284,23 +284,12 @@ static void skl_init_clock_gating(struct drm_i915_private *i915)
 
 static void bdw_init_clock_gating(struct drm_i915_private *i915)
 {
-	struct intel_display *display = i915->display;
-	enum pipe pipe;
-
-	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+	intel_display_bdw_clock_gating_disable_fbcq(i915->display);
 
 	/* WaSwitchSolVfFArbitrationPriority:bdw */
 	intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
 
-	/* WaPsrDPAMaskVBlankInSRD:bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
-
-	for_each_pipe(display, pipe) {
-		/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
-				 0, BDW_UNMASK_VBL_TO_REGS_IN_SRD);
-	}
+	intel_display_bdw_clock_gating_vblank_in_srd(i915->display);
 
 	/* WaVSRefCountFullforceMissDisable:bdw */
 	/* WaDSRefCountFullforceMissDisable:bdw */
@@ -316,9 +305,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
 	/* WaProgramL3SqcReg1Default:bdw */
 	gen8_set_l3sqc_credits(i915, 30, 2);
 
-	/* WaKVMNotificationOnConfigChange:bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
-			 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
+	intel_display_bdw_clock_gating_kvm_notif(i915->display);
 
 	intel_pch_init_clock_gating(i915->display);
 
@@ -332,20 +319,7 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915)
 
 static void hsw_init_clock_gating(struct drm_i915_private *i915)
 {
-	struct intel_display *display = i915->display;
-	enum pipe pipe;
-
-	/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
-
-	/* WaPsrDPAMaskVBlankInSRD:hsw */
-	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD);
-
-	for_each_pipe(display, pipe) {
-		/* WaPsrDPRSUnmaskVBlankInSRD:hsw */
-		intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
-				 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD);
-	}
+	intel_display_hsw_init_clock_gating(i915->display);
 
 	/* This is required by WaCatErrorRejectionIssue:hsw */
 	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
-- 
2.53.0

[PATCH v4 7/8] drm/i915/display: move pre-HSW clock gating init to display

[Luca Coelho]

Move the remaining pre-HSW display clock gating programming into
display.

This also drops display register includes from intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 .../i915/display/intel_display_clock_gating.c |  92 ++++++++++++++++
 .../i915/display/intel_display_clock_gating.h |   6 +
 .../gpu/drm/i915/display/intel_display_regs.h |  28 +++++
 drivers/gpu/drm/i915/i915_reg.h               |  28 -----
 drivers/gpu/drm/i915/intel_clock_gating.c     | 103 +-----------------
 5 files changed, 132 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
index 6ba65f6cbeae..585b208fc6c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
@@ -6,6 +6,7 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "intel_de.h"
+#include "i9xx_plane_regs.h"
 #include "intel_display.h"
 #include "intel_display_clock_gating.h"
 #include "intel_display_core.h"
@@ -161,3 +162,94 @@ void intel_display_hsw_init_clock_gating(struct intel_display *display)
 			     HSW_UNMASK_VBL_TO_REGS_IN_SRD);
 	}
 }
+
+void intel_display_disable_trickle_feed(struct intel_display *display)
+{
+	enum pipe pipe;
+
+	for_each_pipe(display, pipe) {
+		intel_de_rmw(display, DSPCNTR(display, pipe), 0,
+			     DISP_TRICKLE_FEED_DISABLE);
+
+		intel_de_rmw(display, DSPSURF(display, pipe), 0, 0);
+		intel_de_posting_read(display, DSPSURF(display, pipe));
+	}
+}
+
+void intel_display_ilk_init_clock_gating(struct intel_display *display)
+{
+	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+
+	/*
+	 * Required for FBC
+	 * WaFbcDisableDpfcClockGating:ilk
+	 */
+	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
+		       ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
+		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
+
+	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
+		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
+	intel_de_write(display, DISP_ARB_CTL,
+		       intel_de_read(display, DISP_ARB_CTL) |
+		       DISP_FBC_WM_DIS);
+
+	if (display->platform.ironlake && display->platform.mobile) {
+		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
+		intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+		intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
+	}
+
+	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_gen6_init_clock_gating(struct intel_display *display)
+{
+	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
+
+	intel_de_write(display, ILK_DSPCLK_GATE_D, dspclk_gate);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+
+	intel_de_write(display, ILK_DISPLAY_CHICKEN1,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN1) |
+		       ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+	intel_de_write(display, ILK_DISPLAY_CHICKEN2,
+		       intel_de_read(display, ILK_DISPLAY_CHICKEN2) |
+		       ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+	intel_de_write(display, ILK_DSPCLK_GATE_D,
+		       intel_de_read(display, ILK_DSPCLK_GATE_D) |
+		       ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
+		       ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_ivb_init_clock_gating(struct intel_display *display)
+{
+	intel_de_write(display, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
+	intel_de_rmw(display, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+}
+
+void intel_display_g4x_init_clock_gating(struct intel_display *display)
+{
+	u32 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+			  OVRUNIT_CLOCK_GATE_DISABLE |
+			  OVCUNIT_CLOCK_GATE_DISABLE;
+
+	if (display->platform.gm45)
+		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+
+	intel_de_write(display, DSPCLK_GATE_D, dspclk_gate);
+
+	intel_display_disable_trickle_feed(display);
+}
+
+void intel_display_i965gm_init_clock_gating(struct intel_display *display)
+{
+	intel_de_write(display, DSPCLK_GATE_D, 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
index e0300dc8b041..b6dd34ca92dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
+++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
@@ -17,5 +17,11 @@ void intel_display_bdw_clock_gating_disable_fbcq(struct intel_display *display);
 void intel_display_bdw_clock_gating_vblank_in_srd(struct intel_display *display);
 void intel_display_bdw_clock_gating_kvm_notif(struct intel_display *display);
 void intel_display_hsw_init_clock_gating(struct intel_display *display);
+void intel_display_disable_trickle_feed(struct intel_display *display);
+void intel_display_ilk_init_clock_gating(struct intel_display *display);
+void intel_display_gen6_init_clock_gating(struct intel_display *display);
+void intel_display_ivb_init_clock_gating(struct intel_display *display);
+void intel_display_g4x_init_clock_gating(struct intel_display *display);
+void intel_display_i965gm_init_clock_gating(struct intel_display *display);
 
 #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 1cb87ba0ebeb..bc508995ad8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -217,6 +217,34 @@
 # define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6) /* 915-945 */
 # define OVFUNIT_CLOCK_GATE_DISABLE		(1 << 5)
 # define OVBUNIT_CLOCK_GATE_DISABLE		(1 << 4)
+
+#define ILK_DISPLAY_CHICKEN1		_MMIO(0x42000)
+#define   ILK_FBCQ_DIS			REG_BIT(22)
+#define   ILK_PABSTRETCH_DIS		REG_BIT(21)
+#define   ILK_SABSTRETCH_DIS		REG_BIT(20)
+#define   IVB_PRI_STRETCH_MAX_MASK	REG_GENMASK(21, 20)
+#define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
+#define   IVB_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
+#define   IVB_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
+#define   IVB_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
+#define   IVB_SPR_STRETCH_MAX_MASK	REG_GENMASK(19, 18)
+#define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
+#define   IVB_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
+#define   IVB_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
+#define   IVB_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
+
+#define ILK_DISPLAY_CHICKEN2		_MMIO(0x42004)
+/* Required on all Ironlake and Sandybridge according to the B-Spec. */
+#define   ILK_ELPIN_409_SELECT		REG_BIT(25)
+#define   ILK_DPARB_GATE		REG_BIT(22)
+#define   ILK_VSDPFD_FULL		REG_BIT(21)
+
+#define ILK_DSPCLK_GATE_D		_MMIO(0x42020)
+#define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	REG_BIT(28)
+#define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	REG_BIT(9)
+#define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	REG_BIT(8)
+#define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	REG_BIT(7)
+#define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	REG_BIT(5)
 /*
  * This bit must be set on the 830 to prevent hangs when turning off the
  * overlay scaler.
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9d7f1c3a288..64e906380131 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -494,21 +494,6 @@
 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
 
-#define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
-#define   ILK_FBCQ_DIS			REG_BIT(22)
-#define   ILK_PABSTRETCH_DIS		REG_BIT(21)
-#define   ILK_SABSTRETCH_DIS		REG_BIT(20)
-#define   IVB_PRI_STRETCH_MAX_MASK	REG_GENMASK(21, 20)
-#define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
-#define   IVB_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
-#define   IVB_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
-#define   IVB_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
-#define   IVB_SPR_STRETCH_MAX_MASK	REG_GENMASK(19, 18)
-#define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
-#define   IVB_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
-#define   IVB_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
-#define   IVB_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
-
 #define DPLL_TEST	_MMIO(0x606c)
 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
 #define   DPLLB_TEST_SDVO_DIV_2		(1 << 22)
@@ -700,19 +685,6 @@
 #define   DG1_MSTR_IRQ			REG_BIT(31)
 #define   DG1_MSTR_TILE(t)		REG_BIT(t)
 
-#define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
-/* Required on all Ironlake and Sandybridge according to the B-Spec. */
-#define   ILK_ELPIN_409_SELECT	REG_BIT(25)
-#define   ILK_DPARB_GATE	REG_BIT(22)
-#define   ILK_VSDPFD_FULL	REG_BIT(21)
-
-#define ILK_DSPCLK_GATE_D	_MMIO(0x42020)
-#define   ILK_VRHUNIT_CLOCK_GATE_DISABLE	REG_BIT(28)
-#define   ILK_DPFCUNIT_CLOCK_GATE_DISABLE	REG_BIT(9)
-#define   ILK_DPFCRUNIT_CLOCK_GATE_DISABLE	REG_BIT(8)
-#define   ILK_DPFDUNIT_CLOCK_GATE_ENABLE	REG_BIT(7)
-#define   ILK_DPARBUNIT_CLOCK_GATE_ENABLE	REG_BIT(5)
-
 #define IVB_CHICKEN3		_MMIO(0x4200c)
 #define   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE	REG_BIT(5)
 #define   CHICKEN3_DGMG_DONE_FIX_DISABLE	REG_BIT(2)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 10aa00e003be..c27b6f9266b1 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -30,11 +30,8 @@
 #include <drm/intel/intel_gmd_misc_regs.h>
 #include <drm/intel/mchbar_regs.h>
 
-#include "display/i9xx_plane_regs.h"
-#include "display/intel_display.h"
 #include "display/intel_display_clock_gating.h"
 #include "display/intel_display_core.h"
-#include "display/intel_display_regs.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -68,74 +65,15 @@ static void glk_init_clock_gating(struct drm_i915_private *i915)
 	intel_display_glk_init_clock_gating(i915->display);
 }
 
-static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
-{
-	struct intel_display *display = dev_priv->display;
-	enum pipe pipe;
-
-	for_each_pipe(display, pipe) {
-		intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(display, pipe),
-				 0, DISP_TRICKLE_FEED_DISABLE);
-
-		intel_uncore_rmw(&dev_priv->uncore, DSPSURF(display, pipe),
-				 0, 0);
-		intel_uncore_posting_read(&dev_priv->uncore,
-					  DSPSURF(display, pipe));
-	}
-}
-
 static void ilk_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
-
-	/*
-	 * Required for FBC
-	 * WaFbcDisableDpfcClockGating:ilk
-	 */
-	dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
-		   ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
-		   ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
-
 	intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
 			   MARIUNIT_CLOCK_GATE_DISABLE |
 			   SVSMUNIT_CLOCK_GATE_DISABLE);
 	intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
 			   VFMUNIT_CLOCK_GATE_DISABLE);
 
-	/*
-	 * According to the spec the following bits should be set in
-	 * order to enable memory self-refresh
-	 * The bit 22/21 of 0x42004
-	 * The bit 5 of 0x42020
-	 * The bit 15 of 0x45000
-	 */
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
-			   (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
-			    ILK_DPARB_GATE | ILK_VSDPFD_FULL));
-	dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
-	intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
-			   (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
-			    DISP_FBC_WM_DIS));
-
-	/*
-	 * Based on the document from hardware guys the following bits
-	 * should be set unconditionally in order to enable FBC.
-	 * The bit 22 of 0x42000
-	 * The bit 22 of 0x42004
-	 * The bit 7,8,9 of 0x42020.
-	 */
-	if (IS_IRONLAKE_M(i915)) {
-		/* WaFbcAsynchFlipDisableFbcQueue:ilk */
-		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
-		intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
-	}
-
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
-
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
-
-	g4x_disable_trickle_feed(i915);
-
+	intel_display_ilk_init_clock_gating(i915->display);
 	intel_pch_init_clock_gating(i915->display);
 }
 
@@ -152,11 +90,7 @@ static void gen6_check_mch_setup(struct drm_i915_private *i915)
 
 static void gen6_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
-
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
-
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+	intel_display_gen6_init_clock_gating(i915->display);
 
 	intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
 			   intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
@@ -191,19 +125,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *i915)
 	 *
 	 * WaFbcAsynchFlipDisableFbcQueue:snb
 	 */
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
-			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
-			   ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
-	intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
-			   intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
-			   ILK_DPARB_GATE | ILK_VSDPFD_FULL);
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
-			   intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
-			   ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
-			   ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
-
-	g4x_disable_trickle_feed(i915);
-
 	intel_pch_init_clock_gating(i915->display);
 
 	gen6_check_mch_setup(i915);
@@ -335,10 +256,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 {
 	struct intel_display *display = i915->display;
 
-	intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
-
-	/* WaFbcAsynchFlipDisableFbcQueue:ivb */
-	intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+	intel_display_ivb_init_clock_gating(display);
 
 	/* WaDisableBackToBackFlipFix:ivb */
 	intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
@@ -367,7 +285,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
 			 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
 
-	g4x_disable_trickle_feed(i915);
+	intel_display_disable_trickle_feed(display);
 
 	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
 			 GEN6_MBC_SNPCR_MED);
@@ -440,21 +358,12 @@ static void chv_init_clock_gating(struct drm_i915_private *i915)
 
 static void g4x_init_clock_gating(struct drm_i915_private *i915)
 {
-	u32 dspclk_gate;
-
 	intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
 	intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
 			   GS_UNIT_CLOCK_GATE_DISABLE |
 			   CL_UNIT_CLOCK_GATE_DISABLE);
 	intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
-	dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
-		OVRUNIT_CLOCK_GATE_DISABLE |
-		OVCUNIT_CLOCK_GATE_DISABLE;
-	if (IS_GM45(i915))
-		dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
-	intel_uncore_write(&i915->uncore, DSPCLK_GATE_D, dspclk_gate);
-
-	g4x_disable_trickle_feed(i915);
+	intel_display_g4x_init_clock_gating(i915->display);
 }
 
 static void i965gm_init_clock_gating(struct drm_i915_private *i915)
@@ -463,7 +372,7 @@ static void i965gm_init_clock_gating(struct drm_i915_private *i915)
 
 	intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
 	intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
-	intel_uncore_write(uncore, DSPCLK_GATE_D, 0);
+	intel_display_i965gm_init_clock_gating(i915->display);
 	intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
 	intel_uncore_write16(uncore, DEUC, 0);
 	intel_uncore_write(uncore,
-- 
2.53.0

[PATCH v4 8/8] drm/i915: remove HAS_PCH_NOP() dependency from clock gating

[Luca Coelho]

intel_pch_init_clock_gating() already handles unsupported PCH types,
including PCH_NOP, by doing nothing.

Drop the explicit HAS_PCH_NOP() check from the IVB clock gating
path and always call the display helper directly. This removes one
more direct dependency on display-side PCH macros from
intel_clock_gating.c.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---
 drivers/gpu/drm/i915/intel_clock_gating.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index c27b6f9266b1..86bdeb20f427 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -31,7 +31,7 @@
 #include <drm/intel/mchbar_regs.h>
 
 #include "display/intel_display_clock_gating.h"
-#include "display/intel_display_core.h"
+#include "display/intel_pch.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_mcr.h"
@@ -290,8 +290,7 @@ static void ivb_init_clock_gating(struct drm_i915_private *i915)
 	intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
 			 GEN6_MBC_SNPCR_MED);
 
-	if (!HAS_PCH_NOP(display))
-		intel_pch_init_clock_gating(display);
+	intel_pch_init_clock_gating(display);
 
 	gen6_check_mch_setup(i915);
 }
-- 
2.53.0

✗ CI.checkpatch: warning for drm/i915: move more display dependencies from i915 (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev4)
URL   : https://patchwork.freedesktop.org/series/163785/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 4b4ff70aa0bd74c3e597d557da0c1aaf0a69b30c
Author: Luca Coelho <luciano.coelho@intel.com>
Date:   Mon Apr 20 23:22:16 2026 +0300

    drm/i915: remove HAS_PCH_NOP() dependency from clock gating
    
    intel_pch_init_clock_gating() already handles unsupported PCH types,
    including PCH_NOP, by doing nothing.
    
    Drop the explicit HAS_PCH_NOP() check from the IVB clock gating
    path and always call the display helper directly. This removes one
    more direct dependency on display-side PCH macros from
    intel_clock_gating.c.
    
    Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
+ /mt/dim checkpatch 898b5aa235c5b269d6c745fd84270b296aa75469 drm-intel
bf7138d0fce3 drm/i915: move SKL clock gating init to display
-:27: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 61 lines checked
dcd75229d892 drm/i915: move KBL clock gating init to display
1a3e4767b692 drm/i915/display: move CFL clock gating init to display
c28084109f26 drm/i915/display: move BXT clock gating init to display
f282eeaeeef7 drm/i915/display: move GLK clock gating init to display
73f19fbf6aaf drm/i915/display: move HSW and BDW clock gating init to display
47b34a8afd6e drm/i915/display: move pre-HSW clock gating init to display
4b4ff70aa0bd drm/i915: remove HAS_PCH_NOP() dependency from clock gating

✓ CI.KUnit: success for drm/i915: move more display dependencies from i915 (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev4)
URL   : https://patchwork.freedesktop.org/series/163785/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[02:39:11] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:39:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:39:46] Starting KUnit Kernel (1/1)...
[02:39:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:39:46] ================== guc_buf (11 subtests) ===================
[02:39:46] [PASSED] test_smallest
[02:39:46] [PASSED] test_largest
[02:39:46] [PASSED] test_granular
[02:39:46] [PASSED] test_unique
[02:39:46] [PASSED] test_overlap
[02:39:46] [PASSED] test_reusable
[02:39:46] [PASSED] test_too_big
[02:39:46] [PASSED] test_flush
[02:39:46] [PASSED] test_lookup
[02:39:46] [PASSED] test_data
[02:39:46] [PASSED] test_class
[02:39:46] ===================== [PASSED] guc_buf =====================
[02:39:46] =================== guc_dbm (7 subtests) ===================
[02:39:46] [PASSED] test_empty
[02:39:46] [PASSED] test_default
[02:39:46] ======================== test_size  ========================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] ==================== [PASSED] test_size ====================
[02:39:46] ======================= test_reuse  ========================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] =================== [PASSED] test_reuse ====================
[02:39:46] =================== test_range_overlap  ====================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] =============== [PASSED] test_range_overlap ================
[02:39:46] =================== test_range_compact  ====================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] =============== [PASSED] test_range_compact ================
[02:39:46] ==================== test_range_spare  =====================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] ================ [PASSED] test_range_spare =================
[02:39:46] ===================== [PASSED] guc_dbm =====================
[02:39:46] =================== guc_idm (6 subtests) ===================
[02:39:46] [PASSED] bad_init
[02:39:46] [PASSED] no_init
[02:39:46] [PASSED] init_fini
[02:39:46] [PASSED] check_used
[02:39:46] [PASSED] check_quota
[02:39:46] [PASSED] check_all
[02:39:46] ===================== [PASSED] guc_idm =====================
[02:39:46] ================== no_relay (3 subtests) ===================
[02:39:46] [PASSED] xe_drops_guc2pf_if_not_ready
[02:39:46] [PASSED] xe_drops_guc2vf_if_not_ready
[02:39:46] [PASSED] xe_rejects_send_if_not_ready
[02:39:46] ==================== [PASSED] no_relay =====================
[02:39:46] ================== pf_relay (14 subtests) ==================
[02:39:46] [PASSED] pf_rejects_guc2pf_too_short
[02:39:46] [PASSED] pf_rejects_guc2pf_too_long
[02:39:46] [PASSED] pf_rejects_guc2pf_no_payload
[02:39:46] [PASSED] pf_fails_no_payload
[02:39:46] [PASSED] pf_fails_bad_origin
[02:39:46] [PASSED] pf_fails_bad_type
[02:39:46] [PASSED] pf_txn_reports_error
[02:39:46] [PASSED] pf_txn_sends_pf2guc
[02:39:46] [PASSED] pf_sends_pf2guc
[02:39:46] [SKIPPED] pf_loopback_nop
[02:39:46] [SKIPPED] pf_loopback_echo
[02:39:46] [SKIPPED] pf_loopback_fail
[02:39:46] [SKIPPED] pf_loopback_busy
[02:39:46] [SKIPPED] pf_loopback_retry
[02:39:46] ==================== [PASSED] pf_relay =====================
[02:39:46] ================== vf_relay (3 subtests) ===================
[02:39:46] [PASSED] vf_rejects_guc2vf_too_short
[02:39:46] [PASSED] vf_rejects_guc2vf_too_long
[02:39:46] [PASSED] vf_rejects_guc2vf_no_payload
[02:39:46] ==================== [PASSED] vf_relay =====================
[02:39:46] ================ pf_gt_config (9 subtests) =================
[02:39:46] [PASSED] fair_contexts_1vf
[02:39:46] [PASSED] fair_doorbells_1vf
[02:39:46] [PASSED] fair_ggtt_1vf
[02:39:46] ====================== fair_vram_1vf  ======================
[02:39:46] [PASSED] 3.50 GiB
[02:39:46] [PASSED] 11.5 GiB
[02:39:46] [PASSED] 15.5 GiB
[02:39:46] [PASSED] 31.5 GiB
[02:39:46] [PASSED] 63.5 GiB
[02:39:46] [PASSED] 1.91 GiB
[02:39:46] ================== [PASSED] fair_vram_1vf ==================
[02:39:46] ================ fair_vram_1vf_admin_only  =================
[02:39:46] [PASSED] 3.50 GiB
[02:39:46] [PASSED] 11.5 GiB
[02:39:46] [PASSED] 15.5 GiB
[02:39:46] [PASSED] 31.5 GiB
[02:39:46] [PASSED] 63.5 GiB
[02:39:46] [PASSED] 1.91 GiB
[02:39:46] ============ [PASSED] fair_vram_1vf_admin_only =============
[02:39:46] ====================== fair_contexts  ======================
[02:39:46] [PASSED] 1 VF
[02:39:46] [PASSED] 2 VFs
[02:39:46] [PASSED] 3 VFs
[02:39:46] [PASSED] 4 VFs
[02:39:46] [PASSED] 5 VFs
[02:39:46] [PASSED] 6 VFs
[02:39:46] [PASSED] 7 VFs
[02:39:46] [PASSED] 8 VFs
[02:39:46] [PASSED] 9 VFs
[02:39:46] [PASSED] 10 VFs
[02:39:46] [PASSED] 11 VFs
[02:39:46] [PASSED] 12 VFs
[02:39:46] [PASSED] 13 VFs
[02:39:46] [PASSED] 14 VFs
[02:39:46] [PASSED] 15 VFs
[02:39:46] [PASSED] 16 VFs
[02:39:46] [PASSED] 17 VFs
[02:39:46] [PASSED] 18 VFs
[02:39:46] [PASSED] 19 VFs
[02:39:46] [PASSED] 20 VFs
[02:39:46] [PASSED] 21 VFs
[02:39:46] [PASSED] 22 VFs
[02:39:46] [PASSED] 23 VFs
[02:39:46] [PASSED] 24 VFs
[02:39:46] [PASSED] 25 VFs
[02:39:46] [PASSED] 26 VFs
[02:39:46] [PASSED] 27 VFs
[02:39:47] [PASSED] 28 VFs
[02:39:47] [PASSED] 29 VFs
[02:39:47] [PASSED] 30 VFs
[02:39:47] [PASSED] 31 VFs
[02:39:47] [PASSED] 32 VFs
[02:39:47] [PASSED] 33 VFs
[02:39:47] [PASSED] 34 VFs
[02:39:47] [PASSED] 35 VFs
[02:39:47] [PASSED] 36 VFs
[02:39:47] [PASSED] 37 VFs
[02:39:47] [PASSED] 38 VFs
[02:39:47] [PASSED] 39 VFs
[02:39:47] [PASSED] 40 VFs
[02:39:47] [PASSED] 41 VFs
[02:39:47] [PASSED] 42 VFs
[02:39:47] [PASSED] 43 VFs
[02:39:47] [PASSED] 44 VFs
[02:39:47] [PASSED] 45 VFs
[02:39:47] [PASSED] 46 VFs
[02:39:47] [PASSED] 47 VFs
[02:39:47] [PASSED] 48 VFs
[02:39:47] [PASSED] 49 VFs
[02:39:47] [PASSED] 50 VFs
[02:39:47] [PASSED] 51 VFs
[02:39:47] [PASSED] 52 VFs
[02:39:47] [PASSED] 53 VFs
[02:39:47] [PASSED] 54 VFs
[02:39:47] [PASSED] 55 VFs
[02:39:47] [PASSED] 56 VFs
[02:39:47] [PASSED] 57 VFs
[02:39:47] [PASSED] 58 VFs
[02:39:47] [PASSED] 59 VFs
[02:39:47] [PASSED] 60 VFs
[02:39:47] [PASSED] 61 VFs
[02:39:47] [PASSED] 62 VFs
[02:39:47] [PASSED] 63 VFs
[02:39:47] ================== [PASSED] fair_contexts ==================
[02:39:47] ===================== fair_doorbells  ======================
[02:39:47] [PASSED] 1 VF
[02:39:47] [PASSED] 2 VFs
[02:39:47] [PASSED] 3 VFs
[02:39:47] [PASSED] 4 VFs
[02:39:47] [PASSED] 5 VFs
[02:39:47] [PASSED] 6 VFs
[02:39:47] [PASSED] 7 VFs
[02:39:47] [PASSED] 8 VFs
[02:39:47] [PASSED] 9 VFs
[02:39:47] [PASSED] 10 VFs
[02:39:47] [PASSED] 11 VFs
[02:39:47] [PASSED] 12 VFs
[02:39:47] [PASSED] 13 VFs
[02:39:47] [PASSED] 14 VFs
[02:39:47] [PASSED] 15 VFs
[02:39:47] [PASSED] 16 VFs
[02:39:47] [PASSED] 17 VFs
[02:39:47] [PASSED] 18 VFs
[02:39:47] [PASSED] 19 VFs
[02:39:47] [PASSED] 20 VFs
[02:39:47] [PASSED] 21 VFs
[02:39:47] [PASSED] 22 VFs
[02:39:47] [PASSED] 23 VFs
[02:39:47] [PASSED] 24 VFs
[02:39:47] [PASSED] 25 VFs
[02:39:47] [PASSED] 26 VFs
[02:39:47] [PASSED] 27 VFs
[02:39:47] [PASSED] 28 VFs
[02:39:47] [PASSED] 29 VFs
[02:39:47] [PASSED] 30 VFs
[02:39:47] [PASSED] 31 VFs
[02:39:47] [PASSED] 32 VFs
[02:39:47] [PASSED] 33 VFs
[02:39:47] [PASSED] 34 VFs
[02:39:47] [PASSED] 35 VFs
[02:39:47] [PASSED] 36 VFs
[02:39:47] [PASSED] 37 VFs
[02:39:47] [PASSED] 38 VFs
[02:39:47] [PASSED] 39 VFs
[02:39:47] [PASSED] 40 VFs
[02:39:47] [PASSED] 41 VFs
[02:39:47] [PASSED] 42 VFs
[02:39:47] [PASSED] 43 VFs
[02:39:47] [PASSED] 44 VFs
[02:39:47] [PASSED] 45 VFs
[02:39:47] [PASSED] 46 VFs
[02:39:47] [PASSED] 47 VFs
[02:39:47] [PASSED] 48 VFs
[02:39:47] [PASSED] 49 VFs
[02:39:47] [PASSED] 50 VFs
[02:39:47] [PASSED] 51 VFs
[02:39:47] [PASSED] 52 VFs
[02:39:47] [PASSED] 53 VFs
[02:39:47] [PASSED] 54 VFs
[02:39:47] [PASSED] 55 VFs
[02:39:47] [PASSED] 56 VFs
[02:39:47] [PASSED] 57 VFs
[02:39:47] [PASSED] 58 VFs
[02:39:47] [PASSED] 59 VFs
[02:39:47] [PASSED] 60 VFs
[02:39:47] [PASSED] 61 VFs
[02:39:47] [PASSED] 62 VFs
[02:39:47] [PASSED] 63 VFs
[02:39:47] ================= [PASSED] fair_doorbells ==================
[02:39:47] ======================== fair_ggtt  ========================
[02:39:47] [PASSED] 1 VF
[02:39:47] [PASSED] 2 VFs
[02:39:47] [PASSED] 3 VFs
[02:39:47] [PASSED] 4 VFs
[02:39:47] [PASSED] 5 VFs
[02:39:47] [PASSED] 6 VFs
[02:39:47] [PASSED] 7 VFs
[02:39:47] [PASSED] 8 VFs
[02:39:47] [PASSED] 9 VFs
[02:39:47] [PASSED] 10 VFs
[02:39:47] [PASSED] 11 VFs
[02:39:47] [PASSED] 12 VFs
[02:39:47] [PASSED] 13 VFs
[02:39:47] [PASSED] 14 VFs
[02:39:47] [PASSED] 15 VFs
[02:39:47] [PASSED] 16 VFs
[02:39:47] [PASSED] 17 VFs
[02:39:47] [PASSED] 18 VFs
[02:39:47] [PASSED] 19 VFs
[02:39:47] [PASSED] 20 VFs
[02:39:47] [PASSED] 21 VFs
[02:39:47] [PASSED] 22 VFs
[02:39:47] [PASSED] 23 VFs
[02:39:47] [PASSED] 24 VFs
[02:39:47] [PASSED] 25 VFs
[02:39:47] [PASSED] 26 VFs
[02:39:47] [PASSED] 27 VFs
[02:39:47] [PASSED] 28 VFs
[02:39:47] [PASSED] 29 VFs
[02:39:47] [PASSED] 30 VFs
[02:39:47] [PASSED] 31 VFs
[02:39:47] [PASSED] 32 VFs
[02:39:47] [PASSED] 33 VFs
[02:39:47] [PASSED] 34 VFs
[02:39:47] [PASSED] 35 VFs
[02:39:47] [PASSED] 36 VFs
[02:39:47] [PASSED] 37 VFs
[02:39:47] [PASSED] 38 VFs
[02:39:47] [PASSED] 39 VFs
[02:39:47] [PASSED] 40 VFs
[02:39:47] [PASSED] 41 VFs
[02:39:47] [PASSED] 42 VFs
[02:39:47] [PASSED] 43 VFs
[02:39:47] [PASSED] 44 VFs
[02:39:47] [PASSED] 45 VFs
[02:39:47] [PASSED] 46 VFs
[02:39:47] [PASSED] 47 VFs
[02:39:47] [PASSED] 48 VFs
[02:39:47] [PASSED] 49 VFs
[02:39:47] [PASSED] 50 VFs
[02:39:47] [PASSED] 51 VFs
[02:39:47] [PASSED] 52 VFs
[02:39:47] [PASSED] 53 VFs
[02:39:47] [PASSED] 54 VFs
[02:39:47] [PASSED] 55 VFs
[02:39:47] [PASSED] 56 VFs
[02:39:47] [PASSED] 57 VFs
[02:39:47] [PASSED] 58 VFs
[02:39:47] [PASSED] 59 VFs
[02:39:47] [PASSED] 60 VFs
[02:39:47] [PASSED] 61 VFs
[02:39:47] [PASSED] 62 VFs
[02:39:47] [PASSED] 63 VFs
[02:39:47] ==================== [PASSED] fair_ggtt ====================
[02:39:47] ======================== fair_vram  ========================
[02:39:47] [PASSED] 1 VF
[02:39:47] [PASSED] 2 VFs
[02:39:47] [PASSED] 3 VFs
[02:39:47] [PASSED] 4 VFs
[02:39:47] [PASSED] 5 VFs
[02:39:47] [PASSED] 6 VFs
[02:39:47] [PASSED] 7 VFs
[02:39:47] [PASSED] 8 VFs
[02:39:47] [PASSED] 9 VFs
[02:39:47] [PASSED] 10 VFs
[02:39:47] [PASSED] 11 VFs
[02:39:47] [PASSED] 12 VFs
[02:39:47] [PASSED] 13 VFs
[02:39:47] [PASSED] 14 VFs
[02:39:47] [PASSED] 15 VFs
[02:39:47] [PASSED] 16 VFs
[02:39:47] [PASSED] 17 VFs
[02:39:47] [PASSED] 18 VFs
[02:39:47] [PASSED] 19 VFs
[02:39:47] [PASSED] 20 VFs
[02:39:47] [PASSED] 21 VFs
[02:39:47] [PASSED] 22 VFs
[02:39:47] [PASSED] 23 VFs
[02:39:47] [PASSED] 24 VFs
[02:39:47] [PASSED] 25 VFs
[02:39:47] [PASSED] 26 VFs
[02:39:47] [PASSED] 27 VFs
[02:39:47] [PASSED] 28 VFs
[02:39:47] [PASSED] 29 VFs
[02:39:47] [PASSED] 30 VFs
[02:39:47] [PASSED] 31 VFs
[02:39:47] [PASSED] 32 VFs
[02:39:47] [PASSED] 33 VFs
[02:39:47] [PASSED] 34 VFs
[02:39:47] [PASSED] 35 VFs
[02:39:47] [PASSED] 36 VFs
[02:39:47] [PASSED] 37 VFs
[02:39:47] [PASSED] 38 VFs
[02:39:47] [PASSED] 39 VFs
[02:39:47] [PASSED] 40 VFs
[02:39:47] [PASSED] 41 VFs
[02:39:47] [PASSED] 42 VFs
[02:39:47] [PASSED] 43 VFs
[02:39:47] [PASSED] 44 VFs
[02:39:47] [PASSED] 45 VFs
[02:39:47] [PASSED] 46 VFs
[02:39:47] [PASSED] 47 VFs
[02:39:47] [PASSED] 48 VFs
[02:39:47] [PASSED] 49 VFs
[02:39:47] [PASSED] 50 VFs
[02:39:47] [PASSED] 51 VFs
[02:39:47] [PASSED] 52 VFs
[02:39:47] [PASSED] 53 VFs
[02:39:47] [PASSED] 54 VFs
[02:39:47] [PASSED] 55 VFs
[02:39:47] [PASSED] 56 VFs
[02:39:47] [PASSED] 57 VFs
[02:39:47] [PASSED] 58 VFs
[02:39:47] [PASSED] 59 VFs
[02:39:47] [PASSED] 60 VFs
[02:39:47] [PASSED] 61 VFs
[02:39:47] [PASSED] 62 VFs
[02:39:47] [PASSED] 63 VFs
[02:39:47] ==================== [PASSED] fair_vram ====================
[02:39:47] ================== [PASSED] pf_gt_config ===================
[02:39:47] ===================== lmtt (1 subtest) =====================
[02:39:47] ======================== test_ops  =========================
[02:39:47] [PASSED] 2-level
[02:39:47] [PASSED] multi-level
[02:39:47] ==================== [PASSED] test_ops =====================
[02:39:47] ====================== [PASSED] lmtt =======================
[02:39:47] ================= pf_service (11 subtests) =================
[02:39:47] [PASSED] pf_negotiate_any
[02:39:47] [PASSED] pf_negotiate_base_match
[02:39:47] [PASSED] pf_negotiate_base_newer
[02:39:47] [PASSED] pf_negotiate_base_next
[02:39:47] [SKIPPED] pf_negotiate_base_older
[02:39:47] [PASSED] pf_negotiate_base_prev
[02:39:47] [PASSED] pf_negotiate_latest_match
[02:39:47] [PASSED] pf_negotiate_latest_newer
[02:39:47] [PASSED] pf_negotiate_latest_next
[02:39:47] [SKIPPED] pf_negotiate_latest_older
[02:39:47] [SKIPPED] pf_negotiate_latest_prev
[02:39:47] =================== [PASSED] pf_service ====================
[02:39:47] ================= xe_guc_g2g (2 subtests) ==================
[02:39:47] ============== xe_live_guc_g2g_kunit_default  ==============
[02:39:47] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[02:39:47] ============== xe_live_guc_g2g_kunit_allmem  ===============
[02:39:47] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[02:39:47] =================== [SKIPPED] xe_guc_g2g ===================
[02:39:47] =================== xe_mocs (2 subtests) ===================
[02:39:47] ================ xe_live_mocs_kernel_kunit  ================
[02:39:47] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[02:39:47] ================ xe_live_mocs_reset_kunit  =================
[02:39:47] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[02:39:47] ==================== [SKIPPED] xe_mocs =====================
[02:39:47] ================= xe_migrate (2 subtests) ==================
[02:39:47] ================= xe_migrate_sanity_kunit  =================
[02:39:47] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[02:39:47] ================== xe_validate_ccs_kunit  ==================
[02:39:47] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[02:39:47] =================== [SKIPPED] xe_migrate ===================
[02:39:47] ================== xe_dma_buf (1 subtest) ==================
[02:39:47] ==================== xe_dma_buf_kunit  =====================
[02:39:47] ================ [SKIPPED] xe_dma_buf_kunit ================
[02:39:47] =================== [SKIPPED] xe_dma_buf ===================
[02:39:47] ================= xe_bo_shrink (1 subtest) =================
[02:39:47] =================== xe_bo_shrink_kunit  ====================
[02:39:47] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[02:39:47] ================== [SKIPPED] xe_bo_shrink ==================
[02:39:47] ==================== xe_bo (2 subtests) ====================
[02:39:47] ================== xe_ccs_migrate_kunit  ===================
[02:39:47] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[02:39:47] ==================== xe_bo_evict_kunit  ====================
[02:39:47] =============== [SKIPPED] xe_bo_evict_kunit ================
[02:39:47] ===================== [SKIPPED] xe_bo ======================
[02:39:47] ==================== args (13 subtests) ====================
[02:39:47] [PASSED] count_args_test
[02:39:47] [PASSED] call_args_example
[02:39:47] [PASSED] call_args_test
[02:39:47] [PASSED] drop_first_arg_example
[02:39:47] [PASSED] drop_first_arg_test
[02:39:47] [PASSED] first_arg_example
[02:39:47] [PASSED] first_arg_test
[02:39:47] [PASSED] last_arg_example
[02:39:47] [PASSED] last_arg_test
[02:39:47] [PASSED] pick_arg_example
[02:39:47] [PASSED] if_args_example
[02:39:47] [PASSED] if_args_test
[02:39:47] [PASSED] sep_comma_example
[02:39:47] ====================== [PASSED] args =======================
[02:39:47] =================== xe_pci (3 subtests) ====================
[02:39:47] ==================== check_graphics_ip  ====================
[02:39:47] [PASSED] 12.00 Xe_LP
[02:39:47] [PASSED] 12.10 Xe_LP+
[02:39:47] [PASSED] 12.55 Xe_HPG
[02:39:47] [PASSED] 12.60 Xe_HPC
[02:39:47] [PASSED] 12.70 Xe_LPG
[02:39:47] [PASSED] 12.71 Xe_LPG
[02:39:47] [PASSED] 12.74 Xe_LPG+
[02:39:47] [PASSED] 20.01 Xe2_HPG
[02:39:47] [PASSED] 20.02 Xe2_HPG
[02:39:47] [PASSED] 20.04 Xe2_LPG
[02:39:47] [PASSED] 30.00 Xe3_LPG
[02:39:47] [PASSED] 30.01 Xe3_LPG
[02:39:47] [PASSED] 30.03 Xe3_LPG
[02:39:47] [PASSED] 30.04 Xe3_LPG
[02:39:47] [PASSED] 30.05 Xe3_LPG
[02:39:47] [PASSED] 35.10 Xe3p_LPG
[02:39:47] [PASSED] 35.11 Xe3p_XPC
[02:39:47] ================ [PASSED] check_graphics_ip ================
[02:39:47] ===================== check_media_ip  ======================
[02:39:47] [PASSED] 12.00 Xe_M
[02:39:47] [PASSED] 12.55 Xe_HPM
[02:39:47] [PASSED] 13.00 Xe_LPM+
[02:39:47] [PASSED] 13.01 Xe2_HPM
[02:39:47] [PASSED] 20.00 Xe2_LPM
[02:39:47] [PASSED] 30.00 Xe3_LPM
[02:39:47] [PASSED] 30.02 Xe3_LPM
[02:39:47] [PASSED] 35.00 Xe3p_LPM
[02:39:47] [PASSED] 35.03 Xe3p_HPM
[02:39:47] ================= [PASSED] check_media_ip ==================
[02:39:47] =================== check_platform_desc  ===================
[02:39:47] [PASSED] 0x9A60 (TIGERLAKE)
[02:39:47] [PASSED] 0x9A68 (TIGERLAKE)
[02:39:47] [PASSED] 0x9A70 (TIGERLAKE)
[02:39:47] [PASSED] 0x9A40 (TIGERLAKE)
[02:39:47] [PASSED] 0x9A49 (TIGERLAKE)
[02:39:47] [PASSED] 0x9A59 (TIGERLAKE)
[02:39:47] [PASSED] 0x9A78 (TIGERLAKE)
[02:39:47] [PASSED] 0x9AC0 (TIGERLAKE)
[02:39:47] [PASSED] 0x9AC9 (TIGERLAKE)
[02:39:47] [PASSED] 0x9AD9 (TIGERLAKE)
[02:39:47] [PASSED] 0x9AF8 (TIGERLAKE)
[02:39:47] [PASSED] 0x4C80 (ROCKETLAKE)
[02:39:47] [PASSED] 0x4C8A (ROCKETLAKE)
[02:39:47] [PASSED] 0x4C8B (ROCKETLAKE)
[02:39:47] [PASSED] 0x4C8C (ROCKETLAKE)
[02:39:47] [PASSED] 0x4C90 (ROCKETLAKE)
[02:39:47] [PASSED] 0x4C9A (ROCKETLAKE)
[02:39:47] [PASSED] 0x4680 (ALDERLAKE_S)
[02:39:47] [PASSED] 0x4682 (ALDERLAKE_S)
[02:39:47] [PASSED] 0x4688 (ALDERLAKE_S)
[02:39:47] [PASSED] 0x468A (ALDERLAKE_S)
[02:39:47] [PASSED] 0x468B (ALDERLAKE_S)
[02:39:47] [PASSED] 0x4690 (ALDERLAKE_S)
[02:39:47] [PASSED] 0x4692 (ALDERLAKE_S)
[02:39:47] [PASSED] 0x4693 (ALDERLAKE_S)
[02:39:47] [PASSED] 0x46A0 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46A1 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46A2 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46A3 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46A6 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46A8 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46AA (ALDERLAKE_P)
[02:39:47] [PASSED] 0x462A (ALDERLAKE_P)
[02:39:47] [PASSED] 0x4626 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x4628 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46B0 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46B1 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46B2 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46B3 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46C0 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46C1 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46C2 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46C3 (ALDERLAKE_P)
[02:39:47] [PASSED] 0x46D0 (ALDERLAKE_N)
[02:39:47] [PASSED] 0x46D1 (ALDERLAKE_N)
[02:39:47] [PASSED] 0x46D2 (ALDERLAKE_N)
[02:39:47] [PASSED] 0x46D3 (ALDERLAKE_N)
[02:39:47] [PASSED] 0x46D4 (ALDERLAKE_N)
[02:39:47] [PASSED] 0xA721 (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7A1 (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7A9 (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7AC (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7AD (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA720 (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7A0 (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7A8 (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7AA (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA7AB (ALDERLAKE_P)
[02:39:47] [PASSED] 0xA780 (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA781 (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA782 (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA783 (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA788 (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA789 (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA78A (ALDERLAKE_S)
[02:39:47] [PASSED] 0xA78B (ALDERLAKE_S)
[02:39:47] [PASSED] 0x4905 (DG1)
[02:39:47] [PASSED] 0x4906 (DG1)
[02:39:47] [PASSED] 0x4907 (DG1)
[02:39:47] [PASSED] 0x4908 (DG1)
[02:39:47] [PASSED] 0x4909 (DG1)
[02:39:47] [PASSED] 0x56C0 (DG2)
[02:39:47] [PASSED] 0x56C2 (DG2)
[02:39:47] [PASSED] 0x56C1 (DG2)
[02:39:47] [PASSED] 0x7D51 (METEORLAKE)
[02:39:47] [PASSED] 0x7DD1 (METEORLAKE)
[02:39:47] [PASSED] 0x7D41 (METEORLAKE)
[02:39:47] [PASSED] 0x7D67 (METEORLAKE)
[02:39:47] [PASSED] 0xB640 (METEORLAKE)
[02:39:47] [PASSED] 0x56A0 (DG2)
[02:39:47] [PASSED] 0x56A1 (DG2)
[02:39:47] [PASSED] 0x56A2 (DG2)
[02:39:47] [PASSED] 0x56BE (DG2)
[02:39:47] [PASSED] 0x56BF (DG2)
[02:39:47] [PASSED] 0x5690 (DG2)
[02:39:47] [PASSED] 0x5691 (DG2)
[02:39:47] [PASSED] 0x5692 (DG2)
[02:39:47] [PASSED] 0x56A5 (DG2)
[02:39:47] [PASSED] 0x56A6 (DG2)
[02:39:47] [PASSED] 0x56B0 (DG2)
[02:39:47] [PASSED] 0x56B1 (DG2)
[02:39:47] [PASSED] 0x56BA (DG2)
[02:39:47] [PASSED] 0x56BB (DG2)
[02:39:47] [PASSED] 0x56BC (DG2)
[02:39:47] [PASSED] 0x56BD (DG2)
[02:39:47] [PASSED] 0x5693 (DG2)
[02:39:47] [PASSED] 0x5694 (DG2)
[02:39:47] [PASSED] 0x5695 (DG2)
[02:39:47] [PASSED] 0x56A3 (DG2)
[02:39:47] [PASSED] 0x56A4 (DG2)
[02:39:47] [PASSED] 0x56B2 (DG2)
[02:39:47] [PASSED] 0x56B3 (DG2)
[02:39:47] [PASSED] 0x5696 (DG2)
[02:39:47] [PASSED] 0x5697 (DG2)
[02:39:47] [PASSED] 0xB69 (PVC)
[02:39:47] [PASSED] 0xB6E (PVC)
[02:39:47] [PASSED] 0xBD4 (PVC)
[02:39:47] [PASSED] 0xBD5 (PVC)
[02:39:47] [PASSED] 0xBD6 (PVC)
[02:39:47] [PASSED] 0xBD7 (PVC)
[02:39:47] [PASSED] 0xBD8 (PVC)
[02:39:47] [PASSED] 0xBD9 (PVC)
[02:39:47] [PASSED] 0xBDA (PVC)
[02:39:47] [PASSED] 0xBDB (PVC)
[02:39:47] [PASSED] 0xBE0 (PVC)
[02:39:47] [PASSED] 0xBE1 (PVC)
[02:39:47] [PASSED] 0xBE5 (PVC)
[02:39:47] [PASSED] 0x7D40 (METEORLAKE)
[02:39:47] [PASSED] 0x7D45 (METEORLAKE)
[02:39:47] [PASSED] 0x7D55 (METEORLAKE)
[02:39:47] [PASSED] 0x7D60 (METEORLAKE)
[02:39:47] [PASSED] 0x7DD5 (METEORLAKE)
[02:39:47] [PASSED] 0x6420 (LUNARLAKE)
[02:39:47] [PASSED] 0x64A0 (LUNARLAKE)
[02:39:47] [PASSED] 0x64B0 (LUNARLAKE)
[02:39:47] [PASSED] 0xE202 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE209 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE20B (BATTLEMAGE)
[02:39:47] [PASSED] 0xE20C (BATTLEMAGE)
[02:39:47] [PASSED] 0xE20D (BATTLEMAGE)
[02:39:47] [PASSED] 0xE210 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE211 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE212 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE216 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE220 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE221 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE222 (BATTLEMAGE)
[02:39:47] [PASSED] 0xE223 (BATTLEMAGE)
[02:39:47] [PASSED] 0xB080 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB081 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB082 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB083 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB084 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB085 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB086 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB087 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB08F (PANTHERLAKE)
[02:39:47] [PASSED] 0xB090 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB0A0 (PANTHERLAKE)
[02:39:47] [PASSED] 0xB0B0 (PANTHERLAKE)
[02:39:47] [PASSED] 0xFD80 (PANTHERLAKE)
[02:39:47] [PASSED] 0xFD81 (PANTHERLAKE)
[02:39:47] [PASSED] 0xD740 (NOVALAKE_S)
[02:39:47] [PASSED] 0xD741 (NOVALAKE_S)
[02:39:47] [PASSED] 0xD742 (NOVALAKE_S)
[02:39:47] [PASSED] 0xD743 (NOVALAKE_S)
[02:39:47] [PASSED] 0xD744 (NOVALAKE_S)
[02:39:47] [PASSED] 0xD745 (NOVALAKE_S)
[02:39:47] [PASSED] 0x674C (CRESCENTISLAND)
[02:39:47] [PASSED] 0xD750 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD751 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD752 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD753 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD754 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD755 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD756 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD757 (NOVALAKE_P)
[02:39:47] [PASSED] 0xD75F (NOVALAKE_P)
[02:39:47] =============== [PASSED] check_platform_desc ===============
[02:39:47] ===================== [PASSED] xe_pci ======================
[02:39:47] =================== xe_rtp (2 subtests) ====================
[02:39:47] =============== xe_rtp_process_to_sr_tests  ================
[02:39:47] [PASSED] coalesce-same-reg
[02:39:47] [PASSED] no-match-no-add
[02:39:47] [PASSED] match-or
[02:39:47] [PASSED] match-or-xfail
[02:39:47] [PASSED] no-match-no-add-multiple-rules
[02:39:47] [PASSED] two-regs-two-entries
[02:39:47] [PASSED] clr-one-set-other
[02:39:47] [PASSED] set-field
[02:39:47] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[02:39:47] [PASSED] conflict-not-disjoint
[02:39:47] [PASSED] conflict-reg-type
[02:39:47] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[02:39:47] ================== xe_rtp_process_tests  ===================
[02:39:47] [PASSED] active1
[02:39:47] [PASSED] active2
[02:39:47] [PASSED] active-inactive
[02:39:47] [PASSED] inactive-active
[02:39:47] [PASSED] inactive-1st_or_active-inactive
[02:39:47] [PASSED] inactive-2nd_or_active-inactive
[02:39:47] [PASSED] inactive-last_or_active-inactive
[02:39:47] [PASSED] inactive-no_or_active-inactive
[02:39:47] ============== [PASSED] xe_rtp_process_tests ===============
[02:39:47] ===================== [PASSED] xe_rtp ======================
[02:39:47] ==================== xe_wa (1 subtest) =====================
[02:39:47] ======================== xe_wa_gt  =========================
[02:39:47] [PASSED] TIGERLAKE B0
[02:39:47] [PASSED] DG1 A0
[02:39:47] [PASSED] DG1 B0
[02:39:47] [PASSED] ALDERLAKE_S A0
[02:39:47] [PASSED] ALDERLAKE_S B0
[02:39:47] [PASSED] ALDERLAKE_S C0
[02:39:47] [PASSED] ALDERLAKE_S D0
[02:39:47] [PASSED] ALDERLAKE_P A0
[02:39:47] [PASSED] ALDERLAKE_P B0
[02:39:47] [PASSED] ALDERLAKE_P C0
[02:39:47] [PASSED] ALDERLAKE_S RPLS D0
[02:39:47] [PASSED] ALDERLAKE_P RPLU E0
[02:39:47] [PASSED] DG2 G10 C0
[02:39:47] [PASSED] DG2 G11 B1
[02:39:47] [PASSED] DG2 G12 A1
[02:39:47] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:39:47] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:39:47] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[02:39:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[02:39:47] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[02:39:47] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[02:39:47] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[02:39:47] ==================== [PASSED] xe_wa_gt =====================
[02:39:47] ====================== [PASSED] xe_wa ======================
[02:39:47] ============================================================
[02:39:47] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[02:39:47] Elapsed time: 35.616s total, 4.171s configuring, 30.777s building, 0.611s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[02:39:47] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:39:49] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:40:12] Starting KUnit Kernel (1/1)...
[02:40:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:40:13] ============ drm_test_pick_cmdline (2 subtests) ============
[02:40:13] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[02:40:13] =============== drm_test_pick_cmdline_named  ===============
[02:40:13] [PASSED] NTSC
[02:40:13] [PASSED] NTSC-J
[02:40:13] [PASSED] PAL
[02:40:13] [PASSED] PAL-M
[02:40:13] =========== [PASSED] drm_test_pick_cmdline_named ===========
[02:40:13] ============== [PASSED] drm_test_pick_cmdline ==============
[02:40:13] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[02:40:13] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[02:40:13] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[02:40:13] =========== drm_validate_clone_mode (2 subtests) ===========
[02:40:13] ============== drm_test_check_in_clone_mode  ===============
[02:40:13] [PASSED] in_clone_mode
[02:40:13] [PASSED] not_in_clone_mode
[02:40:13] ========== [PASSED] drm_test_check_in_clone_mode ===========
[02:40:13] =============== drm_test_check_valid_clones  ===============
[02:40:13] [PASSED] not_in_clone_mode
[02:40:13] [PASSED] valid_clone
[02:40:13] [PASSED] invalid_clone
[02:40:13] =========== [PASSED] drm_test_check_valid_clones ===========
[02:40:13] ============= [PASSED] drm_validate_clone_mode =============
[02:40:13] ============= drm_validate_modeset (1 subtest) =============
[02:40:13] [PASSED] drm_test_check_connector_changed_modeset
[02:40:13] ============== [PASSED] drm_validate_modeset ===============
[02:40:13] ====== drm_test_bridge_get_current_state (2 subtests) ======
[02:40:13] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[02:40:13] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[02:40:13] ======== [PASSED] drm_test_bridge_get_current_state ========
[02:40:13] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[02:40:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[02:40:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[02:40:13] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[02:40:13] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[02:40:13] ============== drm_bridge_alloc (2 subtests) ===============
[02:40:13] [PASSED] drm_test_drm_bridge_alloc_basic
[02:40:13] [PASSED] drm_test_drm_bridge_alloc_get_put
[02:40:13] ================ [PASSED] drm_bridge_alloc =================
[02:40:13] ============= drm_cmdline_parser (40 subtests) =============
[02:40:13] [PASSED] drm_test_cmdline_force_d_only
[02:40:13] [PASSED] drm_test_cmdline_force_D_only_dvi
[02:40:13] [PASSED] drm_test_cmdline_force_D_only_hdmi
[02:40:13] [PASSED] drm_test_cmdline_force_D_only_not_digital
[02:40:13] [PASSED] drm_test_cmdline_force_e_only
[02:40:13] [PASSED] drm_test_cmdline_res
[02:40:13] [PASSED] drm_test_cmdline_res_vesa
[02:40:13] [PASSED] drm_test_cmdline_res_vesa_rblank
[02:40:13] [PASSED] drm_test_cmdline_res_rblank
[02:40:13] [PASSED] drm_test_cmdline_res_bpp
[02:40:13] [PASSED] drm_test_cmdline_res_refresh
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[02:40:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[02:40:13] [PASSED] drm_test_cmdline_res_margins_force_on
[02:40:13] [PASSED] drm_test_cmdline_res_vesa_margins
[02:40:13] [PASSED] drm_test_cmdline_name
[02:40:13] [PASSED] drm_test_cmdline_name_bpp
[02:40:13] [PASSED] drm_test_cmdline_name_option
[02:40:13] [PASSED] drm_test_cmdline_name_bpp_option
[02:40:13] [PASSED] drm_test_cmdline_rotate_0
[02:40:13] [PASSED] drm_test_cmdline_rotate_90
[02:40:13] [PASSED] drm_test_cmdline_rotate_180
[02:40:13] [PASSED] drm_test_cmdline_rotate_270
[02:40:13] [PASSED] drm_test_cmdline_hmirror
[02:40:13] [PASSED] drm_test_cmdline_vmirror
[02:40:13] [PASSED] drm_test_cmdline_margin_options
[02:40:13] [PASSED] drm_test_cmdline_multiple_options
[02:40:13] [PASSED] drm_test_cmdline_bpp_extra_and_option
[02:40:13] [PASSED] drm_test_cmdline_extra_and_option
[02:40:13] [PASSED] drm_test_cmdline_freestanding_options
[02:40:13] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[02:40:13] [PASSED] drm_test_cmdline_panel_orientation
[02:40:13] ================ drm_test_cmdline_invalid  =================
[02:40:13] [PASSED] margin_only
[02:40:13] [PASSED] interlace_only
[02:40:13] [PASSED] res_missing_x
[02:40:13] [PASSED] res_missing_y
[02:40:13] [PASSED] res_bad_y
[02:40:13] [PASSED] res_missing_y_bpp
[02:40:13] [PASSED] res_bad_bpp
[02:40:13] [PASSED] res_bad_refresh
[02:40:13] [PASSED] res_bpp_refresh_force_on_off
[02:40:13] [PASSED] res_invalid_mode
[02:40:13] [PASSED] res_bpp_wrong_place_mode
[02:40:13] [PASSED] name_bpp_refresh
[02:40:13] [PASSED] name_refresh
[02:40:13] [PASSED] name_refresh_wrong_mode
[02:40:13] [PASSED] name_refresh_invalid_mode
[02:40:13] [PASSED] rotate_multiple
[02:40:13] [PASSED] rotate_invalid_val
[02:40:13] [PASSED] rotate_truncated
[02:40:13] [PASSED] invalid_option
[02:40:13] [PASSED] invalid_tv_option
[02:40:13] [PASSED] truncated_tv_option
[02:40:13] ============ [PASSED] drm_test_cmdline_invalid =============
[02:40:13] =============== drm_test_cmdline_tv_options  ===============
[02:40:13] [PASSED] NTSC
[02:40:13] [PASSED] NTSC_443
[02:40:13] [PASSED] NTSC_J
[02:40:13] [PASSED] PAL
[02:40:13] [PASSED] PAL_M
[02:40:13] [PASSED] PAL_N
[02:40:13] [PASSED] SECAM
[02:40:13] [PASSED] MONO_525
[02:40:13] [PASSED] MONO_625
[02:40:13] =========== [PASSED] drm_test_cmdline_tv_options ===========
[02:40:13] =============== [PASSED] drm_cmdline_parser ================
[02:40:13] ========== drmm_connector_hdmi_init (20 subtests) ==========
[02:40:13] [PASSED] drm_test_connector_hdmi_init_valid
[02:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_8
[02:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_10
[02:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_12
[02:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[02:40:13] [PASSED] drm_test_connector_hdmi_init_bpc_null
[02:40:13] [PASSED] drm_test_connector_hdmi_init_formats_empty
[02:40:13] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[02:40:13] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[02:40:13] [PASSED] supported_formats=0x9 yuv420_allowed=1
[02:40:13] [PASSED] supported_formats=0x9 yuv420_allowed=0
[02:40:13] [PASSED] supported_formats=0x5 yuv420_allowed=1
[02:40:13] [PASSED] supported_formats=0x5 yuv420_allowed=0
[02:40:13] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[02:40:13] [PASSED] drm_test_connector_hdmi_init_null_ddc
[02:40:13] [PASSED] drm_test_connector_hdmi_init_null_product
[02:40:13] [PASSED] drm_test_connector_hdmi_init_null_vendor
[02:40:13] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[02:40:13] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[02:40:13] [PASSED] drm_test_connector_hdmi_init_product_valid
[02:40:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[02:40:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[02:40:13] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[02:40:13] ========= drm_test_connector_hdmi_init_type_valid  =========
[02:40:13] [PASSED] HDMI-A
[02:40:13] [PASSED] HDMI-B
[02:40:13] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[02:40:13] ======== drm_test_connector_hdmi_init_type_invalid  ========
[02:40:13] [PASSED] Unknown
[02:40:13] [PASSED] VGA
[02:40:13] [PASSED] DVI-I
[02:40:13] [PASSED] DVI-D
[02:40:13] [PASSED] DVI-A
[02:40:13] [PASSED] Composite
[02:40:13] [PASSED] SVIDEO
[02:40:13] [PASSED] LVDS
[02:40:13] [PASSED] Component
[02:40:13] [PASSED] DIN
[02:40:13] [PASSED] DP
[02:40:13] [PASSED] TV
[02:40:13] [PASSED] eDP
[02:40:13] [PASSED] Virtual
[02:40:13] [PASSED] DSI
[02:40:13] [PASSED] DPI
[02:40:13] [PASSED] Writeback
[02:40:13] [PASSED] SPI
[02:40:13] [PASSED] USB
[02:40:13] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[02:40:13] ============ [PASSED] drmm_connector_hdmi_init =============
[02:40:13] ============= drmm_connector_init (3 subtests) =============
[02:40:13] [PASSED] drm_test_drmm_connector_init
[02:40:13] [PASSED] drm_test_drmm_connector_init_null_ddc
[02:40:13] ========= drm_test_drmm_connector_init_type_valid  =========
[02:40:13] [PASSED] Unknown
[02:40:13] [PASSED] VGA
[02:40:13] [PASSED] DVI-I
[02:40:13] [PASSED] DVI-D
[02:40:13] [PASSED] DVI-A
[02:40:13] [PASSED] Composite
[02:40:13] [PASSED] SVIDEO
[02:40:13] [PASSED] LVDS
[02:40:13] [PASSED] Component
[02:40:13] [PASSED] DIN
[02:40:13] [PASSED] DP
[02:40:13] [PASSED] HDMI-A
[02:40:13] [PASSED] HDMI-B
[02:40:13] [PASSED] TV
[02:40:13] [PASSED] eDP
[02:40:13] [PASSED] Virtual
[02:40:13] [PASSED] DSI
[02:40:13] [PASSED] DPI
[02:40:13] [PASSED] Writeback
[02:40:13] [PASSED] SPI
[02:40:13] [PASSED] USB
[02:40:13] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[02:40:13] =============== [PASSED] drmm_connector_init ===============
[02:40:13] ========= drm_connector_dynamic_init (6 subtests) ==========
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_init
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_init_properties
[02:40:13] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[02:40:13] [PASSED] Unknown
[02:40:13] [PASSED] VGA
[02:40:13] [PASSED] DVI-I
[02:40:13] [PASSED] DVI-D
[02:40:13] [PASSED] DVI-A
[02:40:13] [PASSED] Composite
[02:40:13] [PASSED] SVIDEO
[02:40:13] [PASSED] LVDS
[02:40:13] [PASSED] Component
[02:40:13] [PASSED] DIN
[02:40:13] [PASSED] DP
[02:40:13] [PASSED] HDMI-A
[02:40:13] [PASSED] HDMI-B
[02:40:13] [PASSED] TV
[02:40:13] [PASSED] eDP
[02:40:13] [PASSED] Virtual
[02:40:13] [PASSED] DSI
[02:40:13] [PASSED] DPI
[02:40:13] [PASSED] Writeback
[02:40:13] [PASSED] SPI
[02:40:13] [PASSED] USB
[02:40:13] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[02:40:13] ======== drm_test_drm_connector_dynamic_init_name  =========
[02:40:13] [PASSED] Unknown
[02:40:13] [PASSED] VGA
[02:40:13] [PASSED] DVI-I
[02:40:13] [PASSED] DVI-D
[02:40:13] [PASSED] DVI-A
[02:40:13] [PASSED] Composite
[02:40:13] [PASSED] SVIDEO
[02:40:13] [PASSED] LVDS
[02:40:13] [PASSED] Component
[02:40:13] [PASSED] DIN
[02:40:13] [PASSED] DP
[02:40:13] [PASSED] HDMI-A
[02:40:13] [PASSED] HDMI-B
[02:40:13] [PASSED] TV
[02:40:13] [PASSED] eDP
[02:40:13] [PASSED] Virtual
[02:40:13] [PASSED] DSI
[02:40:13] [PASSED] DPI
[02:40:13] [PASSED] Writeback
[02:40:13] [PASSED] SPI
[02:40:13] [PASSED] USB
[02:40:13] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[02:40:13] =========== [PASSED] drm_connector_dynamic_init ============
[02:40:13] ==== drm_connector_dynamic_register_early (4 subtests) =====
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[02:40:13] ====== [PASSED] drm_connector_dynamic_register_early =======
[02:40:13] ======= drm_connector_dynamic_register (7 subtests) ========
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[02:40:13] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[02:40:13] ========= [PASSED] drm_connector_dynamic_register ==========
[02:40:13] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[02:40:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[02:40:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[02:40:13] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[02:40:13] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[02:40:13] ========== drm_test_get_tv_mode_from_name_valid  ===========
[02:40:13] [PASSED] NTSC
[02:40:13] [PASSED] NTSC-443
[02:40:13] [PASSED] NTSC-J
[02:40:13] [PASSED] PAL
[02:40:13] [PASSED] PAL-M
[02:40:13] [PASSED] PAL-N
[02:40:13] [PASSED] SECAM
[02:40:13] [PASSED] Mono
[02:40:13] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[02:40:13] [PASSED] drm_test_get_tv_mode_from_name_truncated
[02:40:13] ============ [PASSED] drm_get_tv_mode_from_name ============
[02:40:13] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[02:40:13] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[02:40:13] [PASSED] VIC 96
[02:40:13] [PASSED] VIC 97
[02:40:13] [PASSED] VIC 101
[02:40:13] [PASSED] VIC 102
[02:40:13] [PASSED] VIC 106
[02:40:13] [PASSED] VIC 107
[02:40:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[02:40:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[02:40:13] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[02:40:13] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[02:40:13] [PASSED] Automatic
[02:40:13] [PASSED] Full
[02:40:13] [PASSED] Limited 16:235
[02:40:13] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[02:40:13] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[02:40:13] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[02:40:13] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[02:40:13] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[02:40:13] [PASSED] RGB
[02:40:13] [PASSED] YUV 4:2:0
[02:40:13] [PASSED] YUV 4:2:2
[02:40:13] [PASSED] YUV 4:4:4
[02:40:13] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[02:40:13] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[02:40:13] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[02:40:13] ============= drm_damage_helper (21 subtests) ==============
[02:40:13] [PASSED] drm_test_damage_iter_no_damage
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_not_visible
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_no_fb
[02:40:13] [PASSED] drm_test_damage_iter_simple_damage
[02:40:13] [PASSED] drm_test_damage_iter_single_damage
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_outside_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_damage
[02:40:13] [PASSED] drm_test_damage_iter_damage_one_intersect
[02:40:13] [PASSED] drm_test_damage_iter_damage_one_outside
[02:40:13] [PASSED] drm_test_damage_iter_damage_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_damage_not_visible
[02:40:13] ================ [PASSED] drm_damage_helper ================
[02:40:13] ============== drm_dp_mst_helper (3 subtests) ==============
[02:40:13] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[02:40:13] [PASSED] Clock 154000 BPP 30 DSC disabled
[02:40:13] [PASSED] Clock 234000 BPP 30 DSC disabled
[02:40:13] [PASSED] Clock 297000 BPP 24 DSC disabled
[02:40:13] [PASSED] Clock 332880 BPP 24 DSC enabled
[02:40:13] [PASSED] Clock 324540 BPP 24 DSC enabled
[02:40:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[02:40:13] ============== drm_test_dp_mst_calc_pbn_div  ===============
[02:40:13] [PASSED] Link rate 2000000 lane count 4
[02:40:13] [PASSED] Link rate 2000000 lane count 2
[02:40:13] [PASSED] Link rate 2000000 lane count 1
[02:40:13] [PASSED] Link rate 1350000 lane count 4
[02:40:13] [PASSED] Link rate 1350000 lane count 2
[02:40:13] [PASSED] Link rate 1350000 lane count 1
[02:40:13] [PASSED] Link rate 1000000 lane count 4
[02:40:13] [PASSED] Link rate 1000000 lane count 2
[02:40:13] [PASSED] Link rate 1000000 lane count 1
[02:40:13] [PASSED] Link rate 810000 lane count 4
[02:40:13] [PASSED] Link rate 810000 lane count 2
[02:40:13] [PASSED] Link rate 810000 lane count 1
[02:40:13] [PASSED] Link rate 540000 lane count 4
[02:40:13] [PASSED] Link rate 540000 lane count 2
[02:40:13] [PASSED] Link rate 540000 lane count 1
[02:40:13] [PASSED] Link rate 270000 lane count 4
[02:40:13] [PASSED] Link rate 270000 lane count 2
[02:40:13] [PASSED] Link rate 270000 lane count 1
[02:40:13] [PASSED] Link rate 162000 lane count 4
[02:40:13] [PASSED] Link rate 162000 lane count 2
[02:40:13] [PASSED] Link rate 162000 lane count 1
[02:40:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[02:40:13] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[02:40:13] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[02:40:13] [PASSED] DP_POWER_UP_PHY with port number
[02:40:13] [PASSED] DP_POWER_DOWN_PHY with port number
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[02:40:13] [PASSED] DP_QUERY_PAYLOAD with port number
[02:40:13] [PASSED] DP_QUERY_PAYLOAD with VCPI
[02:40:13] [PASSED] DP_REMOTE_DPCD_READ with port number
[02:40:13] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[02:40:13] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[02:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[02:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[02:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[02:40:13] [PASSED] DP_REMOTE_I2C_READ with port number
[02:40:13] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[02:40:13] [PASSED] DP_REMOTE_I2C_READ with transactions array
[02:40:13] [PASSED] DP_REMOTE_I2C_WRITE with port number
[02:40:13] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[02:40:13] [PASSED] DP_REMOTE_I2C_WRITE with data array
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[02:40:13] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[02:40:13] ================ [PASSED] drm_dp_mst_helper ================
[02:40:13] ================== drm_exec (7 subtests) ===================
[02:40:13] [PASSED] sanitycheck
[02:40:13] [PASSED] test_lock
[02:40:13] [PASSED] test_lock_unlock
[02:40:13] [PASSED] test_duplicates
[02:40:13] [PASSED] test_prepare
[02:40:13] [PASSED] test_prepare_array
[02:40:13] [PASSED] test_multiple_loops
[02:40:13] ==================== [PASSED] drm_exec =====================
[02:40:13] =========== drm_format_helper_test (17 subtests) ===========
[02:40:13] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[02:40:13] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[02:40:13] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[02:40:13] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[02:40:13] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[02:40:13] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[02:40:13] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[02:40:13] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[02:40:13] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[02:40:13] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[02:40:13] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[02:40:13] ============== drm_test_fb_xrgb8888_to_mono  ===============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[02:40:13] ==================== drm_test_fb_swab  =====================
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ================ [PASSED] drm_test_fb_swab =================
[02:40:13] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[02:40:13] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[02:40:13] ================= drm_test_fb_clip_offset  =================
[02:40:13] [PASSED] pass through
[02:40:13] [PASSED] horizontal offset
[02:40:13] [PASSED] vertical offset
[02:40:13] [PASSED] horizontal and vertical offset
[02:40:13] [PASSED] horizontal offset (custom pitch)
[02:40:13] [PASSED] vertical offset (custom pitch)
[02:40:13] [PASSED] horizontal and vertical offset (custom pitch)
[02:40:13] ============= [PASSED] drm_test_fb_clip_offset =============
[02:40:13] =================== drm_test_fb_memcpy  ====================
[02:40:13] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[02:40:13] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[02:40:13] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[02:40:13] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[02:40:13] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[02:40:13] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[02:40:13] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[02:40:13] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[02:40:13] =============== [PASSED] drm_test_fb_memcpy ================
[02:40:13] ============= [PASSED] drm_format_helper_test ==============
[02:40:13] ================= drm_format (18 subtests) =================
[02:40:13] [PASSED] drm_test_format_block_width_invalid
[02:40:13] [PASSED] drm_test_format_block_width_one_plane
[02:40:13] [PASSED] drm_test_format_block_width_two_plane
[02:40:13] [PASSED] drm_test_format_block_width_three_plane
[02:40:13] [PASSED] drm_test_format_block_width_tiled
[02:40:13] [PASSED] drm_test_format_block_height_invalid
[02:40:13] [PASSED] drm_test_format_block_height_one_plane
[02:40:13] [PASSED] drm_test_format_block_height_two_plane
[02:40:13] [PASSED] drm_test_format_block_height_three_plane
[02:40:13] [PASSED] drm_test_format_block_height_tiled
[02:40:13] [PASSED] drm_test_format_min_pitch_invalid
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_two_plane
[02:40:13] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_tiled
[02:40:13] =================== [PASSED] drm_format ====================
[02:40:13] ============== drm_framebuffer (10 subtests) ===============
[02:40:13] ========== drm_test_framebuffer_check_src_coords  ==========
[02:40:13] [PASSED] Success: source fits into fb
[02:40:13] [PASSED] Fail: overflowing fb with x-axis coordinate
[02:40:13] [PASSED] Fail: overflowing fb with y-axis coordinate
[02:40:13] [PASSED] Fail: overflowing fb with source width
[02:40:13] [PASSED] Fail: overflowing fb with source height
[02:40:13] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[02:40:13] [PASSED] drm_test_framebuffer_cleanup
[02:40:13] =============== drm_test_framebuffer_create  ===============
[02:40:13] [PASSED] ABGR8888 normal sizes
[02:40:13] [PASSED] ABGR8888 max sizes
[02:40:13] [PASSED] ABGR8888 pitch greater than min required
[02:40:13] [PASSED] ABGR8888 pitch less than min required
[02:40:13] [PASSED] ABGR8888 Invalid width
[02:40:13] [PASSED] ABGR8888 Invalid buffer handle
[02:40:13] [PASSED] No pixel format
[02:40:13] [PASSED] ABGR8888 Width 0
[02:40:13] [PASSED] ABGR8888 Height 0
[02:40:13] [PASSED] ABGR8888 Out of bound height * pitch combination
[02:40:13] [PASSED] ABGR8888 Large buffer offset
[02:40:13] [PASSED] ABGR8888 Buffer offset for inexistent plane
[02:40:13] [PASSED] ABGR8888 Invalid flag
[02:40:13] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[02:40:13] [PASSED] ABGR8888 Valid buffer modifier
[02:40:13] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[02:40:13] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] NV12 Normal sizes
[02:40:13] [PASSED] NV12 Max sizes
[02:40:13] [PASSED] NV12 Invalid pitch
[02:40:13] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[02:40:13] [PASSED] NV12 different  modifier per-plane
[02:40:13] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[02:40:13] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] NV12 Modifier for inexistent plane
[02:40:13] [PASSED] NV12 Handle for inexistent plane
[02:40:13] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[02:40:13] [PASSED] YVU420 Normal sizes
[02:40:13] [PASSED] YVU420 Max sizes
[02:40:13] [PASSED] YVU420 Invalid pitch
[02:40:13] [PASSED] YVU420 Different pitches
[02:40:13] [PASSED] YVU420 Different buffer offsets/pitches
[02:40:13] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 Valid modifier
[02:40:13] [PASSED] YVU420 Different modifiers per plane
[02:40:13] [PASSED] YVU420 Modifier for inexistent plane
[02:40:13] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[02:40:13] [PASSED] X0L2 Normal sizes
[02:40:13] [PASSED] X0L2 Max sizes
[02:40:13] [PASSED] X0L2 Invalid pitch
[02:40:13] [PASSED] X0L2 Pitch greater than minimum required
[02:40:13] [PASSED] X0L2 Handle for inexistent plane
[02:40:13] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[02:40:13] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[02:40:13] [PASSED] X0L2 Valid modifier
[02:40:13] [PASSED] X0L2 Modifier for inexistent plane
[02:40:13] =========== [PASSED] drm_test_framebuffer_create ===========
[02:40:13] [PASSED] drm_test_framebuffer_free
[02:40:13] [PASSED] drm_test_framebuffer_init
[02:40:13] [PASSED] drm_test_framebuffer_init_bad_format
[02:40:13] [PASSED] drm_test_framebuffer_init_dev_mismatch
[02:40:13] [PASSED] drm_test_framebuffer_lookup
[02:40:13] [PASSED] drm_test_framebuffer_lookup_inexistent
[02:40:13] [PASSED] drm_test_framebuffer_modifiers_not_supported
[02:40:13] ================= [PASSED] drm_framebuffer =================
[02:40:13] ================ drm_gem_shmem (8 subtests) ================
[02:40:13] [PASSED] drm_gem_shmem_test_obj_create
[02:40:13] [PASSED] drm_gem_shmem_test_obj_create_private
[02:40:13] [PASSED] drm_gem_shmem_test_pin_pages
[02:40:13] [PASSED] drm_gem_shmem_test_vmap
[02:40:13] [PASSED] drm_gem_shmem_test_get_sg_table
[02:40:13] [PASSED] drm_gem_shmem_test_get_pages_sgt
[02:40:13] [PASSED] drm_gem_shmem_test_madvise
[02:40:13] [PASSED] drm_gem_shmem_test_purge
[02:40:13] ================== [PASSED] drm_gem_shmem ==================
[02:40:13] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[02:40:13] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[02:40:13] [PASSED] Automatic
[02:40:13] [PASSED] Full
[02:40:13] [PASSED] Limited 16:235
[02:40:13] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[02:40:13] [PASSED] drm_test_check_disable_connector
[02:40:13] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[02:40:13] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[02:40:13] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[02:40:13] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[02:40:13] [PASSED] drm_test_check_output_bpc_dvi
[02:40:13] [PASSED] drm_test_check_output_bpc_format_vic_1
[02:40:13] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[02:40:13] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[02:40:13] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[02:40:13] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[02:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[02:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[02:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[02:40:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[02:40:13] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_value
[02:40:13] [PASSED] drm_test_check_bpc_8_value
[02:40:13] [PASSED] drm_test_check_bpc_10_value
[02:40:13] [PASSED] drm_test_check_bpc_12_value
[02:40:13] [PASSED] drm_test_check_format_value
[02:40:13] [PASSED] drm_test_check_tmds_char_value
[02:40:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[02:40:13] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[02:40:13] [PASSED] drm_test_check_mode_valid
[02:40:13] [PASSED] drm_test_check_mode_valid_reject
[02:40:13] [PASSED] drm_test_check_mode_valid_reject_rate
[02:40:13] [PASSED] drm_test_check_mode_valid_reject_max_clock
[02:40:13] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[02:40:13] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[02:40:13] [PASSED] drm_test_check_infoframes
[02:40:13] [PASSED] drm_test_check_reject_avi_infoframe
[02:40:13] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[02:40:13] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[02:40:13] [PASSED] drm_test_check_reject_audio_infoframe
[02:40:13] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[02:40:13] ================= drm_managed (2 subtests) =================
[02:40:13] [PASSED] drm_test_managed_release_action
[02:40:13] [PASSED] drm_test_managed_run_action
[02:40:13] =================== [PASSED] drm_managed ===================
[02:40:13] =================== drm_mm (6 subtests) ====================
[02:40:13] [PASSED] drm_test_mm_init
[02:40:13] [PASSED] drm_test_mm_debug
[02:40:13] [PASSED] drm_test_mm_align32
[02:40:13] [PASSED] drm_test_mm_align64
[02:40:13] [PASSED] drm_test_mm_lowest
[02:40:13] [PASSED] drm_test_mm_highest
[02:40:13] ===================== [PASSED] drm_mm ======================
[02:40:13] ============= drm_modes_analog_tv (5 subtests) =============
[02:40:13] [PASSED] drm_test_modes_analog_tv_mono_576i
[02:40:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[02:40:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[02:40:13] [PASSED] drm_test_modes_analog_tv_pal_576i
[02:40:13] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[02:40:13] =============== [PASSED] drm_modes_analog_tv ===============
[02:40:13] ============== drm_plane_helper (2 subtests) ===============
[02:40:13] =============== drm_test_check_plane_state  ================
[02:40:13] [PASSED] clipping_simple
[02:40:13] [PASSED] clipping_rotate_reflect
[02:40:13] [PASSED] positioning_simple
[02:40:13] [PASSED] upscaling
[02:40:13] [PASSED] downscaling
[02:40:13] [PASSED] rounding1
[02:40:13] [PASSED] rounding2
[02:40:13] [PASSED] rounding3
[02:40:13] [PASSED] rounding4
[02:40:13] =========== [PASSED] drm_test_check_plane_state ============
[02:40:13] =========== drm_test_check_invalid_plane_state  ============
[02:40:13] [PASSED] positioning_invalid
[02:40:13] [PASSED] upscaling_invalid
[02:40:13] [PASSED] downscaling_invalid
[02:40:13] ======= [PASSED] drm_test_check_invalid_plane_state ========
[02:40:13] ================ [PASSED] drm_plane_helper =================
[02:40:13] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[02:40:13] ====== drm_test_connector_helper_tv_get_modes_check  =======
[02:40:13] [PASSED] None
[02:40:13] [PASSED] PAL
[02:40:13] [PASSED] NTSC
[02:40:13] [PASSED] Both, NTSC Default
[02:40:13] [PASSED] Both, PAL Default
[02:40:13] [PASSED] Both, NTSC Default, with PAL on command-line
[02:40:13] [PASSED] Both, PAL Default, with NTSC on command-line
[02:40:13] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[02:40:13] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[02:40:13] ================== drm_rect (9 subtests) ===================
[02:40:13] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[02:40:13] [PASSED] drm_test_rect_clip_scaled_not_clipped
[02:40:13] [PASSED] drm_test_rect_clip_scaled_clipped
[02:40:13] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[02:40:13] ================= drm_test_rect_intersect  =================
[02:40:13] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[02:40:13] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[02:40:13] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[02:40:13] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[02:40:13] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[02:40:13] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[02:40:13] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[02:40:13] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[02:40:13] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[02:40:13] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[02:40:13] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[02:40:13] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[02:40:13] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[02:40:13] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[02:40:13] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[02:40:13] ============= [PASSED] drm_test_rect_intersect =============
[02:40:13] ================ drm_test_rect_calc_hscale  ================
[02:40:13] [PASSED] normal use
[02:40:13] [PASSED] out of max range
[02:40:13] [PASSED] out of min range
[02:40:13] [PASSED] zero dst
[02:40:13] [PASSED] negative src
[02:40:13] [PASSED] negative dst
[02:40:13] ============ [PASSED] drm_test_rect_calc_hscale ============
[02:40:13] ================ drm_test_rect_calc_vscale  ================
[02:40:13] [PASSED] normal use
[02:40:13] [PASSED] out of max range
[02:40:13] [PASSED] out of min range
[02:40:13] [PASSED] zero dst
[02:40:13] [PASSED] negative src
[02:40:13] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[02:40:13] ============ [PASSED] drm_test_rect_calc_vscale ============
[02:40:13] ================== drm_test_rect_rotate  ===================
[02:40:13] [PASSED] reflect-x
[02:40:13] [PASSED] reflect-y
[02:40:13] [PASSED] rotate-0
[02:40:13] [PASSED] rotate-90
[02:40:13] [PASSED] rotate-180
[02:40:13] [PASSED] rotate-270
[02:40:13] ============== [PASSED] drm_test_rect_rotate ===============
[02:40:13] ================ drm_test_rect_rotate_inv  =================
[02:40:13] [PASSED] reflect-x
[02:40:13] [PASSED] reflect-y
[02:40:13] [PASSED] rotate-0
[02:40:13] [PASSED] rotate-90
[02:40:13] [PASSED] rotate-180
[02:40:13] [PASSED] rotate-270
[02:40:13] ============ [PASSED] drm_test_rect_rotate_inv =============
[02:40:13] ==================== [PASSED] drm_rect =====================
[02:40:13] ============ drm_sysfb_modeset_test (1 subtest) ============
[02:40:13] ============ drm_test_sysfb_build_fourcc_list  =============
[02:40:13] [PASSED] no native formats
[02:40:13] [PASSED] XRGB8888 as native format
[02:40:13] [PASSED] remove duplicates
[02:40:13] [PASSED] convert alpha formats
[02:40:13] [PASSED] random formats
[02:40:13] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[02:40:13] ============= [PASSED] drm_sysfb_modeset_test ==============
[02:40:13] ================== drm_fixp (2 subtests) ===================
[02:40:13] [PASSED] drm_test_int2fixp
[02:40:13] [PASSED] drm_test_sm2fixp
[02:40:13] ==================== [PASSED] drm_fixp =====================
[02:40:13] ============================================================
[02:40:13] Testing complete. Ran 621 tests: passed: 621
[02:40:13] Elapsed time: 25.692s total, 1.616s configuring, 23.904s building, 0.145s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[02:40:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:40:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:40:24] Starting KUnit Kernel (1/1)...
[02:40:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:40:24] ================= ttm_device (5 subtests) ==================
[02:40:24] [PASSED] ttm_device_init_basic
[02:40:24] [PASSED] ttm_device_init_multiple
[02:40:24] [PASSED] ttm_device_fini_basic
[02:40:24] [PASSED] ttm_device_init_no_vma_man
[02:40:24] ================== ttm_device_init_pools  ==================
[02:40:24] [PASSED] No DMA allocations, no DMA32 required
[02:40:24] [PASSED] DMA allocations, DMA32 required
[02:40:24] [PASSED] No DMA allocations, DMA32 required
[02:40:24] [PASSED] DMA allocations, no DMA32 required
[02:40:24] ============== [PASSED] ttm_device_init_pools ==============
[02:40:24] =================== [PASSED] ttm_device ====================
[02:40:24] ================== ttm_pool (8 subtests) ===================
[02:40:24] ================== ttm_pool_alloc_basic  ===================
[02:40:24] [PASSED] One page
[02:40:24] [PASSED] More than one page
[02:40:24] [PASSED] Above the allocation limit
[02:40:24] [PASSED] One page, with coherent DMA mappings enabled
[02:40:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:40:24] ============== [PASSED] ttm_pool_alloc_basic ===============
[02:40:24] ============== ttm_pool_alloc_basic_dma_addr  ==============
[02:40:24] [PASSED] One page
[02:40:24] [PASSED] More than one page
[02:40:24] [PASSED] Above the allocation limit
[02:40:24] [PASSED] One page, with coherent DMA mappings enabled
[02:40:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:40:24] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[02:40:24] [PASSED] ttm_pool_alloc_order_caching_match
[02:40:24] [PASSED] ttm_pool_alloc_caching_mismatch
[02:40:24] [PASSED] ttm_pool_alloc_order_mismatch
[02:40:24] [PASSED] ttm_pool_free_dma_alloc
[02:40:24] [PASSED] ttm_pool_free_no_dma_alloc
[02:40:24] [PASSED] ttm_pool_fini_basic
[02:40:24] ==================== [PASSED] ttm_pool =====================
[02:40:24] ================ ttm_resource (8 subtests) =================
[02:40:24] ================= ttm_resource_init_basic  =================
[02:40:24] [PASSED] Init resource in TTM_PL_SYSTEM
[02:40:24] [PASSED] Init resource in TTM_PL_VRAM
[02:40:24] [PASSED] Init resource in a private placement
[02:40:24] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[02:40:24] ============= [PASSED] ttm_resource_init_basic =============
[02:40:24] [PASSED] ttm_resource_init_pinned
[02:40:24] [PASSED] ttm_resource_fini_basic
[02:40:24] [PASSED] ttm_resource_manager_init_basic
[02:40:24] [PASSED] ttm_resource_manager_usage_basic
[02:40:24] [PASSED] ttm_resource_manager_set_used_basic
[02:40:24] [PASSED] ttm_sys_man_alloc_basic
[02:40:24] [PASSED] ttm_sys_man_free_basic
[02:40:24] ================== [PASSED] ttm_resource ===================
[02:40:24] =================== ttm_tt (15 subtests) ===================
[02:40:24] ==================== ttm_tt_init_basic  ====================
[02:40:24] [PASSED] Page-aligned size
[02:40:24] [PASSED] Extra pages requested
[02:40:24] ================ [PASSED] ttm_tt_init_basic ================
[02:40:24] [PASSED] ttm_tt_init_misaligned
[02:40:24] [PASSED] ttm_tt_fini_basic
[02:40:24] [PASSED] ttm_tt_fini_sg
[02:40:24] [PASSED] ttm_tt_fini_shmem
[02:40:24] [PASSED] ttm_tt_create_basic
[02:40:24] [PASSED] ttm_tt_create_invalid_bo_type
[02:40:24] [PASSED] ttm_tt_create_ttm_exists
[02:40:24] [PASSED] ttm_tt_create_failed
[02:40:24] [PASSED] ttm_tt_destroy_basic
[02:40:24] [PASSED] ttm_tt_populate_null_ttm
[02:40:24] [PASSED] ttm_tt_populate_populated_ttm
[02:40:24] [PASSED] ttm_tt_unpopulate_basic
[02:40:24] [PASSED] ttm_tt_unpopulate_empty_ttm
[02:40:24] [PASSED] ttm_tt_swapin_basic
[02:40:24] ===================== [PASSED] ttm_tt ======================
[02:40:24] =================== ttm_bo (14 subtests) ===================
[02:40:24] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[02:40:24] [PASSED] Cannot be interrupted and sleeps
[02:40:24] [PASSED] Cannot be interrupted, locks straight away
[02:40:24] [PASSED] Can be interrupted, sleeps
[02:40:24] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[02:40:24] [PASSED] ttm_bo_reserve_locked_no_sleep
[02:40:24] [PASSED] ttm_bo_reserve_no_wait_ticket
[02:40:24] [PASSED] ttm_bo_reserve_double_resv
[02:40:24] [PASSED] ttm_bo_reserve_interrupted
[02:40:24] [PASSED] ttm_bo_reserve_deadlock
[02:40:24] [PASSED] ttm_bo_unreserve_basic
[02:40:24] [PASSED] ttm_bo_unreserve_pinned
[02:40:24] [PASSED] ttm_bo_unreserve_bulk
[02:40:24] [PASSED] ttm_bo_fini_basic
[02:40:24] [PASSED] ttm_bo_fini_shared_resv
[02:40:24] [PASSED] ttm_bo_pin_basic
[02:40:24] [PASSED] ttm_bo_pin_unpin_resource
[02:40:24] [PASSED] ttm_bo_multiple_pin_one_unpin
[02:40:24] ===================== [PASSED] ttm_bo ======================
[02:40:24] ============== ttm_bo_validate (22 subtests) ===============
[02:40:24] ============== ttm_bo_init_reserved_sys_man  ===============
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[02:40:24] ============== ttm_bo_init_reserved_mock_man  ==============
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[02:40:24] [PASSED] ttm_bo_init_reserved_resv
[02:40:24] ================== ttm_bo_validate_basic  ==================
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ============== [PASSED] ttm_bo_validate_basic ==============
[02:40:24] [PASSED] ttm_bo_validate_invalid_placement
[02:40:24] ============= ttm_bo_validate_same_placement  ==============
[02:40:24] [PASSED] System manager
[02:40:24] [PASSED] VRAM manager
[02:40:24] ========= [PASSED] ttm_bo_validate_same_placement ==========
[02:40:24] [PASSED] ttm_bo_validate_failed_alloc
[02:40:24] [PASSED] ttm_bo_validate_pinned
[02:40:24] [PASSED] ttm_bo_validate_busy_placement
[02:40:24] ================ ttm_bo_validate_multihop  =================
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ============ [PASSED] ttm_bo_validate_multihop =============
[02:40:24] ========== ttm_bo_validate_no_placement_signaled  ==========
[02:40:24] [PASSED] Buffer object in system domain, no page vector
[02:40:24] [PASSED] Buffer object in system domain with an existing page vector
[02:40:24] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[02:40:24] ======== ttm_bo_validate_no_placement_not_signaled  ========
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[02:40:24] [PASSED] ttm_bo_validate_move_fence_signaled
[02:40:24] ========= ttm_bo_validate_move_fence_not_signaled  =========
[02:40:24] [PASSED] Waits for GPU
[02:40:24] [PASSED] Tries to lock straight away
[02:40:24] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[02:40:24] [PASSED] ttm_bo_validate_swapout
[02:40:24] [PASSED] ttm_bo_validate_happy_evict
[02:40:24] [PASSED] ttm_bo_validate_all_pinned_evict
[02:40:24] [PASSED] ttm_bo_validate_allowed_only_evict
[02:40:24] [PASSED] ttm_bo_validate_deleted_evict
[02:40:24] [PASSED] ttm_bo_validate_busy_domain_evict
[02:40:24] [PASSED] ttm_bo_validate_evict_gutting
[02:40:24] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[02:40:24] ================= [PASSED] ttm_bo_validate =================
[02:40:24] ============================================================
[02:40:24] Testing complete. Ran 102 tests: passed: 102
[02:40:24] Elapsed time: 11.076s total, 1.638s configuring, 9.222s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915: move more display dependencies from i915 (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 971 bytes --]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev4)
URL   : https://patchwork.freedesktop.org/series/163785/
State : success

== Summary ==

CI Bug Log - changes from xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201_BAT -> xe-pw-163785v4_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201 -> xe-pw-163785v4

  IGT_8863: 5b279a8b71dc1672099205a1a9e8135c7c7fadb5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201: da91cb4e6137507f74e4da41c39d0260b4cd1201
  xe-pw-163785v4: 163785v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/index.html

[-- Attachment #2: Type: text/html, Size: 1519 bytes --]

✗ Xe.CI.FULL: failure for drm/i915: move more display dependencies from i915 (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 21314 bytes --]

== Series Details ==

Series: drm/i915: move more display dependencies from i915 (rev4)
URL   : https://patchwork.freedesktop.org/series/163785/
State : failure

== Summary ==

CI Bug Log - changes from xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201_FULL -> xe-pw-163785v4_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-163785v4_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-163785v4_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-163785v4_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-dp-2:
    - shard-bmg:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-10/igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-dp-2.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-dp-2.html

  
Known issues
------------

  Here are the changes found in xe-pw-163785v4_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2652]) +7 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_cursor_edge_walk@256x256-top-bottom:
    - shard-bmg:          [PASS][4] -> [ABORT][5] ([Intel XE#1727])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-10/igt@kms_cursor_edge_walk@256x256-top-bottom.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-top-bottom.html

  * igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-d-dp-2:
    - shard-bmg:          [PASS][6] -> [INCOMPLETE][7] ([Intel XE#1727])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-10/igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-d-dp-2.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-2/igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-d-dp-2.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-bmg:          [PASS][8] -> [DMESG-WARN][9] ([Intel XE#5354])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][10] -> [FAIL][11] ([Intel XE#7571])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling:
    - shard-bmg:          [PASS][12] -> [DMESG-WARN][13] ([Intel XE#1727] / [Intel XE#6819]) +1 other test dmesg-warn
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-upscaling.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][14] -> [SKIP][15] ([Intel XE#1503])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-6/igt@kms_hdr@invalid-hdr.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-bmg:          [DMESG-FAIL][16] ([Intel XE#5545]) -> [PASS][17] +1 other test pass
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][18] ([Intel XE#6321]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-10/igt@xe_evict@evict-mixed-many-threads-small.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [FAIL][20] ([Intel XE#5625]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-lnl-6/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_exec_system_allocator@threads-many-stride-malloc-nomemset:
    - shard-bmg:          [SKIP][22] ([Intel XE#6703]) -> [PASS][23] +89 other tests pass
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-stride-malloc-nomemset.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_exec_system_allocator@threads-many-stride-malloc-nomemset.html

  
#### Warnings ####

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-bmg:          [SKIP][24] ([Intel XE#6703]) -> [SKIP][25] ([Intel XE#1124])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_bw@linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [SKIP][26] ([Intel XE#6703]) -> [SKIP][27] ([Intel XE#367] / [Intel XE#7354])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_bw@linear-tiling-2-displays-3840x2160p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-bmg:          [SKIP][28] ([Intel XE#6703]) -> [SKIP][29] ([Intel XE#2652])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs:
    - shard-bmg:          [SKIP][30] ([Intel XE#6703]) -> [SKIP][31] ([Intel XE#2887]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-bmg:          [SKIP][32] ([Intel XE#6703]) -> [SKIP][33] ([Intel XE#2252])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-bmg:          [SKIP][34] ([Intel XE#6703]) -> [SKIP][35] ([Intel XE#2320])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_cursor_crc@cursor-random-max-size.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_fbcon_fbt@psr:
    - shard-bmg:          [SKIP][36] ([Intel XE#6703]) -> [SKIP][37] ([Intel XE#6126] / [Intel XE#776])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_fbcon_fbt@psr.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_fbcon_fbt@psr.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-bmg:          [SKIP][38] ([Intel XE#6703]) -> [SKIP][39] ([Intel XE#4141]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][40] ([Intel XE#6703]) -> [SKIP][41] ([Intel XE#2311]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
    - shard-bmg:          [SKIP][42] ([Intel XE#6703]) -> [SKIP][43] ([Intel XE#2313]) +2 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][44] ([Intel XE#2312]) -> [SKIP][45] ([Intel XE#2313])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-3/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-10/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][46] ([Intel XE#3544]) -> [SKIP][47] ([Intel XE#3374] / [Intel XE#3544])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          [SKIP][48] ([Intel XE#6703]) -> [SKIP][49] ([Intel XE#4090] / [Intel XE#7443])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-bmg:          [SKIP][50] ([Intel XE#6703]) -> [SKIP][51] ([Intel XE#7283])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          [SKIP][52] ([Intel XE#6703]) -> [SKIP][53] ([Intel XE#2499])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_pm_lpsp@kms-lpsp.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr@psr-basic:
    - shard-bmg:          [SKIP][54] ([Intel XE#6703]) -> [SKIP][55] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_psr@psr-basic.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_psr@psr-basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-bmg:          [SKIP][56] ([Intel XE#6703]) -> [SKIP][57] ([Intel XE#1435])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_setmode@basic-clone-single-crtc.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaling-mode:
    - shard-bmg:          [SKIP][58] ([Intel XE#6703]) -> [SKIP][59] ([Intel XE#6503])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@kms_sharpness_filter@invalid-filter-with-scaling-mode.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@kms_sharpness_filter@invalid-filter-with-scaling-mode.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][60] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][61] ([Intel XE#2426] / [Intel XE#5848])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@xe_eudebug@basic-exec-queues-enable:
    - shard-bmg:          [SKIP][62] ([Intel XE#6703]) -> [SKIP][63] ([Intel XE#7636]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_eudebug@basic-exec-queues-enable.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_eudebug@basic-exec-queues-enable.html

  * igt@xe_evict@evict-small-multi-queue:
    - shard-bmg:          [SKIP][64] ([Intel XE#6703]) -> [SKIP][65] ([Intel XE#7140])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_evict@evict-small-multi-queue.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_evict@evict-small-multi-queue.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue:
    - shard-bmg:          [SKIP][66] ([Intel XE#6703]) -> [SKIP][67] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-imm:
    - shard-bmg:          [SKIP][68] ([Intel XE#6703]) -> [SKIP][69] ([Intel XE#7136])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_exec_fault_mode@many-multi-queue-userptr-imm.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_exec_fault_mode@many-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-basic:
    - shard-bmg:          [SKIP][70] ([Intel XE#6703]) -> [SKIP][71] ([Intel XE#6874]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-basic.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_exec_multi_queue@many-queues-preempt-mode-basic.html

  * igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind:
    - shard-bmg:          [SKIP][72] ([Intel XE#6703]) -> [SKIP][73] ([Intel XE#7138])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-userptr-rebind.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6126
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7140
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7443
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776


Build changes
-------------

  * Linux: xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201 -> xe-pw-163785v4

  IGT_8863: 5b279a8b71dc1672099205a1a9e8135c7c7fadb5 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4920-da91cb4e6137507f74e4da41c39d0260b4cd1201: da91cb4e6137507f74e4da41c39d0260b4cd1201
  xe-pw-163785v4: 163785v4

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-163785v4/index.html

[-- Attachment #2: Type: text/html, Size: 24503 bytes --]

Re: [PATCH v4 5/8] drm/i915/display: move GLK clock gating init to display

[Jani Nikula]

On Mon, 20 Apr 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> Move the GLK-specific display clock gating programming into display
> intel_display_clock_gating.c, to remove more dependencies from i915 to
> display registers.
>
> Now that all remaining Gen9-family callers moved into display, we can
> move the shared Gen9 display clock gating helper into display and
> remove the old local helper from intel_clock_gating.c.
>
> Additionally, the SKL_DE_COMPRESSED_HASH_MODE programming was
> protected by HAS_LLC(), but that's incidental, because in Gen9
> platforms, only SKL and KBL, for which this workaround applies, have
> LLC().  In order not to use HAS_LLC() in display code, we can simply
> remove this check from the generic Gen9 function and move the
> SKL_DE_COMPRESSED_HASH_MODE programming to the KBL and SKL specific
> functions.

The macros in i915_pci.c are hard to read, but basically for gen 9 you
have GEN9_FEATURES and GEN9_LP_FEATURES.

GEN9_FEATURES "inherits" .has_llc = 1 through GEN7_FEATURES ->
G75_FEATURES -> GEN8_FEATURES -> GEN9_FEATURES. GEN9_LP_FEATURES does
not have it.

SKL, KBL, CFL, and CML use GEN9_FEATURES i.e. have LLC.

BXT, GLK use GEN9_LP_FEATURES i.e. don't have LLC.

CML and CFL share the functions, so this is a long-winded way of saying
that intel_display_cfl_init_clock_gating() also needs the
SKL_DE_COMPRESSED_HASH_MODE programming.


BR,
Jani.


>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>  .../i915/display/intel_display_clock_gating.c | 57 +++++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h |  1 +
>  drivers/gpu/drm/i915/intel_clock_gating.c     | 44 +-------------
>  3 files changed, 59 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> index 59041c807d6d..b2cb18478577 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.c
> @@ -6,11 +6,39 @@
>  #include <drm/intel/intel_gmd_misc_regs.h>
>  
>  #include "intel_de.h"
> +#include "intel_display.h"
>  #include "intel_display_clock_gating.h"
> +#include "intel_display_core.h"
>  #include "intel_display_regs.h"
>  
> +static void intel_display_gen9_init_clock_gating(struct intel_display *display)
> +{
> +	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> +	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> +
> +	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> +	intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> +
> +	/*
> +	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> +	 * Display WA #0859: skl,bxt,kbl,glk,cfl
> +	 */
> +	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> +}
> +
>  void intel_display_skl_init_clock_gating(struct intel_display *display)
>  {
> +	/*
> +	 * WaCompressedResourceDisplayNewHashMode:skl,kbl
> +	 * Display WA #0390: skl,kbl
> +	 *
> +	 * Must match Sampler, Pixel Back End, and Media. See
> +	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
> +	 */
> +	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> +
> +	intel_display_gen9_init_clock_gating(display);
> +
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:skl
>  	 * Display WA #0562: skl
> @@ -20,6 +48,17 @@ void intel_display_skl_init_clock_gating(struct intel_display *display)
>  
>  void intel_display_kbl_init_clock_gating(struct intel_display *display)
>  {
> +	/*
> +	 * WaCompressedResourceDisplayNewHashMode:skl,kbl
> +	 * Display WA #0390: skl,kbl
> +	 *
> +	 * Must match Sampler, Pixel Back End, and Media. See
> +	 * WaCompressedResourceSamplerPbeMediaNewHashMode.
> +	 */
> +	intel_de_rmw(display, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> +
> +	intel_display_gen9_init_clock_gating(display);
> +
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:kbl
>  	 * Display WA #0562: kbl
> @@ -29,6 +68,8 @@ void intel_display_kbl_init_clock_gating(struct intel_display *display)
>  
>  void intel_display_cfl_init_clock_gating(struct intel_display *display)
>  {
> +	intel_display_gen9_init_clock_gating(display);
> +
>  	/*
>  	 * WaFbcTurnOffFbcWatermark:cfl
>  	 * Display WA #0562: cfl
> @@ -38,6 +79,8 @@ void intel_display_cfl_init_clock_gating(struct intel_display *display)
>  
>  void intel_display_bxt_init_clock_gating(struct intel_display *display)
>  {
> +	intel_display_gen9_init_clock_gating(display);
> +
>  	/*
>  	 * Wa: Backlight PWM may stop in the asserted state, causing backlight
>  	 * to stay fully on.
> @@ -60,3 +103,17 @@ void intel_display_bxt_init_clock_gating(struct intel_display *display)
>  	 */
>  	intel_de_rmw(display, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>  }
> +
> +void intel_display_glk_init_clock_gating(struct intel_display *display)
> +{
> +	intel_display_gen9_init_clock_gating(display);
> +
> +	/*
> +	 * WaDisablePWMClockGating:glk
> +	 * Backlight PWM may stop in the asserted state, causing backlight
> +	 * to stay fully on.
> +	 */
> +	intel_de_write(display, GEN9_CLKGATE_DIS_0,
> +		       intel_de_read(display, GEN9_CLKGATE_DIS_0) |
> +		       PWM1_GATING_DIS | PWM2_GATING_DIS);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> index 6bc84a9a4342..a7784db9d97a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_clock_gating.h
> @@ -12,5 +12,6 @@ void intel_display_skl_init_clock_gating(struct intel_display *display);
>  void intel_display_kbl_init_clock_gating(struct intel_display *display);
>  void intel_display_cfl_init_clock_gating(struct intel_display *display);
>  void intel_display_bxt_init_clock_gating(struct intel_display *display);
> +void intel_display_glk_init_clock_gating(struct intel_display *display);
>  
>  #endif /* __INTEL_DISPLAY_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index a9efa5ce8f6a..96fe16753e58 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -49,36 +49,8 @@ struct drm_i915_clock_gating_funcs {
>  	void (*init_clock_gating)(struct drm_i915_private *i915);
>  };
>  
> -static void gen9_init_clock_gating(struct drm_i915_private *i915)
> -{
> -	if (HAS_LLC(i915)) {
> -		/*
> -		 * WaCompressedResourceDisplayNewHashMode:skl,kbl
> -		 * Display WA #0390: skl,kbl
> -		 *
> -		 * Must match Sampler, Pixel Back End, and Media. See
> -		 * WaCompressedResourceSamplerPbeMediaNewHashMode.
> -		 */
> -		intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> -	}
> -
> -	/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> -	intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> -
> -	/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> -	intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> -
> -	/*
> -	 * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> -	 * Display WA #0859: skl,bxt,kbl,glk,cfl
> -	 */
> -	intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> -}
> -
>  static void bxt_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
>  	/* WaDisableSDEUnitClockGating:bxt */
>  	intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
> @@ -93,16 +65,7 @@ static void bxt_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void glk_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
> -	/*
> -	 * WaDisablePWMClockGating:glk
> -	 * Backlight PWM may stop in the asserted state, causing backlight
> -	 * to stay fully on.
> -	 */
> -	intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
> -			   intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
> -			   PWM1_GATING_DIS | PWM2_GATING_DIS);
> +	intel_display_glk_init_clock_gating(i915->display);
>  }
>  
>  static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> @@ -282,7 +245,6 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
>  static void cfl_init_clock_gating(struct drm_i915_private *i915)
>  {
>  	intel_pch_init_clock_gating(i915->display);
> -	gen9_init_clock_gating(i915);
>  
>  	/* WAC6entrylatency:cfl */
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
> @@ -292,8 +254,6 @@ static void cfl_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void kbl_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
>  	/* WAC6entrylatency:kbl */
>  	intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>  
> @@ -312,8 +272,6 @@ static void kbl_init_clock_gating(struct drm_i915_private *i915)
>  
>  static void skl_init_clock_gating(struct drm_i915_private *i915)
>  {
> -	gen9_init_clock_gating(i915);
> -
>  	/* WaDisableDopClockGating:skl */
>  	intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
>  			 GEN7_DOP_CLOCK_GATE_ENABLE, 0);

-- 
Jani Nikula, Intel

Re: [PATCH v4 0/8] drm/i915: move more display dependencies from i915

[Jani Nikula]

On Mon, 20 Apr 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> This series continues my work of refactoring the clock gating
> initialization, so that i915 doesn't do display-specific stuff.
>
> With this, all register dependencies should be gone.
>
> Changes in v4:
> 	* Explain why HAS_LLC() is not needed anymore (Jani);
> 	* Replace intel_display_core.h include with intel_pch.h (Jani);
>
> Please review.

There's the one omission in patch 5 that I pointed out that needs to be
fixed.

Other than that, this is

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

I do have a nagging feeling that further refactoring will be needed, as
this introduces a plethora of new display interfaces i915 core needs to
call, and we should work to minimize that surface. However, this is good
stuff for moving the display stuff out of i915 core, so let's roll with
this.

A minor nit for further reference. If you can, please try to avoid
combining code movement and other changes. Reviewing pure code movement
with 'git show --color-moved' is quick. Reviewing other mechanical
changes with 'git show --color-words' is also quick. Unfortunately,
having code movement and other inline changes in one breaks both
approaches, and you have to fall back to more manual review.

BR,
Jani.


>
> Cheers,
> Luca.
>
>
> Luca Coelho (8):
>   drm/i915: move SKL clock gating init to display
>   drm/i915: move KBL clock gating init to display
>   drm/i915/display: move CFL clock gating init to display
>   drm/i915/display: move BXT clock gating init to display
>   drm/i915/display: move GLK clock gating init to display
>   drm/i915/display: move HSW and BDW clock gating init to display
>   drm/i915/display: move pre-HSW clock gating init to display
>   drm/i915: remove HAS_PCH_NOP() dependency from clock gating
>
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  .../i915/display/intel_display_clock_gating.c | 255 ++++++++++++++++++
>  .../i915/display/intel_display_clock_gating.h |  27 ++
>  .../gpu/drm/i915/display/intel_display_regs.h |  31 +++
>  drivers/gpu/drm/i915/i915_reg.h               |  31 ---
>  drivers/gpu/drm/i915/intel_clock_gating.c     | 226 ++--------------
>  6 files changed, 331 insertions(+), 240 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_display_clock_gating.h

-- 
Jani Nikula, Intel

Re: [PATCH v4 5/8] drm/i915/display: move GLK clock gating init to display

[Luca Coelho]

On Mon, 2026-04-27 at 12:50 +0300, Jani Nikula wrote:
> On Mon, 20 Apr 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> > Move the GLK-specific display clock gating programming into display
> > intel_display_clock_gating.c, to remove more dependencies from i915 to
> > display registers.
> > 
> > Now that all remaining Gen9-family callers moved into display, we can
> > move the shared Gen9 display clock gating helper into display and
> > remove the old local helper from intel_clock_gating.c.
> > 
> > Additionally, the SKL_DE_COMPRESSED_HASH_MODE programming was
> > protected by HAS_LLC(), but that's incidental, because in Gen9
> > platforms, only SKL and KBL, for which this workaround applies, have
> > LLC().  In order not to use HAS_LLC() in display code, we can simply
> > remove this check from the generic Gen9 function and move the
> > SKL_DE_COMPRESSED_HASH_MODE programming to the KBL and SKL specific
> > functions.
> 
> The macros in i915_pci.c are hard to read, but basically for gen 9 you
> have GEN9_FEATURES and GEN9_LP_FEATURES.
> 
> GEN9_FEATURES "inherits" .has_llc = 1 through GEN7_FEATURES ->
> G75_FEATURES -> GEN8_FEATURES -> GEN9_FEATURES. GEN9_LP_FEATURES does
> not have it.
> 
> SKL, KBL, CFL, and CML use GEN9_FEATURES i.e. have LLC.
> 
> BXT, GLK use GEN9_LP_FEATURES i.e. don't have LLC.
> 
> CML and CFL share the functions, so this is a long-winded way of saying
> that intel_display_cfl_init_clock_gating() also needs the
> SKL_DE_COMPRESSED_HASH_MODE programming.

Okay, makes sense.  The comment for the workaround only mentions skl
and kbl, so I guess the comment needs to be modified slightly too.

But I wonder if this was a mistake in the implementation (using
HAS_LLC() and not checking the platform), or in the specification for
the workaround, which apparently only says SKL and KBL...

In any case, the goal of this series is not to change anything
functionally, so if doing this for CFL/CML is a bug, my series won't
change that.

--
Cheers,
Luca.

Re: [PATCH v4 0/8] drm/i915: move more display dependencies from i915

[Luca Coelho]

On Mon, 2026-04-27 at 13:06 +0300, Jani Nikula wrote:
> On Mon, 20 Apr 2026, Luca Coelho <luciano.coelho@intel.com> wrote:
> > This series continues my work of refactoring the clock gating
> > initialization, so that i915 doesn't do display-specific stuff.
> > 
> > With this, all register dependencies should be gone.
> > 
> > Changes in v4:
> > 	* Explain why HAS_LLC() is not needed anymore (Jani);
> > 	* Replace intel_display_core.h include with intel_pch.h (Jani);
> > 
> > Please review.
> 
> There's the one omission in patch 5 that I pointed out that needs to be
> fixed.
> 
> Other than that, this is
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Thanks for the review!


> I do have a nagging feeling that further refactoring will be needed, as
> this introduces a plethora of new display interfaces i915 core needs to
> call, and we should work to minimize that surface. However, this is good
> stuff for moving the display stuff out of i915 core, so let's roll with
> this.

Yeah, the main problem is that the calls to platform specific things
were all over, sometimes in the beginning, sometimes in the middle and
sometimes in the end of the flows.  Ville already mentioned that most
of these are probably not order-sensitive, so we could generalize the
implementation and reduce the number of interfaces.

I didn't want to change the order of these workarounds in this series.
Now that the functions are inside the display code, we can start make
some functional changes in a more isolated way.


> A minor nit for further reference. If you can, please try to avoid
> combining code movement and other changes. Reviewing pure code movement
> with 'git show --color-moved' is quick. Reviewing other mechanical
> changes with 'git show --color-words' is also quick. Unfortunately,
> having code movement and other inline changes in one breaks both
> approaches, and you have to fall back to more manual review.

Sorry for that.  I've been nagging about the same thing many times in
the past myself, so it's silly I've done it too.  I've been moving this
code forth and back quite a few times, and ended up mixing moves from
actual changes. :(

--
Cheers,
Luca.