* [PATCH v2 0/9] Handle non-fatal errors routed via IRQ
@ 2026-10-26 6:04 Riana Tauro
2026-10-26 6:05 ` [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling Riana Tauro
` (11 more replies)
0 siblings, 12 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:04 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Implement wa_14028434957 to route non-fatal errors via IRQ and trigger
SBR for all fatal errors.
Process, log and recover non-fatal errors routed via direct IRQ.
Double-bit ECC errors are also reported as non-fatal errors. Process and
offline pages for user bos. Critical Bo's require a SBR to recover.
Wedge the device with bus reset.
Race Case Handling:
There is a potential race between errors reported via AER that require
an SBR (Secondary Bus Reset) and non-fatal errors still being processed
by the worker. Since a reset is imminent once AER reports such an
error, the worker processing non-fatal errors is flushed and disabled.
There is also a possibility of the AER handler running first, in which
case firmware reports all pending errors — including non-fatal ones —
as a single response, since it maintains a single queue for all error
types. Skip handling of double-bit ECC errors in that case, since the
SBR already clears the offlined pages on reload and firmware drops them
from its queue once read, so offlining them here would be unnecessary
and could leave the queue and the soft-offlined pages list out of sync.
Rev2: Handle Race between AER
Use WA number
Raag Jadav (1):
drm/xe/hw_error: Initialize hw_error_work per tile
Riana Tauro (7):
drm/xe/hw_error: Reuse CSC worker for generic error handling
drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
drm/xe/ras: Treat non-fatal PCIe errors as recovered
drm/xe/pci: Add upstream switch port lookup helper
drm/xe/xe_ras: Disable hw error worker for uncorrectable internal AER
drm/xe/xe_ras: Trigger SBR for all errors reported via AER
drm/xe/ras: Skip double-bit ECC page offlining on AER path
Varun Gupta (1):
drm/xe: Add wa_14028434957 to Graphics Version 35.11
drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 +
drivers/gpu/drm/xe/xe_hw_error.c | 69 ++++++++++++++++++----
drivers/gpu/drm/xe/xe_hw_error.h | 1 +
drivers/gpu/drm/xe/xe_pci.c | 23 ++++++++
drivers/gpu/drm/xe/xe_pci.h | 1 +
drivers/gpu/drm/xe/xe_pci_error.c | 33 +++++++++++
drivers/gpu/drm/xe/xe_ras.c | 72 ++++++++++++++++-------
drivers/gpu/drm/xe/xe_ras.h | 1 +
drivers/gpu/drm/xe/xe_ras_types.h | 2 +
drivers/gpu/drm/xe/xe_tile_types.h | 6 +-
10 files changed, 176 insertions(+), 33 deletions(-)
--
2.47.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-27 13:01 ` Mallesh, Koujalagi
2026-10-26 6:05 ` [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
` (10 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Convert the CSC hardware error worker to a delayed work item so it
can be reused for generic hardware error handling in later patches.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_hw_error.c | 10 +++++-----
drivers/gpu/drm/xe/xe_tile_types.h | 6 +++---
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index ac720710c8e8..41ddd997478b 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -166,9 +166,9 @@ static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) == XE_RAS_REG_SIZE);
pvc_master_local_fatal_err_reg : \
pvc_master_local_nonfatal_err_reg)
-static void csc_hw_error_work(struct work_struct *work)
+static void hw_error_work(struct work_struct *work)
{
- struct xe_tile *tile = container_of(work, typeof(*tile), csc_hw_error_work);
+ struct xe_tile *tile = container_of(work, typeof(*tile), hw_error_work.work);
struct xe_device *xe = tile_to_xe(tile);
guard(xe_pm_runtime)(xe);
@@ -204,7 +204,7 @@ static void csc_hw_error_handler(struct xe_tile *tile, const enum hardware_error
hec_uncorrected_fw_errors[err_bit], severity_str,
err_bit);
- schedule_work(&tile->csc_hw_error_work);
+ schedule_delayed_work(&tile->hw_error_work, 0);
}
}
@@ -513,7 +513,7 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
enum hardware_error hw_err;
if (xe_fault_csc_hw_error())
- schedule_work(&tile->csc_hw_error_work);
+ schedule_delayed_work(&tile->hw_error_work, 0);
for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
if (master_ctl & ERROR_IRQ(hw_err))
@@ -551,7 +551,7 @@ void xe_hw_error_init(struct xe_device *xe)
if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
return;
- INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
+ INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
process_hw_errors(xe);
}
diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
index e1368c04846a..0f41738635c5 100644
--- a/drivers/gpu/drm/xe/xe_tile_types.h
+++ b/drivers/gpu/drm/xe/xe_tile_types.h
@@ -7,7 +7,7 @@
#define _XE_TILE_TYPES_H_
#include <linux/mutex_types.h>
-#include <linux/workqueue_types.h>
+#include <linux/workqueue.h>
#include "xe_lmtt_types.h"
#include "xe_memirq_types.h"
@@ -118,8 +118,8 @@ struct xe_tile {
/** @memirq: Memory Based Interrupts. */
struct xe_memirq memirq;
- /** @csc_hw_error_work: worker to report CSC HW errors */
- struct work_struct csc_hw_error_work;
+ /** @hw_error_work: delayed work to handle HW errors */
+ struct delayed_work hw_error_work;
/** @pcode: tile's PCODE */
struct {
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
2026-10-26 6:05 ` [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-26 9:37 ` sashiko-bot
` (2 more replies)
2026-10-26 6:05 ` [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11 Riana Tauro
` (9 subsequent siblings)
11 siblings, 3 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
From: Raag Jadav <raag.jadav@intel.com>
Since hw_error_work is now being reused generically, initialize it per tile
so that we don't hit uninitialized work for non-root tile. While at it,
disable hw_error_work on fini to prevent UAF during unwind.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_hw_error.c | 24 ++++++++++++++++++++++--
drivers/gpu/drm/xe/xe_hw_error.h | 1 +
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index 41ddd997478b..f7799c3c08aa 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -537,6 +537,23 @@ static void process_hw_errors(struct xe_device *xe)
}
}
+/**
+ * xe_hw_error_work_disable - Disable hw error work
+ * @arg: xe device instance
+ *
+ * This function disables the delayed work for hardware error handling
+ * for all tiles.
+ */
+void xe_hw_error_work_disable(void *arg)
+{
+ struct xe_device *xe = arg;
+ struct xe_tile *tile;
+ u8 id;
+
+ for_each_tile(tile, xe, id)
+ disable_delayed_work_sync(&tile->hw_error_work);
+}
+
/**
* xe_hw_error_init - Initialize hw errors
* @xe: xe device instance
@@ -546,12 +563,15 @@ static void process_hw_errors(struct xe_device *xe)
*/
void xe_hw_error_init(struct xe_device *xe)
{
- struct xe_tile *tile = xe_device_get_root_tile(xe);
+ struct xe_tile *tile;
+ u8 id;
if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
return;
- INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
+ for_each_tile(tile, xe, id)
+ INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
process_hw_errors(xe);
+ devm_add_action_or_reset(xe->drm.dev, xe_hw_error_work_disable, xe);
}
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index 5e3a11424108..c2c0bfa6d9f9 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -12,4 +12,5 @@ struct xe_device;
void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
void xe_hw_error_init(struct xe_device *xe);
+void xe_hw_error_work_disable(void *arg);
#endif
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
2026-10-26 6:05 ` [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling Riana Tauro
2026-10-26 6:05 ` [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-28 6:16 ` Mallesh, Koujalagi
2026-10-28 14:19 ` Gustavo Sousa
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
` (8 subsequent siblings)
11 siblings, 2 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay, Varun Gupta
From: Varun Gupta <varun.gupta@intel.com>
Add wa_14028434957 for Graphics Version 35.11 to the table.
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Varun Gupta <varun.gupta@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
index d8dc41851425..36b2567994db 100644
--- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
@@ -7,3 +7,4 @@
14026633728 PLATFORM(CRESCENTISLAND)
14026746987 PLATFORM(CRESCENTISLAND)
14026779378 PLATFORM(CRESCENTISLAND)
+14028434957 PLATFORM(CRESCENTISLAND)
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (2 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11 Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-26 10:09 ` sashiko-bot
` (3 more replies)
2026-10-26 6:05 ` [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered Riana Tauro
` (7 subsequent siblings)
11 siblings, 4 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Process, log and recover non-fatal errors routed via direct IRQ.
Double-bit ecc errors belong to non-fatal error category and are reported
via irq. For pages that belong to critical BO, wedge the device with
bus-reset as the recovery action.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_hw_error.c | 37 ++++++++++++++++++++++++++++----
drivers/gpu/drm/xe/xe_ras.c | 9 +++++++-
2 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
index f7799c3c08aa..269ce6a19a80 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.c
+++ b/drivers/gpu/drm/xe/xe_hw_error.c
@@ -5,6 +5,8 @@
#include <linux/bitmap.h>
+#include <generated/xe_device_wa_oob.h>
+
#include "regs/xe_gsc_regs.h"
#include "regs/xe_hw_error_regs.h"
#include "regs/xe_irq_regs.h"
@@ -15,7 +17,9 @@
#include "xe_hw_error.h"
#include "xe_mmio.h"
#include "xe_pm.h"
+#include "xe_ras.h"
#include "xe_survivability_mode.h"
+#include "xe_wa.h"
#define GT_HW_ERROR_MAX_ERR_BITS 16
#define HEC_UNCORR_FW_ERR_BITS 4
@@ -166,12 +170,36 @@ static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) == XE_RAS_REG_SIZE);
pvc_master_local_fatal_err_reg : \
pvc_master_local_nonfatal_err_reg)
+static const char *hw_err_to_str(const enum hardware_error hw_err)
+{
+ switch (hw_err) {
+ case HARDWARE_ERROR_CORRECTABLE:
+ return "Correctable";
+ case HARDWARE_ERROR_NONFATAL:
+ return "Non-Fatal";
+ case HARDWARE_ERROR_FATAL:
+ return "Fatal";
+ default:
+ return "Unknown";
+ }
+}
+
static void hw_error_work(struct work_struct *work)
{
struct xe_tile *tile = container_of(work, typeof(*tile), hw_error_work.work);
struct xe_device *xe = tile_to_xe(tile);
guard(xe_pm_runtime)(xe);
+
+ if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
+ /* If the device is in reset in AER path, skip processing hardware errors */
+ if (xe_device_is_in_reset(xe))
+ return;
+
+ xe_ras_process_errors(xe);
+ return;
+ }
+
xe_survivability_mode_runtime_enable(xe);
}
@@ -433,12 +461,13 @@ static void hw_error_source_handler(struct xe_tile *tile, const enum hardware_er
return;
/*
- * Hardware errors are reported through System Controller on the platforms that
- * support it, and never routed as direct IRQ to SGUnit. So we should never be
- * here for those platforms.
+ * Non fatal errors are routed as a direct IRQ on platforms that support
+ * system controller.
*/
if (xe->info.has_sysctrl) {
- drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error routing\n");
+ drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n", hw_err_to_str(hw_err),
+ severity_str);
+ schedule_delayed_work(&tile->hw_error_work, msecs_to_jiffies(MSEC_PER_SEC));
return;
}
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index db3cbc186a51..e6a0ee468b17 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -628,8 +628,15 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
break;
case XE_RAS_MEMORY_DB_ECC:
ret = handle_page_offline(xe, info->sw_address, true);
- if (ret)
+ /*
+ * Double-bit ECC errors are non-fatal errors and are reported via IRQ.
+ * Wedge the device with a bus reset for errors that require SBR to recover.
+ * TODO: Trigger SBR using pci_reset_bus
+ */
+ if (ret) {
+ xe_wedge_declare(xe, DRM_WEDGE_RECOVERY_BUS_RESET);
return XE_RAS_RECOVERY_ACTION_RESET;
+ }
break;
default:
return XE_RAS_RECOVERY_ACTION_RESET;
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (3 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-28 9:24 ` Mallesh, Koujalagi
2026-10-26 6:05 ` [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper Riana Tauro
` (6 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
On systems lacking RAS capability, only PCIe errors are reported, via
AER, not device errors. Non-fatal PCIe errors reported at the Upstream
Switch Port (USP) have no impact on link or device state, so treat
them as recovered without requiring a secondary bus reset (SBR).
Fixes: 25913a062cd4 ("drm/xe/xe_ras: Add support for uncorrectable core-compute errors")
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_ras.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index e6a0ee468b17..2b1a7cb01b0d 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -747,7 +747,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
}
if (!xe->info.has_sysctrl)
- return XE_RAS_RECOVERY_ACTION_RESET;
+ return XE_RAS_RECOVERY_ACTION_RECOVERED;
BUILD_BUG_ON(BITS_PER_TYPE(sent) < XE_RAS_COMP_MAX);
/* Default action */
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (4 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-28 9:45 ` Mallesh, Koujalagi
2026-10-28 16:19 ` Andi Shyti
2026-10-26 6:05 ` [PATCH v2 7/9] drm/xe/xe_ras: Disable hw error worker when AER handling is in progress Riana Tauro
` (5 subsequent siblings)
11 siblings, 2 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Move the USP lookup logic out of RAS code and into the PCI
layer so it can be reused by other callers.
No functional change.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 23 +++++++++++++++++++++++
drivers/gpu/drm/xe/xe_pci.h | 1 +
drivers/gpu/drm/xe/xe_ras.c | 19 ++-----------------
3 files changed, 26 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 0c13eb901aa7..a9b8e65dff07 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -1521,6 +1521,29 @@ struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev)
return to_xe_device(drm);
}
+/**
+ * xe_pci_get_usp_dev() - Get the upstream switch port device.
+ * @pdev: pci device of SGunit
+ *
+ * Device Hierarchy:
+ * Upstream Switch Port (USP) --> Virtual Switch Port (VSP) --> SGunit (GPU endpoint)
+ *
+ * The function traverses the PCI device hierarchy to find the upstream switch port
+ * device.
+ *
+ * Return: pointer to USP &pci_dev, NULL otherwise.
+ */
+struct pci_dev *xe_pci_get_usp_dev(struct pci_dev *pdev)
+{
+ struct pci_dev *vsp;
+
+ vsp = pci_upstream_bridge(pdev);
+ if (!vsp)
+ return NULL;
+
+ return pci_upstream_bridge(vsp);
+}
+
int xe_register_pci_driver(void)
{
return pci_register_driver(&xe_pci_driver);
diff --git a/drivers/gpu/drm/xe/xe_pci.h b/drivers/gpu/drm/xe/xe_pci.h
index 11bcc5fe2c5b..3dc3539c3970 100644
--- a/drivers/gpu/drm/xe/xe_pci.h
+++ b/drivers/gpu/drm/xe/xe_pci.h
@@ -11,5 +11,6 @@ struct pci_dev;
int xe_register_pci_driver(void);
void xe_unregister_pci_driver(void);
struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev);
+struct pci_dev *xe_pci_get_usp_dev(struct pci_dev *pdev);
#endif
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 2b1a7cb01b0d..a91c3d924e8c 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -10,6 +10,7 @@
#include "xe_device.h"
#include "xe_drm_ras.h"
#include "xe_log.h"
+#include "xe_pci.h"
#include "xe_pm.h"
#include "xe_printk.h"
#include "xe_ras.h"
@@ -462,22 +463,6 @@ static void get_offline_list(struct xe_device *xe)
&response, sizeof(response), &response.common, false);
}
-static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
-{
- struct pci_dev *vsp;
-
- /*
- * Device Hierarchy:
- *
- * Upstream Switch Port (USP) --> Virtual Switch Port (VSP) --> SGunit (GPU endpoint)
- */
- vsp = pci_upstream_bridge(pdev);
- if (!vsp)
- return NULL;
-
- return pci_upstream_bridge(vsp);
-}
-
static void ras_usp_aer_init(struct xe_device *xe)
{
struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
@@ -485,7 +470,7 @@ static void ras_usp_aer_init(struct xe_device *xe)
u16 aer_cap;
u32 status;
- usp = find_usp_dev(pdev);
+ usp = xe_pci_get_usp_dev(pdev);
if (!usp)
return;
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 7/9] drm/xe/xe_ras: Disable hw error worker when AER handling is in progress
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (5 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-26 10:32 ` sashiko-bot
2026-10-26 6:05 ` [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors Riana Tauro
` (4 subsequent siblings)
11 siblings, 1 reply; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
An uncorrectable internal AER error event is triggered for device fatal
errors. If non-fatal error processing is in progress, flush and disable
the worker to prevent further processing, as a reset is imminent.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_pci_error.c | 33 +++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.c | 12 +++++++++++
drivers/gpu/drm/xe/xe_ras.h | 1 +
drivers/gpu/drm/xe/xe_ras_types.h | 2 ++
4 files changed, 48 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci_error.c b/drivers/gpu/drm/xe/xe_pci_error.c
index 9bf0da3a3d15..b27f8a0f1b17 100644
--- a/drivers/gpu/drm/xe/xe_pci_error.c
+++ b/drivers/gpu/drm/xe/xe_pci_error.c
@@ -5,14 +5,18 @@
#include <linux/pci.h>
+#include <generated/xe_device_wa_oob.h>
+
#include "xe_device.h"
#include "xe_gt.h"
+#include "xe_hw_error.h"
#include "xe_log.h"
#include "xe_pci.h"
#include "xe_pm.h"
#include "xe_printk.h"
#include "xe_ras.h"
#include "xe_survivability_mode.h"
+#include "xe_wa.h"
#include "xe_wedge.h"
static void prepare_device_for_reset(struct pci_dev *pdev)
@@ -54,6 +58,26 @@ static pci_ers_result_t ras_action_to_pci_result(struct pci_dev *pdev, u8 action
}
}
+static bool is_aer_internal_error(struct pci_dev *pdev)
+{
+ struct pci_dev *usp;
+ u16 aer_cap;
+ u32 status;
+
+ usp = xe_pci_get_usp_dev(pdev);
+ if (!usp)
+ return false;
+
+ aer_cap = pci_find_ext_capability(usp, PCI_EXT_CAP_ID_ERR);
+ if (!aer_cap) {
+ dev_warn(&usp->dev, "AER capability unavailable\n");
+ return false;
+ }
+
+ pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_STATUS, &status);
+ return status & PCI_ERR_UNC_INTN;
+}
+
static pci_ers_result_t xe_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
{
struct xe_device *xe = pdev_to_xe_device(pdev);
@@ -67,6 +91,15 @@ static pci_ers_result_t xe_pci_error_detected(struct pci_dev *pdev, pci_channel_
if (xe_survivability_mode_is_boot_enabled(xe) || xe_wedged(xe))
return PCI_ERS_RESULT_DISCONNECT;
+ /*
+ * If non-fatal error processing is in progress when uncorrectable internal error occurs,
+ * flush and disable the worker to prevent further processing, as a reset is imminent.
+ */
+ if (XE_DEVICE_WA(xe, 14028434957) && is_aer_internal_error(pdev)) {
+ xe_ras_set_aer_path(xe, true);
+ xe_hw_error_work_disable(xe);
+ }
+
switch (state) {
case pci_channel_io_normal:
return PCI_ERS_RESULT_CAN_RECOVER;
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index a91c3d924e8c..42fb24366a6b 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -1170,6 +1170,18 @@ u32 xe_ras_get_max_pages(struct xe_device *xe)
return xe->ras.state.max_pages;
}
+/**
+ * xe_ras_set_aer_path - Set whether errors are processed via the AER path
+ * @xe: xe device instance
+ * @aer_path: true if errors are processed via the AER path, false if via irq
+ *
+ * Set if errors are processed via AER
+ */
+void xe_ras_set_aer_path(struct xe_device *xe, bool aer_path)
+{
+ xe->ras.state.aer_path = aer_path;
+}
+
/**
* xe_ras_init - Initialize Xe RAS
* @xe: xe device instance
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index 1b358c7d040f..06518226db85 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -23,5 +23,6 @@ int xe_ras_init(struct xe_device *xe);
enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
u32 xe_ras_get_max_pages(struct xe_device *xe);
+void xe_ras_set_aer_path(struct xe_device *xe, bool aer_path);
#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index a86f9d2b8c92..558df12bcd9b 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -414,6 +414,8 @@ struct xe_ras_set_health_response {
* struct xe_ras_state - RAS device and firmware state
*/
struct xe_ras_state {
+ /** @aer_path: True if errors are processed via the AER path, false if via irq */
+ bool aer_path;
/** @disable_vram_page_offline: cached configfs policy, immutable after init */
bool disable_vram_page_offline;
/** @max_pages: Total number of pages that can be stored by firmware */
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (6 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 7/9] drm/xe/xe_ras: Disable hw error worker when AER handling is in progress Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-28 16:25 ` Andi Shyti
2026-10-29 5:18 ` Mallesh, Koujalagi
2026-10-26 6:05 ` [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path Riana Tauro
` (3 subsequent siblings)
11 siblings, 2 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
There are two paths for error reporting. Uncorrectable non-fatal device
errors are reported via direct IRQ. Uncorrectable device fatal errors are
downgraded as non fatal uncorrectable internal errors and reported as AER.
Set the default action to Secondary Bus Reset (SBR) for device fatal
uncorrectable errors.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_ras.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 42fb24366a6b..3b07b2fa8cd4 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -3,6 +3,8 @@
* Copyright © 2026 Intel Corporation
*/
+#include <generated/xe_device_wa_oob.h>
+
#include "xe_assert.h"
#include "xe_bo.h"
#include "xe_configfs.h"
@@ -20,6 +22,7 @@
#include "xe_sysctrl_mailbox.h"
#include "xe_sysctrl_mailbox_types.h"
#include "xe_ttm_vram_mgr.h"
+#include "xe_wa.h"
#include "xe_wedge.h"
/* Any non-null entry marks the page as offlined by firmware */
@@ -718,6 +721,7 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
{
struct xe_sysctrl_mailbox_command command = {0};
+ struct xe_ras_state *ras = &xe->ras.state;
enum xe_ras_recovery_action final_action;
u32 remaining = XE_SYSCTRL_FLOOD_LIMIT;
struct xe_ras_get_soc_error response;
@@ -735,9 +739,16 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
return XE_RAS_RECOVERY_ACTION_RECOVERED;
BUILD_BUG_ON(BITS_PER_TYPE(sent) < XE_RAS_COMP_MAX);
- /* Default action */
+ /* Default action for PCIe bus errors */
final_action = XE_RAS_RECOVERY_ACTION_RECOVERED;
+ /*
+ * Device fatal errors are downgraded to non-fatal and reported as an uncorrectable
+ * internal error. Set the default action to reset.
+ */
+ if (ras->aer_path && XE_DEVICE_WA(xe, 14028434957))
+ final_action = XE_RAS_RECOVERY_ACTION_RESET;
+
xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_SOC_ERROR,
NULL, 0, &response, sizeof(response));
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (7 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors Riana Tauro
@ 2026-10-26 6:05 ` Riana Tauro
2026-10-28 16:26 ` Andi Shyti
2026-10-29 5:25 ` Mallesh, Koujalagi
2026-10-26 6:30 ` ✓ CI.KUnit: success for Handle non-fatal errors routed via IRQ (rev2) Patchwork
` (2 subsequent siblings)
11 siblings, 2 replies; 42+ messages in thread
From: Riana Tauro @ 2026-10-26 6:05 UTC (permalink / raw)
To: intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Device fatal errors trigger AER, which can race with non-fatal
double-bit ECC errors reported via IRQ. If the AER PCI error handler
runs first, it receives all errors as a single response from the
system controller firmware, which can include the double-bit ECC errors.
Handling these on the AER path leads to unnecessary page offlining,
since an SBR clears the offlined pages on reload and firmware drops them
from its queue once read. Skip double-bit ECC handling when on the AER
path to avoid this.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_ras.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 3b07b2fa8cd4..22ecca10b7a2 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -598,6 +598,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
{
struct xe_ras_memory_error *info = (void *)arr->details;
+ struct xe_ras_state *ras = &xe->ras.state;
int ret;
/*
@@ -615,9 +616,25 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
xe_info(xe, "[RAS]: Data parity error detected\n");
break;
case XE_RAS_MEMORY_DB_ECC:
- ret = handle_page_offline(xe, info->sw_address, true);
/*
* Double-bit ECC errors are non-fatal errors and are reported via IRQ.
+ * On a race between AER for device fatal errors and non-fatal double-bit ECC
+ * errors, if AER pci error handlers execute first it will get all errors as
+ * a single response from system controller, which can include the double-bit
+ * ECC errors. This leads to unnecessary offlining of pages, since an SBR clears
+ * them on reload and firmware drops them from its queue once read.
+ * Skip handling of double-bit ECC errors on the AER path to avoid this.
+ *
+ * TODO: Remove this check once AER handling is optimized to retain soft
+ * offlined pages.
+ */
+ if (ras->aer_path) {
+ xe_info(xe, "[RAS]: Skipping double-bit ECC error handling on AER path\n");
+ break;
+ }
+
+ ret = handle_page_offline(xe, info->sw_address, true);
+ /*
* Wedge the device with a bus reset for errors that require SBR to recover.
* TODO: Trigger SBR using pci_reset_bus
*/
--
2.47.1
^ permalink raw reply related [flat|nested] 42+ messages in thread
* ✓ CI.KUnit: success for Handle non-fatal errors routed via IRQ (rev2)
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (8 preceding siblings ...)
2026-10-26 6:05 ` [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path Riana Tauro
@ 2026-10-26 6:30 ` Patchwork
2026-10-26 7:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-26 8:55 ` ✗ Xe.CI.FULL: failure " Patchwork
11 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2026-10-26 6:30 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
== Series Details ==
Series: Handle non-fatal errors routed via IRQ (rev2)
URL : https://patchwork.freedesktop.org/series/173001/
State : success
== Summary ==
+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[06:28:26] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:28:31] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:28:51] Starting KUnit Kernel (1/1)...
[06:28:51] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:28:51] ================= gpu_buddy (14 subtests) ==================
[06:28:51] [PASSED] gpu_test_buddy_alloc_limit
[06:28:51] [PASSED] gpu_test_buddy_alloc_optimistic
[06:28:51] [PASSED] gpu_test_buddy_alloc_pessimistic
[06:28:51] [PASSED] gpu_test_buddy_alloc_pathological
[06:28:51] [PASSED] gpu_test_buddy_alloc_contiguous
[06:28:51] [PASSED] gpu_test_buddy_alloc_clear
[06:28:51] [PASSED] gpu_test_buddy_alloc_range
[06:28:52] [PASSED] gpu_test_buddy_alloc_range_bias
[06:28:52] [PASSED] gpu_test_buddy_fragmentation_performance
[06:28:53] [PASSED] gpu_test_buddy_dirty_tracker_performance
[06:28:53] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[06:28:53] [PASSED] gpu_test_buddy_offset_aligned_allocation
[06:28:53] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[06:28:53] [PASSED] gpu_test_buddy_addr_to_block
[06:28:53] ==================== [PASSED] gpu_buddy ====================
[06:28:53] ============================================================
[06:28:53] Testing complete. Ran 14 tests: passed: 14
[06:28:53] Elapsed time: 26.726s total, 4.479s configuring, 20.380s building, 1.807s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[06:28:53] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:28:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:29:34] Starting KUnit Kernel (1/1)...
[06:29:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:29:34] ================== guc_buf (11 subtests) ===================
[06:29:34] [PASSED] test_smallest
[06:29:34] [PASSED] test_largest
[06:29:34] [PASSED] test_granular
[06:29:34] [PASSED] test_unique
[06:29:34] [PASSED] test_overlap
[06:29:34] [PASSED] test_reusable
[06:29:34] [PASSED] test_too_big
[06:29:34] [PASSED] test_flush
[06:29:34] [PASSED] test_lookup
[06:29:34] [PASSED] test_data
[06:29:34] [PASSED] test_class
[06:29:34] ===================== [PASSED] guc_buf =====================
[06:29:34] =================== guc_dbm (7 subtests) ===================
[06:29:34] [PASSED] test_empty
[06:29:34] [PASSED] test_default
[06:29:34] ======================== test_size ========================
[06:29:34] [PASSED] 4
[06:29:34] [PASSED] 8
[06:29:34] [PASSED] 32
[06:29:34] [PASSED] 256
[06:29:34] ==================== [PASSED] test_size ====================
[06:29:34] ======================= test_reuse ========================
[06:29:34] [PASSED] 4
[06:29:34] [PASSED] 8
[06:29:34] [PASSED] 32
[06:29:34] [PASSED] 256
[06:29:34] =================== [PASSED] test_reuse ====================
[06:29:34] =================== test_range_overlap ====================
[06:29:34] [PASSED] 4
[06:29:34] [PASSED] 8
[06:29:34] [PASSED] 32
[06:29:34] [PASSED] 256
[06:29:34] =============== [PASSED] test_range_overlap ================
[06:29:34] =================== test_range_compact ====================
[06:29:34] [PASSED] 4
[06:29:34] [PASSED] 8
[06:29:34] [PASSED] 32
[06:29:34] [PASSED] 256
[06:29:34] =============== [PASSED] test_range_compact ================
[06:29:34] ==================== test_range_spare =====================
[06:29:34] [PASSED] 4
[06:29:34] [PASSED] 8
[06:29:34] [PASSED] 32
[06:29:34] [PASSED] 256
[06:29:34] ================ [PASSED] test_range_spare =================
[06:29:34] ===================== [PASSED] guc_dbm =====================
[06:29:34] ================== guc_idm (22 subtests) ===================
[06:29:34] [PASSED] bad_init
[06:29:34] [PASSED] no_init
[06:29:34] [PASSED] init_fini
[06:29:34] [PASSED] check_init_small
[06:29:34] [PASSED] check_init_shared
[06:29:34] [PASSED] check_used
[06:29:34] [PASSED] check_quota
[06:29:34] [PASSED] check_all
[06:29:34] [PASSED] check_limits
[06:29:34] [PASSED] check_overlap
[06:29:34] [PASSED] check_overlap_alloc
[06:29:34] [PASSED] check_overlap_release
[06:29:34] [PASSED] check_overlap_partial_init
[06:29:34] [PASSED] check_overlap_partial_shared_range_blocking
[06:29:34] [PASSED] check_used_usable
[06:29:34] [PASSED] check_used_shareable
[06:29:34] [PASSED] check_used_mixed
[06:29:34] [PASSED] check_release_usable_range
[06:29:34] [PASSED] check_release_shareable_range
[06:29:34] [PASSED] check_split_boundaries
[06:29:34] [PASSED] check_shareable_spare
[06:29:34] [PASSED] check_shareable_spare_fragmented_tail
[06:29:34] ===================== [PASSED] guc_idm =====================
[06:29:34] ============== guc_klv_helpers (13 subtests) ===============
[06:29:34] [PASSED] test_count
[06:29:34] [PASSED] test_encode_u32
[06:29:34] [PASSED] test_encode_u64
[06:29:34] [PASSED] test_encode_string
[06:29:34] [PASSED] test_encode_object_raw
[06:29:34] [PASSED] test_encode_object_klv
[06:29:34] [PASSED] test_encode_object_nested
[06:29:34] [PASSED] test_encode_object_basic
[06:29:34] ===================== test_decode_u16 =====================
[06:29:34] [PASSED] empty
[06:29:34] [PASSED] valid
[06:29:34] [PASSED] max
[06:29:34] [PASSED] big
[06:29:34] [PASSED] long
[06:29:34] ================= [PASSED] test_decode_u16 =================
[06:29:34] ===================== test_decode_u32 =====================
[06:29:34] [PASSED] empty
[06:29:34] [PASSED] valid
[06:29:34] [PASSED] max
[06:29:34] [PASSED] long
[06:29:34] ================= [PASSED] test_decode_u32 =================
[06:29:34] ===================== test_decode_u64 =====================
[06:29:34] [PASSED] empty
[06:29:34] [PASSED] short
[06:29:34] [PASSED] valid
[06:29:34] [PASSED] max
[06:29:34] [PASSED] long
[06:29:34] ================= [PASSED] test_decode_u64 =================
[06:29:34] ===================== test_decode_str =====================
[06:29:34] [PASSED] empty
[06:29:34] [PASSED] one
[06:29:34] [PASSED] one_trash
[06:29:34] [PASSED] two
[06:29:34] [PASSED] two_trash
[06:29:34] [PASSED] three
[06:29:34] [PASSED] dword
[06:29:34] [PASSED] four
[06:29:34] [PASSED] five
[06:29:34] [PASSED] six
[06:29:34] [PASSED] seven
[06:29:34] [PASSED] qword
[06:29:34] ================= [PASSED] test_decode_str =================
[06:29:34] [PASSED] test_print
[06:29:34] ================= [PASSED] guc_klv_helpers =================
[06:29:34] =================== xe_log (4 subtests) ====================
[06:29:34] [PASSED] demo_cper
[06:29:34] [PASSED] demo_dmesg
[06:29:34] ======================= test_dmesg ========================
[06:29:34] [PASSED] test_fatal
[06:29:34] [PASSED] test_fatal_tile
[06:29:34] [PASSED] test_fatal_gt
[06:29:34] [PASSED] test_fatal_comp
[06:29:34] [PASSED] test_fatal_comp_tile
[06:29:34] [PASSED] test_fatal_comp_gt
[06:29:34] [PASSED] test_fatal_all
[06:29:34] [PASSED] test_recoverable
[06:29:34] [PASSED] test_recoverable_tile
[06:29:34] [PASSED] test_recoverable_gt
[06:29:34] [PASSED] test_recoverable_comp
[06:29:34] [PASSED] test_recoverable_comp_tile
[06:29:34] [PASSED] test_recoverable_comp_gt
[06:29:34] [PASSED] test_recoverable_all
[06:29:34] [PASSED] test_info
[06:29:34] [PASSED] test_info_tile
[06:29:34] [PASSED] test_info_gt
[06:29:34] [PASSED] test_info_err
[06:29:34] [PASSED] test_info_comp
[06:29:34] [PASSED] test_info_comp_tile
[06:29:34] [PASSED] test_info_comp_gt
[06:29:34] [PASSED] test_info_all
[06:29:34] [PASSED] test_hw_fatal
[06:29:34] [PASSED] test_hw_recoverable
[06:29:34] [PASSED] test_hw_corrected
[06:29:34] [PASSED] test_hw_informational
[06:29:34] =================== [PASSED] test_dmesg ====================
[06:29:34] ====================== test_invalid =======================
[06:29:34] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[06:29:34] ================== [SKIPPED] test_invalid ==================
[06:29:34] ===================== [PASSED] xe_log ======================
[06:29:34] ================== no_relay (3 subtests) ===================
[06:29:34] [PASSED] xe_drops_guc2pf_if_not_ready
[06:29:34] [PASSED] xe_drops_guc2vf_if_not_ready
[06:29:34] [PASSED] xe_rejects_send_if_not_ready
[06:29:34] ==================== [PASSED] no_relay =====================
[06:29:34] ================== pf_relay (14 subtests) ==================
[06:29:34] [PASSED] pf_rejects_guc2pf_too_short
[06:29:34] [PASSED] pf_rejects_guc2pf_too_long
[06:29:34] [PASSED] pf_rejects_guc2pf_no_payload
[06:29:34] [PASSED] pf_fails_no_payload
[06:29:34] [PASSED] pf_fails_bad_origin
[06:29:34] [PASSED] pf_fails_bad_type
[06:29:34] [PASSED] pf_txn_reports_error
[06:29:34] [PASSED] pf_txn_sends_pf2guc
[06:29:34] [PASSED] pf_sends_pf2guc
[06:29:34] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:29:34] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:29:34] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:29:34] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:29:34] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[06:29:34] ==================== [PASSED] pf_relay =====================
[06:29:34] ================== vf_relay (3 subtests) ===================
[06:29:34] [PASSED] vf_rejects_guc2vf_too_short
[06:29:34] [PASSED] vf_rejects_guc2vf_too_long
[06:29:34] [PASSED] vf_rejects_guc2vf_no_payload
[06:29:34] ==================== [PASSED] vf_relay =====================
[06:29:34] ================ pf_gt_config (9 subtests) =================
[06:29:34] [PASSED] fair_contexts_1vf
[06:29:34] [PASSED] fair_doorbells_1vf
[06:29:34] [PASSED] fair_ggtt_1vf
[06:29:34] ====================== fair_vram_1vf ======================
[06:29:34] [PASSED] 3.50 GiB
[06:29:34] [PASSED] 11.5 GiB
[06:29:34] [PASSED] 15.5 GiB
[06:29:34] [PASSED] 31.5 GiB
[06:29:34] [PASSED] 63.5 GiB
[06:29:34] [PASSED] 1.91 GiB
[06:29:34] ================== [PASSED] fair_vram_1vf ==================
[06:29:34] ================ fair_vram_1vf_admin_only =================
[06:29:34] [PASSED] 3.50 GiB
[06:29:34] [PASSED] 11.5 GiB
[06:29:34] [PASSED] 15.5 GiB
[06:29:34] [PASSED] 31.5 GiB
[06:29:34] [PASSED] 63.5 GiB
[06:29:34] [PASSED] 1.91 GiB
[06:29:34] ============ [PASSED] fair_vram_1vf_admin_only =============
[06:29:34] ====================== fair_contexts ======================
[06:29:34] [PASSED] 1 VF
[06:29:34] [PASSED] 2 VFs
[06:29:34] [PASSED] 3 VFs
[06:29:34] [PASSED] 4 VFs
[06:29:34] [PASSED] 5 VFs
[06:29:34] [PASSED] 6 VFs
[06:29:34] [PASSED] 7 VFs
[06:29:34] [PASSED] 8 VFs
[06:29:34] [PASSED] 9 VFs
[06:29:34] [PASSED] 10 VFs
[06:29:34] [PASSED] 11 VFs
[06:29:34] [PASSED] 12 VFs
[06:29:34] [PASSED] 13 VFs
[06:29:34] [PASSED] 14 VFs
[06:29:34] [PASSED] 15 VFs
[06:29:34] [PASSED] 16 VFs
[06:29:34] [PASSED] 17 VFs
[06:29:34] [PASSED] 18 VFs
[06:29:34] [PASSED] 19 VFs
[06:29:34] [PASSED] 20 VFs
[06:29:34] [PASSED] 21 VFs
[06:29:34] [PASSED] 22 VFs
[06:29:34] [PASSED] 23 VFs
[06:29:34] [PASSED] 24 VFs
[06:29:34] [PASSED] 25 VFs
[06:29:34] [PASSED] 26 VFs
[06:29:34] [PASSED] 27 VFs
[06:29:34] [PASSED] 28 VFs
[06:29:34] [PASSED] 29 VFs
[06:29:34] [PASSED] 30 VFs
[06:29:34] [PASSED] 31 VFs
[06:29:34] [PASSED] 32 VFs
[06:29:34] [PASSED] 33 VFs
[06:29:34] [PASSED] 34 VFs
[06:29:34] [PASSED] 35 VFs
[06:29:34] [PASSED] 36 VFs
[06:29:34] [PASSED] 37 VFs
[06:29:34] [PASSED] 38 VFs
[06:29:34] [PASSED] 39 VFs
[06:29:34] [PASSED] 40 VFs
[06:29:34] [PASSED] 41 VFs
[06:29:34] [PASSED] 42 VFs
[06:29:34] [PASSED] 43 VFs
[06:29:34] [PASSED] 44 VFs
[06:29:34] [PASSED] 45 VFs
[06:29:34] [PASSED] 46 VFs
[06:29:34] [PASSED] 47 VFs
[06:29:34] [PASSED] 48 VFs
[06:29:34] [PASSED] 49 VFs
[06:29:34] [PASSED] 50 VFs
[06:29:34] [PASSED] 51 VFs
[06:29:34] [PASSED] 52 VFs
[06:29:34] [PASSED] 53 VFs
[06:29:34] [PASSED] 54 VFs
[06:29:34] [PASSED] 55 VFs
[06:29:34] [PASSED] 56 VFs
[06:29:34] [PASSED] 57 VFs
[06:29:34] [PASSED] 58 VFs
[06:29:34] [PASSED] 59 VFs
[06:29:34] [PASSED] 60 VFs
[06:29:34] [PASSED] 61 VFs
[06:29:34] [PASSED] 62 VFs
[06:29:34] [PASSED] 63 VFs
[06:29:34] ================== [PASSED] fair_contexts ==================
[06:29:34] ===================== fair_doorbells ======================
[06:29:34] [PASSED] 1 VF
[06:29:34] [PASSED] 2 VFs
[06:29:34] [PASSED] 3 VFs
[06:29:34] [PASSED] 4 VFs
[06:29:34] [PASSED] 5 VFs
[06:29:34] [PASSED] 6 VFs
[06:29:34] [PASSED] 7 VFs
[06:29:34] [PASSED] 8 VFs
[06:29:34] [PASSED] 9 VFs
[06:29:34] [PASSED] 10 VFs
[06:29:34] [PASSED] 11 VFs
[06:29:34] [PASSED] 12 VFs
[06:29:34] [PASSED] 13 VFs
[06:29:34] [PASSED] 14 VFs
[06:29:34] [PASSED] 15 VFs
[06:29:34] [PASSED] 16 VFs
[06:29:34] [PASSED] 17 VFs
[06:29:34] [PASSED] 18 VFs
[06:29:34] [PASSED] 19 VFs
[06:29:34] [PASSED] 20 VFs
[06:29:34] [PASSED] 21 VFs
[06:29:34] [PASSED] 22 VFs
[06:29:34] [PASSED] 23 VFs
[06:29:34] [PASSED] 24 VFs
[06:29:34] [PASSED] 25 VFs
[06:29:34] [PASSED] 26 VFs
[06:29:34] [PASSED] 27 VFs
[06:29:34] [PASSED] 28 VFs
[06:29:34] [PASSED] 29 VFs
[06:29:34] [PASSED] 30 VFs
[06:29:34] [PASSED] 31 VFs
[06:29:34] [PASSED] 32 VFs
[06:29:34] [PASSED] 33 VFs
[06:29:34] [PASSED] 34 VFs
[06:29:34] [PASSED] 35 VFs
[06:29:34] [PASSED] 36 VFs
[06:29:34] [PASSED] 37 VFs
[06:29:34] [PASSED] 38 VFs
[06:29:34] [PASSED] 39 VFs
[06:29:34] [PASSED] 40 VFs
[06:29:34] [PASSED] 41 VFs
[06:29:34] [PASSED] 42 VFs
[06:29:34] [PASSED] 43 VFs
[06:29:34] [PASSED] 44 VFs
[06:29:34] [PASSED] 45 VFs
[06:29:34] [PASSED] 46 VFs
[06:29:34] [PASSED] 47 VFs
[06:29:34] [PASSED] 48 VFs
[06:29:34] [PASSED] 49 VFs
[06:29:34] [PASSED] 50 VFs
[06:29:34] [PASSED] 51 VFs
[06:29:34] [PASSED] 52 VFs
[06:29:34] [PASSED] 53 VFs
[06:29:34] [PASSED] 54 VFs
[06:29:34] [PASSED] 55 VFs
[06:29:34] [PASSED] 56 VFs
[06:29:34] [PASSED] 57 VFs
[06:29:34] [PASSED] 58 VFs
[06:29:34] [PASSED] 59 VFs
[06:29:34] [PASSED] 60 VFs
[06:29:34] [PASSED] 61 VFs
[06:29:34] [PASSED] 62 VFs
[06:29:34] [PASSED] 63 VFs
[06:29:34] ================= [PASSED] fair_doorbells ==================
[06:29:34] ======================== fair_ggtt ========================
[06:29:34] [PASSED] 1 VF
[06:29:34] [PASSED] 2 VFs
[06:29:34] [PASSED] 3 VFs
[06:29:34] [PASSED] 4 VFs
[06:29:34] [PASSED] 5 VFs
[06:29:34] [PASSED] 6 VFs
[06:29:34] [PASSED] 7 VFs
[06:29:34] [PASSED] 8 VFs
[06:29:34] [PASSED] 9 VFs
[06:29:34] [PASSED] 10 VFs
[06:29:34] [PASSED] 11 VFs
[06:29:34] [PASSED] 12 VFs
[06:29:34] [PASSED] 13 VFs
[06:29:34] [PASSED] 14 VFs
[06:29:34] [PASSED] 15 VFs
[06:29:34] [PASSED] 16 VFs
[06:29:34] [PASSED] 17 VFs
[06:29:34] [PASSED] 18 VFs
[06:29:34] [PASSED] 19 VFs
[06:29:34] [PASSED] 20 VFs
[06:29:34] [PASSED] 21 VFs
[06:29:34] [PASSED] 22 VFs
[06:29:34] [PASSED] 23 VFs
[06:29:34] [PASSED] 24 VFs
[06:29:34] [PASSED] 25 VFs
[06:29:34] [PASSED] 26 VFs
[06:29:34] [PASSED] 27 VFs
[06:29:34] [PASSED] 28 VFs
[06:29:34] [PASSED] 29 VFs
[06:29:34] [PASSED] 30 VFs
[06:29:34] [PASSED] 31 VFs
[06:29:34] [PASSED] 32 VFs
[06:29:34] [PASSED] 33 VFs
[06:29:34] [PASSED] 34 VFs
[06:29:34] [PASSED] 35 VFs
[06:29:34] [PASSED] 36 VFs
[06:29:34] [PASSED] 37 VFs
[06:29:34] [PASSED] 38 VFs
[06:29:34] [PASSED] 39 VFs
[06:29:34] [PASSED] 40 VFs
[06:29:34] [PASSED] 41 VFs
[06:29:34] [PASSED] 42 VFs
[06:29:34] [PASSED] 43 VFs
[06:29:34] [PASSED] 44 VFs
[06:29:34] [PASSED] 45 VFs
[06:29:34] [PASSED] 46 VFs
[06:29:34] [PASSED] 47 VFs
[06:29:34] [PASSED] 48 VFs
[06:29:34] [PASSED] 49 VFs
[06:29:34] [PASSED] 50 VFs
[06:29:34] [PASSED] 51 VFs
[06:29:34] [PASSED] 52 VFs
[06:29:34] [PASSED] 53 VFs
[06:29:34] [PASSED] 54 VFs
[06:29:34] [PASSED] 55 VFs
[06:29:34] [PASSED] 56 VFs
[06:29:34] [PASSED] 57 VFs
[06:29:34] [PASSED] 58 VFs
[06:29:34] [PASSED] 59 VFs
[06:29:34] [PASSED] 60 VFs
[06:29:34] [PASSED] 61 VFs
[06:29:34] [PASSED] 62 VFs
[06:29:34] [PASSED] 63 VFs
[06:29:34] ==================== [PASSED] fair_ggtt ====================
[06:29:34] ======================== fair_vram ========================
[06:29:34] [PASSED] 1 VF
[06:29:34] [PASSED] 2 VFs
[06:29:34] [PASSED] 3 VFs
[06:29:34] [PASSED] 4 VFs
[06:29:34] [PASSED] 5 VFs
[06:29:34] [PASSED] 6 VFs
[06:29:34] [PASSED] 7 VFs
[06:29:34] [PASSED] 8 VFs
[06:29:34] [PASSED] 9 VFs
[06:29:34] [PASSED] 10 VFs
[06:29:34] [PASSED] 11 VFs
[06:29:34] [PASSED] 12 VFs
[06:29:34] [PASSED] 13 VFs
[06:29:34] [PASSED] 14 VFs
[06:29:34] [PASSED] 15 VFs
[06:29:34] [PASSED] 16 VFs
[06:29:34] [PASSED] 17 VFs
[06:29:34] [PASSED] 18 VFs
[06:29:34] [PASSED] 19 VFs
[06:29:34] [PASSED] 20 VFs
[06:29:34] [PASSED] 21 VFs
[06:29:34] [PASSED] 22 VFs
[06:29:34] [PASSED] 23 VFs
[06:29:34] [PASSED] 24 VFs
[06:29:34] [PASSED] 25 VFs
[06:29:34] [PASSED] 26 VFs
[06:29:34] [PASSED] 27 VFs
[06:29:34] [PASSED] 28 VFs
[06:29:34] [PASSED] 29 VFs
[06:29:34] [PASSED] 30 VFs
[06:29:34] [PASSED] 31 VFs
[06:29:34] [PASSED] 32 VFs
[06:29:34] [PASSED] 33 VFs
[06:29:34] [PASSED] 34 VFs
[06:29:34] [PASSED] 35 VFs
[06:29:34] [PASSED] 36 VFs
[06:29:34] [PASSED] 37 VFs
[06:29:34] [PASSED] 38 VFs
[06:29:34] [PASSED] 39 VFs
[06:29:34] [PASSED] 40 VFs
[06:29:34] [PASSED] 41 VFs
[06:29:34] [PASSED] 42 VFs
[06:29:34] [PASSED] 43 VFs
[06:29:34] [PASSED] 44 VFs
[06:29:34] [PASSED] 45 VFs
[06:29:34] [PASSED] 46 VFs
[06:29:34] [PASSED] 47 VFs
[06:29:34] [PASSED] 48 VFs
[06:29:34] [PASSED] 49 VFs
[06:29:34] [PASSED] 50 VFs
[06:29:34] [PASSED] 51 VFs
[06:29:34] [PASSED] 52 VFs
[06:29:34] [PASSED] 53 VFs
[06:29:34] [PASSED] 54 VFs
[06:29:34] [PASSED] 55 VFs
[06:29:34] [PASSED] 56 VFs
[06:29:34] [PASSED] 57 VFs
[06:29:34] [PASSED] 58 VFs
[06:29:34] [PASSED] 59 VFs
[06:29:34] [PASSED] 60 VFs
[06:29:34] [PASSED] 61 VFs
[06:29:34] [PASSED] 62 VFs
[06:29:34] [PASSED] 63 VFs
[06:29:34] ==================== [PASSED] fair_vram ====================
[06:29:34] ================== [PASSED] pf_gt_config ===================
[06:29:34] ===================== lmtt (1 subtest) =====================
[06:29:34] ======================== test_ops =========================
[06:29:34] [PASSED] 2-level
[06:29:34] [PASSED] multi-level
[06:29:34] ==================== [PASSED] test_ops =====================
[06:29:34] ====================== [PASSED] lmtt =======================
[06:29:34] ================= sriov_packet (1 subtest) =================
[06:29:34] [PASSED] test_descriptor_init
[06:29:34] ================== [PASSED] sriov_packet ===================
[06:29:34] ================= pf_service (11 subtests) =================
[06:29:34] [PASSED] pf_negotiate_any
[06:29:34] [PASSED] pf_negotiate_base_match
[06:29:34] [PASSED] pf_negotiate_base_newer
[06:29:34] [PASSED] pf_negotiate_base_next
[06:29:34] [SKIPPED] pf_negotiate_base_older (no older minor)
[06:29:34] [PASSED] pf_negotiate_base_prev
[06:29:34] [PASSED] pf_negotiate_latest_match
[06:29:34] [PASSED] pf_negotiate_latest_newer
[06:29:34] [PASSED] pf_negotiate_latest_next
[06:29:34] [SKIPPED] pf_negotiate_latest_older (no older minor)
[06:29:34] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[06:29:34] =================== [PASSED] pf_service ====================
[06:29:34] ================= xe_guc_g2g (2 subtests) ==================
[06:29:34] ============== xe_live_guc_g2g_kunit_default ==============
[06:29:34] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[06:29:34] ============== xe_live_guc_g2g_kunit_allmem ===============
[06:29:34] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[06:29:34] =================== [SKIPPED] xe_guc_g2g ===================
[06:29:34] =================== xe_mocs (2 subtests) ===================
[06:29:34] ================ xe_live_mocs_kernel_kunit ================
[06:29:34] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[06:29:34] ================ xe_live_mocs_reset_kunit =================
[06:29:34] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[06:29:34] ==================== [SKIPPED] xe_mocs =====================
[06:29:34] ================= xe_migrate (3 subtests) ==================
[06:29:34] ================= xe_migrate_sanity_kunit =================
[06:29:34] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[06:29:34] ================== xe_validate_ccs_kunit ==================
[06:29:34] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[06:29:34] ============= xe_migrate_access_memory_kunit ==============
[06:29:34] ========= [SKIPPED] xe_migrate_access_memory_kunit =========
[06:29:34] =================== [SKIPPED] xe_migrate ===================
[06:29:34] ================== xe_dma_buf (1 subtest) ==================
[06:29:34] ==================== xe_dma_buf_kunit =====================
[06:29:34] ================ [SKIPPED] xe_dma_buf_kunit ================
[06:29:34] =================== [SKIPPED] xe_dma_buf ===================
[06:29:34] ================= xe_bo_shrink (1 subtest) =================
[06:29:34] =================== xe_bo_shrink_kunit ====================
[06:29:34] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[06:29:34] ================== [SKIPPED] xe_bo_shrink ==================
[06:29:34] ==================== xe_bo (2 subtests) ====================
[06:29:34] ================== xe_ccs_migrate_kunit ===================
[06:29:34] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[06:29:34] ==================== xe_bo_evict_kunit ====================
[06:29:34] =============== [SKIPPED] xe_bo_evict_kunit ================
[06:29:34] ===================== [SKIPPED] xe_bo ======================
[06:29:34] =================== xe_any (9 subtests) ====================
[06:29:34] [PASSED] test_to_xe
[06:29:34] [PASSED] test_to_dev
[06:29:34] [PASSED] test_to_pdev
[06:29:34] [PASSED] test_to_drm
[06:29:34] [PASSED] test_if_pdev
[06:29:34] [PASSED] test_if_xe
[06:29:34] [PASSED] test_if_tile
[06:29:34] [PASSED] test_if_gt
[06:29:34] [PASSED] test_to_id
[06:29:34] ===================== [PASSED] xe_any ======================
[06:29:34] ==================== args (13 subtests) ====================
[06:29:34] [PASSED] count_args_test
[06:29:34] [PASSED] call_args_example
[06:29:34] [PASSED] call_args_test
[06:29:34] [PASSED] drop_first_arg_example
[06:29:34] [PASSED] drop_first_arg_test
[06:29:34] [PASSED] first_arg_example
[06:29:34] [PASSED] first_arg_test
[06:29:34] [PASSED] last_arg_example
[06:29:34] [PASSED] last_arg_test
[06:29:34] [PASSED] pick_arg_example
[06:29:34] [PASSED] if_args_example
[06:29:34] [PASSED] if_args_test
[06:29:34] [PASSED] sep_comma_example
[06:29:34] ====================== [PASSED] args =======================
[06:29:34] =================== xe_pci (3 subtests) ====================
[06:29:34] ==================== check_graphics_ip ====================
[06:29:34] [PASSED] 12.00 Xe_LP
[06:29:34] [PASSED] 12.10 Xe_LP+
[06:29:34] [PASSED] 12.55 Xe_HPG
[06:29:34] [PASSED] 12.60 Xe_HPC
[06:29:34] [PASSED] 12.70 Xe_LPG
[06:29:34] [PASSED] 12.71 Xe_LPG
[06:29:34] [PASSED] 12.74 Xe_LPG+
[06:29:34] [PASSED] 20.01 Xe2_HPG
[06:29:34] [PASSED] 20.02 Xe2_HPG
[06:29:34] [PASSED] 20.04 Xe2_LPG
[06:29:34] [PASSED] 30.00 Xe3_LPG
[06:29:34] [PASSED] 30.01 Xe3_LPG
[06:29:34] [PASSED] 30.03 Xe3_LPG
[06:29:34] [PASSED] 30.04 Xe3_LPG
[06:29:34] [PASSED] 30.05 Xe3_LPG
[06:29:34] [PASSED] 35.10 Xe3p_LPG
[06:29:34] [PASSED] 35.11 Xe3p_XPC
[06:29:34] ================ [PASSED] check_graphics_ip ================
[06:29:34] ===================== check_media_ip ======================
[06:29:34] [PASSED] 12.00 Xe_M
[06:29:34] [PASSED] 12.55 Xe_HPM
[06:29:34] [PASSED] 13.00 Xe_LPM+
[06:29:34] [PASSED] 13.01 Xe2_HPM
[06:29:34] [PASSED] 20.00 Xe2_LPM
[06:29:34] [PASSED] 30.00 Xe3_LPM
[06:29:34] [PASSED] 30.02 Xe3_LPM
[06:29:34] [PASSED] 35.00 Xe3p_LPM
[06:29:34] [PASSED] 35.03 Xe3p_HPM
[06:29:34] ================= [PASSED] check_media_ip ==================
[06:29:34] =================== check_platform_desc ===================
[06:29:34] [PASSED] 0x9A60 (TIGERLAKE)
[06:29:34] [PASSED] 0x9A68 (TIGERLAKE)
[06:29:34] [PASSED] 0x9A70 (TIGERLAKE)
[06:29:34] [PASSED] 0x9A40 (TIGERLAKE)
[06:29:34] [PASSED] 0x9A49 (TIGERLAKE)
[06:29:34] [PASSED] 0x9A59 (TIGERLAKE)
[06:29:34] [PASSED] 0x9A78 (TIGERLAKE)
[06:29:34] [PASSED] 0x9AC0 (TIGERLAKE)
[06:29:34] [PASSED] 0x9AC9 (TIGERLAKE)
[06:29:34] [PASSED] 0x9AD9 (TIGERLAKE)
[06:29:34] [PASSED] 0x9AF8 (TIGERLAKE)
[06:29:34] [PASSED] 0x4C80 (ROCKETLAKE)
[06:29:34] [PASSED] 0x4C8A (ROCKETLAKE)
[06:29:34] [PASSED] 0x4C8B (ROCKETLAKE)
[06:29:34] [PASSED] 0x4C8C (ROCKETLAKE)
[06:29:34] [PASSED] 0x4C90 (ROCKETLAKE)
[06:29:34] [PASSED] 0x4C9A (ROCKETLAKE)
[06:29:34] [PASSED] 0x4680 (ALDERLAKE_S)
[06:29:34] [PASSED] 0x4682 (ALDERLAKE_S)
[06:29:34] [PASSED] 0x4688 (ALDERLAKE_S)
[06:29:34] [PASSED] 0x468A (ALDERLAKE_S)
[06:29:34] [PASSED] 0x468B (ALDERLAKE_S)
[06:29:34] [PASSED] 0x4690 (ALDERLAKE_S)
[06:29:34] [PASSED] 0x4692 (ALDERLAKE_S)
[06:29:34] [PASSED] 0x4693 (ALDERLAKE_S)
[06:29:34] [PASSED] 0x46A0 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46A1 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46A2 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46A3 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46A6 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46A8 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46AA (ALDERLAKE_P)
[06:29:34] [PASSED] 0x462A (ALDERLAKE_P)
[06:29:34] [PASSED] 0x4626 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x4628 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46B0 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46B1 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46B2 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46B3 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46C0 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46C1 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46C2 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46C3 (ALDERLAKE_P)
[06:29:34] [PASSED] 0x46D0 (ALDERLAKE_N)
[06:29:34] [PASSED] 0x46D1 (ALDERLAKE_N)
[06:29:34] [PASSED] 0x46D2 (ALDERLAKE_N)
[06:29:34] [PASSED] 0x46D3 (ALDERLAKE_N)
[06:29:34] [PASSED] 0x46D4 (ALDERLAKE_N)
[06:29:34] [PASSED] 0xA721 (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7A1 (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7A9 (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7AC (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7AD (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA720 (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7A0 (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7A8 (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7AA (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA7AB (ALDERLAKE_P)
[06:29:34] [PASSED] 0xA780 (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA781 (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA782 (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA783 (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA788 (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA789 (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA78A (ALDERLAKE_S)
[06:29:34] [PASSED] 0xA78B (ALDERLAKE_S)
[06:29:34] [PASSED] 0x4905 (DG1)
[06:29:34] [PASSED] 0x4906 (DG1)
[06:29:34] [PASSED] 0x4907 (DG1)
[06:29:34] [PASSED] 0x4908 (DG1)
[06:29:34] [PASSED] 0x4909 (DG1)
[06:29:34] [PASSED] 0x56C0 (DG2)
[06:29:34] [PASSED] 0x56C2 (DG2)
[06:29:34] [PASSED] 0x56C1 (DG2)
[06:29:34] [PASSED] 0x7D51 (METEORLAKE)
[06:29:34] [PASSED] 0x7DD1 (METEORLAKE)
[06:29:34] [PASSED] 0x7D41 (METEORLAKE)
[06:29:34] [PASSED] 0x7D67 (METEORLAKE)
[06:29:34] [PASSED] 0xB640 (METEORLAKE)
[06:29:34] [PASSED] 0x56A0 (DG2)
[06:29:34] [PASSED] 0x56A1 (DG2)
[06:29:34] [PASSED] 0x56A2 (DG2)
[06:29:34] [PASSED] 0x56BE (DG2)
[06:29:34] [PASSED] 0x56BF (DG2)
[06:29:34] [PASSED] 0x5690 (DG2)
[06:29:34] [PASSED] 0x5691 (DG2)
[06:29:34] [PASSED] 0x5692 (DG2)
[06:29:34] [PASSED] 0x56A5 (DG2)
[06:29:34] [PASSED] 0x56A6 (DG2)
[06:29:34] [PASSED] 0x56B0 (DG2)
[06:29:34] [PASSED] 0x56B1 (DG2)
[06:29:34] [PASSED] 0x56BA (DG2)
[06:29:34] [PASSED] 0x56BB (DG2)
[06:29:34] [PASSED] 0x56BC (DG2)
[06:29:34] [PASSED] 0x56BD (DG2)
[06:29:34] [PASSED] 0x5693 (DG2)
[06:29:34] [PASSED] 0x5694 (DG2)
[06:29:34] [PASSED] 0x5695 (DG2)
[06:29:34] [PASSED] 0x56A3 (DG2)
[06:29:34] [PASSED] 0x56A4 (DG2)
[06:29:34] [PASSED] 0x56B2 (DG2)
[06:29:34] [PASSED] 0x56B3 (DG2)
[06:29:34] [PASSED] 0x5696 (DG2)
[06:29:34] [PASSED] 0x5697 (DG2)
[06:29:34] [PASSED] 0xB69 (PVC)
[06:29:34] [PASSED] 0xB6E (PVC)
[06:29:34] [PASSED] 0xBD4 (PVC)
[06:29:34] [PASSED] 0xBD5 (PVC)
[06:29:34] [PASSED] 0xBD6 (PVC)
[06:29:34] [PASSED] 0xBD7 (PVC)
[06:29:34] [PASSED] 0xBD8 (PVC)
[06:29:34] [PASSED] 0xBD9 (PVC)
[06:29:34] [PASSED] 0xBDA (PVC)
[06:29:34] [PASSED] 0xBDB (PVC)
[06:29:34] [PASSED] 0xBE0 (PVC)
[06:29:34] [PASSED] 0xBE1 (PVC)
[06:29:34] [PASSED] 0xBE5 (PVC)
[06:29:34] [PASSED] 0x7D40 (METEORLAKE)
[06:29:34] [PASSED] 0x7D45 (METEORLAKE)
[06:29:34] [PASSED] 0x7D55 (METEORLAKE)
[06:29:34] [PASSED] 0x7D60 (METEORLAKE)
[06:29:34] [PASSED] 0x7DD5 (METEORLAKE)
[06:29:34] [PASSED] 0x6420 (LUNARLAKE)
[06:29:34] [PASSED] 0x64A0 (LUNARLAKE)
[06:29:34] [PASSED] 0x64B0 (LUNARLAKE)
[06:29:34] [PASSED] 0xE202 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE209 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE20B (BATTLEMAGE)
[06:29:34] [PASSED] 0xE20C (BATTLEMAGE)
[06:29:34] [PASSED] 0xE20D (BATTLEMAGE)
[06:29:34] [PASSED] 0xE210 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE211 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE212 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE216 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE220 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE221 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE222 (BATTLEMAGE)
[06:29:34] [PASSED] 0xE223 (BATTLEMAGE)
[06:29:34] [PASSED] 0xB080 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB081 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB082 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB083 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB084 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB085 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB086 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB087 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB08F (PANTHERLAKE)
[06:29:34] [PASSED] 0xB090 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB0A0 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB0A1 (PANTHERLAKE)
[06:29:34] [PASSED] 0xB0B0 (PANTHERLAKE)
[06:29:34] [PASSED] 0xFD80 (PANTHERLAKE)
[06:29:34] [PASSED] 0xFD81 (PANTHERLAKE)
[06:29:34] [PASSED] 0xD740 (NOVALAKE_S)
[06:29:34] [PASSED] 0xD741 (NOVALAKE_S)
[06:29:34] [PASSED] 0xD742 (NOVALAKE_S)
[06:29:34] [PASSED] 0xD743 (NOVALAKE_S)
[06:29:34] [PASSED] 0xD745 (NOVALAKE_S)
[06:29:34] [PASSED] 0xD74A (NOVALAKE_S)
[06:29:34] [PASSED] 0xD74B (NOVALAKE_S)
[06:29:34] [PASSED] 0x674C (CRESCENTISLAND)
[06:29:34] [PASSED] 0x674D (CRESCENTISLAND)
[06:29:34] [PASSED] 0x674E (CRESCENTISLAND)
[06:29:34] [PASSED] 0x674F (CRESCENTISLAND)
[06:29:34] [PASSED] 0x6750 (CRESCENTISLAND)
[06:29:34] [PASSED] 0x6751 (CRESCENTISLAND)
[06:29:34] [PASSED] 0xD750 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD751 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD752 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD753 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD754 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD755 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD756 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD757 (NOVALAKE_P)
[06:29:34] [PASSED] 0xD75F (NOVALAKE_P)
[06:29:34] =============== [PASSED] check_platform_desc ===============
[06:29:34] ===================== [PASSED] xe_pci ======================
[06:29:34] ============= xe_rtp_tables_test (5 subtests) ==============
[06:29:34] ================== xe_rtp_table_gt_test ===================
[06:29:34] [PASSED] gt_was/14011060649
[06:29:34] [PASSED] gt_was/14011059788
[06:29:34] [PASSED] gt_was/14015795083
[06:29:34] [PASSED] gt_was/16021867713
[06:29:34] [PASSED] gt_was/14019449301
[06:29:34] [PASSED] gt_was/16028005424
[06:29:34] [PASSED] gt_was/14026578760
[06:29:34] [PASSED] gt_was/1409420604
[06:29:34] [PASSED] gt_was/1408615072
[06:29:34] [PASSED] gt_was/22010523718
[06:29:34] [PASSED] gt_was/14011006942
[06:29:34] [PASSED] gt_was/14014830051
[06:29:34] [PASSED] gt_was/18018781329
[06:29:34] [PASSED] gt_was/1509235366
[06:29:34] [PASSED] gt_was/18018781329
[06:29:34] [PASSED] gt_was/16016694945
[06:29:34] [PASSED] gt_was/14018575942
[06:29:34] [PASSED] gt_was/22016670082
[06:29:34] [PASSED] gt_was/22016670082
[06:29:34] [PASSED] gt_was/14017421178
[06:29:34] [PASSED] gt_was/16025250150
[06:29:34] [PASSED] gt_was/14021871409
[06:29:34] [PASSED] gt_was/16021865536
[06:29:34] [PASSED] gt_was/14021486841
[06:29:34] [PASSED] gt_was/14025160223
[06:29:34] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[06:29:34] [PASSED] gt_was/14025635424
[06:29:34] [PASSED] gt_was/16028005424
[06:29:34] ============== [PASSED] xe_rtp_table_gt_test ===============
[06:29:34] ================== xe_rtp_table_gt_test ===================
[06:29:34] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[06:29:34] [PASSED] gt_tunings/Tuning: 32B Access Enable
[06:29:34] [PASSED] gt_tunings/Tuning: L3 cache
[06:29:34] [PASSED] gt_tunings/Tuning: L3 cache - media
[06:29:34] [PASSED] gt_tunings/Tuning: Compression Overfetch
[06:29:34] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[06:29:34] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[06:29:34] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[06:29:34] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[06:29:34] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[06:29:34] [PASSED] gt_tunings/Tuning: Stateless compression control
[06:29:34] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[06:29:34] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[06:29:34] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[06:29:34] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[06:29:34] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[06:29:34] ============== [PASSED] xe_rtp_table_gt_test ===============
[06:29:34] ================== xe_rtp_table_oob_test ==================
[06:29:34] [PASSED] oob_was/1607983814
[06:29:34] [PASSED] oob_was/16010904313
[06:29:34] [PASSED] oob_was/18022495364
[06:29:34] [PASSED] oob_was/22012773006
[06:29:34] [PASSED] oob_was/14014475959
[06:29:34] [PASSED] oob_was/22011391025
[06:29:34] [PASSED] oob_was/22012727170
[06:29:34] [PASSED] oob_was/22012727685
[06:29:34] [PASSED] oob_was/22016596838
[06:29:34] [PASSED] oob_was/18020744125
[06:29:34] [PASSED] oob_was/1409600907
[06:29:34] [PASSED] oob_was/22014953428
[06:29:34] [PASSED] oob_was/16017236439
[06:29:34] [PASSED] oob_was/14019821291
[06:29:34] [PASSED] oob_was/14015076503
[06:29:34] [PASSED] oob_was/22016122933
[06:29:34] [PASSED] oob_was/14018913170
[06:29:34] [PASSED] oob_was/14018094691
[06:29:34] [PASSED] oob_was/18024947630
[06:29:34] [PASSED] oob_was/16022287689
[06:29:34] [PASSED] oob_was/13011645652
[06:29:34] [PASSED] oob_was/14022293748
[06:29:34] [PASSED] oob_was/22019794406
[06:29:34] [PASSED] oob_was/22019338487
[06:29:34] [PASSED] oob_was/16023588340
[06:29:34] [PASSED] oob_was/14019789679
[06:29:34] [PASSED] oob_was/14022866841
[06:29:34] [PASSED] oob_was/16021333562
[06:29:34] [PASSED] oob_was/14016712196
[06:29:34] [PASSED] oob_was/14015568240
[06:29:34] [PASSED] oob_was/18013179988
[06:29:34] [PASSED] oob_was/1508761755
[06:29:34] [PASSED] oob_was/16023105232
[06:29:34] [PASSED] oob_was/16026508708
[06:29:34] [PASSED] oob_was/14020001231
[06:29:34] [PASSED] oob_was/16023683509
[06:29:34] [PASSED] oob_was/14025515070
[06:29:34] [PASSED] oob_was/15015404425_disable
[06:29:34] [PASSED] oob_was/16026007364
[06:29:34] [PASSED] oob_was/14020316580
[06:29:34] [PASSED] oob_was/14025883347
[06:29:34] [PASSED] oob_was/16029380221
[06:29:34] [PASSED] oob_was/22022079272
[06:29:34] [PASSED] oob_was/16029897822
[06:29:34] [PASSED] oob_was/14027054324
[06:29:34] [PASSED] oob_was/14025941587
[06:29:34] [PASSED] oob_was/16030224309
[06:29:34] ============== [PASSED] xe_rtp_table_oob_test ==============
[06:29:34] ================ xe_rtp_table_dev_oob_test ================
[06:29:34] [PASSED] device_oob_was/22010954014
[06:29:34] [PASSED] device_oob_was/15015404425
[06:29:34] [PASSED] device_oob_was/22019338487_display
[06:29:34] [PASSED] device_oob_was/14022085890
[06:29:34] [PASSED] device_oob_was/14026539277
[06:29:34] [PASSED] device_oob_was/14026633728
[06:29:34] [PASSED] device_oob_was/14026746987
[06:29:34] [PASSED] device_oob_was/14026779378
[06:29:34] [PASSED] device_oob_was/14028434957
[06:29:34] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[06:29:34] ========== xe_rtp_table_missing_upper_bound_test ==========
[06:29:34] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[06:29:34] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[06:29:34] [PASSED] register_whitelist/1806527549
[06:29:34] [PASSED] register_whitelist/allow_read_ctx_timestamp
[06:29:34] [PASSED] register_whitelist/allow_read_queue_timestamp
[06:29:34] [PASSED] register_whitelist/16014440446
[06:29:34] [PASSED] register_whitelist/16017236439
[06:29:34] [PASSED] register_whitelist/16020183090
[06:29:34] [PASSED] register_whitelist/14024997852
[06:29:34] [PASSED] register_whitelist/14024997852
[06:29:34] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[06:29:34] =============== [PASSED] xe_rtp_tables_test ================
[06:29:34] =================== xe_rtp (3 subtests) ====================
[06:29:34] =================== xe_rtp_rules_tests ====================
[06:29:34] [PASSED] no
[06:29:34] [PASSED] yes
[06:29:34] [PASSED] no-and-no
[06:29:34] [PASSED] no-and-yes
[06:29:34] [PASSED] yes-and-no
[06:29:34] [PASSED] yes-and-yes
[06:29:34] [PASSED] no-or-no
[06:29:34] [PASSED] no-or-yes
[06:29:34] [PASSED] yes-or-no
[06:29:34] [PASSED] yes-or-yes
[06:29:34] [PASSED] no-yes-or-yes-no
[06:29:34] [PASSED] no-yes-or-yes-yes
[06:29:34] [PASSED] yes-yes-or-no-yes
[06:29:34] [PASSED] yes-yes-or-yes-yes
[06:29:34] [PASSED] no-no-or-yes-or-no
[06:29:34] [PASSED] or
[06:29:34] [PASSED] or-yes
[06:29:34] [PASSED] or-no
[06:29:34] [PASSED] yes-or
[06:29:34] [PASSED] no-or
[06:29:34] [PASSED] no-or-or-yes
[06:29:34] [PASSED] yes-or-or-no
[06:29:34] [PASSED] no-or-or-no
[06:29:34] [PASSED] missing-context-engine-class
[06:29:34] [PASSED] missing-context-engine-class-or-yes
[06:29:34] [PASSED] missing-context-engine-class-or-or-yes
[06:29:34] =============== [PASSED] xe_rtp_rules_tests ================
[06:29:34] =============== xe_rtp_process_to_sr_tests ================
[06:29:34] [PASSED] coalesce-same-reg
[06:29:34] [PASSED] coalesce-same-reg-literal-and-func
[06:29:34] [PASSED] no-match-no-add
[06:29:34] [PASSED] two-regs-two-entries
[06:29:34] [PASSED] clr-one-set-other
[06:29:34] [PASSED] set-field
[06:29:34] [PASSED] conflict-duplicate
[06:29:34] [PASSED] conflict-not-disjoint
[06:29:34] [PASSED] conflict-not-disjoint-literal-and-func
[06:29:34] [PASSED] conflict-reg-type
[06:29:34] [PASSED] bad-mcr-reg-forced-to-regular
[06:29:34] [PASSED] bad-regular-reg-forced-to-mcr
[06:29:34] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[06:29:34] ================== xe_rtp_process_tests ===================
[06:29:34] [PASSED] active1
[06:29:34] [PASSED] active2
[06:29:34] [PASSED] active-inactive
[06:29:34] [PASSED] inactive-active
[06:29:34] [PASSED] inactive-active-inactive
[06:29:34] [PASSED] inactive-inactive-inactive
[06:29:34] ============== [PASSED] xe_rtp_process_tests ===============
[06:29:34] ===================== [PASSED] xe_rtp ======================
[06:29:34] ==================== xe_wa (1 subtest) =====================
[06:29:34] ======================== xe_wa_gt =========================
[06:29:34] [PASSED] TIGERLAKE B0
[06:29:34] [PASSED] DG1 A0
[06:29:34] [PASSED] DG1 B0
[06:29:34] [PASSED] ALDERLAKE_S A0
[06:29:34] [PASSED] ALDERLAKE_S B0
[06:29:34] [PASSED] ALDERLAKE_S C0
[06:29:34] [PASSED] ALDERLAKE_S D0
[06:29:34] [PASSED] ALDERLAKE_P A0
[06:29:34] [PASSED] ALDERLAKE_P B0
[06:29:34] [PASSED] ALDERLAKE_P C0
[06:29:34] [PASSED] ALDERLAKE_S RPLS D0
[06:29:34] [PASSED] ALDERLAKE_P RPLU E0
[06:29:34] [PASSED] DG2 G10 C0
[06:29:34] [PASSED] DG2 G11 B1
[06:29:34] [PASSED] DG2 G12 A1
[06:29:34] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:29:34] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[06:29:34] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[06:29:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[06:29:34] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[06:29:34] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[06:29:34] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[06:29:34] ==================== [PASSED] xe_wa_gt =====================
[06:29:34] ====================== [PASSED] xe_wa ======================
[06:29:34] ============================================================
[06:29:34] Testing complete. Ran 839 tests: passed: 810, skipped: 29
[06:29:34] Elapsed time: 41.015s total, 1.862s configuring, 38.386s building, 0.721s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[06:29:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:29:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:30:01] Starting KUnit Kernel (1/1)...
[06:30:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:30:01] ============ drm_test_pick_cmdline (2 subtests) ============
[06:30:01] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[06:30:01] =============== drm_test_pick_cmdline_named ===============
[06:30:01] [PASSED] NTSC
[06:30:01] [PASSED] NTSC-J
[06:30:01] [PASSED] PAL
[06:30:01] [PASSED] PAL-M
[06:30:01] =========== [PASSED] drm_test_pick_cmdline_named ===========
[06:30:01] ============== [PASSED] drm_test_pick_cmdline ==============
[06:30:01] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[06:30:01] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[06:30:01] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[06:30:01] =========== drm_validate_clone_mode (2 subtests) ===========
[06:30:01] ============== drm_test_check_in_clone_mode ===============
[06:30:01] [PASSED] in_clone_mode
[06:30:01] [PASSED] not_in_clone_mode
[06:30:01] ========== [PASSED] drm_test_check_in_clone_mode ===========
[06:30:01] =============== drm_test_check_valid_clones ===============
[06:30:01] [PASSED] not_in_clone_mode
[06:30:01] [PASSED] valid_clone
[06:30:01] [PASSED] invalid_clone
[06:30:01] =========== [PASSED] drm_test_check_valid_clones ===========
[06:30:01] ============= [PASSED] drm_validate_clone_mode =============
[06:30:01] ============= drm_validate_modeset (1 subtest) =============
[06:30:01] [PASSED] drm_test_check_connector_changed_modeset
[06:30:01] ============== [PASSED] drm_validate_modeset ===============
[06:30:01] ====== drm_test_bridge_get_current_state (1 subtest) =======
[06:30:01] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[06:30:01] ======== [PASSED] drm_test_bridge_get_current_state ========
[06:30:01] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[06:30:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[06:30:01] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[06:30:01] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[06:30:01] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[06:30:01] ============== drm_bridge_alloc (2 subtests) ===============
[06:30:01] [PASSED] drm_test_drm_bridge_alloc_basic
[06:30:01] [PASSED] drm_test_drm_bridge_alloc_get_put
[06:30:01] ================ [PASSED] drm_bridge_alloc =================
[06:30:01] ============= drm_bridge_bus_fmt (5 subtests) ==============
[06:30:01] [PASSED] drm_test_bridge_rgb_yuv_rgb
[06:30:01] [PASSED] drm_test_bridge_must_convert_to_yuv444
[06:30:01] [PASSED] drm_test_bridge_hdmi_auto_rgb
[06:30:01] [PASSED] drm_test_bridge_auto_first
[06:30:01] [PASSED] drm_test_bridge_rgb_yuv_no_path
[06:30:01] =============== [PASSED] drm_bridge_bus_fmt ================
[06:30:01] ============= drm_cmdline_parser (40 subtests) =============
[06:30:01] [PASSED] drm_test_cmdline_force_d_only
[06:30:01] [PASSED] drm_test_cmdline_force_D_only_dvi
[06:30:01] [PASSED] drm_test_cmdline_force_D_only_hdmi
[06:30:01] [PASSED] drm_test_cmdline_force_D_only_not_digital
[06:30:01] [PASSED] drm_test_cmdline_force_e_only
[06:30:01] [PASSED] drm_test_cmdline_res
[06:30:01] [PASSED] drm_test_cmdline_res_vesa
[06:30:01] [PASSED] drm_test_cmdline_res_vesa_rblank
[06:30:01] [PASSED] drm_test_cmdline_res_rblank
[06:30:01] [PASSED] drm_test_cmdline_res_bpp
[06:30:01] [PASSED] drm_test_cmdline_res_refresh
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[06:30:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[06:30:01] [PASSED] drm_test_cmdline_res_margins_force_on
[06:30:01] [PASSED] drm_test_cmdline_res_vesa_margins
[06:30:01] [PASSED] drm_test_cmdline_name
[06:30:01] [PASSED] drm_test_cmdline_name_bpp
[06:30:01] [PASSED] drm_test_cmdline_name_option
[06:30:01] [PASSED] drm_test_cmdline_name_bpp_option
[06:30:01] [PASSED] drm_test_cmdline_rotate_0
[06:30:01] [PASSED] drm_test_cmdline_rotate_90
[06:30:01] [PASSED] drm_test_cmdline_rotate_180
[06:30:01] [PASSED] drm_test_cmdline_rotate_270
[06:30:01] [PASSED] drm_test_cmdline_hmirror
[06:30:01] [PASSED] drm_test_cmdline_vmirror
[06:30:01] [PASSED] drm_test_cmdline_margin_options
[06:30:01] [PASSED] drm_test_cmdline_multiple_options
[06:30:01] [PASSED] drm_test_cmdline_bpp_extra_and_option
[06:30:01] [PASSED] drm_test_cmdline_extra_and_option
[06:30:01] [PASSED] drm_test_cmdline_freestanding_options
[06:30:01] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[06:30:01] [PASSED] drm_test_cmdline_panel_orientation
[06:30:01] ================ drm_test_cmdline_invalid =================
[06:30:01] [PASSED] margin_only
[06:30:01] [PASSED] interlace_only
[06:30:01] [PASSED] res_missing_x
[06:30:01] [PASSED] res_missing_y
[06:30:01] [PASSED] res_bad_y
[06:30:01] [PASSED] res_missing_y_bpp
[06:30:01] [PASSED] res_bad_bpp
[06:30:01] [PASSED] res_bad_refresh
[06:30:01] [PASSED] res_bpp_refresh_force_on_off
[06:30:01] [PASSED] res_invalid_mode
[06:30:01] [PASSED] res_bpp_wrong_place_mode
[06:30:01] [PASSED] name_bpp_refresh
[06:30:01] [PASSED] name_refresh
[06:30:01] [PASSED] name_refresh_wrong_mode
[06:30:01] [PASSED] name_refresh_invalid_mode
[06:30:01] [PASSED] rotate_multiple
[06:30:01] [PASSED] rotate_invalid_val
[06:30:01] [PASSED] rotate_truncated
[06:30:01] [PASSED] invalid_option
[06:30:01] [PASSED] invalid_tv_option
[06:30:01] [PASSED] truncated_tv_option
[06:30:01] ============ [PASSED] drm_test_cmdline_invalid =============
[06:30:01] =============== drm_test_cmdline_tv_options ===============
[06:30:01] [PASSED] NTSC
[06:30:01] [PASSED] NTSC_443
[06:30:01] [PASSED] NTSC_J
[06:30:01] [PASSED] PAL
[06:30:01] [PASSED] PAL_M
[06:30:01] [PASSED] PAL_N
[06:30:01] [PASSED] SECAM
[06:30:01] [PASSED] MONO_525
[06:30:01] [PASSED] MONO_625
[06:30:01] =========== [PASSED] drm_test_cmdline_tv_options ===========
[06:30:01] =============== [PASSED] drm_cmdline_parser ================
[06:30:01] ========== drmm_connector_hdmi_init (20 subtests) ==========
[06:30:01] [PASSED] drm_test_connector_hdmi_init_valid
[06:30:01] [PASSED] drm_test_connector_hdmi_init_bpc_8
[06:30:01] [PASSED] drm_test_connector_hdmi_init_bpc_10
[06:30:01] [PASSED] drm_test_connector_hdmi_init_bpc_12
[06:30:01] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[06:30:01] [PASSED] drm_test_connector_hdmi_init_bpc_null
[06:30:01] [PASSED] drm_test_connector_hdmi_init_formats_empty
[06:30:01] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[06:30:01] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:30:01] [PASSED] supported_formats=0x9 yuv420_allowed=1
[06:30:01] [PASSED] supported_formats=0x9 yuv420_allowed=0
[06:30:01] [PASSED] supported_formats=0x5 yuv420_allowed=1
[06:30:01] [PASSED] supported_formats=0x5 yuv420_allowed=0
[06:30:01] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[06:30:01] [PASSED] drm_test_connector_hdmi_init_null_ddc
[06:30:01] [PASSED] drm_test_connector_hdmi_init_null_product
[06:30:01] [PASSED] drm_test_connector_hdmi_init_null_vendor
[06:30:01] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[06:30:01] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[06:30:01] [PASSED] drm_test_connector_hdmi_init_product_valid
[06:30:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[06:30:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[06:30:01] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[06:30:01] ========= drm_test_connector_hdmi_init_type_valid =========
[06:30:01] [PASSED] HDMI-A
[06:30:01] [PASSED] HDMI-B
[06:30:01] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[06:30:01] ======== drm_test_connector_hdmi_init_type_invalid ========
[06:30:01] [PASSED] Unknown
[06:30:01] [PASSED] VGA
[06:30:01] [PASSED] DVI-I
[06:30:01] [PASSED] DVI-D
[06:30:01] [PASSED] DVI-A
[06:30:01] [PASSED] Composite
[06:30:01] [PASSED] SVIDEO
[06:30:01] [PASSED] LVDS
[06:30:01] [PASSED] Component
[06:30:01] [PASSED] DIN
[06:30:01] [PASSED] DP
[06:30:01] [PASSED] TV
[06:30:01] [PASSED] eDP
[06:30:01] [PASSED] Virtual
[06:30:01] [PASSED] DSI
[06:30:01] [PASSED] DPI
[06:30:01] [PASSED] Writeback
[06:30:01] [PASSED] SPI
[06:30:01] [PASSED] USB
[06:30:01] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[06:30:01] ============ [PASSED] drmm_connector_hdmi_init =============
[06:30:01] ============= drmm_connector_init (3 subtests) =============
[06:30:01] [PASSED] drm_test_drmm_connector_init
[06:30:01] [PASSED] drm_test_drmm_connector_init_null_ddc
[06:30:01] ========= drm_test_drmm_connector_init_type_valid =========
[06:30:01] [PASSED] Unknown
[06:30:01] [PASSED] VGA
[06:30:01] [PASSED] DVI-I
[06:30:01] [PASSED] DVI-D
[06:30:01] [PASSED] DVI-A
[06:30:01] [PASSED] Composite
[06:30:01] [PASSED] SVIDEO
[06:30:01] [PASSED] LVDS
[06:30:01] [PASSED] Component
[06:30:01] [PASSED] DIN
[06:30:01] [PASSED] DP
[06:30:01] [PASSED] HDMI-A
[06:30:01] [PASSED] HDMI-B
[06:30:01] [PASSED] TV
[06:30:01] [PASSED] eDP
[06:30:01] [PASSED] Virtual
[06:30:01] [PASSED] DSI
[06:30:01] [PASSED] DPI
[06:30:01] [PASSED] Writeback
[06:30:01] [PASSED] SPI
[06:30:01] [PASSED] USB
[06:30:01] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[06:30:01] =============== [PASSED] drmm_connector_init ===============
[06:30:01] ========= drm_connector_dynamic_init (6 subtests) ==========
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_init
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_init_properties
[06:30:01] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[06:30:01] [PASSED] Unknown
[06:30:01] [PASSED] VGA
[06:30:01] [PASSED] DVI-I
[06:30:01] [PASSED] DVI-D
[06:30:01] [PASSED] DVI-A
[06:30:01] [PASSED] Composite
[06:30:01] [PASSED] SVIDEO
[06:30:01] [PASSED] LVDS
[06:30:01] [PASSED] Component
[06:30:01] [PASSED] DIN
[06:30:01] [PASSED] DP
[06:30:01] [PASSED] HDMI-A
[06:30:01] [PASSED] HDMI-B
[06:30:01] [PASSED] TV
[06:30:01] [PASSED] eDP
[06:30:01] [PASSED] Virtual
[06:30:01] [PASSED] DSI
[06:30:01] [PASSED] DPI
[06:30:01] [PASSED] Writeback
[06:30:01] [PASSED] SPI
[06:30:01] [PASSED] USB
[06:30:01] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[06:30:01] ======== drm_test_drm_connector_dynamic_init_name =========
[06:30:01] [PASSED] Unknown
[06:30:01] [PASSED] VGA
[06:30:01] [PASSED] DVI-I
[06:30:01] [PASSED] DVI-D
[06:30:01] [PASSED] DVI-A
[06:30:01] [PASSED] Composite
[06:30:01] [PASSED] SVIDEO
[06:30:01] [PASSED] LVDS
[06:30:01] [PASSED] Component
[06:30:01] [PASSED] DIN
[06:30:01] [PASSED] DP
[06:30:01] [PASSED] HDMI-A
[06:30:01] [PASSED] HDMI-B
[06:30:01] [PASSED] TV
[06:30:01] [PASSED] eDP
[06:30:01] [PASSED] Virtual
[06:30:01] [PASSED] DSI
[06:30:01] [PASSED] DPI
[06:30:01] [PASSED] Writeback
[06:30:01] [PASSED] SPI
[06:30:01] [PASSED] USB
[06:30:01] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[06:30:01] =========== [PASSED] drm_connector_dynamic_init ============
[06:30:01] ==== drm_connector_dynamic_register_early (4 subtests) =====
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[06:30:01] ====== [PASSED] drm_connector_dynamic_register_early =======
[06:30:01] ======= drm_connector_dynamic_register (7 subtests) ========
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[06:30:01] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[06:30:01] ========= [PASSED] drm_connector_dynamic_register ==========
[06:30:01] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[06:30:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[06:30:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[06:30:01] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[06:30:01] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[06:30:01] ========== drm_test_get_tv_mode_from_name_valid ===========
[06:30:01] [PASSED] NTSC
[06:30:01] [PASSED] NTSC-443
[06:30:01] [PASSED] NTSC-J
[06:30:01] [PASSED] PAL
[06:30:01] [PASSED] PAL-M
[06:30:01] [PASSED] PAL-N
[06:30:01] [PASSED] SECAM
[06:30:01] [PASSED] Mono
[06:30:01] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[06:30:01] [PASSED] drm_test_get_tv_mode_from_name_truncated
[06:30:01] ============ [PASSED] drm_get_tv_mode_from_name ============
[06:30:01] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[06:30:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[06:30:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[06:30:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[06:30:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[06:30:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[06:30:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[06:30:01] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[06:30:01] [PASSED] VIC 96
[06:30:01] [PASSED] VIC 97
[06:30:01] [PASSED] VIC 101
[06:30:01] [PASSED] VIC 102
[06:30:01] [PASSED] VIC 106
[06:30:01] [PASSED] VIC 107
[06:30:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[06:30:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[06:30:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[06:30:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[06:30:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[06:30:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[06:30:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[06:30:01] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[06:30:01] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[06:30:01] [PASSED] Automatic
[06:30:01] [PASSED] Full
[06:30:01] [PASSED] Limited 16:235
[06:30:01] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[06:30:01] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[06:30:01] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[06:30:01] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[06:30:01] === drm_test_drm_hdmi_connector_get_output_format_name ====
[06:30:01] [PASSED] RGB
[06:30:01] [PASSED] YUV 4:2:0
[06:30:01] [PASSED] YUV 4:2:2
[06:30:01] [PASSED] YUV 4:4:4
[06:30:01] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[06:30:01] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[06:30:01] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[06:30:01] ============= drm_damage_helper (21 subtests) ==============
[06:30:01] [PASSED] drm_test_damage_iter_no_damage
[06:30:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[06:30:01] [PASSED] drm_test_damage_iter_no_damage_src_moved
[06:30:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[06:30:01] [PASSED] drm_test_damage_iter_no_damage_not_visible
[06:30:01] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[06:30:01] [PASSED] drm_test_damage_iter_no_damage_no_fb
[06:30:01] [PASSED] drm_test_damage_iter_simple_damage
[06:30:01] [PASSED] drm_test_damage_iter_single_damage
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_outside_src
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_src_moved
[06:30:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[06:30:01] [PASSED] drm_test_damage_iter_damage
[06:30:01] [PASSED] drm_test_damage_iter_damage_one_intersect
[06:30:01] [PASSED] drm_test_damage_iter_damage_one_outside
[06:30:01] [PASSED] drm_test_damage_iter_damage_src_moved
[06:30:01] [PASSED] drm_test_damage_iter_damage_not_visible
[06:30:01] ================ [PASSED] drm_damage_helper ================
[06:30:01] ============== drm_dp_mst_helper (3 subtests) ==============
[06:30:01] ============== drm_test_dp_mst_calc_pbn_mode ==============
[06:30:01] [PASSED] Clock 154000 BPP 30 DSC disabled
[06:30:01] [PASSED] Clock 234000 BPP 30 DSC disabled
[06:30:01] [PASSED] Clock 297000 BPP 24 DSC disabled
[06:30:01] [PASSED] Clock 332880 BPP 24 DSC enabled
[06:30:01] [PASSED] Clock 324540 BPP 24 DSC enabled
[06:30:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[06:30:01] ============== drm_test_dp_mst_calc_pbn_div ===============
[06:30:01] [PASSED] Link rate 2000000 lane count 4
[06:30:01] [PASSED] Link rate 2000000 lane count 2
[06:30:01] [PASSED] Link rate 2000000 lane count 1
[06:30:01] [PASSED] Link rate 1350000 lane count 4
[06:30:01] [PASSED] Link rate 1350000 lane count 2
[06:30:01] [PASSED] Link rate 1350000 lane count 1
[06:30:01] [PASSED] Link rate 1000000 lane count 4
[06:30:01] [PASSED] Link rate 1000000 lane count 2
[06:30:01] [PASSED] Link rate 1000000 lane count 1
[06:30:01] [PASSED] Link rate 810000 lane count 4
[06:30:01] [PASSED] Link rate 810000 lane count 2
[06:30:01] [PASSED] Link rate 810000 lane count 1
[06:30:01] [PASSED] Link rate 540000 lane count 4
[06:30:01] [PASSED] Link rate 540000 lane count 2
[06:30:01] [PASSED] Link rate 540000 lane count 1
[06:30:01] [PASSED] Link rate 270000 lane count 4
[06:30:01] [PASSED] Link rate 270000 lane count 2
[06:30:01] [PASSED] Link rate 270000 lane count 1
[06:30:01] [PASSED] Link rate 162000 lane count 4
[06:30:01] [PASSED] Link rate 162000 lane count 2
[06:30:01] [PASSED] Link rate 162000 lane count 1
[06:30:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[06:30:01] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[06:30:01] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[06:30:01] [PASSED] DP_POWER_UP_PHY with port number
[06:30:01] [PASSED] DP_POWER_DOWN_PHY with port number
[06:30:01] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[06:30:01] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[06:30:01] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[06:30:01] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[06:30:01] [PASSED] DP_QUERY_PAYLOAD with port number
[06:30:01] [PASSED] DP_QUERY_PAYLOAD with VCPI
[06:30:01] [PASSED] DP_REMOTE_DPCD_READ with port number
[06:30:01] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[06:30:01] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[06:30:01] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[06:30:01] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[06:30:01] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[06:30:01] [PASSED] DP_REMOTE_I2C_READ with port number
[06:30:01] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[06:30:01] [PASSED] DP_REMOTE_I2C_READ with transactions array
[06:30:01] [PASSED] DP_REMOTE_I2C_WRITE with port number
[06:30:01] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[06:30:01] [PASSED] DP_REMOTE_I2C_WRITE with data array
[06:30:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[06:30:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[06:30:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[06:30:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[06:30:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[06:30:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[06:30:01] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[06:30:01] ================ [PASSED] drm_dp_mst_helper ================
[06:30:01] ================== drm_exec (7 subtests) ===================
[06:30:01] [PASSED] sanitycheck
[06:30:01] [PASSED] test_lock
[06:30:01] [PASSED] test_lock_unlock
[06:30:01] [PASSED] test_duplicates
[06:30:01] [PASSED] test_prepare
[06:30:01] [PASSED] test_prepare_array
[06:30:01] [PASSED] test_multiple_loops
[06:30:01] ==================== [PASSED] drm_exec =====================
[06:30:01] =========== drm_format_helper_test (17 subtests) ===========
[06:30:01] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[06:30:01] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[06:30:01] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[06:30:01] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[06:30:01] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[06:30:01] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[06:30:01] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[06:30:01] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[06:30:01] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[06:30:01] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[06:30:01] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[06:30:01] ============== drm_test_fb_xrgb8888_to_mono ===============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[06:30:01] ==================== drm_test_fb_swab =====================
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ================ [PASSED] drm_test_fb_swab =================
[06:30:01] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[06:30:01] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[06:30:01] [PASSED] single_pixel_source_buffer
[06:30:01] [PASSED] single_pixel_clip_rectangle
[06:30:01] [PASSED] well_known_colors
[06:30:01] [PASSED] destination_pitch
[06:30:01] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[06:30:01] ================= drm_test_fb_clip_offset =================
[06:30:01] [PASSED] pass through
[06:30:01] [PASSED] horizontal offset
[06:30:01] [PASSED] vertical offset
[06:30:01] [PASSED] horizontal and vertical offset
[06:30:01] [PASSED] horizontal offset (custom pitch)
[06:30:01] [PASSED] vertical offset (custom pitch)
[06:30:01] [PASSED] horizontal and vertical offset (custom pitch)
[06:30:01] ============= [PASSED] drm_test_fb_clip_offset =============
[06:30:01] =================== drm_test_fb_memcpy ====================
[06:30:01] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[06:30:01] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[06:30:01] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[06:30:01] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[06:30:01] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[06:30:01] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[06:30:01] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[06:30:01] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[06:30:01] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[06:30:01] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[06:30:01] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[06:30:01] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[06:30:01] =============== [PASSED] drm_test_fb_memcpy ================
[06:30:01] ============= [PASSED] drm_format_helper_test ==============
[06:30:01] ================= drm_format (18 subtests) =================
[06:30:01] [PASSED] drm_test_format_block_width_invalid
[06:30:01] [PASSED] drm_test_format_block_width_one_plane
[06:30:01] [PASSED] drm_test_format_block_width_two_plane
[06:30:01] [PASSED] drm_test_format_block_width_three_plane
[06:30:01] [PASSED] drm_test_format_block_width_tiled
[06:30:01] [PASSED] drm_test_format_block_height_invalid
[06:30:01] [PASSED] drm_test_format_block_height_one_plane
[06:30:01] [PASSED] drm_test_format_block_height_two_plane
[06:30:01] [PASSED] drm_test_format_block_height_three_plane
[06:30:01] [PASSED] drm_test_format_block_height_tiled
[06:30:01] [PASSED] drm_test_format_min_pitch_invalid
[06:30:01] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[06:30:01] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[06:30:01] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[06:30:01] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[06:30:01] [PASSED] drm_test_format_min_pitch_two_plane
[06:30:01] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[06:30:01] [PASSED] drm_test_format_min_pitch_tiled
[06:30:01] =================== [PASSED] drm_format ====================
[06:30:01] ============== drm_framebuffer (10 subtests) ===============
[06:30:01] ========== drm_test_framebuffer_check_src_coords ==========
[06:30:01] [PASSED] Success: source fits into fb
[06:30:01] [PASSED] Fail: overflowing fb with x-axis coordinate
[06:30:01] [PASSED] Fail: overflowing fb with y-axis coordinate
[06:30:01] [PASSED] Fail: overflowing fb with source width
[06:30:01] [PASSED] Fail: overflowing fb with source height
[06:30:01] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[06:30:01] [PASSED] drm_test_framebuffer_cleanup
[06:30:01] =============== drm_test_framebuffer_create ===============
[06:30:01] [PASSED] ABGR8888 normal sizes
[06:30:01] [PASSED] ABGR8888 max sizes
[06:30:01] [PASSED] ABGR8888 pitch greater than min required
[06:30:01] [PASSED] ABGR8888 pitch less than min required
[06:30:01] [PASSED] ABGR8888 Invalid width
[06:30:01] [PASSED] ABGR8888 Invalid buffer handle
[06:30:01] [PASSED] No pixel format
[06:30:01] [PASSED] ABGR8888 Width 0
[06:30:01] [PASSED] ABGR8888 Height 0
[06:30:01] [PASSED] ABGR8888 Out of bound height * pitch combination
[06:30:01] [PASSED] ABGR8888 Large buffer offset
[06:30:01] [PASSED] ABGR8888 Buffer offset for inexistent plane
[06:30:01] [PASSED] ABGR8888 Invalid flag
[06:30:01] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[06:30:01] [PASSED] ABGR8888 Valid buffer modifier
[06:30:01] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[06:30:01] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] NV12 Normal sizes
[06:30:01] [PASSED] NV12 Max sizes
[06:30:01] [PASSED] NV12 Invalid pitch
[06:30:01] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[06:30:01] [PASSED] NV12 different modifier per-plane
[06:30:01] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[06:30:01] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] NV12 Modifier for inexistent plane
[06:30:01] [PASSED] NV12 Handle for inexistent plane
[06:30:01] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[06:30:01] [PASSED] YVU420 Normal sizes
[06:30:01] [PASSED] YVU420 Max sizes
[06:30:01] [PASSED] YVU420 Invalid pitch
[06:30:01] [PASSED] YVU420 Different pitches
[06:30:01] [PASSED] YVU420 Different buffer offsets/pitches
[06:30:01] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[06:30:01] [PASSED] YVU420 Valid modifier
[06:30:01] [PASSED] YVU420 Different modifiers per plane
[06:30:01] [PASSED] YVU420 Modifier for inexistent plane
[06:30:01] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[06:30:01] [PASSED] X0L2 Normal sizes
[06:30:01] [PASSED] X0L2 Max sizes
[06:30:01] [PASSED] X0L2 Invalid pitch
[06:30:01] [PASSED] X0L2 Pitch greater than minimum required
[06:30:01] [PASSED] X0L2 Handle for inexistent plane
[06:30:01] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[06:30:01] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[06:30:01] [PASSED] X0L2 Valid modifier
[06:30:01] [PASSED] X0L2 Modifier for inexistent plane
[06:30:01] =========== [PASSED] drm_test_framebuffer_create ===========
[06:30:01] [PASSED] drm_test_framebuffer_free
[06:30:01] [PASSED] drm_test_framebuffer_init
[06:30:01] [PASSED] drm_test_framebuffer_init_bad_format
[06:30:01] [PASSED] drm_test_framebuffer_init_dev_mismatch
[06:30:01] [PASSED] drm_test_framebuffer_lookup
[06:30:01] [PASSED] drm_test_framebuffer_lookup_inexistent
[06:30:01] [PASSED] drm_test_framebuffer_modifiers_not_supported
[06:30:01] ================= [PASSED] drm_framebuffer =================
[06:30:01] ================ drm_gem_shmem (8 subtests) ================
[06:30:01] [PASSED] drm_gem_shmem_test_obj_create
[06:30:01] [PASSED] drm_gem_shmem_test_obj_create_private
[06:30:01] [PASSED] drm_gem_shmem_test_pin_pages
[06:30:01] [PASSED] drm_gem_shmem_test_vmap
[06:30:01] [PASSED] drm_gem_shmem_test_get_sg_table
[06:30:01] [PASSED] drm_gem_shmem_test_get_pages_sgt
[06:30:01] [PASSED] drm_gem_shmem_test_madvise
[06:30:01] [PASSED] drm_gem_shmem_test_purge
[06:30:01] ================== [PASSED] drm_gem_shmem ==================
[06:30:01] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[06:30:01] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[06:30:01] [PASSED] Automatic
[06:30:01] [PASSED] Full
[06:30:01] [PASSED] Limited 16:235
[06:30:01] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[06:30:01] [PASSED] drm_test_check_disable_connector
[06:30:01] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[06:30:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[06:30:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[06:30:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[06:30:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[06:30:01] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[06:30:01] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[06:30:01] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[06:30:01] [PASSED] drm_test_check_output_bpc_dvi
[06:30:01] [PASSED] drm_test_check_output_bpc_format_vic_1
[06:30:01] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[06:30:01] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[06:30:01] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[06:30:01] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[06:30:01] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[06:30:01] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[06:30:01] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[06:30:01] ============ drm_test_check_hdmi_color_format =============
[06:30:01] [PASSED] AUTO -> RGB
[06:30:01] [PASSED] YCBCR422 -> YUV422
[06:30:01] [PASSED] YCBCR420 -> YUV420
[06:30:01] [PASSED] YCBCR444 -> YUV444
[06:30:01] [PASSED] RGB -> RGB
[06:30:01] ======== [PASSED] drm_test_check_hdmi_color_format =========
[06:30:01] ======== drm_test_check_hdmi_color_format_420_only ========
[06:30:01] [PASSED] RGB should fail
[06:30:01] [PASSED] YUV444 should fail
[06:30:01] [PASSED] YUV422 should fail
[06:30:01] [PASSED] YUV420 should work
[06:30:01] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[06:30:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[06:30:01] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[06:30:01] [PASSED] drm_test_check_broadcast_rgb_value
[06:30:01] [PASSED] drm_test_check_bpc_8_value
[06:30:01] [PASSED] drm_test_check_bpc_10_value
[06:30:01] [PASSED] drm_test_check_bpc_12_value
[06:30:01] [PASSED] drm_test_check_format_value
[06:30:01] [PASSED] drm_test_check_tmds_char_value
[06:30:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[06:30:01] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[06:30:01] [PASSED] drm_test_check_mode_valid
[06:30:01] [PASSED] drm_test_check_mode_valid_reject
[06:30:01] [PASSED] drm_test_check_mode_valid_reject_rate
[06:30:01] [PASSED] drm_test_check_mode_valid_reject_max_clock
[06:30:01] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[06:30:01] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[06:30:01] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[06:30:01] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[06:30:01] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[06:30:01] [PASSED] drm_test_check_infoframes
[06:30:01] [PASSED] drm_test_check_reject_avi_infoframe
[06:30:01] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[06:30:01] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[06:30:01] [PASSED] drm_test_check_reject_audio_infoframe
[06:30:01] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[06:30:01] ================= drm_managed (2 subtests) =================
[06:30:01] [PASSED] drm_test_managed_release_action
[06:30:01] [PASSED] drm_test_managed_run_action
[06:30:01] =================== [PASSED] drm_managed ===================
[06:30:01] =================== drm_mm (6 subtests) ====================
[06:30:01] [PASSED] drm_test_mm_init
[06:30:01] [PASSED] drm_test_mm_debug
[06:30:01] [PASSED] drm_test_mm_align32
[06:30:01] [PASSED] drm_test_mm_align64
[06:30:01] [PASSED] drm_test_mm_lowest
[06:30:01] [PASSED] drm_test_mm_highest
[06:30:01] ===================== [PASSED] drm_mm ======================
[06:30:01] ============= drm_modes_analog_tv (5 subtests) =============
[06:30:01] [PASSED] drm_test_modes_analog_tv_mono_576i
[06:30:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[06:30:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[06:30:01] [PASSED] drm_test_modes_analog_tv_pal_576i
[06:30:01] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[06:30:01] =============== [PASSED] drm_modes_analog_tv ===============
[06:30:01] ============== drm_panic_helper (3 subtests) ===============
[06:30:01] ============= drm_test_panic_screen_user_map ==============
[06:30:01] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:30:01] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:30:01] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:30:01] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:30:01] ========= [PASSED] drm_test_panic_screen_user_map ==========
[06:30:01] ============= drm_test_panic_screen_user_page =============
[06:30:01] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:30:01] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:30:01] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:30:01] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:30:02] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:30:02] ========= [PASSED] drm_test_panic_screen_user_page =========
[06:30:02] ========== drm_test_panic_screen_user_set_pixel ===========
[06:30:02] [PASSED] Panic screen user, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen user, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen user, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen user, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:30:02] [PASSED] Panic screen user, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:30:02] [PASSED] Panic screen kmsg, mode: 1024 x 768 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen kmsg, mode: 494 x 494 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen kmsg, mode: 1920 x 1080 XR24 little-endian (0x34325258)
[06:30:02] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG16 little-endian (0x36314752)
[06:30:02] [PASSED] Panic screen kmsg, mode: 1024 x 768 RG24 little-endian (0x34324752)
[06:30:02] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[06:30:02] ================ [PASSED] drm_panic_helper =================
[06:30:02] ============== drm_plane_helper (2 subtests) ===============
[06:30:02] =============== drm_test_check_plane_state ================
[06:30:02] [PASSED] clipping_simple
[06:30:02] [PASSED] clipping_rotate_reflect
[06:30:02] [PASSED] positioning_simple
[06:30:02] [PASSED] upscaling
[06:30:02] [PASSED] downscaling
[06:30:02] [PASSED] rounding1
[06:30:02] [PASSED] rounding2
[06:30:02] [PASSED] rounding3
[06:30:02] [PASSED] rounding4
[06:30:02] =========== [PASSED] drm_test_check_plane_state ============
[06:30:02] =========== drm_test_check_invalid_plane_state ============
[06:30:02] [PASSED] positioning_invalid
[06:30:02] [PASSED] upscaling_invalid
[06:30:02] [PASSED] downscaling_invalid
[06:30:02] ======= [PASSED] drm_test_check_invalid_plane_state ========
[06:30:02] ================ [PASSED] drm_plane_helper =================
[06:30:02] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[06:30:02] ====== drm_test_connector_helper_tv_get_modes_check =======
[06:30:02] [PASSED] None
[06:30:02] [PASSED] PAL
[06:30:02] [PASSED] NTSC
[06:30:02] [PASSED] Both, NTSC Default
[06:30:02] [PASSED] Both, PAL Default
[06:30:02] [PASSED] Both, NTSC Default, with PAL on command-line
[06:30:02] [PASSED] Both, PAL Default, with NTSC on command-line
[06:30:02] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[06:30:02] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[06:30:02] ================== drm_rect (9 subtests) ===================
[06:30:02] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[06:30:02] [PASSED] drm_test_rect_clip_scaled_not_clipped
[06:30:02] [PASSED] drm_test_rect_clip_scaled_clipped
[06:30:02] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[06:30:02] ================= drm_test_rect_intersect =================
[06:30:02] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[06:30:02] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[06:30:02] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[06:30:02] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[06:30:02] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[06:30:02] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[06:30:02] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[06:30:02] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[06:30:02] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[06:30:02] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[06:30:02] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[06:30:02] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[06:30:02] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[06:30:02] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[06:30:02] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[06:30:02] ============= [PASSED] drm_test_rect_intersect =============
[06:30:02] ================ drm_test_rect_calc_hscale ================
[06:30:02] [PASSED] normal use
[06:30:02] [PASSED] out of max range
[06:30:02] [PASSED] out of min range
[06:30:02] [PASSED] zero dst
[06:30:02] [PASSED] negative src
[06:30:02] [PASSED] negative dst
[06:30:02] ============ [PASSED] drm_test_rect_calc_hscale ============
[06:30:02] ================ drm_test_rect_calc_vscale ================
[06:30:02] [PASSED] normal use
[06:30:02] [PASSED] out of max range
[06:30:02] [PASSED] out of min range
[06:30:02] [PASSED] zero dst
[06:30:02] [PASSED] negative src
[06:30:02] [PASSED] negative dst
[06:30:02] ============ [PASSED] drm_test_rect_calc_vscale ============
[06:30:02] ================== drm_test_rect_rotate ===================
[06:30:02] [PASSED] reflect-x
[06:30:02] [PASSED] reflect-y
[06:30:02] [PASSED] rotate-0
[06:30:02] [PASSED] rotate-90
[06:30:02] [PASSED] rotate-180
[06:30:02] [PASSED] rotate-270
[06:30:02] ============== [PASSED] drm_test_rect_rotate ===============
[06:30:02] ================ drm_test_rect_rotate_inv =================
[06:30:02] [PASSED] reflect-x
[06:30:02] [PASSED] reflect-y
[06:30:02] [PASSED] rotate-0
[06:30:02] [PASSED] rotate-90
[06:30:02] [PASSED] rotate-180
[06:30:02] [PASSED] rotate-270
[06:30:02] ============ [PASSED] drm_test_rect_rotate_inv =============
[06:30:02] ==================== [PASSED] drm_rect =====================
[06:30:02] ============ drm_sysfb_modeset_test (1 subtest) ============
[06:30:02] ============ drm_test_sysfb_build_fourcc_list =============
[06:30:02] [PASSED] no native formats
[06:30:02] [PASSED] XRGB8888 as native format
[06:30:02] [PASSED] remove duplicates
[06:30:02] [PASSED] convert alpha formats
[06:30:02] [PASSED] random formats
[06:30:02] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[06:30:02] ============= [PASSED] drm_sysfb_modeset_test ==============
[06:30:02] ================== drm_fixp (2 subtests) ===================
[06:30:02] [PASSED] drm_test_int2fixp
[06:30:02] [PASSED] drm_test_sm2fixp
[06:30:02] ==================== [PASSED] drm_fixp =====================
[06:30:02] ============================================================
[06:30:02] Testing complete. Ran 667 tests: passed: 667
[06:30:02] Elapsed time: 27.205s total, 1.804s configuring, 24.934s building, 0.455s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[06:30:02] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:30:04] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:30:14] Starting KUnit Kernel (1/1)...
[06:30:14] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:30:14] ================= ttm_device (5 subtests) ==================
[06:30:14] [PASSED] ttm_device_init_basic
[06:30:14] [PASSED] ttm_device_init_multiple
[06:30:14] [PASSED] ttm_device_fini_basic
[06:30:14] [PASSED] ttm_device_init_no_vma_man
[06:30:14] ================== ttm_device_init_pools ==================
[06:30:14] [PASSED] No DMA allocations, no DMA32 required
[06:30:14] [PASSED] DMA allocations, DMA32 required
[06:30:14] [PASSED] No DMA allocations, DMA32 required
[06:30:14] [PASSED] DMA allocations, no DMA32 required
[06:30:14] ============== [PASSED] ttm_device_init_pools ==============
[06:30:14] =================== [PASSED] ttm_device ====================
[06:30:14] ================== ttm_pool (8 subtests) ===================
[06:30:14] ================== ttm_pool_alloc_basic ===================
[06:30:14] [PASSED] One page
[06:30:14] [PASSED] More than one page
[06:30:14] [PASSED] Above the allocation limit
[06:30:14] [PASSED] One page, with coherent DMA mappings enabled
[06:30:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:30:14] ============== [PASSED] ttm_pool_alloc_basic ===============
[06:30:14] ============== ttm_pool_alloc_basic_dma_addr ==============
[06:30:14] [PASSED] One page
[06:30:14] [PASSED] More than one page
[06:30:14] [PASSED] Above the allocation limit
[06:30:14] [PASSED] One page, with coherent DMA mappings enabled
[06:30:14] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[06:30:14] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[06:30:14] [PASSED] ttm_pool_alloc_order_caching_match
[06:30:14] [PASSED] ttm_pool_alloc_caching_mismatch
[06:30:14] [PASSED] ttm_pool_alloc_order_mismatch
[06:30:14] [PASSED] ttm_pool_free_dma_alloc
[06:30:14] [PASSED] ttm_pool_free_no_dma_alloc
[06:30:14] [PASSED] ttm_pool_fini_basic
[06:30:14] ==================== [PASSED] ttm_pool =====================
[06:30:14] ================ ttm_resource (8 subtests) =================
[06:30:14] ================= ttm_resource_init_basic =================
[06:30:14] [PASSED] Init resource in TTM_PL_SYSTEM
[06:30:14] [PASSED] Init resource in TTM_PL_VRAM
[06:30:14] [PASSED] Init resource in a private placement
[06:30:14] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[06:30:14] ============= [PASSED] ttm_resource_init_basic =============
[06:30:14] [PASSED] ttm_resource_init_pinned
[06:30:14] [PASSED] ttm_resource_fini_basic
[06:30:14] [PASSED] ttm_resource_manager_init_basic
[06:30:14] [PASSED] ttm_resource_manager_usage_basic
[06:30:14] [PASSED] ttm_resource_manager_set_used_basic
[06:30:14] [PASSED] ttm_sys_man_alloc_basic
[06:30:14] [PASSED] ttm_sys_man_free_basic
[06:30:14] ================== [PASSED] ttm_resource ===================
[06:30:14] =================== ttm_tt (15 subtests) ===================
[06:30:14] ==================== ttm_tt_init_basic ====================
[06:30:14] [PASSED] Page-aligned size
[06:30:14] [PASSED] Extra pages requested
[06:30:14] ================ [PASSED] ttm_tt_init_basic ================
[06:30:14] [PASSED] ttm_tt_init_misaligned
[06:30:14] [PASSED] ttm_tt_fini_basic
[06:30:14] [PASSED] ttm_tt_fini_sg
[06:30:14] [PASSED] ttm_tt_fini_shmem
[06:30:14] [PASSED] ttm_tt_create_basic
[06:30:14] [PASSED] ttm_tt_create_invalid_bo_type
[06:30:14] [PASSED] ttm_tt_create_ttm_exists
[06:30:14] [PASSED] ttm_tt_create_failed
[06:30:14] [PASSED] ttm_tt_destroy_basic
[06:30:14] [PASSED] ttm_tt_populate_null_ttm
[06:30:14] [PASSED] ttm_tt_populate_populated_ttm
[06:30:14] [PASSED] ttm_tt_unpopulate_basic
[06:30:14] [PASSED] ttm_tt_unpopulate_empty_ttm
[06:30:14] [PASSED] ttm_tt_swapin_basic
[06:30:14] ===================== [PASSED] ttm_tt ======================
[06:30:14] =================== ttm_bo (14 subtests) ===================
[06:30:14] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[06:30:14] [PASSED] Cannot be interrupted and sleeps
[06:30:14] [PASSED] Cannot be interrupted, locks straight away
[06:30:14] [PASSED] Can be interrupted, sleeps
[06:30:14] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[06:30:14] [PASSED] ttm_bo_reserve_locked_no_sleep
[06:30:14] [PASSED] ttm_bo_reserve_no_wait_ticket
[06:30:14] [PASSED] ttm_bo_reserve_double_resv
[06:30:14] [PASSED] ttm_bo_reserve_interrupted
[06:30:14] [PASSED] ttm_bo_reserve_deadlock
[06:30:14] [PASSED] ttm_bo_unreserve_basic
[06:30:14] [PASSED] ttm_bo_unreserve_pinned
[06:30:14] [PASSED] ttm_bo_unreserve_bulk
[06:30:14] [PASSED] ttm_bo_fini_basic
[06:30:14] [PASSED] ttm_bo_fini_shared_resv
[06:30:14] [PASSED] ttm_bo_pin_basic
[06:30:14] [PASSED] ttm_bo_pin_unpin_resource
[06:30:14] [PASSED] ttm_bo_multiple_pin_one_unpin
[06:30:14] ===================== [PASSED] ttm_bo ======================
[06:30:14] ============== ttm_bo_validate (22 subtests) ===============
[06:30:14] ============== ttm_bo_init_reserved_sys_man ===============
[06:30:14] [PASSED] Buffer object for userspace
[06:30:14] [PASSED] Kernel buffer object
[06:30:14] [PASSED] Shared buffer object
[06:30:14] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[06:30:14] ============== ttm_bo_init_reserved_mock_man ==============
[06:30:14] [PASSED] Buffer object for userspace
[06:30:14] [PASSED] Kernel buffer object
[06:30:14] [PASSED] Shared buffer object
[06:30:14] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[06:30:14] [PASSED] ttm_bo_init_reserved_resv
[06:30:14] ================== ttm_bo_validate_basic ==================
[06:30:14] [PASSED] Buffer object for userspace
[06:30:14] [PASSED] Kernel buffer object
[06:30:14] [PASSED] Shared buffer object
[06:30:14] ============== [PASSED] ttm_bo_validate_basic ==============
[06:30:14] [PASSED] ttm_bo_validate_invalid_placement
[06:30:14] ============= ttm_bo_validate_same_placement ==============
[06:30:14] [PASSED] System manager
[06:30:14] [PASSED] VRAM manager
[06:30:14] ========= [PASSED] ttm_bo_validate_same_placement ==========
[06:30:14] [PASSED] ttm_bo_validate_failed_alloc
[06:30:14] [PASSED] ttm_bo_validate_pinned
[06:30:14] [PASSED] ttm_bo_validate_busy_placement
[06:30:14] ================ ttm_bo_validate_multihop =================
[06:30:14] [PASSED] Buffer object for userspace
[06:30:14] [PASSED] Kernel buffer object
[06:30:14] [PASSED] Shared buffer object
[06:30:14] ============ [PASSED] ttm_bo_validate_multihop =============
[06:30:14] ========== ttm_bo_validate_no_placement_signaled ==========
[06:30:14] [PASSED] Buffer object in system domain, no page vector
[06:30:14] [PASSED] Buffer object in system domain with an existing page vector
[06:30:14] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[06:30:14] ======== ttm_bo_validate_no_placement_not_signaled ========
[06:30:14] [PASSED] Buffer object for userspace
[06:30:14] [PASSED] Kernel buffer object
[06:30:14] [PASSED] Shared buffer object
[06:30:14] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[06:30:14] [PASSED] ttm_bo_validate_move_fence_signaled
[06:30:14] ========= ttm_bo_validate_move_fence_not_signaled =========
[06:30:14] [PASSED] Waits for GPU
[06:30:14] [PASSED] Tries to lock straight away
[06:30:14] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[06:30:14] [PASSED] ttm_bo_validate_swapout
[06:30:14] [PASSED] ttm_bo_validate_happy_evict
[06:30:14] [PASSED] ttm_bo_validate_all_pinned_evict
[06:30:14] [PASSED] ttm_bo_validate_allowed_only_evict
[06:30:14] [PASSED] ttm_bo_validate_deleted_evict
[06:30:14] [PASSED] ttm_bo_validate_busy_domain_evict
[06:30:14] [PASSED] ttm_bo_validate_evict_gutting
[06:30:14] [PASSED] ttm_bo_validate_recrusive_evict
[06:30:14] ================= [PASSED] ttm_bo_validate =================
[06:30:14] ============================================================
[06:30:14] Testing complete. Ran 102 tests: passed: 102
[06:30:14] Elapsed time: 12.193s total, 1.878s configuring, 10.100s building, 0.180s running
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[06:30:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[06:30:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[06:30:25] Starting KUnit Kernel (1/1)...
[06:30:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[06:30:25] =============== dma-buf-fence (12 subtests) ================
[06:30:25] [PASSED] test_sanitycheck
[06:30:25] [PASSED] test_signaling
[06:30:25] [PASSED] test_add_callback
[06:30:25] [PASSED] test_late_add_callback
[06:30:25] [PASSED] test_rm_callback
[06:30:25] [PASSED] test_late_rm_callback
[06:30:25] [PASSED] test_status
[06:30:25] [PASSED] test_error
[06:30:25] [PASSED] test_wait
[06:30:25] [PASSED] test_wait_timeout
[06:30:25] [PASSED] test_stub
[06:30:25] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[06:30:25] ================== [PASSED] dma-buf-fence ==================
[06:30:25] ============ dma-buf-fence-chain (11 subtests) =============
[06:30:25] [PASSED] test_sanitycheck
[06:30:25] [PASSED] test_find_seqno
[06:30:25] [PASSED] test_find_signaled
[06:30:25] [PASSED] test_find_out_of_order
[06:30:30] [PASSED] test_find_gap
[06:30:30] [PASSED] test_find_race
[06:30:30] [PASSED] test_signal_forward
[06:30:30] [PASSED] test_signal_backward
[06:30:30] [PASSED] test_wait_forward
[06:30:30] [PASSED] test_wait_backward
[06:30:30] [PASSED] test_wait_random
[06:30:30] =============== [PASSED] dma-buf-fence-chain ===============
[06:30:30] ============ dma-buf-fence-unwrap (11 subtests) ============
[06:30:30] [PASSED] test_sanitycheck
[06:30:30] [PASSED] test_unwrap_array
[06:30:30] [PASSED] test_unwrap_chain
[06:30:30] [PASSED] test_unwrap_chain_array
[06:30:30] [PASSED] test_unwrap_merge
[06:30:30] [PASSED] test_unwrap_merge_duplicate
[06:30:30] [PASSED] test_unwrap_merge_seqno
[06:30:30] [PASSED] test_unwrap_merge_order
[06:30:30] [PASSED] test_unwrap_merge_complex
[06:30:30] [PASSED] test_unwrap_merge_complex_seqno
[06:30:30] [PASSED] test_dedup_empty
[06:30:30] ============== [PASSED] dma-buf-fence-unwrap ===============
[06:30:30] ================ dma-buf-resv (5 subtests) =================
[06:30:30] [PASSED] test_sanitycheck
[06:30:30] ===================== test_signaling ======================
[06:30:30] [PASSED] kernel
[06:30:30] [PASSED] write
[06:30:30] [PASSED] read
[06:30:30] [PASSED] bookkeep
[06:30:30] ================= [PASSED] test_signaling ==================
[06:30:30] ====================== test_for_each ======================
[06:30:30] [PASSED] kernel
[06:30:30] [PASSED] write
[06:30:30] [PASSED] read
[06:30:30] [PASSED] bookkeep
[06:30:30] ================== [PASSED] test_for_each ==================
[06:30:30] ================= test_for_each_unlocked ==================
[06:30:30] [PASSED] kernel
[06:30:30] [PASSED] write
[06:30:30] [PASSED] read
[06:30:30] [PASSED] bookkeep
[06:30:30] ============= [PASSED] test_for_each_unlocked ==============
[06:30:30] ===================== test_get_fences =====================
[06:30:30] [PASSED] kernel
[06:30:30] [PASSED] write
[06:30:30] [PASSED] read
[06:30:30] [PASSED] bookkeep
[06:30:30] ================= [PASSED] test_get_fences =================
[06:30:30] ================== [PASSED] dma-buf-resv ===================
[06:30:30] ============================================================
[06:30:30] Testing complete. Ran 51 tests: passed: 50, skipped: 1
[06:30:30] Elapsed time: 15.921s total, 1.905s configuring, 8.744s building, 5.256s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 42+ messages in thread
* ✓ Xe.CI.BAT: success for Handle non-fatal errors routed via IRQ (rev2)
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (9 preceding siblings ...)
2026-10-26 6:30 ` ✓ CI.KUnit: success for Handle non-fatal errors routed via IRQ (rev2) Patchwork
@ 2026-10-26 7:05 ` Patchwork
2026-10-26 8:55 ` ✗ Xe.CI.FULL: failure " Patchwork
11 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2026-10-26 7:05 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 915 bytes --]
== Series Details ==
Series: Handle non-fatal errors routed via IRQ (rev2)
URL : https://patchwork.freedesktop.org/series/173001/
State : success
== Summary ==
CI Bug Log - changes from xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a_BAT -> xe-pw-173001v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (15 -> 15)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* IGT: IGT_9163 -> IGT_9164
* Linux: xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a -> xe-pw-173001v2
IGT_9163: 9163
IGT_9164: 9164
xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a: d56ff005f0d16ec136ee31fe3238eb447fefdc1a
xe-pw-173001v2: 173001v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/index.html
[-- Attachment #2: Type: text/html, Size: 1477 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* ✗ Xe.CI.FULL: failure for Handle non-fatal errors routed via IRQ (rev2)
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
` (10 preceding siblings ...)
2026-10-26 7:05 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-10-26 8:55 ` Patchwork
11 siblings, 0 replies; 42+ messages in thread
From: Patchwork @ 2026-10-26 8:55 UTC (permalink / raw)
To: Riana Tauro; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 57369 bytes --]
== Series Details ==
Series: Handle non-fatal errors routed via IRQ (rev2)
URL : https://patchwork.freedesktop.org/series/173001/
State : failure
== Summary ==
CI Bug Log - changes from xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a_FULL -> xe-pw-173001v2_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-173001v2_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-173001v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (3 -> 3)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-173001v2_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_setmode@basic@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-7/igt@kms_setmode@basic@pipe-a-dp-1.html
Known issues
------------
Here are the changes found in xe-pw-173001v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@alternate-sync-async-flip-atomic:
- shard-bmg: [PASS][2] -> [FAIL][3] ([Intel XE#3718] / [Intel XE#6078])
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
* igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2:
- shard-bmg: [PASS][4] -> [FAIL][5] ([Intel XE#6078])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-5/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-d-dp-2.html
* igt@kms_async_flips@async-flip-hang@pipe-a-edp-1:
- shard-ptl: [PASS][6] -> [DMESG-FAIL][7] ([Intel XE#1727]) +1 other test dmesg-fail
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-4/igt@kms_async_flips@async-flip-hang@pipe-a-edp-1.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@kms_async_flips@async-flip-hang@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-ptl: NOTRUN -> [SKIP][8] ([Intel XE#5901]) +3 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-3/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-lnl: NOTRUN -> [SKIP][9] ([Intel XE#1407])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#607] / [Intel XE#7361])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-6/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-ptl: NOTRUN -> [SKIP][11] ([Intel XE#5808]) +5 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
- shard-bmg: NOTRUN -> [SKIP][12] ([Intel XE#1124]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-lnl: NOTRUN -> [SKIP][13] ([Intel XE#1124]) +1 other test skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p:
- shard-ptl: NOTRUN -> [SKIP][14] ([Intel XE#7679])
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_bw@connected-linear-tiling-3-displays-target-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#7679])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-9/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html
* igt@kms_bw@linear-tiling-4-displays-target-3840x2160p:
- shard-ptl: NOTRUN -> [SKIP][16] ([Intel XE#367])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_bw@linear-tiling-4-displays-target-3840x2160p.html
* igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
- shard-lnl: NOTRUN -> [SKIP][17] ([Intel XE#2887]) +2 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc:
- shard-ptl: NOTRUN -> [SKIP][18] ([Intel XE#5822]) +5 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#3432])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2887]) +4 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-b-dp-1:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2652]) +3 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-7/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-b-dp-1.html
* igt@kms_chamelium_audio@hdmi-audio-after-suspend:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2252]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-9/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-lnl: NOTRUN -> [SKIP][23] ([Intel XE#306] / [Intel XE#7358])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-3/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim:
- shard-ptl: NOTRUN -> [SKIP][24] ([Intel XE#8391]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-3/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lim.html
* igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lim-lut1d:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#7358]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-7/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lim-lut1d.html
* igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4-lut1d:
- shard-lnl: NOTRUN -> [SKIP][26] ([Intel XE#7358])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-4/igt@kms_chamelium_color_pipeline@plane-lut1d-ctm3x4-lut1d.html
* igt@kms_chamelium_edid@dp-mode-timings:
- shard-ptl: NOTRUN -> [SKIP][27] ([Intel XE#2252]) +1 other test skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@kms_chamelium_edid@dp-mode-timings.html
* igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-a-plane-3:
- shard-ptl: NOTRUN -> [SKIP][28] ([Intel XE#6969]) +7 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-a-plane-3.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2390] / [Intel XE#6974])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-3/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-ptl: NOTRUN -> [SKIP][30] ([Intel XE#5832] / [Intel XE#6974])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@dp-mst-type-0-suspend-resume:
- shard-ptl: NOTRUN -> [SKIP][31] ([Intel XE#6974])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html
* igt@kms_content_protection@legacy:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#7642])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][33] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-8/igt@kms_content_protection@lic-type-0-hdcp14@pipe-a-dp-2.html
* igt@kms_content_protection@suspend-resume@pipe-a-dp-1:
- shard-bmg: NOTRUN -> [FAIL][34] ([Intel XE#3304])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-7/igt@kms_content_protection@suspend-resume@pipe-a-dp-1.html
* igt@kms_cursor_crc@cursor-onscreen-32x10:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2320]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-32x10.html
* igt@kms_cursor_crc@cursor-onscreen-512x170:
- shard-lnl: NOTRUN -> [SKIP][36] ([Intel XE#2321] / [Intel XE#7355])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
* igt@kms_cursor_crc@cursor-random-256x85:
- shard-lnl: NOTRUN -> [SKIP][37] ([Intel XE#1424])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-3/igt@kms_cursor_crc@cursor-random-256x85.html
* igt@kms_cursor_crc@cursor-rapid-movement-256x85:
- shard-ptl: NOTRUN -> [SKIP][38] ([Intel XE#5900]) +3 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-3/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#2321] / [Intel XE#7355])
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-3/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-ptl: NOTRUN -> [SKIP][40] ([Intel XE#5962])
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-lnl: NOTRUN -> [SKIP][41] ([Intel XE#309] / [Intel XE#7343])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-ptl: NOTRUN -> [SKIP][42] ([Intel XE#9533])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-lnl: NOTRUN -> [SKIP][43] ([Intel XE#8265]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-3/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_feature_discovery@chamelium:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#2372] / [Intel XE#7359])
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-9/igt@kms_feature_discovery@chamelium.html
- shard-ptl: NOTRUN -> [SKIP][45] ([Intel XE#7359])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-5/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-4x:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#1138] / [Intel XE#7344])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-6/igt@kms_feature_discovery@display-4x.html
- shard-ptl: NOTRUN -> [SKIP][47] ([Intel XE#7344])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@kms_feature_discovery@display-4x.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-ptl: NOTRUN -> [SKIP][48] ([Intel XE#2316]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-5/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][49] ([Intel XE#7178] / [Intel XE#7351])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling:
- shard-ptl: NOTRUN -> [SKIP][50] ([Intel XE#7178]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
- shard-lnl: NOTRUN -> [SKIP][51] ([Intel XE#7178] / [Intel XE#7351])
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc:
- shard-ptl: NOTRUN -> [SKIP][52] ([Intel XE#5800] / [Intel XE#6312]) +6 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt:
- shard-ptl: NOTRUN -> [SKIP][53] ([Intel XE#6312]) +7 other tests skip
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move:
- shard-lnl: NOTRUN -> [SKIP][54] ([Intel XE#656] / [Intel XE#7905]) +4 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-ptl: NOTRUN -> [SKIP][55] ([Intel XE#5812]) +47 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][56] ([Intel XE#7061] / [Intel XE#7356])
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html
- shard-ptl: NOTRUN -> [SKIP][57] ([Intel XE#7061] / [Intel XE#7356]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-bmg: NOTRUN -> [SKIP][58] ([Intel XE#4141]) +6 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt:
- shard-lnl: NOTRUN -> [SKIP][59] ([Intel XE#6312] / [Intel XE#651])
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen:
- shard-bmg: NOTRUN -> [SKIP][60] ([Intel XE#2311]) +22 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][61] ([Intel XE#6312])
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][62] ([Intel XE#7061])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#7061]) +2 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-pgflip-blt:
- shard-ptl: NOTRUN -> [SKIP][64] ([Intel XE#7865]) +13 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-msflip-blt:
- shard-lnl: NOTRUN -> [SKIP][65] ([Intel XE#7905]) +7 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-render:
- shard-ptl: NOTRUN -> [SKIP][66] ([Intel XE#7061]) +1 other test skip
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][67] ([Intel XE#2313]) +15 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psrhdr-rgb101010-draw-render:
- shard-lnl: NOTRUN -> [SKIP][68] ([Intel XE#7865]) +4 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-1/igt@kms_frontbuffer_tracking@psrhdr-rgb101010-draw-render.html
* igt@kms_hdmi_audio_bw@suspend-mem-audio-recovery:
- shard-ptl: NOTRUN -> [SKIP][69] ([Intel XE#9312])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@kms_hdmi_audio_bw@suspend-mem-audio-recovery.html
* igt@kms_joiner@basic-big-joiner:
- shard-lnl: NOTRUN -> [SKIP][70] ([Intel XE#6901])
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@invalid-modeset-force-ultra-joiner:
- shard-bmg: NOTRUN -> [SKIP][71] ([Intel XE#6911] / [Intel XE#7466])
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-10/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
* igt@kms_mst@mst-suspend-read-crc:
- shard-ptl: NOTRUN -> [SKIP][72] ([Intel XE#8348])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@kms_mst@mst-suspend-read-crc.html
* igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier:
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#7283])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-1/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier.html
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#7283]) +1 other test skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-6/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html
- shard-ptl: NOTRUN -> [SKIP][75] ([Intel XE#7283])
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html
* igt@kms_plane_lowres@tiling-x:
- shard-ptl: NOTRUN -> [SKIP][76] ([Intel XE#5946])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_plane_lowres@tiling-x.html
* igt@kms_plane_multiple@2x-tiling-none:
- shard-ptl: NOTRUN -> [SKIP][77] ([Intel XE#4596] / [Intel XE#5854])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_plane_multiple@2x-tiling-none.html
* igt@kms_plane_multiple@tiling-yf:
- shard-ptl: NOTRUN -> [SKIP][78] ([Intel XE#5020])
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-ptl: NOTRUN -> [SKIP][79] ([Intel XE#5879] / [Intel XE#7343])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5:
- shard-lnl: NOTRUN -> [SKIP][80] ([Intel XE#2763] / [Intel XE#6886]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-8/igt@kms_plane_scaling@planes-downscale-factor-0-5.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-d:
- shard-ptl: NOTRUN -> [SKIP][81] ([Intel XE#6886]) +4 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-d.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][82] ([Intel XE#2938] / [Intel XE#7376] / [Intel XE#7760])
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_dc@dc3co-framedrop-check:
- shard-ptl: NOTRUN -> [SKIP][83] ([Intel XE#8395] / [Intel XE#8396]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_pm_dc@dc3co-framedrop-check.html
* igt@kms_pm_dc@dc3co-framedrop-check@psr2-xrgb8888:
- shard-ptl: NOTRUN -> [SKIP][84] ([Intel XE#8396]) +1 other test skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_pm_dc@dc3co-framedrop-check@psr2-xrgb8888.html
* igt@kms_pm_dc@deep-pkgc:
- shard-lnl: [PASS][85] -> [FAIL][86] ([Intel XE#2029] / [Intel XE#7395])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-4/igt@kms_pm_dc@deep-pkgc.html
* igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
- shard-ptl: NOTRUN -> [SKIP][87] ([Intel XE#7304]) +2 other tests skip
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1:
- shard-ptl: NOTRUN -> [SKIP][88] ([Intel XE#5858]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1.html
* igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1:
- shard-ptl: NOTRUN -> [SKIP][89] ([Intel XE#5858] / [Intel XE#7304]) +3 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#1489]) +3 other tests skip
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-3/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@fbc-psr2-sprite-blt:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-5/igt@kms_psr@fbc-psr2-sprite-blt.html
* igt@kms_psr@fbc-psr2-sprite-blt@edp-1:
- shard-ptl: NOTRUN -> [SKIP][92] ([Intel XE#1406] / [Intel XE#5835]) +3 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_psr@fbc-psr2-sprite-blt@edp-1.html
* igt@kms_psr@pr-dpms:
- shard-ptl: NOTRUN -> [SKIP][93] ([Intel XE#1406])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_psr@pr-dpms.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-ptl: NOTRUN -> [SKIP][94] ([Intel XE#5821])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-ptl: NOTRUN -> [SKIP][95] ([Intel XE#5813])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_setmode@basic:
- shard-bmg: [PASS][96] -> [FAIL][97] ([Intel XE#8618])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-6/igt@kms_setmode@basic.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-7/igt@kms_setmode@basic.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#1435] / [Intel XE#8695])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@kms_setmode@invalid-clone-exclusive-crtc.html
- shard-ptl: NOTRUN -> [SKIP][99] ([Intel XE#5910])
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_vrr@cmrr-video-mode:
- shard-ptl: [PASS][100] -> [FAIL][101] ([Intel XE#9547]) +1 other test fail
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-2/igt@kms_vrr@cmrr-video-mode.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@kms_vrr@cmrr-video-mode.html
* igt@kms_vrr@flip-dpms@pipe-a-edp-1:
- shard-ptl: [PASS][102] -> [FAIL][103] ([Intel XE#4227] / [Intel XE#7397]) +1 other test fail
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-4/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@kms_vrr@flip-dpms@pipe-a-edp-1.html
* igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all:
- shard-bmg: NOTRUN -> [ABORT][104] ([Intel XE#8868])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-9/igt@sriov_basic@pf-unbind-with-vfs-enabled-numvfs-all.html
* igt@xe_configfs@survivability-mode:
- shard-ptl: NOTRUN -> [SKIP][105] ([Intel XE#8428])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@xe_configfs@survivability-mode.html
* igt@xe_create@multigpu-create-massive-size:
- shard-ptl: NOTRUN -> [SKIP][106] ([Intel XE#5878])
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_evict@evict-mixed-many-threads-small:
- shard-bmg: [PASS][107] -> [INCOMPLETE][108] ([Intel XE#6321] / [Intel XE#8355])
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-10/igt@xe_evict@evict-mixed-many-threads-small.html
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html
* igt@xe_evict@evict-mixed-threads-large-multi-vm:
- shard-ptl: NOTRUN -> [SKIP][109] ([Intel XE#5764]) +4 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@xe_evict@evict-mixed-threads-large-multi-vm.html
* igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen:
- shard-lnl: NOTRUN -> [SKIP][110] ([Intel XE#6540] / [Intel XE#688])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-1/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-reopen.html
* igt@xe_exec_balancer@no-exec-virtual-rebind:
- shard-lnl: NOTRUN -> [SKIP][111] ([Intel XE#7482]) +3 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-3/igt@xe_exec_balancer@no-exec-virtual-rebind.html
* igt@xe_exec_balancer@once-parallel-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][112] ([Intel XE#7482]) +6 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@xe_exec_balancer@once-parallel-userptr-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind:
- shard-bmg: NOTRUN -> [SKIP][113] ([Intel XE#2322] / [Intel XE#7372]) +3 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-10/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate:
- shard-lnl: NOTRUN -> [SKIP][114] ([Intel XE#1392])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@xe_exec_basic@multigpu-no-exec-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
- shard-ptl: NOTRUN -> [SKIP][115] ([Intel XE#5575] / [Intel XE#7484]) +3 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html
* igt@xe_exec_fault_mode@many-execqueues-multi-queue-invalid-fault:
- shard-bmg: NOTRUN -> [SKIP][116] ([Intel XE#8374]) +2 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@xe_exec_fault_mode@many-execqueues-multi-queue-invalid-fault.html
* igt@xe_exec_fault_mode@many-multi-queue-rebind-imm:
- shard-lnl: NOTRUN -> [SKIP][117] ([Intel XE#8374]) +1 other test skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@xe_exec_fault_mode@many-multi-queue-rebind-imm.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race:
- shard-ptl: NOTRUN -> [SKIP][118] ([Intel XE#8374]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html
* igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr:
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#9003])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-3/igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr.html
- shard-ptl: NOTRUN -> [SKIP][120] ([Intel XE#9003])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-3/igt@xe_exec_mix_modes@exec-multi-queue-spinner-interrupted-lr.html
* igt@xe_exec_multi_queue@few-execs-preempt-mode-priority:
- shard-ptl: NOTRUN -> [SKIP][121] ([Intel XE#8364]) +11 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@xe_exec_multi_queue@few-execs-preempt-mode-priority.html
* igt@xe_exec_multi_queue@many-execs-preempt-mode-dyn-priority:
- shard-bmg: NOTRUN -> [SKIP][122] ([Intel XE#8364]) +7 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-2/igt@xe_exec_multi_queue@many-execs-preempt-mode-dyn-priority.html
* igt@xe_exec_multi_queue@one-queue-preempt-mode-priority-smem:
- shard-lnl: NOTRUN -> [SKIP][123] ([Intel XE#8364]) +3 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-1/igt@xe_exec_multi_queue@one-queue-preempt-mode-priority-smem.html
* igt@xe_exec_reset@cm-multi-queue-close-fd:
- shard-ptl: NOTRUN -> [SKIP][124] ([Intel XE#8369])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@xe_exec_reset@cm-multi-queue-close-fd.html
* igt@xe_exec_reset@multi-queue-cat-error-on-secondary:
- shard-lnl: NOTRUN -> [SKIP][125] ([Intel XE#8369])
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@xe_exec_reset@multi-queue-cat-error-on-secondary.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-single-vma:
- shard-ptl: NOTRUN -> [SKIP][126] ([Intel XE#6196])
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-comp-single-vma.html
* igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][127] ([Intel XE#8378]) +4 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@xe_exec_threads@threads-multi-queue-cm-fd-userptr-invalidate.html
* igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind:
- shard-lnl: NOTRUN -> [SKIP][128] ([Intel XE#8378])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@xe_exec_threads@threads-multi-queue-cm-shared-vm-rebind.html
* igt@xe_exec_threads@threads-multi-queue-hang-basic:
- shard-ptl: NOTRUN -> [SKIP][129] ([Intel XE#8378]) +4 other tests skip
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-1/igt@xe_exec_threads@threads-multi-queue-hang-basic.html
* igt@xe_mmap@pci-membarrier:
- shard-ptl: NOTRUN -> [SKIP][130] ([Intel XE#5100] / [Intel XE#7408])
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@xe_mmap@pci-membarrier.html
* igt@xe_multigpu_svm@mgpu-concurrent-access-basic:
- shard-lnl: NOTRUN -> [SKIP][131] ([Intel XE#6964])
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-2/igt@xe_multigpu_svm@mgpu-concurrent-access-basic.html
* igt@xe_multigpu_svm@mgpu-latency-copy-prefetch:
- shard-ptl: NOTRUN -> [SKIP][132] ([Intel XE#6964])
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@xe_multigpu_svm@mgpu-latency-copy-prefetch.html
* igt@xe_pat@l2-flush-opt-svm-pat-restrict:
- shard-ptl: NOTRUN -> [SKIP][133] ([Intel XE#7590])
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@xe_pat@l2-flush-opt-svm-pat-restrict.html
* igt@xe_pat@pat-sw-hw-compare:
- shard-ptl: NOTRUN -> [FAIL][134] ([Intel XE#7695]) +1 other test fail
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-5/igt@xe_pat@pat-sw-hw-compare.html
- shard-bmg: NOTRUN -> [FAIL][135] ([Intel XE#7695])
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-9/igt@xe_pat@pat-sw-hw-compare.html
* igt@xe_pm@s2idle-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][136] ([Intel XE#2284] / [Intel XE#7370])
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-5/igt@xe_pm@s2idle-d3cold-basic-exec.html
- shard-ptl: NOTRUN -> [SKIP][137] ([Intel XE#5741])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@xe_pm@s2idle-d3cold-basic-exec.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-ptl: [PASS][138] -> [ABORT][139] ([Intel XE#9362])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-4/igt@xe_pm@s4-vm-bind-prefetch.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@xe_pm@s4-vm-bind-prefetch.html
* igt@xe_pm@s4-vm-bind-userptr:
- shard-lnl: [PASS][140] -> [ABORT][141] ([Intel XE#9362])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-8/igt@xe_pm@s4-vm-bind-userptr.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-4/igt@xe_pm@s4-vm-bind-userptr.html
* igt@xe_pm_residency@gt-c6-freeze@gt0:
- shard-bmg: [PASS][142] -> [FAIL][143] ([Intel XE#9254]) +1 other test fail
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-10/igt@xe_pm_residency@gt-c6-freeze@gt0.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@xe_pm_residency@gt-c6-freeze@gt0.html
* igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
- shard-bmg: NOTRUN -> [SKIP][144] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-5/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html
* igt@xe_query@multigpu-query-hwconfig:
- shard-bmg: NOTRUN -> [SKIP][145] ([Intel XE#944]) +1 other test skip
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-8/igt@xe_query@multigpu-query-hwconfig.html
* igt@xe_query@multigpu-query-invalid-query:
- shard-ptl: NOTRUN -> [SKIP][146] ([Intel XE#6019]) +2 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-4/igt@xe_query@multigpu-query-invalid-query.html
* igt@xe_survivability@i2c-functionality:
- shard-lnl: NOTRUN -> [SKIP][147] ([Intel XE#8415])
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-4/igt@xe_survivability@i2c-functionality.html
* igt@xe_vm@overcommit-fault-vram-lr:
- shard-ptl: NOTRUN -> [SKIP][148] ([Intel XE#9597])
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-7/igt@xe_vm@overcommit-fault-vram-lr.html
#### Possible fixes ####
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-bmg: [FAIL][149] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2:
- shard-bmg: [FAIL][151] ([Intel XE#6078]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-dp-2.html
* igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-edp-1:
- shard-ptl: [FAIL][153] ([Intel XE#9673]) -> [PASS][154] +1 other test pass
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-3/igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-edp-1.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-6/igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-edp-1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-lnl: [FAIL][155] ([Intel XE#301]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [FAIL][157] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][158] +1 other test pass
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_hdmi_audio_bw@audio-bw-hblank80:
- shard-bmg: [FAIL][159] ([Intel XE#9313]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-10/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-3/igt@kms_hdmi_audio_bw@audio-bw-hblank80.html
* igt@kms_hdmi_inject@inject-audio:
- shard-ptl: [SKIP][161] ([Intel XE#7308]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-4/igt@kms_hdmi_inject@inject-audio.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-2/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_pm_dc@dc5-dpms-suspend-resume:
- shard-lnl: [FAIL][163] ([Intel XE#8399]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-8/igt@kms_pm_dc@dc5-dpms-suspend-resume.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-3/igt@kms_pm_dc@dc5-dpms-suspend-resume.html
* igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
- shard-lnl: [FAIL][165] ([Intel XE#9096]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-6/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-bmg: [ABORT][167] ([Intel XE#6652] / [Intel XE#9470]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-2/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-8/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
* igt@xe_pm@s4-multiple-execs:
- shard-ptl: [ABORT][169] ([Intel XE#9362]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-ptl-3/igt@xe_pm@s4-multiple-execs.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-ptl-8/igt@xe_pm@s4-multiple-execs.html
* igt@xe_pm@s4-vm-bind-prefetch:
- shard-lnl: [ABORT][171] ([Intel XE#9362]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-2/igt@xe_pm@s4-vm-bind-prefetch.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-6/igt@xe_pm@s4-vm-bind-prefetch.html
#### Warnings ####
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][173] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][174] ([Intel XE#1729] / [Intel XE#7424])
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][175] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][176] ([Intel XE#2426] / [Intel XE#5848])
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@sriov_basic@pf-unbind-with-vf-probed:
- shard-bmg: [ABORT][177] ([Intel XE#8868]) -> [ABORT][178] ([Intel XE#8868] / [Intel XE#9463])
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-bmg-5/igt@sriov_basic@pf-unbind-with-vf-probed.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-bmg-4/igt@sriov_basic@pf-unbind-with-vf-probed.html
* igt@xe_pm@s4-basic:
- shard-lnl: [DMESG-WARN][179] ([Intel XE#7727]) -> [ABORT][180] ([Intel XE#9362])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a/shard-lnl-5/igt@xe_pm@s4-basic.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/shard-lnl-4/igt@xe_pm@s4-basic.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
[Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2372
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
[Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
[Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
[Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
[Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
[Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
[Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
[Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
[Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
[Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
[Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
[Intel XE#5832]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5832
[Intel XE#5835]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5835
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
[Intel XE#5858]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5858
[Intel XE#5878]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5878
[Intel XE#5879]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5879
[Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
[Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
[Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
[Intel XE#5946]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5946
[Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
[Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
[Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
[Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
[Intel XE#7308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7308
[Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
[Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
[Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
[Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
[Intel XE#7359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7359
[Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
[Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
[Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
[Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
[Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
[Intel XE#7408]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7408
[Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
[Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
[Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
[Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
[Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
[Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
[Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
[Intel XE#7727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7727
[Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
[Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
[Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
[Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
[Intel XE#8348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8348
[Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
[Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
[Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
[Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
[Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
[Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
[Intel XE#8395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8395
[Intel XE#8396]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8396
[Intel XE#8399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8399
[Intel XE#8415]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8415
[Intel XE#8428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8428
[Intel XE#8618]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8618
[Intel XE#8695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8695
[Intel XE#8868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8868
[Intel XE#9003]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9003
[Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
[Intel XE#9254]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9254
[Intel XE#9312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9312
[Intel XE#9313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9313
[Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
[Intel XE#9470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9470
[Intel XE#9533]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9533
[Intel XE#9547]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9547
[Intel XE#9597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9597
[Intel XE#9673]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9673
Build changes
-------------
* IGT: IGT_9163 -> IGT_9164
* Linux: xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a -> xe-pw-173001v2
IGT_9163: 9163
IGT_9164: 9164
xe-6010-d56ff005f0d16ec136ee31fe3238eb447fefdc1a: d56ff005f0d16ec136ee31fe3238eb447fefdc1a
xe-pw-173001v2: 173001v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-173001v2/index.html
[-- Attachment #2: Type: text/html, Size: 64974 bytes --]
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile
2026-10-26 6:05 ` [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
@ 2026-10-26 9:37 ` sashiko-bot
2026-10-27 14:51 ` Mallesh, Koujalagi
2026-10-28 16:07 ` Andi Shyti
2 siblings, 0 replies; 42+ messages in thread
From: sashiko-bot @ 2026-10-26 9:37 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] drm/xe/hw_error: devres teardown race in xe_hw_error_work_disable()
- [Medium] drm/xe/hw_error: unchecked devm_add_action_or_reset() in xe_hw_error_init()
- [Medium] drm/xe/hw_error: uninitialized delayed_work in xe_hw_error_work_disable()
--
commit eb5d3c525869285977a7b6ae0cced93702f4f61e
Author: Raag Jadav <raag.jadav@intel.com>
drm/xe/hw_error: Initialize hw_error_work per tile
This commit initializes tile->hw_error_work across all tiles in
xe_hw_error_init() rather than only on the root tile, and registers a
xe_hw_error_work_disable() callback with devm_add_action_or_reset() to
disable the delayed work on teardown.
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 41ddd997478b8..f7799c3c08aac 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -537,6 +537,23 @@ static void process_hw_errors(struct xe_device *xe)
> }
> }
>
> +/**
> + * xe_hw_error_work_disable - Disable hw error work
> + * @arg: xe device instance
> + *
> + * This function disables the delayed work for hardware error handling
> + * for all tiles.
> + */
> +void xe_hw_error_work_disable(void *arg)
> +{
> + struct xe_device *xe = arg;
> + struct xe_tile *tile;
> + u8 id;
> +
> + for_each_tile(tile, xe, id)
> + disable_delayed_work_sync(&tile->hw_error_work);
> +}
[Severity: Medium]
Should xe_hw_error_work_disable() also check !IS_DGFX(xe) || IS_SRIOV_VF(xe)
before calling disable_delayed_work_sync()?
In xe_hw_error_init(), tile->hw_error_work is only initialized via
INIT_DELAYED_WORK() when IS_DGFX(xe) && !IS_SRIOV_VF(xe):
drivers/gpu/drm/xe/xe_hw_error.c:xe_hw_error_init()
if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
return;
for_each_tile(tile, xe, id)
INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
However, xe_hw_error_work_disable() is exported in drivers/gpu/drm/xe/xe_hw_error.h
without that guard. In the commit "drm/xe/xe_ras: Disable hw error worker when
AER handling is in progress", xe_pci_error_detected() in
drivers/gpu/drm/xe/xe_pci_error.c calls xe_hw_error_work_disable(xe) whenever
XE_DEVICE_WA(xe, 14028434957) && is_aer_internal_error(pdev) is true.
Because Crescent Island (cri_desc) sets .has_sriov = true and enables
workaround 14028434957 at the platform level in xe_device_probe_early() before
xe_sriov_probe_early(), an SR-IOV VF on Crescent Island has
XE_DEVICE_WA(xe, 14028434957) set while tile->hw_error_work remains
uninitialized.
If pcie_do_recovery() invokes xe_pci_error_detected() on the VF, won't
xe_hw_error_work_disable() pass an uninitialized tile->hw_error_work (with
work->func == NULL) to disable_delayed_work_sync() -> __cancel_work_sync() ->
__flush_work(), triggering WARN_ON(!work->func) in kernel/workqueue.c?
> +
> /**
> * xe_hw_error_init - Initialize hw errors
> * @xe: xe device instance
> @@ -546,12 +563,15 @@ static void process_hw_errors(struct xe_device *xe)
> */
> void xe_hw_error_init(struct xe_device *xe)
> {
> - struct xe_tile *tile = xe_device_get_root_tile(xe);
> + struct xe_tile *tile;
> + u8 id;
>
> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
> return;
>
> - INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
> + for_each_tile(tile, xe, id)
> + INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>
> process_hw_errors(xe);
> + devm_add_action_or_reset(xe->drm.dev, xe_hw_error_work_disable, xe);
> }
[Severity: High]
Can registering xe_hw_error_work_disable() via devm_add_action_or_reset() race
with an in-flight hw_error_work() callback during devres teardown and leave
behind dangling devres nodes and sysfs attributes after struct xe_device is
freed?
When devres teardown runs during probe failure unwind, driver unbind
(__device_release_driver() -> xe_pci_remove() -> device_unbind_cleanup() ->
devres_release_all()), or PCI slot reset (xe_pci_error_slot_reset() ->
devres_release_group()), drivers/base/devres.c moves all queued nodes from
dev->devres_head onto a local todo list before running any release callbacks:
drivers/base/devres.c:devres_release_all()
spin_lock_irqsave(&dev->devres_lock, flags);
cnt = remove_nodes(dev, dev->devres_head.next, &dev->devres_head, &todo);
spin_unlock_irqrestore(&dev->devres_lock, flags);
release_nodes(dev, &todo);
If tile->hw_error_work was scheduled by process_hw_errors() or an interrupt and
begins executing before release_nodes() invokes xe_hw_error_work_disable()
(including while xe_hw_error_work_disable() is waiting inside
disable_delayed_work_sync(&tile->hw_error_work) for the running worker to
finish), the worker executes:
drivers/gpu/drm/xe/xe_hw_error.c:hw_error_work()
-> xe_survivability_mode_runtime_enable(xe)
-> create_survivability_sysfs(pdev)
Inside drivers/gpu/drm/xe/xe_survivability_mode.c:create_survivability_sysfs(),
the worker creates sysfs files and registers new devres actions on
xe->drm.dev:
ret = device_create_file(dev, &dev_attr_survivability_mode);
if (ret)
goto failed;
ret = devm_add_action_or_reset(xe->drm.dev,
xe_survivability_mode_fini, xe);
if (ret)
goto failed;
if (needs_info) {
ret = devm_device_add_group(dev, &survivability_info_group);
if (ret)
goto failed;
}
Because remove_nodes() already drained dev->devres_head into todo before
release_nodes() started, those newly registered devres actions are appended to
dev->devres_head and are not run by the active release_nodes(dev, &todo) pass,
while devm_drm_dev_init_release on todo frees struct xe_device *xe.
Wouldn't this leave the survivability_mode and survivability_info sysfs files
exposed on pdev->dev after xe is freed and drvdata is cleared (leading to a
NULL pointer dereference or use-after-free in survivability_mode_show() and
survivability_info_show()), leave xe_survivability_mode_fini(xe) queued on
dev->devres_head with a dangling xe pointer, and cause subsequent driver
re-probing in really_probe() to fail with -EBUSY because dev->devres_head is
non-empty?
Additionally, what happens in xe_hw_error_init() if devm_add_action_or_reset()
fails with -ENOMEM?
include/linux/device/devres.h:__devm_add_action_or_reset()
ret = __devm_add_action(dev, action, data, name);
if (ret)
action(data);
return ret;
On allocation failure, __devm_add_action_or_reset() immediately runs
xe_hw_error_work_disable(xe), which cancels any delayed work just scheduled by
process_hw_errors(xe) (after the hardware error registers and GFX_MSTR_IRQ
have already been cleared) and permanently disables tile->hw_error_work across
all tiles via WORK_CANCEL_DISABLE. Because xe_hw_error_init() returns void and
ignores the return value, xe_irq_install() and xe_device_probe() continue probing
with tile->hw_error_work permanently disabled for the lifetime of the device.
Should xe_hw_error_init() propagate the error to xe_irq_install()?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261026060459.771448-11-riana.tauro@intel.com?part=2
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
@ 2026-10-26 10:09 ` sashiko-bot
2026-10-26 10:49 ` Upadhyay, Tejas
` (2 subsequent siblings)
3 siblings, 0 replies; 42+ messages in thread
From: sashiko-bot @ 2026-10-26 10:09 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/xe: ignored recovery action in hw_error_work() and premature DB_ECC wedge
- [High] drm/xe: race between hw_error_work() and PCIe AER reset and removal paths
--
commit 599d1ef3076a9398588bb132729ba7fcc7f8f463
Author: Riana Tauro <riana.tauro@intel.com>
drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
This patch schedules hw_error_work() when non-fatal hardware errors are
routed via direct IRQ on platforms with a system controller, invokes
xe_ras_process_errors() from the worker, and declares the device wedged
with a bus reset if double-bit ECC page offlining fails.
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index f7799c3c08aac..269ce6a19a80b 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
[ ... ]
> @@ -166,12 +170,36 @@ static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) == XE_RAS_REG_SIZE);
[ ... ]
> static void hw_error_work(struct work_struct *work)
> {
> struct xe_tile *tile = container_of(work, typeof(*tile), hw_error_work.work);
> struct xe_device *xe = tile_to_xe(tile);
>
> guard(xe_pm_runtime)(xe);
> +
> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
> + /* If the device is in reset in AER path, skip processing hardware errors */
> + if (xe_device_is_in_reset(xe))
> + return;
[Severity: High]
Can hw_error_work() race with the PCIe AER reset and removal paths here?
In hw_error_source_handler(), a non-fatal hardware error IRQ schedules
tile->hw_error_work with a 1-second delay, and hw_error_work() checks
xe_device_is_in_reset(xe) without synchronization before calling
xe_ras_process_errors(xe).
Although the later commit "drm/xe/xe_ras: Disable hw error worker when AER
handling is in progress" calls xe_hw_error_work_disable(xe) in
xe_pci_error_detected(), that call is gated on:
if (XE_DEVICE_WA(xe, 14028434957) && is_aer_internal_error(pdev))
which only checks PCI_ERR_UNC_INTN on the upstream switch port, and is
also skipped if xe_wedged(xe) is already true.
When an AER event occurs without PCI_ERR_UNC_INTN set on the upstream
switch port (such as a fatal link or protocol error with
state == pci_channel_io_frozen, or a non-fatal error where
xe_pci_error_mmio_enabled() runs xe_ras_process_errors(xe) and triggers
XE_RAS_RECOVERY_ACTION_RESET), xe_hw_error_work_disable(xe) is not called:
1. In drivers/gpu/drm/xe/xe_pci_error.c:prepare_device_for_reset():
xe_device_set_in_reset(xe);
for_each_gt(gt, xe, id) {
xe_gt_wedge_declare(gt);
flush_work(>->wedge.worker);
}
pci_disable_device(pdev);
If hw_error_work() passes the xe_device_is_in_reset(xe) check just before
xe_device_set_in_reset(xe) is called, xe_ras_process_errors(xe) can run
system controller MMIO mailbox transactions and TTM VRAM page offlining
concurrently with pci_disable_device(pdev) and secondary bus reset.
2. In drivers/gpu/drm/xe/xe_pci_error.c:xe_pci_error_slot_reset():
xe_device_clear_in_reset(xe);
pdev->driver->remove(pdev);
devres_release_group(&pdev->dev, xe->devres_group);
Because xe_device_clear_in_reset(xe) clears xe->in_reset before
pdev->driver->remove(pdev) and devres_release_group() run, if the delayed
tile->hw_error_work fires in this window, xe_device_is_in_reset(xe) will
return false and xe_ras_process_errors(xe) will execute concurrently with
driver teardown.
Should prepare_device_for_reset() also cancel or flush tile->hw_error_work,
and should in_reset remain set across removal in xe_pci_error_slot_reset()?
> +
> + xe_ras_process_errors(xe);
> + return;
> + }
> +
> xe_survivability_mode_runtime_enable(xe);
> }
[ ... ]
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index db3cbc186a514..e6a0ee468b17b 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -628,8 +628,15 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
> break;
> case XE_RAS_MEMORY_DB_ECC:
> ret = handle_page_offline(xe, info->sw_address, true);
> - if (ret)
> + /*
> + * Double-bit ECC errors are non-fatal errors and are reported via IRQ.
> + * Wedge the device with a bus reset for errors that require SBR to recover.
> + * TODO: Trigger SBR using pci_reset_bus
> + */
> + if (ret) {
> + xe_wedge_declare(xe, DRM_WEDGE_RECOVERY_BUS_RESET);
> return XE_RAS_RECOVERY_ACTION_RESET;
> + }
[Severity: High]
Should theDRM_WEDGE_RECOVERY_BUS_RESET wedging be performed by the caller
based on the enum xe_ras_recovery_action return value of
xe_ras_process_errors(xe) in hw_error_work(), rather than directly inside
handle_device_memory_errors()?
Right now, hw_error_work() in drivers/gpu/drm/xe/xe_hw_error.c calls
xe_ras_process_errors(xe) and ignores its return value. Any error processed
on the direct IRQ path that returns XE_RAS_RECOVERY_ACTION_RESET outside of
XE_RAS_MEMORY_DB_ECC (such as GLOBAL_UNCORR_ERROR in
handle_core_compute_errors(), non-CSC/non-Punit errors in
handle_soc_internal_errors(), other device memory error categories, unknown
RAS components, or a sysctrl mailbox failure/flood jumping to err:) will
not trigger any reset or wedge recovery action.
Conversely, calling xe_wedge_declare(xe, DRM_WEDGE_RECOVERY_BUS_RESET)
directly inside handle_device_memory_errors() affects all callers of
xe_ras_process_errors(xe):
1. Multi-error severity aggregation in xe_ras_process_errors():
/* Process and log all errors and then trigger highest recovery action */
if (action > final_action)
final_action = action;
Because xe_wedge_declare() is one-shot via atomic_xchg(&xe->wedged.flag, 1),
if a XE_RAS_MEMORY_DB_ECC entry with a failing handle_page_offline() is
processed before a higher-severity XE_RAS_RECOVERY_ACTION_DISCONNECT entry
in the batch (such as a Punit error requiring DRM_WEDGE_RECOVERY_COLD_RESET
in punit_error_handler() or a CSC firmware error requiring
DRM_WEDGE_RECOVERY_VENDOR in xe_survivability_mode_runtime_enable()),
xe->wedged.method is latched to DRM_WEDGE_RECOVERY_BUS_RESET and the
higher-severity recovery method is masked.
2. Driver probe path via xe_device_probe() -> xe_ras_init() ->
xe_ras_process_errors(xe):
This runs before xe_gt_init() and drm_dev_register() to log boot-time
errors. If a boot-time XE_RAS_MEMORY_DB_ECC error fails
handle_page_offline() (for example with -EIO on a critical BO/stolen page,
-ENOMEM, or -ENOSPC), handle_device_memory_errors() calls
xe_wedge_declare(), scheduling drm_dev_wedged_event() before
drm_dev_register() and setting xe->wedged.flag, which causes
__guc_ct_send_locked() in xe_gt_init() to fail with -ENOTRECOVERABLE and
aborts probe.
3. PCIe AER path in xe_pci_error_mmio_enabled():
In the AER path, XE_RAS_RECOVERY_ACTION_RESET is handled by
ras_action_to_pci_result() -> prepare_device_for_reset(), which sets
wedged.flag without sending a wedged uevent or setting needs_flr_on_fini
because AER performs an automatic slot reset. Although the later commit
"drm/xe/ras: Skip double-bit ECC page offlining on AER path" skips DB_ECC
when ras->aer_path is set for WA 14028434957 internal errors, ras->aer_path
remains false on non-internal AER errors and on platforms without
WA 14028434957, where calling xe_wedge_declare() emits an unintended
WEDGED=bus-reset uevent and sets xe->needs_flr_on_fini = true.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261026060459.771448-11-riana.tauro@intel.com?part=4
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 7/9] drm/xe/xe_ras: Disable hw error worker when AER handling is in progress
2026-10-26 6:05 ` [PATCH v2 7/9] drm/xe/xe_ras: Disable hw error worker when AER handling is in progress Riana Tauro
@ 2026-10-26 10:32 ` sashiko-bot
0 siblings, 0 replies; 42+ messages in thread
From: sashiko-bot @ 2026-10-26 10:32 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/xe: uninitialized hw_error_work disabled on VF in xe_pci_error_detected()
--
commit b14238c72b86ed2185123242102a8af0419bfeb1
Author: Riana Tauro <riana.tauro@intel.com>
drm/xe/xe_ras: Disable hw error worker when AER handling is in progress
When an uncorrectable internal AER error occurs on a device with workaround
14028434957, this commit marks the RAS state as using the AER path and
flushes and disables the hardware error worker in xe_pci_error_detected().
> diff --git a/drivers/gpu/drm/xe/xe_pci_error.c b/drivers/gpu/drm/xe/xe_pci_error.c
> index 9bf0da3a3d152..b27f8a0f1b170 100644
> --- a/drivers/gpu/drm/xe/xe_pci_error.c
> +++ b/drivers/gpu/drm/xe/xe_pci_error.c
[ ... ]
> @@ -67,6 +91,15 @@ static pci_ers_result_t xe_pci_error_detected(struct pci_dev *pdev, pci_channel_
> if (xe_survivability_mode_is_boot_enabled(xe) || xe_wedged(xe))
> return PCI_ERS_RESULT_DISCONNECT;
>
> + /*
> + * If non-fatal error processing is in progress when uncorrectable internal error occurs,
> + * flush and disable the worker to prevent further processing, as a reset is imminent.
> + */
> + if (XE_DEVICE_WA(xe, 14028434957) && is_aer_internal_error(pdev)) {
> + xe_ras_set_aer_path(xe, true);
> + xe_hw_error_work_disable(xe);
> + }
[Severity: High]
Can this call xe_hw_error_work_disable() on an uninitialized tile->hw_error_work
when xe_pci_error_detected() runs on an SR-IOV VF?
On Crescent Island, SR-IOV is supported and workaround 14028434957 is
populated via xe_wa_process_device_oob() in xe_device_probe_early(), so
XE_DEVICE_WA(xe, 14028434957) evaluates to true on both PF and VF instances.
However, xe_hw_error_init() skips initializing tile->hw_error_work on VFs:
drivers/gpu/drm/xe/xe_hw_error.c:xe_hw_error_init()
if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
return;
for_each_tile(tile, xe, id)
INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
When an uncorrectable internal error occurs on the upstream switch port,
pcie_do_recovery() walks subordinate devices under the bridge and invokes
xe_pci_error_detected() for bound VFs as well as the PF. Because
pci_upstream_bridge() resolves pci_physfn(dev) for VFs,
is_aer_internal_error() returns true on the VF too, and
xe_hw_error_work_disable() then calls disable_delayed_work_sync() on
uninitialized delayed_work structs:
drivers/gpu/drm/xe/xe_hw_error.c:xe_hw_error_work_disable()
for_each_tile(tile, xe, id)
disable_delayed_work_sync(&tile->hw_error_work);
Should this path check !IS_SRIOV_VF(xe) (or xe->info.has_sysctrl) before
disabling the worker?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261026060459.771448-11-riana.tauro@intel.com?part=7
^ permalink raw reply [flat|nested] 42+ messages in thread
* RE: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
2026-10-26 10:09 ` sashiko-bot
@ 2026-10-26 10:49 ` Upadhyay, Tejas
2026-10-26 14:08 ` Tauro, Riana
2026-10-28 16:15 ` Andi Shyti
2026-10-28 16:17 ` Andi Shyti
3 siblings, 1 reply; 42+ messages in thread
From: Upadhyay, Tejas @ 2026-10-26 10:49 UTC (permalink / raw)
To: Tauro, Riana, intel-xe@lists.freedesktop.org
Cc: Gupta, Anshuman, Vivi, Rodrigo,
aravind.iddamsetty@linux.intel.com, Nilawar, Badal, Jadav, Raag,
Koppuravuri, Ravi Kishore, Koujalagi, Mallesh
> -----Original Message-----
> From: Tauro, Riana <riana.tauro@intel.com>
> Sent: 26 October 2026 11:35
> To: intel-xe@lists.freedesktop.org
> Cc: Tauro, Riana <riana.tauro@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
> aravind.iddamsetty@linux.intel.com; Nilawar, Badal
> <badal.nilawar@intel.com>; Jadav, Raag <raag.jadav@intel.com>;
> Koppuravuri, Ravi Kishore <ravi.kishore.koppuravuri@intel.com>; Koujalagi,
> Mallesh <mallesh.koujalagi@intel.com>; Upadhyay, Tejas
> <tejas.upadhyay@intel.com>
> Subject: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed
> via direct IRQ
>
> Process, log and recover non-fatal errors routed via direct IRQ.
> Double-bit ecc errors belong to non-fatal error category and are reported via
> irq. For pages that belong to critical BO, wedge the device with bus-reset as
> the recovery action.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_error.c | 37
> ++++++++++++++++++++++++++++----
> drivers/gpu/drm/xe/xe_ras.c | 9 +++++++-
> 2 files changed, 41 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
> b/drivers/gpu/drm/xe/xe_hw_error.c
> index f7799c3c08aa..269ce6a19a80 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -5,6 +5,8 @@
>
> #include <linux/bitmap.h>
>
> +#include <generated/xe_device_wa_oob.h>
> +
> #include "regs/xe_gsc_regs.h"
> #include "regs/xe_hw_error_regs.h"
> #include "regs/xe_irq_regs.h"
> @@ -15,7 +17,9 @@
> #include "xe_hw_error.h"
> #include "xe_mmio.h"
> #include "xe_pm.h"
> +#include "xe_ras.h"
> #include "xe_survivability_mode.h"
> +#include "xe_wa.h"
>
> #define GT_HW_ERROR_MAX_ERR_BITS 16
> #define HEC_UNCORR_FW_ERR_BITS 4
> @@ -166,12 +170,36 @@
> static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) ==
> XE_RAS_REG_SIZE);
>
> pvc_master_local_fatal_err_reg : \
>
> pvc_master_local_nonfatal_err_reg)
>
> +static const char *hw_err_to_str(const enum hardware_error hw_err) {
> + switch (hw_err) {
> + case HARDWARE_ERROR_CORRECTABLE:
> + return "Correctable";
> + case HARDWARE_ERROR_NONFATAL:
> + return "Non-Fatal";
> + case HARDWARE_ERROR_FATAL:
> + return "Fatal";
> + default:
> + return "Unknown";
> + }
> +}
> +
> static void hw_error_work(struct work_struct *work) {
> struct xe_tile *tile = container_of(work, typeof(*tile),
> hw_error_work.work);
> struct xe_device *xe = tile_to_xe(tile);
>
> guard(xe_pm_runtime)(xe);
> +
> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
I think you should have all these in 1 patch for 14028434957
Tejas
> + /* If the device is in reset in AER path, skip processing
> hardware errors */
> + if (xe_device_is_in_reset(xe))
> + return;
> +
> + xe_ras_process_errors(xe);
> + return;
> + }
> +
> xe_survivability_mode_runtime_enable(xe);
> }
>
> @@ -433,12 +461,13 @@ static void hw_error_source_handler(struct xe_tile
> *tile, const enum hardware_er
> return;
>
> /*
> - * Hardware errors are reported through System Controller on the
> platforms that
> - * support it, and never routed as direct IRQ to SGUnit. So we should
> never be
> - * here for those platforms.
> + * Non fatal errors are routed as a direct IRQ on platforms that support
> + * system controller.
> */
> if (xe->info.has_sysctrl) {
> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error
> routing\n");
> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n",
> hw_err_to_str(hw_err),
> + severity_str);
> + schedule_delayed_work(&tile->hw_error_work,
> +msecs_to_jiffies(MSEC_PER_SEC));
> return;
> }
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c index
> db3cbc186a51..e6a0ee468b17 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -628,8 +628,15 @@ static u8 handle_device_memory_errors(struct
> xe_device *xe, struct xe_ras_error_
> break;
> case XE_RAS_MEMORY_DB_ECC:
> ret = handle_page_offline(xe, info->sw_address, true);
> - if (ret)
> + /*
> + * Double-bit ECC errors are non-fatal errors and are reported
> via IRQ.
> + * Wedge the device with a bus reset for errors that require
> SBR to recover.
> + * TODO: Trigger SBR using pci_reset_bus
> + */
> + if (ret) {
> + xe_wedge_declare(xe,
> DRM_WEDGE_RECOVERY_BUS_RESET);
> return XE_RAS_RECOVERY_ACTION_RESET;
> + }
> break;
> default:
> return XE_RAS_RECOVERY_ACTION_RESET;
> --
> 2.47.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 10:49 ` Upadhyay, Tejas
@ 2026-10-26 14:08 ` Tauro, Riana
2026-10-29 6:36 ` Mallesh, Koujalagi
0 siblings, 1 reply; 42+ messages in thread
From: Tauro, Riana @ 2026-10-26 14:08 UTC (permalink / raw)
To: Upadhyay, Tejas, intel-xe@lists.freedesktop.org
Cc: Gupta, Anshuman, Vivi, Rodrigo,
aravind.iddamsetty@linux.intel.com, Nilawar, Badal, Jadav, Raag,
Koppuravuri, Ravi Kishore, Koujalagi, Mallesh
On 26-10-2026 16:19, Upadhyay, Tejas wrote:
>
>> -----Original Message-----
>> From: Tauro, Riana <riana.tauro@intel.com>
>> Sent: 26 October 2026 11:35
>> To: intel-xe@lists.freedesktop.org
>> Cc: Tauro, Riana <riana.tauro@intel.com>; Gupta, Anshuman
>> <anshuman.gupta@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>> aravind.iddamsetty@linux.intel.com; Nilawar, Badal
>> <badal.nilawar@intel.com>; Jadav, Raag <raag.jadav@intel.com>;
>> Koppuravuri, Ravi Kishore <ravi.kishore.koppuravuri@intel.com>; Koujalagi,
>> Mallesh <mallesh.koujalagi@intel.com>; Upadhyay, Tejas
>> <tejas.upadhyay@intel.com>
>> Subject: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed
>> via direct IRQ
>>
>> Process, log and recover non-fatal errors routed via direct IRQ.
>> Double-bit ecc errors belong to non-fatal error category and are reported via
>> irq. For pages that belong to critical BO, wedge the device with bus-reset as
>> the recovery action.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_hw_error.c | 37
>> ++++++++++++++++++++++++++++----
>> drivers/gpu/drm/xe/xe_ras.c | 9 +++++++-
>> 2 files changed, 41 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>> b/drivers/gpu/drm/xe/xe_hw_error.c
>> index f7799c3c08aa..269ce6a19a80 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -5,6 +5,8 @@
>>
>> #include <linux/bitmap.h>
>>
>> +#include <generated/xe_device_wa_oob.h>
>> +
>> #include "regs/xe_gsc_regs.h"
>> #include "regs/xe_hw_error_regs.h"
>> #include "regs/xe_irq_regs.h"
>> @@ -15,7 +17,9 @@
>> #include "xe_hw_error.h"
>> #include "xe_mmio.h"
>> #include "xe_pm.h"
>> +#include "xe_ras.h"
>> #include "xe_survivability_mode.h"
>> +#include "xe_wa.h"
>>
>> #define GT_HW_ERROR_MAX_ERR_BITS 16
>> #define HEC_UNCORR_FW_ERR_BITS 4
>> @@ -166,12 +170,36 @@
>> static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) ==
>> XE_RAS_REG_SIZE);
>>
>> pvc_master_local_fatal_err_reg : \
>>
>> pvc_master_local_nonfatal_err_reg)
>>
>> +static const char *hw_err_to_str(const enum hardware_error hw_err) {
>> + switch (hw_err) {
>> + case HARDWARE_ERROR_CORRECTABLE:
>> + return "Correctable";
>> + case HARDWARE_ERROR_NONFATAL:
>> + return "Non-Fatal";
>> + case HARDWARE_ERROR_FATAL:
>> + return "Fatal";
>> + default:
>> + return "Unknown";
>> + }
>> +}
>> +
>> static void hw_error_work(struct work_struct *work) {
>> struct xe_tile *tile = container_of(work, typeof(*tile),
>> hw_error_work.work);
>> struct xe_device *xe = tile_to_xe(tile);
>>
>> guard(xe_pm_runtime)(xe);
>> +
>> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
> I think you should have all these in 1 patch for 14028434957
I can combine 3 and 4. If i combine all usages, it would be difficult
to review.
Thanks
Riana
>
> Tejas
>> + /* If the device is in reset in AER path, skip processing
>> hardware errors */
>> + if (xe_device_is_in_reset(xe))
>> + return;
>> +
>> + xe_ras_process_errors(xe);
>> + return;
>> + }
>> +
>> xe_survivability_mode_runtime_enable(xe);
>> }
>>
>> @@ -433,12 +461,13 @@ static void hw_error_source_handler(struct xe_tile
>> *tile, const enum hardware_er
>> return;
>>
>> /*
>> - * Hardware errors are reported through System Controller on the
>> platforms that
>> - * support it, and never routed as direct IRQ to SGUnit. So we should
>> never be
>> - * here for those platforms.
>> + * Non fatal errors are routed as a direct IRQ on platforms that support
>> + * system controller.
>> */
>> if (xe->info.has_sysctrl) {
>> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error
>> routing\n");
>> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n",
>> hw_err_to_str(hw_err),
>> + severity_str);
>> + schedule_delayed_work(&tile->hw_error_work,
>> +msecs_to_jiffies(MSEC_PER_SEC));
>> return;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c index
>> db3cbc186a51..e6a0ee468b17 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -628,8 +628,15 @@ static u8 handle_device_memory_errors(struct
>> xe_device *xe, struct xe_ras_error_
>> break;
>> case XE_RAS_MEMORY_DB_ECC:
>> ret = handle_page_offline(xe, info->sw_address, true);
>> - if (ret)
>> + /*
>> + * Double-bit ECC errors are non-fatal errors and are reported
>> via IRQ.
>> + * Wedge the device with a bus reset for errors that require
>> SBR to recover.
>> + * TODO: Trigger SBR using pci_reset_bus
>> + */
>> + if (ret) {
>> + xe_wedge_declare(xe,
>> DRM_WEDGE_RECOVERY_BUS_RESET);
>> return XE_RAS_RECOVERY_ACTION_RESET;
>> + }
>> break;
>> default:
>> return XE_RAS_RECOVERY_ACTION_RESET;
>> --
>> 2.47.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling
2026-10-26 6:05 ` [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling Riana Tauro
@ 2026-10-27 13:01 ` Mallesh, Koujalagi
2026-10-29 8:07 ` Tauro, Riana
0 siblings, 1 reply; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-27 13:01 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 26-10-2026 11:35 am, Riana Tauro wrote:
> Convert the CSC hardware error worker to a delayed work item so it
> can be reused for generic hardware error handling in later patches.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_error.c | 10 +++++-----
> drivers/gpu/drm/xe/xe_tile_types.h | 6 +++---
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index ac720710c8e8..41ddd997478b 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -166,9 +166,9 @@ static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) == XE_RAS_REG_SIZE);
> pvc_master_local_fatal_err_reg : \
> pvc_master_local_nonfatal_err_reg)
>
> -static void csc_hw_error_work(struct work_struct *work)
> +static void hw_error_work(struct work_struct *work)
> {
> - struct xe_tile *tile = container_of(work, typeof(*tile), csc_hw_error_work);
> + struct xe_tile *tile = container_of(work, typeof(*tile), hw_error_work.work);
> struct xe_device *xe = tile_to_xe(tile);
>
> guard(xe_pm_runtime)(xe);
> @@ -204,7 +204,7 @@ static void csc_hw_error_handler(struct xe_tile *tile, const enum hardware_error
> hec_uncorrected_fw_errors[err_bit], severity_str,
> err_bit);
>
> - schedule_work(&tile->csc_hw_error_work);
> + schedule_delayed_work(&tile->hw_error_work, 0);
hmm, what is rational to use delay work? and making CSC work as generic
hardware error handling?
do u see any impact when we trigger fault injection etc.
> }
> }
>
> @@ -513,7 +513,7 @@ void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl)
> enum hardware_error hw_err;
>
> if (xe_fault_csc_hw_error())
> - schedule_work(&tile->csc_hw_error_work);
> + schedule_delayed_work(&tile->hw_error_work, 0);
>
> for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
> if (master_ctl & ERROR_IRQ(hw_err))
> @@ -551,7 +551,7 @@ void xe_hw_error_init(struct xe_device *xe)
> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
> return;
>
> - INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
> + INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>
> process_hw_errors(xe);
> }
> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
> index e1368c04846a..0f41738635c5 100644
> --- a/drivers/gpu/drm/xe/xe_tile_types.h
> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> @@ -7,7 +7,7 @@
> #define _XE_TILE_TYPES_H_
>
> #include <linux/mutex_types.h>
> -#include <linux/workqueue_types.h>
> +#include <linux/workqueue.h>
>
> #include "xe_lmtt_types.h"
> #include "xe_memirq_types.h"
> @@ -118,8 +118,8 @@ struct xe_tile {
> /** @memirq: Memory Based Interrupts. */
> struct xe_memirq memirq;
>
> - /** @csc_hw_error_work: worker to report CSC HW errors */
> - struct work_struct csc_hw_error_work;
> + /** @hw_error_work: delayed work to handle HW errors */
> + struct delayed_work hw_error_work;
>
> /** @pcode: tile's PCODE */
> struct {
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile
2026-10-26 6:05 ` [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
2026-10-26 9:37 ` sashiko-bot
@ 2026-10-27 14:51 ` Mallesh, Koujalagi
2026-10-29 8:11 ` Tauro, Riana
2026-10-28 16:07 ` Andi Shyti
2 siblings, 1 reply; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-27 14:51 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 26-10-2026 11:35 am, Riana Tauro wrote:
> From: Raag Jadav <raag.jadav@intel.com>
>
> Since hw_error_work is now being reused generically, initialize it per tile
> so that we don't hit uninitialized work for non-root tile. While at it,
> disable hw_error_work on fini to prevent UAF during unwind.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_hw_error.c | 24 ++++++++++++++++++++++--
> drivers/gpu/drm/xe/xe_hw_error.h | 1 +
> 2 files changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 41ddd997478b..f7799c3c08aa 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -537,6 +537,23 @@ static void process_hw_errors(struct xe_device *xe)
> }
> }
>
> +/**
> + * xe_hw_error_work_disable - Disable hw error work
> + * @arg: xe device instance
> + *
> + * This function disables the delayed work for hardware error handling
> + * for all tiles.
> + */
> +void xe_hw_error_work_disable(void *arg)
> +{
> + struct xe_device *xe = arg;
> + struct xe_tile *tile;
> + u8 id;
> +
> + for_each_tile(tile, xe, id)
> + disable_delayed_work_sync(&tile->hw_error_work);
> +}
> +
hmm, we are disabling hw_error_work.
IMO, if we see non-fatal error fires on the IRQ path (since it's
asynchronous), since the work is still disabled,
it would not be processed further.
Thanks,
-/Mallesh
> /**
> * xe_hw_error_init - Initialize hw errors
> * @xe: xe device instance
> @@ -546,12 +563,15 @@ static void process_hw_errors(struct xe_device *xe)
> */
> void xe_hw_error_init(struct xe_device *xe)
> {
> - struct xe_tile *tile = xe_device_get_root_tile(xe);
> + struct xe_tile *tile;
> + u8 id;
>
> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
> return;
>
> - INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
> + for_each_tile(tile, xe, id)
> + INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>
> process_hw_errors(xe);
> + devm_add_action_or_reset(xe->drm.dev, xe_hw_error_work_disable, xe);
> }
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
> index 5e3a11424108..c2c0bfa6d9f9 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.h
> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
> @@ -12,4 +12,5 @@ struct xe_device;
>
> void xe_hw_error_irq_handler(struct xe_tile *tile, const u32 master_ctl);
> void xe_hw_error_init(struct xe_device *xe);
> +void xe_hw_error_work_disable(void *arg);
> #endif
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11
2026-10-26 6:05 ` [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11 Riana Tauro
@ 2026-10-28 6:16 ` Mallesh, Koujalagi
2026-10-29 8:12 ` Tauro, Riana
2026-10-28 14:19 ` Gustavo Sousa
1 sibling, 1 reply; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-28 6:16 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay, Varun Gupta
On 26-10-2026 11:35 am, Riana Tauro wrote:
> From: Varun Gupta <varun.gupta@intel.com>
>
> Add wa_14028434957 for Graphics Version 35.11 to the table.
>
> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> index d8dc41851425..36b2567994db 100644
> --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> @@ -7,3 +7,4 @@
> 14026633728 PLATFORM(CRESCENTISLAND)
> 14026746987 PLATFORM(CRESCENTISLAND)
> 14026779378 PLATFORM(CRESCENTISLAND)
> +14028434957 PLATFORM(CRESCENTISLAND)
can you please combine 3 and 4 patches?
Thanks,
-/Mallesh
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered
2026-10-26 6:05 ` [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered Riana Tauro
@ 2026-10-28 9:24 ` Mallesh, Koujalagi
2026-10-29 8:27 ` Tauro, Riana
0 siblings, 1 reply; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-28 9:24 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 26-10-2026 11:35 am, Riana Tauro wrote:
> On systems lacking RAS capability, only PCIe errors are reported, via
> AER, not device errors. Non-fatal PCIe errors reported at the Upstream
> Switch Port (USP) have no impact on link or device state, so treat
> them as recovered without requiring a secondary bus reset (SBR).
>
> Fixes: 25913a062cd4 ("drm/xe/xe_ras: Add support for uncorrectable core-compute errors")
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ras.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index e6a0ee468b17..2b1a7cb01b0d 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -747,7 +747,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
> }
>
> if (!xe->info.has_sysctrl)
> - return XE_RAS_RECOVERY_ACTION_RESET;
Initially we see Non-fatal PCIe errors reporting via USP required SBR,
however what is rationale behind, not required SBR now?
Thanks,
-/Mallesh
> + return XE_RAS_RECOVERY_ACTION_RECOVERED;
>
> BUILD_BUG_ON(BITS_PER_TYPE(sent) < XE_RAS_COMP_MAX);
> /* Default action */
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper
2026-10-26 6:05 ` [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper Riana Tauro
@ 2026-10-28 9:45 ` Mallesh, Koujalagi
2026-10-28 16:19 ` Andi Shyti
1 sibling, 0 replies; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-28 9:45 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 26-10-2026 11:35 am, Riana Tauro wrote:
> Move the USP lookup logic out of RAS code and into the PCI
nit: s/into the PCI layer/into the xe driver's PCI layer
> layer so it can be reused by other callers.
>
> No functional change.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pci.c | 23 +++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_pci.h | 1 +
> drivers/gpu/drm/xe/xe_ras.c | 19 ++-----------------
> 3 files changed, 26 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 0c13eb901aa7..a9b8e65dff07 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -1521,6 +1521,29 @@ struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev)
> return to_xe_device(drm);
> }
>
> +/**
> + * xe_pci_get_usp_dev() - Get the upstream switch port device.
> + * @pdev: pci device of SGunit
> + *
> + * Device Hierarchy:
> + * Upstream Switch Port (USP) --> Virtual Switch Port (VSP) --> SGunit (GPU endpoint)
> + *
> + * The function traverses the PCI device hierarchy to find the upstream switch port
> + * device.
> + *
> + * Return: pointer to USP &pci_dev, NULL otherwise.
> + */
> +struct pci_dev *xe_pci_get_usp_dev(struct pci_dev *pdev)
> +{
> + struct pci_dev *vsp;
> +
> + vsp = pci_upstream_bridge(pdev);
> + if (!vsp)
> + return NULL;
> +
> + return pci_upstream_bridge(vsp);
> +}
> +
> int xe_register_pci_driver(void)
> {
> return pci_register_driver(&xe_pci_driver);
> diff --git a/drivers/gpu/drm/xe/xe_pci.h b/drivers/gpu/drm/xe/xe_pci.h
> index 11bcc5fe2c5b..3dc3539c3970 100644
> --- a/drivers/gpu/drm/xe/xe_pci.h
> +++ b/drivers/gpu/drm/xe/xe_pci.h
> @@ -11,5 +11,6 @@ struct pci_dev;
> int xe_register_pci_driver(void);
> void xe_unregister_pci_driver(void);
> struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev);
> +struct pci_dev *xe_pci_get_usp_dev(struct pci_dev *pdev);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 2b1a7cb01b0d..a91c3d924e8c 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -10,6 +10,7 @@
> #include "xe_device.h"
> #include "xe_drm_ras.h"
> #include "xe_log.h"
> +#include "xe_pci.h"
> #include "xe_pm.h"
> #include "xe_printk.h"
> #include "xe_ras.h"
> @@ -462,22 +463,6 @@ static void get_offline_list(struct xe_device *xe)
> &response, sizeof(response), &response.common, false);
> }
>
> -static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
> -{
> - struct pci_dev *vsp;
> -
> - /*
> - * Device Hierarchy:
> - *
> - * Upstream Switch Port (USP) --> Virtual Switch Port (VSP) --> SGunit (GPU endpoint)
> - */
> - vsp = pci_upstream_bridge(pdev);
> - if (!vsp)
> - return NULL;
> -
> - return pci_upstream_bridge(vsp);
> -}
> -
> static void ras_usp_aer_init(struct xe_device *xe)
> {
> struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> @@ -485,7 +470,7 @@ static void ras_usp_aer_init(struct xe_device *xe)
> u16 aer_cap;
> u32 status;
>
> - usp = find_usp_dev(pdev);
> + usp = xe_pci_get_usp_dev(pdev);
> if (!usp)
> return;
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11
2026-10-26 6:05 ` [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11 Riana Tauro
2026-10-28 6:16 ` Mallesh, Koujalagi
@ 2026-10-28 14:19 ` Gustavo Sousa
2026-10-29 8:32 ` Tauro, Riana
1 sibling, 1 reply; 42+ messages in thread
From: Gustavo Sousa @ 2026-10-28 14:19 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: riana.tauro, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay, Varun Gupta
Riana Tauro <riana.tauro@intel.com> writes:
> From: Varun Gupta <varun.gupta@intel.com>
>
> Add wa_14028434957 for Graphics Version 35.11 to the table.
>
> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> index d8dc41851425..36b2567994db 100644
> --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
> @@ -7,3 +7,4 @@
> 14026633728 PLATFORM(CRESCENTISLAND)
> 14026746987 PLATFORM(CRESCENTISLAND)
> 14026779378 PLATFORM(CRESCENTISLAND)
> +14028434957 PLATFORM(CRESCENTISLAND)
This conflicts with the patch description. If the workaround applies to
graphics version 35.11, then the rule here should use GRAPHICS_VERSION()
instead of PLATFORM(). Now, if this is a platform-specific workaround,
then the commit message should be rewritten to reflect that.
--
Gustavo Sousa
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile
2026-10-26 6:05 ` [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
2026-10-26 9:37 ` sashiko-bot
2026-10-27 14:51 ` Mallesh, Koujalagi
@ 2026-10-28 16:07 ` Andi Shyti
2 siblings, 0 replies; 42+ messages in thread
From: Andi Shyti @ 2026-10-28 16:07 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Hi Riana,
...
> void xe_hw_error_init(struct xe_device *xe)
> {
> - struct xe_tile *tile = xe_device_get_root_tile(xe);
> + struct xe_tile *tile;
> + u8 id;
>
> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
> return;
>
> - INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
> + for_each_tile(tile, xe, id)
> + INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>
> process_hw_errors(xe);
> + devm_add_action_or_reset(xe->drm.dev, xe_hw_error_work_disable, xe);
we are ignoring the return value of devm_add_action_or_reset().
Perhaps we can make xe_hw_error_init() an int function.
Andi
> }
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
2026-10-26 10:09 ` sashiko-bot
2026-10-26 10:49 ` Upadhyay, Tejas
@ 2026-10-28 16:15 ` Andi Shyti
2026-10-29 8:23 ` Tauro, Riana
2026-10-28 16:17 ` Andi Shyti
3 siblings, 1 reply; 42+ messages in thread
From: Andi Shyti @ 2026-10-28 16:15 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Hi Riana,
...
> static void hw_error_work(struct work_struct *work)
> {
> struct xe_tile *tile = container_of(work, typeof(*tile), hw_error_work.work);
> struct xe_device *xe = tile_to_xe(tile);
>
> guard(xe_pm_runtime)(xe);
> +
> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
> + /* If the device is in reset in AER path, skip processing hardware errors */
> + if (xe_device_is_in_reset(xe))
> + return;
> +
> + xe_ras_process_errors(xe);
also here the return value is completely ignored: we need to
handle the action if we, e.g., receive a
XE_RAS_RECOVERY_ACTION_RESET.
Andi
> + return;
> + }
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
` (2 preceding siblings ...)
2026-10-28 16:15 ` Andi Shyti
@ 2026-10-28 16:17 ` Andi Shyti
2026-10-29 8:20 ` Tauro, Riana
3 siblings, 1 reply; 42+ messages in thread
From: Andi Shyti @ 2026-10-28 16:17 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
One more question here...
...
> /*
> - * Hardware errors are reported through System Controller on the platforms that
> - * support it, and never routed as direct IRQ to SGUnit. So we should never be
> - * here for those platforms.
> + * Non fatal errors are routed as a direct IRQ on platforms that support
> + * system controller.
> */
> if (xe->info.has_sysctrl) {
> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error routing\n");
> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n", hw_err_to_str(hw_err),
> + severity_str);
> + schedule_delayed_work(&tile->hw_error_work, msecs_to_jiffies(MSEC_PER_SEC));
why are we waiting one second here? How did you choose this time?
Andi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper
2026-10-26 6:05 ` [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper Riana Tauro
2026-10-28 9:45 ` Mallesh, Koujalagi
@ 2026-10-28 16:19 ` Andi Shyti
2026-10-29 8:28 ` Tauro, Riana
1 sibling, 1 reply; 42+ messages in thread
From: Andi Shyti @ 2026-10-28 16:19 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Hi Riana,
On Mon, Oct 26, 2026 at 11:35:05AM +0530, Riana Tauro wrote:
> Move the USP lookup logic out of RAS code and into the PCI
> layer so it can be reused by other callers.
>
> No functional change.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors
2026-10-26 6:05 ` [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors Riana Tauro
@ 2026-10-28 16:25 ` Andi Shyti
2026-10-29 5:18 ` Mallesh, Koujalagi
1 sibling, 0 replies; 42+ messages in thread
From: Andi Shyti @ 2026-10-28 16:25 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Hi Riana,
On Mon, Oct 26, 2026 at 11:35:07AM +0530, Riana Tauro wrote:
> There are two paths for error reporting. Uncorrectable non-fatal device
> errors are reported via direct IRQ. Uncorrectable device fatal errors are
> downgraded as non fatal uncorrectable internal errors and reported as AER.
> Set the default action to Secondary Bus Reset (SBR) for device fatal
> uncorrectable errors.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thanks,
Andi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path
2026-10-26 6:05 ` [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path Riana Tauro
@ 2026-10-28 16:26 ` Andi Shyti
2026-10-29 5:25 ` Mallesh, Koujalagi
1 sibling, 0 replies; 42+ messages in thread
From: Andi Shyti @ 2026-10-28 16:26 UTC (permalink / raw)
To: Riana Tauro
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Hi Riana,
On Mon, Oct 26, 2026 at 11:35:08AM +0530, Riana Tauro wrote:
> Device fatal errors trigger AER, which can race with non-fatal
> double-bit ECC errors reported via IRQ. If the AER PCI error handler
> runs first, it receives all errors as a single response from the
> system controller firmware, which can include the double-bit ECC errors.
>
> Handling these on the AER path leads to unnecessary page offlining,
> since an SBR clears the offlined pages on reload and firmware drops them
> from its queue once read. Skip double-bit ECC handling when on the AER
> path to avoid this.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thankss,
Andi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors
2026-10-26 6:05 ` [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors Riana Tauro
2026-10-28 16:25 ` Andi Shyti
@ 2026-10-29 5:18 ` Mallesh, Koujalagi
1 sibling, 0 replies; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-29 5:18 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 26-10-2026 11:35 am, Riana Tauro wrote:
> There are two paths for error reporting. Uncorrectable non-fatal device
> errors are reported via direct IRQ. Uncorrectable device fatal errors are
> downgraded as non fatal uncorrectable internal errors and reported as AER.
> Set the default action to Secondary Bus Reset (SBR) for device fatal
> uncorrectable errors.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
LGTM,
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ras.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 42fb24366a6b..3b07b2fa8cd4 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -3,6 +3,8 @@
> * Copyright © 2026 Intel Corporation
> */
>
> +#include <generated/xe_device_wa_oob.h>
> +
> #include "xe_assert.h"
> #include "xe_bo.h"
> #include "xe_configfs.h"
> @@ -20,6 +22,7 @@
> #include "xe_sysctrl_mailbox.h"
> #include "xe_sysctrl_mailbox_types.h"
> #include "xe_ttm_vram_mgr.h"
> +#include "xe_wa.h"
> #include "xe_wedge.h"
>
> /* Any non-null entry marks the page as offlined by firmware */
> @@ -718,6 +721,7 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
> enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
> {
> struct xe_sysctrl_mailbox_command command = {0};
> + struct xe_ras_state *ras = &xe->ras.state;
> enum xe_ras_recovery_action final_action;
> u32 remaining = XE_SYSCTRL_FLOOD_LIMIT;
> struct xe_ras_get_soc_error response;
> @@ -735,9 +739,16 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
> return XE_RAS_RECOVERY_ACTION_RECOVERED;
>
> BUILD_BUG_ON(BITS_PER_TYPE(sent) < XE_RAS_COMP_MAX);
> - /* Default action */
> + /* Default action for PCIe bus errors */
> final_action = XE_RAS_RECOVERY_ACTION_RECOVERED;
>
> + /*
> + * Device fatal errors are downgraded to non-fatal and reported as an uncorrectable
> + * internal error. Set the default action to reset.
> + */
> + if (ras->aer_path && XE_DEVICE_WA(xe, 14028434957))
> + final_action = XE_RAS_RECOVERY_ACTION_RESET;
> +
> xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_SOC_ERROR,
> NULL, 0, &response, sizeof(response));
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path
2026-10-26 6:05 ` [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path Riana Tauro
2026-10-28 16:26 ` Andi Shyti
@ 2026-10-29 5:25 ` Mallesh, Koujalagi
1 sibling, 0 replies; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-29 5:25 UTC (permalink / raw)
To: Riana Tauro, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 26-10-2026 11:35 am, Riana Tauro wrote:
> Device fatal errors trigger AER, which can race with non-fatal
> double-bit ECC errors reported via IRQ. If the AER PCI error handler
> runs first, it receives all errors as a single response from the
> system controller firmware, which can include the double-bit ECC errors.
>
> Handling these on the AER path leads to unnecessary page offlining,
> since an SBR clears the offlined pages on reload and firmware drops them
> from its queue once read. Skip double-bit ECC handling when on the AER
> path to avoid this.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
LGTM,
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
> drivers/gpu/drm/xe/xe_ras.c | 19 ++++++++++++++++++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 3b07b2fa8cd4..22ecca10b7a2 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -598,6 +598,7 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
> static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
> {
> struct xe_ras_memory_error *info = (void *)arr->details;
> + struct xe_ras_state *ras = &xe->ras.state;
> int ret;
>
> /*
> @@ -615,9 +616,25 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
> xe_info(xe, "[RAS]: Data parity error detected\n");
> break;
> case XE_RAS_MEMORY_DB_ECC:
> - ret = handle_page_offline(xe, info->sw_address, true);
> /*
> * Double-bit ECC errors are non-fatal errors and are reported via IRQ.
> + * On a race between AER for device fatal errors and non-fatal double-bit ECC
> + * errors, if AER pci error handlers execute first it will get all errors as
> + * a single response from system controller, which can include the double-bit
> + * ECC errors. This leads to unnecessary offlining of pages, since an SBR clears
> + * them on reload and firmware drops them from its queue once read.
> + * Skip handling of double-bit ECC errors on the AER path to avoid this.
> + *
> + * TODO: Remove this check once AER handling is optimized to retain soft
> + * offlined pages.
> + */
> + if (ras->aer_path) {
> + xe_info(xe, "[RAS]: Skipping double-bit ECC error handling on AER path\n");
> + break;
> + }
> +
> + ret = handle_page_offline(xe, info->sw_address, true);
> + /*
> * Wedge the device with a bus reset for errors that require SBR to recover.
> * TODO: Trigger SBR using pci_reset_bus
> */
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-26 14:08 ` Tauro, Riana
@ 2026-10-29 6:36 ` Mallesh, Koujalagi
2026-10-29 8:17 ` Tauro, Riana
0 siblings, 1 reply; 42+ messages in thread
From: Mallesh, Koujalagi @ 2026-10-29 6:36 UTC (permalink / raw)
To: Tauro, Riana, Upadhyay, Tejas, intel-xe@lists.freedesktop.org
Cc: Gupta, Anshuman, Vivi, Rodrigo,
aravind.iddamsetty@linux.intel.com, Nilawar, Badal, Jadav, Raag,
Koppuravuri, Ravi Kishore
On 26-10-2026 07:38 pm, Tauro, Riana wrote:
>
> On 26-10-2026 16:19, Upadhyay, Tejas wrote:
>>
>>> -----Original Message-----
>>> From: Tauro, Riana <riana.tauro@intel.com>
>>> Sent: 26 October 2026 11:35
>>> To: intel-xe@lists.freedesktop.org
>>> Cc: Tauro, Riana <riana.tauro@intel.com>; Gupta, Anshuman
>>> <anshuman.gupta@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>>> aravind.iddamsetty@linux.intel.com; Nilawar, Badal
>>> <badal.nilawar@intel.com>; Jadav, Raag <raag.jadav@intel.com>;
>>> Koppuravuri, Ravi Kishore <ravi.kishore.koppuravuri@intel.com>;
>>> Koujalagi,
>>> Mallesh <mallesh.koujalagi@intel.com>; Upadhyay, Tejas
>>> <tejas.upadhyay@intel.com>
>>> Subject: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors
>>> routed
>>> via direct IRQ
>>>
>>> Process, log and recover non-fatal errors routed via direct IRQ.
>>> Double-bit ecc errors belong to non-fatal error category and are
>>> reported via
>>> irq. For pages that belong to critical BO, wedge the device with
>>> bus-reset as
>>> the recovery action.
>>>
>>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/xe_hw_error.c | 37
>>> ++++++++++++++++++++++++++++----
>>> drivers/gpu/drm/xe/xe_ras.c | 9 +++++++-
>>> 2 files changed, 41 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>>> b/drivers/gpu/drm/xe/xe_hw_error.c
>>> index f7799c3c08aa..269ce6a19a80 100644
>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>> @@ -5,6 +5,8 @@
>>>
>>> #include <linux/bitmap.h>
>>>
>>> +#include <generated/xe_device_wa_oob.h>
>>> +
>>> #include "regs/xe_gsc_regs.h"
>>> #include "regs/xe_hw_error_regs.h"
>>> #include "regs/xe_irq_regs.h"
>>> @@ -15,7 +17,9 @@
>>> #include "xe_hw_error.h"
>>> #include "xe_mmio.h"
>>> #include "xe_pm.h"
>>> +#include "xe_ras.h"
>>> #include "xe_survivability_mode.h"
>>> +#include "xe_wa.h"
>>>
>>> #define GT_HW_ERROR_MAX_ERR_BITS 16
>>> #define HEC_UNCORR_FW_ERR_BITS 4
>>> @@ -166,12 +170,36 @@
>>> static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) ==
>>> XE_RAS_REG_SIZE);
>>>
>>> pvc_master_local_fatal_err_reg : \
>>>
>>> pvc_master_local_nonfatal_err_reg)
>>>
>>> +static const char *hw_err_to_str(const enum hardware_error hw_err) {
>>> + switch (hw_err) {
>>> + case HARDWARE_ERROR_CORRECTABLE:
>>> + return "Correctable";
>>> + case HARDWARE_ERROR_NONFATAL:
>>> + return "Non-Fatal";
>>> + case HARDWARE_ERROR_FATAL:
>>> + return "Fatal";
>>> + default:
>>> + return "Unknown";
>>> + }
>>> +}
>>> +
>>> static void hw_error_work(struct work_struct *work) {
>>> struct xe_tile *tile = container_of(work, typeof(*tile),
>>> hw_error_work.work);
>>> struct xe_device *xe = tile_to_xe(tile);
>>>
>>> guard(xe_pm_runtime)(xe);
>>> +
>>> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
>> I think you should have all these in 1 patch for 14028434957
>
> I can combine 3 and 4. If i combine all usages, it would be difficult
> to review.
>
> Thanks
> Riana
>
>>
>> Tejas
>>> + /* If the device is in reset in AER path, skip processing
>>> hardware errors */
>>> + if (xe_device_is_in_reset(xe))
>>> + return;
>>> +
>>> + xe_ras_process_errors(xe);
>>> + return;
>>> + }
>>> +
>>> xe_survivability_mode_runtime_enable(xe);
>>> }
>>>
>>> @@ -433,12 +461,13 @@ static void hw_error_source_handler(struct
>>> xe_tile
>>> *tile, const enum hardware_er
>>> return;
>>>
>>> /*
>>> - * Hardware errors are reported through System Controller on the
>>> platforms that
>>> - * support it, and never routed as direct IRQ to SGUnit. So we
>>> should
>>> never be
>>> - * here for those platforms.
>>> + * Non fatal errors are routed as a direct IRQ on platforms
>>> that support
>>> + * system controller.
>>> */
>>> if (xe->info.has_sysctrl) {
>>> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error
>>> routing\n");
>>> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n",
>>> hw_err_to_str(hw_err),
>>> + severity_str);
>>> + schedule_delayed_work(&tile->hw_error_work,
>>> +msecs_to_jiffies(MSEC_PER_SEC));
hmm, why we are scheduling hw_error_work worker after 1 sec, if we get
AER before and after 1 sec, what is impact?
Thanks,
-/Mallesh
>>> return;
>>> }
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_ras.c
>>> b/drivers/gpu/drm/xe/xe_ras.c index
>>> db3cbc186a51..e6a0ee468b17 100644
>>> --- a/drivers/gpu/drm/xe/xe_ras.c
>>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>>> @@ -628,8 +628,15 @@ static u8 handle_device_memory_errors(struct
>>> xe_device *xe, struct xe_ras_error_
>>> break;
>>> case XE_RAS_MEMORY_DB_ECC:
>>> ret = handle_page_offline(xe, info->sw_address, true);
>>> - if (ret)
>>> + /*
>>> + * Double-bit ECC errors are non-fatal errors and are reported
>>> via IRQ.
>>> + * Wedge the device with a bus reset for errors that require
>>> SBR to recover.
>>> + * TODO: Trigger SBR using pci_reset_bus
>>> + */
>>> + if (ret) {
>>> + xe_wedge_declare(xe,
>>> DRM_WEDGE_RECOVERY_BUS_RESET);
>>> return XE_RAS_RECOVERY_ACTION_RESET;
>>> + }
>>> break;
>>> default:
>>> return XE_RAS_RECOVERY_ACTION_RESET;
>>> --
>>> 2.47.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling
2026-10-27 13:01 ` Mallesh, Koujalagi
@ 2026-10-29 8:07 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:07 UTC (permalink / raw)
To: Mallesh, Koujalagi, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 27-10-2026 18:31, Mallesh, Koujalagi wrote:
>
> On 26-10-2026 11:35 am, Riana Tauro wrote:
>> Convert the CSC hardware error worker to a delayed work item so it
>> can be reused for generic hardware error handling in later patches.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_hw_error.c | 10 +++++-----
>> drivers/gpu/drm/xe/xe_tile_types.h | 6 +++---
>> 2 files changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>> b/drivers/gpu/drm/xe/xe_hw_error.c
>> index ac720710c8e8..41ddd997478b 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -166,9 +166,9 @@
>> static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) ==
>> XE_RAS_REG_SIZE);
>> pvc_master_local_fatal_err_reg : \
>> pvc_master_local_nonfatal_err_reg)
>> -static void csc_hw_error_work(struct work_struct *work)
>> +static void hw_error_work(struct work_struct *work)
>> {
>> - struct xe_tile *tile = container_of(work, typeof(*tile),
>> csc_hw_error_work);
>> + struct xe_tile *tile = container_of(work, typeof(*tile),
>> hw_error_work.work);
>> struct xe_device *xe = tile_to_xe(tile);
>> guard(xe_pm_runtime)(xe);
>> @@ -204,7 +204,7 @@ static void csc_hw_error_handler(struct xe_tile
>> *tile, const enum hardware_error
>> hec_uncorrected_fw_errors[err_bit],
>> severity_str,
>> err_bit);
>> - schedule_work(&tile->csc_hw_error_work);
>> + schedule_delayed_work(&tile->hw_error_work, 0);
>
> hmm, what is rational to use delay work? and making CSC work as
> generic hardware error handling?
>
> do u see any impact when we trigger fault injection etc.
This is used in patch [4]
We shouldn't have csc error injection in systems with sysctrl. So
shouldn't affect.
Thanks
Riana
>
>> }
>> }
>> @@ -513,7 +513,7 @@ void xe_hw_error_irq_handler(struct xe_tile
>> *tile, const u32 master_ctl)
>> enum hardware_error hw_err;
>> if (xe_fault_csc_hw_error())
>> - schedule_work(&tile->csc_hw_error_work);
>> + schedule_delayed_work(&tile->hw_error_work, 0);
>> for (hw_err = 0; hw_err < HARDWARE_ERROR_MAX; hw_err++) {
>> if (master_ctl & ERROR_IRQ(hw_err))
>> @@ -551,7 +551,7 @@ void xe_hw_error_init(struct xe_device *xe)
>> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
>> return;
>> - INIT_WORK(&tile->csc_hw_error_work, csc_hw_error_work);
>> + INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>> process_hw_errors(xe);
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h
>> b/drivers/gpu/drm/xe/xe_tile_types.h
>> index e1368c04846a..0f41738635c5 100644
>> --- a/drivers/gpu/drm/xe/xe_tile_types.h
>> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
>> @@ -7,7 +7,7 @@
>> #define _XE_TILE_TYPES_H_
>> #include <linux/mutex_types.h>
>> -#include <linux/workqueue_types.h>
>> +#include <linux/workqueue.h>
>> #include "xe_lmtt_types.h"
>> #include "xe_memirq_types.h"
>> @@ -118,8 +118,8 @@ struct xe_tile {
>> /** @memirq: Memory Based Interrupts. */
>> struct xe_memirq memirq;
>> - /** @csc_hw_error_work: worker to report CSC HW errors */
>> - struct work_struct csc_hw_error_work;
>> + /** @hw_error_work: delayed work to handle HW errors */
>> + struct delayed_work hw_error_work;
>> /** @pcode: tile's PCODE */
>> struct {
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile
2026-10-27 14:51 ` Mallesh, Koujalagi
@ 2026-10-29 8:11 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:11 UTC (permalink / raw)
To: Mallesh, Koujalagi, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 27-10-2026 20:21, Mallesh, Koujalagi wrote:
>
> On 26-10-2026 11:35 am, Riana Tauro wrote:
>> From: Raag Jadav <raag.jadav@intel.com>
>>
>> Since hw_error_work is now being reused generically, initialize it
>> per tile
>> so that we don't hit uninitialized work for non-root tile. While at it,
>> disable hw_error_work on fini to prevent UAF during unwind.
>>
>> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
>> Reviewed-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_hw_error.c | 24 ++++++++++++++++++++++--
>> drivers/gpu/drm/xe/xe_hw_error.h | 1 +
>> 2 files changed, 23 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>> b/drivers/gpu/drm/xe/xe_hw_error.c
>> index 41ddd997478b..f7799c3c08aa 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>> @@ -537,6 +537,23 @@ static void process_hw_errors(struct xe_device *xe)
>> }
>> }
>> +/**
>> + * xe_hw_error_work_disable - Disable hw error work
>> + * @arg: xe device instance
>> + *
>> + * This function disables the delayed work for hardware error handling
>> + * for all tiles.
>> + */
>> +void xe_hw_error_work_disable(void *arg)
>> +{
>> + struct xe_device *xe = arg;
>> + struct xe_tile *tile;
>> + u8 id;
>> +
>> + for_each_tile(tile, xe, id)
>> + disable_delayed_work_sync(&tile->hw_error_work);
>> +}
>> +
>
> hmm, we are disabling hw_error_work.
>
> IMO, if we see non-fatal error fires on the IRQ path (since it's
> asynchronous), since the work is still disabled,
This is done on device remove on unbind. So by the time this runs, irq
is already disabled.
There is no way irq will get triggered.
But there is sashiko comment on adding devm inside another devm. Will
fix that.
Thanks
Riana
>
> it would not be processed further.
>
>
> Thanks,
>
> -/Mallesh
>
>> /**
>> * xe_hw_error_init - Initialize hw errors
>> * @xe: xe device instance
>> @@ -546,12 +563,15 @@ static void process_hw_errors(struct xe_device
>> *xe)
>> */
>> void xe_hw_error_init(struct xe_device *xe)
>> {
>> - struct xe_tile *tile = xe_device_get_root_tile(xe);
>> + struct xe_tile *tile;
>> + u8 id;
>> if (!IS_DGFX(xe) || IS_SRIOV_VF(xe))
>> return;
>> - INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>> + for_each_tile(tile, xe, id)
>> + INIT_DELAYED_WORK(&tile->hw_error_work, hw_error_work);
>> process_hw_errors(xe);
>> + devm_add_action_or_reset(xe->drm.dev, xe_hw_error_work_disable,
>> xe);
>> }
>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.h
>> b/drivers/gpu/drm/xe/xe_hw_error.h
>> index 5e3a11424108..c2c0bfa6d9f9 100644
>> --- a/drivers/gpu/drm/xe/xe_hw_error.h
>> +++ b/drivers/gpu/drm/xe/xe_hw_error.h
>> @@ -12,4 +12,5 @@ struct xe_device;
>> void xe_hw_error_irq_handler(struct xe_tile *tile, const u32
>> master_ctl);
>> void xe_hw_error_init(struct xe_device *xe);
>> +void xe_hw_error_work_disable(void *arg);
>> #endif
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11
2026-10-28 6:16 ` Mallesh, Koujalagi
@ 2026-10-29 8:12 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:12 UTC (permalink / raw)
To: Mallesh, Koujalagi, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay, Varun Gupta
On 28-10-2026 11:46, Mallesh, Koujalagi wrote:
>
> On 26-10-2026 11:35 am, Riana Tauro wrote:
>> From: Varun Gupta <varun.gupta@intel.com>
>>
>> Add wa_14028434957 for Graphics Version 35.11 to the table.
>>
>> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
>> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> index d8dc41851425..36b2567994db 100644
>> --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> @@ -7,3 +7,4 @@
>> 14026633728 PLATFORM(CRESCENTISLAND)
>> 14026746987 PLATFORM(CRESCENTISLAND)
>> 14026779378 PLATFORM(CRESCENTISLAND)
>> +14028434957 PLATFORM(CRESCENTISLAND)
>
> can you please combine 3 and 4 patches?
Yeah will do that. Took a patch from different author . So split it.
Thanks
Riana
>
> Thanks,
>
> -/Mallesh
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-29 6:36 ` Mallesh, Koujalagi
@ 2026-10-29 8:17 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:17 UTC (permalink / raw)
To: Mallesh, Koujalagi, Upadhyay, Tejas,
intel-xe@lists.freedesktop.org
Cc: Gupta, Anshuman, Vivi, Rodrigo,
aravind.iddamsetty@linux.intel.com, Nilawar, Badal, Jadav, Raag,
Koppuravuri, Ravi Kishore
On 29-10-2026 12:06, Mallesh, Koujalagi wrote:
>
> On 26-10-2026 07:38 pm, Tauro, Riana wrote:
>>
>> On 26-10-2026 16:19, Upadhyay, Tejas wrote:
>>>
>>>> -----Original Message-----
>>>> From: Tauro, Riana <riana.tauro@intel.com>
>>>> Sent: 26 October 2026 11:35
>>>> To: intel-xe@lists.freedesktop.org
>>>> Cc: Tauro, Riana <riana.tauro@intel.com>; Gupta, Anshuman
>>>> <anshuman.gupta@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>>>> aravind.iddamsetty@linux.intel.com; Nilawar, Badal
>>>> <badal.nilawar@intel.com>; Jadav, Raag <raag.jadav@intel.com>;
>>>> Koppuravuri, Ravi Kishore <ravi.kishore.koppuravuri@intel.com>;
>>>> Koujalagi,
>>>> Mallesh <mallesh.koujalagi@intel.com>; Upadhyay, Tejas
>>>> <tejas.upadhyay@intel.com>
>>>> Subject: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors
>>>> routed
>>>> via direct IRQ
>>>>
>>>> Process, log and recover non-fatal errors routed via direct IRQ.
>>>> Double-bit ecc errors belong to non-fatal error category and are
>>>> reported via
>>>> irq. For pages that belong to critical BO, wedge the device with
>>>> bus-reset as
>>>> the recovery action.
>>>>
>>>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/xe_hw_error.c | 37
>>>> ++++++++++++++++++++++++++++----
>>>> drivers/gpu/drm/xe/xe_ras.c | 9 +++++++-
>>>> 2 files changed, 41 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c
>>>> b/drivers/gpu/drm/xe/xe_hw_error.c
>>>> index f7799c3c08aa..269ce6a19a80 100644
>>>> --- a/drivers/gpu/drm/xe/xe_hw_error.c
>>>> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
>>>> @@ -5,6 +5,8 @@
>>>>
>>>> #include <linux/bitmap.h>
>>>>
>>>> +#include <generated/xe_device_wa_oob.h>
>>>> +
>>>> #include "regs/xe_gsc_regs.h"
>>>> #include "regs/xe_hw_error_regs.h"
>>>> #include "regs/xe_irq_regs.h"
>>>> @@ -15,7 +17,9 @@
>>>> #include "xe_hw_error.h"
>>>> #include "xe_mmio.h"
>>>> #include "xe_pm.h"
>>>> +#include "xe_ras.h"
>>>> #include "xe_survivability_mode.h"
>>>> +#include "xe_wa.h"
>>>>
>>>> #define GT_HW_ERROR_MAX_ERR_BITS 16
>>>> #define HEC_UNCORR_FW_ERR_BITS 4
>>>> @@ -166,12 +170,36 @@
>>>> static_assert(ARRAY_SIZE(pvc_master_local_nonfatal_err_reg) ==
>>>> XE_RAS_REG_SIZE);
>>>>
>>>> pvc_master_local_fatal_err_reg : \
>>>>
>>>> pvc_master_local_nonfatal_err_reg)
>>>>
>>>> +static const char *hw_err_to_str(const enum hardware_error hw_err) {
>>>> + switch (hw_err) {
>>>> + case HARDWARE_ERROR_CORRECTABLE:
>>>> + return "Correctable";
>>>> + case HARDWARE_ERROR_NONFATAL:
>>>> + return "Non-Fatal";
>>>> + case HARDWARE_ERROR_FATAL:
>>>> + return "Fatal";
>>>> + default:
>>>> + return "Unknown";
>>>> + }
>>>> +}
>>>> +
>>>> static void hw_error_work(struct work_struct *work) {
>>>> struct xe_tile *tile = container_of(work, typeof(*tile),
>>>> hw_error_work.work);
>>>> struct xe_device *xe = tile_to_xe(tile);
>>>>
>>>> guard(xe_pm_runtime)(xe);
>>>> +
>>>> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
>>> I think you should have all these in 1 patch for 14028434957
>>
>> I can combine 3 and 4. If i combine all usages, it would be
>> difficult to review.
>>
>> Thanks
>> Riana
>>
>>>
>>> Tejas
>>>> + /* If the device is in reset in AER path, skip processing
>>>> hardware errors */
>>>> + if (xe_device_is_in_reset(xe))
>>>> + return;
>>>> +
>>>> + xe_ras_process_errors(xe);
>>>> + return;
>>>> + }
>>>> +
>>>> xe_survivability_mode_runtime_enable(xe);
>>>> }
>>>>
>>>> @@ -433,12 +461,13 @@ static void hw_error_source_handler(struct
>>>> xe_tile
>>>> *tile, const enum hardware_er
>>>> return;
>>>>
>>>> /*
>>>> - * Hardware errors are reported through System Controller on the
>>>> platforms that
>>>> - * support it, and never routed as direct IRQ to SGUnit. So we
>>>> should
>>>> never be
>>>> - * here for those platforms.
>>>> + * Non fatal errors are routed as a direct IRQ on platforms
>>>> that support
>>>> + * system controller.
>>>> */
>>>> if (xe->info.has_sysctrl) {
>>>> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error
>>>> routing\n");
>>>> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n",
>>>> hw_err_to_str(hw_err),
>>>> + severity_str);
>>>> + schedule_delayed_work(&tile->hw_error_work,
>>>> +msecs_to_jiffies(MSEC_PER_SEC));
>
> hmm, why we are scheduling hw_error_work worker after 1 sec, if we get
> AER before and after 1 sec, what is impact?
Its a best case scenario that if there is a non-fatal error which is
accompanied with a fatal at the same time. We will wait
for AER to get triggered to avoid unnecessary handling of non-fatal errors.
It is not guaranteed that we will see a AER in 1sec because even that
is a worker.
If we get AER when irq handling is in progress, it will wait for it to
complete before triggering a reset,
After 1sec is a same as normal scenario of irq followed by AER
Thanks
Riana
>
> Thanks,
>
> -/Mallesh
>
>>>> return;
>>>> }
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_ras.c
>>>> b/drivers/gpu/drm/xe/xe_ras.c index
>>>> db3cbc186a51..e6a0ee468b17 100644
>>>> --- a/drivers/gpu/drm/xe/xe_ras.c
>>>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>>>> @@ -628,8 +628,15 @@ static u8 handle_device_memory_errors(struct
>>>> xe_device *xe, struct xe_ras_error_
>>>> break;
>>>> case XE_RAS_MEMORY_DB_ECC:
>>>> ret = handle_page_offline(xe, info->sw_address, true);
>>>> - if (ret)
>>>> + /*
>>>> + * Double-bit ECC errors are non-fatal errors and are
>>>> reported
>>>> via IRQ.
>>>> + * Wedge the device with a bus reset for errors that require
>>>> SBR to recover.
>>>> + * TODO: Trigger SBR using pci_reset_bus
>>>> + */
>>>> + if (ret) {
>>>> + xe_wedge_declare(xe,
>>>> DRM_WEDGE_RECOVERY_BUS_RESET);
>>>> return XE_RAS_RECOVERY_ACTION_RESET;
>>>> + }
>>>> break;
>>>> default:
>>>> return XE_RAS_RECOVERY_ACTION_RESET;
>>>> --
>>>> 2.47.1
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-28 16:17 ` Andi Shyti
@ 2026-10-29 8:20 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:20 UTC (permalink / raw)
To: Andi Shyti
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
On 28-10-2026 21:47, Andi Shyti wrote:
> One more question here...
>
> ...
>
>> /*
>> - * Hardware errors are reported through System Controller on the platforms that
>> - * support it, and never routed as direct IRQ to SGUnit. So we should never be
>> - * here for those platforms.
>> + * Non fatal errors are routed as a direct IRQ on platforms that support
>> + * system controller.
>> */
>> if (xe->info.has_sysctrl) {
>> - drm_err_ratelimited(&xe->drm, HW_ERR "Invalid error routing\n");
>> + drm_err_ratelimited(&xe->drm, HW_ERR "%s %s reported\n", hw_err_to_str(hw_err),
>> + severity_str);
>> + schedule_delayed_work(&tile->hw_error_work, msecs_to_jiffies(MSEC_PER_SEC));
> why are we waiting one second here? How did you choose this time?
Its a best case scenario that if there is a non-fatal error which is
accompanied with a fatal at the same time.
We will wait for AER to get triggered to avoid unnecessary handling of
non-fatal errors.
It is not guaranteed that we will see a AER in 1sec because even that is
a worker.
If this is not okay, we can drop it as we are waiting for worker to
complete anyway.
Thanks
Riana
>
> Andi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ
2026-10-28 16:15 ` Andi Shyti
@ 2026-10-29 8:23 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:23 UTC (permalink / raw)
To: Andi Shyti
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
Hi Andi
On 28-10-2026 21:45, Andi Shyti wrote:
> Hi Riana,
>
> ...
>
>> static void hw_error_work(struct work_struct *work)
>> {
>> struct xe_tile *tile = container_of(work, typeof(*tile), hw_error_work.work);
>> struct xe_device *xe = tile_to_xe(tile);
>>
>> guard(xe_pm_runtime)(xe);
>> +
>> + if (xe->info.has_sysctrl && XE_DEVICE_WA(xe, 14028434957)) {
>> + /* If the device is in reset in AER path, skip processing hardware errors */
>> + if (xe_device_is_in_reset(xe))
>> + return;
>> +
>> + xe_ras_process_errors(xe);
> also here the return value is completely ignored: we need to
> handle the action if we, e.g., receive a
> XE_RAS_RECOVERY_ACTION_RESET.
We are re-using the same function as AER handling as the firmware query
is common for both.
For non-fatal errors received via irq, we do not expect a reset.
Handling of reset is not required in
this path. Will add a comment.
Thanks
Riana
>
> Andi
>
>> + return;
>> + }
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered
2026-10-28 9:24 ` Mallesh, Koujalagi
@ 2026-10-29 8:27 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:27 UTC (permalink / raw)
To: Mallesh, Koujalagi, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, tejas.upadhyay
On 28-10-2026 14:54, Mallesh, Koujalagi wrote:
>
> On 26-10-2026 11:35 am, Riana Tauro wrote:
>> On systems lacking RAS capability, only PCIe errors are reported, via
>> AER, not device errors. Non-fatal PCIe errors reported at the Upstream
>> Switch Port (USP) have no impact on link or device state, so treat
>> them as recovered without requiring a secondary bus reset (SBR).
>>
>> Fixes: 25913a062cd4 ("drm/xe/xe_ras: Add support for uncorrectable
>> core-compute errors")
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_ras.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>> index e6a0ee468b17..2b1a7cb01b0d 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -747,7 +747,7 @@ enum xe_ras_recovery_action
>> xe_ras_process_errors(struct xe_device *xe)
>> }
>> if (!xe->info.has_sysctrl)
>> - return XE_RAS_RECOVERY_ACTION_RESET;
>
> Initially we see Non-fatal PCIe errors reporting via USP required SBR,
> however what is rationale behind, not required SBR now?
This was a miss from my end. I have added the details in the commit message.
If you see pcie port driver also, it doesn't reset for pcie bus errors.
I can split this patch out of this series too as it's not related.
Thanks
Riana
>
> Thanks,
>
> -/Mallesh
>
>> + return XE_RAS_RECOVERY_ACTION_RECOVERED;
>> BUILD_BUG_ON(BITS_PER_TYPE(sent) < XE_RAS_COMP_MAX);
>> /* Default action */
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper
2026-10-28 16:19 ` Andi Shyti
@ 2026-10-29 8:28 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:28 UTC (permalink / raw)
To: Andi Shyti
Cc: intel-xe, anshuman.gupta, rodrigo.vivi, aravind.iddamsetty,
badal.nilawar, raag.jadav, ravi.kishore.koppuravuri,
mallesh.koujalagi, tejas.upadhyay
On 28-10-2026 21:49, Andi Shyti wrote:
> Hi Riana,
>
> On Mon, Oct 26, 2026 at 11:35:05AM +0530, Riana Tauro wrote:
>> Move the USP lookup logic out of RAS code and into the PCI
>> layer so it can be reused by other callers.
>>
>> No functional change.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Thank you for the review
>
> Thanks,
> Andi
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11
2026-10-28 14:19 ` Gustavo Sousa
@ 2026-10-29 8:32 ` Tauro, Riana
0 siblings, 0 replies; 42+ messages in thread
From: Tauro, Riana @ 2026-10-29 8:32 UTC (permalink / raw)
To: Gustavo Sousa, intel-xe
Cc: anshuman.gupta, rodrigo.vivi, aravind.iddamsetty, badal.nilawar,
raag.jadav, ravi.kishore.koppuravuri, mallesh.koujalagi,
tejas.upadhyay, Varun Gupta
On 28-10-2026 19:49, Gustavo Sousa wrote:
> Riana Tauro <riana.tauro@intel.com> writes:
>
>> From: Varun Gupta <varun.gupta@intel.com>
>>
>> Add wa_14028434957 for Graphics Version 35.11 to the table.
>>
>> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
>> Signed-off-by: Varun Gupta <varun.gupta@intel.com>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_device_wa_oob.rules | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device_wa_oob.rules b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> index d8dc41851425..36b2567994db 100644
>> --- a/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> +++ b/drivers/gpu/drm/xe/xe_device_wa_oob.rules
>> @@ -7,3 +7,4 @@
>> 14026633728 PLATFORM(CRESCENTISLAND)
>> 14026746987 PLATFORM(CRESCENTISLAND)
>> 14026779378 PLATFORM(CRESCENTISLAND)
>> +14028434957 PLATFORM(CRESCENTISLAND)
> This conflicts with the patch description. If the workaround applies to
> graphics version 35.11, then the rule here should use GRAPHICS_VERSION()
> instead of PLATFORM(). Now, if this is a platform-specific workaround,
> then the commit message should be rewritten to reflect that.
I picked this patch from another series and retained the subject.
Will fix the subject and commit message.
Thanks
Riana
>
> --
> Gustavo Sousa
^ permalink raw reply [flat|nested] 42+ messages in thread
end of thread, other threads:[~2026-10-29 8:33 UTC | newest]
Thread overview: 42+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-10-26 6:04 [PATCH v2 0/9] Handle non-fatal errors routed via IRQ Riana Tauro
2026-10-26 6:05 ` [PATCH v2 1/9] drm/xe/hw_error: Reuse CSC worker for generic error handling Riana Tauro
2026-10-27 13:01 ` Mallesh, Koujalagi
2026-10-29 8:07 ` Tauro, Riana
2026-10-26 6:05 ` [PATCH v2 2/9] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
2026-10-26 9:37 ` sashiko-bot
2026-10-27 14:51 ` Mallesh, Koujalagi
2026-10-29 8:11 ` Tauro, Riana
2026-10-28 16:07 ` Andi Shyti
2026-10-26 6:05 ` [PATCH v2 3/9] drm/xe: Add wa_14028434957 to Graphics Version 35.11 Riana Tauro
2026-10-28 6:16 ` Mallesh, Koujalagi
2026-10-29 8:12 ` Tauro, Riana
2026-10-28 14:19 ` Gustavo Sousa
2026-10-29 8:32 ` Tauro, Riana
2026-10-26 6:05 ` [PATCH v2 4/9] drm/xe/xe_hw_error: Handle non-fatal errors routed via direct IRQ Riana Tauro
2026-10-26 10:09 ` sashiko-bot
2026-10-26 10:49 ` Upadhyay, Tejas
2026-10-26 14:08 ` Tauro, Riana
2026-10-29 6:36 ` Mallesh, Koujalagi
2026-10-29 8:17 ` Tauro, Riana
2026-10-28 16:15 ` Andi Shyti
2026-10-29 8:23 ` Tauro, Riana
2026-10-28 16:17 ` Andi Shyti
2026-10-29 8:20 ` Tauro, Riana
2026-10-26 6:05 ` [PATCH v2 5/9] drm/xe/ras: Treat non-fatal PCIe errors as recovered Riana Tauro
2026-10-28 9:24 ` Mallesh, Koujalagi
2026-10-29 8:27 ` Tauro, Riana
2026-10-26 6:05 ` [PATCH v2 6/9] drm/xe/pci: Add upstream switch port lookup helper Riana Tauro
2026-10-28 9:45 ` Mallesh, Koujalagi
2026-10-28 16:19 ` Andi Shyti
2026-10-29 8:28 ` Tauro, Riana
2026-10-26 6:05 ` [PATCH v2 7/9] drm/xe/xe_ras: Disable hw error worker when AER handling is in progress Riana Tauro
2026-10-26 10:32 ` sashiko-bot
2026-10-26 6:05 ` [PATCH v2 8/9] drm/xe/xe_ras: Trigger SBR for all device errors Riana Tauro
2026-10-28 16:25 ` Andi Shyti
2026-10-29 5:18 ` Mallesh, Koujalagi
2026-10-26 6:05 ` [PATCH v2 9/9] drm/xe/ras: Skip double-bit ECC page offlining on AER path Riana Tauro
2026-10-28 16:26 ` Andi Shyti
2026-10-29 5:25 ` Mallesh, Koujalagi
2026-10-26 6:30 ` ✓ CI.KUnit: success for Handle non-fatal errors routed via IRQ (rev2) Patchwork
2026-10-26 7:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-10-26 8:55 ` ✗ Xe.CI.FULL: failure " Patchwork
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