[PATCH 0/9] drm_i915_private to intel_display cleanup

[PATCH 0/9] drm_i915_private to intel_display cleanup

[Suraj Kandpal]

This series started as a cleanup to convert as many drm_i915_private
to intel_display in intel_display_debug_fs but overflowed and ended up
cleaning intel_dpll_mgr.c part of the code too and some other places
calling these functions. This series also replaces IS_PLATFORM()
with display->platform.xx to reduce drm_i915_private usage.
Some stuff that kept me from removing i915_private altogether were
PCH checks.

--v2
-Rebase

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (9):
  drm/i915/display_debug_fs: Use intel_display wherever possible
  drm/i915/display_debug_fs: Prefer using display->platform
  drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
  drm/i915/dpll: Use intel_display for dpll dump and compare hw state
  drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
  drm/i915/dpll: Use intel_display for asserting pll
  drm/i915/dpll: Use intel_display for update_refclk hook
  drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
  drm/i915/dpll: Replace all other leftover drm_i915_private

 .../drm/i915/display/intel_crtc_state_dump.c  |    3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  130 +--
 drivers/gpu/drm/i915/display/intel_display.c  |   30 +-
 .../drm/i915/display/intel_display_debugfs.c  |  173 +--
 .../drm/i915/display/intel_display_driver.c   |    4 +-
 .../i915/display/intel_display_power_well.c   |   13 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |   54 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |    9 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |   11 +-
 drivers/gpu/drm/i915/display/intel_dpll.h     |    5 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1011 ++++++++---------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   27 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   16 +-
 drivers/gpu/drm/i915/display/intel_fdi.h      |    7 +-
 drivers/gpu/drm/i915/display/intel_lvds.c     |    7 +-
 .../drm/i915/display/intel_modeset_setup.c    |    4 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   45 +-
 .../gpu/drm/i915/display/intel_pch_refclk.c   |   36 +-
 drivers/gpu/drm/i915/display/vlv_dsi_pll.c    |   12 +-
 drivers/gpu/drm/i915/display/vlv_dsi_pll.h    |   10 +-
 20 files changed, 799 insertions(+), 808 deletions(-)

-- 
2.34.1

[PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible

[Suraj Kandpal]

Use struct intel_display wherever possible in intel_display_debug_fs.c
to reduce the use of drm_i915_private.

--v2
-Rebase

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  | 158 +++++++++---------
 1 file changed, 81 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 89e5eea90be8..d85924caa26e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -68,17 +68,17 @@ static int intel_display_caps(struct seq_file *m, void *data)
 
 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 
-	spin_lock(&dev_priv->display.fb_tracking.lock);
+	spin_lock(&display->fb_tracking.lock);
 
 	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
-		   dev_priv->display.fb_tracking.busy_bits);
+		   display->fb_tracking.busy_bits);
 
 	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
-		   dev_priv->display.fb_tracking.flip_bits);
+		   display->fb_tracking.flip_bits);
 
-	spin_unlock(&dev_priv->display.fb_tracking.lock);
+	spin_unlock(&display->fb_tracking.lock);
 
 	return 0;
 }
@@ -86,25 +86,25 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
 static int i915_sr_status(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	struct intel_display *display = &dev_priv->display;
+	struct intel_display *display = node_to_intel_display(m->private);
 	intel_wakeref_t wakeref;
 	bool sr_enabled = false;
 
 	wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
 
-	if (DISPLAY_VER(dev_priv) >= 9)
+	if (DISPLAY_VER(display) >= 9)
 		/* no global SR status; inspect per-plane WM */;
 	else if (HAS_PCH_SPLIT(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
+		sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
 	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
 		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
+		sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
 	else if (IS_I915GM(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
+		sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
 	else if (IS_PINEVIEW(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
+		sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
+		sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
 
@@ -115,12 +115,12 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 
 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct intel_framebuffer *fbdev_fb = NULL;
 	struct drm_framebuffer *drm_fb;
 
 #ifdef CONFIG_DRM_FBDEV_EMULATION
-	fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
+	fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
 	if (fbdev_fb) {
 		seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
 			   fbdev_fb->base.width,
@@ -134,8 +134,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
 	}
 #endif
 
-	mutex_lock(&dev_priv->drm.mode_config.fb_lock);
-	drm_for_each_fb(drm_fb, &dev_priv->drm) {
+	mutex_lock(&display->drm->mode_config.fb_lock);
+	drm_for_each_fb(drm_fb, display->drm) {
 		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
 		if (fb == fbdev_fb)
 			continue;
@@ -150,7 +150,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
 		intel_bo_describe(m, intel_fb_bo(&fb->base));
 		seq_putc(m, '\n');
 	}
-	mutex_unlock(&dev_priv->drm.mode_config.fb_lock);
+	mutex_unlock(&display->drm->mode_config.fb_lock);
 
 	return 0;
 }
@@ -179,14 +179,14 @@ static void intel_encoder_info(struct seq_file *m,
 			       struct intel_crtc *crtc,
 			       struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_connector_list_iter conn_iter;
 	struct drm_connector *connector;
 
 	seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
 		   encoder->base.base.id, encoder->base.name);
 
-	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+	drm_connector_list_iter_begin(display->drm, &conn_iter);
 	drm_for_each_connector_iter(connector, &conn_iter) {
 		const struct drm_connector_state *conn_state =
 			connector->state;
@@ -391,10 +391,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
 
 static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct intel_plane *plane;
 
-	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
 		seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
 			   plane->base.base.id, plane->base.name,
 			   plane_type(plane->base.type));
@@ -537,7 +537,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
 
 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_printer p = drm_seq_file_printer(m);
 	const struct intel_crtc_state *crtc_state =
 		to_intel_crtc_state(crtc->base.state);
@@ -571,7 +571,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 
 	intel_vdsc_state_dump(&p, 1, crtc_state);
 
-	for_each_intel_encoder_mask(&dev_priv->drm, encoder,
+	for_each_intel_encoder_mask(display->drm, encoder,
 				    crtc_state->uapi.encoder_mask)
 		intel_encoder_info(m, crtc, encoder);
 
@@ -586,6 +586,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
 
 static int i915_display_info(struct seq_file *m, void *unused)
 {
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct intel_crtc *crtc;
 	struct drm_connector *connector;
@@ -594,22 +595,22 @@ static int i915_display_info(struct seq_file *m, void *unused)
 
 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
-	drm_modeset_lock_all(&dev_priv->drm);
+	drm_modeset_lock_all(display->drm);
 
 	seq_printf(m, "CRTC info\n");
 	seq_printf(m, "---------\n");
-	for_each_intel_crtc(&dev_priv->drm, crtc)
+	for_each_intel_crtc(display->drm, crtc)
 		intel_crtc_info(m, crtc);
 
 	seq_printf(m, "\n");
 	seq_printf(m, "Connector info\n");
 	seq_printf(m, "--------------\n");
-	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+	drm_connector_list_iter_begin(display->drm, &conn_iter);
 	drm_for_each_connector_iter(connector, &conn_iter)
 		intel_connector_info(m, connector);
 	drm_connector_list_iter_end(&conn_iter);
 
-	drm_modeset_unlock_all(&dev_priv->drm);
+	drm_modeset_unlock_all(display->drm);
 
 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 
@@ -618,11 +619,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
 
 static int i915_display_capabilities(struct seq_file *m, void *unused)
 {
-	struct drm_i915_private *i915 = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_printer p = drm_seq_file_printer(m);
 
-	intel_display_device_info_print(DISPLAY_INFO(i915),
-					DISPLAY_RUNTIME_INFO(i915), &p);
+	intel_display_device_info_print(DISPLAY_INFO(display),
+					DISPLAY_RUNTIME_INFO(display), &p);
 
 	return 0;
 }
@@ -630,15 +631,16 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_printer p = drm_seq_file_printer(m);
 	struct intel_shared_dpll *pll;
 	int i;
 
-	drm_modeset_lock_all(&dev_priv->drm);
+	drm_modeset_lock_all(display->drm);
 
 	drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
-		   dev_priv->display.dpll.ref_clks.nssc,
-		   dev_priv->display.dpll.ref_clks.ssc);
+		   display->dpll.ref_clks.nssc,
+		   display->dpll.ref_clks.ssc);
 
 	for_each_shared_dpll(dev_priv, pll, i) {
 		drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
@@ -649,25 +651,25 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 		drm_printf(&p, " tracked hardware state:\n");
 		intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
 	}
-	drm_modeset_unlock_all(&dev_priv->drm);
+	drm_modeset_unlock_all(display->drm);
 
 	return 0;
 }
 
 static int i915_ddb_info(struct seq_file *m, void *unused)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct skl_ddb_entry *entry;
 	struct intel_crtc *crtc;
 
-	if (DISPLAY_VER(dev_priv) < 9)
+	if (DISPLAY_VER(display) < 9)
 		return -ENODEV;
 
-	drm_modeset_lock_all(&dev_priv->drm);
+	drm_modeset_lock_all(display->drm);
 
 	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(display->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 		enum pipe pipe = crtc->pipe;
@@ -687,16 +689,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
 			   entry->end, skl_ddb_entry_size(entry));
 	}
 
-	drm_modeset_unlock_all(&dev_priv->drm);
+	drm_modeset_unlock_all(display->drm);
 
 	return 0;
 }
 
 static bool
-intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
+intel_lpsp_power_well_enabled(struct intel_display *display,
 			      enum i915_power_well_id power_well_id)
 {
-	struct intel_display *display = &i915->display;
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	intel_wakeref_t wakeref;
 	bool is_enabled;
 
@@ -710,15 +712,16 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
 
 static int i915_lpsp_status(struct seq_file *m, void *unused)
 {
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_i915_private *i915 = node_to_i915(m->private);
 	bool lpsp_enabled = false;
 
-	if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
-		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
-	} else if (IS_DISPLAY_VER(i915, 11, 12)) {
-		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
+	if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
+		lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
+	} else if (IS_DISPLAY_VER(display, 11, 12)) {
+		lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
 	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
-		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
+		lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
 	} else {
 		seq_puts(m, "LPSP: not supported\n");
 		return 0;
@@ -731,13 +734,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
 
 static int i915_dp_mst_info(struct seq_file *m, void *unused)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	struct intel_display *display = node_to_intel_display(m->private);
 	struct intel_encoder *intel_encoder;
 	struct intel_digital_port *dig_port;
 	struct drm_connector *connector;
 	struct drm_connector_list_iter conn_iter;
 
-	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
+	drm_connector_list_iter_begin(display->drm, &conn_iter);
 	drm_for_each_connector_iter(connector, &conn_iter) {
 		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 			continue;
@@ -765,7 +768,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
 			       const char __user *ubuf,
 			       size_t cnt, loff_t *ppos)
 {
-	struct drm_i915_private *dev_priv = filp->private_data;
+	struct intel_display *display = filp->private_data;
 	struct intel_crtc *crtc;
 	int ret;
 	bool reset;
@@ -777,7 +780,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
 	if (!reset)
 		return cnt;
 
-	for_each_intel_crtc(&dev_priv->drm, crtc) {
+	for_each_intel_crtc(display->drm, crtc) {
 		struct drm_crtc_commit *commit;
 		struct intel_crtc_state *crtc_state;
 
@@ -794,7 +797,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
 		}
 
 		if (!ret && crtc_state->hw.active) {
-			drm_dbg_kms(&dev_priv->drm,
+			drm_dbg_kms(display->drm,
 				    "Re-arming FIFO underruns on pipe %c\n",
 				    pipe_name(crtc->pipe));
 
@@ -807,7 +810,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
 			return ret;
 	}
 
-	intel_fbc_reset_underrun(&dev_priv->display);
+	intel_fbc_reset_underrun(display);
 
 	return cnt;
 }
@@ -839,7 +842,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
 	struct drm_minor *minor = i915->drm.primary;
 
 	debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
-			    to_i915(minor->dev), &i915_fifo_underrun_reset_ops);
+			    to_intel_display(minor->dev), &i915_fifo_underrun_reset_ops);
 
 	drm_debugfs_create_files(intel_display_debugfs_list,
 				 ARRAY_SIZE(intel_display_debugfs_list),
@@ -860,8 +863,9 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
 static int i915_lpsp_capability_show(struct seq_file *m, void *data)
 {
 	struct intel_connector *connector = m->private;
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_encoder *encoder = intel_attached_encoder(connector);
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	int connector_type = connector->base.connector_type;
 	bool lpsp_capable = false;
 
@@ -871,19 +875,19 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
 	if (connector->base.status != connector_status_connected)
 		return -ENODEV;
 
-	if (DISPLAY_VER(i915) >= 13)
+	if (DISPLAY_VER(display) >= 13)
 		lpsp_capable = encoder->port <= PORT_B;
-	else if (DISPLAY_VER(i915) >= 12)
+	else if (DISPLAY_VER(display) >= 12)
 		/*
 		 * Actually TGL can drive LPSP on port till DDI_C
 		 * but there is no physical connected DDI_C on TGL sku's,
 		 * even driver is not initializing DDI_C port for gen12.
 		 */
 		lpsp_capable = encoder->port <= PORT_B;
-	else if (DISPLAY_VER(i915) == 11)
+	else if (DISPLAY_VER(display) == 11)
 		lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
 				connector_type == DRM_MODE_CONNECTOR_eDP);
-	else if (IS_DISPLAY_VER(i915, 9, 10))
+	else if (IS_DISPLAY_VER(display, 9, 10))
 		lpsp_capable = (encoder->port == PORT_A &&
 				(connector_type == DRM_MODE_CONNECTOR_DSI ||
 				 connector_type == DRM_MODE_CONNECTOR_eDP ||
@@ -900,7 +904,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
 static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 {
 	struct intel_connector *connector = m->private;
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct drm_crtc *crtc;
 	struct intel_dp *intel_dp;
 	struct drm_modeset_acquire_ctx ctx;
@@ -912,7 +916,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
 
 	do {
 		try_again = false;
-		ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
+		ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
 				       &ctx);
 		if (ret) {
 			if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
@@ -973,7 +977,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
 {
 	struct seq_file *m = file->private_data;
 	struct intel_connector *connector = m->private;
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_encoder *encoder = intel_attached_encoder(connector);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	bool dsc_enable = false;
@@ -982,14 +986,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
 	if (len == 0)
 		return 0;
 
-	drm_dbg(&i915->drm,
+	drm_dbg(display->drm,
 		"Copied %zu bytes from user to force DSC\n", len);
 
 	ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
 	if (ret < 0)
 		return ret;
 
-	drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
+	drm_dbg(display->drm, "Got %s for DSC Enable\n",
 		(dsc_enable) ? "true" : "false");
 	intel_dp->force_dsc_en = dsc_enable;
 
@@ -1016,7 +1020,7 @@ static const struct file_operations i915_dsc_fec_support_fops = {
 static int i915_dsc_bpc_show(struct seq_file *m, void *data)
 {
 	struct intel_connector *connector = m->private;
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_encoder *encoder = intel_attached_encoder(connector);
 	struct drm_crtc *crtc;
 	struct intel_crtc_state *crtc_state;
@@ -1025,7 +1029,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
 	if (!encoder)
 		return -ENODEV;
 
-	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
 	if (ret)
 		return ret;
 
@@ -1038,7 +1042,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
 	crtc_state = to_intel_crtc_state(crtc->state);
 	seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
 
-out:	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+out:	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
 
 	return ret;
 }
@@ -1082,7 +1086,7 @@ static const struct file_operations i915_dsc_bpc_fops = {
 static int i915_dsc_output_format_show(struct seq_file *m, void *data)
 {
 	struct intel_connector *connector = m->private;
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_encoder *encoder = intel_attached_encoder(connector);
 	struct drm_crtc *crtc;
 	struct intel_crtc_state *crtc_state;
@@ -1091,7 +1095,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
 	if (!encoder)
 		return -ENODEV;
 
-	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
 	if (ret)
 		return ret;
 
@@ -1105,7 +1109,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
 	seq_printf(m, "DSC_Output_Format: %s\n",
 		   intel_output_format_name(crtc_state->output_format));
 
-out:	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+out:	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
 
 	return ret;
 }
@@ -1149,7 +1153,7 @@ static const struct file_operations i915_dsc_output_format_fops = {
 static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
 {
 	struct intel_connector *connector = m->private;
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_encoder *encoder = intel_attached_encoder(connector);
 	struct drm_crtc *crtc;
 	struct intel_dp *intel_dp;
@@ -1158,7 +1162,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
 	if (!encoder)
 		return -ENODEV;
 
-	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
+	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
 	if (ret)
 		return ret;
 
@@ -1173,7 +1177,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
 		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
 
 out:
-	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
+	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
 
 	return ret;
 }
@@ -1184,8 +1188,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
 {
 	struct seq_file *m = file->private_data;
 	struct intel_connector *connector = m->private;
+	struct intel_display *display = to_intel_display(connector);
 	struct intel_encoder *encoder = intel_attached_encoder(connector);
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	bool dsc_fractional_bpp_enable = false;
 	int ret;
@@ -1193,14 +1197,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
 	if (len == 0)
 		return 0;
 
-	drm_dbg(&i915->drm,
+	drm_dbg(display->drm,
 		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
 
 	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
 	if (ret < 0)
 		return ret;
 
-	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
+	drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
 		(dsc_fractional_bpp_enable) ? "true" : "false");
 	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
 
@@ -1329,7 +1333,7 @@ static const struct file_operations i915_joiner_fops = {
  */
 void intel_connector_debugfs_add(struct intel_connector *connector)
 {
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+	struct intel_display *display = to_intel_display(connector);
 	struct dentry *root = connector->base.debugfs_entry;
 	int connector_type = connector->base.connector_type;
 
@@ -1344,7 +1348,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
 	intel_alpm_lobf_debugfs_add(connector);
 	intel_dp_link_training_debugfs_add(connector);
 
-	if (DISPLAY_VER(i915) >= 11 &&
+	if (DISPLAY_VER(display) >= 11 &&
 	    ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
 	     connector_type == DRM_MODE_CONNECTOR_eDP)) {
 		debugfs_create_file("i915_dsc_fec_support", 0644, root,
-- 
2.34.1

Re: [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use struct intel_display wherever possible in intel_display_debug_fs.c
> to reduce the use of drm_i915_private.
>
> --v2
> -Rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 158 +++++++++---------
>  1 file changed, 81 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 89e5eea90be8..d85924caa26e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -68,17 +68,17 @@ static int intel_display_caps(struct seq_file *m, void *data)
>  
>  static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  
> -	spin_lock(&dev_priv->display.fb_tracking.lock);
> +	spin_lock(&display->fb_tracking.lock);
>  
>  	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
> -		   dev_priv->display.fb_tracking.busy_bits);
> +		   display->fb_tracking.busy_bits);
>  
>  	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
> -		   dev_priv->display.fb_tracking.flip_bits);
> +		   display->fb_tracking.flip_bits);
>  
> -	spin_unlock(&dev_priv->display.fb_tracking.lock);
> +	spin_unlock(&display->fb_tracking.lock);
>  
>  	return 0;
>  }
> @@ -86,25 +86,25 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
>  static int i915_sr_status(struct seq_file *m, void *unused)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	struct intel_display *display = &dev_priv->display;
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	intel_wakeref_t wakeref;
>  	bool sr_enabled = false;
>  
>  	wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
>  
> -	if (DISPLAY_VER(dev_priv) >= 9)
> +	if (DISPLAY_VER(display) >= 9)
>  		/* no global SR status; inspect per-plane WM */;
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
> +		sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
>  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
> +		sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
>  	else if (IS_I915GM(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
> +		sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> +		sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> +		sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
>  
> @@ -115,12 +115,12 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  
>  static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct intel_framebuffer *fbdev_fb = NULL;
>  	struct drm_framebuffer *drm_fb;
>  
>  #ifdef CONFIG_DRM_FBDEV_EMULATION
> -	fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
> +	fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
>  	if (fbdev_fb) {
>  		seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
>  			   fbdev_fb->base.width,
> @@ -134,8 +134,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
>  	}
>  #endif
>  
> -	mutex_lock(&dev_priv->drm.mode_config.fb_lock);
> -	drm_for_each_fb(drm_fb, &dev_priv->drm) {
> +	mutex_lock(&display->drm->mode_config.fb_lock);
> +	drm_for_each_fb(drm_fb, display->drm) {
>  		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
>  		if (fb == fbdev_fb)
>  			continue;
> @@ -150,7 +150,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
>  		intel_bo_describe(m, intel_fb_bo(&fb->base));
>  		seq_putc(m, '\n');
>  	}
> -	mutex_unlock(&dev_priv->drm.mode_config.fb_lock);
> +	mutex_unlock(&display->drm->mode_config.fb_lock);
>  
>  	return 0;
>  }
> @@ -179,14 +179,14 @@ static void intel_encoder_info(struct seq_file *m,
>  			       struct intel_crtc *crtc,
>  			       struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_connector_list_iter conn_iter;
>  	struct drm_connector *connector;
>  
>  	seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
>  		   encoder->base.base.id, encoder->base.name);
>  
> -	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(connector, &conn_iter) {
>  		const struct drm_connector_state *conn_state =
>  			connector->state;
> @@ -391,10 +391,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
>  
>  static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct intel_plane *plane;
>  
> -	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
>  		seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
>  			   plane->base.base.id, plane->base.name,
>  			   plane_type(plane->base.type));
> @@ -537,7 +537,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
>  
>  static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  	const struct intel_crtc_state *crtc_state =
>  		to_intel_crtc_state(crtc->base.state);
> @@ -571,7 +571,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  
>  	intel_vdsc_state_dump(&p, 1, crtc_state);
>  
> -	for_each_intel_encoder_mask(&dev_priv->drm, encoder,
> +	for_each_intel_encoder_mask(display->drm, encoder,
>  				    crtc_state->uapi.encoder_mask)
>  		intel_encoder_info(m, crtc, encoder);
>  
> @@ -586,6 +586,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  
>  static int i915_display_info(struct seq_file *m, void *unused)
>  {
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  	struct intel_crtc *crtc;
>  	struct drm_connector *connector;
> @@ -594,22 +595,22 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  
>  	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>  
> -	drm_modeset_lock_all(&dev_priv->drm);
> +	drm_modeset_lock_all(display->drm);
>  
>  	seq_printf(m, "CRTC info\n");
>  	seq_printf(m, "---------\n");
> -	for_each_intel_crtc(&dev_priv->drm, crtc)
> +	for_each_intel_crtc(display->drm, crtc)
>  		intel_crtc_info(m, crtc);
>  
>  	seq_printf(m, "\n");
>  	seq_printf(m, "Connector info\n");
>  	seq_printf(m, "--------------\n");
> -	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(connector, &conn_iter)
>  		intel_connector_info(m, connector);
>  	drm_connector_list_iter_end(&conn_iter);
>  
> -	drm_modeset_unlock_all(&dev_priv->drm);
> +	drm_modeset_unlock_all(display->drm);
>  
>  	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>  
> @@ -618,11 +619,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  
>  static int i915_display_capabilities(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *i915 = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  
> -	intel_display_device_info_print(DISPLAY_INFO(i915),
> -					DISPLAY_RUNTIME_INFO(i915), &p);
> +	intel_display_device_info_print(DISPLAY_INFO(display),
> +					DISPLAY_RUNTIME_INFO(display), &p);
>  
>  	return 0;
>  }
> @@ -630,15 +631,16 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
>  static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  	struct intel_shared_dpll *pll;
>  	int i;
>  
> -	drm_modeset_lock_all(&dev_priv->drm);
> +	drm_modeset_lock_all(display->drm);
>  
>  	drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
> -		   dev_priv->display.dpll.ref_clks.nssc,
> -		   dev_priv->display.dpll.ref_clks.ssc);
> +		   display->dpll.ref_clks.nssc,
> +		   display->dpll.ref_clks.ssc);
>  
>  	for_each_shared_dpll(dev_priv, pll, i) {
>  		drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
> @@ -649,25 +651,25 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  		drm_printf(&p, " tracked hardware state:\n");
>  		intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
>  	}
> -	drm_modeset_unlock_all(&dev_priv->drm);
> +	drm_modeset_unlock_all(display->drm);
>  
>  	return 0;
>  }
>  
>  static int i915_ddb_info(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct skl_ddb_entry *entry;
>  	struct intel_crtc *crtc;
>  
> -	if (DISPLAY_VER(dev_priv) < 9)
> +	if (DISPLAY_VER(display) < 9)
>  		return -ENODEV;
>  
> -	drm_modeset_lock_all(&dev_priv->drm);
> +	drm_modeset_lock_all(display->drm);
>  
>  	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
>  
> -	for_each_intel_crtc(&dev_priv->drm, crtc) {
> +	for_each_intel_crtc(display->drm, crtc) {
>  		struct intel_crtc_state *crtc_state =
>  			to_intel_crtc_state(crtc->base.state);
>  		enum pipe pipe = crtc->pipe;
> @@ -687,16 +689,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>  			   entry->end, skl_ddb_entry_size(entry));
>  	}
>  
> -	drm_modeset_unlock_all(&dev_priv->drm);
> +	drm_modeset_unlock_all(display->drm);
>  
>  	return 0;
>  }
>  
>  static bool
> -intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
> +intel_lpsp_power_well_enabled(struct intel_display *display,
>  			      enum i915_power_well_id power_well_id)
>  {
> -	struct intel_display *display = &i915->display;
> +	struct drm_i915_private *i915 = to_i915(display->drm);
>  	intel_wakeref_t wakeref;
>  	bool is_enabled;
>  
> @@ -710,15 +712,16 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
>  
>  static int i915_lpsp_status(struct seq_file *m, void *unused)
>  {
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_i915_private *i915 = node_to_i915(m->private);
>  	bool lpsp_enabled = false;
>  
> -	if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
> -		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
> -	} else if (IS_DISPLAY_VER(i915, 11, 12)) {
> -		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
> +	if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
> +		lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
> +	} else if (IS_DISPLAY_VER(display, 11, 12)) {
> +		lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
>  	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> -		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
> +		lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
>  	} else {
>  		seq_puts(m, "LPSP: not supported\n");
>  		return 0;
> @@ -731,13 +734,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
>  
>  static int i915_dp_mst_info(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct intel_encoder *intel_encoder;
>  	struct intel_digital_port *dig_port;
>  	struct drm_connector *connector;
>  	struct drm_connector_list_iter conn_iter;
>  
> -	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(connector, &conn_iter) {
>  		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
>  			continue;
> @@ -765,7 +768,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  			       const char __user *ubuf,
>  			       size_t cnt, loff_t *ppos)
>  {
> -	struct drm_i915_private *dev_priv = filp->private_data;
> +	struct intel_display *display = filp->private_data;
>  	struct intel_crtc *crtc;
>  	int ret;
>  	bool reset;
> @@ -777,7 +780,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  	if (!reset)
>  		return cnt;
>  
> -	for_each_intel_crtc(&dev_priv->drm, crtc) {
> +	for_each_intel_crtc(display->drm, crtc) {
>  		struct drm_crtc_commit *commit;
>  		struct intel_crtc_state *crtc_state;
>  
> @@ -794,7 +797,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  		}
>  
>  		if (!ret && crtc_state->hw.active) {
> -			drm_dbg_kms(&dev_priv->drm,
> +			drm_dbg_kms(display->drm,
>  				    "Re-arming FIFO underruns on pipe %c\n",
>  				    pipe_name(crtc->pipe));
>  
> @@ -807,7 +810,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  			return ret;
>  	}
>  
> -	intel_fbc_reset_underrun(&dev_priv->display);
> +	intel_fbc_reset_underrun(display);
>  
>  	return cnt;
>  }
> @@ -839,7 +842,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>  	struct drm_minor *minor = i915->drm.primary;
>  
>  	debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
> -			    to_i915(minor->dev), &i915_fifo_underrun_reset_ops);
> +			    to_intel_display(minor->dev), &i915_fifo_underrun_reset_ops);

Please don't inline to_intel_display(minor->dev), add a separate local
variable instead. Eventually we'll pass display to
intel_display_debugfs_register(), the local variable will get removed,
and this place doesn't need to be changed.

Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  
>  	drm_debugfs_create_files(intel_display_debugfs_list,
>  				 ARRAY_SIZE(intel_display_debugfs_list),
> @@ -860,8 +863,9 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>  static int i915_lpsp_capability_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
> +	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	int connector_type = connector->base.connector_type;
>  	bool lpsp_capable = false;
>  
> @@ -871,19 +875,19 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
>  	if (connector->base.status != connector_status_connected)
>  		return -ENODEV;
>  
> -	if (DISPLAY_VER(i915) >= 13)
> +	if (DISPLAY_VER(display) >= 13)
>  		lpsp_capable = encoder->port <= PORT_B;
> -	else if (DISPLAY_VER(i915) >= 12)
> +	else if (DISPLAY_VER(display) >= 12)
>  		/*
>  		 * Actually TGL can drive LPSP on port till DDI_C
>  		 * but there is no physical connected DDI_C on TGL sku's,
>  		 * even driver is not initializing DDI_C port for gen12.
>  		 */
>  		lpsp_capable = encoder->port <= PORT_B;
> -	else if (DISPLAY_VER(i915) == 11)
> +	else if (DISPLAY_VER(display) == 11)
>  		lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
>  				connector_type == DRM_MODE_CONNECTOR_eDP);
> -	else if (IS_DISPLAY_VER(i915, 9, 10))
> +	else if (IS_DISPLAY_VER(display, 9, 10))
>  		lpsp_capable = (encoder->port == PORT_A &&
>  				(connector_type == DRM_MODE_CONNECTOR_DSI ||
>  				 connector_type == DRM_MODE_CONNECTOR_eDP ||
> @@ -900,7 +904,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
>  static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_dp *intel_dp;
>  	struct drm_modeset_acquire_ctx ctx;
> @@ -912,7 +916,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  
>  	do {
>  		try_again = false;
> -		ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
> +		ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
>  				       &ctx);
>  		if (ret) {
>  			if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
> @@ -973,7 +977,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
>  {
>  	struct seq_file *m = file->private_data;
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	bool dsc_enable = false;
> @@ -982,14 +986,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
>  	if (len == 0)
>  		return 0;
>  
> -	drm_dbg(&i915->drm,
> +	drm_dbg(display->drm,
>  		"Copied %zu bytes from user to force DSC\n", len);
>  
>  	ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
>  	if (ret < 0)
>  		return ret;
>  
> -	drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
> +	drm_dbg(display->drm, "Got %s for DSC Enable\n",
>  		(dsc_enable) ? "true" : "false");
>  	intel_dp->force_dsc_en = dsc_enable;
>  
> @@ -1016,7 +1020,7 @@ static const struct file_operations i915_dsc_fec_support_fops = {
>  static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_crtc_state *crtc_state;
> @@ -1025,7 +1029,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  	if (!encoder)
>  		return -ENODEV;
>  
> -	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> +	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
>  	if (ret)
>  		return ret;
>  
> @@ -1038,7 +1042,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  	crtc_state = to_intel_crtc_state(crtc->state);
>  	seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
>  
> -out:	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out:	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>  
>  	return ret;
>  }
> @@ -1082,7 +1086,7 @@ static const struct file_operations i915_dsc_bpc_fops = {
>  static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_crtc_state *crtc_state;
> @@ -1091,7 +1095,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>  	if (!encoder)
>  		return -ENODEV;
>  
> -	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> +	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
>  	if (ret)
>  		return ret;
>  
> @@ -1105,7 +1109,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>  	seq_printf(m, "DSC_Output_Format: %s\n",
>  		   intel_output_format_name(crtc_state->output_format));
>  
> -out:	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out:	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>  
>  	return ret;
>  }
> @@ -1149,7 +1153,7 @@ static const struct file_operations i915_dsc_output_format_fops = {
>  static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_dp *intel_dp;
> @@ -1158,7 +1162,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>  	if (!encoder)
>  		return -ENODEV;
>  
> -	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> +	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
>  	if (ret)
>  		return ret;
>  
> @@ -1173,7 +1177,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>  		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>  
>  out:
> -	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>  
>  	return ret;
>  }
> @@ -1184,8 +1188,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>  {
>  	struct seq_file *m = file->private_data;
>  	struct intel_connector *connector = m->private;
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	bool dsc_fractional_bpp_enable = false;
>  	int ret;
> @@ -1193,14 +1197,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>  	if (len == 0)
>  		return 0;
>  
> -	drm_dbg(&i915->drm,
> +	drm_dbg(display->drm,
>  		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>  
>  	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>  	if (ret < 0)
>  		return ret;
>  
> -	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> +	drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
>  		(dsc_fractional_bpp_enable) ? "true" : "false");
>  	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>  
> @@ -1329,7 +1333,7 @@ static const struct file_operations i915_joiner_fops = {
>   */
>  void intel_connector_debugfs_add(struct intel_connector *connector)
>  {
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct dentry *root = connector->base.debugfs_entry;
>  	int connector_type = connector->base.connector_type;
>  
> @@ -1344,7 +1348,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
>  	intel_alpm_lobf_debugfs_add(connector);
>  	intel_dp_link_training_debugfs_add(connector);
>  
> -	if (DISPLAY_VER(i915) >= 11 &&
> +	if (DISPLAY_VER(display) >= 11 &&
>  	    ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
>  	     connector_type == DRM_MODE_CONNECTOR_eDP)) {
>  		debugfs_create_file("i915_dsc_fec_support", 0644, root,

-- 
Jani Nikula, Intel

Re: [PATCH 1/9] drm/i915/display_debug_fs: Use intel_display wherever possible

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use struct intel_display wherever possible in intel_display_debug_fs.c
> to reduce the use of drm_i915_private.

PS. "drm/i915/display_debug_fs:" is not a prefix we've ever used.

>
> --v2
> -Rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  | 158 +++++++++---------
>  1 file changed, 81 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 89e5eea90be8..d85924caa26e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -68,17 +68,17 @@ static int intel_display_caps(struct seq_file *m, void *data)
>  
>  static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  
> -	spin_lock(&dev_priv->display.fb_tracking.lock);
> +	spin_lock(&display->fb_tracking.lock);
>  
>  	seq_printf(m, "FB tracking busy bits: 0x%08x\n",
> -		   dev_priv->display.fb_tracking.busy_bits);
> +		   display->fb_tracking.busy_bits);
>  
>  	seq_printf(m, "FB tracking flip bits: 0x%08x\n",
> -		   dev_priv->display.fb_tracking.flip_bits);
> +		   display->fb_tracking.flip_bits);
>  
> -	spin_unlock(&dev_priv->display.fb_tracking.lock);
> +	spin_unlock(&display->fb_tracking.lock);
>  
>  	return 0;
>  }
> @@ -86,25 +86,25 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
>  static int i915_sr_status(struct seq_file *m, void *unused)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	struct intel_display *display = &dev_priv->display;
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	intel_wakeref_t wakeref;
>  	bool sr_enabled = false;
>  
>  	wakeref = intel_display_power_get(display, POWER_DOMAIN_INIT);
>  
> -	if (DISPLAY_VER(dev_priv) >= 9)
> +	if (DISPLAY_VER(display) >= 9)
>  		/* no global SR status; inspect per-plane WM */;
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
> +		sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
>  	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
>  		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
> +		sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
>  	else if (IS_I915GM(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN;
> +		sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
>  	else if (IS_PINEVIEW(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> +		sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
> +		sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
>  
> @@ -115,12 +115,12 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  
>  static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct intel_framebuffer *fbdev_fb = NULL;
>  	struct drm_framebuffer *drm_fb;
>  
>  #ifdef CONFIG_DRM_FBDEV_EMULATION
> -	fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
> +	fbdev_fb = intel_fbdev_framebuffer(display->fbdev.fbdev);
>  	if (fbdev_fb) {
>  		seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
>  			   fbdev_fb->base.width,
> @@ -134,8 +134,8 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
>  	}
>  #endif
>  
> -	mutex_lock(&dev_priv->drm.mode_config.fb_lock);
> -	drm_for_each_fb(drm_fb, &dev_priv->drm) {
> +	mutex_lock(&display->drm->mode_config.fb_lock);
> +	drm_for_each_fb(drm_fb, display->drm) {
>  		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
>  		if (fb == fbdev_fb)
>  			continue;
> @@ -150,7 +150,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
>  		intel_bo_describe(m, intel_fb_bo(&fb->base));
>  		seq_putc(m, '\n');
>  	}
> -	mutex_unlock(&dev_priv->drm.mode_config.fb_lock);
> +	mutex_unlock(&display->drm->mode_config.fb_lock);
>  
>  	return 0;
>  }
> @@ -179,14 +179,14 @@ static void intel_encoder_info(struct seq_file *m,
>  			       struct intel_crtc *crtc,
>  			       struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_connector_list_iter conn_iter;
>  	struct drm_connector *connector;
>  
>  	seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n",
>  		   encoder->base.base.id, encoder->base.name);
>  
> -	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(connector, &conn_iter) {
>  		const struct drm_connector_state *conn_state =
>  			connector->state;
> @@ -391,10 +391,10 @@ static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane)
>  
>  static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct intel_plane *plane;
>  
> -	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +	for_each_intel_plane_on_crtc(display->drm, crtc, plane) {
>  		seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n",
>  			   plane->base.base.id, plane->base.name,
>  			   plane_type(plane->base.type));
> @@ -537,7 +537,7 @@ static void crtc_updates_add(struct intel_crtc *crtc)
>  
>  static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  	const struct intel_crtc_state *crtc_state =
>  		to_intel_crtc_state(crtc->base.state);
> @@ -571,7 +571,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  
>  	intel_vdsc_state_dump(&p, 1, crtc_state);
>  
> -	for_each_intel_encoder_mask(&dev_priv->drm, encoder,
> +	for_each_intel_encoder_mask(display->drm, encoder,
>  				    crtc_state->uapi.encoder_mask)
>  		intel_encoder_info(m, crtc, encoder);
>  
> @@ -586,6 +586,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc)
>  
>  static int i915_display_info(struct seq_file *m, void *unused)
>  {
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  	struct intel_crtc *crtc;
>  	struct drm_connector *connector;
> @@ -594,22 +595,22 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  
>  	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>  
> -	drm_modeset_lock_all(&dev_priv->drm);
> +	drm_modeset_lock_all(display->drm);
>  
>  	seq_printf(m, "CRTC info\n");
>  	seq_printf(m, "---------\n");
> -	for_each_intel_crtc(&dev_priv->drm, crtc)
> +	for_each_intel_crtc(display->drm, crtc)
>  		intel_crtc_info(m, crtc);
>  
>  	seq_printf(m, "\n");
>  	seq_printf(m, "Connector info\n");
>  	seq_printf(m, "--------------\n");
> -	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(connector, &conn_iter)
>  		intel_connector_info(m, connector);
>  	drm_connector_list_iter_end(&conn_iter);
>  
> -	drm_modeset_unlock_all(&dev_priv->drm);
> +	drm_modeset_unlock_all(display->drm);
>  
>  	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
>  
> @@ -618,11 +619,11 @@ static int i915_display_info(struct seq_file *m, void *unused)
>  
>  static int i915_display_capabilities(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *i915 = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  
> -	intel_display_device_info_print(DISPLAY_INFO(i915),
> -					DISPLAY_RUNTIME_INFO(i915), &p);
> +	intel_display_device_info_print(DISPLAY_INFO(display),
> +					DISPLAY_RUNTIME_INFO(display), &p);
>  
>  	return 0;
>  }
> @@ -630,15 +631,16 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
>  static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  	struct intel_shared_dpll *pll;
>  	int i;
>  
> -	drm_modeset_lock_all(&dev_priv->drm);
> +	drm_modeset_lock_all(display->drm);
>  
>  	drm_printf(&p, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
> -		   dev_priv->display.dpll.ref_clks.nssc,
> -		   dev_priv->display.dpll.ref_clks.ssc);
> +		   display->dpll.ref_clks.nssc,
> +		   display->dpll.ref_clks.ssc);
>  
>  	for_each_shared_dpll(dev_priv, pll, i) {
>  		drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
> @@ -649,25 +651,25 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  		drm_printf(&p, " tracked hardware state:\n");
>  		intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
>  	}
> -	drm_modeset_unlock_all(&dev_priv->drm);
> +	drm_modeset_unlock_all(display->drm);
>  
>  	return 0;
>  }
>  
>  static int i915_ddb_info(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct skl_ddb_entry *entry;
>  	struct intel_crtc *crtc;
>  
> -	if (DISPLAY_VER(dev_priv) < 9)
> +	if (DISPLAY_VER(display) < 9)
>  		return -ENODEV;
>  
> -	drm_modeset_lock_all(&dev_priv->drm);
> +	drm_modeset_lock_all(display->drm);
>  
>  	seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
>  
> -	for_each_intel_crtc(&dev_priv->drm, crtc) {
> +	for_each_intel_crtc(display->drm, crtc) {
>  		struct intel_crtc_state *crtc_state =
>  			to_intel_crtc_state(crtc->base.state);
>  		enum pipe pipe = crtc->pipe;
> @@ -687,16 +689,16 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
>  			   entry->end, skl_ddb_entry_size(entry));
>  	}
>  
> -	drm_modeset_unlock_all(&dev_priv->drm);
> +	drm_modeset_unlock_all(display->drm);
>  
>  	return 0;
>  }
>  
>  static bool
> -intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
> +intel_lpsp_power_well_enabled(struct intel_display *display,
>  			      enum i915_power_well_id power_well_id)
>  {
> -	struct intel_display *display = &i915->display;
> +	struct drm_i915_private *i915 = to_i915(display->drm);
>  	intel_wakeref_t wakeref;
>  	bool is_enabled;
>  
> @@ -710,15 +712,16 @@ intel_lpsp_power_well_enabled(struct drm_i915_private *i915,
>  
>  static int i915_lpsp_status(struct seq_file *m, void *unused)
>  {
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_i915_private *i915 = node_to_i915(m->private);
>  	bool lpsp_enabled = false;
>  
> -	if (DISPLAY_VER(i915) >= 13 || IS_DISPLAY_VER(i915, 9, 10)) {
> -		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, SKL_DISP_PW_2);
> -	} else if (IS_DISPLAY_VER(i915, 11, 12)) {
> -		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, ICL_DISP_PW_3);
> +	if (DISPLAY_VER(display) >= 13 || IS_DISPLAY_VER(display, 9, 10)) {
> +		lpsp_enabled = !intel_lpsp_power_well_enabled(display, SKL_DISP_PW_2);
> +	} else if (IS_DISPLAY_VER(display, 11, 12)) {
> +		lpsp_enabled = !intel_lpsp_power_well_enabled(display, ICL_DISP_PW_3);
>  	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> -		lpsp_enabled = !intel_lpsp_power_well_enabled(i915, HSW_DISP_PW_GLOBAL);
> +		lpsp_enabled = !intel_lpsp_power_well_enabled(display, HSW_DISP_PW_GLOBAL);
>  	} else {
>  		seq_puts(m, "LPSP: not supported\n");
>  		return 0;
> @@ -731,13 +734,13 @@ static int i915_lpsp_status(struct seq_file *m, void *unused)
>  
>  static int i915_dp_mst_info(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> +	struct intel_display *display = node_to_intel_display(m->private);
>  	struct intel_encoder *intel_encoder;
>  	struct intel_digital_port *dig_port;
>  	struct drm_connector *connector;
>  	struct drm_connector_list_iter conn_iter;
>  
> -	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
> +	drm_connector_list_iter_begin(display->drm, &conn_iter);
>  	drm_for_each_connector_iter(connector, &conn_iter) {
>  		if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
>  			continue;
> @@ -765,7 +768,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  			       const char __user *ubuf,
>  			       size_t cnt, loff_t *ppos)
>  {
> -	struct drm_i915_private *dev_priv = filp->private_data;
> +	struct intel_display *display = filp->private_data;
>  	struct intel_crtc *crtc;
>  	int ret;
>  	bool reset;
> @@ -777,7 +780,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  	if (!reset)
>  		return cnt;
>  
> -	for_each_intel_crtc(&dev_priv->drm, crtc) {
> +	for_each_intel_crtc(display->drm, crtc) {
>  		struct drm_crtc_commit *commit;
>  		struct intel_crtc_state *crtc_state;
>  
> @@ -794,7 +797,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  		}
>  
>  		if (!ret && crtc_state->hw.active) {
> -			drm_dbg_kms(&dev_priv->drm,
> +			drm_dbg_kms(display->drm,
>  				    "Re-arming FIFO underruns on pipe %c\n",
>  				    pipe_name(crtc->pipe));
>  
> @@ -807,7 +810,7 @@ i915_fifo_underrun_reset_write(struct file *filp,
>  			return ret;
>  	}
>  
> -	intel_fbc_reset_underrun(&dev_priv->display);
> +	intel_fbc_reset_underrun(display);
>  
>  	return cnt;
>  }
> @@ -839,7 +842,7 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>  	struct drm_minor *minor = i915->drm.primary;
>  
>  	debugfs_create_file("i915_fifo_underrun_reset", 0644, minor->debugfs_root,
> -			    to_i915(minor->dev), &i915_fifo_underrun_reset_ops);
> +			    to_intel_display(minor->dev), &i915_fifo_underrun_reset_ops);
>  
>  	drm_debugfs_create_files(intel_display_debugfs_list,
>  				 ARRAY_SIZE(intel_display_debugfs_list),
> @@ -860,8 +863,9 @@ void intel_display_debugfs_register(struct drm_i915_private *i915)
>  static int i915_lpsp_capability_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
> +	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	int connector_type = connector->base.connector_type;
>  	bool lpsp_capable = false;
>  
> @@ -871,19 +875,19 @@ static int i915_lpsp_capability_show(struct seq_file *m, void *data)
>  	if (connector->base.status != connector_status_connected)
>  		return -ENODEV;
>  
> -	if (DISPLAY_VER(i915) >= 13)
> +	if (DISPLAY_VER(display) >= 13)
>  		lpsp_capable = encoder->port <= PORT_B;
> -	else if (DISPLAY_VER(i915) >= 12)
> +	else if (DISPLAY_VER(display) >= 12)
>  		/*
>  		 * Actually TGL can drive LPSP on port till DDI_C
>  		 * but there is no physical connected DDI_C on TGL sku's,
>  		 * even driver is not initializing DDI_C port for gen12.
>  		 */
>  		lpsp_capable = encoder->port <= PORT_B;
> -	else if (DISPLAY_VER(i915) == 11)
> +	else if (DISPLAY_VER(display) == 11)
>  		lpsp_capable = (connector_type == DRM_MODE_CONNECTOR_DSI ||
>  				connector_type == DRM_MODE_CONNECTOR_eDP);
> -	else if (IS_DISPLAY_VER(i915, 9, 10))
> +	else if (IS_DISPLAY_VER(display, 9, 10))
>  		lpsp_capable = (encoder->port == PORT_A &&
>  				(connector_type == DRM_MODE_CONNECTOR_DSI ||
>  				 connector_type == DRM_MODE_CONNECTOR_eDP ||
> @@ -900,7 +904,7 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability);
>  static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_dp *intel_dp;
>  	struct drm_modeset_acquire_ctx ctx;
> @@ -912,7 +916,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data)
>  
>  	do {
>  		try_again = false;
> -		ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex,
> +		ret = drm_modeset_lock(&display->drm->mode_config.connection_mutex,
>  				       &ctx);
>  		if (ret) {
>  			if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) {
> @@ -973,7 +977,7 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
>  {
>  	struct seq_file *m = file->private_data;
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	bool dsc_enable = false;
> @@ -982,14 +986,14 @@ static ssize_t i915_dsc_fec_support_write(struct file *file,
>  	if (len == 0)
>  		return 0;
>  
> -	drm_dbg(&i915->drm,
> +	drm_dbg(display->drm,
>  		"Copied %zu bytes from user to force DSC\n", len);
>  
>  	ret = kstrtobool_from_user(ubuf, len, &dsc_enable);
>  	if (ret < 0)
>  		return ret;
>  
> -	drm_dbg(&i915->drm, "Got %s for DSC Enable\n",
> +	drm_dbg(display->drm, "Got %s for DSC Enable\n",
>  		(dsc_enable) ? "true" : "false");
>  	intel_dp->force_dsc_en = dsc_enable;
>  
> @@ -1016,7 +1020,7 @@ static const struct file_operations i915_dsc_fec_support_fops = {
>  static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_crtc_state *crtc_state;
> @@ -1025,7 +1029,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  	if (!encoder)
>  		return -ENODEV;
>  
> -	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> +	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
>  	if (ret)
>  		return ret;
>  
> @@ -1038,7 +1042,7 @@ static int i915_dsc_bpc_show(struct seq_file *m, void *data)
>  	crtc_state = to_intel_crtc_state(crtc->state);
>  	seq_printf(m, "Input_BPC: %d\n", crtc_state->dsc.config.bits_per_component);
>  
> -out:	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out:	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>  
>  	return ret;
>  }
> @@ -1082,7 +1086,7 @@ static const struct file_operations i915_dsc_bpc_fops = {
>  static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_crtc_state *crtc_state;
> @@ -1091,7 +1095,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>  	if (!encoder)
>  		return -ENODEV;
>  
> -	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> +	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
>  	if (ret)
>  		return ret;
>  
> @@ -1105,7 +1109,7 @@ static int i915_dsc_output_format_show(struct seq_file *m, void *data)
>  	seq_printf(m, "DSC_Output_Format: %s\n",
>  		   intel_output_format_name(crtc_state->output_format));
>  
> -out:	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +out:	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>  
>  	return ret;
>  }
> @@ -1149,7 +1153,7 @@ static const struct file_operations i915_dsc_output_format_fops = {
>  static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>  {
>  	struct intel_connector *connector = m->private;
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
>  	struct drm_crtc *crtc;
>  	struct intel_dp *intel_dp;
> @@ -1158,7 +1162,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>  	if (!encoder)
>  		return -ENODEV;
>  
> -	ret = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex);
> +	ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
>  	if (ret)
>  		return ret;
>  
> @@ -1173,7 +1177,7 @@ static int i915_dsc_fractional_bpp_show(struct seq_file *m, void *data)
>  		   str_yes_no(intel_dp->force_dsc_fractional_bpp_en));
>  
>  out:
> -	drm_modeset_unlock(&i915->drm.mode_config.connection_mutex);
> +	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
>  
>  	return ret;
>  }
> @@ -1184,8 +1188,8 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>  {
>  	struct seq_file *m = file->private_data;
>  	struct intel_connector *connector = m->private;
> +	struct intel_display *display = to_intel_display(connector);
>  	struct intel_encoder *encoder = intel_attached_encoder(connector);
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	bool dsc_fractional_bpp_enable = false;
>  	int ret;
> @@ -1193,14 +1197,14 @@ static ssize_t i915_dsc_fractional_bpp_write(struct file *file,
>  	if (len == 0)
>  		return 0;
>  
> -	drm_dbg(&i915->drm,
> +	drm_dbg(display->drm,
>  		"Copied %zu bytes from user to force fractional bpp for DSC\n", len);
>  
>  	ret = kstrtobool_from_user(ubuf, len, &dsc_fractional_bpp_enable);
>  	if (ret < 0)
>  		return ret;
>  
> -	drm_dbg(&i915->drm, "Got %s for DSC Fractional BPP Enable\n",
> +	drm_dbg(display->drm, "Got %s for DSC Fractional BPP Enable\n",
>  		(dsc_fractional_bpp_enable) ? "true" : "false");
>  	intel_dp->force_dsc_fractional_bpp_en = dsc_fractional_bpp_enable;
>  
> @@ -1329,7 +1333,7 @@ static const struct file_operations i915_joiner_fops = {
>   */
>  void intel_connector_debugfs_add(struct intel_connector *connector)
>  {
> -	struct drm_i915_private *i915 = to_i915(connector->base.dev);
> +	struct intel_display *display = to_intel_display(connector);
>  	struct dentry *root = connector->base.debugfs_entry;
>  	int connector_type = connector->base.connector_type;
>  
> @@ -1344,7 +1348,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
>  	intel_alpm_lobf_debugfs_add(connector);
>  	intel_dp_link_training_debugfs_add(connector);
>  
> -	if (DISPLAY_VER(i915) >= 11 &&
> +	if (DISPLAY_VER(display) >= 11 &&
>  	    ((connector_type == DRM_MODE_CONNECTOR_DisplayPort && !connector->mst_port) ||
>  	     connector_type == DRM_MODE_CONNECTOR_eDP)) {
>  		debugfs_create_file("i915_dsc_fec_support", 0644, root,

-- 
Jani Nikula, Intel

[PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform

[Suraj Kandpal]

Prefer using display->platform.xx instead of IS_PLATFORM() checks

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index d85924caa26e..991c1726f522 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -96,14 +96,14 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 		/* no global SR status; inspect per-plane WM */;
 	else if (HAS_PCH_SPLIT(dev_priv))
 		sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
-	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
-		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
+	else if (display->platform.i965gm || display->platform.g4x ||
+		 display->platform.i945g || display->platform.i945gm)
 		sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
-	else if (IS_I915GM(dev_priv))
+	else if (display->platform.i915gm)
 		sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
-	else if (IS_PINEVIEW(dev_priv))
+	else if (display->platform.pineview)
 		sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
-	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+	else if (display->platform.valleyview || display->platform.cherryview)
 		sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
 	intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);
-- 
2.34.1

Re: [PATCH 2/9] drm/i915/display_debug_fs: Prefer using display->platform

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Prefer using display->platform.xx instead of IS_PLATFORM() checks

Could've been squashed to the previous patch?

Ditto about the subject prefix as previous patch.

Regardless,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index d85924caa26e..991c1726f522 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -96,14 +96,14 @@ static int i915_sr_status(struct seq_file *m, void *unused)
>  		/* no global SR status; inspect per-plane WM */;
>  	else if (HAS_PCH_SPLIT(dev_priv))
>  		sr_enabled = intel_de_read(display, WM1_LP_ILK) & WM_LP_ENABLE;
> -	else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
> -		 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
> +	else if (display->platform.i965gm || display->platform.g4x ||
> +		 display->platform.i945g || display->platform.i945gm)
>  		sr_enabled = intel_de_read(display, FW_BLC_SELF) & FW_BLC_SELF_EN;
> -	else if (IS_I915GM(dev_priv))
> +	else if (display->platform.i915gm)
>  		sr_enabled = intel_de_read(display, INSTPM) & INSTPM_SELF_EN;
> -	else if (IS_PINEVIEW(dev_priv))
> +	else if (display->platform.pineview)
>  		sr_enabled = intel_de_read(display, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN;
> -	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> +	else if (display->platform.valleyview || display->platform.cherryview)
>  		sr_enabled = intel_de_read(display, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
>  
>  	intel_display_power_put(display, POWER_DOMAIN_INIT, wakeref);

-- 
Jani Nikula, Intel

[PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll

[Suraj Kandpal]

Change the argument of for_each_shared_dpll to take intel_display which
helps move as an ongoing effort to get rid off the dependency on
drm_i915_private. Some opportunistic changes in intel_pch_refclk done
too.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 ++++++++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  6 ++--
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 36 +++++++++----------
 4 files changed, 37 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 991c1726f522..87e6f4000101 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -642,7 +642,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 		   display->dpll.ref_clks.nssc,
 		   display->dpll.ref_clks.ssc);
 
-	for_each_shared_dpll(dev_priv, pll, i) {
+	for_each_shared_dpll(display, pll, i) {
 		drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
 			   pll->info->name, pll->info->id);
 		drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index cb2ef317d219..171d16e91c61 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -121,10 +121,11 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
 				  struct intel_shared_dpll_state *shared_dpll)
 {
 	struct intel_shared_dpll *pll;
+	struct intel_display *display = to_intel_display(&i915->drm);
 	int i;
 
 	/* Copy shared dpll state */
-	for_each_shared_dpll(i915, pll, i)
+	for_each_shared_dpll(display, pll, i)
 		shared_dpll[pll->index] = pll->state;
 }
 
@@ -157,10 +158,11 @@ struct intel_shared_dpll *
 intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
 			    enum intel_dpll_id id)
 {
+	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
-	for_each_shared_dpll(i915, pll, i) {
+	for_each_shared_dpll(display, pll, i) {
 		if (pll->info->id == id)
 			return pll;
 	}
@@ -344,12 +346,13 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 static unsigned long
 intel_dpll_mask_all(struct drm_i915_private *i915)
 {
+	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	unsigned long dpll_mask = 0;
 	int i;
 
-	for_each_shared_dpll(i915, pll, i) {
-		drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
+	for_each_shared_dpll(display, pll, i) {
+		drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
 
 		dpll_mask |= BIT(pll->info->id);
 	}
@@ -513,7 +516,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
  */
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
 	struct intel_shared_dpll *pll;
 	int i;
@@ -521,7 +524,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
 	if (!state->dpll_set)
 		return;
 
-	for_each_shared_dpll(i915, pll, i)
+	for_each_shared_dpll(display, pll, i)
 		swap(pll->state, shared_dpll[pll->index]);
 }
 
@@ -4551,10 +4554,11 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
 
 void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
 {
+	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
-	for_each_shared_dpll(i915, pll, i)
+	for_each_shared_dpll(display, pll, i)
 		readout_dpll_hw_state(i915, pll);
 }
 
@@ -4578,10 +4582,11 @@ static void sanitize_dpll_state(struct drm_i915_private *i915,
 
 void intel_dpll_sanitize_state(struct drm_i915_private *i915)
 {
+	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
-	for_each_shared_dpll(i915, pll, i)
+	for_each_shared_dpll(display, pll, i)
 		sanitize_dpll_state(i915, pll);
 }
 
@@ -4728,10 +4733,11 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
 
 void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_shared_dpll *pll;
 	int i;
 
-	for_each_shared_dpll(i915, pll, i)
+	for_each_shared_dpll(display, pll, i)
 		verify_single_dpll_state(i915, pll, NULL, NULL);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3eee76874304..382bdf8f0b65 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -30,9 +30,9 @@
 #include "intel_display_power.h"
 #include "intel_wakeref.h"
 
-#define for_each_shared_dpll(__i915, __pll, __i) \
-	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
-		     ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
+#define for_each_shared_dpll(__display, __pll, __i) \
+	for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
+		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
 
 enum tc_port;
 struct drm_i915_private;
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 71471c1d7dc9..68e953d2b124 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -492,7 +492,7 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
 
 static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 {
-	struct intel_display *display = &dev_priv->display;
+	struct intel_display *display = to_intel_display(&dev_priv->drm);
 	struct intel_encoder *encoder;
 	struct intel_shared_dpll *pll;
 	int i;
@@ -505,7 +505,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 	bool using_ssc_source = false;
 
 	/* We need to take the global config into account */
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
+	for_each_intel_encoder(display->drm, encoder) {
 		switch (encoder->type) {
 		case INTEL_OUTPUT_LVDS:
 			has_panel = true;
@@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 	}
 
 	if (HAS_PCH_IBX(dev_priv)) {
-		has_ck505 = dev_priv->display.vbt.display_clock_mode;
+		has_ck505 = display->vbt.display_clock_mode;
 		can_ssc = has_ck505;
 	} else {
 		has_ck505 = false;
@@ -530,10 +530,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 	}
 
 	/* Check if any DPLLs are using the SSC source */
-	for_each_shared_dpll(dev_priv, pll, i) {
+	for_each_shared_dpll(display, pll, i) {
 		u32 temp;
 
-		temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
+		temp = intel_de_read(display, PCH_DPLL(pll->info->id));
 
 		if (!(temp & DPLL_VCO_ENABLE))
 			continue;
@@ -545,7 +545,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 		}
 	}
 
-	drm_dbg_kms(&dev_priv->drm,
+	drm_dbg_kms(display->drm,
 		    "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
 		    has_panel, has_lvds, has_ck505, using_ssc_source);
 
@@ -554,7 +554,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 	 * PCH B stepping, previous chipset stepping should be
 	 * ignoring this setting.
 	 */
-	val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
+	val = intel_de_read(display, PCH_DREF_CONTROL);
 
 	/* As we must carefully and slowly disable/enable each source in turn,
 	 * compute the final state we want first and check if we need to
@@ -614,8 +614,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 		}
 
 		/* Get SSC going before enabling the outputs */
-		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
-		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+		intel_de_write(display, PCH_DREF_CONTROL, val);
+		intel_de_posting_read(display, PCH_DREF_CONTROL);
 		udelay(200);
 
 		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
@@ -633,23 +633,23 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
 		}
 
-		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
-		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+		intel_de_write(display, PCH_DREF_CONTROL, val);
+		intel_de_posting_read(display, PCH_DREF_CONTROL);
 		udelay(200);
 	} else {
-		drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
+		drm_dbg_kms(display->drm, "Disabling CPU source output\n");
 
 		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 
 		/* Turn off CPU output */
 		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
 
-		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
-		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+		intel_de_write(display, PCH_DREF_CONTROL, val);
+		intel_de_posting_read(display, PCH_DREF_CONTROL);
 		udelay(200);
 
 		if (!using_ssc_source) {
-			drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
+			drm_dbg_kms(display->drm, "Disabling SSC source\n");
 
 			/* Turn off the SSC source */
 			val &= ~DREF_SSC_SOURCE_MASK;
@@ -658,13 +658,13 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
 			/* Turn off SSC1 */
 			val &= ~DREF_SSC1_ENABLE;
 
-			intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
-			intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
+			intel_de_write(display, PCH_DREF_CONTROL, val);
+			intel_de_posting_read(display, PCH_DREF_CONTROL);
 			udelay(200);
 		}
 	}
 
-	drm_WARN_ON(&dev_priv->drm, val != final);
+	drm_WARN_ON(display->drm, val != final);
 }
 
 /*
-- 
2.34.1

Re: [PATCH 3/9] drm/i915/dpll: Change param to intel_display in for_each_shared_dpll

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Change the argument of for_each_shared_dpll to take intel_display which
> helps move as an ongoing effort to get rid off the dependency on
> drm_i915_private. Some opportunistic changes in intel_pch_refclk done
> too.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../drm/i915/display/intel_display_debugfs.c  |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 ++++++++-----
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  6 ++--
>  .../gpu/drm/i915/display/intel_pch_refclk.c   | 36 +++++++++----------
>  4 files changed, 37 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 991c1726f522..87e6f4000101 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -642,7 +642,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  		   display->dpll.ref_clks.nssc,
>  		   display->dpll.ref_clks.ssc);
>  
> -	for_each_shared_dpll(dev_priv, pll, i) {
> +	for_each_shared_dpll(display, pll, i) {
>  		drm_printf(&p, "DPLL%i: %s, id: %i\n", pll->index,
>  			   pll->info->name, pll->info->id);
>  		drm_printf(&p, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index cb2ef317d219..171d16e91c61 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -121,10 +121,11 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
>  				  struct intel_shared_dpll_state *shared_dpll)
>  {
>  	struct intel_shared_dpll *pll;
> +	struct intel_display *display = to_intel_display(&i915->drm);

Nitpick, these could just be:

	struct intel_display *display = &i915->display;

And they'll go away once the function parameter gets changed to display.

Anyway,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

either way

>  	int i;
>  
>  	/* Copy shared dpll state */
> -	for_each_shared_dpll(i915, pll, i)
> +	for_each_shared_dpll(display, pll, i)
>  		shared_dpll[pll->index] = pll->state;
>  }
>  
> @@ -157,10 +158,11 @@ struct intel_shared_dpll *
>  intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
>  			    enum intel_dpll_id id)
>  {
> +	struct intel_display *display = to_intel_display(&i915->drm);
>  	struct intel_shared_dpll *pll;
>  	int i;
>  
> -	for_each_shared_dpll(i915, pll, i) {
> +	for_each_shared_dpll(display, pll, i) {
>  		if (pll->info->id == id)
>  			return pll;
>  	}
> @@ -344,12 +346,13 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  static unsigned long
>  intel_dpll_mask_all(struct drm_i915_private *i915)
>  {
> +	struct intel_display *display = to_intel_display(&i915->drm);
>  	struct intel_shared_dpll *pll;
>  	unsigned long dpll_mask = 0;
>  	int i;
>  
> -	for_each_shared_dpll(i915, pll, i) {
> -		drm_WARN_ON(&i915->drm, dpll_mask & BIT(pll->info->id));
> +	for_each_shared_dpll(display, pll, i) {
> +		drm_WARN_ON(display->drm, dpll_mask & BIT(pll->info->id));
>  
>  		dpll_mask |= BIT(pll->info->id);
>  	}
> @@ -513,7 +516,7 @@ static void intel_put_dpll(struct intel_atomic_state *state,
>   */
>  void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> +	struct intel_display *display = to_intel_display(state);
>  	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
>  	struct intel_shared_dpll *pll;
>  	int i;
> @@ -521,7 +524,7 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
>  	if (!state->dpll_set)
>  		return;
>  
> -	for_each_shared_dpll(i915, pll, i)
> +	for_each_shared_dpll(display, pll, i)
>  		swap(pll->state, shared_dpll[pll->index]);
>  }
>  
> @@ -4551,10 +4554,11 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
>  
>  void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
>  {
> +	struct intel_display *display = to_intel_display(&i915->drm);
>  	struct intel_shared_dpll *pll;
>  	int i;
>  
> -	for_each_shared_dpll(i915, pll, i)
> +	for_each_shared_dpll(display, pll, i)
>  		readout_dpll_hw_state(i915, pll);
>  }
>  
> @@ -4578,10 +4582,11 @@ static void sanitize_dpll_state(struct drm_i915_private *i915,
>  
>  void intel_dpll_sanitize_state(struct drm_i915_private *i915)
>  {
> +	struct intel_display *display = to_intel_display(&i915->drm);
>  	struct intel_shared_dpll *pll;
>  	int i;
>  
> -	for_each_shared_dpll(i915, pll, i)
> +	for_each_shared_dpll(display, pll, i)
>  		sanitize_dpll_state(i915, pll);
>  }
>  
> @@ -4728,10 +4733,11 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
>  
>  void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
>  {
> +	struct intel_display *display = to_intel_display(state);
>  	struct drm_i915_private *i915 = to_i915(state->base.dev);
>  	struct intel_shared_dpll *pll;
>  	int i;
>  
> -	for_each_shared_dpll(i915, pll, i)
> +	for_each_shared_dpll(display, pll, i)
>  		verify_single_dpll_state(i915, pll, NULL, NULL);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 3eee76874304..382bdf8f0b65 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -30,9 +30,9 @@
>  #include "intel_display_power.h"
>  #include "intel_wakeref.h"
>  
> -#define for_each_shared_dpll(__i915, __pll, __i) \
> -	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
> -		     ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
> +#define for_each_shared_dpll(__display, __pll, __i) \
> +	for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
> +		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>  
>  enum tc_port;
>  struct drm_i915_private;
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 71471c1d7dc9..68e953d2b124 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -492,7 +492,7 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
>  
>  static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  {
> -	struct intel_display *display = &dev_priv->display;
> +	struct intel_display *display = to_intel_display(&dev_priv->drm);
>  	struct intel_encoder *encoder;
>  	struct intel_shared_dpll *pll;
>  	int i;
> @@ -505,7 +505,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  	bool using_ssc_source = false;
>  
>  	/* We need to take the global config into account */
> -	for_each_intel_encoder(&dev_priv->drm, encoder) {
> +	for_each_intel_encoder(display->drm, encoder) {
>  		switch (encoder->type) {
>  		case INTEL_OUTPUT_LVDS:
>  			has_panel = true;
> @@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  	}
>  
>  	if (HAS_PCH_IBX(dev_priv)) {
> -		has_ck505 = dev_priv->display.vbt.display_clock_mode;
> +		has_ck505 = display->vbt.display_clock_mode;
>  		can_ssc = has_ck505;
>  	} else {
>  		has_ck505 = false;
> @@ -530,10 +530,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  	}
>  
>  	/* Check if any DPLLs are using the SSC source */
> -	for_each_shared_dpll(dev_priv, pll, i) {
> +	for_each_shared_dpll(display, pll, i) {
>  		u32 temp;
>  
> -		temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
> +		temp = intel_de_read(display, PCH_DPLL(pll->info->id));
>  
>  		if (!(temp & DPLL_VCO_ENABLE))
>  			continue;
> @@ -545,7 +545,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  		}
>  	}
>  
> -	drm_dbg_kms(&dev_priv->drm,
> +	drm_dbg_kms(display->drm,
>  		    "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
>  		    has_panel, has_lvds, has_ck505, using_ssc_source);
>  
> @@ -554,7 +554,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  	 * PCH B stepping, previous chipset stepping should be
>  	 * ignoring this setting.
>  	 */
> -	val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
> +	val = intel_de_read(display, PCH_DREF_CONTROL);
>  
>  	/* As we must carefully and slowly disable/enable each source in turn,
>  	 * compute the final state we want first and check if we need to
> @@ -614,8 +614,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  		}
>  
>  		/* Get SSC going before enabling the outputs */
> -		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> -		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> +		intel_de_write(display, PCH_DREF_CONTROL, val);
> +		intel_de_posting_read(display, PCH_DREF_CONTROL);
>  		udelay(200);
>  
>  		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
> @@ -633,23 +633,23 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  			val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
>  		}
>  
> -		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> -		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> +		intel_de_write(display, PCH_DREF_CONTROL, val);
> +		intel_de_posting_read(display, PCH_DREF_CONTROL);
>  		udelay(200);
>  	} else {
> -		drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n");
> +		drm_dbg_kms(display->drm, "Disabling CPU source output\n");
>  
>  		val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
>  
>  		/* Turn off CPU output */
>  		val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
>  
> -		intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> -		intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> +		intel_de_write(display, PCH_DREF_CONTROL, val);
> +		intel_de_posting_read(display, PCH_DREF_CONTROL);
>  		udelay(200);
>  
>  		if (!using_ssc_source) {
> -			drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n");
> +			drm_dbg_kms(display->drm, "Disabling SSC source\n");
>  
>  			/* Turn off the SSC source */
>  			val &= ~DREF_SSC_SOURCE_MASK;
> @@ -658,13 +658,13 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
>  			/* Turn off SSC1 */
>  			val &= ~DREF_SSC1_ENABLE;
>  
> -			intel_de_write(dev_priv, PCH_DREF_CONTROL, val);
> -			intel_de_posting_read(dev_priv, PCH_DREF_CONTROL);
> +			intel_de_write(display, PCH_DREF_CONTROL, val);
> +			intel_de_posting_read(display, PCH_DREF_CONTROL);
>  			udelay(200);
>  		}
>  	}
>  
> -	drm_WARN_ON(&dev_priv->drm, val != final);
> +	drm_WARN_ON(display->drm, val != final);
>  }
>  
>  /*

-- 
Jani Nikula, Intel

[PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state

[Suraj Kandpal]

Lets use intel_display for dpll dump and compare hw state. This also
helps elimanate drm_i915_private dependency from i915_shared_dplls_info
in display_debug_fs.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_crtc_state_dump.c |  3 ++-
 drivers/gpu/drm/i915/display/intel_display.c     |  8 ++++----
 .../gpu/drm/i915/display/intel_display_debugfs.c |  3 +--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c    | 16 ++++++++--------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h    |  4 ++--
 5 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index ecd0d9853c60..599ddce96371 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -176,6 +176,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 			   struct intel_atomic_state *state,
 			   const char *context)
 {
+	struct intel_display *display = to_intel_display(pipe_config);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	const struct intel_plane_state *plane_state;
@@ -340,7 +341,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 		   pipe_config->ips_enabled, pipe_config->double_wide,
 		   pipe_config->has_drrs);
 
-	intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state);
+	intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);
 
 	if (IS_CHERRYVIEW(i915))
 		drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9f8a8c94cf4c..5f4b1d8eed3e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5348,14 +5348,14 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
 			 const struct intel_dpll_hw_state *a,
 			 const struct intel_dpll_hw_state *b)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(crtc);
 
 	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
 
 	drm_printf(p, "expected:\n");
-	intel_dpll_dump_hw_state(i915, p, a);
+	intel_dpll_dump_hw_state(display, p, a);
 	drm_printf(p, "found:\n");
-	intel_dpll_dump_hw_state(i915, p, b);
+	intel_dpll_dump_hw_state(display, p, b);
 }
 
 static void
@@ -5495,7 +5495,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 } while (0)
 
 #define PIPE_CONF_CHECK_PLL(name) do { \
-	if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \
+	if (!intel_dpll_compare_hw_state(display, &current_config->name, \
 					 &pipe_config->name)) { \
 		pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
 					 &current_config->name, \
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 87e6f4000101..970b8078db8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -630,7 +630,6 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
 
 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 {
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
 	struct intel_display *display = node_to_intel_display(m->private);
 	struct drm_printer p = drm_seq_file_printer(m);
 	struct intel_shared_dpll *pll;
@@ -649,7 +648,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 			   pll->state.pipe_mask, pll->active_mask,
 			   str_yes_no(pll->on));
 		drm_printf(&p, " tracked hardware state:\n");
-		intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
+		intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
 	}
 	drm_modeset_unlock_all(display->drm);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 171d16e91c61..ee4e263ce999 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4592,18 +4592,18 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
 
 /**
  * intel_dpll_dump_hw_state - dump hw_state
- * @i915: i915 drm device
+ * @display: intel_display structure
  * @p: where to print the state to
  * @dpll_hw_state: hw state to be dumped
  *
  * Dumo out the relevant values in @dpll_hw_state.
  */
-void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
+void intel_dpll_dump_hw_state(struct intel_display *display,
 			      struct drm_printer *p,
 			      const struct intel_dpll_hw_state *dpll_hw_state)
 {
-	if (i915->display.dpll.mgr) {
-		i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
+	if (display->dpll.mgr) {
+		display->dpll.mgr->dump_hw_state(p, dpll_hw_state);
 	} else {
 		/* fallback for platforms that don't use the shared dpll
 		 * infrastructure
@@ -4614,7 +4614,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
 
 /**
  * intel_dpll_compare_hw_state - compare the two states
- * @i915: i915 drm device
+ * @display: intel_display structure
  * @a: first DPLL hw state
  * @b: second DPLL hw state
  *
@@ -4622,12 +4622,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
  *
  * Returns: true if the states are equal, false if the differ
  */
-bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_compare_hw_state(struct intel_display *display,
 				 const struct intel_dpll_hw_state *a,
 				 const struct intel_dpll_hw_state *b)
 {
-	if (i915->display.dpll.mgr) {
-		return i915->display.dpll.mgr->compare_hw_state(a, b);
+	if (display->dpll.mgr) {
+		return display->dpll.mgr->compare_hw_state(a, b);
 	} else {
 		/* fallback for platforms that don't use the shared dpll
 		 * infrastructure
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 382bdf8f0b65..42379494f347 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -427,10 +427,10 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
 void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
 void intel_dpll_sanitize_state(struct drm_i915_private *i915);
 
-void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
+void intel_dpll_dump_hw_state(struct intel_display *display,
 			      struct drm_printer *p,
 			      const struct intel_dpll_hw_state *dpll_hw_state);
-bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_compare_hw_state(struct intel_display *display,
 				 const struct intel_dpll_hw_state *a,
 				 const struct intel_dpll_hw_state *b);
 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
-- 
2.34.1

Re: [PATCH 4/9] drm/i915/dpll: Use intel_display for dpll dump and compare hw state

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Lets use intel_display for dpll dump and compare hw state. This also

*Let's

> helps elimanate drm_i915_private dependency from i915_shared_dplls_info
> in display_debug_fs.

There's no display_debug_fs...

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_crtc_state_dump.c |  3 ++-
>  drivers/gpu/drm/i915/display/intel_display.c     |  8 ++++----
>  .../gpu/drm/i915/display/intel_display_debugfs.c |  3 +--
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c    | 16 ++++++++--------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h    |  4 ++--
>  5 files changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index ecd0d9853c60..599ddce96371 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -176,6 +176,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  			   struct intel_atomic_state *state,
>  			   const char *context)
>  {
> +	struct intel_display *display = to_intel_display(pipe_config);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	const struct intel_plane_state *plane_state;
> @@ -340,7 +341,7 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  		   pipe_config->ips_enabled, pipe_config->double_wide,
>  		   pipe_config->has_drrs);
>  
> -	intel_dpll_dump_hw_state(i915, &p, &pipe_config->dpll_hw_state);
> +	intel_dpll_dump_hw_state(display, &p, &pipe_config->dpll_hw_state);
>  
>  	if (IS_CHERRYVIEW(i915))
>  		drm_printf(&p, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 9f8a8c94cf4c..5f4b1d8eed3e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5348,14 +5348,14 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
>  			 const struct intel_dpll_hw_state *a,
>  			 const struct intel_dpll_hw_state *b)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_display *display = to_intel_display(crtc);
>  
>  	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */
>  
>  	drm_printf(p, "expected:\n");
> -	intel_dpll_dump_hw_state(i915, p, a);
> +	intel_dpll_dump_hw_state(display, p, a);
>  	drm_printf(p, "found:\n");
> -	intel_dpll_dump_hw_state(i915, p, b);
> +	intel_dpll_dump_hw_state(display, p, b);
>  }
>  
>  static void
> @@ -5495,7 +5495,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  } while (0)
>  
>  #define PIPE_CONF_CHECK_PLL(name) do { \
> -	if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \
> +	if (!intel_dpll_compare_hw_state(display, &current_config->name, \
>  					 &pipe_config->name)) { \
>  		pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
>  					 &current_config->name, \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 87e6f4000101..970b8078db8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -630,7 +630,6 @@ static int i915_display_capabilities(struct seq_file *m, void *unused)
>  
>  static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  {
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
>  	struct intel_display *display = node_to_intel_display(m->private);
>  	struct drm_printer p = drm_seq_file_printer(m);
>  	struct intel_shared_dpll *pll;
> @@ -649,7 +648,7 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
>  			   pll->state.pipe_mask, pll->active_mask,
>  			   str_yes_no(pll->on));
>  		drm_printf(&p, " tracked hardware state:\n");
> -		intel_dpll_dump_hw_state(dev_priv, &p, &pll->state.hw_state);
> +		intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
>  	}
>  	drm_modeset_unlock_all(display->drm);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 171d16e91c61..ee4e263ce999 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4592,18 +4592,18 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
>  
>  /**
>   * intel_dpll_dump_hw_state - dump hw_state
> - * @i915: i915 drm device
> + * @display: intel_display structure
>   * @p: where to print the state to
>   * @dpll_hw_state: hw state to be dumped
>   *
>   * Dumo out the relevant values in @dpll_hw_state.
>   */
> -void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
> +void intel_dpll_dump_hw_state(struct intel_display *display,
>  			      struct drm_printer *p,
>  			      const struct intel_dpll_hw_state *dpll_hw_state)
>  {
> -	if (i915->display.dpll.mgr) {
> -		i915->display.dpll.mgr->dump_hw_state(p, dpll_hw_state);
> +	if (display->dpll.mgr) {
> +		display->dpll.mgr->dump_hw_state(p, dpll_hw_state);
>  	} else {
>  		/* fallback for platforms that don't use the shared dpll
>  		 * infrastructure
> @@ -4614,7 +4614,7 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
>  
>  /**
>   * intel_dpll_compare_hw_state - compare the two states
> - * @i915: i915 drm device
> + * @display: intel_display structure
>   * @a: first DPLL hw state
>   * @b: second DPLL hw state
>   *
> @@ -4622,12 +4622,12 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
>   *
>   * Returns: true if the states are equal, false if the differ
>   */
> -bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
> +bool intel_dpll_compare_hw_state(struct intel_display *display,
>  				 const struct intel_dpll_hw_state *a,
>  				 const struct intel_dpll_hw_state *b)
>  {
> -	if (i915->display.dpll.mgr) {
> -		return i915->display.dpll.mgr->compare_hw_state(a, b);
> +	if (display->dpll.mgr) {
> +		return display->dpll.mgr->compare_hw_state(a, b);
>  	} else {
>  		/* fallback for platforms that don't use the shared dpll
>  		 * infrastructure
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 382bdf8f0b65..42379494f347 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -427,10 +427,10 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
>  void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
>  void intel_dpll_sanitize_state(struct drm_i915_private *i915);
>  
> -void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
> +void intel_dpll_dump_hw_state(struct intel_display *display,
>  			      struct drm_printer *p,
>  			      const struct intel_dpll_hw_state *dpll_hw_state);
> -bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
> +bool intel_dpll_compare_hw_state(struct intel_display *display,
>  				 const struct intel_dpll_hw_state *a,
>  				 const struct intel_dpll_hw_state *b);
>  enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);

-- 
Jani Nikula, Intel

[PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks

[Suraj Kandpal]

We use intel_display for function hooks of shared_dpll_mgr and
any function that gets called when we use for_each_shared_dpll.
This also contains some opportunistic display->platform.xx changes
all to reductate the use of drm_i915_private.

--v2
-rebase

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 130 +--
 .../i915/display/intel_display_power_well.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |  54 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |   9 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 794 +++++++++---------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  10 +-
 .../drm/i915/display/intel_modeset_setup.c    |   4 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |  43 +-
 8 files changed, 517 insertions(+), 530 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6e09dfcbaa7d..bb7abcb9e633 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -358,10 +358,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 	}
 }
 
-static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
+static int icl_calc_tbt_pll_link(struct intel_display *display,
 				 enum port port)
 {
-	u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+	u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 
 	switch (val) {
 	case DDI_CLK_SEL_NONE:
@@ -1367,7 +1367,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 					  const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum tc_port tc_port = intel_encoder_to_tc(encoder);
 	const struct intel_ddi_buf_trans *trans;
 	int n_entries, ln;
@@ -1376,17 +1376,17 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 		return;
 
 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
+	if (drm_WARN_ON_ONCE(display->drm, !trans))
 		return;
 
 	for (ln = 0; ln < 2; ln++) {
 		int level;
 
-		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
+		intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
+		intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
 				  DKL_TX_PRESHOOT_COEFF_MASK |
 				  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 				  DKL_TX_VSWING_CONTROL_MASK,
@@ -1396,7 +1396,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
+		intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
 				  DKL_TX_PRESHOOT_COEFF_MASK |
 				  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 				  DKL_TX_VSWING_CONTROL_MASK,
@@ -1404,10 +1404,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 				  DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
 				  DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
-		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+		intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
 				  DKL_TX_DP20BITMODE, 0);
 
-		if (IS_ALDERLAKE_P(dev_priv)) {
+		if (display->platform.alderlake_p) {
 			u32 val;
 
 			if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -1423,7 +1423,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 				val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
 			}
 
-			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+			intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
 					  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
 					  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
 					  val);
@@ -1551,14 +1551,14 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t
 }
 
 static struct intel_shared_dpll *
-_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
+_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
 		 u32 clk_sel_mask, u32 clk_sel_shift)
 {
 	enum intel_dpll_id id;
 
-	id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
+	id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1597,10 +1597,10 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 
-	return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
+	return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
 				ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
 				ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
 }
@@ -1641,10 +1641,10 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 
-	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
 				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
 }
@@ -1694,12 +1694,12 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 	enum intel_dpll_id id;
 	u32 val;
 
-	val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
+	val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
 	val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 	val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
 	id = val;
@@ -1712,7 +1712,7 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
 	if (phy >= PHY_C)
 		id += DPLL_ID_DG1_DPLL2;
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1751,10 +1751,10 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
 
 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 
-	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
 				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
 }
@@ -1859,13 +1859,13 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum tc_port tc_port = intel_encoder_to_tc(encoder);
 	enum port port = encoder->port;
 	enum intel_dpll_id id;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+	tmp = intel_de_read(display, DDI_CLK_SEL(port));
 
 	switch (tmp & DDI_CLK_SEL_MASK) {
 	case DDI_CLK_SEL_TBT_162:
@@ -1884,12 +1884,12 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
 		return NULL;
 	}
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder->base.dev);
 	enum intel_dpll_id id;
 
 	switch (encoder->port) {
@@ -1907,7 +1907,7 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
 		return NULL;
 	}
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1958,12 +1958,12 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
 	enum intel_dpll_id id;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, DPLL_CTRL2);
+	tmp = intel_de_read(display, DPLL_CTRL2);
 
 	/*
 	 * FIXME Not sure if the override affects both
@@ -1975,7 +1975,7 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
 	id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
 		DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2009,12 +2009,12 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
 	enum intel_dpll_id id;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, PORT_CLK_SEL(port));
+	tmp = intel_de_read(display, PORT_CLK_SEL(port));
 
 	switch (tmp & PORT_CLK_SEL_MASK) {
 	case PORT_CLK_SEL_WRPLL1:
@@ -2042,7 +2042,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
 		return NULL;
 	}
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2122,13 +2122,13 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 }
 
 static void
-tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
 			      enum tc_port tc_port, u32 ln0, u32 ln1)
 {
-	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
-	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+	if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
 }
 
 static void
@@ -2136,24 +2136,23 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
 	u32 ln0, ln1, pin_assignment;
 	u8 width;
 
-	if (DISPLAY_VER(dev_priv) >= 14)
+	if (DISPLAY_VER(display) >= 14)
 		return;
 
 	if (!intel_encoder_is_tc(&dig_port->base) ||
 	    intel_tc_port_in_tbt_alt_mode(dig_port))
 		return;
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
-		ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
-		ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
+	if (DISPLAY_VER(display) >= 12) {
+		ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
+		ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
 	} else {
-		ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
-		ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
+		ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
+		ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
 	}
 
 	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -2165,7 +2164,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 
 	switch (pin_assignment) {
 	case 0x0:
-		drm_WARN_ON(&dev_priv->drm,
+		drm_WARN_ON(display->drm,
 			    !intel_tc_port_in_legacy_mode(dig_port));
 		if (width == 1) {
 			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
@@ -2210,16 +2209,16 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		MISSING_CASE(pin_assignment);
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+	if (DISPLAY_VER(display) >= 12) {
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
 		 /* WA_14018221282 */
 		if (IS_DISPLAY_VER(display, 12, 13))
-			tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+			tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
 
 	} else {
-		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
-		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
+		intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
+		intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
 	}
 }
 
@@ -3731,12 +3730,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 
 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum tc_port tc_port = intel_encoder_to_tc(encoder);
 	int ln;
 
 	for (ln = 0; ln < 2; ln++)
-		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
+		intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
+				  DKL_PCS_DW5_CORE_SOFTRESET, 0);
 }
 
 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
@@ -4257,21 +4257,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 			 struct intel_crtc_state *crtc_state,
 			 struct intel_shared_dpll *pll)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
 	struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
 	bool pll_active;
 
-	if (drm_WARN_ON(&i915->drm, !pll))
+	if (drm_WARN_ON(display->drm, !pll))
 		return;
 
 	port_dpll->pll = pll;
-	pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
-	drm_WARN_ON(&i915->drm, !pll_active);
+	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+	drm_WARN_ON(display->drm, !pll_active);
 
 	icl_set_active_port_dpll(crtc_state, port_dpll_id);
 
-	crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+	crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
 						     &crtc_state->dpll_hw_state);
 }
 
@@ -4360,12 +4360,12 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
 				 struct intel_crtc_state *crtc_state,
 				 struct intel_shared_dpll *pll)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum icl_port_dpll_id port_dpll_id;
 	struct icl_port_dpll *port_dpll;
 	bool pll_active;
 
-	if (drm_WARN_ON(&i915->drm, !pll))
+	if (drm_WARN_ON(display->drm, !pll))
 		return;
 
 	if (icl_ddi_tc_pll_is_tbt(pll))
@@ -4376,15 +4376,15 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
 	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
 
 	port_dpll->pll = pll;
-	pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
-	drm_WARN_ON(&i915->drm, !pll_active);
+	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+	drm_WARN_ON(display->drm, !pll_active);
 
 	icl_set_active_port_dpll(crtc_state, port_dpll_id);
 
 	if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
-		crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
+		crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
 	else
-		crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
 							     &crtc_state->dpll_hw_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f45a4f9ba23c..a31d1678dfc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -507,7 +507,6 @@ static void
 icl_tc_phy_aux_power_well_enable(struct intel_display *display,
 				 struct i915_power_well *power_well)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -539,7 +538,7 @@ icl_tc_phy_aux_power_well_enable(struct intel_display *display,
 
 		tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
 
-		if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
+		if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) &
 			     DKL_CMN_UC_DW27_UC_HEALTH, 1))
 			drm_warn(display->drm,
 				 "Timeout waiting TC uC health\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
index b146b4c46943..0920f78f182e 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
@@ -20,20 +20,20 @@ void intel_dkl_phy_init(struct drm_i915_private *i915)
 }
 
 static void
-dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
 {
 	enum tc_port tc_port = DKL_REG_TC_PORT(reg);
 
-	drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
+	drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
 
-	intel_de_write(i915,
+	intel_de_write(display,
 		       HIP_INDEX_REG(tc_port),
 		       HIP_INDEX_VAL(tc_port, reg.bank_idx));
 }
 
 /**
  * intel_dkl_phy_read - read a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
  * @reg: Dekel PHY register
  *
  * Read the @reg Dekel PHY register.
@@ -41,42 +41,42 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
  * Returns the read value.
  */
 u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
 {
 	u32 val;
 
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	val = intel_de_read(i915, DKL_REG_MMIO(reg));
+	dkl_phy_set_hip_idx(display, reg);
+	val = intel_de_read(display, DKL_REG_MMIO(reg));
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 
 	return val;
 }
 
 /**
  * intel_dkl_phy_write - write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
  * @reg: Dekel PHY register
  * @val: value to write
  *
  * Write @val to the @reg Dekel PHY register.
  */
 void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
 {
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	intel_de_write(i915, DKL_REG_MMIO(reg), val);
+	dkl_phy_set_hip_idx(display, reg);
+	intel_de_write(display, DKL_REG_MMIO(reg), val);
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 }
 
 /**
  * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
  * @reg: Dekel PHY register
  * @clear: mask to clear
  * @set: mask to set
@@ -85,30 +85,30 @@ intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg,
  * this value back to the register if the value differs from the read one.
  */
 void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
 {
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
+	dkl_phy_set_hip_idx(display, reg);
+	intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 }
 
 /**
  * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
  * @reg: Dekel PHY register
  *
  * Read the @reg Dekel PHY register without returning the read value.
  */
 void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
 {
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	intel_de_posting_read(i915, DKL_REG_MMIO(reg));
+	dkl_phy_set_hip_idx(display, reg);
+	intel_de_posting_read(display, DKL_REG_MMIO(reg));
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
index 5956ec3e940b..1d96e6be657c 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
@@ -11,15 +11,16 @@
 #include "intel_dkl_phy_regs.h"
 
 struct drm_i915_private;
+struct intel_display;
 
 void intel_dkl_phy_init(struct drm_i915_private *i915);
 u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
 void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val);
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
 void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
 void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
 
 #endif /* __INTEL_DKL_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ee4e263ce999..9976ac6322d1 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -65,7 +65,7 @@ struct intel_shared_dpll_funcs {
 	 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
 	 * the pll is not already enabled.
 	 */
-	void (*enable)(struct drm_i915_private *i915,
+	void (*enable)(struct intel_display *display,
 		       struct intel_shared_dpll *pll,
 		       const struct intel_dpll_hw_state *dpll_hw_state);
 
@@ -74,7 +74,7 @@ struct intel_shared_dpll_funcs {
 	 * only when it is safe to disable the pll, i.e., there are no more
 	 * tracked users for it.
 	 */
-	void (*disable)(struct drm_i915_private *i915,
+	void (*disable)(struct intel_display *display,
 			struct intel_shared_dpll *pll);
 
 	/*
@@ -82,7 +82,7 @@ struct intel_shared_dpll_funcs {
 	 * registers. This is used for initial hw state readout and state
 	 * verification after a mode set.
 	 */
-	bool (*get_hw_state)(struct drm_i915_private *i915,
+	bool (*get_hw_state)(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *dpll_hw_state);
 
@@ -90,7 +90,7 @@ struct intel_shared_dpll_funcs {
 	 * Hook for calculating the pll's output frequency based on its passed
 	 * in state.
 	 */
-	int (*get_freq)(struct drm_i915_private *i915,
+	int (*get_freq)(struct intel_display *i915,
 			const struct intel_shared_dpll *pll,
 			const struct intel_dpll_hw_state *dpll_hw_state);
 };
@@ -148,17 +148,16 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
 
 /**
  * intel_get_shared_dpll_by_id - get a DPLL given its id
- * @i915: i915 device instance
+ * @display: intel_display device instance
  * @id: pll id
  *
  * Returns:
  * A pointer to the DPLL with @id
  */
 struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
 			    enum intel_dpll_id id)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
@@ -184,7 +183,7 @@ void assert_shared_dpll(struct drm_i915_private *i915,
 		     "asserting DPLL %s with no DPLL\n", str_on_off(state)))
 		return;
 
-	cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
+	cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
 				 "%s assertion failure (expected %s, current %s)\n",
 				 pll->info->name, str_on_off(state),
@@ -202,12 +201,12 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 }
 
 static i915_reg_t
-intel_combo_pll_enable_reg(struct drm_i915_private *i915,
+intel_combo_pll_enable_reg(struct intel_display *display,
 			   struct intel_shared_dpll *pll)
 {
-	if (IS_DG1(i915))
+	if (display->platform.dg1)
 		return DG1_DPLL_ENABLE(pll->info->id);
-	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		 (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
@@ -215,36 +214,32 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 }
 
 static i915_reg_t
-intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+intel_tc_pll_enable_reg(struct intel_display *display,
 			struct intel_shared_dpll *pll)
 {
 	const enum intel_dpll_id id = pll->info->id;
 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
 
-	if (IS_ALDERLAKE_P(i915))
+	if (display->platform.alderlake_p)
 		return ADLP_PORTTC_PLL_ENABLE(tc_port);
 
 	return MG_PLL_ENABLE(tc_port);
 }
 
-static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_enable_shared_dpll(struct intel_display *display,
 				      struct intel_shared_dpll *pll)
 {
-	struct intel_display *display = &i915->display;
-
 	if (pll->info->power_domain)
 		pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
 
-	pll->info->funcs->enable(i915, pll, &pll->state.hw_state);
+	pll->info->funcs->enable(display, pll, &pll->state.hw_state);
 	pll->on = true;
 }
 
-static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_disable_shared_dpll(struct intel_display *display,
 				       struct intel_shared_dpll *pll)
 {
-	struct intel_display *display = &i915->display;
-
-	pll->info->funcs->disable(i915, pll);
+	pll->info->funcs->disable(display, pll);
 	pll->on = false;
 
 	if (pll->info->power_domain)
@@ -259,42 +254,43 @@ static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
  */
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int pipe_mask = BIT(crtc->pipe);
 	unsigned int old_mask;
 
-	if (drm_WARN_ON(&i915->drm, pll == NULL))
+	if (drm_WARN_ON(display->drm, !pll))
 		return;
 
-	mutex_lock(&i915->display.dpll.lock);
+	mutex_lock(&display->dpll.lock);
 	old_mask = pll->active_mask;
 
-	if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
-	    drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
+	if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
+	    drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
 		goto out;
 
 	pll->active_mask |= pipe_mask;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
 		    pll->info->name, pll->active_mask, pll->on,
 		    crtc->base.base.id, crtc->base.name);
 
 	if (old_mask) {
-		drm_WARN_ON(&i915->drm, !pll->on);
+		drm_WARN_ON(display->drm, !pll->on);
 		assert_shared_dpll_enabled(i915, pll);
 		goto out;
 	}
-	drm_WARN_ON(&i915->drm, pll->on);
+	drm_WARN_ON(display->drm, pll->on);
 
-	drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
+	drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
 
-	_intel_enable_shared_dpll(i915, pll);
+	_intel_enable_shared_dpll(display, pll);
 
 out:
-	mutex_unlock(&i915->display.dpll.lock);
+	mutex_unlock(&display->dpll.lock);
 }
 
 /**
@@ -305,48 +301,48 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
  */
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int pipe_mask = BIT(crtc->pipe);
 
 	/* PCH only available on ILK+ */
-	if (DISPLAY_VER(i915) < 5)
+	if (DISPLAY_VER(display) < 5)
 		return;
 
 	if (pll == NULL)
 		return;
 
-	mutex_lock(&i915->display.dpll.lock);
-	if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
+	mutex_lock(&display->dpll.lock);
+	if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
 		     "%s not used by [CRTC:%d:%s]\n", pll->info->name,
 		     crtc->base.base.id, crtc->base.name))
 		goto out;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
 		    pll->info->name, pll->active_mask, pll->on,
 		    crtc->base.base.id, crtc->base.name);
 
 	assert_shared_dpll_enabled(i915, pll);
-	drm_WARN_ON(&i915->drm, !pll->on);
+	drm_WARN_ON(display->drm, !pll->on);
 
 	pll->active_mask &= ~pipe_mask;
 	if (pll->active_mask)
 		goto out;
 
-	drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
+	drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
 
-	_intel_disable_shared_dpll(i915, pll);
+	_intel_disable_shared_dpll(display, pll);
 
 out:
-	mutex_unlock(&i915->display.dpll.lock);
+	mutex_unlock(&display->dpll.lock);
 }
 
 static unsigned long
-intel_dpll_mask_all(struct drm_i915_private *i915)
+intel_dpll_mask_all(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	unsigned long dpll_mask = 0;
 	int i;
@@ -366,20 +362,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 		       const struct intel_dpll_hw_state *dpll_hw_state,
 		       unsigned long dpll_mask)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	unsigned long dpll_mask_all = intel_dpll_mask_all(i915);
+	struct intel_display *display = to_intel_display(crtc);
+	unsigned long dpll_mask_all = intel_dpll_mask_all(display);
 	struct intel_shared_dpll_state *shared_dpll;
 	struct intel_shared_dpll *unused_pll = NULL;
 	enum intel_dpll_id id;
 
 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
 
-	drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
+	drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
 
 	for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
 		struct intel_shared_dpll *pll;
 
-		pll = intel_get_shared_dpll_by_id(i915, id);
+		pll = intel_get_shared_dpll_by_id(display, id);
 		if (!pll)
 			continue;
 
@@ -393,7 +389,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 		if (memcmp(dpll_hw_state,
 			   &shared_dpll[pll->index].hw_state,
 			   sizeof(*dpll_hw_state)) == 0) {
-			drm_dbg_kms(&i915->drm,
+			drm_dbg_kms(display->drm,
 				    "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
 				    crtc->base.base.id, crtc->base.name,
 				    pll->info->name,
@@ -405,7 +401,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 
 	/* Ok no matching timings, maybe there's a free one? */
 	if (unused_pll) {
-		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
+		drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",
 			    crtc->base.base.id, crtc->base.name,
 			    unused_pll->info->name);
 		return unused_pll;
@@ -528,11 +524,10 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
 		swap(pll->state, shared_dpll[pll->index]);
 }
 
-static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
+static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
 				      struct intel_shared_dpll *pll,
 				      struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
 	const enum intel_dpll_id id = pll->info->id;
 	intel_wakeref_t wakeref;
@@ -543,10 +538,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, PCH_DPLL(id));
+	val = intel_de_read(display, PCH_DPLL(id));
 	hw_state->dpll = val;
-	hw_state->fp0 = intel_de_read(i915, PCH_FP0(id));
-	hw_state->fp1 = intel_de_read(i915, PCH_FP1(id));
+	hw_state->fp0 = intel_de_read(display, PCH_FP0(id));
+	hw_state->fp1 = intel_de_read(display, PCH_FP1(id));
 
 	intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
@@ -566,23 +561,24 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
 				 "PCH refclk assertion failure, should be active but is disabled\n");
 }
 
-static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_enable(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
 	const enum intel_dpll_id id = pll->info->id;
 
 	/* PCH refclock must be enabled first */
 	ibx_assert_pch_refclk_enabled(i915);
 
-	intel_de_write(i915, PCH_FP0(id), hw_state->fp0);
-	intel_de_write(i915, PCH_FP1(id), hw_state->fp1);
+	intel_de_write(display, PCH_FP0(id), hw_state->fp0);
+	intel_de_write(display, PCH_FP1(id), hw_state->fp1);
 
-	intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
+	intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
 
 	/* Wait for the clocks to stabilize. */
-	intel_de_posting_read(i915, PCH_DPLL(id));
+	intel_de_posting_read(display, PCH_DPLL(id));
 	udelay(150);
 
 	/* The pixel multiplier can only be updated once the
@@ -590,18 +586,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
 	 *
 	 * So write it again.
 	 */
-	intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
-	intel_de_posting_read(i915, PCH_DPLL(id));
+	intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
+	intel_de_posting_read(display, PCH_DPLL(id));
 	udelay(200);
 }
 
-static void ibx_pch_dpll_disable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_disable(struct intel_display *display,
 				 struct intel_shared_dpll *pll)
 {
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_write(i915, PCH_DPLL(id), 0);
-	intel_de_posting_read(i915, PCH_DPLL(id));
+	intel_de_write(display, PCH_DPLL(id), 0);
+	intel_de_posting_read(display, PCH_DPLL(id));
 	udelay(200);
 }
 
@@ -616,18 +612,19 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(state);
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
 
 	if (HAS_PCH_IBX(i915)) {
 		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
 		id = (enum intel_dpll_id) crtc->pipe;
-		pll = intel_get_shared_dpll_by_id(i915, id);
+		pll = intel_get_shared_dpll_by_id(display, id);
 
-		drm_dbg_kms(&i915->drm,
+		drm_dbg_kms(display->drm,
 			    "[CRTC:%d:%s] using pre-allocated %s\n",
 			    crtc->base.base.id, crtc->base.name,
 			    pll->info->name);
@@ -696,66 +693,65 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
 	.compare_hw_state = ibx_compare_hw_state,
 };
 
-static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
-	intel_de_posting_read(i915, WRPLL_CTL(id));
+	intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
+	intel_de_posting_read(display, WRPLL_CTL(id));
 	udelay(20);
 }
 
-static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_enable(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 
-	intel_de_write(i915, SPLL_CTL, hw_state->spll);
-	intel_de_posting_read(i915, SPLL_CTL);
+	intel_de_write(display, SPLL_CTL, hw_state->spll);
+	intel_de_posting_read(display, SPLL_CTL);
 	udelay(20);
 }
 
-static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_disable(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, WRPLL_CTL(id));
+	intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
+	intel_de_posting_read(display, WRPLL_CTL(id));
 
 	/*
 	 * Try to set up the PCH reference clock once all DPLLs
 	 * that depend on it have been shut down.
 	 */
-	if (i915->display.dpll.pch_ssc_use & BIT(id))
-		intel_init_pch_refclk(i915);
+	if (display->dpll.pch_ssc_use & BIT(id))
+		intel_init_pch_refclk(to_i915(display->drm));
 }
 
-static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_disable(struct intel_display *display,
 				 struct intel_shared_dpll *pll)
 {
 	enum intel_dpll_id id = pll->info->id;
 
-	intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, SPLL_CTL);
+	intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);
+	intel_de_posting_read(display, SPLL_CTL);
 
 	/*
 	 * Try to set up the PCH reference clock once all DPLLs
 	 * that depend on it have been shut down.
 	 */
-	if (i915->display.dpll.pch_ssc_use & BIT(id))
-		intel_init_pch_refclk(i915);
+	if (display->dpll.pch_ssc_use & BIT(id))
+		intel_init_pch_refclk(to_i915(display->drm));
 }
 
-static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 	const enum intel_dpll_id id = pll->info->id;
 	intel_wakeref_t wakeref;
@@ -766,7 +762,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, WRPLL_CTL(id));
+	val = intel_de_read(display, WRPLL_CTL(id));
 	hw_state->wrpll = val;
 
 	intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -774,11 +770,10 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
 	return val & WRPLL_PLL_ENABLE;
 }
 
-static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
 				      struct intel_shared_dpll *pll,
 				      struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 	intel_wakeref_t wakeref;
 	u32 val;
@@ -788,7 +783,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, SPLL_CTL);
+	val = intel_de_read(display, SPLL_CTL);
 	hw_state->spll = val;
 
 	intel_display_power_put(display, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -1002,7 +997,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 	*r2_out = best.r2;
 }
 
-static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1014,8 +1009,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	switch (wrpll & WRPLL_REF_MASK) {
 	case WRPLL_REF_SPECIAL_HSW:
 		/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
-		if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) {
-			refclk = i915->display.dpll.ref_clks.nssc;
+		if (display->platform.haswell && !display->platform.haswell_ult) {
+			refclk = display->dpll.ref_clks.nssc;
 			break;
 		}
 		fallthrough;
@@ -1025,7 +1020,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 		 * code only cares about 5% accuracy, and spread is a max of
 		 * 0.5% downspread.
 		 */
-		refclk = i915->display.dpll.ref_clks.ssc;
+		refclk = display->dpll.ref_clks.ssc;
 		break;
 	case WRPLL_REF_LCPLL:
 		refclk = 2700000;
@@ -1047,7 +1042,7 @@ static int
 hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1060,7 +1055,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
 		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		WRPLL_DIVIDER_POST(p);
 
-	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
+	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
 							&crtc_state->dpll_hw_state);
 
 	return 0;
@@ -1100,7 +1095,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
 static struct intel_shared_dpll *
 hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id pll_id;
 	int clock = crtc_state->port_clock;
@@ -1120,7 +1115,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 		return NULL;
 	}
 
-	pll = intel_get_shared_dpll_by_id(i915, pll_id);
+	pll = intel_get_shared_dpll_by_id(display, pll_id);
 
 	if (!pll)
 		return NULL;
@@ -1128,7 +1123,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 	return pll;
 }
 
-static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1145,7 +1140,7 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 		link_clock = 270000;
 		break;
 	default:
-		drm_WARN(&i915->drm, 1, "bad port clock sel\n");
+		drm_WARN(display->drm, 1, "bad port clock sel\n");
 		break;
 	}
 
@@ -1180,7 +1175,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
 				      BIT(DPLL_ID_SPLL));
 }
 
-static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_spll_get_freq(struct intel_display *display,
 				 const struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1198,7 +1193,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
 		link_clock = 270000;
 		break;
 	default:
-		drm_WARN(&i915->drm, 1, "bad spll freq\n");
+		drm_WARN(display->drm, 1, "bad spll freq\n");
 		break;
 	}
 
@@ -1291,18 +1286,18 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
 	.get_freq = hsw_ddi_spll_get_freq,
 };
 
-static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *hw_state)
 {
 }
 
-static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_disable(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
 }
 
-static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1370,21 +1365,21 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
 	},
 };
 
-static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
+static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
 				    struct intel_shared_dpll *pll,
 				    const struct skl_dpll_hw_state *hw_state)
 {
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_rmw(i915, DPLL_CTRL1,
+	intel_de_rmw(display, DPLL_CTRL1,
 		     DPLL_CTRL1_HDMI_MODE(id) |
 		     DPLL_CTRL1_SSC(id) |
 		     DPLL_CTRL1_LINK_RATE_MASK(id),
 		     hw_state->ctrl1 << (id * 6));
-	intel_de_posting_read(i915, DPLL_CTRL1);
+	intel_de_posting_read(display, DPLL_CTRL1);
 }
 
-static void skl_ddi_pll_enable(struct drm_i915_private *i915,
+static void skl_ddi_pll_enable(struct intel_display *display,
 			       struct intel_shared_dpll *pll,
 			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1392,50 +1387,49 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915,
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
 
-	skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+	skl_ddi_pll_write_ctrl1(display, pll, hw_state);
 
-	intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
-	intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
-	intel_de_posting_read(i915, regs[id].cfgcr1);
-	intel_de_posting_read(i915, regs[id].cfgcr2);
+	intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);
+	intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);
+	intel_de_posting_read(display, regs[id].cfgcr1);
+	intel_de_posting_read(display, regs[id].cfgcr2);
 
 	/* the enable bit is always bit 31 */
-	intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
+	intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
 
-	if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
-		drm_err(&i915->drm, "DPLL %d not locked\n", id);
+	if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
+		drm_err(display->drm, "DPLL %d not locked\n", id);
 }
 
-static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
 
-	skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+	skl_ddi_pll_write_ctrl1(display, pll, hw_state);
 }
 
-static void skl_ddi_pll_disable(struct drm_i915_private *i915,
+static void skl_ddi_pll_disable(struct intel_display *display,
 				struct intel_shared_dpll *pll)
 {
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
 
 	/* the enable bit is always bit 31 */
-	intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, regs[id].ctl);
+	intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
+	intel_de_posting_read(display, regs[id].ctl);
 }
 
-static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_disable(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
 }
 
-static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
 				     struct intel_shared_dpll *pll,
 				     struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
@@ -1450,17 +1444,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 
 	ret = false;
 
-	val = intel_de_read(i915, regs[id].ctl);
+	val = intel_de_read(display, regs[id].ctl);
 	if (!(val & LCPLL_PLL_ENABLE))
 		goto out;
 
-	val = intel_de_read(i915, DPLL_CTRL1);
+	val = intel_de_read(display, DPLL_CTRL1);
 	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
 
 	/* avoid reading back stale values if HDMI mode is not enabled */
 	if (val & DPLL_CTRL1_HDMI_MODE(id)) {
-		hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1);
-		hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2);
+		hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);
+		hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);
 	}
 	ret = true;
 
@@ -1470,11 +1464,10 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
@@ -1490,11 +1483,11 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
 	ret = false;
 
 	/* DPLL0 is always enabled since it drives CDCLK */
-	val = intel_de_read(i915, regs[id].ctl);
-	if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
+	val = intel_de_read(display, regs[id].ctl);
+	if (drm_WARN_ON(display->drm, !(val & LCPLL_PLL_ENABLE)))
 		goto out;
 
-	val = intel_de_read(i915, DPLL_CTRL1);
+	val = intel_de_read(display, DPLL_CTRL1);
 	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
 
 	ret = true;
@@ -1744,12 +1737,12 @@ skl_ddi_calculate_wrpll(int clock,
 	return 0;
 }
 
-static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_wrpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
-	int ref_clock = i915->display.dpll.ref_clks.nssc;
+	int ref_clock = display->dpll.ref_clks.nssc;
 	u32 p0, p1, p2, dco_freq;
 
 	p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1776,7 +1769,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 		 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
 		 * handling it the same way as PDIV_7.
 		 */
-		drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+		drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
 		fallthrough;
 	case DPLL_CFGCR2_PDIV_7:
 		p0 = 7;
@@ -1810,7 +1803,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
 		    ref_clock / 0x8000;
 
-	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+	if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
 		return 0;
 
 	return dco_freq / (p0 * p1 * p2 * 5);
@@ -1818,13 +1811,13 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 
 static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
 	struct skl_wrpll_params wrpll_params = {};
 	int ret;
 
 	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
-				      i915->display.dpll.ref_clks.nssc, &wrpll_params);
+				      display->dpll.ref_clks.nssc, &wrpll_params);
 	if (ret)
 		return ret;
 
@@ -1848,7 +1841,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 		DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
 		wrpll_params.central_freq;
 
-	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
+	crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,
 							&crtc_state->dpll_hw_state);
 
 	return 0;
@@ -1892,7 +1885,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_lcpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1920,7 +1913,7 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 		link_clock = 270000;
 		break;
 	default:
-		drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
+		drm_WARN(display->drm, 1, "Unsupported link rate\n");
 		break;
 	}
 
@@ -1971,7 +1964,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_pll_get_freq(struct intel_display *display,
 				const struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1982,9 +1975,9 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
 	 * the internal shift for each field
 	 */
 	if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
-		return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
+		return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
 	else
-		return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
+		return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
 }
 
 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2046,11 +2039,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
 	.compare_hw_state = skl_compare_hw_state,
 };
 
-static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_enable(struct intel_display *display,
 			       struct intel_shared_dpll *pll,
 			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	enum dpio_phy phy;
@@ -2060,120 +2052,119 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
 	bxt_port_to_phy_channel(display, port, &phy, &ch);
 
 	/* Non-SSC reference */
-	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
+	intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
 
-	if (IS_GEMINILAKE(i915)) {
-		intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+	if (display->platform.geminilake) {
+		intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
 			     0, PORT_PLL_POWER_ENABLE);
 
-		if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+		if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
 				 PORT_PLL_POWER_STATE), 200))
-			drm_err(&i915->drm,
+			drm_err(display->drm,
 				"Power state not set for PLL:%d\n", port);
 	}
 
 	/* Disable 10 bit clock */
-	intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch),
+	intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),
 		     PORT_PLL_10BIT_CLK_ENABLE, 0);
 
 	/* Write P1 & P2 */
-	intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
+	intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),
 		     PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
 
 	/* Write M2 integer */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),
 		     PORT_PLL_M2_INT_MASK, hw_state->pll0);
 
 	/* Write N */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),
 		     PORT_PLL_N_MASK, hw_state->pll1);
 
 	/* Write M2 fraction */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),
 		     PORT_PLL_M2_FRAC_MASK, hw_state->pll2);
 
 	/* Write M2 fraction enable */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),
 		     PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3);
 
 	/* Write coeff */
-	temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+	temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
 	temp &= ~PORT_PLL_PROP_COEFF_MASK;
 	temp &= ~PORT_PLL_INT_COEFF_MASK;
 	temp &= ~PORT_PLL_GAIN_CTL_MASK;
 	temp |= hw_state->pll6;
-	intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
+	intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);
 
 	/* Write calibration val */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),
 		     PORT_PLL_TARGET_CNT_MASK, hw_state->pll8);
 
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),
 		     PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9);
 
-	temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+	temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
 	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
 	temp &= ~PORT_PLL_DCO_AMP_MASK;
 	temp |= hw_state->pll10;
-	intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
+	intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);
 
 	/* Recalibrate with new settings */
-	temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+	temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
 	temp |= PORT_PLL_RECALIBRATE;
-	intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+	intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
 	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
 	temp |= hw_state->ebb4;
-	intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+	intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
 
 	/* Enable PLL */
-	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
-	intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+	intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
+	intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
 
-	if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
+	if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
 			200))
-		drm_err(&i915->drm, "PLL %d not locked\n", port);
+		drm_err(display->drm, "PLL %d not locked\n", port);
 
-	if (IS_GEMINILAKE(i915)) {
-		temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
+	if (display->platform.geminilake) {
+		temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));
 		temp |= DCC_DELAY_RANGE_2;
-		intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
+		intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
 	}
 
 	/*
 	 * While we write to the group register to program all lanes at once we
 	 * can read only lane registers and we pick lanes 0/1 for that.
 	 */
-	temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
+	temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));
 	temp &= ~LANE_STAGGER_MASK;
 	temp &= ~LANESTAGGER_STRAP_OVRD;
 	temp |= hw_state->pcsdw12;
-	intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
+	intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
 }
 
-static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_disable(struct intel_display *display,
 				struct intel_shared_dpll *pll)
 {
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 
-	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+	intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
+	intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
 
-	if (IS_GEMINILAKE(i915)) {
-		intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+	if (display->platform.geminilake) {
+		intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
 			     PORT_PLL_POWER_ENABLE, 0);
 
-		if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+		if (wait_for_us(!(intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
 				  PORT_PLL_POWER_STATE), 200))
-			drm_err(&i915->drm,
+			drm_err(display->drm,
 				"Power state not reset for PLL:%d\n", port);
 	}
 }
 
-static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
 				     struct intel_shared_dpll *pll,
 				     struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	intel_wakeref_t wakeref;
@@ -2191,40 +2182,40 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 
 	ret = false;
 
-	val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
+	val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
 	if (!(val & PORT_PLL_ENABLE))
 		goto out;
 
-	hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch));
+	hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));
 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
 
-	hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+	hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
 	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
 
-	hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0));
+	hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));
 	hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
 
-	hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1));
+	hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));
 	hw_state->pll1 &= PORT_PLL_N_MASK;
 
-	hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
+	hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));
 	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
 
-	hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3));
+	hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));
 	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
 
-	hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+	hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
 	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
 			  PORT_PLL_INT_COEFF_MASK |
 			  PORT_PLL_GAIN_CTL_MASK;
 
-	hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8));
+	hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));
 	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
 
-	hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9));
+	hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));
 	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
 
-	hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+	hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
 	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
 			   PORT_PLL_DCO_AMP_MASK;
 
@@ -2233,13 +2224,13 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 	 * can read only lane registers. We configure all lanes the same way, so
 	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
 	 */
-	hw_state->pcsdw12 = intel_de_read(i915,
+	hw_state->pcsdw12 = intel_de_read(display,
 					  BXT_PORT_PCS_DW12_LN01(phy, ch));
-	if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
-		drm_dbg(&i915->drm,
+	if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
+		drm_dbg(display->drm,
 			"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
 			hw_state->pcsdw12,
-			intel_de_read(i915,
+			intel_de_read(display,
 				      BXT_PORT_PCS_DW12_LN23(phy, ch)));
 	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
 
@@ -2370,7 +2361,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int bxt_ddi_pll_get_freq(struct intel_display *display,
 				const struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -2386,7 +2377,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
 	clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
 	clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
 
-	return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
+	return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);
 }
 
 static int
@@ -2402,7 +2393,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 static int
 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct dpll clk_div = {};
 	int ret;
 
@@ -2412,7 +2403,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 	if (ret)
 		return ret;
 
-	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
+	crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
 						      &crtc_state->dpll_hw_state);
 
 	return 0;
@@ -2437,17 +2428,17 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
 
 	/* 1:1 mapping between ports and PLLs */
 	id = (enum intel_dpll_id) encoder->port;
-	pll = intel_get_shared_dpll_by_id(i915, id);
+	pll = intel_get_shared_dpll_by_id(display, id);
 
-	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
 		    crtc->base.base.id, crtc->base.name, pll->info->name);
 
 	intel_reference_shared_dpll(state, crtc,
@@ -2613,12 +2604,14 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
-ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
 {
-	return ((IS_ELKHARTLAKE(i915) &&
-		 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
-		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
-		 i915->display.dpll.ref_clks.nssc == 38400;
+	return ((display->platform.elkhartlake &&
+		 IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
+		 display->platform.tigerlake ||
+		 display->platform.alderlake_s ||
+		 display->platform.alderlake_p) &&
+		 display->dpll.ref_clks.nssc == 38400;
 }
 
 struct icl_combo_pll_params {
@@ -2765,7 +2758,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
 				    const struct intel_shared_dpll *pll,
 				    const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -2773,14 +2766,14 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
 	 * The PLL outputs multiple frequencies at the same time, selection is
 	 * made at DDI clock mux level.
 	 */
-	drm_WARN_ON(&i915->drm, 1);
+	drm_WARN_ON(display->drm, 1);
 
 	return 0;
 }
 
-static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
+static int icl_wrpll_ref_clock(struct intel_display *display)
 {
-	int ref_clock = i915->display.dpll.ref_clks.nssc;
+	int ref_clock = display->dpll.ref_clks.nssc;
 
 	/*
 	 * For ICL+, the spec states: if reference frequency is 38.4,
@@ -2796,8 +2789,8 @@ static int
 icl_calc_wrpll(struct intel_crtc_state *crtc_state,
 	       struct skl_wrpll_params *wrpll_params)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-	int ref_clock = icl_wrpll_ref_clock(i915);
+	struct intel_display *display = to_intel_display(crtc_state);
+	int ref_clock = icl_wrpll_ref_clock(display);
 	u32 afe_clock = crtc_state->port_clock * 5;
 	u32 dco_min = 7998000;
 	u32 dco_max = 10000000;
@@ -2836,12 +2829,12 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
 				      const struct intel_shared_dpll *pll,
 				      const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	int ref_clock = icl_wrpll_ref_clock(i915);
+	int ref_clock = icl_wrpll_ref_clock(display);
 	u32 dco_fraction;
 	u32 p0, p1, p2, dco_freq;
 
@@ -2887,25 +2880,25 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
 	dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
 		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
 
-	if (ehl_combo_pll_div_frac_wa_needed(i915))
+	if (ehl_combo_pll_div_frac_wa_needed(display))
 		dco_fraction *= 2;
 
 	dco_freq += (dco_fraction * ref_clock) / 0x8000;
 
-	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+	if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
 		return 0;
 
 	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
-static void icl_calc_dpll_state(struct drm_i915_private *i915,
+static void icl_calc_dpll_state(struct intel_display *display,
 				const struct skl_wrpll_params *pll_params,
 				struct intel_dpll_hw_state *dpll_hw_state)
 {
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	u32 dco_fraction = pll_params->dco_fraction;
 
-	if (ehl_combo_pll_div_frac_wa_needed(i915))
+	if (ehl_combo_pll_div_frac_wa_needed(display))
 		dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
 
 	hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
@@ -2916,13 +2909,13 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
 			    DPLL_CFGCR1_KDIV(pll_params->kdiv) |
 			    DPLL_CFGCR1_PDIV(pll_params->pdiv);
 
-	if (DISPLAY_VER(i915) >= 12)
+	if (DISPLAY_VER(display) >= 12)
 		hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
 	else
 		hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
 
-	if (i915->display.vbt.override_afc_startup)
-		hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
+	if (display->vbt.override_afc_startup)
+		hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);
 }
 
 static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -3209,7 +3202,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
 				   const struct intel_shared_dpll *pll,
 				   const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -3217,9 +3210,9 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
 	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
 	u64 tmp;
 
-	ref_clock = i915->display.dpll.ref_clks.nssc;
+	ref_clock = display->dpll.ref_clks.nssc;
 
-	if (DISPLAY_VER(i915) >= 12) {
+	if (DISPLAY_VER(display) >= 12) {
 		m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
 		m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
 		m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
@@ -3324,7 +3317,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state,
 static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct icl_port_dpll *port_dpll =
@@ -3341,12 +3334,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+	icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
 
 	/* this is mainly for the fastset check */
 	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
 
-	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL,
+	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
 							    &port_dpll->hw_state);
 
 	return 0;
@@ -3416,7 +3409,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_crtc_state *old_crtc_state =
@@ -3431,7 +3424,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+	icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
@@ -3445,7 +3438,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	else
 		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
 
-	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
+	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
 							 &port_dpll->hw_state);
 
 	return 0;
@@ -3549,11 +3542,10 @@ static void icl_put_dplls(struct intel_atomic_state *state,
 	}
 }
 
-static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
+static bool mg_pll_get_hw_state(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3561,46 +3553,46 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
 	bool ret = false;
 	u32 val;
 
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
 	wakeref = intel_display_power_get_if_enabled(display,
 						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, enable_reg);
+	val = intel_de_read(display, enable_reg);
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	hw_state->mg_refclkin_ctl = intel_de_read(i915,
+	hw_state->mg_refclkin_ctl = intel_de_read(display,
 						  MG_REFCLKIN_CTL(tc_port));
 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
 
 	hw_state->mg_clktop2_coreclkctl1 =
-		intel_de_read(i915, MG_CLKTOP2_CORECLKCTL1(tc_port));
+		intel_de_read(display, MG_CLKTOP2_CORECLKCTL1(tc_port));
 	hw_state->mg_clktop2_coreclkctl1 &=
 		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
 
 	hw_state->mg_clktop2_hsclkctl =
-		intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port));
+		intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));
 	hw_state->mg_clktop2_hsclkctl &=
 		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
 		MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
 
-	hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port));
-	hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port));
-	hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port));
-	hw_state->mg_pll_frac_lock = intel_de_read(i915,
+	hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));
+	hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));
+	hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));
+	hw_state->mg_pll_frac_lock = intel_de_read(display,
 						   MG_PLL_FRAC_LOCK(tc_port));
-	hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port));
+	hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));
 
-	hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port));
+	hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));
 	hw_state->mg_pll_tdc_coldst_bias =
-		intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+		intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
 
-	if (i915->display.dpll.ref_clks.nssc == 38400) {
+	if (display->dpll.ref_clks.nssc == 38400) {
 		hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
 		hw_state->mg_pll_bias_mask = 0;
 	} else {
@@ -3617,11 +3609,10 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool dkl_pll_get_hw_state(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3634,7 +3625,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll));
+	val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
 	if (!(val & PLL_ENABLE))
 		goto out;
 
@@ -3642,12 +3633,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 	 * All registers read here have the same HIP_INDEX_REG even though
 	 * they are on different building blocks
 	 */
-	hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915,
+	hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,
 						       DKL_REFCLKIN_CTL(tc_port));
 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
 
 	hw_state->mg_clktop2_hsclkctl =
-		intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+		intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
 	hw_state->mg_clktop2_hsclkctl &=
 		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
@@ -3655,32 +3646,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
 
 	hw_state->mg_clktop2_coreclkctl1 =
-		intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+		intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
 	hw_state->mg_clktop2_coreclkctl1 &=
 		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
 
-	hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port));
+	hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));
 	val = DKL_PLL_DIV0_MASK;
-	if (i915->display.vbt.override_afc_startup)
+	if (display->vbt.override_afc_startup)
 		val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
 	hw_state->mg_pll_div0 &= val;
 
-	hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+	hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
 	hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
 				  DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
 
-	hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+	hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
 	hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
 				 DKL_PLL_SSC_STEP_LEN_MASK |
 				 DKL_PLL_SSC_STEP_NUM_MASK |
 				 DKL_PLL_SSC_EN);
 
-	hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+	hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
 	hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
 				  DKL_PLL_BIAS_FBDIV_FRAC_MASK);
 
 	hw_state->mg_pll_tdc_coldst_bias =
-		intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+		intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
 	hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
 					     DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
 
@@ -3690,12 +3681,11 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool icl_pll_get_hw_state(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state,
 				 i915_reg_t enable_reg)
 {
-	struct intel_display *display = &i915->display;
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
 	intel_wakeref_t wakeref;
@@ -3707,41 +3697,41 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, enable_reg);
+	val = intel_de_read(display, enable_reg);
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	if (IS_ALDERLAKE_S(i915)) {
-		hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id));
-	} else if (IS_DG1(i915)) {
-		hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id));
-	} else if (IS_ROCKETLAKE(i915)) {
-		hw_state->cfgcr0 = intel_de_read(i915,
+	if (display->platform.alderlake_s) {
+		hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));
+	} else if (display->platform.dg1) {
+		hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));
+	} else if (display->platform.rocketlake) {
+		hw_state->cfgcr0 = intel_de_read(display,
 						 RKL_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915,
+		hw_state->cfgcr1 = intel_de_read(display,
 						 RKL_DPLL_CFGCR1(id));
-	} else if (DISPLAY_VER(i915) >= 12) {
-		hw_state->cfgcr0 = intel_de_read(i915,
+	} else if (DISPLAY_VER(display) >= 12) {
+		hw_state->cfgcr0 = intel_de_read(display,
 						 TGL_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915,
+		hw_state->cfgcr1 = intel_de_read(display,
 						 TGL_DPLL_CFGCR1(id));
-		if (i915->display.vbt.override_afc_startup) {
-			hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id));
+		if (display->vbt.override_afc_startup) {
+			hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));
 			hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
 		}
 	} else {
-		if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+		if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		    id == DPLL_ID_EHL_DPLL4) {
-			hw_state->cfgcr0 = intel_de_read(i915,
+			hw_state->cfgcr0 = intel_de_read(display,
 							 ICL_DPLL_CFGCR0(4));
-			hw_state->cfgcr1 = intel_de_read(i915,
+			hw_state->cfgcr1 = intel_de_read(display,
 							 ICL_DPLL_CFGCR1(4));
 		} else {
-			hw_state->cfgcr0 = intel_de_read(i915,
+			hw_state->cfgcr0 = intel_de_read(display,
 							 ICL_DPLL_CFGCR0(id));
-			hw_state->cfgcr1 = intel_de_read(i915,
+			hw_state->cfgcr1 = intel_de_read(display,
 							 ICL_DPLL_CFGCR1(id));
 		}
 	}
@@ -3752,44 +3742,44 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
+static bool combo_pll_get_hw_state(struct intel_display *display,
 				   struct intel_shared_dpll *pll,
 				   struct intel_dpll_hw_state *dpll_hw_state)
 {
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
-	return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
+	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
 }
 
-static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
+static bool tbt_pll_get_hw_state(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state)
 {
-	return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
+	return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
 }
 
-static void icl_dpll_write(struct drm_i915_private *i915,
+static void icl_dpll_write(struct intel_display *display,
 			   struct intel_shared_dpll *pll,
 			   const struct icl_dpll_hw_state *hw_state)
 {
 	const enum intel_dpll_id id = pll->info->id;
 	i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
 
-	if (IS_ALDERLAKE_S(i915)) {
+	if (display->platform.alderlake_s) {
 		cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
 		cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
-	} else if (IS_DG1(i915)) {
+	} else if (display->platform.dg1) {
 		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
 		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
-	} else if (IS_ROCKETLAKE(i915)) {
+	} else if (display->platform.rocketlake) {
 		cfgcr0_reg = RKL_DPLL_CFGCR0(id);
 		cfgcr1_reg = RKL_DPLL_CFGCR1(id);
-	} else if (DISPLAY_VER(i915) >= 12) {
+	} else if (DISPLAY_VER(display) >= 12) {
 		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
 		div0_reg = TGL_DPLL0_DIV0(id);
 	} else {
-		if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+		if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		    id == DPLL_ID_EHL_DPLL4) {
 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
@@ -3799,18 +3789,18 @@ static void icl_dpll_write(struct drm_i915_private *i915,
 		}
 	}
 
-	intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0);
-	intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1);
-	drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
+	intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);
+	intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);
+	drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&
 			 !i915_mmio_reg_valid(div0_reg));
-	if (i915->display.vbt.override_afc_startup &&
+	if (display->vbt.override_afc_startup &&
 	    i915_mmio_reg_valid(div0_reg))
-		intel_de_rmw(i915, div0_reg,
+		intel_de_rmw(display, div0_reg,
 			     TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
-	intel_de_posting_read(i915, cfgcr1_reg);
+	intel_de_posting_read(display, cfgcr1_reg);
 }
 
-static void icl_mg_pll_write(struct drm_i915_private *i915,
+static void icl_mg_pll_write(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     const struct icl_dpll_hw_state *hw_state)
 {
@@ -3822,38 +3812,38 @@ static void icl_mg_pll_write(struct drm_i915_private *i915,
 	 * during the calc/readout phase if the mask depends on some other HW
 	 * state like refclk, see icl_calc_mg_pll_state().
 	 */
-	intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port),
+	intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),
 		     MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
 
-	intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port),
+	intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),
 		     MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
 		     hw_state->mg_clktop2_coreclkctl1);
 
-	intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port),
+	intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),
 		     MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		     MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
 		     MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
 		     MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
 		     hw_state->mg_clktop2_hsclkctl);
 
-	intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
-	intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
-	intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
-	intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port),
+	intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
+	intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
+	intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
+	intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),
 		       hw_state->mg_pll_frac_lock);
-	intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
+	intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
 
-	intel_de_rmw(i915, MG_PLL_BIAS(tc_port),
+	intel_de_rmw(display, MG_PLL_BIAS(tc_port),
 		     hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
 
-	intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port),
+	intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),
 		     hw_state->mg_pll_tdc_coldst_bias_mask,
 		     hw_state->mg_pll_tdc_coldst_bias);
 
-	intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+	intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
 }
 
-static void dkl_pll_write(struct drm_i915_private *i915,
+static void dkl_pll_write(struct intel_display *display,
 			  struct intel_shared_dpll *pll,
 			  const struct icl_dpll_hw_state *hw_state)
 {
@@ -3865,90 +3855,90 @@ static void dkl_pll_write(struct drm_i915_private *i915,
 	 * though on different building block
 	 */
 	/* All the registers are RMW */
-	val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port));
+	val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
 	val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
 	val |= hw_state->mg_refclkin_ctl;
-	intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val);
+	intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+	val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
 	val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
 	val |= hw_state->mg_clktop2_coreclkctl1;
-	intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+	intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+	val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
 	val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
 		 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
 		 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
 	val |= hw_state->mg_clktop2_hsclkctl;
-	intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+	intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
 
 	val = DKL_PLL_DIV0_MASK;
-	if (i915->display.vbt.override_afc_startup)
+	if (display->vbt.override_afc_startup)
 		val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
-	intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val,
+	intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,
 			  hw_state->mg_pll_div0);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
 	val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
 		 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
 	val |= hw_state->mg_pll_div1;
-	intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
 	val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
 		 DKL_PLL_SSC_STEP_LEN_MASK |
 		 DKL_PLL_SSC_STEP_NUM_MASK |
 		 DKL_PLL_SSC_EN);
 	val |= hw_state->mg_pll_ssc;
-	intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
 	val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
 		 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
 	val |= hw_state->mg_pll_bias;
-	intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
 	val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
 		 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
 	val |= hw_state->mg_pll_tdc_coldst_bias;
-	intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
 
-	intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+	intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
 }
 
-static void icl_pll_power_enable(struct drm_i915_private *i915,
+static void icl_pll_power_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 i915_reg_t enable_reg)
 {
-	intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE);
+	intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
 
 	/*
 	 * The spec says we need to "wait" but it also says it should be
 	 * immediate.
 	 */
-	if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
-		drm_err(&i915->drm, "PLL %d Power not enabled\n",
+	if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
+		drm_err(display->drm, "PLL %d Power not enabled\n",
 			pll->info->id);
 }
 
-static void icl_pll_enable(struct drm_i915_private *i915,
+static void icl_pll_enable(struct intel_display *display,
 			   struct intel_shared_dpll *pll,
 			   i915_reg_t enable_reg)
 {
-	intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE);
+	intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
 
 	/* Timeout is actually 600us. */
-	if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
-		drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
+	if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
+		drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
 }
 
-static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
 {
 	u32 val;
 
-	if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
+	if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||
 	    pll->info->id != DPLL_ID_ICL_DPLL0)
 		return;
 	/*
@@ -3962,22 +3952,22 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
 	 * Instead of the usual place for workarounds we apply this one here,
 	 * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
 	 */
-	val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
-	val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
-	if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
-		drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
+	val = intel_de_read(display, TRANS_CMTG_CHICKEN);
+	val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
+	if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))
+		drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
 }
 
-static void combo_pll_enable(struct drm_i915_private *i915,
+static void combo_pll_enable(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
-	icl_pll_power_enable(i915, pll, enable_reg);
+	icl_pll_power_enable(display, pll, enable_reg);
 
-	icl_dpll_write(i915, pll, hw_state);
+	icl_dpll_write(display, pll, hw_state);
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3985,22 +3975,22 @@ static void combo_pll_enable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	icl_pll_enable(i915, pll, enable_reg);
+	icl_pll_enable(display, pll, enable_reg);
 
-	adlp_cmtg_clock_gating_wa(i915, pll);
+	adlp_cmtg_clock_gating_wa(display, pll);
 
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void tbt_pll_enable(struct drm_i915_private *i915,
+static void tbt_pll_enable(struct intel_display *display,
 			   struct intel_shared_dpll *pll,
 			   const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 
-	icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
+	icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
 
-	icl_dpll_write(i915, pll, hw_state);
+	icl_dpll_write(display, pll, hw_state);
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
@@ -4008,24 +3998,24 @@ static void tbt_pll_enable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	icl_pll_enable(i915, pll, TBT_PLL_ENABLE);
+	icl_pll_enable(display, pll, TBT_PLL_ENABLE);
 
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void mg_pll_enable(struct drm_i915_private *i915,
+static void mg_pll_enable(struct intel_display *display,
 			  struct intel_shared_dpll *pll,
 			  const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
-	icl_pll_power_enable(i915, pll, enable_reg);
+	icl_pll_power_enable(display, pll, enable_reg);
 
-	if (DISPLAY_VER(i915) >= 12)
-		dkl_pll_write(i915, pll, hw_state);
+	if (DISPLAY_VER(display) >= 12)
+		dkl_pll_write(display, pll, hw_state);
 	else
-		icl_mg_pll_write(i915, pll, hw_state);
+		icl_mg_pll_write(display, pll, hw_state);
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
@@ -4033,12 +4023,12 @@ static void mg_pll_enable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	icl_pll_enable(i915, pll, enable_reg);
+	icl_pll_enable(display, pll, enable_reg);
 
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void icl_pll_disable(struct drm_i915_private *i915,
+static void icl_pll_disable(struct intel_display *display,
 			    struct intel_shared_dpll *pll,
 			    i915_reg_t enable_reg)
 {
@@ -4050,45 +4040,45 @@ static void icl_pll_disable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
+	intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
 
 	/* Timeout is actually 1us. */
-	if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
-		drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
+	if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
+		drm_err(display->drm, "PLL %d locked\n", pll->info->id);
 
 	/* DVFS post sequence would be here. See the comment above. */
 
-	intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0);
+	intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);
 
 	/*
 	 * The spec says we need to "wait" but it also says it should be
 	 * immediate.
 	 */
-	if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
-		drm_err(&i915->drm, "PLL %d Power not disabled\n",
+	if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
+		drm_err(display->drm, "PLL %d Power not disabled\n",
 			pll->info->id);
 }
 
-static void combo_pll_disable(struct drm_i915_private *i915,
+static void combo_pll_disable(struct intel_display *display,
 			      struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
-	icl_pll_disable(i915, pll, enable_reg);
+	icl_pll_disable(display, pll, enable_reg);
 }
 
-static void tbt_pll_disable(struct drm_i915_private *i915,
+static void tbt_pll_disable(struct intel_display *display,
 			    struct intel_shared_dpll *pll)
 {
-	icl_pll_disable(i915, pll, TBT_PLL_ENABLE);
+	icl_pll_disable(display, pll, TBT_PLL_ENABLE);
 }
 
-static void mg_pll_disable(struct drm_i915_private *i915,
+static void mg_pll_disable(struct intel_display *display,
 			   struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
-	icl_pll_disable(i915, pll, enable_reg);
+	icl_pll_disable(display, pll, enable_reg);
 }
 
 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -4489,50 +4479,49 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
 
 /**
  * intel_dpll_get_freq - calculate the DPLL's output frequency
- * @i915: i915 device
+ * @display: intel_display device
  * @pll: DPLL for which to calculate the output frequency
  * @dpll_hw_state: DPLL state from which to calculate the output frequency
  *
  * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
  */
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
 			const struct intel_shared_dpll *pll,
 			const struct intel_dpll_hw_state *dpll_hw_state)
 {
-	if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
+	if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
 		return 0;
 
-	return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
+	return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
 }
 
 /**
  * intel_dpll_get_hw_state - readout the DPLL's hardware state
- * @i915: i915 device
+ * @display: intel_display device instance
  * @pll: DPLL for which to calculate the output frequency
  * @dpll_hw_state: DPLL's hardware state
  *
  * Read out @pll's hardware state into @dpll_hw_state.
  */
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *dpll_hw_state)
 {
-	return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
+	return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
 }
 
-static void readout_dpll_hw_state(struct drm_i915_private *i915,
+static void readout_dpll_hw_state(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
-	struct intel_display *display = &i915->display;
 	struct intel_crtc *crtc;
 
-	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
+	pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
 
 	if (pll->on && pll->info->power_domain)
 		pll->wakeref = intel_display_power_get(display, pll->info->power_domain);
 
 	pll->state.pipe_mask = 0;
-	for_each_intel_crtc(&i915->drm, crtc) {
+	for_each_intel_crtc(display->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
@@ -4541,7 +4530,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
 	}
 	pll->active_mask = pll->state.pipe_mask;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "%s hw state readout: pipe_mask 0x%x, on %i\n",
 		    pll->info->name, pll->state.pipe_mask, pll->on);
 }
@@ -4552,42 +4541,40 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
 		i915->display.dpll.mgr->update_ref_clks(i915);
 }
 
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+void intel_dpll_readout_hw_state(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
 	for_each_shared_dpll(display, pll, i)
-		readout_dpll_hw_state(i915, pll);
+		readout_dpll_hw_state(display, pll);
 }
 
-static void sanitize_dpll_state(struct drm_i915_private *i915,
+static void sanitize_dpll_state(struct intel_display *display,
 				struct intel_shared_dpll *pll)
 {
 	if (!pll->on)
 		return;
 
-	adlp_cmtg_clock_gating_wa(i915, pll);
+	adlp_cmtg_clock_gating_wa(display, pll);
 
 	if (pll->active_mask)
 		return;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "%s enabled but not in use, disabling\n",
 		    pll->info->name);
 
-	_intel_disable_shared_dpll(i915, pll);
+	_intel_disable_shared_dpll(display, pll);
 }
 
-void intel_dpll_sanitize_state(struct drm_i915_private *i915)
+void intel_dpll_sanitize_state(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
 	for_each_shared_dpll(display, pll, i)
-		sanitize_dpll_state(i915, pll);
+		sanitize_dpll_state(display, pll);
 }
 
 /**
@@ -4637,17 +4624,16 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
 }
 
 static void
-verify_single_dpll_state(struct drm_i915_private *i915,
+verify_single_dpll_state(struct intel_display *display,
 			 struct intel_shared_dpll *pll,
 			 struct intel_crtc *crtc,
 			 const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_display *display = &i915->display;
 	struct intel_dpll_hw_state dpll_hw_state = {};
 	u8 pipe_mask;
 	bool active;
 
-	active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
+	active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
 
 	if (!pll->info->always_on) {
 		INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
@@ -4703,14 +4689,13 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (new_crtc_state->shared_dpll)
-		verify_single_dpll_state(i915, new_crtc_state->shared_dpll,
+		verify_single_dpll_state(display, new_crtc_state->shared_dpll,
 					 crtc, new_crtc_state);
 
 	if (old_crtc_state->shared_dpll &&
@@ -4734,10 +4719,9 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
 void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_shared_dpll *pll;
 	int i;
 
 	for_each_shared_dpll(display, pll, i)
-		verify_single_dpll_state(i915, pll, NULL, NULL);
+		verify_single_dpll_state(display, pll, NULL, NULL);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 42379494f347..ebd0ed79d2b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,7 +390,7 @@ struct intel_shared_dpll {
 
 /* shared dpll functions */
 struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
 			    enum intel_dpll_id id);
 void assert_shared_dpll(struct drm_i915_private *i915,
 			struct intel_shared_dpll *pll,
@@ -413,10 +413,10 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
 void intel_update_active_dpll(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc,
 			      struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
 			const struct intel_shared_dpll *pll,
 			const struct intel_dpll_hw_state *dpll_hw_state);
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *dpll_hw_state);
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
@@ -424,8 +424,8 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_i915_private *i915);
 void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
-void intel_dpll_sanitize_state(struct drm_i915_private *i915);
+void intel_dpll_readout_hw_state(struct intel_display *display);
+void intel_dpll_sanitize_state(struct intel_display *display);
 
 void intel_dpll_dump_hw_state(struct intel_display *display,
 			      struct drm_printer *p,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 69373031c557..b4d1a18e9fd4 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -795,7 +795,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 			    pipe_name(pipe));
 	}
 
-	intel_dpll_readout_hw_state(i915);
+	intel_dpll_readout_hw_state(display);
 
 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 	for_each_intel_connector_iter(connector, &conn_iter) {
@@ -1014,7 +1014,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 
 	intel_sanitize_all_crtcs(i915, ctx);
 
-	intel_dpll_sanitize_state(i915);
+	intel_dpll_sanitize_state(display);
 
 	intel_wm_get_hw_state(i915);
 
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 8fa5a6334d10..e874a577b7d1 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -249,6 +249,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	i915_reg_t reg;
@@ -263,7 +264,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 
 	if (HAS_PCH_CPT(dev_priv)) {
 		reg = TRANS_CHICKEN2(pipe);
-		val = intel_de_read(dev_priv, reg);
+		val = intel_de_read(display, reg);
 		/*
 		 * Workaround: Set the timing override bit
 		 * before enabling the pch transcoder.
@@ -272,12 +273,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		/* Configure frame start delay to match the CPU */
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
 		val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
-		intel_de_write(dev_priv, reg, val);
+		intel_de_write(display, reg, val);
 	}
 
 	reg = PCH_TRANSCONF(pipe);
-	val = intel_de_read(dev_priv, reg);
-	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
+	val = intel_de_read(display, reg);
+	pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
 
 	if (HAS_PCH_IBX(dev_priv)) {
 		/* Configure frame start delay to match the CPU */
@@ -307,9 +308,9 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		val |= TRANS_INTERLACE_PROGRESSIVE;
 	}
 
-	intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
-	if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
-		drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
+	intel_de_write(display, reg, val | TRANS_ENABLE);
+	if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
+		drm_err(display->drm, "failed to enable transcoder %c\n",
 			pipe_name(pipe));
 }
 
@@ -383,15 +384,15 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 	if (HAS_PCH_CPT(dev_priv)) {
 		u32 sel;
 
-		temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+		temp = intel_de_read(display, PCH_DPLL_SEL);
 		temp |= TRANS_DPLL_ENABLE(pipe);
 		sel = TRANS_DPLLB_SEL(pipe);
 		if (crtc_state->shared_dpll ==
-		    intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
+		    intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
 			temp |= sel;
 		else
 			temp &= ~sel;
-		intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+		intel_de_write(display, PCH_DPLL_SEL, temp);
 	}
 
 	/*
@@ -420,11 +421,12 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 	    intel_crtc_has_dp_encoder(crtc_state)) {
 		const struct drm_display_mode *adjusted_mode =
 			&crtc_state->hw.adjusted_mode;
-		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
+		u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
+			   & TRANSCONF_BPC_MASK) >> 5;
 		i915_reg_t reg = TRANS_DP_CTL(pipe);
 		enum port port;
 
-		temp = intel_de_read(dev_priv, reg);
+		temp = intel_de_read(display, reg);
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
 			  TRANS_DP_VSYNC_ACTIVE_HIGH |
 			  TRANS_DP_HSYNC_ACTIVE_HIGH |
@@ -438,10 +440,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
 		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
-		drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
+		drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
 		temp |= TRANS_DP_PORT_SEL(port);
 
-		intel_de_write(dev_priv, reg, temp);
+		intel_de_write(display, reg, temp);
 	}
 
 	ilk_enable_pch_transcoder(crtc_state);
@@ -496,6 +498,7 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
 void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum pipe pipe = crtc->pipe;
@@ -503,12 +506,12 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 	bool pll_active;
 	u32 tmp;
 
-	if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
+	if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
 		return;
 
 	crtc_state->has_pch_encoder = true;
 
-	tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
+	tmp = intel_de_read(display, FDI_RX_CTL(pipe));
 	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
@@ -522,19 +525,19 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 		 */
 		pll_id = (enum intel_dpll_id) pipe;
 	} else {
-		tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+		tmp = intel_de_read(display, PCH_DPLL_SEL);
 		if (tmp & TRANS_DPLLB_SEL(pipe))
 			pll_id = DPLL_ID_PCH_PLL_B;
 		else
 			pll_id = DPLL_ID_PCH_PLL_A;
 	}
 
-	crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+	crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
 	pll = crtc_state->shared_dpll;
 
-	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+	pll_active = intel_dpll_get_hw_state(display, pll,
 					     &crtc_state->dpll_hw_state);
-	drm_WARN_ON(&dev_priv->drm, !pll_active);
+	drm_WARN_ON(display->drm, !pll_active);
 
 	tmp = crtc_state->dpll_hw_state.i9xx.dpll;
 	crtc_state->pixel_multiplier =
-- 
2.34.1

Re: [PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> We use intel_display for function hooks of shared_dpll_mgr and
> any function that gets called when we use for_each_shared_dpll.
> This also contains some opportunistic display->platform.xx changes
> all to reductate the use of drm_i915_private.
>
> --v2
> -rebase
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---


>  	/*
>  	 * Try to set up the PCH reference clock once all DPLLs
>  	 * that depend on it have been shut down.
>  	 */
> -	if (i915->display.dpll.pch_ssc_use & BIT(id))
> -		intel_init_pch_refclk(i915);
> +	if (display->dpll.pch_ssc_use & BIT(id))
> +		intel_init_pch_refclk(to_i915(display->drm));

For future reference:

- Please don't add inline uses of to_i915().

- There's too much going on in one patch.

Regardless, this is supposed to be non-functional, so I'll let it pass.


Reviewed-by: Jani Nikula <jani.nikula@intel.com>


-- 
Jani Nikula, Intel

[PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll

[Suraj Kandpal]

Use intel_display instead of drm_i915_private to assert pll enabled
and disabled and the corresponding changes needed to make that happen.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 22 +++++++++----------
 .../i915/display/intel_display_power_well.c   | 10 ++++-----
 drivers/gpu/drm/i915/display/intel_dpll.c     | 11 +++++-----
 drivers/gpu/drm/i915/display/intel_dpll.h     |  5 +++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  9 +++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      | 16 ++++++--------
 drivers/gpu/drm/i915/display/intel_fdi.h      |  7 +++---
 drivers/gpu/drm/i915/display/intel_lvds.c     |  7 +++---
 .../gpu/drm/i915/display/intel_pch_display.c  |  2 +-
 drivers/gpu/drm/i915/display/vlv_dsi_pll.c    | 12 +++++-----
 drivers/gpu/drm/i915/display/vlv_dsi_pll.h    | 10 +++++----
 12 files changed, 55 insertions(+), 58 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5f4b1d8eed3e..64a139676524 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -518,7 +518,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 	enum pipe pipe = crtc->pipe;
 	u32 val;
 
-	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
+	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
 
 	assert_planes_disabled(crtc);
 
@@ -529,15 +529,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 	 */
 	if (HAS_GMCH(dev_priv)) {
 		if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
-			assert_dsi_pll_enabled(dev_priv);
+			assert_dsi_pll_enabled(display);
 		else
-			assert_pll_enabled(dev_priv, pipe);
+			assert_pll_enabled(display, pipe);
 	} else {
 		if (new_crtc_state->has_pch_encoder) {
 			/* if driving the PCH, we need FDI enabled */
-			assert_fdi_rx_pll_enabled(dev_priv,
+			assert_fdi_rx_pll_enabled(display,
 						  intel_crtc_pch_transcoder(crtc));
-			assert_fdi_tx_pll_enabled(dev_priv,
+			assert_fdi_tx_pll_enabled(display,
 						  (enum pipe) cpu_transcoder);
 		}
 		/* FIXME: assert CPU port conditions for SNB+ */
@@ -545,21 +545,21 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 
 	/* Wa_22012358565:adl-p */
 	if (DISPLAY_VER(dev_priv) == 13)
-		intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
+		intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
 			     0, PIPE_ARB_USE_PROG_SLOTS);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
 		u32 set = 0;
 
-		if (DISPLAY_VER(dev_priv) == 14)
+		if (DISPLAY_VER(display) == 14)
 			set |= DP_FEC_BS_JITTER_WA;
 
 		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
 			     clear, set);
 	}
 
-	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
+	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
 	if (val & TRANSCONF_ENABLE) {
 		/* we keep both pipes enabled on 830 */
 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
@@ -567,16 +567,16 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 	}
 
 	/* Wa_1409098942:adlp+ */
-	if (DISPLAY_VER(dev_priv) >= 13 &&
+	if (DISPLAY_VER(display) >= 13 &&
 	    new_crtc_state->dsc.compression_enable) {
 		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
 		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
 				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
 	}
 
-	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+	intel_de_write(display, TRANSCONF(display, cpu_transcoder),
 		       val | TRANSCONF_ENABLE);
-	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
+	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
 
 	/*
 	 * Until the pipe starts PIPEDSL reads will return a stale value,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a31d1678dfc0..c2db076fd344 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1313,11 +1313,10 @@ static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,
 static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,
 					    struct i915_power_well *power_well)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	enum pipe pipe;
 
 	for_each_pipe(display, pipe)
-		assert_pll_disabled(dev_priv, pipe);
+		assert_pll_disabled(display, pipe);
 
 	/* Assert common reset */
 	intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);
@@ -1499,7 +1498,6 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
 static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
 					    struct i915_power_well *power_well)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
 	enum dpio_phy phy;
 
@@ -1509,11 +1507,11 @@ static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
 
 	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
 		phy = DPIO_PHY0;
-		assert_pll_disabled(dev_priv, PIPE_A);
-		assert_pll_disabled(dev_priv, PIPE_B);
+		assert_pll_disabled(display, PIPE_A);
+		assert_pll_disabled(display, PIPE_B);
 	} else {
 		phy = DPIO_PHY1;
-		assert_pll_disabled(dev_priv, PIPE_C);
+		assert_pll_disabled(display, PIPE_C);
 	}
 
 	display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 3256b1293f7f..cc19cd51ab4d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -2329,10 +2329,9 @@ void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
 }
 
 /* Only for pre-ILK configs */
-static void assert_pll(struct drm_i915_private *dev_priv,
+static void assert_pll(struct intel_display *display,
 		       enum pipe pipe, bool state)
 {
-	struct intel_display *display = &dev_priv->display;
 	bool cur_state;
 
 	cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
@@ -2341,12 +2340,12 @@ static void assert_pll(struct drm_i915_private *dev_priv,
 				 str_on_off(state), str_on_off(cur_state));
 }
 
-void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_pll_enabled(struct intel_display *display, enum pipe pipe)
 {
-	assert_pll(i915, pipe, true);
+	assert_pll(display, pipe, true);
 }
 
-void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_pll_disabled(struct intel_display *display, enum pipe pipe)
 {
-	assert_pll(i915, pipe, false);
+	assert_pll(display, pipe, false);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
index a86a79408af0..21d06cbd2ce7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_dpll_hw_state;
 enum pipe;
 
@@ -46,7 +47,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
 void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
 void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
 
-void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
+void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
+void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9976ac6322d1..104054a6df56 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -171,11 +171,10 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
 }
 
 /* For ILK+ */
-void assert_shared_dpll(struct drm_i915_private *i915,
+void assert_shared_dpll(struct intel_display *display,
 			struct intel_shared_dpll *pll,
 			bool state)
 {
-	struct intel_display *display = &i915->display;
 	bool cur_state;
 	struct intel_dpll_hw_state hw_state;
 
@@ -256,7 +255,6 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int pipe_mask = BIT(crtc->pipe);
 	unsigned int old_mask;
@@ -280,7 +278,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 
 	if (old_mask) {
 		drm_WARN_ON(display->drm, !pll->on);
-		assert_shared_dpll_enabled(i915, pll);
+		assert_shared_dpll_enabled(display, pll);
 		goto out;
 	}
 	drm_WARN_ON(display->drm, pll->on);
@@ -303,7 +301,6 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int pipe_mask = BIT(crtc->pipe);
 
@@ -325,7 +322,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 		    pll->info->name, pll->active_mask, pll->on,
 		    crtc->base.base.id, crtc->base.name);
 
-	assert_shared_dpll_enabled(i915, pll);
+	assert_shared_dpll_enabled(display, pll);
 	drm_WARN_ON(display->drm, !pll->on);
 
 	pll->active_mask &= ~pipe_mask;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ebd0ed79d2b5..b6f2cbce13e4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -392,7 +392,7 @@ struct intel_shared_dpll {
 struct intel_shared_dpll *
 intel_get_shared_dpll_by_id(struct intel_display *display,
 			    enum intel_dpll_id id);
-void assert_shared_dpll(struct drm_i915_private *i915,
+void assert_shared_dpll(struct intel_display *display,
 			struct intel_shared_dpll *pll,
 			bool state);
 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 3e8d6d8af780..9ebe80bfaab6 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -80,14 +80,13 @@ void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe)
 	assert_fdi_rx(i915, pipe, false);
 }
 
-void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
+void assert_fdi_tx_pll_enabled(struct intel_display *display,
 			       enum pipe pipe)
 {
-	struct intel_display *display = &i915->display;
 	bool cur_state;
 
 	/* ILK FDI PLL is always enabled */
-	if (IS_IRONLAKE(i915))
+	if (display->platform.ironlake)
 		return;
 
 	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -99,10 +98,9 @@ void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
 				 "FDI TX PLL assertion failure, should be active but is disabled\n");
 }
 
-static void assert_fdi_rx_pll(struct drm_i915_private *i915,
+static void assert_fdi_rx_pll(struct intel_display *display,
 			      enum pipe pipe, bool state)
 {
-	struct intel_display *display = &i915->display;
 	bool cur_state;
 
 	cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
@@ -111,14 +109,14 @@ static void assert_fdi_rx_pll(struct drm_i915_private *i915,
 				 str_on_off(state), str_on_off(cur_state));
 }
 
-void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)
 {
-	assert_fdi_rx_pll(i915, pipe, true);
+	assert_fdi_rx_pll(display, pipe, true);
 }
 
-void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
+void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)
 {
-	assert_fdi_rx_pll(i915, pipe, false);
+	assert_fdi_rx_pll(display, pipe, false);
 }
 
 void intel_fdi_link_train(struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 477ff0136934..b5be09efb36f 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -13,6 +13,7 @@ struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_encoder;
 struct intel_link_bw_limits;
 
@@ -41,8 +42,8 @@ void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe);
 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe);
 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe);
 void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
-void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
+void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);
+void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);
+void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index e86b3a86db82..6b05db2c10ba 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -240,6 +240,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -248,10 +249,10 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
 	u32 temp;
 
 	if (HAS_PCH_SPLIT(i915)) {
-		assert_fdi_rx_pll_disabled(i915, pipe);
-		assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
+		assert_fdi_rx_pll_disabled(display, pipe);
+		assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
 	} else {
-		assert_pll_disabled(i915, pipe);
+		assert_pll_disabled(display, pipe);
 	}
 
 	intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index e874a577b7d1..75ff5592312f 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -256,7 +256,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 	u32 val, pipeconf_val;
 
 	/* Make sure PCH DPLL is enabled */
-	assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
+	assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
 
 	/* FDI must be feeding us bits for PCH ports */
 	assert_fdi_tx_enabled(dev_priv, pipe);
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
index ac69eaece0fd..2ed47e7d1051 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
@@ -590,9 +590,9 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 	intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
 }
 
-static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
+static void assert_dsi_pll(struct intel_display *display, bool state)
 {
-	struct intel_display *display = &i915->display;
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	bool cur_state;
 
 	vlv_cck_get(i915);
@@ -604,12 +604,12 @@ static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
 				 str_on_off(state), str_on_off(cur_state));
 }
 
-void assert_dsi_pll_enabled(struct drm_i915_private *i915)
+void assert_dsi_pll_enabled(struct intel_display *display)
 {
-	assert_dsi_pll(i915, true);
+	assert_dsi_pll(display, true);
 }
 
-void assert_dsi_pll_disabled(struct drm_i915_private *i915)
+void assert_dsi_pll_disabled(struct intel_display *display)
 {
-	assert_dsi_pll(i915, false);
+	assert_dsi_pll(display, false);
 }
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
index fbe5113dbeb9..a032cc2a2524 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
@@ -11,6 +11,7 @@
 enum port;
 struct drm_i915_private;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_encoder;
 
 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
@@ -33,13 +34,14 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
 
 #ifdef I915
-void assert_dsi_pll_enabled(struct drm_i915_private *i915);
-void assert_dsi_pll_disabled(struct drm_i915_private *i915);
+void assert_dsi_pll_enabled(struct intel_display *display);
+void assert_dsi_pll_disabled(struct intel_display *display);
 #else
-static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915)
+static inline void assert_dsi_pll_enabled(struct intel_display *display)
 {
 }
-static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915)
+
+static inline void assert_dsi_pll_disabled(struct intel_display *display)
 {
 }
 #endif
-- 
2.34.1

Re: [PATCH 6/9] drm/i915/dpll: Use intel_display for asserting pll

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use intel_display instead of drm_i915_private to assert pll enabled
> and disabled and the corresponding changes needed to make that happen.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 22 +++++++++----------
>  .../i915/display/intel_display_power_well.c   | 10 ++++-----
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 11 +++++-----
>  drivers/gpu/drm/i915/display/intel_dpll.h     |  5 +++--
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  9 +++-----
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c      | 16 ++++++--------
>  drivers/gpu/drm/i915/display/intel_fdi.h      |  7 +++---
>  drivers/gpu/drm/i915/display/intel_lvds.c     |  7 +++---
>  .../gpu/drm/i915/display/intel_pch_display.c  |  2 +-
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c    | 12 +++++-----
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.h    | 10 +++++----
>  12 files changed, 55 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5f4b1d8eed3e..64a139676524 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -518,7 +518,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  	u32 val;
>  
> -	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
> +	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
>  
>  	assert_planes_disabled(crtc);
>  
> @@ -529,15 +529,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  	 */
>  	if (HAS_GMCH(dev_priv)) {
>  		if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
> -			assert_dsi_pll_enabled(dev_priv);
> +			assert_dsi_pll_enabled(display);
>  		else
> -			assert_pll_enabled(dev_priv, pipe);
> +			assert_pll_enabled(display, pipe);
>  	} else {
>  		if (new_crtc_state->has_pch_encoder) {
>  			/* if driving the PCH, we need FDI enabled */
> -			assert_fdi_rx_pll_enabled(dev_priv,
> +			assert_fdi_rx_pll_enabled(display,
>  						  intel_crtc_pch_transcoder(crtc));
> -			assert_fdi_tx_pll_enabled(dev_priv,
> +			assert_fdi_tx_pll_enabled(display,
>  						  (enum pipe) cpu_transcoder);
>  		}
>  		/* FIXME: assert CPU port conditions for SNB+ */
> @@ -545,21 +545,21 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  
>  	/* Wa_22012358565:adl-p */
>  	if (DISPLAY_VER(dev_priv) == 13)
> -		intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe),
> +		intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
>  			     0, PIPE_ARB_USE_PROG_SLOTS);
>  
>  	if (DISPLAY_VER(dev_priv) >= 14) {
>  		u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
>  		u32 set = 0;
>  
> -		if (DISPLAY_VER(dev_priv) == 14)
> +		if (DISPLAY_VER(display) == 14)
>  			set |= DP_FEC_BS_JITTER_WA;
>  
>  		intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
>  			     clear, set);
>  	}
>  
> -	val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
> +	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
>  	if (val & TRANSCONF_ENABLE) {
>  		/* we keep both pipes enabled on 830 */
>  		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
> @@ -567,16 +567,16 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
>  	}
>  
>  	/* Wa_1409098942:adlp+ */
> -	if (DISPLAY_VER(dev_priv) >= 13 &&
> +	if (DISPLAY_VER(display) >= 13 &&
>  	    new_crtc_state->dsc.compression_enable) {
>  		val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
>  		val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
>  				      TRANSCONF_PIXEL_COUNT_SCALING_X4);
>  	}
>  
> -	intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
> +	intel_de_write(display, TRANSCONF(display, cpu_transcoder),
>  		       val | TRANSCONF_ENABLE);
> -	intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder));
> +	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
>  
>  	/*
>  	 * Until the pipe starts PIPEDSL reads will return a stale value,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index a31d1678dfc0..c2db076fd344 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1313,11 +1313,10 @@ static void vlv_dpio_cmn_power_well_enable(struct intel_display *display,
>  static void vlv_dpio_cmn_power_well_disable(struct intel_display *display,
>  					    struct i915_power_well *power_well)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	enum pipe pipe;
>  
>  	for_each_pipe(display, pipe)
> -		assert_pll_disabled(dev_priv, pipe);
> +		assert_pll_disabled(display, pipe);
>  
>  	/* Assert common reset */
>  	intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0);
> @@ -1499,7 +1498,6 @@ static void chv_dpio_cmn_power_well_enable(struct intel_display *display,
>  static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
>  					    struct i915_power_well *power_well)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(display->drm);
>  	enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
>  	enum dpio_phy phy;
>  
> @@ -1509,11 +1507,11 @@ static void chv_dpio_cmn_power_well_disable(struct intel_display *display,
>  
>  	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
>  		phy = DPIO_PHY0;
> -		assert_pll_disabled(dev_priv, PIPE_A);
> -		assert_pll_disabled(dev_priv, PIPE_B);
> +		assert_pll_disabled(display, PIPE_A);
> +		assert_pll_disabled(display, PIPE_B);
>  	} else {
>  		phy = DPIO_PHY1;
> -		assert_pll_disabled(dev_priv, PIPE_C);
> +		assert_pll_disabled(display, PIPE_C);
>  	}
>  
>  	display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 3256b1293f7f..cc19cd51ab4d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -2329,10 +2329,9 @@ void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
>  }
>  
>  /* Only for pre-ILK configs */
> -static void assert_pll(struct drm_i915_private *dev_priv,
> +static void assert_pll(struct intel_display *display,
>  		       enum pipe pipe, bool state)
>  {
> -	struct intel_display *display = &dev_priv->display;
>  	bool cur_state;
>  
>  	cur_state = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE;
> @@ -2341,12 +2340,12 @@ static void assert_pll(struct drm_i915_private *dev_priv,
>  				 str_on_off(state), str_on_off(cur_state));
>  }
>  
> -void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_pll_enabled(struct intel_display *display, enum pipe pipe)
>  {
> -	assert_pll(i915, pipe, true);
> +	assert_pll(display, pipe, true);
>  }
>  
> -void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_pll_disabled(struct intel_display *display, enum pipe pipe)
>  {
> -	assert_pll(i915, pipe, false);
> +	assert_pll(display, pipe, false);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.h b/drivers/gpu/drm/i915/display/intel_dpll.h
> index a86a79408af0..21d06cbd2ce7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.h
> @@ -13,6 +13,7 @@ struct drm_i915_private;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  struct intel_crtc_state;
> +struct intel_display;
>  struct intel_dpll_hw_state;
>  enum pipe;
>  
> @@ -46,7 +47,7 @@ void i9xx_crtc_clock_get(struct intel_crtc_state *crtc_state);
>  void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state);
>  void chv_crtc_clock_get(struct intel_crtc_state *crtc_state);
>  
> -void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
> +void assert_pll_enabled(struct intel_display *display, enum pipe pipe);
> +void assert_pll_disabled(struct intel_display *display, enum pipe pipe);
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9976ac6322d1..104054a6df56 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -171,11 +171,10 @@ intel_get_shared_dpll_by_id(struct intel_display *display,
>  }
>  
>  /* For ILK+ */
> -void assert_shared_dpll(struct drm_i915_private *i915,
> +void assert_shared_dpll(struct intel_display *display,
>  			struct intel_shared_dpll *pll,
>  			bool state)
>  {
> -	struct intel_display *display = &i915->display;
>  	bool cur_state;
>  	struct intel_dpll_hw_state hw_state;
>  
> @@ -256,7 +255,6 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	unsigned int pipe_mask = BIT(crtc->pipe);
>  	unsigned int old_mask;
> @@ -280,7 +278,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  
>  	if (old_mask) {
>  		drm_WARN_ON(display->drm, !pll->on);
> -		assert_shared_dpll_enabled(i915, pll);
> +		assert_shared_dpll_enabled(display, pll);
>  		goto out;
>  	}
>  	drm_WARN_ON(display->drm, pll->on);
> @@ -303,7 +301,6 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>  	unsigned int pipe_mask = BIT(crtc->pipe);
>  
> @@ -325,7 +322,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
>  		    pll->info->name, pll->active_mask, pll->on,
>  		    crtc->base.base.id, crtc->base.name);
>  
> -	assert_shared_dpll_enabled(i915, pll);
> +	assert_shared_dpll_enabled(display, pll);
>  	drm_WARN_ON(display->drm, !pll->on);
>  
>  	pll->active_mask &= ~pipe_mask;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index ebd0ed79d2b5..b6f2cbce13e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -392,7 +392,7 @@ struct intel_shared_dpll {
>  struct intel_shared_dpll *
>  intel_get_shared_dpll_by_id(struct intel_display *display,
>  			    enum intel_dpll_id id);
> -void assert_shared_dpll(struct drm_i915_private *i915,
> +void assert_shared_dpll(struct intel_display *display,
>  			struct intel_shared_dpll *pll,
>  			bool state);
>  #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 3e8d6d8af780..9ebe80bfaab6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -80,14 +80,13 @@ void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe)
>  	assert_fdi_rx(i915, pipe, false);
>  }
>  
> -void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
> +void assert_fdi_tx_pll_enabled(struct intel_display *display,
>  			       enum pipe pipe)
>  {
> -	struct intel_display *display = &i915->display;
>  	bool cur_state;
>  
>  	/* ILK FDI PLL is always enabled */
> -	if (IS_IRONLAKE(i915))
> +	if (display->platform.ironlake)
>  		return;
>  
>  	/* On Haswell, DDI ports are responsible for the FDI PLL setup */
> @@ -99,10 +98,9 @@ void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915,
>  				 "FDI TX PLL assertion failure, should be active but is disabled\n");
>  }
>  
> -static void assert_fdi_rx_pll(struct drm_i915_private *i915,
> +static void assert_fdi_rx_pll(struct intel_display *display,
>  			      enum pipe pipe, bool state)
>  {
> -	struct intel_display *display = &i915->display;
>  	bool cur_state;
>  
>  	cur_state = intel_de_read(display, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE;
> @@ -111,14 +109,14 @@ static void assert_fdi_rx_pll(struct drm_i915_private *i915,
>  				 str_on_off(state), str_on_off(cur_state));
>  }
>  
> -void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe)
>  {
> -	assert_fdi_rx_pll(i915, pipe, true);
> +	assert_fdi_rx_pll(display, pipe, true);
>  }
>  
> -void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe)
> +void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe)
>  {
> -	assert_fdi_rx_pll(i915, pipe, false);
> +	assert_fdi_rx_pll(display, pipe, false);
>  }
>  
>  void intel_fdi_link_train(struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
> index 477ff0136934..b5be09efb36f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> @@ -13,6 +13,7 @@ struct drm_i915_private;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  struct intel_crtc_state;
> +struct intel_display;
>  struct intel_encoder;
>  struct intel_link_bw_limits;
>  
> @@ -41,8 +42,8 @@ void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe);
>  void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe);
>  void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe);
>  void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
> -void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
> +void assert_fdi_tx_pll_enabled(struct intel_display *display, enum pipe pipe);
> +void assert_fdi_rx_pll_enabled(struct intel_display *display, enum pipe pipe);
> +void assert_fdi_rx_pll_disabled(struct intel_display *display, enum pipe pipe);
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index e86b3a86db82..6b05db2c10ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -240,6 +240,7 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
>  				  const struct intel_crtc_state *crtc_state,
>  				  const struct drm_connector_state *conn_state)
>  {
> +	struct intel_display *display = to_intel_display(state);
>  	struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
>  	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -248,10 +249,10 @@ static void intel_pre_enable_lvds(struct intel_atomic_state *state,
>  	u32 temp;
>  
>  	if (HAS_PCH_SPLIT(i915)) {
> -		assert_fdi_rx_pll_disabled(i915, pipe);
> -		assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
> +		assert_fdi_rx_pll_disabled(display, pipe);
> +		assert_shared_dpll_disabled(display, crtc_state->shared_dpll);
>  	} else {
> -		assert_pll_disabled(i915, pipe);
> +		assert_pll_disabled(display, pipe);
>  	}
>  
>  	intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index e874a577b7d1..75ff5592312f 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -256,7 +256,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  	u32 val, pipeconf_val;
>  
>  	/* Make sure PCH DPLL is enabled */
> -	assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll);
> +	assert_shared_dpll_enabled(display, crtc_state->shared_dpll);
>  
>  	/* FDI must be feeding us bits for PCH ports */
>  	assert_fdi_tx_enabled(dev_priv, pipe);
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> index ac69eaece0fd..2ed47e7d1051 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c
> @@ -590,9 +590,9 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
>  	intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP);
>  }
>  
> -static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
> +static void assert_dsi_pll(struct intel_display *display, bool state)
>  {
> -	struct intel_display *display = &i915->display;
> +	struct drm_i915_private *i915 = to_i915(display->drm);
>  	bool cur_state;
>  
>  	vlv_cck_get(i915);
> @@ -604,12 +604,12 @@ static void assert_dsi_pll(struct drm_i915_private *i915, bool state)
>  				 str_on_off(state), str_on_off(cur_state));
>  }
>  
> -void assert_dsi_pll_enabled(struct drm_i915_private *i915)
> +void assert_dsi_pll_enabled(struct intel_display *display)
>  {
> -	assert_dsi_pll(i915, true);
> +	assert_dsi_pll(display, true);
>  }
>  
> -void assert_dsi_pll_disabled(struct drm_i915_private *i915)
> +void assert_dsi_pll_disabled(struct intel_display *display)
>  {
> -	assert_dsi_pll(i915, false);
> +	assert_dsi_pll(display, false);
>  }
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
> index fbe5113dbeb9..a032cc2a2524 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.h
> @@ -11,6 +11,7 @@
>  enum port;
>  struct drm_i915_private;
>  struct intel_crtc_state;
> +struct intel_display;
>  struct intel_encoder;
>  
>  int vlv_dsi_pll_compute(struct intel_encoder *encoder,
> @@ -33,13 +34,14 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
>  void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
>  
>  #ifdef I915
> -void assert_dsi_pll_enabled(struct drm_i915_private *i915);
> -void assert_dsi_pll_disabled(struct drm_i915_private *i915);
> +void assert_dsi_pll_enabled(struct intel_display *display);
> +void assert_dsi_pll_disabled(struct intel_display *display);
>  #else
> -static inline void assert_dsi_pll_enabled(struct drm_i915_private *i915)
> +static inline void assert_dsi_pll_enabled(struct intel_display *display)
>  {
>  }
> -static inline void assert_dsi_pll_disabled(struct drm_i915_private *i915)
> +
> +static inline void assert_dsi_pll_disabled(struct intel_display *display)
>  {
>  }
>  #endif

-- 
Jani Nikula, Intel

[PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook

[Suraj Kandpal]

Use intel_display instead of drm_i915_private for update_refclk hook.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_driver.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +++++++++----------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  2 +-
 3 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index d448672fdfa4..978f530c810e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -453,7 +453,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
 
 	intel_update_czclk(i915);
 	intel_display_driver_init_hw(display);
-	intel_dpll_update_ref_clks(i915);
+	intel_dpll_update_ref_clks(display);
 
 	if (display->cdclk.max_cdclk_freq == 0)
 		intel_update_max_cdclk(display);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 104054a6df56..f94da1ffc8ce 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -109,7 +109,7 @@ struct intel_dpll_mgr {
 	void (*update_active_dpll)(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc,
 				   struct intel_encoder *encoder);
-	void (*update_ref_clks)(struct drm_i915_private *i915);
+	void (*update_ref_clks)(struct intel_display *display);
 	void (*dump_hw_state)(struct drm_printer *p,
 			      const struct intel_dpll_hw_state *dpll_hw_state);
 	bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
@@ -1240,14 +1240,14 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
 	return 0;
 }
 
-static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void hsw_update_dpll_ref_clks(struct intel_display *display)
 {
-	i915->display.dpll.ref_clks.ssc = 135000;
+	display->dpll.ref_clks.ssc = 135000;
 	/* Non-SSC is only used on non-ULT HSW. */
-	if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
-		i915->display.dpll.ref_clks.nssc = 24000;
+	if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
+		display->dpll.ref_clks.nssc = 24000;
 	else
-		i915->display.dpll.ref_clks.nssc = 135000;
+		display->dpll.ref_clks.nssc = 135000;
 }
 
 static void hsw_dump_hw_state(struct drm_printer *p,
@@ -1977,10 +1977,10 @@ static int skl_ddi_pll_get_freq(struct intel_display *display,
 		return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
 }
 
-static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void skl_update_dpll_ref_clks(struct intel_display *display)
 {
 	/* No SSC ref */
-	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
+	display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
 }
 
 static void skl_dump_hw_state(struct drm_printer *p,
@@ -2446,10 +2446,10 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
 	return 0;
 }
 
-static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void bxt_update_dpll_ref_clks(struct intel_display *display)
 {
-	i915->display.dpll.ref_clks.ssc = 100000;
-	i915->display.dpll.ref_clks.nssc = 100000;
+	display->dpll.ref_clks.ssc = 100000;
+	display->dpll.ref_clks.nssc = 100000;
 	/* DSI non-SSC ref 19.2MHz */
 }
 
@@ -4078,10 +4078,10 @@ static void mg_pll_disable(struct intel_display *display,
 	icl_pll_disable(display, pll, enable_reg);
 }
 
-static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
+static void icl_update_dpll_ref_clks(struct intel_display *display)
 {
 	/* No SSC ref */
-	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
+	display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
 }
 
 static void icl_dump_hw_state(struct drm_printer *p,
@@ -4532,10 +4532,10 @@ static void readout_dpll_hw_state(struct intel_display *display,
 		    pll->info->name, pll->state.pipe_mask, pll->on);
 }
 
-void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
+void intel_dpll_update_ref_clks(struct intel_display *display)
 {
-	if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
-		i915->display.dpll.mgr->update_ref_clks(i915);
+	if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)
+		display->dpll.mgr->update_ref_clks(display);
 }
 
 void intel_dpll_readout_hw_state(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index b6f2cbce13e4..3d988f17f31d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -423,7 +423,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_i915_private *i915);
-void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
+void intel_dpll_update_ref_clks(struct intel_display *display);
 void intel_dpll_readout_hw_state(struct intel_display *display);
 void intel_dpll_sanitize_state(struct intel_display *display);
 
-- 
2.34.1

Re: [PATCH 7/9] drm/i915/dpll: Use intel_display for update_refclk hook

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use intel_display instead of drm_i915_private for update_refclk hook.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  .../drm/i915/display/intel_display_driver.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 32 +++++++++----------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  2 +-
>  3 files changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index d448672fdfa4..978f530c810e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -453,7 +453,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
>  
>  	intel_update_czclk(i915);
>  	intel_display_driver_init_hw(display);
> -	intel_dpll_update_ref_clks(i915);
> +	intel_dpll_update_ref_clks(display);
>  
>  	if (display->cdclk.max_cdclk_freq == 0)
>  		intel_update_max_cdclk(display);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 104054a6df56..f94da1ffc8ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -109,7 +109,7 @@ struct intel_dpll_mgr {
>  	void (*update_active_dpll)(struct intel_atomic_state *state,
>  				   struct intel_crtc *crtc,
>  				   struct intel_encoder *encoder);
> -	void (*update_ref_clks)(struct drm_i915_private *i915);
> +	void (*update_ref_clks)(struct intel_display *display);
>  	void (*dump_hw_state)(struct drm_printer *p,
>  			      const struct intel_dpll_hw_state *dpll_hw_state);
>  	bool (*compare_hw_state)(const struct intel_dpll_hw_state *a,
> @@ -1240,14 +1240,14 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> -static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void hsw_update_dpll_ref_clks(struct intel_display *display)
>  {
> -	i915->display.dpll.ref_clks.ssc = 135000;
> +	display->dpll.ref_clks.ssc = 135000;
>  	/* Non-SSC is only used on non-ULT HSW. */
> -	if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> -		i915->display.dpll.ref_clks.nssc = 24000;
> +	if (intel_de_read(display, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
> +		display->dpll.ref_clks.nssc = 24000;
>  	else
> -		i915->display.dpll.ref_clks.nssc = 135000;
> +		display->dpll.ref_clks.nssc = 135000;
>  }
>  
>  static void hsw_dump_hw_state(struct drm_printer *p,
> @@ -1977,10 +1977,10 @@ static int skl_ddi_pll_get_freq(struct intel_display *display,
>  		return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
>  }
>  
> -static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void skl_update_dpll_ref_clks(struct intel_display *display)
>  {
>  	/* No SSC ref */
> -	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
> +	display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
>  }
>  
>  static void skl_dump_hw_state(struct drm_printer *p,
> @@ -2446,10 +2446,10 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> -static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void bxt_update_dpll_ref_clks(struct intel_display *display)
>  {
> -	i915->display.dpll.ref_clks.ssc = 100000;
> -	i915->display.dpll.ref_clks.nssc = 100000;
> +	display->dpll.ref_clks.ssc = 100000;
> +	display->dpll.ref_clks.nssc = 100000;
>  	/* DSI non-SSC ref 19.2MHz */
>  }
>  
> @@ -4078,10 +4078,10 @@ static void mg_pll_disable(struct intel_display *display,
>  	icl_pll_disable(display, pll, enable_reg);
>  }
>  
> -static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
> +static void icl_update_dpll_ref_clks(struct intel_display *display)
>  {
>  	/* No SSC ref */
> -	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
> +	display->dpll.ref_clks.nssc = display->cdclk.hw.ref;
>  }
>  
>  static void icl_dump_hw_state(struct drm_printer *p,
> @@ -4532,10 +4532,10 @@ static void readout_dpll_hw_state(struct intel_display *display,
>  		    pll->info->name, pll->state.pipe_mask, pll->on);
>  }
>  
> -void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
> +void intel_dpll_update_ref_clks(struct intel_display *display)
>  {
> -	if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
> -		i915->display.dpll.mgr->update_ref_clks(i915);
> +	if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)
> +		display->dpll.mgr->update_ref_clks(display);
>  }
>  
>  void intel_dpll_readout_hw_state(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index b6f2cbce13e4..3d988f17f31d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -423,7 +423,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
>  void intel_shared_dpll_init(struct drm_i915_private *i915);
> -void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
> +void intel_dpll_update_ref_clks(struct intel_display *display);
>  void intel_dpll_readout_hw_state(struct intel_display *display);
>  void intel_dpll_sanitize_state(struct intel_display *display);

-- 
Jani Nikula, Intel

[PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init

[Suraj Kandpal]

Use intel_display as an argument for intel_shared_dpll_init() and
replace drm_i915_private in function wherever possible.
While at it prefer using display->platform.xx over IS_PLATFORM.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../drm/i915/display/intel_display_driver.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49 ++++++++++---------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +-
 3 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 978f530c810e..852f1129a058 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
 	}
 
 	intel_plane_possible_crtcs_init(display);
-	intel_shared_dpll_init(i915);
+	intel_shared_dpll_init(display);
 	intel_fdi_pll_freq_update(i915);
 
 	intel_update_czclk(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f94da1ffc8ce..26b6b9372fa3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
 {
 	const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
-	enum dpio_phy phy;
-	enum dpio_channel ch;
+	enum dpio_phy phy = DPIO_PHY0;
+	enum dpio_channel ch = DPIO_CH0;
 	u32 temp;
 
 	bxt_port_to_phy_channel(display, port, &phy, &ch);
@@ -4302,40 +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
 
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
- * @i915: i915 device
+ * @display: intel_display device
  *
- * Initialize shared DPLLs for @i915.
+ * Initialize shared DPLLs for @display.
  */
-void intel_shared_dpll_init(struct drm_i915_private *i915)
+void intel_shared_dpll_init(struct intel_display *display)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	const struct intel_dpll_mgr *dpll_mgr = NULL;
 	const struct dpll_info *dpll_info;
 	int i;
 
-	mutex_init(&i915->display.dpll.lock);
+	mutex_init(&display->dpll.lock);
 
-	if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
+	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
 		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
 		dpll_mgr = NULL;
-	else if (IS_ALDERLAKE_P(i915))
+	else if (display->platform.alderlake_p)
 		dpll_mgr = &adlp_pll_mgr;
-	else if (IS_ALDERLAKE_S(i915))
+	else if (display->platform.alderlake_s)
 		dpll_mgr = &adls_pll_mgr;
-	else if (IS_DG1(i915))
+	else if (display->platform.dg1)
 		dpll_mgr = &dg1_pll_mgr;
-	else if (IS_ROCKETLAKE(i915))
+	else if (display->platform.rocketlake)
 		dpll_mgr = &rkl_pll_mgr;
-	else if (DISPLAY_VER(i915) >= 12)
+	else if (DISPLAY_VER(display) >= 12)
 		dpll_mgr = &tgl_pll_mgr;
-	else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
+	else if (display->platform.jasperlake || display->platform.elkhartlake)
 		dpll_mgr = &ehl_pll_mgr;
-	else if (DISPLAY_VER(i915) >= 11)
+	else if (DISPLAY_VER(display) >= 11)
 		dpll_mgr = &icl_pll_mgr;
-	else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
+	else if (display->platform.geminilake || display->platform.broxton)
 		dpll_mgr = &bxt_pll_mgr;
-	else if (DISPLAY_VER(i915) == 9)
+	else if (DISPLAY_VER(display) == 9)
 		dpll_mgr = &skl_pll_mgr;
-	else if (HAS_DDI(i915))
+	else if (HAS_DDI(display))
 		dpll_mgr = &hsw_pll_mgr;
 	else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
 		dpll_mgr = &pch_pll_mgr;
@@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct drm_i915_private *i915)
 	dpll_info = dpll_mgr->dpll_info;
 
 	for (i = 0; dpll_info[i].name; i++) {
-		if (drm_WARN_ON(&i915->drm,
-				i >= ARRAY_SIZE(i915->display.dpll.shared_dplls)))
+		if (drm_WARN_ON(display->drm,
+				i >= ARRAY_SIZE(display->dpll.shared_dplls)))
 			break;
 
 		/* must fit into unsigned long bitmask on 32bit */
-		if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
+		if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
 			break;
 
-		i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
-		i915->display.dpll.shared_dplls[i].index = i;
+		display->dpll.shared_dplls[i].info = &dpll_info[i];
+		display->dpll.shared_dplls[i].index = i;
 	}
 
-	i915->display.dpll.mgr = dpll_mgr;
-	i915->display.dpll.num_shared_dpll = i;
+	display->dpll.mgr = dpll_mgr;
+	display->dpll.num_shared_dpll = i;
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 3d988f17f31d..caffb084830c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -35,7 +35,6 @@
 		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
 
 enum tc_port;
-struct drm_i915_private;
 struct drm_printer;
 struct intel_atomic_state;
 struct intel_crtc;
@@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
-void intel_shared_dpll_init(struct drm_i915_private *i915);
+void intel_shared_dpll_init(struct intel_display *display);
 void intel_dpll_update_ref_clks(struct intel_display *display);
 void intel_dpll_readout_hw_state(struct intel_display *display);
 void intel_dpll_sanitize_state(struct intel_display *display);
-- 
2.34.1

Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Use intel_display as an argument for intel_shared_dpll_init() and
> replace drm_i915_private in function wherever possible.
> While at it prefer using display->platform.xx over IS_PLATFORM.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  .../drm/i915/display/intel_display_driver.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49 ++++++++++---------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  3 +-
>  3 files changed, 27 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 978f530c810e..852f1129a058 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct intel_display *display)
>  	}
>  
>  	intel_plane_possible_crtcs_init(display);
> -	intel_shared_dpll_init(i915);
> +	intel_shared_dpll_init(display);
>  	intel_fdi_pll_freq_update(i915);
>  
>  	intel_update_czclk(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f94da1ffc8ce..26b6b9372fa3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
>  {
>  	const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
>  	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> -	enum dpio_phy phy;
> -	enum dpio_channel ch;
> +	enum dpio_phy phy = DPIO_PHY0;
> +	enum dpio_channel ch = DPIO_CH0;

Unrelated change, please drop.

With that fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  	u32 temp;
>  
>  	bxt_port_to_phy_channel(display, port, &phy, &ch);
> @@ -4302,40 +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>  
>  /**
>   * intel_shared_dpll_init - Initialize shared DPLLs
> - * @i915: i915 device
> + * @display: intel_display device
>   *
> - * Initialize shared DPLLs for @i915.
> + * Initialize shared DPLLs for @display.
>   */
> -void intel_shared_dpll_init(struct drm_i915_private *i915)
> +void intel_shared_dpll_init(struct intel_display *display)
>  {
> +	struct drm_i915_private *i915 = to_i915(display->drm);
>  	const struct intel_dpll_mgr *dpll_mgr = NULL;
>  	const struct dpll_info *dpll_info;
>  	int i;
>  
> -	mutex_init(&i915->display.dpll.lock);
> +	mutex_init(&display->dpll.lock);
>  
> -	if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
> +	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>  		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
>  		dpll_mgr = NULL;
> -	else if (IS_ALDERLAKE_P(i915))
> +	else if (display->platform.alderlake_p)
>  		dpll_mgr = &adlp_pll_mgr;
> -	else if (IS_ALDERLAKE_S(i915))
> +	else if (display->platform.alderlake_s)
>  		dpll_mgr = &adls_pll_mgr;
> -	else if (IS_DG1(i915))
> +	else if (display->platform.dg1)
>  		dpll_mgr = &dg1_pll_mgr;
> -	else if (IS_ROCKETLAKE(i915))
> +	else if (display->platform.rocketlake)
>  		dpll_mgr = &rkl_pll_mgr;
> -	else if (DISPLAY_VER(i915) >= 12)
> +	else if (DISPLAY_VER(display) >= 12)
>  		dpll_mgr = &tgl_pll_mgr;
> -	else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
> +	else if (display->platform.jasperlake || display->platform.elkhartlake)
>  		dpll_mgr = &ehl_pll_mgr;
> -	else if (DISPLAY_VER(i915) >= 11)
> +	else if (DISPLAY_VER(display) >= 11)
>  		dpll_mgr = &icl_pll_mgr;
> -	else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> +	else if (display->platform.geminilake || display->platform.broxton)
>  		dpll_mgr = &bxt_pll_mgr;
> -	else if (DISPLAY_VER(i915) == 9)
> +	else if (DISPLAY_VER(display) == 9)
>  		dpll_mgr = &skl_pll_mgr;
> -	else if (HAS_DDI(i915))
> +	else if (HAS_DDI(display))
>  		dpll_mgr = &hsw_pll_mgr;
>  	else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
>  		dpll_mgr = &pch_pll_mgr;
> @@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct drm_i915_private *i915)
>  	dpll_info = dpll_mgr->dpll_info;
>  
>  	for (i = 0; dpll_info[i].name; i++) {
> -		if (drm_WARN_ON(&i915->drm,
> -				i >= ARRAY_SIZE(i915->display.dpll.shared_dplls)))
> +		if (drm_WARN_ON(display->drm,
> +				i >= ARRAY_SIZE(display->dpll.shared_dplls)))
>  			break;
>  
>  		/* must fit into unsigned long bitmask on 32bit */
> -		if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
> +		if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
>  			break;
>  
> -		i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
> -		i915->display.dpll.shared_dplls[i].index = i;
> +		display->dpll.shared_dplls[i].info = &dpll_info[i];
> +		display->dpll.shared_dplls[i].index = i;
>  	}
>  
> -	i915->display.dpll.mgr = dpll_mgr;
> -	i915->display.dpll.num_shared_dpll = i;
> +	display->dpll.mgr = dpll_mgr;
> +	display->dpll.num_shared_dpll = i;
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 3d988f17f31d..caffb084830c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -35,7 +35,6 @@
>  		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>  
>  enum tc_port;
> -struct drm_i915_private;
>  struct drm_printer;
>  struct intel_atomic_state;
>  struct intel_crtc;
> @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display *display,
>  void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
>  void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
> -void intel_shared_dpll_init(struct drm_i915_private *i915);
> +void intel_shared_dpll_init(struct intel_display *display);
>  void intel_dpll_update_ref_clks(struct intel_display *display);
>  void intel_dpll_readout_hw_state(struct intel_display *display);
>  void intel_dpll_sanitize_state(struct intel_display *display);

-- 
Jani Nikula, Intel

RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init

[Kandpal, Suraj]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 11, 2025 6:45 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for
> shared_dpll_init
> 
> On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> > Use intel_display as an argument for intel_shared_dpll_init() and
> > replace drm_i915_private in function wherever possible.
> > While at it prefer using display->platform.xx over IS_PLATFORM.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_driver.c   |  2 +-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49
> > ++++++++++---------  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |
> > 3 +-
> >  3 files changed, 27 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index 978f530c810e..852f1129a058 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct
> intel_display *display)
> >  	}
> >
> >  	intel_plane_possible_crtcs_init(display);
> > -	intel_shared_dpll_init(i915);
> > +	intel_shared_dpll_init(display);
> >  	intel_fdi_pll_freq_update(i915);
> >
> >  	intel_update_czclk(i915);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index f94da1ffc8ce..26b6b9372fa3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct
> > intel_display *display,  {
> >  	const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> >  	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping
> */
> > -	enum dpio_phy phy;
> > -	enum dpio_channel ch;
> > +	enum dpio_phy phy = DPIO_PHY0;
> > +	enum dpio_channel ch = DPIO_CH0;
> 
> Unrelated change, please drop.
> 

The problem is by dropping these changes I am not able to build the kernel and it throws the following warning because of which I had to add this


drivers/gpu/drm/i915/display/intel_dpll_mgr.c: In function _bxt_ddi_pll_enable_:
./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:240:56: error: _phy_ is used uninitialized [-Werror=uniniti
alized]
  240 |         (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +                        \
      |                                                        ^
drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2047:23: note: _phy_ was declared here
 2047 |         enum dpio_phy phy;
      |                       ^~~
In file included from ./drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h:6,
                 from drivers/gpu/drm/i915/display/intel_display_reg_defs.h:9,
                 from drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:9,
                 from drivers/gpu/drm/i915/display/intel_dpll_mgr.c:27:
./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:213:58: error: _ch_ is used uninitialized [-Werror=uninitia
lized]
  213 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
      |                                                          ^
drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2048:27: note: _ch_ was declared here
 2048 |         enum dpio_channel ch;

Regards,
Suraj Kandpal

> With that fixed,
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> 
> >  	u32 temp;
> >
> >  	bxt_port_to_phy_channel(display, port, &phy, &ch); @@ -4302,40
> > +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> >
> >  /**
> >   * intel_shared_dpll_init - Initialize shared DPLLs
> > - * @i915: i915 device
> > + * @display: intel_display device
> >   *
> > - * Initialize shared DPLLs for @i915.
> > + * Initialize shared DPLLs for @display.
> >   */
> > -void intel_shared_dpll_init(struct drm_i915_private *i915)
> > +void intel_shared_dpll_init(struct intel_display *display)
> >  {
> > +	struct drm_i915_private *i915 = to_i915(display->drm);
> >  	const struct intel_dpll_mgr *dpll_mgr = NULL;
> >  	const struct dpll_info *dpll_info;
> >  	int i;
> >
> > -	mutex_init(&i915->display.dpll.lock);
> > +	mutex_init(&display->dpll.lock);
> >
> > -	if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
> > +	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> >  		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
> >  		dpll_mgr = NULL;
> > -	else if (IS_ALDERLAKE_P(i915))
> > +	else if (display->platform.alderlake_p)
> >  		dpll_mgr = &adlp_pll_mgr;
> > -	else if (IS_ALDERLAKE_S(i915))
> > +	else if (display->platform.alderlake_s)
> >  		dpll_mgr = &adls_pll_mgr;
> > -	else if (IS_DG1(i915))
> > +	else if (display->platform.dg1)
> >  		dpll_mgr = &dg1_pll_mgr;
> > -	else if (IS_ROCKETLAKE(i915))
> > +	else if (display->platform.rocketlake)
> >  		dpll_mgr = &rkl_pll_mgr;
> > -	else if (DISPLAY_VER(i915) >= 12)
> > +	else if (DISPLAY_VER(display) >= 12)
> >  		dpll_mgr = &tgl_pll_mgr;
> > -	else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
> > +	else if (display->platform.jasperlake ||
> > +display->platform.elkhartlake)
> >  		dpll_mgr = &ehl_pll_mgr;
> > -	else if (DISPLAY_VER(i915) >= 11)
> > +	else if (DISPLAY_VER(display) >= 11)
> >  		dpll_mgr = &icl_pll_mgr;
> > -	else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> > +	else if (display->platform.geminilake || display->platform.broxton)
> >  		dpll_mgr = &bxt_pll_mgr;
> > -	else if (DISPLAY_VER(i915) == 9)
> > +	else if (DISPLAY_VER(display) == 9)
> >  		dpll_mgr = &skl_pll_mgr;
> > -	else if (HAS_DDI(i915))
> > +	else if (HAS_DDI(display))
> >  		dpll_mgr = &hsw_pll_mgr;
> >  	else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
> >  		dpll_mgr = &pch_pll_mgr;
> > @@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct
> drm_i915_private *i915)
> >  	dpll_info = dpll_mgr->dpll_info;
> >
> >  	for (i = 0; dpll_info[i].name; i++) {
> > -		if (drm_WARN_ON(&i915->drm,
> > -				i >= ARRAY_SIZE(i915-
> >display.dpll.shared_dplls)))
> > +		if (drm_WARN_ON(display->drm,
> > +				i >= ARRAY_SIZE(display->dpll.shared_dplls)))
> >  			break;
> >
> >  		/* must fit into unsigned long bitmask on 32bit */
> > -		if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
> > +		if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> >  			break;
> >
> > -		i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
> > -		i915->display.dpll.shared_dplls[i].index = i;
> > +		display->dpll.shared_dplls[i].info = &dpll_info[i];
> > +		display->dpll.shared_dplls[i].index = i;
> >  	}
> >
> > -	i915->display.dpll.mgr = dpll_mgr;
> > -	i915->display.dpll.num_shared_dpll = i;
> > +	display->dpll.mgr = dpll_mgr;
> > +	display->dpll.num_shared_dpll = i;
> >  }
> >
> >  /**
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > index 3d988f17f31d..caffb084830c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> > @@ -35,7 +35,6 @@
> >  		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
> >
> >  enum tc_port;
> > -struct drm_i915_private;
> >  struct drm_printer;
> >  struct intel_atomic_state;
> >  struct intel_crtc;
> > @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display
> > *display,  void intel_enable_shared_dpll(const struct intel_crtc_state
> > *crtc_state);  void intel_disable_shared_dpll(const struct
> > intel_crtc_state *crtc_state);  void
> > intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void
> > intel_shared_dpll_init(struct drm_i915_private *i915);
> > +void intel_shared_dpll_init(struct intel_display *display);
> >  void intel_dpll_update_ref_clks(struct intel_display *display);  void
> > intel_dpll_readout_hw_state(struct intel_display *display);  void
> > intel_dpll_sanitize_state(struct intel_display *display);
> 
> --
> Jani Nikula, Intel

RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init

[Jani Nikula]

On Tue, 11 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Tuesday, February 11, 2025 6:45 PM
>> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
>> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
>> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
>> <suraj.kandpal@intel.com>
>> Subject: Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for
>> shared_dpll_init
>>
>> On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> > Use intel_display as an argument for intel_shared_dpll_init() and
>> > replace drm_i915_private in function wherever possible.
>> > While at it prefer using display->platform.xx over IS_PLATFORM.
>> >
>> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> > ---
>> >  .../drm/i915/display/intel_display_driver.c   |  2 +-
>> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49
>> > ++++++++++---------  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |
>> > 3 +-
>> >  3 files changed, 27 insertions(+), 27 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > index 978f530c810e..852f1129a058 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
>> > @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct
>> intel_display *display)
>> >     }
>> >
>> >     intel_plane_possible_crtcs_init(display);
>> > -   intel_shared_dpll_init(i915);
>> > +   intel_shared_dpll_init(display);
>> >     intel_fdi_pll_freq_update(i915);
>> >
>> >     intel_update_czclk(i915);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > index f94da1ffc8ce..26b6b9372fa3 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> > @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct
>> > intel_display *display,  {
>> >     const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
>> >     enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping
>> */
>> > -   enum dpio_phy phy;
>> > -   enum dpio_channel ch;
>> > +   enum dpio_phy phy = DPIO_PHY0;
>> > +   enum dpio_channel ch = DPIO_CH0;
>>
>> Unrelated change, please drop.
>>
>
> The problem is by dropping these changes I am not able to build the kernel and it throws the following warning because of which I had to add this
>
>
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c: In function _bxt_ddi_pll_enable_:
> ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:240:56: error: _phy_ is used uninitialized [-Werror=uniniti
> alized]
>   240 |         (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +                        \
>       |                                                        ^
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2047:23: note: _phy_ was declared here
>  2047 |         enum dpio_phy phy;
>       |                       ^~~
> In file included from ./drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h:6,
>                  from drivers/gpu/drm/i915/display/intel_display_reg_defs.h:9,
>                  from drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:9,
>                  from drivers/gpu/drm/i915/display/intel_dpll_mgr.c:27:
> ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:213:58: error: _ch_ is used uninitialized [-Werror=uninitia
> lized]
>   213 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) - (__a)))
>       |                                                          ^
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2048:27: note: _ch_ was declared here
>  2048 |         enum dpio_channel ch;

Did you think to look into why this happens? I encourage you to always
do that instead of just silencing the warning. You'll learn about C and
the compiler.

It's quite interesting and subtle and deserves to be mentioned in the
commit message.

For i915.ko, bxt_port_to_phy_channel() is a regular function, and the
compiler will likely assume it'll initialize the parameters. And it
does.

For xe.ko, bxt_port_to_phy_channel() is a static inline stub, and the
compiler can be absolutely certain the parameters aren't initialized.

So, why does this cause an error now? The above didn't change now!

With IS_GEMINILAKE() || IS_BROXTON() the compiler can be sure it's false
for xe.ko. The whole chain bxt_pll_mgr -> bxt_plls -> bxt_ddi_pll_funcs
-> bxt_ddi_pll_enable can be optimized away. It's unreachable.

Not so with display->platform.geminilake ||
display->platform.broxton. The compiler sees use of uninitialized
variables.

BR,
Jani.



>
> Regards,
> Suraj Kandpal
>
>> With that fixed,
>>
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>>
>> >     u32 temp;
>> >
>> >     bxt_port_to_phy_channel(display, port, &phy, &ch); @@ -4302,40
>> > +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>> >
>> >  /**
>> >   * intel_shared_dpll_init - Initialize shared DPLLs
>> > - * @i915: i915 device
>> > + * @display: intel_display device
>> >   *
>> > - * Initialize shared DPLLs for @i915.
>> > + * Initialize shared DPLLs for @display.
>> >   */
>> > -void intel_shared_dpll_init(struct drm_i915_private *i915)
>> > +void intel_shared_dpll_init(struct intel_display *display)
>> >  {
>> > +   struct drm_i915_private *i915 = to_i915(display->drm);
>> >     const struct intel_dpll_mgr *dpll_mgr = NULL;
>> >     const struct dpll_info *dpll_info;
>> >     int i;
>> >
>> > -   mutex_init(&i915->display.dpll.lock);
>> > +   mutex_init(&display->dpll.lock);
>> >
>> > -   if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
>> > +   if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
>> >             /* No shared DPLLs on DG2; port PLLs are part of the PHY */
>> >             dpll_mgr = NULL;
>> > -   else if (IS_ALDERLAKE_P(i915))
>> > +   else if (display->platform.alderlake_p)
>> >             dpll_mgr = &adlp_pll_mgr;
>> > -   else if (IS_ALDERLAKE_S(i915))
>> > +   else if (display->platform.alderlake_s)
>> >             dpll_mgr = &adls_pll_mgr;
>> > -   else if (IS_DG1(i915))
>> > +   else if (display->platform.dg1)
>> >             dpll_mgr = &dg1_pll_mgr;
>> > -   else if (IS_ROCKETLAKE(i915))
>> > +   else if (display->platform.rocketlake)
>> >             dpll_mgr = &rkl_pll_mgr;
>> > -   else if (DISPLAY_VER(i915) >= 12)
>> > +   else if (DISPLAY_VER(display) >= 12)
>> >             dpll_mgr = &tgl_pll_mgr;
>> > -   else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
>> > +   else if (display->platform.jasperlake ||
>> > +display->platform.elkhartlake)
>> >             dpll_mgr = &ehl_pll_mgr;
>> > -   else if (DISPLAY_VER(i915) >= 11)
>> > +   else if (DISPLAY_VER(display) >= 11)
>> >             dpll_mgr = &icl_pll_mgr;
>> > -   else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
>> > +   else if (display->platform.geminilake || display->platform.broxton)
>> >             dpll_mgr = &bxt_pll_mgr;
>> > -   else if (DISPLAY_VER(i915) == 9)
>> > +   else if (DISPLAY_VER(display) == 9)
>> >             dpll_mgr = &skl_pll_mgr;
>> > -   else if (HAS_DDI(i915))
>> > +   else if (HAS_DDI(display))
>> >             dpll_mgr = &hsw_pll_mgr;
>> >     else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
>> >             dpll_mgr = &pch_pll_mgr;
>> > @@ -4346,20 +4347,20 @@ void intel_shared_dpll_init(struct
>> drm_i915_private *i915)
>> >     dpll_info = dpll_mgr->dpll_info;
>> >
>> >     for (i = 0; dpll_info[i].name; i++) {
>> > -           if (drm_WARN_ON(&i915->drm,
>> > -                           i >= ARRAY_SIZE(i915-
>> >display.dpll.shared_dplls)))
>> > +           if (drm_WARN_ON(display->drm,
>> > +                           i >= ARRAY_SIZE(display->dpll.shared_dplls)))
>> >                     break;
>> >
>> >             /* must fit into unsigned long bitmask on 32bit */
>> > -           if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
>> > +           if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
>> >                     break;
>> >
>> > -           i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
>> > -           i915->display.dpll.shared_dplls[i].index = i;
>> > +           display->dpll.shared_dplls[i].info = &dpll_info[i];
>> > +           display->dpll.shared_dplls[i].index = i;
>> >     }
>> >
>> > -   i915->display.dpll.mgr = dpll_mgr;
>> > -   i915->display.dpll.num_shared_dpll = i;
>> > +   display->dpll.mgr = dpll_mgr;
>> > +   display->dpll.num_shared_dpll = i;
>> >  }
>> >
>> >  /**
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > index 3d988f17f31d..caffb084830c 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> > @@ -35,7 +35,6 @@
>> >                  ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)
>> >
>> >  enum tc_port;
>> > -struct drm_i915_private;
>> >  struct drm_printer;
>> >  struct intel_atomic_state;
>> >  struct intel_crtc;
>> > @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct intel_display
>> > *display,  void intel_enable_shared_dpll(const struct intel_crtc_state
>> > *crtc_state);  void intel_disable_shared_dpll(const struct
>> > intel_crtc_state *crtc_state);  void
>> > intel_shared_dpll_swap_state(struct intel_atomic_state *state); -void
>> > intel_shared_dpll_init(struct drm_i915_private *i915);
>> > +void intel_shared_dpll_init(struct intel_display *display);
>> >  void intel_dpll_update_ref_clks(struct intel_display *display);  void
>> > intel_dpll_readout_hw_state(struct intel_display *display);  void
>> > intel_dpll_sanitize_state(struct intel_display *display);
>>
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for shared_dpll_init

[Kandpal, Suraj]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 11, 2025 10:27 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: RE: [PATCH 8/9] drm/i915/dpll: Accept intel_display as argument for
> shared_dpll_init
> 
> On Tue, 11 Feb 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Tuesday, February 11, 2025 6:45 PM
> >> To: Kandpal, Suraj <suraj.kandpal@intel.com>; intel-
> >> xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> >> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> >> <suraj.kandpal@intel.com>
> >> Subject: Re: [PATCH 8/9] drm/i915/dpll: Accept intel_display as
> >> argument for shared_dpll_init
> >>
> >> On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >> > Use intel_display as an argument for intel_shared_dpll_init() and
> >> > replace drm_i915_private in function wherever possible.
> >> > While at it prefer using display->platform.xx over IS_PLATFORM.
> >> >
> >> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> > ---
> >> >  .../drm/i915/display/intel_display_driver.c   |  2 +-
> >> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 49
> >> > ++++++++++---------  drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > ++++++++++|
> >> > 3 +-
> >> >  3 files changed, 27 insertions(+), 27 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > b/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > index 978f530c810e..852f1129a058 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> >> > @@ -448,7 +448,7 @@ int intel_display_driver_probe_nogem(struct
> >> intel_display *display)
> >> >     }
> >> >
> >> >     intel_plane_possible_crtcs_init(display);
> >> > -   intel_shared_dpll_init(i915);
> >> > +   intel_shared_dpll_init(display);
> >> >     intel_fdi_pll_freq_update(i915);
> >> >
> >> >     intel_update_czclk(i915);
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > index f94da1ffc8ce..26b6b9372fa3 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> > @@ -2042,8 +2042,8 @@ static void bxt_ddi_pll_enable(struct
> >> > intel_display *display,  {
> >> >     const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> >> >     enum port port = (enum port)pll->info->id; /* 1:1 port->PLL
> >> > mapping
> >> */
> >> > -   enum dpio_phy phy;
> >> > -   enum dpio_channel ch;
> >> > +   enum dpio_phy phy = DPIO_PHY0;
> >> > +   enum dpio_channel ch = DPIO_CH0;
> >>
> >> Unrelated change, please drop.
> >>
> >
> > The problem is by dropping these changes I am not able to build the
> > kernel and it throws the following warning because of which I had to
> > add this
> >
> >
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c: In function
> _bxt_ddi_pll_enable_:
> > ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:24
> > 0:56: error: _phy_ is used uninitialized [-Werror=uniniti alized]
> >   240 |         (BUILD_BUG_ON_ZERO(!__is_constexpr(__c_index)) +
> \
> >       |                                                        ^
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2047:23: note: _phy_ was
> declared here
> >  2047 |         enum dpio_phy phy;
> >       |                       ^~~
> > In file included from ./drivers/gpu/drm/xe/compat-i915-
> headers/i915_reg_defs.h:6,
> >                  from drivers/gpu/drm/i915/display/intel_display_reg_defs.h:9,
> >                  from drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:9,
> >                  from drivers/gpu/drm/i915/display/intel_dpll_mgr.c:27:
> > ./drivers/gpu/drm/xe/compat-i915-headers/../../i915/i915_reg_defs.h:21
> > 3:58: error: _ch_ is used uninitialized [-Werror=uninitia lized]
> >   213 | #define _PICK_EVEN(__index, __a, __b) ((__a) + (__index) * ((__b) -
> (__a)))
> >       |                                                          ^
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2048:27: note: _ch_ was
> declared here
> >  2048 |         enum dpio_channel ch;
> 
> Did you think to look into why this happens? I encourage you to always do
> that instead of just silencing the warning. You'll learn about C and the
> compiler.
> 
> It's quite interesting and subtle and deserves to be mentioned in the
> commit message.
> 
> For i915.ko, bxt_port_to_phy_channel() is a regular function, and the
> compiler will likely assume it'll initialize the parameters. And it does.
> 
> For xe.ko, bxt_port_to_phy_channel() is a static inline stub, and the
> compiler can be absolutely certain the parameters aren't initialized.
> 
> So, why does this cause an error now? The above didn't change now!
> 
> With IS_GEMINILAKE() || IS_BROXTON() the compiler can be sure it's false
> for xe.ko. The whole chain bxt_pll_mgr -> bxt_plls -> bxt_ddi_pll_funcs
> -> bxt_ddi_pll_enable can be optimized away. It's unreachable.
> 
> Not so with display->platform.geminilake ||
> display->platform.broxton. The compiler sees use of uninitialized
> variables.

Ahh ohkay, I understand it now thanks for explaining it.
Will amend the commit message
Will explore these things and add them to commit message in  future too.

Regards,
Suraj Kandpal 

> 
> BR,
> Jani.
> 
> 
> 
> >
> > Regards,
> > Suraj Kandpal
> >
> >> With that fixed,
> >>
> >> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> >>
> >>
> >> >     u32 temp;
> >> >
> >> >     bxt_port_to_phy_channel(display, port, &phy, &ch); @@ -4302,40
> >> > +4302,41 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> >> >
> >> >  /**
> >> >   * intel_shared_dpll_init - Initialize shared DPLLs
> >> > - * @i915: i915 device
> >> > + * @display: intel_display device
> >> >   *
> >> > - * Initialize shared DPLLs for @i915.
> >> > + * Initialize shared DPLLs for @display.
> >> >   */
> >> > -void intel_shared_dpll_init(struct drm_i915_private *i915)
> >> > +void intel_shared_dpll_init(struct intel_display *display)
> >> >  {
> >> > +   struct drm_i915_private *i915 = to_i915(display->drm);
> >> >     const struct intel_dpll_mgr *dpll_mgr = NULL;
> >> >     const struct dpll_info *dpll_info;
> >> >     int i;
> >> >
> >> > -   mutex_init(&i915->display.dpll.lock);
> >> > +   mutex_init(&display->dpll.lock);
> >> >
> >> > -   if (DISPLAY_VER(i915) >= 14 || IS_DG2(i915))
> >> > +   if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> >> >             /* No shared DPLLs on DG2; port PLLs are part of the PHY */
> >> >             dpll_mgr = NULL;
> >> > -   else if (IS_ALDERLAKE_P(i915))
> >> > +   else if (display->platform.alderlake_p)
> >> >             dpll_mgr = &adlp_pll_mgr;
> >> > -   else if (IS_ALDERLAKE_S(i915))
> >> > +   else if (display->platform.alderlake_s)
> >> >             dpll_mgr = &adls_pll_mgr;
> >> > -   else if (IS_DG1(i915))
> >> > +   else if (display->platform.dg1)
> >> >             dpll_mgr = &dg1_pll_mgr;
> >> > -   else if (IS_ROCKETLAKE(i915))
> >> > +   else if (display->platform.rocketlake)
> >> >             dpll_mgr = &rkl_pll_mgr;
> >> > -   else if (DISPLAY_VER(i915) >= 12)
> >> > +   else if (DISPLAY_VER(display) >= 12)
> >> >             dpll_mgr = &tgl_pll_mgr;
> >> > -   else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915))
> >> > +   else if (display->platform.jasperlake ||
> >> > +display->platform.elkhartlake)
> >> >             dpll_mgr = &ehl_pll_mgr;
> >> > -   else if (DISPLAY_VER(i915) >= 11)
> >> > +   else if (DISPLAY_VER(display) >= 11)
> >> >             dpll_mgr = &icl_pll_mgr;
> >> > -   else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> >> > +   else if (display->platform.geminilake ||
> >> > + display->platform.broxton)
> >> >             dpll_mgr = &bxt_pll_mgr;
> >> > -   else if (DISPLAY_VER(i915) == 9)
> >> > +   else if (DISPLAY_VER(display) == 9)
> >> >             dpll_mgr = &skl_pll_mgr;
> >> > -   else if (HAS_DDI(i915))
> >> > +   else if (HAS_DDI(display))
> >> >             dpll_mgr = &hsw_pll_mgr;
> >> >     else if (HAS_PCH_IBX(i915) || HAS_PCH_CPT(i915))
> >> >             dpll_mgr = &pch_pll_mgr; @@ -4346,20 +4347,20 @@ void
> >> > intel_shared_dpll_init(struct
> >> drm_i915_private *i915)
> >> >     dpll_info = dpll_mgr->dpll_info;
> >> >
> >> >     for (i = 0; dpll_info[i].name; i++) {
> >> > -           if (drm_WARN_ON(&i915->drm,
> >> > -                           i >= ARRAY_SIZE(i915-
> >> >display.dpll.shared_dplls)))
> >> > +           if (drm_WARN_ON(display->drm,
> >> > +                           i >=
> >> > + ARRAY_SIZE(display->dpll.shared_dplls)))
> >> >                     break;
> >> >
> >> >             /* must fit into unsigned long bitmask on 32bit */
> >> > -           if (drm_WARN_ON(&i915->drm, dpll_info[i].id >= 32))
> >> > +           if (drm_WARN_ON(display->drm, dpll_info[i].id >= 32))
> >> >                     break;
> >> >
> >> > -           i915->display.dpll.shared_dplls[i].info = &dpll_info[i];
> >> > -           i915->display.dpll.shared_dplls[i].index = i;
> >> > +           display->dpll.shared_dplls[i].info = &dpll_info[i];
> >> > +           display->dpll.shared_dplls[i].index = i;
> >> >     }
> >> >
> >> > -   i915->display.dpll.mgr = dpll_mgr;
> >> > -   i915->display.dpll.num_shared_dpll = i;
> >> > +   display->dpll.mgr = dpll_mgr;
> >> > +   display->dpll.num_shared_dpll = i;
> >> >  }
> >> >
> >> >  /**
> >> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > index 3d988f17f31d..caffb084830c 100644
> >> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> >> > @@ -35,7 +35,6 @@
> >> >                  ((__pll) = &(__display)->dpll.shared_dplls[(__i)])
> >> > ; (__i)++)
> >> >
> >> >  enum tc_port;
> >> > -struct drm_i915_private;
> >> >  struct drm_printer;
> >> >  struct intel_atomic_state;
> >> >  struct intel_crtc;
> >> > @@ -422,7 +421,7 @@ bool intel_dpll_get_hw_state(struct
> >> > intel_display *display,  void intel_enable_shared_dpll(const struct
> >> > intel_crtc_state *crtc_state);  void
> >> > intel_disable_shared_dpll(const struct intel_crtc_state
> >> > *crtc_state);  void intel_shared_dpll_swap_state(struct
> >> > intel_atomic_state *state); -void intel_shared_dpll_init(struct
> >> > drm_i915_private *i915);
> >> > +void intel_shared_dpll_init(struct intel_display *display);
> >> >  void intel_dpll_update_ref_clks(struct intel_display *display);
> >> > void intel_dpll_readout_hw_state(struct intel_display *display);
> >> > void intel_dpll_sanitize_state(struct intel_display *display);
> >>
> >> --
> >> Jani Nikula, Intel
> 
> --
> Jani Nikula, Intel

[PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private

[Suraj Kandpal]

Replace all other left over drm_i915_private with intel_display
in dpll_mgr.c.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 99 +++++++++----------
 1 file changed, 48 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 26b6b9372fa3..96abb7e295a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -117,11 +117,10 @@ struct intel_dpll_mgr {
 };
 
 static void
-intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
+intel_atomic_duplicate_dpll_state(struct intel_display *display,
 				  struct intel_shared_dpll_state *shared_dpll)
 {
 	struct intel_shared_dpll *pll;
-	struct intel_display *display = to_intel_display(&i915->drm);
 	int i;
 
 	/* Copy shared dpll state */
@@ -139,7 +138,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
 	if (!state->dpll_set) {
 		state->dpll_set = true;
 
-		intel_atomic_duplicate_dpll_state(to_i915(s->dev),
+		intel_atomic_duplicate_dpll_state(to_intel_display(state),
 						  state->shared_dpll);
 	}
 
@@ -420,13 +419,13 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
 				 const struct intel_shared_dpll *pll,
 				 struct intel_shared_dpll_state *shared_dpll_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(crtc);
 
-	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
+	drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
 
 	shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
 
-	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
 		    crtc->base.base.id, crtc->base.name, pll->info->name);
 }
 
@@ -459,13 +458,13 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
 				   const struct intel_shared_dpll *pll,
 				   struct intel_shared_dpll_state *shared_dpll_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(crtc);
 
-	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
+	drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
 
 	shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
 
-	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
 		    crtc->base.base.id, crtc->base.name, pll->info->name);
 }
 
@@ -545,9 +544,8 @@ static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
 	return val & DPLL_VCO_ENABLE;
 }
 
-static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
+static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
 {
-	struct intel_display *display = &i915->display;
 	u32 val;
 	bool enabled;
 
@@ -562,12 +560,11 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct drm_i915_private *i915 = to_i915(display->drm);
 	const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
 	const enum intel_dpll_id id = pll->info->id;
 
 	/* PCH refclock must be enabled first */
-	ibx_assert_pch_refclk_enabled(i915);
+	ibx_assert_pch_refclk_enabled(display);
 
 	intel_de_write(display, PCH_FP0(id), hw_state->fp0);
 	intel_de_write(display, PCH_FP1(id), hw_state->fp1);
@@ -1074,7 +1071,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
 static int
 hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	int clock = crtc_state->port_clock;
 
 	switch (clock / 2) {
@@ -1083,7 +1080,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
 	case 270000:
 		return 0;
 	default:
-		drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
+		drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",
 			    clock);
 		return -EINVAL;
 	}
@@ -2255,7 +2252,7 @@ static int
 bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 			  struct dpll *clk_div)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 
 	/* Calculate HDMI div */
 	/*
@@ -2265,7 +2262,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 	if (!bxt_find_best_dpll(crtc_state, clk_div))
 		return -EINVAL;
 
-	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
+	drm_WARN_ON(display->drm, clk_div->m1 != 2);
 
 	return 0;
 }
@@ -2273,7 +2270,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
 				    struct dpll *clk_div)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	int i;
 
 	*clk_div = bxt_dp_clk_val[0];
@@ -2284,16 +2281,16 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
 		}
 	}
 
-	chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
+	chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);
 
-	drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
+	drm_WARN_ON(display->drm, clk_div->vco == 0 ||
 		    clk_div->dot != crtc_state->port_clock);
 }
 
 static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 				     const struct dpll *clk_div)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
 	int clock = crtc_state->port_clock;
 	int vco = clk_div->vco;
@@ -2317,7 +2314,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 		gain_ctl = 1;
 		targ_cnt = 9;
 	} else {
-		drm_err(&i915->drm, "Invalid VCO\n");
+		drm_err(display->drm, "Invalid VCO\n");
 		return -EINVAL;
 	}
 
@@ -2700,9 +2697,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
 static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
 				 struct skl_wrpll_params *pll_params)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	const struct icl_combo_pll_params *params =
-		i915->display.dpll.ref_clks.nssc == 24000 ?
+		display->dpll.ref_clks.nssc == 24000 ?
 		icl_dp_combo_pll_24MHz_values :
 		icl_dp_combo_pll_19_2MHz_values;
 	int clock = crtc_state->port_clock;
@@ -2722,12 +2719,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
 static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 			    struct skl_wrpll_params *pll_params)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 
-	if (DISPLAY_VER(i915) >= 12) {
-		switch (i915->display.dpll.ref_clks.nssc) {
+	if (DISPLAY_VER(display) >= 12) {
+		switch (display->dpll.ref_clks.nssc) {
 		default:
-			MISSING_CASE(i915->display.dpll.ref_clks.nssc);
+			MISSING_CASE(display->dpll.ref_clks.nssc);
 			fallthrough;
 		case 19200:
 		case 38400:
@@ -2738,9 +2735,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 			break;
 		}
 	} else {
-		switch (i915->display.dpll.ref_clks.nssc) {
+		switch (display->dpll.ref_clks.nssc) {
 		default:
-			MISSING_CASE(i915->display.dpll.ref_clks.nssc);
+			MISSING_CASE(display->dpll.ref_clks.nssc);
 			fallthrough;
 		case 19200:
 		case 38400:
@@ -2998,9 +2995,9 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 				 struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	int refclk_khz = i915->display.dpll.ref_clks.nssc;
+	int refclk_khz = display->dpll.ref_clks.nssc;
 	int clock = crtc_state->port_clock;
 	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
 	u32 iref_ndiv, iref_trim, iref_pulse_w;
@@ -3010,7 +3007,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 	u64 tmp;
 	bool use_ssc = false;
 	bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
-	bool is_dkl = DISPLAY_VER(i915) >= 12;
+	bool is_dkl = DISPLAY_VER(display) >= 12;
 	int ret;
 
 	ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
@@ -3108,8 +3105,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 					 DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
 					 DKL_PLL_DIV0_FBPREDIV(m1div) |
 					 DKL_PLL_DIV0_FBDIV_INT(m2div_int);
-		if (i915->display.vbt.override_afc_startup) {
-			u8 val = i915->display.vbt.override_afc_startup_val;
+		if (display->vbt.override_afc_startup) {
+			u8 val = display->vbt.override_afc_startup_val;
 
 			hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
 		}
@@ -3347,7 +3344,6 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 				  struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct icl_port_dpll *port_dpll =
@@ -3355,13 +3351,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 	enum port port = encoder->port;
 	unsigned long dpll_mask;
 
-	if (IS_ALDERLAKE_S(i915)) {
+	if (display->platform.alderlake_s) {
 		dpll_mask =
 			BIT(DPLL_ID_DG1_DPLL3) |
 			BIT(DPLL_ID_DG1_DPLL2) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	} else if (IS_DG1(i915)) {
+	} else if (display->platform.dg1) {
 		if (port == PORT_D || port == PORT_E) {
 			dpll_mask =
 				BIT(DPLL_ID_DG1_DPLL2) |
@@ -3371,12 +3367,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 				BIT(DPLL_ID_DG1_DPLL0) |
 				BIT(DPLL_ID_DG1_DPLL1);
 		}
-	} else if (IS_ROCKETLAKE(i915)) {
+	} else if (display->platform.rocketlake) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
 			BIT(DPLL_ID_ICL_DPLL1) |
 			BIT(DPLL_ID_ICL_DPLL0);
-	} else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+	} else if ((display->platform.jasperlake ||
+		    display->platform.elkhartlake) &&
 		   port != PORT_A) {
 		dpll_mask =
 			BIT(DPLL_ID_EHL_DPLL4) |
@@ -4381,10 +4378,10 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
 			       struct intel_crtc *crtc,
 			       struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
 
-	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
+	if (drm_WARN_ON(display->drm, !dpll_mgr))
 		return -EINVAL;
 
 	return dpll_mgr->compute_dplls(state, crtc, encoder);
@@ -4414,10 +4411,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
 			       struct intel_crtc *crtc,
 			       struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
 
-	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
+	if (drm_WARN_ON(display->drm, !dpll_mgr))
 		return -EINVAL;
 
 	return dpll_mgr->get_dplls(state, crtc, encoder);
@@ -4437,8 +4434,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
 void intel_release_shared_dplls(struct intel_atomic_state *state,
 				struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
 
 	/*
 	 * FIXME: this function is called for every platform having a
@@ -4466,10 +4463,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc,
 			      struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
+	struct intel_display *display = to_intel_display(encoder);
+	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
 
-	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
+	if (drm_WARN_ON(display->drm, !dpll_mgr))
 		return;
 
 	dpll_mgr->update_active_dpll(state, crtc, encoder);
-- 
2.34.1

Re: [PATCH 9/9] drm/i915/dpll: Replace all other leftover drm_i915_private

[Jani Nikula]

On Tue, 11 Feb 2025, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> Replace all other left over drm_i915_private with intel_display
> in dpll_mgr.c.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 99 +++++++++----------
>  1 file changed, 48 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 26b6b9372fa3..96abb7e295a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -117,11 +117,10 @@ struct intel_dpll_mgr {
>  };
>  
>  static void
> -intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915,
> +intel_atomic_duplicate_dpll_state(struct intel_display *display,
>  				  struct intel_shared_dpll_state *shared_dpll)
>  {
>  	struct intel_shared_dpll *pll;
> -	struct intel_display *display = to_intel_display(&i915->drm);
>  	int i;
>  
>  	/* Copy shared dpll state */
> @@ -139,7 +138,7 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
>  	if (!state->dpll_set) {
>  		state->dpll_set = true;
>  
> -		intel_atomic_duplicate_dpll_state(to_i915(s->dev),
> +		intel_atomic_duplicate_dpll_state(to_intel_display(state),

Please do not add inline to_intel_display() usages, ever, anywhere. Add
a local display variable instead.

With that fixed,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  						  state->shared_dpll);
>  	}
>  
> @@ -420,13 +419,13 @@ intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
>  				 const struct intel_shared_dpll *pll,
>  				 struct intel_shared_dpll_state *shared_dpll_state)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_display *display = to_intel_display(crtc);
>  
> -	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
> +	drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
>  
>  	shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
>  
> -	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
> +	drm_dbg_kms(display->drm, "[CRTC:%d:%s] reserving %s\n",
>  		    crtc->base.base.id, crtc->base.name, pll->info->name);
>  }
>  
> @@ -459,13 +458,13 @@ intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
>  				   const struct intel_shared_dpll *pll,
>  				   struct intel_shared_dpll_state *shared_dpll_state)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	struct intel_display *display = to_intel_display(crtc);
>  
> -	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
> +	drm_WARN_ON(display->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
>  
>  	shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
>  
> -	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
> +	drm_dbg_kms(display->drm, "[CRTC:%d:%s] releasing %s\n",
>  		    crtc->base.base.id, crtc->base.name, pll->info->name);
>  }
>  
> @@ -545,9 +544,8 @@ static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
>  	return val & DPLL_VCO_ENABLE;
>  }
>  
> -static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
> +static void ibx_assert_pch_refclk_enabled(struct intel_display *display)
>  {
> -	struct intel_display *display = &i915->display;
>  	u32 val;
>  	bool enabled;
>  
> @@ -562,12 +560,11 @@ static void ibx_pch_dpll_enable(struct intel_display *display,
>  				struct intel_shared_dpll *pll,
>  				const struct intel_dpll_hw_state *dpll_hw_state)
>  {
> -	struct drm_i915_private *i915 = to_i915(display->drm);
>  	const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
>  	const enum intel_dpll_id id = pll->info->id;
>  
>  	/* PCH refclock must be enabled first */
> -	ibx_assert_pch_refclk_enabled(i915);
> +	ibx_assert_pch_refclk_enabled(display);
>  
>  	intel_de_write(display, PCH_FP0(id), hw_state->fp0);
>  	intel_de_write(display, PCH_FP1(id), hw_state->fp1);
> @@ -1074,7 +1071,7 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
>  static int
>  hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	int clock = crtc_state->port_clock;
>  
>  	switch (clock / 2) {
> @@ -1083,7 +1080,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
>  	case 270000:
>  		return 0;
>  	default:
> -		drm_dbg_kms(&i915->drm, "Invalid clock for DP: %d\n",
> +		drm_dbg_kms(display->drm, "Invalid clock for DP: %d\n",
>  			    clock);
>  		return -EINVAL;
>  	}
> @@ -2255,7 +2252,7 @@ static int
>  bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  			  struct dpll *clk_div)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  
>  	/* Calculate HDMI div */
>  	/*
> @@ -2265,7 +2262,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  	if (!bxt_find_best_dpll(crtc_state, clk_div))
>  		return -EINVAL;
>  
> -	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
> +	drm_WARN_ON(display->drm, clk_div->m1 != 2);
>  
>  	return 0;
>  }
> @@ -2273,7 +2270,7 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
>  static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
>  				    struct dpll *clk_div)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	int i;
>  
>  	*clk_div = bxt_dp_clk_val[0];
> @@ -2284,16 +2281,16 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
>  		}
>  	}
>  
> -	chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
> +	chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);
>  
> -	drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
> +	drm_WARN_ON(display->drm, clk_div->vco == 0 ||
>  		    clk_div->dot != crtc_state->port_clock);
>  }
>  
>  static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
>  				     const struct dpll *clk_div)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct bxt_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.bxt;
>  	int clock = crtc_state->port_clock;
>  	int vco = clk_div->vco;
> @@ -2317,7 +2314,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
>  		gain_ctl = 1;
>  		targ_cnt = 9;
>  	} else {
> -		drm_err(&i915->drm, "Invalid VCO\n");
> +		drm_err(display->drm, "Invalid VCO\n");
>  		return -EINVAL;
>  	}
>  
> @@ -2700,9 +2697,9 @@ static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
>  static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
>  				 struct skl_wrpll_params *pll_params)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	const struct icl_combo_pll_params *params =
> -		i915->display.dpll.ref_clks.nssc == 24000 ?
> +		display->dpll.ref_clks.nssc == 24000 ?
>  		icl_dp_combo_pll_24MHz_values :
>  		icl_dp_combo_pll_19_2MHz_values;
>  	int clock = crtc_state->port_clock;
> @@ -2722,12 +2719,12 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
>  static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
>  			    struct skl_wrpll_params *pll_params)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  
> -	if (DISPLAY_VER(i915) >= 12) {
> -		switch (i915->display.dpll.ref_clks.nssc) {
> +	if (DISPLAY_VER(display) >= 12) {
> +		switch (display->dpll.ref_clks.nssc) {
>  		default:
> -			MISSING_CASE(i915->display.dpll.ref_clks.nssc);
> +			MISSING_CASE(display->dpll.ref_clks.nssc);
>  			fallthrough;
>  		case 19200:
>  		case 38400:
> @@ -2738,9 +2735,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
>  			break;
>  		}
>  	} else {
> -		switch (i915->display.dpll.ref_clks.nssc) {
> +		switch (display->dpll.ref_clks.nssc) {
>  		default:
> -			MISSING_CASE(i915->display.dpll.ref_clks.nssc);
> +			MISSING_CASE(display->dpll.ref_clks.nssc);
>  			fallthrough;
>  		case 19200:
>  		case 38400:
> @@ -2998,9 +2995,9 @@ static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>  static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  				 struct intel_dpll_hw_state *dpll_hw_state)
>  {
> -	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> -	int refclk_khz = i915->display.dpll.ref_clks.nssc;
> +	int refclk_khz = display->dpll.ref_clks.nssc;
>  	int clock = crtc_state->port_clock;
>  	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
>  	u32 iref_ndiv, iref_trim, iref_pulse_w;
> @@ -3010,7 +3007,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  	u64 tmp;
>  	bool use_ssc = false;
>  	bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
> -	bool is_dkl = DISPLAY_VER(i915) >= 12;
> +	bool is_dkl = DISPLAY_VER(display) >= 12;
>  	int ret;
>  
>  	ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
> @@ -3108,8 +3105,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
>  					 DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
>  					 DKL_PLL_DIV0_FBPREDIV(m1div) |
>  					 DKL_PLL_DIV0_FBDIV_INT(m2div_int);
> -		if (i915->display.vbt.override_afc_startup) {
> -			u8 val = i915->display.vbt.override_afc_startup_val;
> +		if (display->vbt.override_afc_startup) {
> +			u8 val = display->vbt.override_afc_startup_val;
>  
>  			hw_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
>  		}
> @@ -3347,7 +3344,6 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  				  struct intel_encoder *encoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct icl_port_dpll *port_dpll =
> @@ -3355,13 +3351,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  	enum port port = encoder->port;
>  	unsigned long dpll_mask;
>  
> -	if (IS_ALDERLAKE_S(i915)) {
> +	if (display->platform.alderlake_s) {
>  		dpll_mask =
>  			BIT(DPLL_ID_DG1_DPLL3) |
>  			BIT(DPLL_ID_DG1_DPLL2) |
>  			BIT(DPLL_ID_ICL_DPLL1) |
>  			BIT(DPLL_ID_ICL_DPLL0);
> -	} else if (IS_DG1(i915)) {
> +	} else if (display->platform.dg1) {
>  		if (port == PORT_D || port == PORT_E) {
>  			dpll_mask =
>  				BIT(DPLL_ID_DG1_DPLL2) |
> @@ -3371,12 +3367,13 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
>  				BIT(DPLL_ID_DG1_DPLL0) |
>  				BIT(DPLL_ID_DG1_DPLL1);
>  		}
> -	} else if (IS_ROCKETLAKE(i915)) {
> +	} else if (display->platform.rocketlake) {
>  		dpll_mask =
>  			BIT(DPLL_ID_EHL_DPLL4) |
>  			BIT(DPLL_ID_ICL_DPLL1) |
>  			BIT(DPLL_ID_ICL_DPLL0);
> -	} else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
> +	} else if ((display->platform.jasperlake ||
> +		    display->platform.elkhartlake) &&
>  		   port != PORT_A) {
>  		dpll_mask =
>  			BIT(DPLL_ID_EHL_DPLL4) |
> @@ -4381,10 +4378,10 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
>  			       struct intel_crtc *crtc,
>  			       struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> +	struct intel_display *display = to_intel_display(state);
> +	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>  
> -	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
> +	if (drm_WARN_ON(display->drm, !dpll_mgr))
>  		return -EINVAL;
>  
>  	return dpll_mgr->compute_dplls(state, crtc, encoder);
> @@ -4414,10 +4411,10 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
>  			       struct intel_crtc *crtc,
>  			       struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> +	struct intel_display *display = to_intel_display(state);
> +	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>  
> -	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
> +	if (drm_WARN_ON(display->drm, !dpll_mgr))
>  		return -EINVAL;
>  
>  	return dpll_mgr->get_dplls(state, crtc, encoder);
> @@ -4437,8 +4434,8 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
>  void intel_release_shared_dplls(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc)
>  {
> -	struct drm_i915_private *i915 = to_i915(state->base.dev);
> -	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> +	struct intel_display *display = to_intel_display(state);
> +	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>  
>  	/*
>  	 * FIXME: this function is called for every platform having a
> @@ -4466,10 +4463,10 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
>  			      struct intel_crtc *crtc,
>  			      struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -	const struct intel_dpll_mgr *dpll_mgr = i915->display.dpll.mgr;
> +	struct intel_display *display = to_intel_display(encoder);
> +	const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;
>  
> -	if (drm_WARN_ON(&i915->drm, !dpll_mgr))
> +	if (drm_WARN_ON(display->drm, !dpll_mgr))
>  		return;
>  
>  	dpll_mgr->update_active_dpll(state, crtc, encoder);

-- 
Jani Nikula, Intel

✓ CI.Patch_applied: success for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : success

== Summary ==

=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 27f9e4e38665 drm-tip: 2025y-02m-11d-09h-54m-33s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/display_debug_fs: Use intel_display wherever possible
Applying: drm/i915/display_debug_fs: Prefer using display->platform
Applying: drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
Applying: drm/i915/dpll: Use intel_display for dpll dump and compare hw state
Applying: drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
Applying: drm/i915/dpll: Use intel_display for asserting pll
Applying: drm/i915/dpll: Use intel_display for update_refclk hook
Applying: drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
Applying: drm/i915/dpll: Replace all other leftover drm_i915_private

✗ CI.checkpatch: warning for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
22f9cda3436b4fe965b5c5f31d2f2c1bcb483189
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1f3acac76736d9598784b153dd4d7f7d6c552dda
Author: Suraj Kandpal <suraj.kandpal@intel.com>
Date:   Tue Feb 11 16:18:57 2025 +0530

    drm/i915/dpll: Replace all other leftover drm_i915_private
    
    Replace all other left over drm_i915_private with intel_display
    in dpll_mgr.c.
    
    Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
+ /mt/dim checkpatch 27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f drm-intel
0c9c8fdd19b6 drm/i915/display_debug_fs: Use intel_display wherever possible
-:54: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 63)
#54: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:95:
+	if (DISPLAY_VER(display) >= 9)
 		/* no global SR status; inspect per-plane WM */;

total: 0 errors, 1 warnings, 0 checks, 507 lines checked
869c25c351e1 drm/i915/display_debug_fs: Prefer using display->platform
1eb71cbed5e8 drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
-:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__display' - possible side-effects?
#141: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_shared_dpll(__display, __pll, __i) \
+	for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
+		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)

-:141: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#141: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.h:33:
+#define for_each_shared_dpll(__display, __pll, __i) \
+	for ((__i) = 0; (__i) < (__display)->dpll.num_shared_dpll && \
+		     ((__pll) = &(__display)->dpll.shared_dplls[(__i)]) ; (__i)++)

total: 0 errors, 0 warnings, 2 checks, 218 lines checked
2efa14bd8694 drm/i915/dpll: Use intel_display for dpll dump and compare hw state
31f898c03ebf drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
fd69bc1f8d4d drm/i915/dpll: Use intel_display for asserting pll
52fd522258d2 drm/i915/dpll: Use intel_display for update_refclk hook
7a7e82d4ee53 drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
1f3acac76736 drm/i915/dpll: Replace all other leftover drm_i915_private

✓ CI.KUnit: success for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:51:20] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:51:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[11:51:50] Starting KUnit Kernel (1/1)...
[11:51:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:51:50] ================== guc_buf (11 subtests) ===================
[11:51:50] [PASSED] test_smallest
[11:51:50] [PASSED] test_largest
[11:51:50] [PASSED] test_granular
[11:51:50] [PASSED] test_unique
[11:51:50] [PASSED] test_overlap
[11:51:50] [PASSED] test_reusable
[11:51:50] [PASSED] test_too_big
[11:51:50] [PASSED] test_flush
[11:51:50] [PASSED] test_lookup
[11:51:50] [PASSED] test_data
[11:51:50] [PASSED] test_class
[11:51:50] ===================== [PASSED] guc_buf =====================
[11:51:50] =================== guc_dbm (7 subtests) ===================
[11:51:50] [PASSED] test_empty
[11:51:50] [PASSED] test_default
[11:51:50] ======================== test_size  ========================
[11:51:50] [PASSED] 4
[11:51:50] [PASSED] 8
[11:51:50] [PASSED] 32
[11:51:50] [PASSED] 256
[11:51:50] ==================== [PASSED] test_size ====================
[11:51:50] ======================= test_reuse  ========================
[11:51:50] [PASSED] 4
[11:51:50] [PASSED] 8
[11:51:50] [PASSED] 32
[11:51:50] [PASSED] 256
[11:51:50] =================== [PASSED] test_reuse ====================
[11:51:50] =================== test_range_overlap  ====================
[11:51:50] [PASSED] 4
[11:51:50] [PASSED] 8
[11:51:50] [PASSED] 32
[11:51:50] [PASSED] 256
[11:51:50] =============== [PASSED] test_range_overlap ================
[11:51:50] =================== test_range_compact  ====================
[11:51:50] [PASSED] 4
[11:51:50] [PASSED] 8
[11:51:50] [PASSED] 32
[11:51:50] [PASSED] 256
[11:51:50] =============== [PASSED] test_range_compact ================
[11:51:50] ==================== test_range_spare  =====================
[11:51:50] [PASSED] 4
[11:51:50] [PASSED] 8
[11:51:50] [PASSED] 32
[11:51:50] [PASSED] 256
[11:51:50] ================ [PASSED] test_range_spare =================
[11:51:50] ===================== [PASSED] guc_dbm =====================
[11:51:50] =================== guc_idm (6 subtests) ===================
[11:51:50] [PASSED] bad_init
[11:51:50] [PASSED] no_init
[11:51:50] [PASSED] init_fini
[11:51:50] [PASSED] check_used
[11:51:50] [PASSED] check_quota
[11:51:50] [PASSED] check_all
[11:51:50] ===================== [PASSED] guc_idm =====================
[11:51:50] ================== no_relay (3 subtests) ===================
[11:51:50] [PASSED] xe_drops_guc2pf_if_not_ready
[11:51:50] [PASSED] xe_drops_guc2vf_if_not_ready
[11:51:50] [PASSED] xe_rejects_send_if_not_ready
[11:51:50] ==================== [PASSED] no_relay =====================
[11:51:50] ================== pf_relay (14 subtests) ==================
[11:51:50] [PASSED] pf_rejects_guc2pf_too_short
[11:51:50] [PASSED] pf_rejects_guc2pf_too_long
[11:51:50] [PASSED] pf_rejects_guc2pf_no_payload
[11:51:50] [PASSED] pf_fails_no_payload
[11:51:50] [PASSED] pf_fails_bad_origin
[11:51:50] [PASSED] pf_fails_bad_type
[11:51:50] [PASSED] pf_txn_reports_error
[11:51:50] [PASSED] pf_txn_sends_pf2guc
[11:51:50] [PASSED] pf_sends_pf2guc
[11:51:50] [SKIPPED] pf_loopback_nop
[11:51:50] [SKIPPED] pf_loopback_echo
[11:51:50] [SKIPPED] pf_loopback_fail
[11:51:50] [SKIPPED] pf_loopback_busy
[11:51:50] [SKIPPED] pf_loopback_retry
[11:51:50] ==================== [PASSED] pf_relay =====================
[11:51:50] ================== vf_relay (3 subtests) ===================
[11:51:50] [PASSED] vf_rejects_guc2vf_too_short
[11:51:50] [PASSED] vf_rejects_guc2vf_too_long
[11:51:50] [PASSED] vf_rejects_guc2vf_no_payload
[11:51:50] ==================== [PASSED] vf_relay =====================
[11:51:50] ================= pf_service (11 subtests) =================
[11:51:50] [PASSED] pf_negotiate_any
[11:51:50] [PASSED] pf_negotiate_base_match
[11:51:50] [PASSED] pf_negotiate_base_newer
[11:51:50] [PASSED] pf_negotiate_base_next
[11:51:50] [SKIPPED] pf_negotiate_base_older
[11:51:50] [PASSED] pf_negotiate_base_prev
[11:51:50] [PASSED] pf_negotiate_latest_match
[11:51:50] [PASSED] pf_negotiate_latest_newer
[11:51:50] [PASSED] pf_negotiate_latest_next
[11:51:50] [SKIPPED] pf_negotiate_latest_older
[11:51:50] [SKIPPED] pf_negotiate_latest_prev
[11:51:50] =================== [PASSED] pf_service ====================
[11:51:50] ===================== lmtt (1 subtest) =====================
[11:51:50] ======================== test_ops  =========================
[11:51:50] [PASSED] 2-level
[11:51:50] [PASSED] multi-level
[11:51:50] ==================== [PASSED] test_ops =====================
[11:51:50] ====================== [PASSED] lmtt =======================
[11:51:50] =================== xe_mocs (2 subtests) ===================
[11:51:50] ================ xe_live_mocs_kernel_kunit  ================
[11:51:50] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:51:50] ================ xe_live_mocs_reset_kunit  =================
[11:51:50] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:51:50] ==================== [SKIPPED] xe_mocs =====================
[11:51:50] ================= xe_migrate (2 subtests) ==================
[11:51:50] ================= xe_migrate_sanity_kunit  =================
[11:51:50] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:51:50] ================== xe_validate_ccs_kunit  ==================
[11:51:50] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:51:50] =================== [SKIPPED] xe_migrate ===================
[11:51:50] ================== xe_dma_buf (1 subtest) ==================
[11:51:50] ==================== xe_dma_buf_kunit  =====================
[11:51:50] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:51:50] =================== [SKIPPED] xe_dma_buf ===================
[11:51:50] ================= xe_bo_shrink (1 subtest) =================
[11:51:50] =================== xe_bo_shrink_kunit  ====================
[11:51:50] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:51:50] ================== [SKIPPED] xe_bo_shrink ==================
[11:51:50] ==================== xe_bo (2 subtests) ====================
[11:51:50] ================== xe_ccs_migrate_kunit  ===================
[11:51:50] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
stty: 'standard input': Inappropriate ioctl for device
[11:51:50] ==================== xe_bo_evict_kunit  ====================
[11:51:50] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:51:50] ===================== [SKIPPED] xe_bo ======================
[11:51:50] ==================== args (11 subtests) ====================
[11:51:50] [PASSED] count_args_test
[11:51:50] [PASSED] call_args_example
[11:51:50] [PASSED] call_args_test
[11:51:50] [PASSED] drop_first_arg_example
[11:51:50] [PASSED] drop_first_arg_test
[11:51:50] [PASSED] first_arg_example
[11:51:50] [PASSED] first_arg_test
[11:51:50] [PASSED] last_arg_example
[11:51:50] [PASSED] last_arg_test
[11:51:50] [PASSED] pick_arg_example
[11:51:50] [PASSED] sep_comma_example
[11:51:50] ====================== [PASSED] args =======================
[11:51:50] =================== xe_pci (2 subtests) ====================
[11:51:50] [PASSED] xe_gmdid_graphics_ip
[11:51:50] [PASSED] xe_gmdid_media_ip
[11:51:50] ===================== [PASSED] xe_pci ======================
[11:51:50] =================== xe_rtp (2 subtests) ====================
[11:51:50] =============== xe_rtp_process_to_sr_tests  ================
[11:51:50] [PASSED] coalesce-same-reg
[11:51:50] [PASSED] no-match-no-add
[11:51:50] [PASSED] match-or
[11:51:50] [PASSED] match-or-xfail
[11:51:50] [PASSED] no-match-no-add-multiple-rules
[11:51:50] [PASSED] two-regs-two-entries
[11:51:50] [PASSED] clr-one-set-other
[11:51:50] [PASSED] set-field
[11:51:50] [PASSED] conflict-duplicate
[11:51:50] [PASSED] conflict-not-disjoint
[11:51:50] [PASSED] conflict-reg-type
[11:51:50] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:51:50] ================== xe_rtp_process_tests  ===================
[11:51:50] [PASSED] active1
[11:51:50] [PASSED] active2
[11:51:50] [PASSED] active-inactive
[11:51:50] [PASSED] inactive-active
[11:51:50] [PASSED] inactive-1st_or_active-inactive
[11:51:50] [PASSED] inactive-2nd_or_active-inactive
[11:51:50] [PASSED] inactive-last_or_active-inactive
[11:51:50] [PASSED] inactive-no_or_active-inactive
[11:51:50] ============== [PASSED] xe_rtp_process_tests ===============
[11:51:50] ===================== [PASSED] xe_rtp ======================
[11:51:50] ==================== xe_wa (1 subtest) =====================
[11:51:50] ======================== xe_wa_gt  =========================
[11:51:50] [PASSED] TIGERLAKE (B0)
[11:51:50] [PASSED] DG1 (A0)
[11:51:50] [PASSED] DG1 (B0)
[11:51:50] [PASSED] ALDERLAKE_S (A0)
[11:51:50] [PASSED] ALDERLAKE_S (B0)
[11:51:50] [PASSED] ALDERLAKE_S (C0)
[11:51:50] [PASSED] ALDERLAKE_S (D0)
[11:51:50] [PASSED] ALDERLAKE_P (A0)
[11:51:50] [PASSED] ALDERLAKE_P (B0)
[11:51:50] [PASSED] ALDERLAKE_P (C0)
[11:51:50] [PASSED] ALDERLAKE_S_RPLS (D0)
[11:51:50] [PASSED] ALDERLAKE_P_RPLU (E0)
[11:51:50] [PASSED] DG2_G10 (C0)
[11:51:50] [PASSED] DG2_G11 (B1)
[11:51:50] [PASSED] DG2_G12 (A1)
[11:51:50] [PASSED] METEORLAKE (g:A0, m:A0)
[11:51:50] [PASSED] METEORLAKE (g:A0, m:A0)
[11:51:50] [PASSED] METEORLAKE (g:A0, m:A0)
[11:51:50] [PASSED] LUNARLAKE (g:A0, m:A0)
[11:51:50] [PASSED] LUNARLAKE (g:B0, m:A0)
[11:51:50] [PASSED] BATTLEMAGE (g:A0, m:A1)
[11:51:50] ==================== [PASSED] xe_wa_gt =====================
[11:51:50] ====================== [PASSED] xe_wa ======================
[11:51:50] ============================================================
[11:51:50] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[11:51:50] Elapsed time: 30.354s total, 4.117s configuring, 25.971s building, 0.252s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:51:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:51:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
  156 | u64 ioread64_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
  163 | u64 ioread64_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
  170 | u64 ioread64be_lo_hi(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
  178 | u64 ioread64be_hi_lo(const void __iomem *addr)
      |     ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
  264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
  272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
  280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
  288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
      |      ^~~~~~~~~~~~~~~~~

[11:52:13] Starting KUnit Kernel (1/1)...
[11:52:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:52:13] =========== drm_validate_clone_mode (2 subtests) ===========
[11:52:13] ============== drm_test_check_in_clone_mode  ===============
[11:52:13] [PASSED] in_clone_mode
[11:52:13] [PASSED] not_in_clone_mode
[11:52:13] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:52:13] =============== drm_test_check_valid_clones  ===============
[11:52:13] [PASSED] not_in_clone_mode
[11:52:13] [PASSED] valid_clone
[11:52:13] [PASSED] invalid_clone
[11:52:13] =========== [PASSED] drm_test_check_valid_clones ===========
[11:52:13] ============= [PASSED] drm_validate_clone_mode =============
[11:52:13] ============= drm_validate_modeset (1 subtest) =============
[11:52:13] [PASSED] drm_test_check_connector_changed_modeset
[11:52:13] ============== [PASSED] drm_validate_modeset ===============
[11:52:13] ================== drm_buddy (7 subtests) ==================
[11:52:13] [PASSED] drm_test_buddy_alloc_limit
[11:52:13] [PASSED] drm_test_buddy_alloc_optimistic
[11:52:13] [PASSED] drm_test_buddy_alloc_pessimistic
[11:52:13] [PASSED] drm_test_buddy_alloc_pathological
[11:52:13] [PASSED] drm_test_buddy_alloc_contiguous
[11:52:13] [PASSED] drm_test_buddy_alloc_clear
[11:52:13] [PASSED] drm_test_buddy_alloc_range_bias
[11:52:13] ==================== [PASSED] drm_buddy ====================
[11:52:13] ============= drm_cmdline_parser (40 subtests) =============
[11:52:13] [PASSED] drm_test_cmdline_force_d_only
[11:52:13] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:52:13] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:52:13] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:52:13] [PASSED] drm_test_cmdline_force_e_only
[11:52:13] [PASSED] drm_test_cmdline_res
[11:52:13] [PASSED] drm_test_cmdline_res_vesa
[11:52:13] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:52:13] [PASSED] drm_test_cmdline_res_rblank
[11:52:13] [PASSED] drm_test_cmdline_res_bpp
[11:52:13] [PASSED] drm_test_cmdline_res_refresh
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:52:13] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:52:13] [PASSED] drm_test_cmdline_res_margins_force_on
[11:52:13] [PASSED] drm_test_cmdline_res_vesa_margins
[11:52:13] [PASSED] drm_test_cmdline_name
[11:52:13] [PASSED] drm_test_cmdline_name_bpp
[11:52:13] [PASSED] drm_test_cmdline_name_option
[11:52:13] [PASSED] drm_test_cmdline_name_bpp_option
[11:52:13] [PASSED] drm_test_cmdline_rotate_0
[11:52:13] [PASSED] drm_test_cmdline_rotate_90
[11:52:13] [PASSED] drm_test_cmdline_rotate_180
[11:52:13] [PASSED] drm_test_cmdline_rotate_270
[11:52:13] [PASSED] drm_test_cmdline_hmirror
[11:52:13] [PASSED] drm_test_cmdline_vmirror
[11:52:13] [PASSED] drm_test_cmdline_margin_options
[11:52:13] [PASSED] drm_test_cmdline_multiple_options
[11:52:13] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:52:13] [PASSED] drm_test_cmdline_extra_and_option
[11:52:13] [PASSED] drm_test_cmdline_freestanding_options
[11:52:13] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:52:13] [PASSED] drm_test_cmdline_panel_orientation
[11:52:13] ================ drm_test_cmdline_invalid  =================
[11:52:13] [PASSED] margin_only
[11:52:13] [PASSED] interlace_only
[11:52:13] [PASSED] res_missing_x
[11:52:13] [PASSED] res_missing_y
[11:52:13] [PASSED] res_bad_y
[11:52:13] [PASSED] res_missing_y_bpp
[11:52:13] [PASSED] res_bad_bpp
[11:52:13] [PASSED] res_bad_refresh
[11:52:13] [PASSED] res_bpp_refresh_force_on_off
[11:52:13] [PASSED] res_invalid_mode
[11:52:13] [PASSED] res_bpp_wrong_place_mode
[11:52:13] [PASSED] name_bpp_refresh
[11:52:13] [PASSED] name_refresh
[11:52:13] [PASSED] name_refresh_wrong_mode
[11:52:13] [PASSED] name_refresh_invalid_mode
[11:52:13] [PASSED] rotate_multiple
[11:52:13] [PASSED] rotate_invalid_val
[11:52:13] [PASSED] rotate_truncated
[11:52:13] [PASSED] invalid_option
[11:52:13] [PASSED] invalid_tv_option
[11:52:13] [PASSED] truncated_tv_option
[11:52:13] ============ [PASSED] drm_test_cmdline_invalid =============
[11:52:13] =============== drm_test_cmdline_tv_options  ===============
[11:52:13] [PASSED] NTSC
[11:52:13] [PASSED] NTSC_443
[11:52:13] [PASSED] NTSC_J
[11:52:13] [PASSED] PAL
[11:52:13] [PASSED] PAL_M
[11:52:13] [PASSED] PAL_N
[11:52:13] [PASSED] SECAM
[11:52:13] [PASSED] MONO_525
[11:52:13] [PASSED] MONO_625
[11:52:13] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:52:13] =============== [PASSED] drm_cmdline_parser ================
[11:52:13] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:52:13] [PASSED] drm_test_connector_hdmi_init_valid
[11:52:13] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:52:13] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:52:13] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:52:13] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:52:13] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:52:13] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:52:13] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:52:13] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:52:13] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:52:13] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:52:13] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:52:13] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:52:13] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:52:13] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:52:13] [PASSED] drm_test_connector_hdmi_init_null_product
[11:52:13] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:52:13] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:52:13] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:52:13] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:52:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:52:13] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:52:13] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:52:13] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:52:13] [PASSED] HDMI-A
[11:52:13] [PASSED] HDMI-B
[11:52:13] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:52:13] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:52:13] [PASSED] Unknown
[11:52:13] [PASSED] VGA
[11:52:13] [PASSED] DVI-I
[11:52:13] [PASSED] DVI-D
[11:52:13] [PASSED] DVI-A
[11:52:13] [PASSED] Composite
[11:52:13] [PASSED] SVIDEO
[11:52:13] [PASSED] LVDS
[11:52:13] [PASSED] Component
[11:52:13] [PASSED] DIN
[11:52:13] [PASSED] DP
[11:52:13] [PASSED] TV
[11:52:13] [PASSED] eDP
[11:52:13] [PASSED] Virtual
[11:52:13] [PASSED] DSI
[11:52:13] [PASSED] DPI
[11:52:13] [PASSED] Writeback
[11:52:13] [PASSED] SPI
[11:52:13] [PASSED] USB
[11:52:13] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:52:13] ============ [PASSED] drmm_connector_hdmi_init =============
[11:52:13] ============= drmm_connector_init (3 subtests) =============
[11:52:13] [PASSED] drm_test_drmm_connector_init
[11:52:13] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:52:13] ========= drm_test_drmm_connector_init_type_valid  =========
[11:52:13] [PASSED] Unknown
[11:52:13] [PASSED] VGA
[11:52:13] [PASSED] DVI-I
[11:52:13] [PASSED] DVI-D
[11:52:13] [PASSED] DVI-A
[11:52:13] [PASSED] Composite
[11:52:13] [PASSED] SVIDEO
[11:52:13] [PASSED] LVDS
[11:52:13] [PASSED] Component
[11:52:13] [PASSED] DIN
[11:52:13] [PASSED] DP
[11:52:13] [PASSED] HDMI-A
[11:52:13] [PASSED] HDMI-B
[11:52:13] [PASSED] TV
[11:52:13] [PASSED] eDP
[11:52:13] [PASSED] Virtual
[11:52:13] [PASSED] DSI
[11:52:13] [PASSED] DPI
[11:52:13] [PASSED] Writeback
[11:52:13] [PASSED] SPI
[11:52:13] [PASSED] USB
[11:52:13] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:52:13] =============== [PASSED] drmm_connector_init ===============
[11:52:13] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_init
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:52:13] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:52:13] [PASSED] Unknown
[11:52:13] [PASSED] VGA
[11:52:13] [PASSED] DVI-I
[11:52:13] [PASSED] DVI-D
[11:52:13] [PASSED] DVI-A
[11:52:13] [PASSED] Composite
[11:52:13] [PASSED] SVIDEO
[11:52:13] [PASSED] LVDS
[11:52:13] [PASSED] Component
[11:52:13] [PASSED] DIN
[11:52:13] [PASSED] DP
[11:52:13] [PASSED] HDMI-A
[11:52:13] [PASSED] HDMI-B
[11:52:13] [PASSED] TV
[11:52:13] [PASSED] eDP
[11:52:13] [PASSED] Virtual
[11:52:13] [PASSED] DSI
[11:52:13] [PASSED] DPI
[11:52:13] [PASSED] Writeback
[11:52:13] [PASSED] SPI
[11:52:13] [PASSED] USB
[11:52:13] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:52:13] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:52:13] [PASSED] Unknown
[11:52:13] [PASSED] VGA
[11:52:13] [PASSED] DVI-I
[11:52:13] [PASSED] DVI-D
[11:52:13] [PASSED] DVI-A
[11:52:13] [PASSED] Composite
[11:52:13] [PASSED] SVIDEO
[11:52:13] [PASSED] LVDS
[11:52:13] [PASSED] Component
[11:52:13] [PASSED] DIN
[11:52:13] [PASSED] DP
[11:52:13] [PASSED] HDMI-A
[11:52:13] [PASSED] HDMI-B
[11:52:13] [PASSED] TV
[11:52:13] [PASSED] eDP
[11:52:13] [PASSED] Virtual
[11:52:13] [PASSED] DSI
[11:52:13] [PASSED] DPI
[11:52:13] [PASSED] Writeback
[11:52:13] [PASSED] SPI
[11:52:13] [PASSED] USB
[11:52:13] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:52:13] =========== [PASSED] drm_connector_dynamic_init ============
[11:52:13] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:52:13] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:52:13] ======= drm_connector_dynamic_register (7 subtests) ========
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:52:13] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:52:13] ========= [PASSED] drm_connector_dynamic_register ==========
[11:52:13] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:52:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:52:13] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:52:13] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:52:13] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:52:13] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:52:13] [PASSED] NTSC
[11:52:13] [PASSED] NTSC-443
[11:52:13] [PASSED] NTSC-J
[11:52:13] [PASSED] PAL
[11:52:13] [PASSED] PAL-M
[11:52:13] [PASSED] PAL-N
[11:52:13] [PASSED] SECAM
[11:52:13] [PASSED] Mono
[11:52:13] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:52:13] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:52:13] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:52:13] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:52:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:52:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:52:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:52:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:52:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:52:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:52:13] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:52:13] [PASSED] VIC 96
[11:52:13] [PASSED] VIC 97
[11:52:13] [PASSED] VIC 101
[11:52:13] [PASSED] VIC 102
[11:52:13] [PASSED] VIC 106
[11:52:13] [PASSED] VIC 107
[11:52:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:52:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:52:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:52:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:52:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:52:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:52:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:52:13] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:52:13] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:52:13] [PASSED] Automatic
[11:52:13] [PASSED] Full
[11:52:13] [PASSED] Limited 16:235
[11:52:13] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:52:13] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:52:13] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:52:13] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:52:13] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:52:13] [PASSED] RGB
[11:52:13] [PASSED] YUV 4:2:0
[11:52:13] [PASSED] YUV 4:2:2
[11:52:13] [PASSED] YUV 4:4:4
[11:52:13] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:52:13] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:52:13] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:52:13] ============= drm_damage_helper (21 subtests) ==============
[11:52:13] [PASSED] drm_test_damage_iter_no_damage
[11:52:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:52:13] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:52:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:52:13] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:52:13] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:52:13] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:52:13] [PASSED] drm_test_damage_iter_simple_damage
[11:52:13] [PASSED] drm_test_damage_iter_single_damage
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:52:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:52:13] [PASSED] drm_test_damage_iter_damage
[11:52:13] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:52:13] [PASSED] drm_test_damage_iter_damage_one_outside
[11:52:13] [PASSED] drm_test_damage_iter_damage_src_moved
[11:52:13] [PASSED] drm_test_damage_iter_damage_not_visible
[11:52:13] ================ [PASSED] drm_damage_helper ================
[11:52:13] ============== drm_dp_mst_helper (3 subtests) ==============
[11:52:13] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:52:13] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:52:13] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:52:13] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:52:13] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:52:13] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:52:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:52:13] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:52:13] [PASSED] Link rate 2000000 lane count 4
[11:52:13] [PASSED] Link rate 2000000 lane count 2
[11:52:13] [PASSED] Link rate 2000000 lane count 1
[11:52:13] [PASSED] Link rate 1350000 lane count 4
[11:52:13] [PASSED] Link rate 1350000 lane count 2
[11:52:13] [PASSED] Link rate 1350000 lane count 1
[11:52:13] [PASSED] Link rate 1000000 lane count 4
[11:52:13] [PASSED] Link rate 1000000 lane count 2
[11:52:13] [PASSED] Link rate 1000000 lane count 1
[11:52:13] [PASSED] Link rate 810000 lane count 4
[11:52:13] [PASSED] Link rate 810000 lane count 2
[11:52:13] [PASSED] Link rate 810000 lane count 1
[11:52:13] [PASSED] Link rate 540000 lane count 4
[11:52:13] [PASSED] Link rate 540000 lane count 2
[11:52:13] [PASSED] Link rate 540000 lane count 1
[11:52:13] [PASSED] Link rate 270000 lane count 4
[11:52:13] [PASSED] Link rate 270000 lane count 2
[11:52:13] [PASSED] Link rate 270000 lane count 1
[11:52:13] [PASSED] Link rate 162000 lane count 4
[11:52:13] [PASSED] Link rate 162000 lane count 2
[11:52:13] [PASSED] Link rate 162000 lane count 1
[11:52:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:52:13] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:52:13] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:52:13] [PASSED] DP_POWER_UP_PHY with port number
[11:52:13] [PASSED] DP_POWER_DOWN_PHY with port number
[11:52:13] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:52:13] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:52:13] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:52:13] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:52:13] [PASSED] DP_QUERY_PAYLOAD with port number
[11:52:13] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:52:13] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:52:13] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:52:13] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:52:13] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:52:13] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:52:13] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:52:13] [PASSED] DP_REMOTE_I2C_READ with port number
[11:52:13] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:52:13] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:52:13] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:52:13] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:52:13] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:52:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:52:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:52:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:52:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:52:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:52:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:52:13] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:52:13] ================ [PASSED] drm_dp_mst_helper ================
[11:52:13] ================== drm_exec (7 subtests) ===================
[11:52:13] [PASSED] sanitycheck
[11:52:13] [PASSED] test_lock
[11:52:13] [PASSED] test_lock_unlock
[11:52:13] [PASSED] test_duplicates
[11:52:13] [PASSED] test_prepare
[11:52:13] [PASSED] test_prepare_array
[11:52:13] [PASSED] test_multiple_loops
[11:52:13] ==================== [PASSED] drm_exec =====================
[11:52:13] =========== drm_format_helper_test (17 subtests) ===========
[11:52:13] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:52:13] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:52:13] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:52:13] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:52:13] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:52:13] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:52:13] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:52:13] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:52:13] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:52:13] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:52:13] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:52:13] ==================== drm_test_fb_swab  =====================
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ================ [PASSED] drm_test_fb_swab =================
[11:52:13] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:52:13] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:52:13] [PASSED] single_pixel_source_buffer
[11:52:13] [PASSED] single_pixel_clip_rectangle
[11:52:13] [PASSED] well_known_colors
[11:52:13] [PASSED] destination_pitch
[11:52:13] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:52:13] ================= drm_test_fb_clip_offset  =================
[11:52:13] [PASSED] pass through
[11:52:13] [PASSED] horizontal offset
[11:52:13] [PASSED] vertical offset
[11:52:13] [PASSED] horizontal and vertical offset
[11:52:13] [PASSED] horizontal offset (custom pitch)
[11:52:13] [PASSED] vertical offset (custom pitch)
[11:52:13] [PASSED] horizontal and vertical offset (custom pitch)
[11:52:13] ============= [PASSED] drm_test_fb_clip_offset =============
[11:52:13] ============== drm_test_fb_build_fourcc_list  ==============
[11:52:13] [PASSED] no native formats
[11:52:13] [PASSED] XRGB8888 as native format
[11:52:13] [PASSED] remove duplicates
[11:52:13] [PASSED] convert alpha formats
[11:52:13] [PASSED] random formats
[11:52:13] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[11:52:13] =================== drm_test_fb_memcpy  ====================
[11:52:13] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:52:13] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:52:13] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:52:13] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:52:13] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:52:13] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:52:13] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:52:13] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:52:13] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:52:13] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:52:13] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:52:13] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:52:13] =============== [PASSED] drm_test_fb_memcpy ================
[11:52:13] ============= [PASSED] drm_format_helper_test ==============
[11:52:13] ================= drm_format (18 subtests) =================
[11:52:13] [PASSED] drm_test_format_block_width_invalid
[11:52:13] [PASSED] drm_test_format_block_width_one_plane
[11:52:13] [PASSED] drm_test_format_block_width_two_plane
[11:52:13] [PASSED] drm_test_format_block_width_three_plane
[11:52:13] [PASSED] drm_test_format_block_width_tiled
[11:52:13] [PASSED] drm_test_format_block_height_invalid
[11:52:13] [PASSED] drm_test_format_block_height_one_plane
[11:52:13] [PASSED] drm_test_format_block_height_two_plane
[11:52:13] [PASSED] drm_test_format_block_height_three_plane
[11:52:13] [PASSED] drm_test_format_block_height_tiled
[11:52:13] [PASSED] drm_test_format_min_pitch_invalid
[11:52:13] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:52:13] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:52:13] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:52:13] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:52:13] [PASSED] drm_test_format_min_pitch_two_plane
[11:52:13] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:52:13] [PASSED] drm_test_format_min_pitch_tiled
[11:52:13] =================== [PASSED] drm_format ====================
[11:52:13] ============== drm_framebuffer (10 subtests) ===============
[11:52:13] ========== drm_test_framebuffer_check_src_coords  ==========
[11:52:13] [PASSED] Success: source fits into fb
[11:52:13] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:52:13] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:52:13] [PASSED] Fail: overflowing fb with source width
[11:52:13] [PASSED] Fail: overflowing fb with source height
[11:52:13] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:52:13] [PASSED] drm_test_framebuffer_cleanup
[11:52:13] =============== drm_test_framebuffer_create  ===============
[11:52:13] [PASSED] ABGR8888 normal sizes
[11:52:13] [PASSED] ABGR8888 max sizes
[11:52:13] [PASSED] ABGR8888 pitch greater than min required
[11:52:13] [PASSED] ABGR8888 pitch less than min required
[11:52:13] [PASSED] ABGR8888 Invalid width
[11:52:13] [PASSED] ABGR8888 Invalid buffer handle
[11:52:13] [PASSED] No pixel format
[11:52:13] [PASSED] ABGR8888 Width 0
[11:52:13] [PASSED] ABGR8888 Height 0
[11:52:13] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:52:13] [PASSED] ABGR8888 Large buffer offset
[11:52:13] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:52:13] [PASSED] ABGR8888 Invalid flag
[11:52:13] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:52:13] [PASSED] ABGR8888 Valid buffer modifier
[11:52:13] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:52:13] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] NV12 Normal sizes
[11:52:13] [PASSED] NV12 Max sizes
[11:52:13] [PASSED] NV12 Invalid pitch
[11:52:13] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:52:13] [PASSED] NV12 different  modifier per-plane
[11:52:13] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:52:13] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] NV12 Modifier for inexistent plane
[11:52:13] [PASSED] NV12 Handle for inexistent plane
[11:52:13] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:52:13] [PASSED] YVU420 Normal sizes
[11:52:13] [PASSED] YVU420 Max sizes
[11:52:13] [PASSED] YVU420 Invalid pitch
[11:52:13] [PASSED] YVU420 Different pitches
[11:52:13] [PASSED] YVU420 Different buffer offsets/pitches
[11:52:13] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:52:13] [PASSED] YVU420 Valid modifier
[11:52:13] [PASSED] YVU420 Different modifiers per plane
[11:52:13] [PASSED] YVU420 Modifier for inexistent plane
[11:52:13] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:52:13] [PASSED] X0L2 Normal sizes
[11:52:13] [PASSED] X0L2 Max sizes
[11:52:13] [PASSED] X0L2 Invalid pitch
[11:52:13] [PASSED] X0L2 Pitch greater than minimum required
[11:52:13] [PASSED] X0L2 Handle for inexistent plane
[11:52:13] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:52:13] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:52:13] [PASSED] X0L2 Valid modifier
[11:52:13] [PASSED] X0L2 Modifier for inexistent plane
[11:52:13] =========== [PASSED] drm_test_framebuffer_create ===========
[11:52:13] [PASSED] drm_test_framebuffer_free
[11:52:13] [PASSED] drm_test_framebuffer_init
[11:52:13] [PASSED] drm_test_framebuffer_init_bad_format
[11:52:13] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:52:13] [PASSED] drm_test_framebuffer_lookup
[11:52:13] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:52:13] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:52:13] ================= [PASSED] drm_framebuffer =================
[11:52:13] ================ drm_gem_shmem (8 subtests) ================
[11:52:13] [PASSED] drm_gem_shmem_test_obj_create
[11:52:13] [PASSED] drm_gem_shmem_test_obj_create_private
[11:52:13] [PASSED] drm_gem_shmem_test_pin_pages
[11:52:13] [PASSED] drm_gem_shmem_test_vmap
[11:52:13] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:52:13] [PASSED] drm_gem_shmem_test_get_sg_table
[11:52:13] [PASSED] drm_gem_shmem_test_madvise
[11:52:13] [PASSED] drm_gem_shmem_test_purge
[11:52:13] ================== [PASSED] drm_gem_shmem ==================
[11:52:13] === drm_atomic_helper_connector_hdmi_check (23 subtests) ===
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:52:13] [PASSED] drm_test_check_disable_connector
[11:52:13] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:52:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[11:52:13] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[11:52:13] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:52:13] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:52:13] [PASSED] drm_test_check_output_bpc_dvi
[11:52:13] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:52:13] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:52:13] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:52:13] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:52:13] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:52:13] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:52:13] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:52:13] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:52:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:52:13] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:52:13] [PASSED] drm_test_check_broadcast_rgb_value
[11:52:13] [PASSED] drm_test_check_bpc_8_value
[11:52:13] [PASSED] drm_test_check_bpc_10_value
[11:52:13] [PASSED] drm_test_check_bpc_12_value
[11:52:13] [PASSED] drm_test_check_format_value
[11:52:13] [PASSED] drm_test_check_tmds_char_value
[11:52:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:52:13] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:52:13] [PASSED] drm_test_check_mode_valid
[11:52:13] [PASSED] drm_test_check_mode_valid_reject
[11:52:13] [PASSED] drm_test_check_mode_valid_reject_rate
[11:52:13] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:52:13] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:52:13] ================= drm_managed (2 subtests) =================
[11:52:13] [PASSED] drm_test_managed_release_action
[11:52:13] [PASSED] drm_test_managed_run_action
[11:52:13] =================== [PASSED] drm_managed ===================
[11:52:13] =================== drm_mm (6 subtests) ====================
[11:52:13] [PASSED] drm_test_mm_init
[11:52:13] [PASSED] drm_test_mm_debug
[11:52:13] [PASSED] drm_test_mm_align32
[11:52:13] [PASSED] drm_test_mm_align64
[11:52:13] [PASSED] drm_test_mm_lowest
[11:52:13] [PASSED] drm_test_mm_highest
[11:52:13] ===================== [PASSED] drm_mm ======================
[11:52:13] ============= drm_modes_analog_tv (5 subtests) =============
[11:52:13] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:52:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:52:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:52:13] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:52:13] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:52:13] =============== [PASSED] drm_modes_analog_tv ===============
[11:52:13] ============== drm_plane_helper (2 subtests) ===============
[11:52:13] =============== drm_test_check_plane_state  ================
[11:52:13] [PASSED] clipping_simple
[11:52:13] [PASSED] clipping_rotate_reflect
[11:52:13] [PASSED] positioning_simple
[11:52:13] [PASSED] upscaling
[11:52:13] [PASSED] downscaling
[11:52:13] [PASSED] rounding1
[11:52:13] [PASSED] rounding2
[11:52:13] [PASSED] rounding3
[11:52:13] [PASSED] rounding4
[11:52:13] =========== [PASSED] drm_test_check_plane_state ============
[11:52:13] =========== drm_test_check_invalid_plane_state  ============
[11:52:13] [PASSED] positioning_invalid
[11:52:13] [PASSED] upscaling_invalid
[11:52:13] [PASSED] downscaling_invalid
[11:52:13] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:52:13] ================ [PASSED] drm_plane_helper =================
[11:52:13] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:52:13] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:52:13] [PASSED] None
[11:52:13] [PASSED] PAL
[11:52:13] [PASSED] NTSC
[11:52:13] [PASSED] Both, NTSC Default
[11:52:13] [PASSED] Both, PAL Default
[11:52:13] [PASSED] Both, NTSC Default, with PAL on command-line
[11:52:13] [PASSED] Both, PAL Default, with NTSC on command-line
[11:52:13] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:52:13] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:52:13] ================== drm_rect (9 subtests) ===================
[11:52:13] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:52:13] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:52:13] [PASSED] drm_test_rect_clip_scaled_clipped
[11:52:13] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:52:13] ================= drm_test_rect_intersect  =================
[11:52:13] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:52:13] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:52:13] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:52:13] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:52:13] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:52:13] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:52:13] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:52:13] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:52:13] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:52:13] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:52:13] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:52:13] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:52:13] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:52:13] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:52:13] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:52:13] ============= [PASSED] drm_test_rect_intersect =============
[11:52:13] ================ drm_test_rect_calc_hscale  ================
[11:52:13] [PASSED] normal use
[11:52:13] [PASSED] out of max range
[11:52:13] [PASSED] out of min range
[11:52:13] [PASSED] zero dst
[11:52:13] [PASSED] negative src
[11:52:13] [PASSED] negative dst
[11:52:13] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:52:13] ================ drm_test_rect_calc_vscale  ================
[11:52:13] [PASSED] normal use
[11:52:13] [PASSED] out of max range
[11:52:13] [PASSED] out of min range
[11:52:13] [PASSED] zero dst
[11:52:13] [PASSED] negative src
[11:52:13] [PASSED] negative dst
[11:52:13] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:52:13] ================== drm_test_rect_rotate  ===================
[11:52:13] [PASSED] reflect-x
[11:52:13] [PASSED] reflect-y
[11:52:13] [PASSED] rotate-0
[11:52:13] [PASSED] rotate-90
[11:52:13] [PASSED] rotate-180
[11:52:13] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[11:52:13] ============== [PASSED] drm_test_rect_rotate ===============
[11:52:13] ================ drm_test_rect_rotate_inv  =================
[11:52:13] [PASSED] reflect-x
[11:52:13] [PASSED] reflect-y
[11:52:13] [PASSED] rotate-0
[11:52:13] [PASSED] rotate-90
[11:52:13] [PASSED] rotate-180
[11:52:13] [PASSED] rotate-270
[11:52:13] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:52:13] ==================== [PASSED] drm_rect =====================
[11:52:13] ============================================================
[11:52:13] Testing complete. Ran 598 tests: passed: 598
[11:52:13] Elapsed time: 22.918s total, 1.656s configuring, 21.091s building, 0.140s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:52:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:52:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
[11:52:23] Starting KUnit Kernel (1/1)...
[11:52:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:52:23] ================= ttm_device (5 subtests) ==================
[11:52:23] [PASSED] ttm_device_init_basic
[11:52:23] [PASSED] ttm_device_init_multiple
[11:52:23] [PASSED] ttm_device_fini_basic
[11:52:23] [PASSED] ttm_device_init_no_vma_man
[11:52:23] ================== ttm_device_init_pools  ==================
[11:52:23] [PASSED] No DMA allocations, no DMA32 required
[11:52:23] [PASSED] DMA allocations, DMA32 required
[11:52:23] [PASSED] No DMA allocations, DMA32 required
[11:52:23] [PASSED] DMA allocations, no DMA32 required
[11:52:23] ============== [PASSED] ttm_device_init_pools ==============
[11:52:23] =================== [PASSED] ttm_device ====================
[11:52:23] ================== ttm_pool (8 subtests) ===================
[11:52:23] ================== ttm_pool_alloc_basic  ===================
[11:52:23] [PASSED] One page
[11:52:23] [PASSED] More than one page
[11:52:23] [PASSED] Above the allocation limit
[11:52:23] [PASSED] One page, with coherent DMA mappings enabled
[11:52:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:52:23] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:52:23] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:52:23] [PASSED] One page
[11:52:23] [PASSED] More than one page
[11:52:23] [PASSED] Above the allocation limit
[11:52:23] [PASSED] One page, with coherent DMA mappings enabled
[11:52:23] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:52:23] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:52:23] [PASSED] ttm_pool_alloc_order_caching_match
[11:52:23] [PASSED] ttm_pool_alloc_caching_mismatch
[11:52:23] [PASSED] ttm_pool_alloc_order_mismatch
[11:52:23] [PASSED] ttm_pool_free_dma_alloc
[11:52:23] [PASSED] ttm_pool_free_no_dma_alloc
[11:52:23] [PASSED] ttm_pool_fini_basic
[11:52:23] ==================== [PASSED] ttm_pool =====================
[11:52:23] ================ ttm_resource (8 subtests) =================
[11:52:23] ================= ttm_resource_init_basic  =================
[11:52:23] [PASSED] Init resource in TTM_PL_SYSTEM
[11:52:23] [PASSED] Init resource in TTM_PL_VRAM
[11:52:23] [PASSED] Init resource in a private placement
[11:52:23] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:52:23] ============= [PASSED] ttm_resource_init_basic =============
[11:52:23] [PASSED] ttm_resource_init_pinned
[11:52:23] [PASSED] ttm_resource_fini_basic
[11:52:23] [PASSED] ttm_resource_manager_init_basic
[11:52:23] [PASSED] ttm_resource_manager_usage_basic
[11:52:23] [PASSED] ttm_resource_manager_set_used_basic
[11:52:23] [PASSED] ttm_sys_man_alloc_basic
[11:52:23] [PASSED] ttm_sys_man_free_basic
[11:52:23] ================== [PASSED] ttm_resource ===================
[11:52:23] =================== ttm_tt (15 subtests) ===================
[11:52:23] ==================== ttm_tt_init_basic  ====================
[11:52:23] [PASSED] Page-aligned size
[11:52:23] [PASSED] Extra pages requested
[11:52:23] ================ [PASSED] ttm_tt_init_basic ================
[11:52:23] [PASSED] ttm_tt_init_misaligned
[11:52:23] [PASSED] ttm_tt_fini_basic
[11:52:23] [PASSED] ttm_tt_fini_sg
[11:52:23] [PASSED] ttm_tt_fini_shmem
[11:52:23] [PASSED] ttm_tt_create_basic
[11:52:23] [PASSED] ttm_tt_create_invalid_bo_type
[11:52:23] [PASSED] ttm_tt_create_ttm_exists
[11:52:23] [PASSED] ttm_tt_create_failed
[11:52:23] [PASSED] ttm_tt_destroy_basic
[11:52:23] [PASSED] ttm_tt_populate_null_ttm
[11:52:23] [PASSED] ttm_tt_populate_populated_ttm
[11:52:23] [PASSED] ttm_tt_unpopulate_basic
[11:52:23] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:52:23] [PASSED] ttm_tt_swapin_basic
[11:52:23] ===================== [PASSED] ttm_tt ======================
[11:52:23] =================== ttm_bo (14 subtests) ===================
[11:52:23] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:52:23] [PASSED] Cannot be interrupted and sleeps
[11:52:23] [PASSED] Cannot be interrupted, locks straight away
[11:52:23] [PASSED] Can be interrupted, sleeps
[11:52:23] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:52:23] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:52:23] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:52:23] [PASSED] ttm_bo_reserve_double_resv
[11:52:23] [PASSED] ttm_bo_reserve_interrupted
[11:52:23] [PASSED] ttm_bo_reserve_deadlock
[11:52:23] [PASSED] ttm_bo_unreserve_basic
[11:52:23] [PASSED] ttm_bo_unreserve_pinned
[11:52:23] [PASSED] ttm_bo_unreserve_bulk
[11:52:23] [PASSED] ttm_bo_put_basic
[11:52:23] [PASSED] ttm_bo_put_shared_resv
[11:52:23] [PASSED] ttm_bo_pin_basic
[11:52:23] [PASSED] ttm_bo_pin_unpin_resource
[11:52:23] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:52:23] ===================== [PASSED] ttm_bo ======================
[11:52:23] ============== ttm_bo_validate (22 subtests) ===============
[11:52:23] ============== ttm_bo_init_reserved_sys_man  ===============
[11:52:23] [PASSED] Buffer object for userspace
[11:52:23] [PASSED] Kernel buffer object
[11:52:23] [PASSED] Shared buffer object
[11:52:23] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:52:23] ============== ttm_bo_init_reserved_mock_man  ==============
[11:52:23] [PASSED] Buffer object for userspace
[11:52:23] [PASSED] Kernel buffer object
[11:52:23] [PASSED] Shared buffer object
[11:52:23] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:52:23] [PASSED] ttm_bo_init_reserved_resv
[11:52:23] ================== ttm_bo_validate_basic  ==================
[11:52:23] [PASSED] Buffer object for userspace
[11:52:23] [PASSED] Kernel buffer object
[11:52:23] [PASSED] Shared buffer object
[11:52:23] ============== [PASSED] ttm_bo_validate_basic ==============
[11:52:23] [PASSED] ttm_bo_validate_invalid_placement
[11:52:23] ============= ttm_bo_validate_same_placement  ==============
[11:52:23] [PASSED] System manager
[11:52:23] [PASSED] VRAM manager
[11:52:23] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:52:23] [PASSED] ttm_bo_validate_failed_alloc
[11:52:23] [PASSED] ttm_bo_validate_pinned
[11:52:23] [PASSED] ttm_bo_validate_busy_placement
[11:52:23] ================ ttm_bo_validate_multihop  =================
[11:52:23] [PASSED] Buffer object for userspace
[11:52:23] [PASSED] Kernel buffer object
[11:52:23] [PASSED] Shared buffer object
[11:52:23] ============ [PASSED] ttm_bo_validate_multihop =============
[11:52:23] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:52:23] [PASSED] Buffer object in system domain, no page vector
[11:52:23] [PASSED] Buffer object in system domain with an existing page vector
[11:52:23] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:52:23] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:52:23] [PASSED] Buffer object for userspace
[11:52:23] [PASSED] Kernel buffer object
[11:52:23] [PASSED] Shared buffer object
[11:52:23] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:52:23] [PASSED] ttm_bo_validate_move_fence_signaled
[11:52:23] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:52:23] [PASSED] Waits for GPU
[11:52:23] [PASSED] Tries to lock straight away
[11:52:23] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:52:23] [PASSED] ttm_bo_validate_swapout
[11:52:23] [PASSED] ttm_bo_validate_happy_evict
[11:52:23] [PASSED] ttm_bo_validate_all_pinned_evict
[11:52:23] [PASSED] ttm_bo_validate_allowed_only_evict
[11:52:23] [PASSED] ttm_bo_validate_deleted_evict
[11:52:23] [PASSED] ttm_bo_validate_busy_domain_evict
[11:52:23] [PASSED] ttm_bo_validate_evict_gutting
[11:52:23] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:52:23] ================= [PASSED] ttm_bo_validate =================
[11:52:23] ============================================================
[11:52:23] Testing complete. Ran 102 tests: passed: 102
[11:52:23] Elapsed time: 9.963s total, 1.636s configuring, 7.710s building, 0.528s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ CI.Build: success for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : success

== Summary ==

lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/events/amd/
lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/events/amd/amd-uncore.ko
lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/events/rapl.ko
lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/kvm/
lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.14.0-rc2-xe+/kernel/arch/x86/kvm/kvm-amd.ko
lib/modules/6.14.0-rc2-xe+/kernel/kernel/
lib/modules/6.14.0-rc2-xe+/kernel/kernel/kheaders.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/
lib/modules/6.14.0-rc2-xe+/kernel/crypto/ecrdsa_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/xcbc.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/serpent_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/aria_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/crypto_simd.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/adiantum.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/tcrypt.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/crypto_engine.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/zstd.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/asymmetric_keys/
lib/modules/6.14.0-rc2-xe+/kernel/crypto/asymmetric_keys/pkcs7_test_key.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/asymmetric_keys/pkcs8_key_parser.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/des_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/xctr.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/authenc.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/sm4_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/camellia_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/sm3.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/pcrypt.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/aegis128.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/af_alg.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/algif_aead.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/cmac.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/sm3_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/aes_ti.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/chacha_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/poly1305_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/nhpoly1305.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/crc32_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/essiv.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/ccm.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/wp512.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/streebog_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/authencesn.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/echainiv.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/lrw.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/cryptd.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/crypto_user.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/algif_hash.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/polyval-generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/hctr2.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/842.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/pcbc.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/ansi_cprng.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/cast6_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/twofish_common.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/twofish_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/lz4hc.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/blowfish_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/md4.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/chacha20poly1305.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/curve25519-generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/lz4.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/rmd160.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/algif_skcipher.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/cast5_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/fcrypt.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/ecdsa_generic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/sm4.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/cast_common.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/blowfish_common.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/michael_mic.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/async_tx/
lib/modules/6.14.0-rc2-xe+/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.14.0-rc2-xe+/kernel/crypto/algif_rng.ko
lib/modules/6.14.0-rc2-xe+/kernel/block/
lib/modules/6.14.0-rc2-xe+/kernel/block/bfq.ko
lib/modules/6.14.0-rc2-xe+/kernel/block/kyber-iosched.ko
lib/modules/6.14.0-rc2-xe+/build
lib/modules/6.14.0-rc2-xe+/modules.alias.bin
lib/modules/6.14.0-rc2-xe+/modules.builtin
lib/modules/6.14.0-rc2-xe+/modules.softdep
lib/modules/6.14.0-rc2-xe+/modules.alias
lib/modules/6.14.0-rc2-xe+/modules.order
lib/modules/6.14.0-rc2-xe+/modules.symbols
lib/modules/6.14.0-rc2-xe+/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1739275729:package_x86_64_nodebug\r\e[0K'
^[[0Ksection_end:1739275729:package_x86_64_nodebug
^[[0K
+ sync
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.Hooks: failure for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : failure

== Summary ==

run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
  GEN     Makefile
mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool 
  INSTALL libsubcmd_headers
  CALL    ../scripts/checksyscalls.sh
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
  CC      /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
  LD      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
  AR      /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
  CC      /workspace/kernel/build64-default/tools/objtool/weak.o
  CC      /workspace/kernel/build64-default/tools/objtool/check.o
  CC      /workspace/kernel/build64-default/tools/objtool/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/builtin-check.o
  CC      /workspace/kernel/build64-default/tools/objtool/elf.o
  CC      /workspace/kernel/build64-default/tools/objtool/objtool.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_gen.o
  CC      /workspace/kernel/build64-default/tools/objtool/orc_dump.o
  CC      /workspace/kernel/build64-default/tools/objtool/libstring.o
  CC      /workspace/kernel/build64-default/tools/objtool/libctype.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
  CC      /workspace/kernel/build64-default/tools/objtool/str_error_r.o
  CC      /workspace/kernel/build64-default/tools/objtool/librbtree.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
  CC      /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
  LD      /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
  LD      /workspace/kernel/build64-default/tools/objtool/objtool-in.o
  LINK    /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-default'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-default'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ BUILD_DIR=/workspace/kernel/build64-default/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-default/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-default/build32'
  GEN     Makefile
  HOSTCC  scripts/basic/fixdep
  HOSTCC  scripts/kconfig/conf.o
  HOSTCC  scripts/kconfig/confdata.o
  HOSTCC  scripts/kconfig/expr.o
  LEX     scripts/kconfig/lexer.lex.c
  YACC    scripts/kconfig/parser.tab.[ch]
  HOSTCC  scripts/kconfig/menu.o
  HOSTCC  scripts/kconfig/preprocess.o
  HOSTCC  scripts/kconfig/symbol.o
  HOSTCC  scripts/kconfig/util.o
  HOSTCC  scripts/kconfig/lexer.lex.o
  HOSTCC  scripts/kconfig/parser.tab.o
  HOSTLD  scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-default/build32'
+ cd /workspace/kernel/build64-default/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/fragments/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/fragments/10-xe.fragment
Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/fragments/10-xe.fragment:
Previous value: # CONFIG_DRM_XE is not set
New value: CONFIG_DRM_XE=m

  GEN     Makefile

WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
  Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
  Selected by [m]:
  - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
#
# configuration written to .config
#
Value requested for CONFIG_HAVE_UID16 not in final .config
Requested value:  CONFIG_HAVE_UID16=y
Actual value:     

Value requested for CONFIG_UID16 not in final .config
Requested value:  CONFIG_UID16=y
Actual value:     

Value requested for CONFIG_X86_32 not in final .config
Requested value:  CONFIG_X86_32=y
Actual value:     

Value requested for CONFIG_OUTPUT_FORMAT not in final .config
Requested value:  CONFIG_OUTPUT_FORMAT="elf32-i386"
Actual value:     CONFIG_OUTPUT_FORMAT="elf64-x86-64"

Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config
Requested value:  CONFIG_ARCH_MMAP_RND_BITS_MIN=8
Actual value:     CONFIG_ARCH_MMAP_RND_BITS_MIN=28

Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config
Requested value:  CONFIG_ARCH_MMAP_RND_BITS_MAX=16
Actual value:     CONFIG_ARCH_MMAP_RND_BITS_MAX=32

Value requested for CONFIG_PGTABLE_LEVELS not in final .config
Requested value:  CONFIG_PGTABLE_LEVELS=2
Actual value:     CONFIG_PGTABLE_LEVELS=5

Value requested for CONFIG_X86_BIGSMP not in final .config
Requested value:  # CONFIG_X86_BIGSMP is not set
Actual value:     

Value requested for CONFIG_X86_INTEL_QUARK not in final .config
Requested value:  # CONFIG_X86_INTEL_QUARK is not set
Actual value:     

Value requested for CONFIG_X86_RDC321X not in final .config
Requested value:  # CONFIG_X86_RDC321X is not set
Actual value:     

Value requested for CONFIG_X86_32_NON_STANDARD not in final .config
Requested value:  # CONFIG_X86_32_NON_STANDARD is not set
Actual value:     

Value requested for CONFIG_X86_32_IRIS not in final .config
Requested value:  # CONFIG_X86_32_IRIS is not set
Actual value:     

Value requested for CONFIG_M486SX not in final .config
Requested value:  # CONFIG_M486SX is not set
Actual value:     

Value requested for CONFIG_M486 not in final .config
Requested value:  # CONFIG_M486 is not set
Actual value:     

Value requested for CONFIG_M586 not in final .config
Requested value:  # CONFIG_M586 is not set
Actual value:     

Value requested for CONFIG_M586TSC not in final .config
Requested value:  # CONFIG_M586TSC is not set
Actual value:     

Value requested for CONFIG_M586MMX not in final .config
Requested value:  # CONFIG_M586MMX is not set
Actual value:     

Value requested for CONFIG_M686 not in final .config
Requested value:  CONFIG_M686=y
Actual value:     

Value requested for CONFIG_MPENTIUMII not in final .config
Requested value:  # CONFIG_MPENTIUMII is not set
Actual value:     

Value requested for CONFIG_MPENTIUMIII not in final .config
Requested value:  # CONFIG_MPENTIUMIII is not set
Actual value:     

Value requested for CONFIG_MPENTIUMM not in final .config
Requested value:  # CONFIG_MPENTIUMM is not set
Actual value:     

Value requested for CONFIG_MPENTIUM4 not in final .config
Requested value:  # CONFIG_MPENTIUM4 is not set
Actual value:     

Value requested for CONFIG_MK6 not in final .config
Requested value:  # CONFIG_MK6 is not set
Actual value:     

Value requested for CONFIG_MK7 not in final .config
Requested value:  # CONFIG_MK7 is not set
Actual value:     

Value requested for CONFIG_MCRUSOE not in final .config
Requested value:  # CONFIG_MCRUSOE is not set
Actual value:     

Value requested for CONFIG_MEFFICEON not in final .config
Requested value:  # CONFIG_MEFFICEON is not set
Actual value:     

Value requested for CONFIG_MWINCHIPC6 not in final .config
Requested value:  # CONFIG_MWINCHIPC6 is not set
Actual value:     

Value requested for CONFIG_MWINCHIP3D not in final .config
Requested value:  # CONFIG_MWINCHIP3D is not set
Actual value:     

Value requested for CONFIG_MELAN not in final .config
Requested value:  # CONFIG_MELAN is not set
Actual value:     

Value requested for CONFIG_MGEODEGX1 not in final .config
Requested value:  # CONFIG_MGEODEGX1 is not set
Actual value:     

Value requested for CONFIG_MGEODE_LX not in final .config
Requested value:  # CONFIG_MGEODE_LX is not set
Actual value:     

Value requested for CONFIG_MCYRIXIII not in final .config
Requested value:  # CONFIG_MCYRIXIII is not set
Actual value:     

Value requested for CONFIG_MVIAC3_2 not in final .config
Requested value:  # CONFIG_MVIAC3_2 is not set
Actual value:     

Value requested for CONFIG_MVIAC7 not in final .config
Requested value:  # CONFIG_MVIAC7 is not set
Actual value:     

Value requested for CONFIG_X86_GENERIC not in final .config
Requested value:  # CONFIG_X86_GENERIC is not set
Actual value:     

Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config
Requested value:  CONFIG_X86_INTERNODE_CACHE_SHIFT=5
Actual value:     CONFIG_X86_INTERNODE_CACHE_SHIFT=6

Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config
Requested value:  CONFIG_X86_L1_CACHE_SHIFT=5
Actual value:     CONFIG_X86_L1_CACHE_SHIFT=6

Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config
Requested value:  CONFIG_X86_USE_PPRO_CHECKSUM=y
Actual value:     

Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config
Requested value:  CONFIG_X86_MINIMUM_CPU_FAMILY=6
Actual value:     CONFIG_X86_MINIMUM_CPU_FAMILY=64

Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config
Requested value:  CONFIG_CPU_SUP_TRANSMETA_32=y
Actual value:     

Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config
Requested value:  CONFIG_CPU_SUP_VORTEX_32=y
Actual value:     

Value requested for CONFIG_HPET_TIMER not in final .config
Requested value:  # CONFIG_HPET_TIMER is not set
Actual value:     CONFIG_HPET_TIMER=y

Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config
Requested value:  CONFIG_NR_CPUS_RANGE_END=8
Actual value:     CONFIG_NR_CPUS_RANGE_END=512

Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config
Requested value:  CONFIG_NR_CPUS_DEFAULT=8
Actual value:     CONFIG_NR_CPUS_DEFAULT=64

Value requested for CONFIG_X86_ANCIENT_MCE not in final .config
Requested value:  # CONFIG_X86_ANCIENT_MCE is not set
Actual value:     

Value requested for CONFIG_X86_LEGACY_VM86 not in final .config
Requested value:  # CONFIG_X86_LEGACY_VM86 is not set
Actual value:     

Value requested for CONFIG_X86_ESPFIX32 not in final .config
Requested value:  CONFIG_X86_ESPFIX32=y
Actual value:     

Value requested for CONFIG_TOSHIBA not in final .config
Requested value:  # CONFIG_TOSHIBA is not set
Actual value:     

Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config
Requested value:  # CONFIG_X86_REBOOTFIXUPS is not set
Actual value:     

Value requested for CONFIG_MICROCODE_INITRD32 not in final .config
Requested value:  CONFIG_MICROCODE_INITRD32=y
Actual value:     

Value requested for CONFIG_NOHIGHMEM not in final .config
Requested value:  # CONFIG_NOHIGHMEM is not set
Actual value:     

Value requested for CONFIG_HIGHMEM4G not in final .config
Requested value:  CONFIG_HIGHMEM4G=y
Actual value:     

Value requested for CONFIG_HIGHMEM64G not in final .config
Requested value:  # CONFIG_HIGHMEM64G is not set
Actual value:     

Value requested for CONFIG_VMSPLIT_3G not in final .config
Requested value:  CONFIG_VMSPLIT_3G=y
Actual value:     

Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config
Requested value:  # CONFIG_VMSPLIT_3G_OPT is not set
Actual value:     

Value requested for CONFIG_VMSPLIT_2G not in final .config
Requested value:  # CONFIG_VMSPLIT_2G is not set
Actual value:     

Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config
Requested value:  # CONFIG_VMSPLIT_2G_OPT is not set
Actual value:     

Value requested for CONFIG_VMSPLIT_1G not in final .config
Requested value:  # CONFIG_VMSPLIT_1G is not set
Actual value:     

Value requested for CONFIG_PAGE_OFFSET not in final .config
Requested value:  CONFIG_PAGE_OFFSET=0xC0000000
Actual value:     

Value requested for CONFIG_HIGHMEM not in final .config
Requested value:  CONFIG_HIGHMEM=y
Actual value:     

Value requested for CONFIG_X86_PAE not in final .config
Requested value:  # CONFIG_X86_PAE is not set
Actual value:     

Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config
Requested value:  CONFIG_ARCH_FLATMEM_ENABLE=y
Actual value:     

Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config
Requested value:  CONFIG_ARCH_SELECT_MEMORY_MODEL=y
Actual value:     

Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config
Requested value:  CONFIG_ILLEGAL_POINTER_VALUE=0
Actual value:     CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000

Value requested for CONFIG_HIGHPTE not in final .config
Requested value:  # CONFIG_HIGHPTE is not set
Actual value:     

Value requested for CONFIG_COMPAT_VDSO not in final .config
Requested value:  # CONFIG_COMPAT_VDSO is not set
Actual value:     

Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config
Requested value:  CONFIG_FUNCTION_PADDING_CFI=0
Actual value:     CONFIG_FUNCTION_PADDING_CFI=11

Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config
Requested value:  CONFIG_FUNCTION_PADDING_BYTES=4
Actual value:     CONFIG_FUNCTION_PADDING_BYTES=16

Value requested for CONFIG_APM not in final .config
Requested value:  # CONFIG_APM is not set
Actual value:     

Value requested for CONFIG_X86_POWERNOW_K6 not in final .config
Requested value:  # CONFIG_X86_POWERNOW_K6 is not set
Actual value:     

Value requested for CONFIG_X86_POWERNOW_K7 not in final .config
Requested value:  # CONFIG_X86_POWERNOW_K7 is not set
Actual value:     

Value requested for CONFIG_X86_GX_SUSPMOD not in final .config
Requested value:  # CONFIG_X86_GX_SUSPMOD is not set
Actual value:     

Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config
Requested value:  # CONFIG_X86_SPEEDSTEP_ICH is not set
Actual value:     

Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config
Requested value:  # CONFIG_X86_SPEEDSTEP_SMI is not set
Actual value:     

Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config
Requested value:  # CONFIG_X86_CPUFREQ_NFORCE2 is not set
Actual value:     

Value requested for CONFIG_X86_LONGRUN not in final .config
Requested value:  # CONFIG_X86_LONGRUN is not set
Actual value:     

Value requested for CONFIG_X86_LONGHAUL not in final .config
Requested value:  # CONFIG_X86_LONGHAUL is not set
Actual value:     

Value requested for CONFIG_X86_E_POWERSAVER not in final .config
Requested value:  # CONFIG_X86_E_POWERSAVER is not set
Actual value:     

Value requested for CONFIG_PCI_GOBIOS not in final .config
Requested value:  # CONFIG_PCI_GOBIOS is not set
Actual value:     

Value requested for CONFIG_PCI_GOMMCONFIG not in final .config
Requested value:  # CONFIG_PCI_GOMMCONFIG is not set
Actual value:     

Value requested for CONFIG_PCI_GODIRECT not in final .config
Requested value:  # CONFIG_PCI_GODIRECT is not set
Actual value:     

Value requested for CONFIG_PCI_GOANY not in final .config
Requested value:  CONFIG_PCI_GOANY=y
Actual value:     

Value requested for CONFIG_PCI_BIOS not in final .config
Requested value:  CONFIG_PCI_BIOS=y
Actual value:     

Value requested for CONFIG_ISA not in final .config
Requested value:  # CONFIG_ISA is not set
Actual value:     

Value requested for CONFIG_SCx200 not in final .config
Requested value:  # CONFIG_SCx200 is not set
Actual value:     

Value requested for CONFIG_OLPC not in final .config
Requested value:  # CONFIG_OLPC is not set
Actual value:     

Value requested for CONFIG_ALIX not in final .config
Requested value:  # CONFIG_ALIX is not set
Actual value:     

Value requested for CONFIG_NET5501 not in final .config
Requested value:  # CONFIG_NET5501 is not set
Actual value:     

Value requested for CONFIG_GEOS not in final .config
Requested value:  # CONFIG_GEOS is not set
Actual value:     

Value requested for CONFIG_COMPAT_32 not in final .config
Requested value:  CONFIG_COMPAT_32=y
Actual value:     

Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config
Requested value:  CONFIG_HAVE_ATOMIC_IOMAP=y
Actual value:     

Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config
Requested value:  CONFIG_ARCH_32BIT_OFF_T=y
Actual value:     

Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config
Requested value:  CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
Actual value:     

Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config
Requested value:  CONFIG_MODULES_USE_ELF_REL=y
Actual value:     

Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config
Requested value:  CONFIG_ARCH_MMAP_RND_BITS=8
Actual value:     CONFIG_ARCH_MMAP_RND_BITS=28

Value requested for CONFIG_CLONE_BACKWARDS not in final .config
Requested value:  CONFIG_CLONE_BACKWARDS=y
Actual value:     

Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config
Requested value:  CONFIG_OLD_SIGSUSPEND3=y
Actual value:     

Value requested for CONFIG_OLD_SIGACTION not in final .config
Requested value:  CONFIG_OLD_SIGACTION=y
Actual value:     

Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config
Requested value:  CONFIG_ARCH_SPLIT_ARG64=y
Actual value:     

Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config
Requested value:  CONFIG_FUNCTION_ALIGNMENT=4
Actual value:     CONFIG_FUNCTION_ALIGNMENT=16

Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config
Requested value:  CONFIG_SELECT_MEMORY_MODEL=y
Actual value:     

Value requested for CONFIG_FLATMEM_MANUAL not in final .config
Requested value:  CONFIG_FLATMEM_MANUAL=y
Actual value:     

Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config
Requested value:  # CONFIG_SPARSEMEM_MANUAL is not set
Actual value:     

Value requested for CONFIG_FLATMEM not in final .config
Requested value:  CONFIG_FLATMEM=y
Actual value:     

Value requested for CONFIG_SPARSEMEM_STATIC not in final .config
Requested value:  CONFIG_SPARSEMEM_STATIC=y
Actual value:     

Value requested for CONFIG_BOUNCE not in final .config
Requested value:  CONFIG_BOUNCE=y
Actual value:     

Value requested for CONFIG_KMAP_LOCAL not in final .config
Requested value:  CONFIG_KMAP_LOCAL=y
Actual value:     

Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config
Requested value:  # CONFIG_HOTPLUG_PCI_COMPAQ is not set
Actual value:     

Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config
Requested value:  # CONFIG_HOTPLUG_PCI_IBM is not set
Actual value:     

Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config
Requested value:  CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
Actual value:     

Value requested for CONFIG_PCH_PHUB not in final .config
Requested value:  # CONFIG_PCH_PHUB is not set
Actual value:     

Value requested for CONFIG_SCSI_NSP32 not in final .config
Requested value:  # CONFIG_SCSI_NSP32 is not set
Actual value:     

Value requested for CONFIG_PATA_CS5520 not in final .config
Requested value:  # CONFIG_PATA_CS5520 is not set
Actual value:     

Value requested for CONFIG_PATA_CS5530 not in final .config
Requested value:  # CONFIG_PATA_CS5530 is not set
Actual value:     

Value requested for CONFIG_PATA_CS5535 not in final .config
Requested value:  # CONFIG_PATA_CS5535 is not set
Actual value:     

Value requested for CONFIG_PATA_CS5536 not in final .config
Requested value:  # CONFIG_PATA_CS5536 is not set
Actual value:     

Value requested for CONFIG_PATA_SC1200 not in final .config
Requested value:  # CONFIG_PATA_SC1200 is not set
Actual value:     

Value requested for CONFIG_PCH_GBE not in final .config
Requested value:  # CONFIG_PCH_GBE is not set
Actual value:     

Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config
Requested value:  # CONFIG_INPUT_WISTRON_BTNS is not set
Actual value:     

Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config
Requested value:  # CONFIG_SERIAL_TIMBERDALE is not set
Actual value:     

Value requested for CONFIG_SERIAL_PCH_UART not in final .config
Requested value:  # CONFIG_SERIAL_PCH_UART is not set
Actual value:     

Value requested for CONFIG_HW_RANDOM_GEODE not in final .config
Requested value:  CONFIG_HW_RANDOM_GEODE=y
Actual value:     

Value requested for CONFIG_SONYPI not in final .config
Requested value:  # CONFIG_SONYPI is not set
Actual value:     

Value requested for CONFIG_PC8736x_GPIO not in final .config
Requested value:  # CONFIG_PC8736x_GPIO is not set
Actual value:     

Value requested for CONFIG_NSC_GPIO not in final .config
Requested value:  # CONFIG_NSC_GPIO is not set
Actual value:     

Value requested for CONFIG_I2C_EG20T not in final .config
Requested value:  # CONFIG_I2C_EG20T is not set
Actual value:     

Value requested for CONFIG_SCx200_ACB not in final .config
Requested value:  # CONFIG_SCx200_ACB is not set
Actual value:     

Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config
Requested value:  # CONFIG_PTP_1588_CLOCK_PCH is not set
Actual value:     

Value requested for CONFIG_SBC8360_WDT not in final .config
Requested value:  # CONFIG_SBC8360_WDT is not set
Actual value:     

Value requested for CONFIG_SBC7240_WDT not in final .config
Requested value:  # CONFIG_SBC7240_WDT is not set
Actual value:     

Value requested for CONFIG_MFD_CS5535 not in final .config
Requested value:  # CONFIG_MFD_CS5535 is not set
Actual value:     

Value requested for CONFIG_AGP_ALI not in final .config
Requested value:  # CONFIG_AGP_ALI is not set
Actual value:     

Value requested for CONFIG_AGP_ATI not in final .config
Requested value:  # CONFIG_AGP_ATI is not set
Actual value:     

Value requested for CONFIG_AGP_AMD not in final .config
Requested value:  # CONFIG_AGP_AMD is not set
Actual value:     

Value requested for CONFIG_AGP_NVIDIA not in final .config
Requested value:  # CONFIG_AGP_NVIDIA is not set
Actual value:     

Value requested for CONFIG_AGP_SWORKS not in final .config
Requested value:  # CONFIG_AGP_SWORKS is not set
Actual value:     

Value requested for CONFIG_AGP_EFFICEON not in final .config
Requested value:  # CONFIG_AGP_EFFICEON is not set
Actual value:     

Value requested for CONFIG_SND_CS5530 not in final .config
Requested value:  # CONFIG_SND_CS5530 is not set
Actual value:     

Value requested for CONFIG_SND_CS5535AUDIO not in final .config
Requested value:  # CONFIG_SND_CS5535AUDIO is not set
Actual value:     

Value requested for CONFIG_SND_SIS7019 not in final .config
Requested value:  # CONFIG_SND_SIS7019 is not set
Actual value:     

Value requested for CONFIG_LEDS_OT200 not in final .config
Requested value:  # CONFIG_LEDS_OT200 is not set
Actual value:     

Value requested for CONFIG_PCH_DMA not in final .config
Requested value:  # CONFIG_PCH_DMA is not set
Actual value:     

Value requested for CONFIG_CLKSRC_I8253 not in final .config
Requested value:  CONFIG_CLKSRC_I8253=y
Actual value:     

Value requested for CONFIG_MAILBOX not in final .config
Requested value:  # CONFIG_MAILBOX is not set
Actual value:     CONFIG_MAILBOX=y

Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config
Requested value:  # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
Actual value:     

Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config
Requested value:  # CONFIG_CRYPTO_TWOFISH_586 is not set
Actual value:     

Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config
Requested value:  # CONFIG_CRYPTO_DEV_GEODE is not set
Actual value:     

Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config
Requested value:  # CONFIG_CRYPTO_DEV_HIFN_795X is not set
Actual value:     

Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config
Requested value:  CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
Actual value:     CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11

Value requested for CONFIG_AUDIT_GENERIC not in final .config
Requested value:  CONFIG_AUDIT_GENERIC=y
Actual value:     

Value requested for CONFIG_GENERIC_VDSO_32 not in final .config
Requested value:  CONFIG_GENERIC_VDSO_32=y
Actual value:     

Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config
Requested value:  # CONFIG_DEBUG_KMAP_LOCAL is not set
Actual value:     

Value requested for CONFIG_DEBUG_HIGHMEM not in final .config
Requested value:  # CONFIG_DEBUG_HIGHMEM is not set
Actual value:     

Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config
Requested value:  CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
Actual value:     

Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config
Requested value:  # CONFIG_DEBUG_STACKOVERFLOW is not set
Actual value:     

Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config
Requested value:  CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
Actual value:     

Value requested for CONFIG_HAVE_FUNCTION_GRAPH_FREGS not in final .config
Requested value:  CONFIG_HAVE_FUNCTION_GRAPH_FREGS=y
Actual value:     

Value requested for CONFIG_HAVE_FTRACE_GRAPH_FUNC not in final .config
Requested value:  CONFIG_HAVE_FTRACE_GRAPH_FUNC=y
Actual value:     

Value requested for CONFIG_DRM_KUNIT_TEST not in final .config
Requested value:  CONFIG_DRM_KUNIT_TEST=m
Actual value:     

Value requested for CONFIG_DRM_XE_WERROR not in final .config
Requested value:  CONFIG_DRM_XE_WERROR=y
Actual value:     

Value requested for CONFIG_DRM_XE_DEBUG not in final .config
Requested value:  CONFIG_DRM_XE_DEBUG=y
Actual value:     

Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config
Requested value:  CONFIG_DRM_XE_DEBUG_MEM=y
Actual value:     

Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config
Requested value:  CONFIG_DRM_XE_KUNIT_TEST=m
Actual value:     

++ nproc
+ make -j48 ARCH=i386 olddefconfig
  GEN     Makefile

WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
  Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
  Selected by [m]:
  - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
#
# configuration written to .config
#
++ nproc
+ make -j48 ARCH=i386
  SYNC    include/config/auto.conf.cmd
  GEN     Makefile

WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
  Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
  Selected by [m]:
  - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]

WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
  Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
  Selected by [m]:
  - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]

WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
  Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
  Selected by [m]:
  - DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m] && HAS_IOPORT [=y]
  WRAP    arch/x86/include/generated/uapi/asm/bpf_perf_event.h
  GEN     Makefile
  WRAP    arch/x86/include/generated/uapi/asm/errno.h
  WRAP    arch/x86/include/generated/uapi/asm/fcntl.h
  WRAP    arch/x86/include/generated/uapi/asm/ioctl.h
  WRAP    arch/x86/include/generated/uapi/asm/ioctls.h
  WRAP    arch/x86/include/generated/uapi/asm/ipcbuf.h
  WRAP    arch/x86/include/generated/uapi/asm/param.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_64.h
  UPD     include/generated/uapi/linux/version.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_32.h
  WRAP    arch/x86/include/generated/uapi/asm/resource.h
  WRAP    arch/x86/include/generated/uapi/asm/poll.h
  SYSHDR  arch/x86/include/generated/uapi/asm/unistd_x32.h
  WRAP    arch/x86/include/generated/uapi/asm/socket.h
  SYSTBL  arch/x86/include/generated/asm/syscalls_32.h
  WRAP    arch/x86/include/generated/uapi/asm/sockios.h
  WRAP    arch/x86/include/generated/uapi/asm/termbits.h
  WRAP    arch/x86/include/generated/uapi/asm/termios.h
  WRAP    arch/x86/include/generated/uapi/asm/types.h
  UPD     include/generated/compile.h
  HOSTCC  arch/x86/tools/relocs_32.o
  WRAP    arch/x86/include/generated/asm/early_ioremap.h
  HOSTCC  arch/x86/tools/relocs_64.o
  WRAP    arch/x86/include/generated/asm/fprobe.h
  WRAP    arch/x86/include/generated/asm/mcs_spinlock.h
  HOSTCC  arch/x86/tools/relocs_common.o
  WRAP    arch/x86/include/generated/asm/mmzone.h
  WRAP    arch/x86/include/generated/asm/irq_regs.h
  WRAP    arch/x86/include/generated/asm/kmap_size.h
  WRAP    arch/x86/include/generated/asm/local64.h
  WRAP    arch/x86/include/generated/asm/mmiowb.h
  WRAP    arch/x86/include/generated/asm/module.lds.h
  WRAP    arch/x86/include/generated/asm/rwonce.h
  HOSTCC  scripts/kallsyms
  HOSTCC  scripts/sorttable
  HOSTCC  scripts/asn1_compiler
  HOSTCC  scripts/selinux/mdp/mdp
  HOSTLD  arch/x86/tools/relocs
  UPD     include/config/kernel.release
  UPD     include/generated/utsrelease.h
  CC      scripts/mod/empty.o
  HOSTCC  scripts/mod/mk_elfconfig
  CC      scripts/mod/devicetable-offsets.s
  UPD     scripts/mod/devicetable-offsets.h
  MKELF   scripts/mod/elfconfig.h
  HOSTCC  scripts/mod/modpost.o
  HOSTCC  scripts/mod/file2alias.o
  HOSTCC  scripts/mod/sumversion.o
  HOSTCC  scripts/mod/symsearch.o
  HOSTLD  scripts/mod/modpost
  CC      kernel/bounds.s
  CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h
  CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h
  CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h
  UPD     include/generated/timeconst.h
  UPD     include/generated/bounds.h
  CC      arch/x86/kernel/asm-offsets.s
  UPD     include/generated/asm-offsets.h
  CALL    /workspace/kernel/scripts/checksyscalls.sh
  LDS     scripts/module.lds
  CC      init/main.o
  HOSTCC  usr/gen_init_cpio
  CC      init/do_mounts.o
  CC      certs/system_keyring.o
  CC      init/do_mounts_initrd.o
  UPD     init/utsversion-tmp.h
  CC      ipc/util.o
  CC      init/initramfs.o
  CC      init/calibrate.o
  CC      ipc/msgutil.o
  CC      init/init_task.o
  CC      security/commoncap.o
  CC      ipc/msg.o
  CC      mm/filemap.o
  CC      io_uring/io_uring.o
  AS      arch/x86/lib/atomic64_cx8_32.o
  CC      security/lsm_syscalls.o
  CC      ipc/sem.o
  CC      init/version.o
  CC      mm/mempool.o
  CC      block/bdev.o
  CC      arch/x86/pci/i386.o
  AS      arch/x86/lib/checksum_32.o
  CC      arch/x86/realmode/init.o
  CC      arch/x86/power/cpu.o
  CC      arch/x86/video/video-common.o
  AR      arch/x86/crypto/built-in.a
  AR      arch/x86/net/built-in.a
  HOSTCC  security/selinux/genheaders
  CC      security/integrity/iint.o
  CC      block/partitions/core.o
  AR      virt/lib/built-in.a
  CC      security/keys/gc.o
  CC      fs/nfs_common/nfsacl.o
  CC      arch/x86/events/amd/core.o
  AR      drivers/cache/built-in.a
  CC      net/ethernet/eth.o
  CC      fs/iomap/trace.o
  CC      block/partitions/msdos.o
  AR      arch/x86/platform/atom/built-in.a
  CC      block/fops.o
  CC      net/core/sock.o
  CC      arch/x86/mm/pat/set_memory.o
  CC      fs/notify/dnotify/dnotify.o
  CC      lib/math/div64.o
  CC      arch/x86/virt/svm/cmdline.o
  CC      arch/x86/kernel/fpu/init.o
  AR      virt/built-in.a
  AR      drivers/irqchip/built-in.a
  CC      sound/core/seq/seq.o
  AR      arch/x86/platform/ce4100/built-in.a
  CC      arch/x86/entry/vdso/vma.o
  CC      arch/x86/platform/efi/memmap.o
  CC      arch/x86/lib/cmdline.o
  AR      drivers/pwm/built-in.a
  AS      arch/x86/realmode/rm/header.o
  AR      drivers/bus/mhi/built-in.a
  CC      arch/x86/events/amd/lbr.o
  CC      kernel/sched/core.o
  AR      drivers/bus/built-in.a
  AS      arch/x86/realmode/rm/trampoline_32.o
  CC      crypto/asymmetric_keys/asymmetric_type.o
  AR      drivers/leds/trigger/built-in.a
  AR      drivers/leds/blink/built-in.a
  AS      arch/x86/realmode/rm/stack.o
  AR      drivers/leds/simple/built-in.a
  CC      drivers/leds/led-core.o
  AS      arch/x86/realmode/rm/reboot.o
  AR      arch/x86/virt/svm/built-in.a
  AR      arch/x86/virt/vmx/built-in.a
  AS      arch/x86/realmode/rm/wakeup_asm.o
  AS      arch/x86/lib/cmpxchg8b_emu.o
  AR      arch/x86/virt/built-in.a
  CC      arch/x86/lib/cpu.o
  CC      lib/math/gcd.o
  CC      fs/notify/inotify/inotify_fsnotify.o
  CC      arch/x86/realmode/rm/wakemain.o
  GEN     security/selinux/flask.h security/selinux/av_permissions.h
  CC      security/selinux/avc.o
  CC      arch/x86/events/amd/ibs.o
  CC      lib/math/lcm.o
  CC      arch/x86/realmode/rm/video-mode.o
  CC      lib/math/int_log.o
  CC      security/min_addr.o
  GEN     usr/initramfs_data.cpio
  COPY    usr/initramfs_inc_data
  AS      usr/initramfs_data.o
  AS      arch/x86/realmode/rm/copy.o
  HOSTCC  certs/extract-cert
  AR      usr/built-in.a
  CC      lib/math/int_pow.o
  CC      arch/x86/kernel/fpu/bugs.o
  CC      lib/math/int_sqrt.o
  AS      arch/x86/realmode/rm/bioscall.o
  CC      arch/x86/realmode/rm/regs.o
  CC      arch/x86/events/amd/uncore.o
  CC      lib/math/reciprocal_div.o
  CC      arch/x86/realmode/rm/video-vga.o
  CC      arch/x86/kernel/fpu/core.o
  CC      arch/x86/realmode/rm/video-vesa.o
  CC      arch/x86/lib/delay.o
  CC      lib/math/rational.o
  CC      sound/core/seq/seq_lock.o
  CC      fs/quota/dquot.o
  AR      arch/x86/video/built-in.a
  CC      arch/x86/realmode/rm/video-bios.o
  CC      arch/x86/power/hibernate_32.o
  CERT    certs/x509_certificate_list
  CERT    certs/signing_key.x509
  CC      block/partitions/efi.o
  AS      certs/system_certificates.o
  CC      fs/notify/inotify/inotify_user.o
  CC      drivers/leds/led-class.o
  AR      certs/built-in.a
  PASYMS  arch/x86/realmode/rm/pasyms.h
  CC      fs/nfs_common/grace.o
  CC      security/integrity/integrity_audit.o
  CC      kernel/locking/mutex.o
  CC      kernel/power/qos.o
  CC      arch/x86/kernel/fpu/regset.o
  CC      kernel/printk/printk.o
  LDS     arch/x86/realmode/rm/realmode.lds
  LD      arch/x86/realmode/rm/realmode.elf
  CC      net/core/request_sock.o
  CC      crypto/asymmetric_keys/restrict.o
  CC      arch/x86/pci/init.o
  RELOCS  arch/x86/realmode/rm/realmode.relocs
  OBJCOPY arch/x86/realmode/rm/realmode.bin
  AS      arch/x86/realmode/rmpiggy.o
  CC      security/keys/key.o
  CC      arch/x86/entry/vdso/extable.o
  AR      fs/notify/dnotify/built-in.a
  CC      arch/x86/platform/efi/quirks.o
  AR      arch/x86/realmode/built-in.a
  AR      fs/notify/fanotify/built-in.a
  CC      arch/x86/pci/pcbios.o
  CC      security/keys/keyring.o
  CC      drivers/leds/led-triggers.o
  AS      arch/x86/lib/getuser.o
  CC      net/core/skbuff.o
  CC      fs/notify/fsnotify.o
  GEN     arch/x86/lib/inat-tables.c
  CC      arch/x86/lib/insn-eval.o
  CC      mm/oom_kill.o
  AR      lib/math/built-in.a
  CC      sound/core/seq/seq_clientmgr.o
  CC      lib/crypto/mpi/generic_mpih-lshift.o
  CC      arch/x86/kernel/fpu/signal.o
  CC      mm/fadvise.o
  CC      io_uring/opdef.o
  CC      kernel/irq/irqdesc.o
  AS      arch/x86/power/hibernate_asm_32.o
  CC      kernel/power/main.o
  CC      fs/iomap/iter.o
  CC      crypto/api.o
  CC      arch/x86/kernel/fpu/xstate.o
  CC      crypto/asymmetric_keys/signature.o
  CC      crypto/asymmetric_keys/public_key.o
  CC      fs/iomap/buffered-io.o
  AR      arch/x86/platform/geode/built-in.a
  CC      fs/nfs_common/common.o
  CC      arch/x86/power/hibernate.o
  CC      arch/x86/mm/pat/memtype.o
  AR      arch/x86/entry/vsyscall/built-in.a
  CC      sound/core/sound.o
  CC      sound/core/init.o
  AR      net/ethernet/built-in.a
  CC      arch/x86/lib/insn.o
  CC      arch/x86/platform/efi/efi.o
  AR      security/integrity/built-in.a
  CC      arch/x86/kernel/cpu/mce/core.o
  AR      init/built-in.a
  CC      lib/zlib_inflate/inffast.o
  CC      arch/x86/pci/mmconfig_32.o
  CC      arch/x86/kernel/cpu/mtrr/mtrr.o
  CC      lib/crypto/mpi/generic_mpih-mul1.o
  AR      block/partitions/built-in.a
  CC      block/bio.o
  LDS     arch/x86/entry/vdso/vdso32/vdso32.lds
  AR      arch/x86/events/amd/built-in.a
  AR      drivers/leds/built-in.a
  AS      arch/x86/entry/vdso/vdso32/note.o
  CC      arch/x86/events/intel/core.o
  CC      drivers/pci/msi/pcidev_msi.o
  AS      arch/x86/entry/vdso/vdso32/system_call.o
  AS      arch/x86/entry/vdso/vdso32/sigreturn.o
  AR      fs/notify/inotify/built-in.a
  CC      arch/x86/entry/vdso/vdso32/vclock_gettime.o
  CC      arch/x86/kernel/cpu/microcode/core.o
  CC      arch/x86/events/zhaoxin/core.o
  CC      lib/zlib_inflate/inflate.o
  CC      security/selinux/hooks.o
  CC      mm/maccess.o
  CC      ipc/shm.o
  AR      arch/x86/platform/iris/built-in.a
  CC      fs/notify/notification.o
  CC      arch/x86/events/core.o
  CC      kernel/printk/printk_safe.o
  CC      sound/core/memory.o
  CC      arch/x86/lib/kaslr.o
  CC      arch/x86/lib/memcpy_32.o
  CC      kernel/irq/handle.o
  AS      arch/x86/entry/entry.o
  CC      ipc/syscall.o
  CC      arch/x86/kernel/cpu/mtrr/if.o
  CC      kernel/rcu/update.o
  CC      arch/x86/mm/pat/memtype_interval.o
  CC      arch/x86/platform/intel/iosf_mbi.o
  ASN.1   crypto/asymmetric_keys/x509.asn1.[ch]
  ASN.1   crypto/asymmetric_keys/x509_akid.asn1.[ch]
  CC      crypto/asymmetric_keys/x509_loader.o
  CC      mm/page-writeback.o
  CC      kernel/locking/semaphore.o
  AS      arch/x86/lib/memmove_32.o
  AR      fs/nfs_common/built-in.a
  CC      kernel/locking/rwsem.o
  CC      ipc/ipc_sysctl.o
  CC      arch/x86/lib/misc.o
  AR      arch/x86/power/built-in.a
  CC      fs/notify/group.o
  CC      security/keys/keyctl.o
  CC      crypto/cipher.o
  CC      arch/x86/lib/pc-conf-reg.o
  CC      crypto/asymmetric_keys/x509_public_key.o
  CC      lib/crypto/mpi/generic_mpih-mul2.o
  CC      arch/x86/pci/direct.o
  AS      arch/x86/lib/putuser.o
  CC      drivers/pci/msi/api.o
  CC      arch/x86/events/probe.o
  AS      arch/x86/lib/retpoline.o
  CC      sound/core/seq/seq_memory.o
  CC      kernel/power/console.o
  CC      arch/x86/lib/string_32.o
  CC      lib/crypto/memneq.o
  CC      kernel/irq/manage.o
  CC      lib/zlib_inflate/infutil.o
  CC      arch/x86/lib/strstr_32.o
  CC      kernel/irq/spurious.o
  CC      arch/x86/kernel/cpu/microcode/intel.o
  AR      net/802/built-in.a
  CC      drivers/pci/pcie/portdrv.o
  CC      arch/x86/entry/vdso/vdso32/vgetcpu.o
  CC      drivers/video/console/dummycon.o
  AR      arch/x86/kernel/fpu/built-in.a
  CC      drivers/video/backlight/backlight.o
  CC      arch/x86/lib/usercopy.o
  CC      lib/crypto/mpi/generic_mpih-mul3.o
  CC      arch/x86/platform/efi/efi_32.o
  ASN.1   crypto/asymmetric_keys/pkcs7.asn1.[ch]
  CC      kernel/power/process.o
  HOSTCC  arch/x86/entry/vdso/vdso2c
  CC      arch/x86/kernel/cpu/mtrr/generic.o
  AR      arch/x86/mm/pat/built-in.a
  CC      arch/x86/lib/usercopy_32.o
  CC      arch/x86/mm/init.o
  AR      drivers/idle/built-in.a
  CC      net/sched/sch_generic.o
  CC      fs/quota/quota_v2.o
  CC      arch/x86/kernel/acpi/boot.o
  AR      arch/x86/events/zhaoxin/built-in.a
  CC      security/selinux/selinuxfs.o
  CC      kernel/irq/resend.o
  AR      arch/x86/platform/intel/built-in.a
  AR      drivers/char/ipmi/built-in.a
  CC      lib/zlib_inflate/inftrees.o
  CC      lib/crypto/mpi/generic_mpih-rshift.o
  CC      fs/notify/mark.o
  CC      security/selinux/netlink.o
  CC      lib/crypto/utils.o
  CC      crypto/asymmetric_keys/pkcs7_trust.o
  CC      crypto/asymmetric_keys/pkcs7_verify.o
  CC      drivers/pci/msi/msi.o
  AR      kernel/livepatch/built-in.a
  CC      arch/x86/lib/msr-smp.o
  CC      kernel/locking/percpu-rwsem.o
  CC      lib/zlib_inflate/inflate_syms.o
  CC      fs/proc/task_mmu.o
  CC      net/sched/sch_mq.o
  CC      arch/x86/entry/vdso/vdso32-setup.o
  CC      arch/x86/pci/mmconfig-shared.o
  CC      arch/x86/kernel/cpu/cacheinfo.o
  CC      drivers/video/console/vgacon.o
  CC      arch/x86/kernel/cpu/mtrr/cleanup.o
  CC      ipc/mqueue.o
  AS      arch/x86/entry/entry_32.o
  CC      io_uring/kbuf.o
  CC      kernel/printk/nbcon.o
  CC      block/elevator.o
  CC      arch/x86/mm/init_32.o
  CC      crypto/compress.o
  CC      arch/x86/lib/cache-smp.o
  CC      arch/x86/kernel/acpi/sleep.o
  AS      arch/x86/kernel/acpi/wakeup_32.o
  CC      security/security.o
  CC      sound/core/seq/seq_queue.o
  AS      arch/x86/platform/efi/efi_stub_32.o
  CC      arch/x86/platform/efi/runtime-map.o
  CC      crypto/asymmetric_keys/x509.asn1.o
  VDSO    arch/x86/entry/vdso/vdso32.so.dbg
  CC      arch/x86/kernel/cpu/microcode/amd.o
  AR      lib/zlib_inflate/built-in.a
  CC      crypto/asymmetric_keys/x509_akid.asn1.o
  CC      arch/x86/mm/fault.o
  CC      net/core/datagram.o
  CC      drivers/pci/pcie/rcec.o
  OBJCOPY arch/x86/entry/vdso/vdso32.so
  CC      crypto/asymmetric_keys/x509_cert_parser.o
  VDSO2C  arch/x86/entry/vdso/vdso-image-32.c
  CC      arch/x86/entry/vdso/vdso-image-32.o
  CC      arch/x86/lib/crc32-glue.o
  AR      drivers/video/backlight/built-in.a
  CC      fs/quota/quota_tree.o
  CC      net/core/stream.o
  CC      fs/iomap/direct-io.o
  CC      lib/crypto/mpi/generic_mpih-sub1.o
  CC      security/keys/permission.o
  CC      arch/x86/kernel/cpu/mce/severity.o
  CC      kernel/locking/spinlock.o
  CC      kernel/power/suspend.o
  CC      kernel/locking/osq_lock.o
  CC      kernel/sched/fair.o
  AR      arch/x86/entry/vdso/built-in.a
  CC      arch/x86/entry/syscall_32.o
  CC      arch/x86/entry/common.o
  CC      fs/notify/fdinfo.o
  CC      sound/core/control.o
  AS      arch/x86/lib/crc32-pclmul.o
  CC      arch/x86/lib/msr.o
  CC      kernel/printk/printk_ringbuffer.o
  CC      kernel/irq/chip.o
  CC      arch/x86/kernel/cpu/mtrr/amd.o
  CC      drivers/pci/msi/irqdomain.o
  CC      drivers/acpi/acpica/dsargs.o
  CC      mm/folio-compat.o
  CC      kernel/locking/qspinlock.o
  CC      crypto/asymmetric_keys/pkcs7.asn1.o
  CC      arch/x86/kernel/acpi/cstate.o
  CC      drivers/pnp/pnpacpi/core.o
  CC      drivers/pnp/core.o
  CC      arch/x86/pci/fixup.o
  CC      crypto/asymmetric_keys/pkcs7_parser.o
  AR      sound/i2c/other/built-in.a
  AR      sound/i2c/built-in.a
  CC      lib/crypto/mpi/generic_mpih-add1.o
  CC      drivers/pci/pcie/bwctrl.o
  CC      drivers/pnp/pnpacpi/rsparser.o
  CC      sound/core/seq/seq_fifo.o
  CC      lib/crypto/chacha.o
  AR      arch/x86/platform/efi/built-in.a
  AR      arch/x86/platform/intel-mid/built-in.a
  CC      lib/crypto/aes.o
  AR      drivers/video/console/built-in.a
  AR      arch/x86/platform/intel-quark/built-in.a
  CC      kernel/irq/dummychip.o
  AR      arch/x86/platform/olpc/built-in.a
  AR      drivers/video/fbdev/core/built-in.a
  AR      arch/x86/platform/scx200/built-in.a
  AR      drivers/video/fbdev/omap/built-in.a
  AR      arch/x86/platform/ts5500/built-in.a
  AR      arch/x86/platform/uv/built-in.a
  CC      security/keys/process_keys.o
  AR      drivers/video/fbdev/omap2/omapfb/dss/built-in.a
  AR      arch/x86/platform/built-in.a
  CC      kernel/irq/devres.o
  AR      drivers/video/fbdev/omap2/omapfb/displays/built-in.a
  AR      drivers/video/fbdev/omap2/omapfb/built-in.a
  CC      arch/x86/mm/ioremap.o
  AR      drivers/video/fbdev/omap2/built-in.a
  AR      drivers/video/fbdev/built-in.a
  CC      drivers/video/aperture.o
  CC      io_uring/rsrc.o
  AR      arch/x86/kernel/cpu/microcode/built-in.a
  CC      drivers/acpi/acpica/dscontrol.o
  CC      security/selinux/nlmsgtab.o
  CC      block/blk-core.o
  CC      arch/x86/kernel/cpu/mce/genpool.o
  CC      fs/quota/quota.o
  AR      fs/notify/built-in.a
  CC      security/selinux/netif.o
  CC      kernel/locking/rtmutex_api.o
  CC      arch/x86/kernel/cpu/mtrr/cyrix.o
  CC      mm/readahead.o
  CC      sound/core/seq/seq_prioq.o
  CC      fs/iomap/fiemap.o
  AR      arch/x86/kernel/acpi/built-in.a
  AR      crypto/asymmetric_keys/built-in.a
  CC      kernel/power/hibernate.o
  CC      crypto/algapi.o
  CC      kernel/rcu/sync.o
  CC      net/netlink/af_netlink.o
  CC      kernel/rcu/srcutree.o
  CC      kernel/printk/sysctl.o
  CC      kernel/rcu/tree.o
  CC      lib/crypto/mpi/mpicoder.o
  CC      kernel/power/snapshot.o
  CC      crypto/scatterwalk.o
  AS      arch/x86/lib/msr-reg.o
  CC      arch/x86/lib/msr-reg-export.o
  AR      drivers/pci/msi/built-in.a
  CC      ipc/namespace.o
  CC      lib/crypto/mpi/mpi-add.o
  CC      kernel/power/swap.o
  AS      arch/x86/entry/thunk.o
  CC      lib/crypto/mpi/mpi-bit.o
  CC      sound/core/misc.o
  CC      drivers/acpi/acpica/dsdebug.o
  CC      security/keys/request_key.o
  CC      net/sched/sch_frag.o
  CC      sound/core/device.o
  AR      arch/x86/entry/built-in.a
  CC      security/lsm_audit.o
  CC      drivers/pci/pcie/aspm.o
  CC      fs/proc/inode.o
  CC      net/netlink/genetlink.o
  CC      kernel/irq/kexec.o
  AS      arch/x86/lib/hweight.o
  CC      arch/x86/pci/acpi.o
  CC      arch/x86/lib/iomem.o
  AR      drivers/pnp/pnpacpi/built-in.a
  AR      kernel/printk/built-in.a
  CC      arch/x86/kernel/cpu/mce/intel.o
  CC      security/keys/request_key_auth.o
  CC      drivers/pnp/card.o
  CC      kernel/locking/qrwlock.o
  CC      arch/x86/kernel/cpu/mtrr/centaur.o
  CC      arch/x86/events/intel/bts.o
  CC      arch/x86/mm/extable.o
  CC      drivers/video/cmdline.o
  CC      drivers/acpi/acpica/dsfield.o
  CC      security/keys/user_defined.o
  CC      sound/core/seq/seq_timer.o
  CC      fs/iomap/seek.o
  CC      arch/x86/events/utils.o
  CC      ipc/mq_sysctl.o
  CC      arch/x86/pci/legacy.o
  CC      kernel/irq/autoprobe.o
  CC      arch/x86/lib/atomic64_32.o
  CC      drivers/video/nomodeset.o
  AR      net/bpf/built-in.a
  CC      arch/x86/kernel/cpu/mtrr/legacy.o
  CC      block/blk-sysfs.o
  CC      drivers/pnp/driver.o
  CC      arch/x86/lib/inat.o
  CC      kernel/irq/irqdomain.o
  CC      lib/crypto/mpi/mpi-cmp.o
  CC      kernel/dma/mapping.o
  CC      drivers/pci/pcie/pme.o
  AR      kernel/locking/built-in.a
  CC      kernel/dma/direct.o
  AR      arch/x86/lib/built-in.a
  AR      arch/x86/lib/lib.a
  CC      mm/swap.o
  CC      kernel/dma/ops_helpers.o
  CC      drivers/acpi/acpica/dsinit.o
  CC      fs/quota/kqid.o
  CC      drivers/video/hdmi.o
  CC      net/sched/sch_api.o
  CC      fs/proc/root.o
  CC      io_uring/notif.o
  CC      arch/x86/kernel/cpu/mce/amd.o
  CC      fs/quota/netlink.o
  CC      kernel/dma/remap.o
  CC      net/sched/sch_blackhole.o
  AR      ipc/built-in.a
  AR      arch/x86/kernel/cpu/mtrr/built-in.a
  CC      security/device_cgroup.o
  CC      lib/crypto/mpi/mpi-sub-ui.o
  CC      security/keys/proc.o
  CC      mm/truncate.o
  CC      security/selinux/netnode.o
  CC      net/core/scm.o
  CC      drivers/pnp/resource.o
  AR      drivers/acpi/pmic/built-in.a
  CC      net/ethtool/ioctl.o
  CC      net/ethtool/common.o
  CC      crypto/proc.o
  CC      fs/kernfs/mount.o
  CC      arch/x86/mm/mmap.o
  CC      fs/iomap/swapfile.o
  CC      arch/x86/pci/irq.o
  CC      drivers/acpi/acpica/dsmethod.o
  CC      sound/core/seq/seq_system.o
  CC      fs/sysfs/file.o
  CC      block/blk-flush.o
  CC      arch/x86/events/rapl.o
  CC      mm/vmscan.o
  CC      arch/x86/kernel/cpu/scattered.o
  CC      block/blk-settings.o
  CC      arch/x86/events/intel/ds.o
  CC      kernel/power/user.o
  CC      fs/devpts/inode.o
  AR      sound/drivers/opl3/built-in.a
  AR      sound/drivers/opl4/built-in.a
  AR      sound/drivers/mpu401/built-in.a
  AR      sound/drivers/vx/built-in.a
  AR      sound/isa/ad1816a/built-in.a
  AR      sound/drivers/pcsp/built-in.a
  AR      sound/isa/ad1848/built-in.a
  AR      sound/drivers/built-in.a
  AR      sound/isa/cs423x/built-in.a
  CC      fs/kernfs/inode.o
  AR      sound/isa/es1688/built-in.a
  AR      drivers/pci/pcie/built-in.a
  AR      sound/isa/galaxy/built-in.a
  AR      drivers/pci/pwrctrl/built-in.a
  AR      sound/isa/gus/built-in.a
  CC      drivers/acpi/acpica/dsmthdat.o
  AR      sound/isa/msnd/built-in.a
  CC      drivers/pci/hotplug/pci_hotplug_core.o
  AR      sound/isa/opti9xx/built-in.a
  AR      sound/isa/sb/built-in.a
  AR      sound/isa/wavefront/built-in.a
  AR      sound/isa/wss/built-in.a
  CC      drivers/pci/hotplug/acpi_pcihp.o
  AR      sound/isa/built-in.a
  CC      net/core/gen_stats.o
  CC      lib/crypto/mpi/mpi-div.o
  CC      kernel/power/poweroff.o
  CC      fs/proc/base.o
  CC      security/keys/sysctl.o
  CC      sound/core/info.o
  CC      fs/proc/generic.o
  CC      io_uring/tctx.o
  CC      arch/x86/events/intel/knc.o
  AR      drivers/amba/built-in.a
  AR      drivers/video/built-in.a
  CC      arch/x86/kernel/cpu/mce/threshold.o
  CC      crypto/aead.o
  CC      lib/crypto/arc4.o
  CC      arch/x86/mm/pgtable.o
  AR      fs/quota/built-in.a
  CC      arch/x86/mm/physaddr.o
  CC      kernel/irq/proc.o
  CC      sound/core/seq/seq_ports.o
  CC      fs/netfs/buffered_read.o
  CC      drivers/acpi/dptf/int340x_thermal.o
  AR      sound/pci/ac97/built-in.a
  AR      sound/pci/ali5451/built-in.a
  CC      drivers/acpi/acpica/dsobject.o
  AR      sound/pci/asihpi/built-in.a
  AR      sound/pci/au88x0/built-in.a
  AR      sound/pci/aw2/built-in.a
  AR      fs/iomap/built-in.a
  AR      sound/pci/ctxfi/built-in.a
  AR      sound/ppc/built-in.a
  CC      net/ethtool/netlink.o
  AR      sound/pci/ca0106/built-in.a
  AR      sound/arm/built-in.a
  AR      sound/pci/cs46xx/built-in.a
  CC      arch/x86/mm/tlb.o
  AR      sound/pci/cs5535audio/built-in.a
  AR      sound/pci/lola/built-in.a
  AR      sound/pci/lx6464es/built-in.a
  AR      sound/pci/echoaudio/built-in.a
  CC      drivers/acpi/x86/apple.o
  AR      sound/pci/emu10k1/built-in.a
  CC      sound/pci/hda/hda_bind.o
  AR      sound/pci/ice1712/built-in.a
  CC      sound/core/isadma.o
  CC      fs/sysfs/dir.o
  CC      drivers/acpi/acpica/dsopcode.o
  AR      kernel/power/built-in.a
  CC      lib/zlib_deflate/deflate.o
  CC      lib/lzo/lzo1x_compress.o
  CC      lib/lz4/lz4_decompress.o
  AR      fs/devpts/built-in.a
  CC      drivers/pnp/manager.o
  CC      lib/zstd/zstd_decompress_module.o
  CC      security/selinux/netport.o
  CC      drivers/acpi/tables.o
  CC      block/blk-ioc.o
  CC      security/keys/keyctl_pkey.o
  CC      lib/crypto/mpi/mpi-mod.o
  CC      lib/lzo/lzo1x_decompress_safe.o
  CC      sound/pci/hda/hda_codec.o
  CC      fs/kernfs/dir.o
  CC      fs/netfs/buffered_write.o
  AR      drivers/acpi/dptf/built-in.a
  CC      lib/zlib_deflate/deftree.o
  CC      arch/x86/kernel/apic/apic.o
  CC      arch/x86/kernel/kprobes/core.o
  CC      lib/xz/xz_dec_syms.o
  CC      net/netlink/policy.o
  AR      drivers/pci/hotplug/built-in.a
  CC      arch/x86/kernel/apic/apic_common.o
  AR      drivers/pci/controller/dwc/built-in.a
  AR      drivers/pci/controller/mobiveil/built-in.a
  AR      drivers/pci/controller/plda/built-in.a
  CC      arch/x86/pci/common.o
  AR      drivers/pci/controller/built-in.a
  AR      drivers/pci/switch/built-in.a
  CC      drivers/pci/access.o
  CC      arch/x86/kernel/apic/apic_noop.o
  LDS     arch/x86/kernel/vmlinux.lds
  CC      fs/netfs/direct_read.o
  CC      kernel/irq/migration.o
  CC      drivers/acpi/acpica/dspkginit.o
  CC      drivers/acpi/acpica/dsutils.o
  CC      net/ethtool/bitset.o
  CC      lib/zstd/decompress/huf_decompress.o
  CC      drivers/acpi/x86/cmos_rtc.o
  CC      arch/x86/kernel/cpu/topology_common.o
  CC      io_uring/filetable.o
  CC      fs/sysfs/symlink.o
  CC      crypto/geniv.o
  CC      sound/core/seq/seq_info.o
  CC      arch/x86/kernel/kprobes/opt.o
  CC      net/core/gen_estimator.o
  CC      lib/xz/xz_dec_stream.o
  AR      lib/lzo/built-in.a
  CC      lib/xz/xz_dec_lzma2.o
  AR      arch/x86/kernel/cpu/mce/built-in.a
  CC      lib/xz/xz_dec_bcj.o
  CC      drivers/pnp/support.o
  AS      arch/x86/kernel/head_32.o
  CC      lib/crypto/mpi/mpi-mul.o
  CC      drivers/pnp/interface.o
  CC      mm/shrinker.o
  AR      security/keys/built-in.a
  CC      lib/zlib_deflate/deflate_syms.o
  AR      kernel/dma/built-in.a
  CC      lib/zstd/decompress/zstd_ddict.o
  CC      arch/x86/events/intel/lbr.o
  CC      fs/kernfs/file.o
  AR      sound/sh/built-in.a
  CC      io_uring/rw.o
  CC      block/blk-map.o
  CC      drivers/acpi/acpica/dswexec.o
  CC      net/sched/cls_api.o
  CC      kernel/irq/cpuhotplug.o
  CC      net/sched/act_api.o
  CC      kernel/irq/pm.o
  CC      arch/x86/kernel/apic/ipi.o
  CC      arch/x86/kernel/cpu/topology_ext.o
  CC      arch/x86/mm/cpu_entry_area.o
  AR      sound/synth/emux/built-in.a
  AR      sound/synth/built-in.a
  CC      net/sched/sch_fifo.o
  CC      kernel/entry/common.o
  CC      drivers/acpi/x86/lpss.o
  CC      sound/core/seq/seq_dummy.o
  AR      drivers/clk/actions/built-in.a
  AR      drivers/clk/analogbits/built-in.a
  AR      lib/zlib_deflate/built-in.a
  AR      drivers/clk/bcm/built-in.a
  CC      mm/shmem.o
  CC      crypto/lskcipher.o
  CC      arch/x86/pci/early.o
  AR      drivers/clk/imgtec/built-in.a
  CC      fs/kernfs/symlink.o
  AR      net/netlink/built-in.a
  AR      drivers/clk/imx/built-in.a
  CC      net/sched/cls_cgroup.o
  AR      drivers/clk/ingenic/built-in.a
  CC      fs/sysfs/mount.o
  AR      drivers/clk/mediatek/built-in.a
  AR      drivers/clk/microchip/built-in.a
  AR      drivers/clk/mstar/built-in.a
  CC      drivers/dma/dw/core.o
  AR      drivers/clk/mvebu/built-in.a
  AR      drivers/soc/apple/built-in.a
  CC      drivers/pci/bus.o
  CC      arch/x86/mm/maccess.o
  AR      drivers/clk/ralink/built-in.a
  CC      security/selinux/status.o
  AR      drivers/soc/aspeed/built-in.a
  AR      drivers/clk/renesas/built-in.a
  AR      drivers/soc/bcm/built-in.a
  CC      drivers/acpi/acpica/dswload.o
  AR      drivers/clk/socfpga/built-in.a
  AR      drivers/soc/fsl/built-in.a
  AR      drivers/clk/sophgo/built-in.a
  CC      fs/netfs/direct_write.o
  AR      drivers/soc/fujitsu/built-in.a
  CC      net/core/net_namespace.o
  AR      drivers/clk/sprd/built-in.a
  CC      lib/crypto/mpi/mpih-cmp.o
  AR      drivers/soc/hisilicon/built-in.a
  AR      drivers/clk/starfive/built-in.a
  AR      drivers/soc/imx/built-in.a
  CC      drivers/pnp/quirks.o
  AR      drivers/soc/ixp4xx/built-in.a
  AR      drivers/clk/sunxi-ng/built-in.a
  AR      lib/lz4/built-in.a
  CC      net/core/secure_seq.o
  AR      drivers/soc/loongson/built-in.a
  AR      drivers/clk/ti/built-in.a
  AR      lib/xz/built-in.a
  AR      drivers/soc/mediatek/built-in.a
  AR      drivers/clk/versatile/built-in.a
  CC      arch/x86/kernel/cpu/topology_amd.o
  CC      arch/x86/kernel/cpu/common.o
  AR      drivers/clk/xilinx/built-in.a
  AR      arch/x86/kernel/kprobes/built-in.a
  AR      drivers/soc/microchip/built-in.a
  AR      drivers/clk/built-in.a
  CC      arch/x86/kernel/apic/vector.o
  AR      drivers/soc/nuvoton/built-in.a
  CC      kernel/sched/build_policy.o
  AR      drivers/soc/pxa/built-in.a
  CC      kernel/rcu/rcu_segcblist.o
  AR      drivers/soc/amlogic/built-in.a
  CC      drivers/virtio/virtio.o
  AR      drivers/soc/qcom/built-in.a
  AR      drivers/soc/renesas/built-in.a
  CC      drivers/acpi/osi.o
  AR      drivers/soc/rockchip/built-in.a
  AR      drivers/soc/sunxi/built-in.a
  AR      drivers/soc/ti/built-in.a
  CC      fs/proc/array.o
  CC      fs/netfs/iterator.o
  AR      drivers/soc/versatile/built-in.a
  AR      drivers/soc/xilinx/built-in.a
  AR      drivers/soc/built-in.a
  CC      arch/x86/mm/pgprot.o
  CC      security/selinux/ss/ebitmap.o
  CC      mm/util.o
  AR      sound/pci/korg1212/built-in.a
  CC      security/selinux/ss/hashtab.o
  CC      drivers/virtio/virtio_ring.o
  CC      lib/crypto/gf128mul.o
  CC      kernel/irq/msi.o
  CC      lib/zstd/decompress/zstd_decompress.o
  AR      sound/core/seq/built-in.a
  CC      sound/core/vmaster.o
  CC      drivers/acpi/acpica/dswload2.o
  CC      arch/x86/events/intel/p4.o
  CC      net/ethtool/strset.o
  CC      arch/x86/kernel/apic/init.o
  CC      block/blk-merge.o
  CC      arch/x86/pci/bus_numa.o
  CC      drivers/dma/dw/dw.o
  CC      drivers/acpi/x86/s2idle.o
  CC      lib/dim/dim.o
  AR      fs/kernfs/built-in.a
  CC      drivers/virtio/virtio_anchor.o
  CC      lib/crypto/mpi/mpih-div.o
  CC      drivers/acpi/osl.o
  AR      kernel/rcu/built-in.a
  CC      kernel/module/main.o
  CC      fs/sysfs/group.o
  CC      kernel/module/strict_rwx.o
  CC      kernel/sched/build_utility.o
  CC      drivers/pci/probe.o
  CC      arch/x86/mm/pgtable_32.o
  CC      fs/netfs/locking.o
  CC      drivers/pnp/system.o
  CC      crypto/skcipher.o
  CC      net/netfilter/core.o
  CC      drivers/acpi/acpica/dswscope.o
  CC      kernel/entry/syscall_user_dispatch.o
  CC      arch/x86/kernel/apic/hw_nmi.o
  CC      lib/fonts/fonts.o
  CC      arch/x86/kernel/cpu/rdrand.o
  CC      net/ethtool/linkinfo.o
  CC      lib/dim/net_dim.o
  CC      lib/zstd/decompress/zstd_decompress_block.o
  CC      sound/core/ctljack.o
  CC      drivers/acpi/x86/utils.o
  CC      lib/crypto/blake2s.o
  CC      io_uring/net.o
  AR      sound/usb/misc/built-in.a
  AR      sound/usb/usx2y/built-in.a
  AR      sound/usb/caiaq/built-in.a
  CC      drivers/dma/hsu/hsu.o
  AR      sound/usb/6fire/built-in.a
  AR      sound/usb/hiface/built-in.a
  AR      sound/usb/bcd2000/built-in.a
  AR      sound/usb/built-in.a
  CC      io_uring/poll.o
  CC      net/netfilter/nf_log.o
  CC      arch/x86/pci/amd_bus.o
  CC      drivers/acpi/acpica/dswstate.o
  CC      sound/pci/hda/hda_jack.o
  CC      drivers/dma/dw/idma32.o
  CC      kernel/module/kmod.o
  CC      drivers/acpi/x86/blacklist.o
  CC      fs/proc/fd.o
  CC      lib/fonts/font_8x16.o
  CC      block/blk-timeout.o
  CC      lib/argv_split.o
  AR      drivers/pnp/built-in.a
  CC      arch/x86/mm/iomap_32.o
  CC      arch/x86/kernel/apic/io_apic.o
  CC      sound/core/jack.o
  CC      fs/ext4/balloc.o
  AR      fs/sysfs/built-in.a
  CC      drivers/acpi/utils.o
  CC      kernel/time/time.o
  AR      sound/firewire/built-in.a
  CC      mm/mmzone.o
  CC      lib/crypto/mpi/mpih-mul.o
  AR      kernel/entry/built-in.a
  CC      arch/x86/events/intel/p6.o
  CC      arch/x86/kernel/cpu/match.o
  CC      security/selinux/ss/symtab.o
  CC      kernel/irq/affinity.o
  CC      net/core/flow_dissector.o
  CC      fs/ext4/bitmap.o
  CC      fs/netfs/main.o
  CC      net/ethtool/linkmodes.o
  AR      lib/fonts/built-in.a
  CC      net/ipv4/netfilter/nf_defrag_ipv4.o
  CC      net/xfrm/xfrm_policy.o
  CC      drivers/pci/host-bridge.o
  CC      net/xfrm/xfrm_state.o
  CC      drivers/acpi/acpica/evevent.o
  CC      net/unix/af_unix.o
  CC      drivers/virtio/virtio_pci_modern_dev.o
  CC      security/selinux/ss/sidtab.o
  AR      drivers/acpi/x86/built-in.a
  CC      net/xfrm/xfrm_hash.o
  CC      net/unix/garbage.o
  CC      arch/x86/kernel/cpu/bugs.o
  CC      arch/x86/kernel/head32.o
  CC      drivers/dma/dw/acpi.o
  CC      lib/dim/rdma_dim.o
  AR      drivers/dma/hsu/built-in.a
  CC      mm/vmstat.o
  CC      crypto/seqiv.o
  CC      arch/x86/mm/hugetlbpage.o
  CC      block/blk-lib.o
  CC      fs/jbd2/transaction.o
  AR      arch/x86/pci/built-in.a
  CC      kernel/irq/matrix.o
  AR      sound/sparc/built-in.a
  CC      net/netfilter/nf_queue.o
  CC      arch/x86/kernel/ebda.o
  CC      fs/proc/proc_tty.o
  CC      drivers/acpi/acpica/evgpe.o
  CC      sound/core/hwdep.o
  AR      sound/pci/mixart/built-in.a
  CC      crypto/echainiv.o
  CC      fs/ext4/block_validity.o
  CC      lib/bug.o
  CC      net/sched/ematch.o
  CC      sound/pci/hda/hda_auto_parser.o
  CC      net/ipv6/netfilter/ip6_tables.o
  CC      kernel/time/timer.o
  CC      arch/x86/events/intel/pt.o
  CC      lib/crypto/mpi/mpi-pow.o
  CC      net/xfrm/xfrm_input.o
  AR      lib/dim/built-in.a
  CC      sound/core/timer.o
  CC      sound/core/hrtimer.o
  CC      net/ethtool/rss.o
  CC      net/unix/sysctl_net_unix.o
  CC      net/ipv6/af_inet6.o
  CC      drivers/pci/remove.o
  CC      drivers/virtio/virtio_pci_legacy_dev.o
  CC      drivers/acpi/acpica/evgpeblk.o
  CC      kernel/futex/core.o
  CC      arch/x86/mm/dump_pagetables.o
  CC      drivers/tty/vt/vt_ioctl.o
  CC      drivers/tty/vt/vc_screen.o
  AR      drivers/dma/dw/built-in.a
  AR      drivers/dma/idxd/built-in.a
  AR      drivers/dma/amd/built-in.a
  AR      drivers/dma/mediatek/built-in.a
  AR      drivers/dma/qcom/built-in.a
  AR      drivers/dma/stm32/built-in.a
  CC      drivers/tty/vt/selection.o
  AR      drivers/dma/ti/built-in.a
  CC      fs/proc/cmdline.o
  AR      drivers/dma/xilinx/built-in.a
  CC      drivers/dma/dmaengine.o
  CC      lib/buildid.o
  CC      crypto/ahash.o
  CC      net/ipv4/netfilter/nf_reject_ipv4.o
  CC      crypto/shash.o
  CC      block/blk-mq.o
  CC      arch/x86/events/intel/uncore.o
  CC      kernel/cgroup/cgroup.o
  CC      io_uring/eventfd.o
  CC      kernel/module/tree_lookup.o
  CC      security/selinux/ss/avtab.o
  CC      lib/crypto/mpi/mpiutil.o
  CC      drivers/acpi/acpica/evgpeinit.o
  CC      fs/ramfs/inode.o
  CC      io_uring/uring_cmd.o
  CC      arch/x86/kernel/apic/msi.o
  CC      fs/netfs/misc.o
  CC      fs/ext4/dir.o
  CC      drivers/pci/pci.o
  CC      drivers/virtio/virtio_pci_modern.o
  AR      kernel/irq/built-in.a
  CC      fs/proc/consoles.o
  AR      net/sched/built-in.a
  CC      drivers/tty/hvc/hvc_console.o
  CC      lib/zstd/zstd_common_module.o
  CC      net/netfilter/nf_sockopt.o
  CC      drivers/tty/serial/8250/8250_core.o
  AR      drivers/tty/ipwireless/built-in.a
  CC      fs/ramfs/file-mmu.o
  CC      mm/backing-dev.o
  CC      net/ethtool/linkstate.o
  CC      sound/pci/hda/hda_sysfs.o
  CC      arch/x86/mm/highmem_32.o
  CC      drivers/acpi/acpica/evgpeutil.o
  CC      lib/zstd/common/debug.o
  CC      kernel/futex/syscalls.o
  CC      io_uring/openclose.o
  CC      kernel/futex/pi.o
  CC      fs/jbd2/commit.o
  CC      drivers/tty/tty_io.o
  CC      arch/x86/kernel/cpu/aperfmperf.o
  CC      kernel/module/kallsyms.o
  CC      net/ipv4/netfilter/ip_tables.o
  CC      fs/hugetlbfs/inode.o
  CC      drivers/tty/vt/keyboard.o
  CC      net/core/sysctl_net_core.o
  CC      lib/zstd/common/entropy_common.o
  AR      lib/crypto/mpi/built-in.a
  CC      lib/crypto/blake2s-generic.o
  CC      drivers/char/hw_random/core.o
  CC      fs/proc/cpuinfo.o
  CC      lib/zstd/common/error_private.o
  CC      sound/core/pcm.o
  CC      crypto/akcipher.o
  CC      drivers/acpi/acpica/evglock.o
  CC      drivers/char/agp/backend.o
  CC      arch/x86/kernel/apic/probe_32.o
  CC      drivers/pci/pci-driver.o
  CC      lib/zstd/common/fse_decompress.o
  CC      drivers/dma/virt-dma.o
  CC      net/ipv6/netfilter/ip6table_filter.o
  CC      kernel/time/hrtimer.o
  CC      drivers/dma/acpi-dma.o
  CC      fs/netfs/objects.o
  AR      fs/ramfs/built-in.a
  CC      block/blk-mq-tag.o
  CC      net/netfilter/utils.o
  CC      sound/pci/hda/hda_controller.o
  CC      security/selinux/ss/policydb.o
  CC      lib/crypto/sha1.o
  AR      drivers/tty/hvc/built-in.a
  CC      drivers/virtio/virtio_pci_common.o
  AR      arch/x86/mm/built-in.a
  CC      net/netfilter/nfnetlink.o
  CC      fs/ext4/ext4_jbd2.o
  CC      sound/pci/hda/hda_proc.o
  AR      net/unix/built-in.a
  CC      lib/crypto/sha256.o
  CC      drivers/char/mem.o
  CC      arch/x86/kernel/cpu/cpuid-deps.o
  CC      security/selinux/ss/services.o
  CC      fs/netfs/read_collect.o
  CC      net/xfrm/xfrm_output.o
  CC      drivers/acpi/acpica/evhandler.o
  AR      arch/x86/kernel/apic/built-in.a
  AR      sound/spi/built-in.a
  CC      arch/x86/events/intel/uncore_nhmex.o
  CC      kernel/module/procfs.o
  CC      io_uring/sqpoll.o
  CC      drivers/tty/serial/8250/8250_platform.o
  CC      kernel/futex/requeue.o
  CC      fs/proc/devices.o
  CC      net/ethtool/debug.o
  CC      lib/zstd/common/zstd_common.o
  AR      drivers/iommu/amd/built-in.a
  CC      mm/mm_init.o
  AR      drivers/iommu/intel/built-in.a
  AR      drivers/iommu/arm/arm-smmu/built-in.a
  AR      drivers/iommu/arm/arm-smmu-v3/built-in.a
  AR      drivers/iommu/arm/built-in.a
  AR      lib/zstd/built-in.a
  CC      net/ipv4/route.o
  AR      drivers/iommu/iommufd/built-in.a
  AR      drivers/iommu/riscv/built-in.a
  CC      arch/x86/events/msr.o
  CC      drivers/char/hw_random/intel-rng.o
  CC      drivers/iommu/iommu.o
  AR      kernel/sched/built-in.a
  CC      drivers/acpi/acpica/evmisc.o
  CC      arch/x86/kernel/cpu/umwait.o
  CC      sound/pci/hda/hda_hwdep.o
  CC      drivers/char/agp/generic.o
  CC      kernel/cgroup/rstat.o
  CC      drivers/virtio/virtio_pci_legacy.o
  CC      fs/jbd2/recovery.o
  CC      crypto/sig.o
  AR      lib/crypto/built-in.a
  CC      lib/clz_tab.o
  CC      sound/core/pcm_native.o
  CC      lib/cmdline.o
  AR      drivers/dma/built-in.a
  CC      net/ethtool/wol.o
  CC      net/core/dev.o
  CC      lib/cpumask.o
  CC      kernel/module/sysfs.o
  CC      drivers/tty/vt/vt.o
  CC      drivers/acpi/acpica/evregion.o
  CC      net/packet/af_packet.o
  CC      fs/proc/interrupts.o
  CC      arch/x86/kernel/platform-quirks.o
  AR      sound/pci/nm256/built-in.a
  CC      drivers/char/agp/isoch.o
  CC      kernel/futex/waitwake.o
  CC      drivers/pci/search.o
  AR      sound/pci/oxygen/built-in.a
  CC      net/ipv4/inetpeer.o
  CC      fs/netfs/read_pgpriv2.o
  CC      drivers/tty/serial/8250/8250_pnp.o
  AR      fs/hugetlbfs/built-in.a
  CC      net/ipv4/netfilter/iptable_filter.o
  CC      drivers/acpi/acpica/evrgnini.o
  CC      drivers/char/hw_random/amd-rng.o
  CC      lib/ctype.o
  CC      net/ipv6/netfilter/ip6table_mangle.o
  CC      lib/dec_and_lock.o
  CC      fs/netfs/read_retry.o
  MKCAP   arch/x86/kernel/cpu/capflags.c
  CC      drivers/virtio/virtio_pci_admin_legacy_io.o
  CC      fs/netfs/read_single.o
  CC      net/core/dev_addr_lists.o
  CC      fs/jbd2/checkpoint.o
  CC      net/netfilter/nfnetlink_log.o
  CC      drivers/acpi/reboot.o
  CC      mm/percpu.o
  CC      fs/ext4/extents.o
  COPY    drivers/tty/vt/defkeymap.c
  CC      sound/core/pcm_lib.o
  CC      sound/pci/hda/hda_intel.o
  CC      arch/x86/events/intel/uncore_snb.o
  CC      kernel/time/sleep_timeout.o
  CC      kernel/time/timekeeping.o
  CC      fs/proc/loadavg.o
  CC      crypto/kpp.o
  CC      lib/decompress.o
  ASN.1   crypto/rsapubkey.asn1.[ch]
  CC      arch/x86/kernel/process_32.o
  CC      drivers/acpi/acpica/evsci.o
  CC      lib/decompress_bunzip2.o
  CC      net/xfrm/xfrm_sysctl.o
  CC      drivers/char/random.o
  AR      kernel/module/built-in.a
  CC      net/xfrm/xfrm_replay.o
  CC      fs/ext4/extents_status.o
  CC      drivers/tty/serial/8250/8250_rsa.o
  CC      fs/proc/meminfo.o
  CC      net/ethtool/features.o
  CC      io_uring/xattr.o
  CC      drivers/char/agp/amd64-agp.o
  CC      drivers/acpi/nvs.o
  AR      kernel/futex/built-in.a
  CC      drivers/char/hw_random/geode-rng.o
  CC      drivers/char/hw_random/via-rng.o
  CC      net/ipv6/anycast.o
  CC      drivers/pci/rom.o
  CC      drivers/virtio/virtio_input.o
  CC      drivers/acpi/acpica/evxface.o
  CC      security/selinux/ss/conditional.o
  CC      io_uring/nop.o
  AR      net/dsa/built-in.a
  CC      net/ipv4/netfilter/iptable_mangle.o
  CC      arch/x86/events/intel/uncore_snbep.o
  CC      sound/core/pcm_misc.o
  CC      block/blk-stat.o
  CC      fs/jbd2/revoke.o
  CC      fs/netfs/rolling_buffer.o
  CC      kernel/cgroup/namespace.o
  CC      arch/x86/events/intel/uncore_discovery.o
  CC      net/sunrpc/auth_gss/auth_gss.o
  ASN.1   crypto/rsaprivkey.asn1.[ch]
  CC      lib/decompress_inflate.o
  CC      crypto/rsa.o
  CC      drivers/iommu/iommu-traces.o
  CC      drivers/tty/serial/8250/8250_port.o
  CC      net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
  AR      net/wireless/tests/built-in.a
  CC      fs/proc/stat.o
  CC      net/wireless/core.o
  CC      drivers/acpi/acpica/evxfevnt.o
  AR      drivers/char/hw_random/built-in.a
  AR      net/mac80211/tests/built-in.a
  CC      net/mac80211/main.o
  CC      net/ipv4/netfilter/ipt_REJECT.o
  CC      fs/fat/cache.o
  CC      fs/fat/dir.o
  CC      drivers/pci/setup-res.o
  CC      drivers/char/agp/intel-agp.o
  CC      net/sunrpc/clnt.o
  CC      net/sunrpc/xprt.o
  CC      drivers/virtio/virtio_dma_buf.o
  CC      arch/x86/kernel/signal.o
  CC      io_uring/fs.o
  CC      arch/x86/kernel/signal_32.o
  CC      net/netfilter/nf_conntrack_core.o
  CC      net/ethtool/privflags.o
  CC      drivers/acpi/acpica/evxfgpe.o
  CC      block/blk-mq-sysfs.o
  CC      net/xfrm/xfrm_device.o
  CC      lib/decompress_unlz4.o
  CC      block/blk-mq-cpumap.o
  CC      drivers/acpi/wakeup.o
  AR      sound/pci/hda/built-in.a
  AR      sound/pci/pcxhr/built-in.a
  CC      crypto/rsa_helper.o
  AR      sound/pci/riptide/built-in.a
  CC      fs/jbd2/journal.o
  AR      sound/pci/rme9652/built-in.a
  AR      sound/pci/trident/built-in.a
  CC      kernel/time/ntp.o
  AR      sound/pci/ymfpci/built-in.a
  CC      kernel/time/clocksource.o
  CC      sound/core/pcm_memory.o
  AR      sound/pci/vx222/built-in.a
  CC      fs/proc/uptime.o
  AR      sound/pci/built-in.a
  CC      arch/x86/kernel/cpu/powerflags.o
  CC      kernel/cgroup/cgroup-v1.o
  CC      net/sunrpc/auth_gss/gss_mech_switch.o
  CC      fs/netfs/write_collect.o
  CC      arch/x86/kernel/cpu/topology.o
  CC      kernel/cgroup/freezer.o
  CC      fs/fat/fatent.o
  CC      security/selinux/ss/mls.o
  CC      drivers/pci/irq.o
  CC      fs/isofs/namei.o
  CC      drivers/char/misc.o
  AR      drivers/virtio/built-in.a
  CC      net/ipv6/netfilter/nf_conntrack_reasm.o
  CC      net/ipv6/netfilter/nf_reject_ipv6.o
  CC      drivers/acpi/acpica/evxfregn.o
  CC      drivers/tty/vt/consolemap.o
  CC      crypto/rsa-pkcs1pad.o
  CC      drivers/iommu/iommu-sysfs.o
  CC      drivers/char/agp/intel-gtt.o
  CC      lib/decompress_unlzma.o
  CC      arch/x86/kernel/traps.o
  CC [M]  net/ipv4/netfilter/iptable_nat.o
  CC      io_uring/splice.o
  CC      drivers/tty/serial/serial_core.o
  CC      block/blk-mq-sched.o
  CC      sound/core/memalloc.o
  CC      fs/isofs/inode.o
  CC      fs/proc/util.o
  CC      fs/proc/version.o
  CC      net/netfilter/nf_conntrack_standalone.o
  CC      mm/slab_common.o
  CC      drivers/acpi/acpica/exconcat.o
  CC      fs/proc/softirqs.o
  CC      net/ethtool/rings.o
  CC      kernel/trace/trace_clock.o
  CC      kernel/bpf/core.o
  CC      drivers/tty/n_tty.o
  CC      drivers/pci/vpd.o
  CC      crypto/rsassa-pkcs1.o
  CC      net/netfilter/nf_conntrack_expect.o
  CC      net/xfrm/xfrm_nat_keepalive.o
  CC      kernel/time/jiffies.o
  CC      drivers/iommu/dma-iommu.o
  CC      fs/ext4/file.o
  CC      fs/nfs/client.o
  CC      drivers/acpi/acpica/exconfig.o
  AR      net/packet/built-in.a
  CC      drivers/char/virtio_console.o
  CC      lib/decompress_unlzo.o
  CC      fs/netfs/write_issue.o
  CC      kernel/trace/ring_buffer.o
  CC      kernel/trace/trace.o
  CC      arch/x86/events/intel/cstate.o
  CC      fs/nfs/dir.o
  HOSTCC  drivers/tty/vt/conmakehash
  CC      fs/proc/namespaces.o
  CC      fs/fat/file.o
  CC      drivers/tty/serial/8250/8250_dma.o
  CC      io_uring/sync.o
  AR      drivers/char/agp/built-in.a
  CC      crypto/acompress.o
  CC      kernel/time/timer_list.o
  CC      kernel/time/timeconv.o
  CC      net/sunrpc/auth_gss/svcauth_gss.o
  CC      security/selinux/ss/context.o
  CC      kernel/cgroup/legacy_freezer.o
  CC      drivers/tty/vt/defkeymap.o
  CC      sound/core/pcm_timer.o
  CC      fs/exportfs/expfs.o
  CC      drivers/acpi/acpica/exconvrt.o
  CC      block/ioctl.o
  AR      net/ipv4/netfilter/built-in.a
  CC      net/ipv4/protocol.o
  CC      fs/lockd/clntlock.o
  CONMK   drivers/tty/vt/consolemap_deftbl.c
  CC      fs/nls/nls_base.o
  CC      drivers/tty/vt/consolemap_deftbl.o
  CC      net/ipv6/netfilter/ip6t_ipv6header.o
  AR      drivers/tty/vt/built-in.a
  AR      fs/unicode/built-in.a
  CC      drivers/acpi/acpica/excreate.o
  CC      lib/decompress_unxz.o
  CC      fs/lockd/clntproc.o
  CC      drivers/pci/setup-bus.o
  CC      net/ipv6/ip6_output.o
  CC      net/ethtool/channels.o
  CC      fs/isofs/dir.o
  CC      drivers/iommu/iova.o
  CC      net/sunrpc/auth_gss/gss_rpc_upcall.o
  CC      fs/proc/self.o
  AR      arch/x86/events/intel/built-in.a
  CC      net/mac80211/status.o
  AR      arch/x86/events/built-in.a
  CC      drivers/acpi/sleep.o
  CC      kernel/time/timecounter.o
  CC      drivers/acpi/acpica/exdebug.o
  CC      kernel/cgroup/pids.o
  CC      drivers/tty/serial/8250/8250_dwlib.o
  CC      fs/nls/nls_cp437.o
  CC      kernel/time/alarmtimer.o
  CC      sound/core/seq_device.o
  CC      fs/autofs/init.o
  CC      fs/proc/thread_self.o
  CC      io_uring/msg_ring.o
  CC      net/xfrm/xfrm_algo.o
  AR      fs/exportfs/built-in.a
  CC      fs/ext4/fsmap.o
  CC      net/wireless/sysfs.o
  AR      sound/parisc/built-in.a
  CC      fs/isofs/util.o
  CC      crypto/scompress.o
  CC      net/netfilter/nf_conntrack_helper.o
  CC      lib/decompress_unzstd.o
  CC      net/wireless/radiotap.o
  CC      fs/fat/inode.o
  CC      net/wireless/util.o
  CC      security/selinux/netlabel.o
  CC      fs/netfs/write_retry.o
  AR      fs/jbd2/built-in.a
  AR      sound/pcmcia/vx/built-in.a
  AR      sound/pcmcia/pdaudiocf/built-in.a
  CC      fs/ext4/fsync.o
  AR      sound/pcmcia/built-in.a
  AR      drivers/gpu/host1x/built-in.a
  CC      fs/nls/nls_ascii.o
  CC      drivers/acpi/acpica/exdump.o
  CC      drivers/char/hpet.o
  CC      block/genhd.o
  CC      net/ipv4/ip_input.o
  AR      drivers/gpu/vga/built-in.a
  CC      crypto/algboss.o
  CC      net/ipv6/netfilter/ip6t_REJECT.o
  AR      drivers/gpu/drm/tests/built-in.a
  AR      drivers/gpu/drm/arm/built-in.a
  AR      drivers/gpu/drm/clients/built-in.a
  CC      drivers/gpu/drm/display/drm_display_helper_mod.o
  CC      drivers/gpu/drm/ttm/ttm_tt.o
  CC      kernel/cgroup/rdma.o
  CC      fs/proc/proc_sysctl.o
  AR      sound/core/built-in.a
  AR      sound/mips/built-in.a
  CC      mm/compaction.o
  AR      sound/soc/built-in.a
  AR      sound/atmel/built-in.a
  CC      sound/hda/hda_bus_type.o
  CC      drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
  CC      fs/isofs/rock.o
  CC      drivers/tty/serial/8250/8250_pcilib.o
  CC      fs/autofs/inode.o
  CC      fs/lockd/clntxdr.o
  CC      drivers/acpi/acpica/exfield.o
  CC      lib/dump_stack.o
  CC      crypto/testmgr.o
  CC      arch/x86/kernel/cpu/proc.o
  CC      fs/nls/nls_iso8859-1.o
  CC      net/ethtool/coalesce.o
  AR      drivers/iommu/built-in.a
  CC      fs/lockd/host.o
  CC      kernel/time/posix-timers.o
  CC      io_uring/advise.o
  CC      drivers/gpu/drm/ttm/ttm_bo.o
  CC      fs/isofs/export.o
  CC      kernel/events/core.o
  CC      fs/nls/nls_utf8.o
  CC      net/netfilter/nf_conntrack_proto.o
  CC      drivers/acpi/acpica/exfldio.o
  CC      kernel/events/ring_buffer.o
  AR      fs/netfs/built-in.a
  CC      net/xfrm/xfrm_user.o
  CC      arch/x86/kernel/idt.o
  CC      net/sunrpc/auth_gss/gss_rpc_xdr.o
  CC      drivers/pci/vc.o
  CC      kernel/cgroup/cpuset.o
  CC      fs/fat/misc.o
  CC      net/ipv4/ip_fragment.o
  CC      sound/hda/hdac_bus.o
  CC      drivers/char/nvram.o
  CC      drivers/tty/serial/8250/8250_early.o
  CC      lib/earlycpio.o
  CC      arch/x86/kernel/cpu/feat_ctl.o
  AR      kernel/bpf/built-in.a
  CC      lib/extable.o
  CC      crypto/cmac.o
  CC      drivers/tty/tty_ioctl.o
  AR      fs/nls/built-in.a
  CC      drivers/gpu/drm/display/drm_dp_helper.o
  CC      net/mac80211/driver-ops.o
  CC      net/netfilter/nf_conntrack_proto_generic.o
  CC      fs/autofs/root.o
  CC      drivers/tty/serial/serial_base_bus.o
  AR      security/selinux/built-in.a
  AR      security/built-in.a
  CC      net/sunrpc/auth_gss/trace.o
  CC      arch/x86/kernel/irq.o
  CC      net/ipv6/ip6_input.o
  CC      block/ioprio.o
  CC      block/badblocks.o
  CC      drivers/acpi/acpica/exmisc.o
  AR      net/ipv6/netfilter/built-in.a
  CC      mm/show_mem.o
  CC      fs/ext4/hash.o
  CC      fs/isofs/joliet.o
  CC      io_uring/epoll.o
  CC      drivers/pci/mmap.o
  CC      lib/flex_proportions.o
  CC      arch/x86/kernel/cpu/intel.o
  CC      drivers/pci/devres.o
  CC      fs/proc/proc_net.o
  CC      crypto/hmac.o
  CC      net/ethtool/pause.o
  CC      drivers/gpu/drm/ttm/ttm_bo_util.o
  CC      drivers/tty/serial/8250/8250_exar.o
  CC      kernel/cgroup/misc.o
  CC      drivers/tty/serial/serial_ctrl.o
  CC      fs/lockd/svc.o
  CC      drivers/acpi/acpica/exmutex.o
  CC      sound/hda/hdac_device.o
  CC      fs/fat/nfs.o
  CC      sound/hda/hdac_sysfs.o
  CC      sound/hda/hdac_regmap.o
  AR      drivers/char/built-in.a
  CC      fs/nfs/file.o
  CC      fs/lockd/svclock.o
  CC      kernel/time/posix-cpu-timers.o
  CC      kernel/time/posix-clock.o
  CC      lib/idr.o
  CC      fs/isofs/compress.o
  CC      kernel/trace/trace_output.o
  CC      io_uring/statx.o
  CC      mm/interval_tree.o
  CC      fs/autofs/symlink.o
  CC      drivers/acpi/acpica/exnames.o
  CC      arch/x86/kernel/cpu/tsx.o
  CC      net/netlabel/netlabel_user.o
  CC      sound/hda/hdac_controller.o
  CC      drivers/pci/proc.o
  CC      fs/ext4/ialloc.o
  CC      mm/list_lru.o
  CC      kernel/fork.o
  CC      net/wireless/reg.o
  CC      drivers/tty/tty_ldisc.o
  CC      drivers/tty/tty_buffer.o
  CC      net/netfilter/nf_conntrack_proto_tcp.o
  CC      block/blk-rq-qos.o
  CC      net/ipv4/ip_forward.o
  CC      crypto/crypto_null.o
  CC      drivers/gpu/drm/i915/i915_config.o
  CC      drivers/tty/serial/8250/8250_lpss.o
  CC      fs/proc/kcore.o
  CC      lib/iomem_copy.o
  CC      drivers/acpi/acpica/exoparg1.o
  CC      net/core/dst.o
  CC      arch/x86/kernel/cpu/intel_epb.o
  CC      lib/irq_regs.o
  CC      fs/fat/namei_vfat.o
  CC      drivers/gpu/drm/ttm/ttm_bo_vm.o
  CC      drivers/gpu/drm/i915/i915_driver.o
  CC      arch/x86/kernel/cpu/amd.o
  CC      net/ethtool/eee.o
  CC      net/mac80211/sta_info.o
  CC      net/mac80211/wep.o
  CC      drivers/acpi/device_sysfs.o
  CC      fs/proc/vmcore.o
  CC      io_uring/timeout.o
  CC      fs/autofs/waitq.o
  AR      fs/isofs/built-in.a
  CC      io_uring/fdinfo.o
  CC      lib/is_single_threaded.o
  CC      mm/workingset.o
  CC      net/ethtool/tsinfo.o
  CC      net/rfkill/core.o
  CC      net/ipv6/addrconf.o
  CC      kernel/events/callchain.o
  CC      crypto/md5.o
  CC      block/disk-events.o
  CC      fs/ext4/indirect.o
  CC      kernel/time/itimer.o
  CC      kernel/cgroup/debug.o
  CC      sound/hda/hdac_stream.o
  CC      drivers/acpi/acpica/exoparg2.o
  CC      fs/ext4/inline.o
  CC      drivers/acpi/acpica/exoparg3.o
  CC      drivers/pci/pci-sysfs.o
  CC      kernel/exec_domain.o
  CC      net/netlabel/netlabel_kapi.o
  CC      kernel/trace/trace_seq.o
  CC      drivers/tty/serial/8250/8250_mid.o
  CC      drivers/gpu/drm/display/drm_dp_mst_topology.o
  CC      lib/klist.o
  CC      fs/lockd/svcshare.o
  CC      net/sunrpc/socklib.o
  CC      net/ipv4/ip_options.o
In file included from /workspace/kernel/drivers/gpu/drm/i915/display/intel_bw.h:12,
                 from /workspace/kernel/drivers/gpu/drm/i915/i915_driver.c:50:
/workspace/kernel/drivers/gpu/drm/i915/display/intel_display_power.h: In function ‘intel_display_power_put’:
  CC      net/sunrpc/auth_gss/gss_krb5_mech.o
/workspace/kernel/drivers/gpu/drm/i915/display/intel_display_power.h:228:43: error: passing argument 1 of ‘intel_display_power_put_unchecked’ from incompatible pointer type [-Werror=incompatible-pointer-types]
  228 |         intel_display_power_put_unchecked(display, domain);
      |                                           ^~~~~~~
      |                                           |
      |                                           struct intel_display *
/workspace/kernel/drivers/gpu/drm/i915/display/intel_display_power.h:220:65: note: expected ‘struct drm_i915_private *’ but argument is of type ‘struct intel_display *’
  220 | void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
      |                                        ~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~
  CC      drivers/gpu/drm/ttm/ttm_module.o
  CC      net/netlabel/netlabel_domainhash.o
  CC      net/sunrpc/auth_gss/gss_krb5_seal.o
  CC      net/netfilter/nf_conntrack_proto_udp.o
  AR      net/xfrm/built-in.a
  CC      io_uring/cancel.o
  CC      drivers/acpi/acpica/exoparg6.o
  CC      crypto/sha256_generic.o
  CC      lib/kobject.o
  CC      arch/x86/kernel/cpu/hygon.o
  CC      drivers/tty/serial/serial_port.o
  CC      fs/autofs/expire.o
  CC      fs/proc/kmsg.o
  CC      fs/lockd/svcproc.o
  CC      mm/debug.o
  CC      crypto/sha512_generic.o
  CC      kernel/trace/trace_stat.o
  CC      fs/nfs/getroot.o
  CC      block/blk-ia-ranges.o
  CC      net/sunrpc/xprtsock.o
  CC      net/core/netevent.o
  CC      fs/9p/vfs_super.o
  CC      net/core/neighbour.o
  AR      kernel/cgroup/built-in.a
  CC      net/netlabel/netlabel_addrlist.o
  CC      drivers/tty/serial/8250/8250_pci.o
  CC      drivers/acpi/acpica/exprep.o
  CC      net/rfkill/input.o
  CC      net/ethtool/cabletest.o
  CC      fs/fat/namei_msdos.o
  CC      kernel/time/clockevents.o
  CC      drivers/gpu/drm/ttm/ttm_execbuf_util.o
  CC      net/sunrpc/sched.o
  CC      block/early-lookup.o
  CC      sound/hda/array.o
  CC      drivers/tty/serial/earlycon.o
  CC      arch/x86/kernel/cpu/centaur.o
  CC      drivers/pci/slot.o
  CC      fs/proc/page.o
  CC      lib/kobject_uevent.o
cc1: all warnings being treated as errors
make[6]: *** [/workspace/kernel/scripts/Makefile.build:207: drivers/gpu/drm/i915/i915_driver.o] Error 1
make[5]: *** [/workspace/kernel/scripts/Makefile.build:465: drivers/gpu/drm/i915] Error 2
make[5]: *** Waiting for unfinished jobs....
  CC      lib/logic_pio.o
  CC      drivers/acpi/acpica/exregion.o
  CC      arch/x86/kernel/irq_32.o
  CC      drivers/gpu/drm/display/drm_dsc_helper.o
  CC      net/sunrpc/auth_gss/gss_krb5_unseal.o
  CC      io_uring/waitid.o
  CC      net/9p/mod.o
  CC      net/9p/client.o
  CC      net/sunrpc/auth_gss/gss_krb5_wrap.o
  CC      fs/autofs/dev-ioctl.o
  CC      drivers/gpu/drm/display/drm_hdcp_helper.o
  CC      crypto/sha3_generic.o
  AR      net/rfkill/built-in.a
  CC      fs/9p/vfs_inode.o
  CC      drivers/tty/serial/8250/8250_pericom.o
  CC      fs/lockd/svcsubs.o
  CC      io_uring/register.o
  CC      arch/x86/kernel/cpu/transmeta.o
  CC      mm/gup.o
  CC      kernel/trace/trace_printk.o
  CC      kernel/time/tick-common.o
  CC      net/core/rtnetlink.o
  CC      net/netfilter/nf_conntrack_proto_icmp.o
  AR      sound/x86/built-in.a
  CC      drivers/gpu/drm/display/drm_hdmi_helper.o
  CC      sound/hda/hdmi_chmap.o
  CC      drivers/gpu/drm/ttm/ttm_range_manager.o
  CC      drivers/acpi/acpica/exresnte.o
  CC      block/bounce.o
  CC      drivers/connector/cn_queue.o
  CC      drivers/acpi/device_pm.o
  CC      lib/maple_tree.o
  CC      net/ipv4/ip_output.o
  CC      fs/ext4/inode.o
  CC      drivers/connector/connector.o
  CC      fs/nfs/inode.o
  CC      arch/x86/kernel/dumpstack_32.o
  AR      fs/fat/built-in.a
  CC      drivers/pci/pci-acpi.o
  CC      net/wireless/scan.o
  CC      drivers/tty/tty_port.o
  CC      net/netlabel/netlabel_mgmt.o
  AR      fs/proc/built-in.a
  CC      net/9p/error.o
  CC      net/dns_resolver/dns_key.o
  CC      net/ethtool/tunnels.o
  CC      crypto/ecb.o
  CC      drivers/acpi/acpica/exresolv.o
  CC      arch/x86/kernel/cpu/zhaoxin.o
  CC      arch/x86/kernel/cpu/vortex.o
  CC      net/9p/protocol.o
  AR      drivers/tty/serial/8250/built-in.a
  AR      drivers/tty/serial/built-in.a
  AR      sound/xen/built-in.a
  CC      net/netfilter/nf_conntrack_extend.o
  CC      drivers/acpi/acpica/exresop.o
  CC      kernel/time/tick-broadcast.o
  AR      fs/hostfs/built-in.a
  CC      net/ipv6/addrlabel.o
  CC      net/netlabel/netlabel_unlabeled.o
  CC      drivers/gpu/drm/ttm/ttm_resource.o
  CC      drivers/pci/iomap.o
  AR      fs/autofs/built-in.a
  CC      net/wireless/nl80211.o
  CC      net/ethtool/fec.o
  CC      kernel/trace/pid_list.o
  CC      crypto/cbc.o
  AR      sound/virtio/built-in.a
  CC      sound/hda/trace.o
  CC      drivers/acpi/proc.o
  CC      net/sunrpc/auth_gss/gss_krb5_crypto.o
  CC      net/sunrpc/auth.o
  CC      kernel/panic.o
  CC      arch/x86/kernel/cpu/perfctr-watchdog.o
  CC      net/handshake/alert.o
  CC      fs/9p/vfs_inode_dotl.o
  CC      net/dns_resolver/dns_query.o
  CC      fs/lockd/mon.o
  CC      net/9p/trans_common.o
  CC      drivers/pci/quirks.o
  CC      drivers/tty/tty_mutex.o
  CC      drivers/acpi/acpica/exserial.o
  CC      block/bsg.o
  CC      block/blk-cgroup.o
  CC      drivers/connector/cn_proc.o
  CC      net/sunrpc/auth_null.o
  CC      crypto/ctr.o
  CC      drivers/pci/pci-label.o
  CC      kernel/time/tick-broadcast-hrtimer.o
  CC      mm/mmap_lock.o
  CC      sound/sound_core.o
  CC      drivers/acpi/acpica/exstore.o
  CC      io_uring/truncate.o
  CC      net/core/utils.o
  CC      fs/debugfs/inode.o
  CC      drivers/gpu/drm/display/drm_scdc_helper.o
  CC      fs/tracefs/inode.o
  CC      net/mac80211/aead_api.o
  CC      arch/x86/kernel/cpu/vmware.o
  CC      net/9p/trans_fd.o
  CC      drivers/gpu/drm/ttm/ttm_pool.o
  CC      kernel/trace/trace_sched_switch.o
  CC [M]  fs/efivarfs/inode.o
  CC      net/netfilter/nf_conntrack_acct.o
  CC      drivers/tty/tty_ldsem.o
  AR      net/dns_resolver/built-in.a
  CC      net/wireless/mlme.o
  CC      kernel/time/tick-oneshot.o
  CC      kernel/events/hw_breakpoint.o
  CC      net/ethtool/eeprom.o
  CC      crypto/gcm.o
  CC      fs/ext4/ioctl.o
  CC      net/sunrpc/auth_gss/gss_krb5_keys.o
  CC      drivers/acpi/acpica/exstoren.o
  CC      sound/hda/hdac_component.o
  CC      kernel/events/uprobes.o
  CC      net/wireless/ibss.o
  CC      fs/9p/vfs_addr.o
  CC      net/handshake/genl.o
  CC      fs/nfs/super.o
  CC      fs/tracefs/event_inode.o
  CC      net/netlabel/netlabel_cipso_v4.o
  CC      fs/lockd/trace.o
  CC      kernel/time/tick-sched.o
  CC      mm/highmem.o
  CC      net/netlabel/netlabel_calipso.o
  CC      net/mac80211/wpa.o
  CC      fs/nfs/io.o
  CC      drivers/acpi/acpica/exstorob.o
  CC      net/ipv4/ip_sockglue.o
  CC      arch/x86/kernel/cpu/hypervisor.o
  AR      drivers/connector/built-in.a
  CC [M]  fs/efivarfs/file.o
  CC      net/9p/trans_virtio.o
  CC      net/ipv6/route.o
  CC      io_uring/memmap.o
  CC [M]  fs/efivarfs/super.o
  CC      drivers/tty/tty_baudrate.o
  AR      drivers/gpu/drm/display/built-in.a
  CC      kernel/cpu.o
  CC      kernel/trace/trace_nop.o
  CC      fs/debugfs/file.o
  CC      arch/x86/kernel/cpu/mshyperv.o
  CC      net/wireless/sme.o
  CC      sound/hda/hdac_i915.o
  CC      drivers/acpi/acpica/exsystem.o
  CC      block/blk-ioprio.o
  CC      drivers/gpu/drm/ttm/ttm_device.o
  CC      drivers/pci/vgaarb.o
  CC      net/netfilter/nf_conntrack_seqadj.o
  CC      fs/9p/vfs_file.o
  CC      crypto/ccm.o
  CC      net/mac80211/scan.o
  CC      net/handshake/netlink.o
  CC      net/ethtool/stats.o
  CC      lib/memcat_p.o
  CC      block/blk-iolatency.o
  CC      net/ethtool/phc_vclocks.o
  CC      drivers/tty/tty_jobctrl.o
  CC      drivers/base/power/sysfs.o
  CC      drivers/base/power/generic_ops.o
  AR      net/sunrpc/auth_gss/built-in.a
  CC      net/sunrpc/auth_tls.o
  AR      fs/tracefs/built-in.a
  CC      net/sunrpc/auth_unix.o
  CC      drivers/acpi/acpica/extrace.o
  CC      io_uring/alloc_cache.o
  CC      net/sunrpc/svc.o
  CC      net/ipv4/inet_hashtables.o
  CC      mm/memory.o
  CC [M]  fs/efivarfs/vars.o
  CC      kernel/time/timer_migration.o
  CC      kernel/trace/blktrace.o
  CC      sound/hda/intel-dsp-config.o
  CC      net/ethtool/mm.o
  CC      fs/lockd/xdr.o
  CC      net/ipv6/ip6_fib.o
  AR      net/netlabel/built-in.a
  CC      drivers/acpi/acpica/exutils.o
  CC      net/core/link_watch.o
  CC      fs/ext4/mballoc.o
  CC      net/core/filter.o
  CC      drivers/gpu/drm/ttm/ttm_sys_manager.o
  CC      arch/x86/kernel/cpu/debugfs.o
  CC      drivers/base/power/common.o
  CC      fs/nfs/direct.o
  CC      fs/9p/vfs_dir.o
  CC      drivers/tty/n_null.o
  AR      net/9p/built-in.a
  AR      kernel/events/built-in.a
  CC      fs/9p/vfs_dentry.o
  AR      fs/debugfs/built-in.a
  CC      net/core/sock_diag.o
  CC      io_uring/io-wq.o
  CC      fs/nfs/pagelist.o
  CC      sound/last.o
  CC      crypto/aes_generic.o
  CC      drivers/acpi/acpica/hwacpi.o
  CC      kernel/time/vsyscall.o
  AR      drivers/pci/built-in.a
  CC      arch/x86/kernel/cpu/bus_lock.o
  CC      net/sunrpc/svcsock.o
  CC      fs/lockd/clnt4xdr.o
  CC      net/handshake/request.o
  CC      mm/mincore.o
  CC      drivers/gpu/drm/ttm/ttm_agp_backend.o
  LD [M]  fs/efivarfs/efivarfs.o
  CC      drivers/acpi/acpica/hwesleep.o
  CC      sound/hda/intel-nhlt.o
  CC      net/netfilter/nf_conntrack_proto_icmpv6.o
  CC      drivers/acpi/bus.o
  CC      arch/x86/kernel/time.o
  CC      crypto/authenc.o
  CC      drivers/base/power/qos.o
  CC      net/handshake/tlshd.o
  CC      arch/x86/kernel/ioport.o
  CC      fs/9p/v9fs.o
  CC      drivers/tty/pty.o
  CC      net/wireless/chan.o
  CC      block/blk-iocost.o
  CC      sound/hda/intel-sdw-acpi.o
  CC      net/devres.o
  CC      drivers/block/loop.o
  CC      drivers/misc/eeprom/eeprom_93cx6.o
  CC      net/ethtool/module.o
  CC      drivers/block/virtio_blk.o
  AR      drivers/misc/cb710/built-in.a
  CC      drivers/acpi/acpica/hwgpe.o
  CC      kernel/trace/trace_events.o
  CC      fs/lockd/xdr4.o
  AR      drivers/mfd/built-in.a
  CC      net/ethtool/cmis_fw_update.o
  CC      net/mac80211/offchannel.o
  CC      net/mac80211/ht.o
  CC      fs/9p/fid.o
  CC      fs/open.o
  AR      drivers/gpu/drm/ttm/built-in.a
make[4]: *** [/workspace/kernel/scripts/Makefile.build:465: drivers/gpu/drm] Error 2
make[3]: *** [/workspace/kernel/scripts/Makefile.build:465: drivers/gpu] Error 2
make[3]: *** Waiting for unfinished jobs....
  CC      kernel/time/timekeeping_debug.o
  CC      arch/x86/kernel/cpu/capflags.o
  AR      arch/x86/kernel/cpu/built-in.a
  AR      sound/hda/built-in.a
  CC      drivers/base/power/runtime.o
  AR      sound/built-in.a
  CC      drivers/tty/tty_audit.o
  AR      drivers/misc/eeprom/built-in.a
  CC      drivers/acpi/glue.o
  AR      drivers/misc/lis3lv02d/built-in.a
  AR      drivers/misc/cardreader/built-in.a
  CC      drivers/acpi/acpica/hwregs.o
  AR      drivers/misc/keba/built-in.a
  CC      kernel/exit.o
  AR      drivers/misc/built-in.a
  CC      drivers/tty/sysrq.o
  CC      fs/read_write.o
  CC      net/netfilter/nf_conntrack_netlink.o
  CC      arch/x86/kernel/dumpstack.o
  CC      net/ipv4/inet_timewait_sock.o
  CC      net/core/dev_ioctl.o
  CC      crypto/authencesn.o
  CC      io_uring/futex.o
  CC      fs/9p/xattr.o
  CC      net/ipv4/inet_connection_sock.o
  CC      drivers/base/firmware_loader/builtin/main.o
  CC      net/ipv4/tcp.o
  CC      drivers/base/firmware_loader/main.o
  CC      kernel/softirq.o
  CC      net/mac80211/agg-tx.o
  CC      net/handshake/trace.o
  CC      drivers/acpi/acpica/hwsleep.o
  CC      kernel/time/namespace.o
  CC      fs/nfs/read.o
  CC      kernel/trace/trace_export.o
  CC      mm/mlock.o
  CC      drivers/base/regmap/regmap.o
  AR      drivers/base/firmware_loader/builtin/built-in.a
  CC      arch/x86/kernel/nmi.o
  CC      fs/ext4/migrate.o
  CC      drivers/acpi/scan.o
  CC      net/core/tso.o
  CC      lib/nmi_backtrace.o
  CC      net/core/sock_reuseport.o
  CC      kernel/trace/trace_event_perf.o
  CC      fs/file_table.o
  CC      fs/lockd/svc4proc.o
  CC      drivers/base/power/wakeirq.o
  CC      drivers/acpi/acpica/hwvalid.o
  CC      net/ethtool/cmis_cdb.o
  AR      drivers/base/test/built-in.a
  CC      net/ipv4/tcp_input.o
  AR      fs/9p/built-in.a
  AR      drivers/block/built-in.a
  CC      drivers/base/regmap/regcache.o
  CC      lib/objpool.o
  CC      net/ipv4/tcp_output.o
  CC      block/mq-deadline.o
  AR      drivers/tty/built-in.a
  CC      net/core/fib_notifier.o
  CC      io_uring/napi.o
  CC      crypto/lzo.o
  CC      drivers/acpi/acpica/hwxface.o
  AR      kernel/time/built-in.a
  CC      net/mac80211/agg-rx.o
  CC      net/ipv6/ipv6_sockglue.o
  CC      drivers/acpi/mipi-disco-img.o
  AR      drivers/base/firmware_loader/built-in.a
  CC      block/kyber-iosched.o
  CC      block/blk-mq-debugfs.o
  CC      drivers/base/power/main.o
  CC      net/netfilter/nf_conntrack_ftp.o
  CC      net/wireless/ethtool.o
  CC      lib/plist.o
  CC      lib/radix-tree.o
  CC      arch/x86/kernel/ldt.o
  CC      net/sunrpc/svcauth.o
  CC      fs/nfs/symlink.o
  CC      kernel/trace/trace_events_filter.o
  CC      drivers/acpi/acpica/hwxfsleep.o
  CC      fs/super.o
  CC      drivers/acpi/resource.o
  CC      mm/mmap.o
  CC      net/mac80211/vht.o
  CC      drivers/base/power/wakeup.o
  CC      drivers/base/regmap/regcache-rbtree.o
  CC      crypto/lzo-rle.o
  CC      net/ethtool/pse-pd.o
  CC      fs/lockd/procfs.o
  CC      net/netfilter/nf_conntrack_irc.o
  CC      net/ipv6/ndisc.o
  AR      net/handshake/built-in.a
  CC      drivers/acpi/acpica/hwpci.o
  CC      net/mac80211/he.o
  CC      net/netfilter/nf_conntrack_sip.o
  CC      net/ethtool/plca.o
  CC      drivers/acpi/acpica/nsaccess.o
  CC      crypto/rng.o
  CC      block/blk-pm.o
  CC      fs/ext4/mmp.o
  CC      lib/ratelimit.o
  CC      fs/char_dev.o
  CC      drivers/base/power/wakeup_stats.o
  CC      drivers/base/component.o
  CC      fs/stat.o
  CC      crypto/drbg.o
  CC      net/mac80211/s1g.o
  CC      drivers/base/regmap/regcache-flat.o
  CC      kernel/resource.o
  CC      drivers/base/power/trace.o
  CC      net/core/xdp.o
  CC      drivers/acpi/acpica/nsalloc.o
  CC      drivers/base/core.o
  CC      arch/x86/kernel/setup.o
  CC      lib/rbtree.o
  CC      mm/mmu_gather.o
  CC      net/ethtool/phy.o
  CC      net/ethtool/tsconfig.o
  AR      fs/lockd/built-in.a
  CC      kernel/trace/trace_events_trigger.o
  CC      net/socket.o
  AR      io_uring/built-in.a
  CC      lib/seq_buf.o
  CC      drivers/acpi/acpica/nsarguments.o
  CC      fs/nfs/unlink.o
  CC      kernel/sysctl.o
  CC      net/ipv4/tcp_timer.o
  CC      block/holder.o
  CC      drivers/base/regmap/regcache-maple.o
  CC      drivers/base/bus.o
  CC      mm/mprotect.o
  CC      kernel/trace/trace_eprobe.o
  CC      fs/ext4/move_extent.o
  CC      net/netfilter/nf_nat_core.o
  CC      net/ipv4/tcp_ipv4.o
  CC      drivers/base/dd.o
  CC      net/core/flow_offload.o
  CC      net/sunrpc/svcauth_unix.o
  CC      drivers/acpi/acpica/nsconvert.o
  CC      net/netfilter/nf_nat_proto.o
  CC      net/wireless/mesh.o
  AR      drivers/base/power/built-in.a
  CC      drivers/acpi/acpi_processor.o
  CC      net/sysctl_net.o
  CC      crypto/jitterentropy.o
  CC      net/netfilter/nf_nat_helper.o
  CC      net/netfilter/nf_nat_masquerade.o
  CC      crypto/jitterentropy-kcapi.o
  CC      net/core/gro.o
  CC      lib/siphash.o
  CC      net/ipv4/tcp_minisocks.o
  CC      kernel/capability.o
  CC      arch/x86/kernel/x86_init.o
  CC      drivers/acpi/acpica/nsdump.o
  CC      fs/exec.o
  CC      drivers/base/regmap/regmap-debugfs.o
  CC      net/ipv6/udp.o
  AR      block/built-in.a
  CC      net/netfilter/nf_nat_ftp.o
  CC      drivers/base/syscore.o
  CC      crypto/ghash-generic.o
  CC      net/core/netdev-genl.o
  CC      net/ipv4/tcp_cong.o
  CC      lib/string.o
  AR      net/ethtool/built-in.a
  CC      fs/ext4/namei.o
  CC      kernel/ptrace.o
  CC      fs/nfs/write.o
  CC      drivers/acpi/acpica/nseval.o
  CC      net/mac80211/ibss.o
  CC      drivers/acpi/processor_core.o
  CC      net/ipv6/udplite.o
  CC      net/mac80211/iface.o
  CC      lib/timerqueue.o
  CC      drivers/acpi/processor_pdc.o
  CC      crypto/hash_info.o
  CC      net/sunrpc/addr.o
  CC      drivers/acpi/acpica/nsinit.o
  CC      mm/mremap.o
  CC      crypto/rsapubkey.asn1.o
  CC      crypto/rsaprivkey.asn1.o
  CC      fs/pipe.o
  AR      crypto/built-in.a
  CC      net/ipv4/tcp_metrics.o
  CC      drivers/acpi/ec.o
  CC      lib/union_find.o
  CC      arch/x86/kernel/i8259.o
  CC      mm/msync.o
  CC      lib/vsprintf.o
  CC      fs/namei.o
  CC      kernel/trace/trace_kprobe.o
  CC      net/core/netdev-genl-gen.o
  CC      net/ipv6/raw.o
  CC      fs/fcntl.o
  AR      drivers/base/regmap/built-in.a
  CC      drivers/acpi/dock.o
  CC      net/ipv4/tcp_fastopen.o
  CC      fs/nfs/namespace.o
  CC      net/netfilter/nf_nat_irc.o
  CC      fs/ext4/page-io.o
  CC      arch/x86/kernel/irqinit.o
  CC      drivers/acpi/acpica/nsload.o
  CC      net/netfilter/nf_nat_sip.o
  CC      drivers/base/driver.o
  CC      net/core/gso.o
  CC      net/mac80211/link.o
  CC      net/wireless/ap.o
  CC      fs/nfs/mount_clnt.o
  CC      drivers/acpi/acpica/nsnames.o
  CC      net/sunrpc/rpcb_clnt.o
  CC      drivers/acpi/pci_root.o
  CC      mm/page_vma_mapped.o
  CC      drivers/base/class.o
  CC      kernel/trace/error_report-traces.o
  CC      kernel/user.o
  CC      net/ipv6/icmp.o
  CC      net/netfilter/x_tables.o
  CC      fs/nfs/nfstrace.o
  CC      fs/ioctl.o
  CC      net/mac80211/rate.o
  CC      drivers/acpi/acpica/nsobject.o
  CC      arch/x86/kernel/jump_label.o
  CC      fs/ext4/readpage.o
  CC      fs/readdir.o
  CC      net/ipv4/tcp_rate.o
  CC      net/wireless/trace.o
  CC      kernel/trace/power-traces.o
  CC      fs/nfs/export.o
  CC      net/ipv6/mcast.o
  CC      net/mac80211/michael.o
  CC      drivers/acpi/pci_link.o
  CC      arch/x86/kernel/irq_work.o
  CC      net/sunrpc/timer.o
  CC      drivers/base/platform.o
  CC      drivers/acpi/acpica/nsparse.o
  CC      lib/win_minmax.o
  CC      mm/pagewalk.o
  CC      net/ipv4/tcp_recovery.o
  CC      net/mac80211/tkip.o
  CC      fs/nfs/sysfs.o
  CC      mm/pgtable-generic.o
  CC      net/netfilter/xt_tcpudp.o
  CC      arch/x86/kernel/probe_roms.o
  CC      net/sunrpc/xdr.o
  CC      fs/ext4/resize.o
  CC      fs/nfs/fs_context.o
  CC      drivers/acpi/acpica/nspredef.o
  CC      net/mac80211/aes_cmac.o
  CC      kernel/signal.o
  CC      fs/select.o
  CC      drivers/acpi/pci_irq.o
  CC      net/core/net-sysfs.o
  CC      net/ipv6/reassembly.o
  CC      arch/x86/kernel/sys_ia32.o
  CC      net/wireless/ocb.o
  CC      net/sunrpc/sunrpc_syms.o
  CC      net/ipv4/tcp_ulp.o
  CC      drivers/acpi/acpica/nsprepkg.o
  CC      net/ipv6/tcp_ipv6.o
  CC      lib/xarray.o
  CC      net/mac80211/aes_gmac.o
  CC      mm/rmap.o
  CC      kernel/sys.o
  CC      net/core/hotdata.o
  CC      net/wireless/pmsr.o
  CC      net/sunrpc/cache.o
  CC      fs/ext4/super.o
  CC      drivers/base/cpu.o
  CC      net/core/netdev_rx_queue.o
  CC      drivers/acpi/acpi_apd.o
  CC      fs/dcache.o
  CC      net/ipv6/ping.o
  CC      kernel/trace/rpm-traces.o
  CC      drivers/acpi/acpi_platform.o
  CC      kernel/umh.o
  CC      net/ipv6/exthdrs.o
  CC      drivers/acpi/acpica/nsrepair.o
  CC      kernel/trace/trace_dynevent.o
  CC      net/ipv6/datagram.o
  CC      drivers/base/firmware.o
  CC      lib/lockref.o
  CC      drivers/acpi/acpi_pnp.o
  CC      arch/x86/kernel/ksysfs.o
  CC      drivers/acpi/acpica/nsrepair2.o
  CC      drivers/acpi/acpica/nssearch.o
  CC      net/ipv6/ip6_flowlabel.o
  CC      lib/bcd.o
  CC      arch/x86/kernel/bootflag.o
  CC      fs/inode.o
  CC      kernel/trace/trace_probe.o
  CC      fs/ext4/symlink.o
  CC      net/netfilter/xt_CONNSECMARK.o
  CC      net/ipv6/inet6_connection_sock.o
  CC      arch/x86/kernel/e820.o
  GEN     net/wireless/shipped-certs.c
  CC      net/mac80211/fils_aead.o
  CC      kernel/workqueue.o
  CC      net/ipv4/tcp_offload.o
  CC      mm/vmalloc.o
  CC      drivers/acpi/power.o
  CC      drivers/base/init.o
  CC      drivers/acpi/acpica/nsutils.o
  CC      mm/vma.o
  CC      fs/attr.o
  CC      arch/x86/kernel/pci-dma.o
  CC      net/ipv6/udp_offload.o
  CC      net/mac80211/cfg.o
  CC      kernel/pid.o
  CC      net/sunrpc/rpc_pipe.o
  CC      net/netfilter/xt_NFLOG.o
  CC      fs/bad_inode.o
  CC      net/core/net-procfs.o
  CC      mm/process_vm_access.o
  CC      lib/sort.o
  CC      net/core/netpoll.o
  CC      net/mac80211/ethtool.o
  CC      drivers/acpi/event.o
  CC      lib/parser.o
  CC      net/ipv4/tcp_plb.o
  CC      kernel/trace/trace_uprobe.o
  CC      drivers/acpi/acpica/nswalk.o
  CC      drivers/acpi/evged.o
  CC      lib/debug_locks.o
  CC      drivers/base/map.o
  CC      drivers/acpi/sysfs.o
  CC      net/ipv6/seg6.o
  CC      kernel/task_work.o
  CC      net/sunrpc/sysfs.o
  CC      net/netfilter/xt_SECMARK.o
  CC      kernel/trace/rethook.o
  CC      lib/random32.o
  CC      fs/nfs/nfsroot.o
  CC      mm/page_alloc.o
  CC      net/ipv4/datagram.o
  CC      drivers/acpi/acpica/nsxfeval.o
  CC      net/ipv6/fib6_notifier.o
  CC      net/core/fib_rules.o
  CC      kernel/extable.o
  CC      net/mac80211/rx.o
  CC      fs/file.o
  CC      net/sunrpc/svc_xprt.o
  CC      arch/x86/kernel/quirks.o
  CC      drivers/base/devres.o
  CC      mm/page_frag_cache.o
  CC      fs/nfs/sysctl.o
  CC      net/netfilter/xt_TCPMSS.o
  CC      net/ipv4/raw.o
  CC      fs/filesystems.o
  CC      fs/nfs/nfs3super.o
  CC      lib/bust_spinlocks.o
  CC      net/wireless/shipped-certs.o
  CC      net/core/net-traces.o
  CC      drivers/base/attribute_container.o
  CC      net/mac80211/spectmgmt.o
  CC      drivers/acpi/acpica/nsxfname.o
  CC      net/ipv4/udp.o
  CC      fs/namespace.o
  CC      net/ipv4/udplite.o
  CC      lib/kasprintf.o
  CC      fs/ext4/sysfs.o
  CC      fs/ext4/xattr.o
  CC      fs/nfs/nfs3client.o
  CC      net/sunrpc/xprtmultipath.o
  CC      net/mac80211/tx.o
  CC      drivers/acpi/acpica/nsxfobj.o
  CC      drivers/base/transport_class.o
  CC      net/ipv6/rpl.o
  CC      net/core/selftests.o
  CC      net/core/ptp_classifier.o
  CC      lib/bitmap.o
  CC      net/core/netprio_cgroup.o
  CC      arch/x86/kernel/kdebugfs.o
  CC      lib/scatterlist.o
  CC      net/mac80211/key.o
  CC      net/sunrpc/stats.o
  CC      net/netfilter/xt_conntrack.o
  CC      fs/ext4/xattr_hurd.o
  CC      kernel/params.o
  CC      mm/init-mm.o
  CC      net/sunrpc/sysctl.o
  CC      net/ipv4/udp_offload.o
  CC      drivers/acpi/acpica/psargs.o
  CC      fs/ext4/xattr_trusted.o
  CC      lib/list_sort.o
  CC      arch/x86/kernel/alternative.o
  CC      arch/x86/kernel/i8253.o
  CC      drivers/base/topology.o
  CC      net/mac80211/util.o
  CC      drivers/acpi/property.o
  CC      fs/seq_file.o
  CC      arch/x86/kernel/hw_breakpoint.o
  CC      net/ipv6/ioam6.o
  CC      mm/memblock.o
  AR      kernel/trace/built-in.a
  CC      net/netfilter/xt_policy.o
  CC      drivers/base/container.o
  CC      arch/x86/kernel/tsc.o
  CC      net/core/netclassid_cgroup.o
  CC      drivers/acpi/acpica/psloop.o
  CC      drivers/acpi/debugfs.o
  CC      fs/nfs/nfs3proc.o
  CC      fs/xattr.o
  CC      fs/ext4/xattr_user.o
  CC      net/core/dst_cache.o
  CC      fs/nfs/nfs3xdr.o
  CC      fs/libfs.o
  CC      net/core/gro_cells.o
  CC      lib/uuid.o
  CC      net/ipv4/arp.o
  CC      drivers/acpi/acpica/psobject.o
  CC      kernel/kthread.o
  CC      drivers/base/property.o
  CC      fs/nfs/nfs3acl.o
  CC      drivers/acpi/acpica/psopcode.o
  CC      net/netfilter/xt_state.o
  CC      net/mac80211/parse.o
  CC      fs/fs-writeback.o
  CC      drivers/acpi/acpi_lpat.o
  CC      mm/slub.o
  CC      lib/iov_iter.o
  CC      net/ipv4/icmp.o
  CC      drivers/base/cacheinfo.o
  CC      fs/nfs/nfs4proc.o
  CC      net/mac80211/wme.o
  CC      drivers/acpi/acpica/psopinfo.o
  CC      drivers/acpi/acpica/psparse.o
  CC      fs/pnode.o
  CC      drivers/acpi/acpica/psscope.o
  CC      mm/madvise.o
  CC      net/ipv4/devinet.o
  CC      kernel/sys_ni.o
  CC [M]  net/netfilter/nf_log_syslog.o
  CC      net/ipv6/sysctl_net_ipv6.o
  CC      fs/nfs/nfs4xdr.o
  CC      drivers/acpi/acpi_pcc.o
  CC      lib/clz_ctz.o
  CC      drivers/acpi/acpica/pstree.o
  CC      fs/nfs/nfs4state.o
  CC      fs/splice.o
  CC      net/ipv6/xfrm6_policy.o
  CC      arch/x86/kernel/tsc_msr.o
  CC      drivers/base/swnode.o
  CC      net/ipv6/xfrm6_state.o
  AR      net/sunrpc/built-in.a
  CC      net/core/failover.o
  CC      arch/x86/kernel/io_delay.o
  CC      fs/sync.o
  CC      drivers/acpi/ac.o
  CC      fs/ext4/fast_commit.o
  CC      fs/ext4/orphan.o
  CC      net/ipv4/af_inet.o
  CC      drivers/acpi/acpica/psutils.o
  CC      drivers/acpi/acpica/pswalk.o
  CC [M]  net/netfilter/xt_mark.o
  CC      kernel/nsproxy.o
  CC      drivers/acpi/button.o
  CC [M]  net/netfilter/xt_nat.o
  CC      lib/bsearch.o
  CC      net/ipv4/igmp.o
  CC      drivers/base/auxiliary.o
  CC      drivers/acpi/acpica/psxface.o
  CC      arch/x86/kernel/rtc.o
  CC      mm/page_io.o
  CC      fs/ext4/acl.o
  CC      fs/utimes.o
  CC      drivers/acpi/fan_core.o
  CC      net/ipv4/fib_frontend.o
  CC [M]  net/netfilter/xt_LOG.o
  CC      arch/x86/kernel/resource.o
  CC [M]  net/netfilter/xt_MASQUERADE.o
  CC      drivers/acpi/acpica/rsaddr.o
  CC      fs/nfs/nfs4renewd.o
  CC      kernel/notifier.o
  CC      fs/d_path.o
  CC      lib/find_bit.o
  CC      fs/nfs/nfs4super.o
  CC      drivers/base/devtmpfs.o
  CC      fs/stack.o
  CC      mm/swap_state.o
  CC      drivers/acpi/fan_attr.o
  CC      drivers/acpi/acpica/rscalc.o
  CC      kernel/ksysfs.o
  AS      arch/x86/kernel/irqflags.o
  CC      fs/ext4/xattr_security.o
  CC      arch/x86/kernel/static_call.o
  CC      net/mac80211/chan.o
  CC      net/ipv6/xfrm6_input.o
  CC      lib/llist.o
  CC [M]  net/netfilter/xt_addrtype.o
  CC      net/ipv4/fib_semantics.o
  CC      drivers/base/module.o
  CC      drivers/acpi/fan_hwmon.o
  CC      arch/x86/kernel/process.o
  CC      mm/swapfile.o
  CC      net/ipv6/xfrm6_output.o
  CC      net/ipv6/xfrm6_protocol.o
  CC      net/mac80211/trace.o
  CC      drivers/base/auxiliary_sysfs.o
  CC      fs/nfs/nfs4file.o
  CC      drivers/acpi/acpica/rscreate.o
  CC      lib/lwq.o
  CC      arch/x86/kernel/ptrace.o
  CC      net/ipv4/fib_trie.o
  CC      net/ipv6/netfilter.o
  CC      drivers/base/devcoredump.o
  CC      fs/nfs/delegation.o
  CC      mm/swap_slots.o
  CC      drivers/base/platform-msi.o
  CC      net/mac80211/mlme.o
  CC      lib/memweight.o
  CC      drivers/acpi/acpi_video.o
  CC      drivers/acpi/acpica/rsdumpinfo.o
  CC      arch/x86/kernel/tls.o
  CC      kernel/cred.o
  CC      net/ipv6/proc.o
  CC      fs/nfs/nfs4idmap.o
  CC      lib/kfifo.o
  CC      net/ipv4/fib_notifier.o
  AR      net/core/built-in.a
  CC      arch/x86/kernel/step.o
  CC      net/ipv4/inet_fragment.o
  CC      mm/dmapool.o
  CC      net/mac80211/tdls.o
  CC      arch/x86/kernel/i8237.o
  CC      fs/fs_struct.o
  CC      fs/statfs.o
  CC      mm/hugetlb.o
  CC      drivers/acpi/video_detect.o
  CC      drivers/acpi/acpica/rsinfo.o
  CC      kernel/reboot.o
  CC      net/ipv4/ping.o
  CC      drivers/base/physical_location.o
  CC      lib/percpu-refcount.o
  CC      kernel/async.o
  CC      arch/x86/kernel/stacktrace.o
  CC      net/mac80211/ocb.o
  CC      fs/fs_pin.o
  CC      drivers/acpi/acpica/rsio.o
  CC      drivers/acpi/processor_driver.o
  AR      net/netfilter/built-in.a
  CC      drivers/base/trace.o
  CC      net/ipv4/ip_tunnel_core.o
  CC      fs/nfs/callback.o
  CC      arch/x86/kernel/reboot.o
  CC      kernel/range.o
  CC      net/ipv4/gre_offload.o
  CC      lib/rhashtable.o
  CC      lib/base64.o
  CC      drivers/acpi/processor_thermal.o
  CC      drivers/acpi/acpica/rsirq.o
  CC      net/mac80211/airtime.o
  CC      fs/nsfs.o
  CC      fs/nfs/callback_xdr.o
  CC      mm/mmu_notifier.o
  CC      drivers/acpi/acpica/rslist.o
  CC      net/ipv6/syncookies.o
  CC      net/ipv4/metrics.o
  CC      arch/x86/kernel/msr.o
  CC      net/ipv4/netlink.o
  CC      kernel/smpboot.o
  CC      net/mac80211/eht.o
  CC      fs/nfs/callback_proc.o
  CC      net/mac80211/led.o
  CC      mm/migrate.o
  CC      lib/once.o
  CC      arch/x86/kernel/cpuid.o
  CC      drivers/acpi/acpica/rsmemory.o
  CC      drivers/acpi/processor_idle.o
  CC      mm/page_counter.o
  CC      net/ipv6/calipso.o
  CC      net/ipv4/nexthop.o
  CC      net/ipv4/udp_tunnel_stub.o
  CC      net/ipv6/ah6.o
  CC      fs/nfs/nfs4namespace.o
  CC      fs/fs_types.o
  CC      arch/x86/kernel/early-quirks.o
  CC      lib/refcount.o
  CC      net/mac80211/pm.o
  AR      drivers/base/built-in.a
  CC      drivers/acpi/acpica/rsmisc.o
  CC      net/ipv6/esp6.o
  CC      lib/rcuref.o
  CC      net/ipv4/ip_tunnel.o
  CC      kernel/ucount.o
  CC      fs/nfs/nfs4getroot.o
  CC      fs/fs_context.o
  CC      lib/usercopy.o
  CC      drivers/acpi/processor_throttling.o
  CC      mm/hugetlb_cgroup.o
  CC      fs/fs_parser.o
  CC      arch/x86/kernel/smp.o
  CC      net/ipv6/sit.o
  CC      arch/x86/kernel/smpboot.o
  CC      fs/fsopen.o
  CC      fs/init.o
  CC      arch/x86/kernel/tsc_sync.o
  AR      fs/ext4/built-in.a
  CC      lib/errseq.o
  CC      net/ipv4/sysctl_net_ipv4.o
  CC      kernel/regset.o
  CC      mm/early_ioremap.o
  CC      net/mac80211/rc80211_minstrel_ht.o
  CC      net/ipv6/addrconf_core.o
  CC      drivers/acpi/acpica/rsserial.o
  CC      mm/secretmem.o
  CC      lib/bucket_locks.o
  CC      kernel/ksyms_common.o
  CC      fs/nfs/nfs4client.o
  CC      net/ipv4/proc.o
  CC      arch/x86/kernel/setup_percpu.o
  CC      net/ipv4/fib_rules.o
  CC      net/ipv4/ipmr.o
  CC      net/ipv4/ipmr_base.o
  CC      drivers/acpi/processor_perflib.o
  CC      net/mac80211/wbrf.o
  CC      kernel/groups.o
  CC      fs/nfs/nfs4session.o
  CC      net/ipv4/syncookies.o
  CC      drivers/acpi/container.o
  CC      fs/kernel_read_file.o
  CC      drivers/acpi/acpica/rsutils.o
  CC      kernel/kcmp.o
  CC      lib/generic-radix-tree.o
  CC      mm/hmm.o
  CC      net/ipv6/exthdrs_core.o
  CC      fs/nfs/dns_resolve.o
  CC      net/ipv4/tunnel4.o
  CC      arch/x86/kernel/mpparse.o
  CC      lib/bitmap-str.o
  CC      net/ipv6/ip6_checksum.o
  CC      drivers/acpi/acpica/rsxface.o
  CC      lib/string_helpers.o
  CC      mm/memfd.o
  CC      kernel/freezer.o
  CC      drivers/acpi/thermal_lib.o
  CC      fs/mnt_idmapping.o
  CC      kernel/profile.o
  CC      net/ipv6/ip6_icmp.o
  CC      net/ipv4/ipconfig.o
  CC      drivers/acpi/acpica/tbdata.o
  CC      lib/hexdump.o
  CC      kernel/stacktrace.o
  CC      drivers/acpi/thermal.o
  CC      kernel/dma.o
  CC      fs/remap_range.o
  CC      net/ipv4/netfilter.o
  CC      fs/nfs/nfs4trace.o
  AR      net/wireless/built-in.a
  CC      fs/nfs/nfs4sysctl.o
  CC      net/ipv6/output_core.o
  CC      lib/kstrtox.o
  CC      mm/ptdump.o
  CC      arch/x86/kernel/trace_clock.o
  CC      drivers/acpi/nhlt.o
  CC      kernel/smp.o
  CC      net/ipv6/protocol.o
  CC      net/ipv4/tcp_cubic.o
  CC      lib/iomap.o
  CC      mm/execmem.o
  CC      drivers/acpi/acpi_memhotplug.o
  CC      lib/iomap_copy.o
  CC      drivers/acpi/acpica/tbfadt.o
  CC      net/ipv6/ip6_offload.o
  CC      arch/x86/kernel/trace.o
  CC      kernel/uid16.o
  CC      net/ipv4/tcp_sigpool.o
  CC      lib/devres.o
  CC      net/ipv6/tcpv6_offload.o
  CC      net/ipv6/exthdrs_offload.o
  CC      net/ipv6/inet6_hashtables.o
  CC      kernel/kallsyms.o
  CC      lib/check_signature.o
  CC      net/ipv6/mcast_snoop.o
  CC      kernel/acct.o
  CC      drivers/acpi/acpica/tbfind.o
  CC      arch/x86/kernel/rethook.o
  CC      lib/interval_tree.o
  CC      fs/pidfs.o
  CC      net/ipv4/cipso_ipv4.o
  CC      kernel/vmcore_info.o
  CC      drivers/acpi/acpica/tbinstal.o
  CC      arch/x86/kernel/vmcore_info_32.o
  CC      fs/buffer.o
  CC      drivers/acpi/acpica/tbprint.o
  CC      fs/mpage.o
  CC      kernel/elfcorehdr.o
  CC      net/ipv4/xfrm4_policy.o
  CC      drivers/acpi/acpica/tbutils.o
  CC      drivers/acpi/ioapic.o
  CC      arch/x86/kernel/machine_kexec_32.o
  CC      kernel/crash_reserve.o
  CC      drivers/acpi/acpica/tbxface.o
  CC      fs/proc_namespace.o
  AS      arch/x86/kernel/relocate_kernel_32.o
  CC      drivers/acpi/battery.o
  CC      kernel/kexec_core.o
  CC      drivers/acpi/bgrt.o
  CC      lib/assoc_array.o
  CC      lib/bitrev.o
  CC      drivers/acpi/acpica/tbxfload.o
  CC      fs/direct-io.o
  CC      kernel/crash_core.o
  AR      mm/built-in.a
  CC      kernel/kexec.o
  CC      lib/crc-ccitt.o
  CC      fs/eventpoll.o
  CC      lib/crc16.o
  CC      arch/x86/kernel/crash_dump_32.o
  CC      drivers/acpi/acpica/tbxfroot.o
  CC      kernel/utsname.o
  CC      fs/anon_inodes.o
  CC      drivers/acpi/spcr.o
  HOSTCC  lib/gen_crc32table
  CC      net/ipv4/xfrm4_state.o
  CC      drivers/acpi/acpica/utaddress.o
  CC      lib/xxhash.o
  CC      kernel/pid_namespace.o
  CC      fs/signalfd.o
  CC      lib/genalloc.o
  CC      kernel/stop_machine.o
  CC      drivers/acpi/acpica/utalloc.o
  CC      net/ipv4/xfrm4_input.o
  CC      arch/x86/kernel/crash.o
  CC      fs/timerfd.o
  CC      kernel/audit.o
  CC      lib/percpu_counter.o
  CC      kernel/auditfilter.o
  CC      drivers/acpi/acpica/utascii.o
  CC      fs/eventfd.o
  CC      kernel/auditsc.o
  CC      kernel/audit_watch.o
  CC      fs/aio.o
  CC      net/ipv4/xfrm4_output.o
  CC      lib/audit.o
  CC      arch/x86/kernel/module.o
  CC      drivers/acpi/acpica/utbuffer.o
  CC      fs/locks.o
  CC      kernel/audit_fsnotify.o
  CC      lib/syscall.o
  CC      fs/binfmt_misc.o
  CC      kernel/audit_tree.o
  CC      drivers/acpi/acpica/utcksum.o
  CC      net/ipv4/xfrm4_protocol.o
  CC      fs/binfmt_script.o
  CC      lib/errname.o
  CC      kernel/kprobes.o
  CC      arch/x86/kernel/doublefault_32.o
  CC      drivers/acpi/acpica/utcopy.o
  CC      kernel/seccomp.o
  CC      fs/binfmt_elf.o
  CC      lib/nlattr.o
  CC      drivers/acpi/acpica/utexcep.o
  CC      arch/x86/kernel/early_printk.o
  CC      kernel/relay.o
  CC      fs/mbcache.o
  CC      arch/x86/kernel/hpet.o
  CC      drivers/acpi/acpica/utdebug.o
  AR      net/ipv6/built-in.a
  CC      kernel/utsname_sysctl.o
  CC      drivers/acpi/acpica/utdecode.o
  CC      lib/cpu_rmap.o
  CC      kernel/delayacct.o
  CC      fs/posix_acl.o
  CC      arch/x86/kernel/amd_nb.o
  CC      kernel/taskstats.o
  CC      drivers/acpi/acpica/utdelete.o
  CC      fs/coredump.o
  CC      arch/x86/kernel/amd_node.o
  CC      arch/x86/kernel/kvm.o
  CC      lib/dynamic_queue_limits.o
  CC      drivers/acpi/acpica/uterror.o
  CC      lib/glob.o
  CC      drivers/acpi/acpica/uteval.o
  CC      arch/x86/kernel/kvmclock.o
  CC      kernel/tsacct.o
  CC      drivers/acpi/acpica/utglobal.o
  CC      fs/drop_caches.o
  CC      lib/strncpy_from_user.o
  CC      kernel/tracepoint.o
  CC      fs/sysctls.o
  CC      drivers/acpi/acpica/uthex.o
  CC      lib/strnlen_user.o
  CC      lib/net_utils.o
  CC      drivers/acpi/acpica/utids.o
  CC      arch/x86/kernel/paravirt.o
  CC      fs/fhandle.o
  CC      lib/sg_pool.o
  CC      drivers/acpi/acpica/utinit.o
  CC      arch/x86/kernel/pvclock.o
  CC      drivers/acpi/acpica/utlock.o
  CC      kernel/irq_work.o
  CC      lib/stackdepot.o
  CC      kernel/static_call.o
  CC      arch/x86/kernel/pcspeaker.o
  CC      arch/x86/kernel/check.o
  CC      drivers/acpi/acpica/utmath.o
  CC      lib/asn1_decoder.o
  CC      kernel/padata.o
  CC      drivers/acpi/acpica/utmisc.o
  CC      kernel/jump_label.o
  CC      arch/x86/kernel/uprobes.o
  GEN     lib/oid_registry_data.c
  CC      drivers/acpi/acpica/utmutex.o
  CC      lib/ucs2_string.o
  CC      drivers/acpi/acpica/utnonansi.o
  CC      kernel/context_tracking.o
  AR      net/ipv4/built-in.a
  CC      arch/x86/kernel/perf_regs.o
  CC      lib/sbitmap.o
  CC      drivers/acpi/acpica/utobject.o
  CC      kernel/iomem.o
  CC      drivers/acpi/acpica/utosi.o
  CC      arch/x86/kernel/tracepoint.o
  CC      arch/x86/kernel/itmt.o
  CC      kernel/rseq.o
  CC      arch/x86/kernel/umip.o
  CC      arch/x86/kernel/unwind_frame.o
  CC      drivers/acpi/acpica/utownerid.o
  CC      lib/group_cpus.o
  CC      drivers/acpi/acpica/utpredef.o
  CC      lib/fw_table.o
  CC      drivers/acpi/acpica/utresdecode.o
  CC      drivers/acpi/acpica/utresrc.o
  AR      lib/lib.a
  GEN     lib/crc32table.h
  CC      lib/oid_registry.o
  CC      lib/crc32.o
  CC      drivers/acpi/acpica/utstate.o
  CC      drivers/acpi/acpica/utstring.o
  CC      drivers/acpi/acpica/utstrsuppt.o
  CC      drivers/acpi/acpica/utstrtoul64.o
  CC      drivers/acpi/acpica/utxface.o
  CC      drivers/acpi/acpica/utxfinit.o
  CC      drivers/acpi/acpica/utxferror.o
  CC      drivers/acpi/acpica/utxfmutex.o
  AR      fs/nfs/built-in.a
  AR      drivers/acpi/acpica/built-in.a
  AR      drivers/acpi/built-in.a
make[2]: *** [/workspace/kernel/scripts/Makefile.build:465: drivers] Error 2
make[2]: *** Waiting for unfinished jobs....
  AR      lib/built-in.a
  AR      arch/x86/kernel/built-in.a
  AR      arch/x86/built-in.a
  AR      fs/built-in.a
  AR      kernel/built-in.a
  AR      net/mac80211/built-in.a
  AR      net/built-in.a
make[1]: *** [/workspace/kernel/Makefile:1994: .] Error 2
make: *** [/workspace/kernel/Makefile:251: __sub-make] Error 2
run-parts: /workspace/ci/hooks/11-build-32b exited with return code 2

✗ CI.checksparse: warning for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2473 bytes --]

== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : success

== Summary ==

CI Bug Log - changes from xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f_BAT -> xe-pw-144587v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-vm 

Known issues
------------

  Here are the changes found in xe-pw-144587v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@xe_exec_basic@twice-bindexecqueue-rebind:
    - bat-adlp-vf:        [PASS][1] -> [DMESG-WARN][2] ([Intel XE#3970])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/bat-adlp-vf/igt@xe_exec_basic@twice-bindexecqueue-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/bat-adlp-vf/igt@xe_exec_basic@twice-bindexecqueue-rebind.html

  * igt@xe_live_ktest@xe_migrate:
    - bat-adlp-vf:        [PASS][3] -> [SKIP][4] ([Intel XE#1192]) +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/bat-adlp-vf/igt@xe_live_ktest@xe_migrate.html

  
#### Warnings ####

  * igt@xe_live_ktest@xe_bo:
    - bat-adlp-vf:        [SKIP][5] ([Intel XE#2229] / [Intel XE#455]) -> [SKIP][6] ([Intel XE#1192])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/bat-adlp-vf/igt@xe_live_ktest@xe_bo.html

  
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455


Build changes
-------------

  * Linux: xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f -> xe-pw-144587v2

  IGT_8228: 8228
  xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f: 27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f
  xe-pw-144587v2: 144587v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/index.html

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✗ Xe.CI.Full: failure for drm_i915_private to intel_display cleanup (rev2)

[Patchwork]

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== Series Details ==

Series: drm_i915_private to intel_display cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/144587/
State : failure

== Summary ==

CI Bug Log - changes from xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f_full -> xe-pw-144587v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-144587v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-144587v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-144587v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane_multiple@tiling-y@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][1] -> [DMESG-WARN][2] +2 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-9/igt@kms_plane_multiple@tiling-y@pipe-a-hdmi-a-1.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-9/igt@kms_plane_multiple@tiling-y@pipe-a-hdmi-a-1.html

  * igt@xe_evict@evict-small-external-cm:
    - shard-dg2-set2:     [PASS][3] -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@xe_evict@evict-small-external-cm.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@xe_evict@evict-small-external-cm.html

  * igt@xe_exec_reset@cm-gt-reset:
    - shard-bmg:          [PASS][5] -> [INCOMPLETE][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-2/igt@xe_exec_reset@cm-gt-reset.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@xe_exec_reset@cm-gt-reset.html
    - shard-dg2-set2:     [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-436/igt@xe_exec_reset@cm-gt-reset.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_exec_reset@cm-gt-reset.html

  
#### Warnings ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-adlp:         [DMESG-WARN][9] ([Intel XE#4173]) -> [INCOMPLETE][10]
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-6/igt@core_hotunplug@unbind-rebind.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-6/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-dg2-set2:     [SKIP][11] ([Intel XE#316]) -> [SKIP][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-set2:     [SKIP][13] ([Intel XE#308]) -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     [SKIP][15] ([Intel XE#653]) -> [SKIP][16]
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-blt.html

  
Known issues
------------

  Here are the changes found in xe-pw-144587v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#316])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#1124]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#2191])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@kms_bw@connected-linear-tiling-3-displays-2560x1440p.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#787]) +137 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-a-dp-4.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][21] ([Intel XE#2907])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#455] / [Intel XE#787]) +29 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][23] ([Intel XE#3862]) +1 other test incomplete
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][24] -> [INCOMPLETE][25] ([Intel XE#4010])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#306])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_color@ctm-0-25@pipe-a-hdmi-a-3:
    - shard-bmg:          [PASS][28] -> [DMESG-WARN][29] ([Intel XE#877]) +1 other test dmesg-warn
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_color@ctm-0-25@pipe-a-hdmi-a-3.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_color@ctm-0-25@pipe-a-hdmi-a-3.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][30] ([Intel XE#4132]) +1 other test incomplete
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-7/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [DMESG-FAIL][31] ([Intel XE#4172])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][32] ([Intel XE#323])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-bmg:          [PASS][33] -> [SKIP][34] ([Intel XE#2291])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-dg2-set2:     [PASS][35] -> [SKIP][36] ([Intel XE#309])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-466/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#455])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [PASS][38] -> [SKIP][39] ([Intel XE#2373])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_feature_discovery@display-2x.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][40] ([Intel XE#4172]) +2 other tests dmesg-warn
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-dg2-set2:     [PASS][41] -> [SKIP][42] ([Intel XE#310]) +4 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_flip@2x-dpms-vs-vblank-race.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4:
    - shard-dg2-set2:     [PASS][43] -> [FAIL][44] ([Intel XE#301] / [Intel XE#3321])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-436/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
    - shard-bmg:          [PASS][45] -> [FAIL][46] ([Intel XE#3321]) +1 other test fail
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-bmg:          [PASS][47] -> [SKIP][48] ([Intel XE#2316]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-2/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-4/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a6-dp4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][49] ([Intel XE#2882]) +2 other tests fail
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-466/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a6-dp4.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a3:
    - shard-bmg:          NOTRUN -> [FAIL][50] ([Intel XE#2882]) +1 other test fail
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_flip@flip-vs-absolute-wf_vblank@c-hdmi-a3.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1:
    - shard-adlp:         [PASS][51] -> [FAIL][52] ([Intel XE#886])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a1:
    - shard-adlp:         [PASS][53] -> [FAIL][54] ([Intel XE#2882]) +2 other tests fail
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@d-dp2:
    - shard-bmg:          [PASS][55] -> [FAIL][56] ([Intel XE#2882]) +1 other test fail
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_flip@plain-flip-ts-check-interruptible@d-dp2.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_flip@plain-flip-ts-check-interruptible@d-dp2.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x:
    - shard-adlp:         [PASS][57] -> [FAIL][58] ([Intel XE#1874])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-x.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#651]) +10 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     [PASS][60] -> [SKIP][61] ([Intel XE#656])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][62] ([Intel XE#653]) +12 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_plane_cursor@primary@pipe-a-hdmi-a-2-size-256:
    - shard-dg2-set2:     NOTRUN -> [FAIL][63] ([Intel XE#616]) +2 other tests fail
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_plane_cursor@primary@pipe-a-hdmi-a-2-size-256.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#1489])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr@fbc-psr-sprite-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#2850] / [Intel XE#929]) +6 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@kms_psr@fbc-psr-sprite-render.html

  * igt@kms_vblank@query-busy@pipe-d-hdmi-a-3:
    - shard-bmg:          [PASS][66] -> [DMESG-WARN][67] ([Intel XE#4172]) +15 other tests dmesg-warn
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-7/igt@kms_vblank@query-busy@pipe-d-hdmi-a-3.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-1/igt@kms_vblank@query-busy@pipe-d-hdmi-a-3.html

  * igt@kms_vblank@query-forked-hang@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [DMESG-WARN][68] ([Intel XE#1033]) +1 other test dmesg-warn
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-463/igt@kms_vblank@query-forked-hang@pipe-d-dp-4.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-dg2-set2:     NOTRUN -> [SKIP][69] ([Intel XE#1091] / [Intel XE#2849])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@xe_eudebug_online@debugger-reopen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][70] ([Intel XE#2905]) +3 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_eudebug_online@debugger-reopen.html

  * igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr-invalidate:
    - shard-dg2-set2:     [PASS][71] -> [DMESG-WARN][72] ([Intel XE#1033]) +4 other tests dmesg-warn
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr-invalidate.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@xe_exec_balancer@many-execqueues-cm-parallel-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][73] ([Intel XE#1392])
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race:
    - shard-dg2-set2:     [PASS][74] -> [SKIP][75] ([Intel XE#1392])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-463/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-rebind-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#288]) +11 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-rebind-imm.html

  * igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit:
    - shard-dg2-set2:     [PASS][77] -> [FAIL][78] ([Intel XE#1999]) +2 other tests fail
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-432/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@xe_live_ktest@xe_mocs@xe_live_mocs_kernel_kunit.html

  * igt@xe_oa@missing-sample-flags:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#2541] / [Intel XE#3573]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_oa@missing-sample-flags.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#2284] / [Intel XE#366])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@d3cold-mocs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#2284])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@xe_pm@d3cold-mocs.html

  * igt@xe_pm@s2idle-basic:
    - shard-adlp:         [PASS][82] -> [DMESG-WARN][83] ([Intel XE#3868])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-9/igt@xe_pm@s2idle-basic.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-3/igt@xe_pm@s2idle-basic.html

  * igt@xe_pm@s3-vm-bind-userptr:
    - shard-dg2-set2:     NOTRUN -> [ABORT][84] ([Intel XE#1033] / [Intel XE#1794])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_pm@s3-vm-bind-userptr.html

  * igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz:
    - shard-dg2-set2:     NOTRUN -> [SKIP][85] ([Intel XE#944])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@xe_query@multigpu-query-invalid-uc-fw-version-mbz.html

  * igt@xe_sriov_auto_provisioning@fair-allocation:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#4130])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@xe_sriov_auto_provisioning@fair-allocation.html

  
#### Possible fixes ####

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - shard-dg2-set2:     [DMESG-WARN][87] ([Intel XE#1033]) -> [PASS][88] +3 other tests pass
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-463/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][89] ([Intel XE#1727] / [Intel XE#3124] / [Intel XE#4010]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-dg2-set2:     [INCOMPLETE][91] ([Intel XE#4148]) -> [PASS][92] +1 other test pass
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-463/igt@kms_cursor_crc@cursor-suspend.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][93] ([Intel XE#2291]) -> [PASS][94] +1 other test pass
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-dg2-set2:     [SKIP][95] ([Intel XE#309]) -> [PASS][96] +1 other test pass
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-466/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg2-set2:     [SKIP][97] ([Intel XE#702]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_feature_discovery@display-2x.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-466/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3:
    - shard-bmg:          [INCOMPLETE][99] ([Intel XE#2049]) -> [PASS][100] +1 other test pass
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-8/igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-7/igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][101] ([Intel XE#3321]) -> [PASS][102] +1 other test pass
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4:
    - shard-dg2-set2:     [FAIL][103] ([Intel XE#301]) -> [PASS][104] +5 other tests pass
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-436/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-435/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-bmg:          [SKIP][105] ([Intel XE#2316]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-dg2-set2:     [SKIP][107] ([Intel XE#310]) -> [PASS][108] +1 other test pass
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_flip@2x-plain-flip-fb-recreate.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-463/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-dg2-set2:     [FAIL][109] ([Intel XE#2882]) -> [PASS][110] +1 other test pass
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a6:
    - shard-dg2-set2:     [FAIL][111] ([Intel XE#886]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a6.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@kms_flip@flip-vs-absolute-wf_vblank@a-hdmi-a6.html

  * igt@kms_flip@flip-vs-expired-vblank@c-dp4:
    - shard-dg2-set2:     [FAIL][113] ([Intel XE#301] / [Intel XE#3321]) -> [PASS][114] +3 other tests pass
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-433/igt@kms_flip@flip-vs-expired-vblank@c-dp4.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-adlp:         [DMESG-WARN][115] ([Intel XE#2953]) -> [PASS][116] +2 other tests pass
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-6/igt@kms_flip@flip-vs-suspend.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2:
    - shard-bmg:          [DMESG-FAIL][117] ([Intel XE#4172]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-dp2.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp2:
    - shard-bmg:          [FAIL][119] ([Intel XE#2882]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp2.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-1/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-dp2.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y:
    - shard-adlp:         [DMESG-FAIL][121] ([Intel XE#1033]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     [SKIP][123] ([Intel XE#656]) -> [PASS][124] +6 other tests pass
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-466/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][125] ([Intel XE#1503]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [SKIP][127] ([Intel XE#3012]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
    - shard-adlp:         [DMESG-WARN][129] ([Intel XE#4173]) -> [PASS][130] +4 other tests pass
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html

  * igt@kms_properties@connector-properties-legacy:
    - shard-bmg:          [DMESG-WARN][131] ([Intel XE#4172]) -> [PASS][132] +8 other tests pass
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_properties@connector-properties-legacy.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_properties@connector-properties-legacy.html

  * igt@kms_rmfb@rmfb-ioctl:
    - shard-adlp:         [DMESG-WARN][133] -> [PASS][134] +1 other test pass
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-8/igt@kms_rmfb@rmfb-ioctl.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_rmfb@rmfb-ioctl.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1:
    - shard-lnl:          [FAIL][135] ([Intel XE#899]) -> [PASS][136] +2 other tests pass
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-lnl-4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-lnl-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-edp-1.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][137] ([Intel XE#2159]) -> [PASS][138] +1 other test pass
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@kms_vrr@negative-basic:
    - shard-bmg:          [SKIP][139] ([Intel XE#1499]) -> [PASS][140]
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@kms_vrr@negative-basic.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-4/igt@kms_vrr@negative-basic.html

  * igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01:
    - shard-dg2-set2:     [ABORT][141] ([Intel XE#2625]) -> [PASS][142] +1 other test pass
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-432/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01.html
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-434/igt@xe_ccs@suspend-resume@tile64-compressed-compfmt0-vram01-vram01.html

  * igt@xe_exec_basic@multigpu-once-null:
    - shard-dg2-set2:     [SKIP][143] ([Intel XE#1392]) -> [PASS][144] +2 other tests pass
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-436/igt@xe_exec_basic@multigpu-once-null.html

  
#### Warnings ####

  * igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][145] ([Intel XE#787]) -> [SKIP][146] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-466/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-6.html
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_ccs@bad-aux-stride-y-tiled-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [DMESG-WARN][147] ([Intel XE#1033]) -> [INCOMPLETE][148] ([Intel XE#1727] / [Intel XE#4010])
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [SKIP][149] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][150] ([Intel XE#787]) +10 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-463/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [FAIL][151] ([Intel XE#1178]) -> [SKIP][152] ([Intel XE#2341])
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_content_protection@atomic.html
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [SKIP][153] ([Intel XE#2341]) -> [DMESG-FAIL][154] ([Intel XE#4172])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@kms_content_protection@srm.html
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_content_protection@srm.html

  * igt@kms_dp_aux_dev:
    - shard-dg2-set2:     [SKIP][155] ([Intel XE#3009]) -> [DMESG-WARN][156] ([Intel XE#1033])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_dp_aux_dev.html
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-463/igt@kms_dp_aux_dev.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-bmg:          [FAIL][157] ([Intel XE#2882]) -> [SKIP][158] ([Intel XE#2316]) +1 other test skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-2/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-bmg:          [FAIL][159] ([Intel XE#3321]) -> [SKIP][160] ([Intel XE#2316])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-bmg:          [SKIP][161] ([Intel XE#2316]) -> [DMESG-WARN][162] ([Intel XE#4172]) +1 other test dmesg-warn
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check:
    - shard-dg2-set2:     [SKIP][163] ([Intel XE#310]) -> [FAIL][164] ([Intel XE#2882])
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_flip@2x-plain-flip-ts-check.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-466/igt@kms_flip@2x-plain-flip-ts-check.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [DMESG-FAIL][165] ([Intel XE#4172]) -> [DMESG-WARN][166] ([Intel XE#4172])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-8/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-1/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-bmg:          [FAIL][167] ([Intel XE#2882]) -> [FAIL][168] ([Intel XE#2882] / [Intel XE#3098])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-dp2:
    - shard-bmg:          [FAIL][169] ([Intel XE#2882]) -> [FAIL][170] ([Intel XE#3098])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_flip@plain-flip-ts-check-interruptible@b-dp2.html
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_flip@plain-flip-ts-check-interruptible@b-dp2.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
    - shard-adlp:         [FAIL][171] ([Intel XE#1874]) -> [DMESG-FAIL][172] ([Intel XE#1033])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff:
    - shard-dg2-set2:     [SKIP][173] ([Intel XE#651]) -> [SKIP][174] ([Intel XE#656]) +5 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][175] ([Intel XE#2311]) -> [SKIP][176] ([Intel XE#2312]) +6 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][177] ([Intel XE#2312]) -> [SKIP][178] ([Intel XE#2311]) +8 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][179] ([Intel XE#2312]) -> [SKIP][180] ([Intel XE#4141]) +3 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     [DMESG-WARN][181] ([Intel XE#1033]) -> [SKIP][182] ([Intel XE#656])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][183] ([Intel XE#4141]) -> [SKIP][184] ([Intel XE#2312]) +7 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][185] ([Intel XE#656]) -> [SKIP][186] ([Intel XE#651]) +10 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          [SKIP][187] ([Intel XE#2312]) -> [SKIP][188] ([Intel XE#2313]) +5 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][189] ([Intel XE#653]) -> [SKIP][190] ([Intel XE#656]) +5 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-bmg:          [SKIP][191] ([Intel XE#2313]) -> [SKIP][192] ([Intel XE#2312]) +5 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-dg2-set2:     [SKIP][193] ([Intel XE#656]) -> [SKIP][194] ([Intel XE#653]) +8 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-dg2-set2:     [DMESG-WARN][195] ([Intel XE#1033]) -> [INCOMPLETE][196] ([Intel XE#1727] / [Intel XE#4170])
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-434/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-464/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@xe_live_ktest@xe_eudebug:
    - shard-bmg:          [SKIP][197] ([Intel XE#1192]) -> [SKIP][198] ([Intel XE#2833])
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-bmg-6/igt@xe_live_ktest@xe_eudebug.html
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-bmg-4/igt@xe_live_ktest@xe_eudebug.html

  * igt@xe_pm@s3-vm-bind-prefetch:
    - shard-dg2-set2:     [DMESG-WARN][199] ([Intel XE#1033] / [Intel XE#569]) -> [ABORT][200] ([Intel XE#1033] / [Intel XE#1794])
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-dg2-466/igt@xe_pm@s3-vm-bind-prefetch.html
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-dg2-432/igt@xe_pm@s3-vm-bind-prefetch.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         [ABORT][201] ([Intel XE#4268]) -> [ABORT][202] ([Intel XE#2953] / [Intel XE#4268])
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f/shard-adlp-2/igt@xe_pm@s4-basic.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/shard-adlp-9/igt@xe_pm@s4-basic.html

  
  [Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
  [Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1192]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1192
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#1999]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1999
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2159
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2625
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
  [Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
  [Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#4010]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4010
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4132]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4132
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4148]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4148
  [Intel XE#4170]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4170
  [Intel XE#4172]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4172
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4268]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4268
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/569
  [Intel XE#616]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/616
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#702]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/702
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f -> xe-pw-144587v2

  IGT_8228: 8228
  xe-2638-27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f: 27f9e4e3866556a4498e3b4ddebc27d4f6d0ae2f
  xe-pw-144587v2: 144587v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-144587v2/index.html

[-- Attachment #2: Type: text/html, Size: 62688 bytes --]

RE: [PATCH 0/9] drm_i915_private to intel_display cleanup

[Kandpal, Suraj]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, February 11, 2025 4:19 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: [PATCH 0/9] drm_i915_private to intel_display cleanup
> 
> This series started as a cleanup to convert as many drm_i915_private to
> intel_display in intel_display_debug_fs but overflowed and ended up
> cleaning intel_dpll_mgr.c part of the code too and some other places calling
> these functions. This series also replaces IS_PLATFORM() with display-
> >platform.xx to reduce drm_i915_private usage.
> Some stuff that kept me from removing i915_private altogether were PCH
> checks.
> 
> --v2
> -Rebase
> 
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Thanks for the reviews pushed to din

Regards,
Suraj Kandpal

> 
> Suraj Kandpal (9):
>   drm/i915/display_debug_fs: Use intel_display wherever possible
>   drm/i915/display_debug_fs: Prefer using display->platform
>   drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
>   drm/i915/dpll: Use intel_display for dpll dump and compare hw state
>   drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
>   drm/i915/dpll: Use intel_display for asserting pll
>   drm/i915/dpll: Use intel_display for update_refclk hook
>   drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
>   drm/i915/dpll: Replace all other leftover drm_i915_private
> 
>  .../drm/i915/display/intel_crtc_state_dump.c  |    3 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  130 +--
>  drivers/gpu/drm/i915/display/intel_display.c  |   30 +-
>  .../drm/i915/display/intel_display_debugfs.c  |  173 +--
>  .../drm/i915/display/intel_display_driver.c   |    4 +-
>  .../i915/display/intel_display_power_well.c   |   13 +-
>  drivers/gpu/drm/i915/display/intel_dkl_phy.c  |   54 +-
>  drivers/gpu/drm/i915/display/intel_dkl_phy.h  |    9 +-
>  drivers/gpu/drm/i915/display/intel_dpll.c     |   11 +-
>  drivers/gpu/drm/i915/display/intel_dpll.h     |    5 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1011 ++++++++---------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   27 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c      |   16 +-
>  drivers/gpu/drm/i915/display/intel_fdi.h      |    7 +-
>  drivers/gpu/drm/i915/display/intel_lvds.c     |    7 +-
>  .../drm/i915/display/intel_modeset_setup.c    |    4 +-
>  .../gpu/drm/i915/display/intel_pch_display.c  |   45 +-
>  .../gpu/drm/i915/display/intel_pch_refclk.c   |   36 +-
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.c    |   12 +-
>  drivers/gpu/drm/i915/display/vlv_dsi_pll.h    |   10 +-
>  20 files changed, 799 insertions(+), 808 deletions(-)
> 
> --
> 2.34.1

[PATCH 0/9] drm_i915_private to intel_display cleanup

[Suraj Kandpal]

This series started as a cleanup to convert as many drm_i915_private
to intel_display in intel_display_debug_fs but overflowed and ended up
cleaning intel_dpll_mgr.c part of the code too and some other places
calling these functions. This series also replaces IS_PLATFORM()
with display->platform.xx to reduce drm_i915_private usage.
Some stuff that kept me from removing i915_private altogether were
PCH checks and intel_display_power_get and put which will be a part of
subsequent patch series.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Suraj Kandpal (9):
  drm/i915/display_debug_fs: Use intel_display wherever possible
  drm/i915/display_debug_fs: Prefer using display->platform
  drm/i915/dpll: Change param to intel_display in for_each_shared_dpll
  drm/i915/dpll: Use intel_display for dpll dump and compare hw state
  drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks
  drm/i915/dpll: Use intel_display for asserting pll
  drm/i915/dpll: Use intel_display for update_refclk hook
  drm/i915/dpll: Accept intel_display as argument for shared_dpll_init
  drm/i915/dpll: Replace all other leftover drm_i915_private

 .../drm/i915/display/intel_crtc_state_dump.c  |    3 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  130 +--
 drivers/gpu/drm/i915/display/intel_display.c  |   30 +-
 .../drm/i915/display/intel_display_debugfs.c  |  172 +--
 .../drm/i915/display/intel_display_driver.c   |    4 +-
 .../i915/display/intel_display_power_well.c   |   13 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |   54 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |    9 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |   11 +-
 drivers/gpu/drm/i915/display/intel_dpll.h     |    5 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1006 +++++++++--------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   27 +-
 drivers/gpu/drm/i915/display/intel_fdi.c      |   16 +-
 drivers/gpu/drm/i915/display/intel_fdi.h      |    7 +-
 drivers/gpu/drm/i915/display/intel_lvds.c     |    7 +-
 .../drm/i915/display/intel_modeset_setup.c    |    4 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |   45 +-
 .../gpu/drm/i915/display/intel_pch_refclk.c   |   36 +-
 drivers/gpu/drm/i915/display/vlv_dsi_pll.c    |   12 +-
 drivers/gpu/drm/i915/display/vlv_dsi_pll.h    |   10 +-
 20 files changed, 810 insertions(+), 791 deletions(-)

-- 
2.34.1

[PATCH 5/9] drm/i915/dpll: Use intel_display possible in shared_dpll_mgr hooks

[Suraj Kandpal]

We use intel_display for function hooks of shared_dpll_mgr and
any function that gets called when we use for_each_shared_dpll.
This also contains some opportunistic display->platform.xx changes
all to reductate the use of drm_i915_private.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 130 +--
 .../i915/display/intel_display_power_well.c   |   3 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.c  |  54 +-
 drivers/gpu/drm/i915/display/intel_dkl_phy.h  |   9 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 789 +++++++++---------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  10 +-
 .../drm/i915/display/intel_modeset_setup.c    |   4 +-
 .../gpu/drm/i915/display/intel_pch_display.c  |  43 +-
 8 files changed, 528 insertions(+), 514 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index db3c2d85c57b..5f072ce1e0ad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -358,10 +358,10 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 	}
 }
 
-static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
+static int icl_calc_tbt_pll_link(struct intel_display *display,
 				 enum port port)
 {
-	u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+	u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 
 	switch (val) {
 	case DDI_CLK_SEL_NONE:
@@ -1366,7 +1366,7 @@ static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 					  const struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum tc_port tc_port = intel_encoder_to_tc(encoder);
 	const struct intel_ddi_buf_trans *trans;
 	int n_entries, ln;
@@ -1375,17 +1375,17 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 		return;
 
 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
+	if (drm_WARN_ON_ONCE(display->drm, !trans))
 		return;
 
 	for (ln = 0; ln < 2; ln++) {
 		int level;
 
-		intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
+		intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0);
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
 
-		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port, ln),
+		intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
 				  DKL_TX_PRESHOOT_COEFF_MASK |
 				  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 				  DKL_TX_VSWING_CONTROL_MASK,
@@ -1395,7 +1395,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 
 		level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
 
-		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port, ln),
+		intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
 				  DKL_TX_PRESHOOT_COEFF_MASK |
 				  DKL_TX_DE_EMPAHSIS_COEFF_MASK |
 				  DKL_TX_VSWING_CONTROL_MASK,
@@ -1403,10 +1403,10 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 				  DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
 				  DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
 
-		intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+		intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
 				  DKL_TX_DP20BITMODE, 0);
 
-		if (IS_ALDERLAKE_P(dev_priv)) {
+		if (display->platform.alderlake_p) {
 			u32 val;
 
 			if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
@@ -1422,7 +1422,7 @@ static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
 				val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
 			}
 
-			intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port, ln),
+			intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
 					  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
 					  DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
 					  val);
@@ -1550,14 +1550,14 @@ static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t
 }
 
 static struct intel_shared_dpll *
-_icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
+_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
 		 u32 clk_sel_mask, u32 clk_sel_shift)
 {
 	enum intel_dpll_id id;
 
-	id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
+	id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1596,10 +1596,10 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 
-	return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
+	return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
 				ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
 				ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
 }
@@ -1640,10 +1640,10 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 
-	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
 				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 				RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
 }
@@ -1693,12 +1693,12 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 	enum intel_dpll_id id;
 	u32 val;
 
-	val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
+	val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
 	val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 	val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
 	id = val;
@@ -1711,7 +1711,7 @@ static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
 	if (phy >= PHY_C)
 		id += DPLL_ID_DG1_DPLL2;
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
@@ -1750,10 +1750,10 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
 
 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 
-	return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
+	return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
 				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
 				ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
 }
@@ -1858,13 +1858,13 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum tc_port tc_port = intel_encoder_to_tc(encoder);
 	enum port port = encoder->port;
 	enum intel_dpll_id id;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+	tmp = intel_de_read(display, DDI_CLK_SEL(port));
 
 	switch (tmp & DDI_CLK_SEL_MASK) {
 	case DDI_CLK_SEL_TBT_162:
@@ -1883,12 +1883,12 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode
 		return NULL;
 	}
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder->base.dev);
 	enum intel_dpll_id id;
 
 	switch (encoder->port) {
@@ -1906,7 +1906,7 @@ static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
 		return NULL;
 	}
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -1957,12 +1957,12 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
 	enum intel_dpll_id id;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, DPLL_CTRL2);
+	tmp = intel_de_read(display, DPLL_CTRL2);
 
 	/*
 	 * FIXME Not sure if the override affects both
@@ -1974,7 +1974,7 @@ static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
 	id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
 		DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2008,12 +2008,12 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
 
 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
 	enum intel_dpll_id id;
 	u32 tmp;
 
-	tmp = intel_de_read(i915, PORT_CLK_SEL(port));
+	tmp = intel_de_read(display, PORT_CLK_SEL(port));
 
 	switch (tmp & PORT_CLK_SEL_MASK) {
 	case PORT_CLK_SEL_WRPLL1:
@@ -2041,7 +2041,7 @@ static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
 		return NULL;
 	}
 
-	return intel_get_shared_dpll_by_id(i915, id);
+	return intel_get_shared_dpll_by_id(display, id);
 }
 
 void intel_ddi_enable_clock(struct intel_encoder *encoder,
@@ -2121,13 +2121,13 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
 }
 
 static void
-tgl_dkl_phy_check_and_rewrite(struct drm_i915_private *dev_priv,
+tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
 			      enum tc_port tc_port, u32 ln0, u32 ln1)
 {
-	if (ln0 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0)))
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
-	if (ln1 != intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1)))
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+	if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+	if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
 }
 
 static void
@@ -2135,24 +2135,23 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		       const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
 	u32 ln0, ln1, pin_assignment;
 	u8 width;
 
-	if (DISPLAY_VER(dev_priv) >= 14)
+	if (DISPLAY_VER(display) >= 14)
 		return;
 
 	if (!intel_encoder_is_tc(&dig_port->base) ||
 	    intel_tc_port_in_tbt_alt_mode(dig_port))
 		return;
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
-		ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 0));
-		ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port, 1));
+	if (DISPLAY_VER(display) >= 12) {
+		ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
+		ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
 	} else {
-		ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
-		ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
+		ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
+		ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
 	}
 
 	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
@@ -2164,7 +2163,7 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 
 	switch (pin_assignment) {
 	case 0x0:
-		drm_WARN_ON(&dev_priv->drm,
+		drm_WARN_ON(display->drm,
 			    !intel_tc_port_in_legacy_mode(dig_port));
 		if (width == 1) {
 			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
@@ -2209,16 +2208,16 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
 		MISSING_CASE(pin_assignment);
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 12) {
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 0), ln0);
-		intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port, 1), ln1);
+	if (DISPLAY_VER(display) >= 12) {
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0);
+		intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1);
 		 /* WA_14018221282 */
 		if (IS_DISPLAY_VER(display, 12, 13))
-			tgl_dkl_phy_check_and_rewrite(dev_priv, tc_port, ln0, ln1);
+			tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
 
 	} else {
-		intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
-		intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
+		intel_de_write(display, MG_DP_MODE(0, tc_port), ln0);
+		intel_de_write(display, MG_DP_MODE(1, tc_port), ln1);
 	}
 }
 
@@ -3725,12 +3724,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
 
 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum tc_port tc_port = intel_encoder_to_tc(encoder);
 	int ln;
 
 	for (ln = 0; ln < 2; ln++)
-		intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port, ln), DKL_PCS_DW5_CORE_SOFTRESET, 0);
+		intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
+				  DKL_PCS_DW5_CORE_SOFTRESET, 0);
 }
 
 static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
@@ -4248,21 +4248,21 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 			 struct intel_crtc_state *crtc_state,
 			 struct intel_shared_dpll *pll)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
 	struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
 	bool pll_active;
 
-	if (drm_WARN_ON(&i915->drm, !pll))
+	if (drm_WARN_ON(display->drm, !pll))
 		return;
 
 	port_dpll->pll = pll;
-	pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
-	drm_WARN_ON(&i915->drm, !pll_active);
+	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+	drm_WARN_ON(display->drm, !pll_active);
 
 	icl_set_active_port_dpll(crtc_state, port_dpll_id);
 
-	crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+	crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
 						     &crtc_state->dpll_hw_state);
 }
 
@@ -4351,12 +4351,12 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
 				 struct intel_crtc_state *crtc_state,
 				 struct intel_shared_dpll *pll)
 {
-	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	struct intel_display *display = to_intel_display(encoder);
 	enum icl_port_dpll_id port_dpll_id;
 	struct icl_port_dpll *port_dpll;
 	bool pll_active;
 
-	if (drm_WARN_ON(&i915->drm, !pll))
+	if (drm_WARN_ON(display->drm, !pll))
 		return;
 
 	if (icl_ddi_tc_pll_is_tbt(pll))
@@ -4367,15 +4367,15 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
 	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
 
 	port_dpll->pll = pll;
-	pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
-	drm_WARN_ON(&i915->drm, !pll_active);
+	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+	drm_WARN_ON(display->drm, !pll_active);
 
 	icl_set_active_port_dpll(crtc_state, port_dpll_id);
 
 	if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))
-		crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
+		crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);
 	else
-		crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
+		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,
 							     &crtc_state->dpll_hw_state);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f45a4f9ba23c..a31d1678dfc0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -507,7 +507,6 @@ static void
 icl_tc_phy_aux_power_well_enable(struct intel_display *display,
 				 struct i915_power_well *power_well)
 {
-	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
 	const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
@@ -539,7 +538,7 @@ icl_tc_phy_aux_power_well_enable(struct intel_display *display,
 
 		tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
 
-		if (wait_for(intel_dkl_phy_read(dev_priv, DKL_CMN_UC_DW_27(tc_port)) &
+		if (wait_for(intel_dkl_phy_read(display, DKL_CMN_UC_DW_27(tc_port)) &
 			     DKL_CMN_UC_DW27_UC_HEALTH, 1))
 			drm_warn(display->drm,
 				 "Timeout waiting TC uC health\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
index b146b4c46943..0920f78f182e 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c
@@ -20,20 +20,20 @@ void intel_dkl_phy_init(struct drm_i915_private *i915)
 }
 
 static void
-dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+dkl_phy_set_hip_idx(struct intel_display *display, struct intel_dkl_phy_reg reg)
 {
 	enum tc_port tc_port = DKL_REG_TC_PORT(reg);
 
-	drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
+	drm_WARN_ON(display->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS);
 
-	intel_de_write(i915,
+	intel_de_write(display,
 		       HIP_INDEX_REG(tc_port),
 		       HIP_INDEX_VAL(tc_port, reg.bank_idx));
 }
 
 /**
  * intel_dkl_phy_read - read a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
  * @reg: Dekel PHY register
  *
  * Read the @reg Dekel PHY register.
@@ -41,42 +41,42 @@ dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
  * Returns the read value.
  */
 u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
 {
 	u32 val;
 
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	val = intel_de_read(i915, DKL_REG_MMIO(reg));
+	dkl_phy_set_hip_idx(display, reg);
+	val = intel_de_read(display, DKL_REG_MMIO(reg));
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 
 	return val;
 }
 
 /**
  * intel_dkl_phy_write - write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: intel_display device instance
  * @reg: Dekel PHY register
  * @val: value to write
  *
  * Write @val to the @reg Dekel PHY register.
  */
 void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val)
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val)
 {
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	intel_de_write(i915, DKL_REG_MMIO(reg), val);
+	dkl_phy_set_hip_idx(display, reg);
+	intel_de_write(display, DKL_REG_MMIO(reg), val);
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 }
 
 /**
  * intel_dkl_phy_rmw - read-modify-write a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
  * @reg: Dekel PHY register
  * @clear: mask to clear
  * @set: mask to set
@@ -85,30 +85,30 @@ intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg,
  * this value back to the register if the value differs from the read one.
  */
 void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set)
 {
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set);
+	dkl_phy_set_hip_idx(display, reg);
+	intel_de_rmw(display, DKL_REG_MMIO(reg), clear, set);
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 }
 
 /**
  * intel_dkl_phy_posting_read - do a posting read from a Dekel PHY register
- * @i915: i915 device instance
+ * @display: display device instance
  * @reg: Dekel PHY register
  *
  * Read the @reg Dekel PHY register without returning the read value.
  */
 void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg)
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg)
 {
-	spin_lock(&i915->display.dkl.phy_lock);
+	spin_lock(&display->dkl.phy_lock);
 
-	dkl_phy_set_hip_idx(i915, reg);
-	intel_de_posting_read(i915, DKL_REG_MMIO(reg));
+	dkl_phy_set_hip_idx(display, reg);
+	intel_de_posting_read(display, DKL_REG_MMIO(reg));
 
-	spin_unlock(&i915->display.dkl.phy_lock);
+	spin_unlock(&display->dkl.phy_lock);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.h b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
index 5956ec3e940b..1d96e6be657c 100644
--- a/drivers/gpu/drm/i915/display/intel_dkl_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.h
@@ -11,15 +11,16 @@
 #include "intel_dkl_phy_regs.h"
 
 struct drm_i915_private;
+struct intel_display;
 
 void intel_dkl_phy_init(struct drm_i915_private *i915);
 u32
-intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
 void
-intel_dkl_phy_write(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 val);
+intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
 void
-intel_dkl_phy_rmw(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
+intel_dkl_phy_rmw(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 clear, u32 set);
 void
-intel_dkl_phy_posting_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg);
+intel_dkl_phy_posting_read(struct intel_display *display, struct intel_dkl_phy_reg reg);
 
 #endif /* __INTEL_DKL_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ec46adb13af7..8655522458d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -65,7 +65,7 @@ struct intel_shared_dpll_funcs {
 	 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
 	 * the pll is not already enabled.
 	 */
-	void (*enable)(struct drm_i915_private *i915,
+	void (*enable)(struct intel_display *display,
 		       struct intel_shared_dpll *pll,
 		       const struct intel_dpll_hw_state *dpll_hw_state);
 
@@ -74,7 +74,7 @@ struct intel_shared_dpll_funcs {
 	 * only when it is safe to disable the pll, i.e., there are no more
 	 * tracked users for it.
 	 */
-	void (*disable)(struct drm_i915_private *i915,
+	void (*disable)(struct intel_display *display,
 			struct intel_shared_dpll *pll);
 
 	/*
@@ -82,7 +82,7 @@ struct intel_shared_dpll_funcs {
 	 * registers. This is used for initial hw state readout and state
 	 * verification after a mode set.
 	 */
-	bool (*get_hw_state)(struct drm_i915_private *i915,
+	bool (*get_hw_state)(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *dpll_hw_state);
 
@@ -90,7 +90,7 @@ struct intel_shared_dpll_funcs {
 	 * Hook for calculating the pll's output frequency based on its passed
 	 * in state.
 	 */
-	int (*get_freq)(struct drm_i915_private *i915,
+	int (*get_freq)(struct intel_display *i915,
 			const struct intel_shared_dpll *pll,
 			const struct intel_dpll_hw_state *dpll_hw_state);
 };
@@ -148,17 +148,16 @@ intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
 
 /**
  * intel_get_shared_dpll_by_id - get a DPLL given its id
- * @i915: i915 device instance
+ * @display: intel_display device instance
  * @id: pll id
  *
  * Returns:
  * A pointer to the DPLL with @id
  */
 struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
 			    enum intel_dpll_id id)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
@@ -184,7 +183,7 @@ void assert_shared_dpll(struct drm_i915_private *i915,
 		     "asserting DPLL %s with no DPLL\n", str_on_off(state)))
 		return;
 
-	cur_state = intel_dpll_get_hw_state(i915, pll, &hw_state);
+	cur_state = intel_dpll_get_hw_state(display, pll, &hw_state);
 	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
 				 "%s assertion failure (expected %s, current %s)\n",
 				 pll->info->name, str_on_off(state),
@@ -202,12 +201,12 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 }
 
 static i915_reg_t
-intel_combo_pll_enable_reg(struct drm_i915_private *i915,
+intel_combo_pll_enable_reg(struct intel_display *display,
 			   struct intel_shared_dpll *pll)
 {
-	if (IS_DG1(i915))
+	if (display->platform.dg1)
 		return DG1_DPLL_ENABLE(pll->info->id);
-	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		 (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
@@ -215,36 +214,40 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 }
 
 static i915_reg_t
-intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+intel_tc_pll_enable_reg(struct intel_display *display,
 			struct intel_shared_dpll *pll)
 {
 	const enum intel_dpll_id id = pll->info->id;
 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
 
-	if (IS_ALDERLAKE_P(i915))
+	if (display->platform.alderlake_p)
 		return ADLP_PORTTC_PLL_ENABLE(tc_port);
 
 	return MG_PLL_ENABLE(tc_port);
 }
 
-static void _intel_enable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_enable_shared_dpll(struct intel_display *display,
 				      struct intel_shared_dpll *pll)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
+
 	if (pll->info->power_domain)
 		pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
 
-	pll->info->funcs->enable(i915, pll, &pll->state.hw_state);
+	pll->info->funcs->enable(display, pll, &pll->state.hw_state);
 	pll->on = true;
 }
 
-static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
+static void _intel_disable_shared_dpll(struct intel_display *display,
 				       struct intel_shared_dpll *pll)
 {
-	pll->info->funcs->disable(i915, pll);
+	pll->info->funcs->disable(display, pll);
 	pll->on = false;
 
 	if (pll->info->power_domain)
-		intel_display_power_put(i915, pll->info->power_domain, pll->wakeref);
+		intel_display_power_put(to_i915(display->drm),
+					pll->info->power_domain,
+					pll->wakeref);
 }
 
 /**
@@ -255,42 +258,43 @@ static void _intel_disable_shared_dpll(struct drm_i915_private *i915,
  */
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int pipe_mask = BIT(crtc->pipe);
 	unsigned int old_mask;
 
-	if (drm_WARN_ON(&i915->drm, pll == NULL))
+	if (drm_WARN_ON(display->drm, !pll))
 		return;
 
-	mutex_lock(&i915->display.dpll.lock);
+	mutex_lock(&display->dpll.lock);
 	old_mask = pll->active_mask;
 
-	if (drm_WARN_ON(&i915->drm, !(pll->state.pipe_mask & pipe_mask)) ||
-	    drm_WARN_ON(&i915->drm, pll->active_mask & pipe_mask))
+	if (drm_WARN_ON(display->drm, !(pll->state.pipe_mask & pipe_mask)) ||
+	    drm_WARN_ON(display->drm, pll->active_mask & pipe_mask))
 		goto out;
 
 	pll->active_mask |= pipe_mask;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
 		    pll->info->name, pll->active_mask, pll->on,
 		    crtc->base.base.id, crtc->base.name);
 
 	if (old_mask) {
-		drm_WARN_ON(&i915->drm, !pll->on);
+		drm_WARN_ON(display->drm, !pll->on);
 		assert_shared_dpll_enabled(i915, pll);
 		goto out;
 	}
-	drm_WARN_ON(&i915->drm, pll->on);
+	drm_WARN_ON(display->drm, pll->on);
 
-	drm_dbg_kms(&i915->drm, "enabling %s\n", pll->info->name);
+	drm_dbg_kms(display->drm, "enabling %s\n", pll->info->name);
 
-	_intel_enable_shared_dpll(i915, pll);
+	_intel_enable_shared_dpll(display, pll);
 
 out:
-	mutex_unlock(&i915->display.dpll.lock);
+	mutex_unlock(&display->dpll.lock);
 }
 
 /**
@@ -301,48 +305,48 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
  */
 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	unsigned int pipe_mask = BIT(crtc->pipe);
 
 	/* PCH only available on ILK+ */
-	if (DISPLAY_VER(i915) < 5)
+	if (DISPLAY_VER(display) < 5)
 		return;
 
 	if (pll == NULL)
 		return;
 
-	mutex_lock(&i915->display.dpll.lock);
-	if (drm_WARN(&i915->drm, !(pll->active_mask & pipe_mask),
+	mutex_lock(&display->dpll.lock);
+	if (drm_WARN(display->drm, !(pll->active_mask & pipe_mask),
 		     "%s not used by [CRTC:%d:%s]\n", pll->info->name,
 		     crtc->base.base.id, crtc->base.name))
 		goto out;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
 		    pll->info->name, pll->active_mask, pll->on,
 		    crtc->base.base.id, crtc->base.name);
 
 	assert_shared_dpll_enabled(i915, pll);
-	drm_WARN_ON(&i915->drm, !pll->on);
+	drm_WARN_ON(display->drm, !pll->on);
 
 	pll->active_mask &= ~pipe_mask;
 	if (pll->active_mask)
 		goto out;
 
-	drm_dbg_kms(&i915->drm, "disabling %s\n", pll->info->name);
+	drm_dbg_kms(display->drm, "disabling %s\n", pll->info->name);
 
-	_intel_disable_shared_dpll(i915, pll);
+	_intel_disable_shared_dpll(display, pll);
 
 out:
-	mutex_unlock(&i915->display.dpll.lock);
+	mutex_unlock(&display->dpll.lock);
 }
 
 static unsigned long
-intel_dpll_mask_all(struct drm_i915_private *i915)
+intel_dpll_mask_all(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	unsigned long dpll_mask = 0;
 	int i;
@@ -362,20 +366,20 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 		       const struct intel_dpll_hw_state *dpll_hw_state,
 		       unsigned long dpll_mask)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	unsigned long dpll_mask_all = intel_dpll_mask_all(i915);
+	struct intel_display *display = to_intel_display(crtc);
+	unsigned long dpll_mask_all = intel_dpll_mask_all(display);
 	struct intel_shared_dpll_state *shared_dpll;
 	struct intel_shared_dpll *unused_pll = NULL;
 	enum intel_dpll_id id;
 
 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
 
-	drm_WARN_ON(&i915->drm, dpll_mask & ~dpll_mask_all);
+	drm_WARN_ON(display->drm, dpll_mask & ~dpll_mask_all);
 
 	for_each_set_bit(id, &dpll_mask, fls(dpll_mask_all)) {
 		struct intel_shared_dpll *pll;
 
-		pll = intel_get_shared_dpll_by_id(i915, id);
+		pll = intel_get_shared_dpll_by_id(display, id);
 		if (!pll)
 			continue;
 
@@ -389,7 +393,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 		if (memcmp(dpll_hw_state,
 			   &shared_dpll[pll->index].hw_state,
 			   sizeof(*dpll_hw_state)) == 0) {
-			drm_dbg_kms(&i915->drm,
+			drm_dbg_kms(display->drm,
 				    "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
 				    crtc->base.base.id, crtc->base.name,
 				    pll->info->name,
@@ -401,7 +405,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
 
 	/* Ok no matching timings, maybe there's a free one? */
 	if (unused_pll) {
-		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] allocated %s\n",
+		drm_dbg_kms(display->drm, "[CRTC:%d:%s] allocated %s\n",
 			    crtc->base.base.id, crtc->base.name,
 			    unused_pll->info->name);
 		return unused_pll;
@@ -524,10 +528,11 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
 		swap(pll->state, shared_dpll[pll->index]);
 }
 
-static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
+static bool ibx_pch_dpll_get_hw_state(struct intel_display *display,
 				      struct intel_shared_dpll *pll,
 				      struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
 	const enum intel_dpll_id id = pll->info->id;
 	intel_wakeref_t wakeref;
@@ -538,10 +543,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, PCH_DPLL(id));
+	val = intel_de_read(display, PCH_DPLL(id));
 	hw_state->dpll = val;
-	hw_state->fp0 = intel_de_read(i915, PCH_FP0(id));
-	hw_state->fp1 = intel_de_read(i915, PCH_FP1(id));
+	hw_state->fp0 = intel_de_read(display, PCH_FP0(id));
+	hw_state->fp1 = intel_de_read(display, PCH_FP1(id));
 
 	intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 
@@ -561,23 +566,24 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *i915)
 				 "PCH refclk assertion failure, should be active but is disabled\n");
 }
 
-static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_enable(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	const struct i9xx_dpll_hw_state *hw_state = &dpll_hw_state->i9xx;
 	const enum intel_dpll_id id = pll->info->id;
 
 	/* PCH refclock must be enabled first */
 	ibx_assert_pch_refclk_enabled(i915);
 
-	intel_de_write(i915, PCH_FP0(id), hw_state->fp0);
-	intel_de_write(i915, PCH_FP1(id), hw_state->fp1);
+	intel_de_write(display, PCH_FP0(id), hw_state->fp0);
+	intel_de_write(display, PCH_FP1(id), hw_state->fp1);
 
-	intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
+	intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
 
 	/* Wait for the clocks to stabilize. */
-	intel_de_posting_read(i915, PCH_DPLL(id));
+	intel_de_posting_read(display, PCH_DPLL(id));
 	udelay(150);
 
 	/* The pixel multiplier can only be updated once the
@@ -585,18 +591,18 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *i915,
 	 *
 	 * So write it again.
 	 */
-	intel_de_write(i915, PCH_DPLL(id), hw_state->dpll);
-	intel_de_posting_read(i915, PCH_DPLL(id));
+	intel_de_write(display, PCH_DPLL(id), hw_state->dpll);
+	intel_de_posting_read(display, PCH_DPLL(id));
 	udelay(200);
 }
 
-static void ibx_pch_dpll_disable(struct drm_i915_private *i915,
+static void ibx_pch_dpll_disable(struct intel_display *display,
 				 struct intel_shared_dpll *pll)
 {
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_write(i915, PCH_DPLL(id), 0);
-	intel_de_posting_read(i915, PCH_DPLL(id));
+	intel_de_write(display, PCH_DPLL(id), 0);
+	intel_de_posting_read(display, PCH_DPLL(id));
 	udelay(200);
 }
 
@@ -611,18 +617,19 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(state);
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
 
 	if (HAS_PCH_IBX(i915)) {
 		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
 		id = (enum intel_dpll_id) crtc->pipe;
-		pll = intel_get_shared_dpll_by_id(i915, id);
+		pll = intel_get_shared_dpll_by_id(display, id);
 
-		drm_dbg_kms(&i915->drm,
+		drm_dbg_kms(display->drm,
 			    "[CRTC:%d:%s] using pre-allocated %s\n",
 			    crtc->base.base.id, crtc->base.name,
 			    pll->info->name);
@@ -691,65 +698,66 @@ static const struct intel_dpll_mgr pch_pll_mgr = {
 	.compare_hw_state = ibx_compare_hw_state,
 };
 
-static void hsw_ddi_wrpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_write(i915, WRPLL_CTL(id), hw_state->wrpll);
-	intel_de_posting_read(i915, WRPLL_CTL(id));
+	intel_de_write(display, WRPLL_CTL(id), hw_state->wrpll);
+	intel_de_posting_read(display, WRPLL_CTL(id));
 	udelay(20);
 }
 
-static void hsw_ddi_spll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_enable(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 
-	intel_de_write(i915, SPLL_CTL, hw_state->spll);
-	intel_de_posting_read(i915, SPLL_CTL);
+	intel_de_write(display, SPLL_CTL, hw_state->spll);
+	intel_de_posting_read(display, SPLL_CTL);
 	udelay(20);
 }
 
-static void hsw_ddi_wrpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_wrpll_disable(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_rmw(i915, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, WRPLL_CTL(id));
+	intel_de_rmw(display, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
+	intel_de_posting_read(display, WRPLL_CTL(id));
 
 	/*
 	 * Try to set up the PCH reference clock once all DPLLs
 	 * that depend on it have been shut down.
 	 */
-	if (i915->display.dpll.pch_ssc_use & BIT(id))
-		intel_init_pch_refclk(i915);
+	if (display->dpll.pch_ssc_use & BIT(id))
+		intel_init_pch_refclk(to_i915(display->drm));
 }
 
-static void hsw_ddi_spll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_spll_disable(struct intel_display *display,
 				 struct intel_shared_dpll *pll)
 {
 	enum intel_dpll_id id = pll->info->id;
 
-	intel_de_rmw(i915, SPLL_CTL, SPLL_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, SPLL_CTL);
+	intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0);
+	intel_de_posting_read(display, SPLL_CTL);
 
 	/*
 	 * Try to set up the PCH reference clock once all DPLLs
 	 * that depend on it have been shut down.
 	 */
-	if (i915->display.dpll.pch_ssc_use & BIT(id))
-		intel_init_pch_refclk(i915);
+	if (display->dpll.pch_ssc_use & BIT(id))
+		intel_init_pch_refclk(to_i915(display->drm));
 }
 
-static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_wrpll_get_hw_state(struct intel_display *display,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 	const enum intel_dpll_id id = pll->info->id;
 	intel_wakeref_t wakeref;
@@ -760,7 +768,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, WRPLL_CTL(id));
+	val = intel_de_read(display, WRPLL_CTL(id));
 	hw_state->wrpll = val;
 
 	intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -768,10 +776,11 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915,
 	return val & WRPLL_PLL_ENABLE;
 }
 
-static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_spll_get_hw_state(struct intel_display *display,
 				      struct intel_shared_dpll *pll,
 				      struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct hsw_dpll_hw_state *hw_state = &dpll_hw_state->hsw;
 	intel_wakeref_t wakeref;
 	u32 val;
@@ -781,7 +790,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, SPLL_CTL);
+	val = intel_de_read(display, SPLL_CTL);
 	hw_state->spll = val;
 
 	intel_display_power_put(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref);
@@ -995,7 +1004,7 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */,
 	*r2_out = best.r2;
 }
 
-static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_wrpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1007,8 +1016,8 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	switch (wrpll & WRPLL_REF_MASK) {
 	case WRPLL_REF_SPECIAL_HSW:
 		/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
-		if (IS_HASWELL(i915) && !IS_HASWELL_ULT(i915)) {
-			refclk = i915->display.dpll.ref_clks.nssc;
+		if (display->platform.haswell && !display->platform.haswell_ult) {
+			refclk = display->dpll.ref_clks.nssc;
 			break;
 		}
 		fallthrough;
@@ -1018,7 +1027,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 		 * code only cares about 5% accuracy, and spread is a max of
 		 * 0.5% downspread.
 		 */
-		refclk = i915->display.dpll.ref_clks.ssc;
+		refclk = display->dpll.ref_clks.ssc;
 		break;
 	case WRPLL_REF_LCPLL:
 		refclk = 2700000;
@@ -1040,7 +1049,7 @@ static int
 hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
 			   struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct hsw_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.hsw;
@@ -1053,7 +1062,7 @@ hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
 		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
 		WRPLL_DIVIDER_POST(p);
 
-	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
+	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(display, NULL,
 							&crtc_state->dpll_hw_state);
 
 	return 0;
@@ -1093,7 +1102,7 @@ hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
 static struct intel_shared_dpll *
 hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id pll_id;
 	int clock = crtc_state->port_clock;
@@ -1113,7 +1122,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 		return NULL;
 	}
 
-	pll = intel_get_shared_dpll_by_id(i915, pll_id);
+	pll = intel_get_shared_dpll_by_id(display, pll_id);
 
 	if (!pll)
 		return NULL;
@@ -1121,7 +1130,7 @@ hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
 	return pll;
 }
 
-static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_lcpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1138,7 +1147,7 @@ static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 		link_clock = 270000;
 		break;
 	default:
-		drm_WARN(&i915->drm, 1, "bad port clock sel\n");
+		drm_WARN(display->drm, 1, "bad port clock sel\n");
 		break;
 	}
 
@@ -1173,7 +1182,7 @@ hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
 				      BIT(DPLL_ID_SPLL));
 }
 
-static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
+static int hsw_ddi_spll_get_freq(struct intel_display *display,
 				 const struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1191,7 +1200,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
 		link_clock = 270000;
 		break;
 	default:
-		drm_WARN(&i915->drm, 1, "bad spll freq\n");
+		drm_WARN(display->drm, 1, "bad spll freq\n");
 		break;
 	}
 
@@ -1284,18 +1293,18 @@ static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
 	.get_freq = hsw_ddi_spll_get_freq,
 };
 
-static void hsw_ddi_lcpll_enable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *hw_state)
 {
 }
 
-static void hsw_ddi_lcpll_disable(struct drm_i915_private *i915,
+static void hsw_ddi_lcpll_disable(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
 }
 
-static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915,
+static bool hsw_ddi_lcpll_get_hw_state(struct intel_display *display,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1363,21 +1372,21 @@ static const struct skl_dpll_regs skl_dpll_regs[4] = {
 	},
 };
 
-static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915,
+static void skl_ddi_pll_write_ctrl1(struct intel_display *display,
 				    struct intel_shared_dpll *pll,
 				    const struct skl_dpll_hw_state *hw_state)
 {
 	const enum intel_dpll_id id = pll->info->id;
 
-	intel_de_rmw(i915, DPLL_CTRL1,
+	intel_de_rmw(display, DPLL_CTRL1,
 		     DPLL_CTRL1_HDMI_MODE(id) |
 		     DPLL_CTRL1_SSC(id) |
 		     DPLL_CTRL1_LINK_RATE_MASK(id),
 		     hw_state->ctrl1 << (id * 6));
-	intel_de_posting_read(i915, DPLL_CTRL1);
+	intel_de_posting_read(display, DPLL_CTRL1);
 }
 
-static void skl_ddi_pll_enable(struct drm_i915_private *i915,
+static void skl_ddi_pll_enable(struct intel_display *display,
 			       struct intel_shared_dpll *pll,
 			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1385,49 +1394,50 @@ static void skl_ddi_pll_enable(struct drm_i915_private *i915,
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
 
-	skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+	skl_ddi_pll_write_ctrl1(display, pll, hw_state);
 
-	intel_de_write(i915, regs[id].cfgcr1, hw_state->cfgcr1);
-	intel_de_write(i915, regs[id].cfgcr2, hw_state->cfgcr2);
-	intel_de_posting_read(i915, regs[id].cfgcr1);
-	intel_de_posting_read(i915, regs[id].cfgcr2);
+	intel_de_write(display, regs[id].cfgcr1, hw_state->cfgcr1);
+	intel_de_write(display, regs[id].cfgcr2, hw_state->cfgcr2);
+	intel_de_posting_read(display, regs[id].cfgcr1);
+	intel_de_posting_read(display, regs[id].cfgcr2);
 
 	/* the enable bit is always bit 31 */
-	intel_de_rmw(i915, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
+	intel_de_rmw(display, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
 
-	if (intel_de_wait_for_set(i915, DPLL_STATUS, DPLL_LOCK(id), 5))
-		drm_err(&i915->drm, "DPLL %d not locked\n", id);
+	if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5))
+		drm_err(display->drm, "DPLL %d not locked\n", id);
 }
 
-static void skl_ddi_dpll0_enable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
 
-	skl_ddi_pll_write_ctrl1(i915, pll, hw_state);
+	skl_ddi_pll_write_ctrl1(display, pll, hw_state);
 }
 
-static void skl_ddi_pll_disable(struct drm_i915_private *i915,
+static void skl_ddi_pll_disable(struct intel_display *display,
 				struct intel_shared_dpll *pll)
 {
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
 
 	/* the enable bit is always bit 31 */
-	intel_de_rmw(i915, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, regs[id].ctl);
+	intel_de_rmw(display, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
+	intel_de_posting_read(display, regs[id].ctl);
 }
 
-static void skl_ddi_dpll0_disable(struct drm_i915_private *i915,
+static void skl_ddi_dpll0_disable(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
 }
 
-static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_pll_get_hw_state(struct intel_display *display,
 				     struct intel_shared_dpll *pll,
 				     struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
@@ -1442,17 +1452,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 
 	ret = false;
 
-	val = intel_de_read(i915, regs[id].ctl);
+	val = intel_de_read(display, regs[id].ctl);
 	if (!(val & LCPLL_PLL_ENABLE))
 		goto out;
 
-	val = intel_de_read(i915, DPLL_CTRL1);
+	val = intel_de_read(display, DPLL_CTRL1);
 	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
 
 	/* avoid reading back stale values if HDMI mode is not enabled */
 	if (val & DPLL_CTRL1_HDMI_MODE(id)) {
-		hw_state->cfgcr1 = intel_de_read(i915, regs[id].cfgcr1);
-		hw_state->cfgcr2 = intel_de_read(i915, regs[id].cfgcr2);
+		hw_state->cfgcr1 = intel_de_read(display, regs[id].cfgcr1);
+		hw_state->cfgcr2 = intel_de_read(display, regs[id].cfgcr2);
 	}
 	ret = true;
 
@@ -1462,10 +1472,11 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
+static bool skl_ddi_dpll0_get_hw_state(struct intel_display *display,
 				       struct intel_shared_dpll *pll,
 				       struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
 	const struct skl_dpll_regs *regs = skl_dpll_regs;
 	const enum intel_dpll_id id = pll->info->id;
@@ -1481,11 +1492,11 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915,
 	ret = false;
 
 	/* DPLL0 is always enabled since it drives CDCLK */
-	val = intel_de_read(i915, regs[id].ctl);
+	val = intel_de_read(display, regs[id].ctl);
 	if (drm_WARN_ON(&i915->drm, !(val & LCPLL_PLL_ENABLE)))
 		goto out;
 
-	val = intel_de_read(i915, DPLL_CTRL1);
+	val = intel_de_read(display, DPLL_CTRL1);
 	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
 
 	ret = true;
@@ -1735,12 +1746,12 @@ skl_ddi_calculate_wrpll(int clock,
 	return 0;
 }
 
-static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_wrpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct skl_dpll_hw_state *hw_state = &dpll_hw_state->skl;
-	int ref_clock = i915->display.dpll.ref_clks.nssc;
+	int ref_clock = display->dpll.ref_clks.nssc;
 	u32 p0, p1, p2, dco_freq;
 
 	p0 = hw_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1767,7 +1778,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 		 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
 		 * handling it the same way as PDIV_7.
 		 */
-		drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
+		drm_dbg_kms(display->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
 		fallthrough;
 	case DPLL_CFGCR2_PDIV_7:
 		p0 = 7;
@@ -1801,7 +1812,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 	dco_freq += ((hw_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
 		    ref_clock / 0x8000;
 
-	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+	if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
 		return 0;
 
 	return dco_freq / (p0 * p1 * p2 * 5);
@@ -1809,13 +1820,13 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
 
 static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct skl_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.skl;
 	struct skl_wrpll_params wrpll_params = {};
 	int ret;
 
 	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock,
-				      i915->display.dpll.ref_clks.nssc, &wrpll_params);
+				      display->dpll.ref_clks.nssc, &wrpll_params);
 	if (ret)
 		return ret;
 
@@ -1839,7 +1850,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
 		DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
 		wrpll_params.central_freq;
 
-	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
+	crtc_state->port_clock = skl_ddi_wrpll_get_freq(display, NULL,
 							&crtc_state->dpll_hw_state);
 
 	return 0;
@@ -1883,7 +1894,7 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
-static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_lcpll_get_freq(struct intel_display *display,
 				  const struct intel_shared_dpll *pll,
 				  const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1911,7 +1922,7 @@ static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
 		link_clock = 270000;
 		break;
 	default:
-		drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
+		drm_WARN(display->drm, 1, "Unsupported link rate\n");
 		break;
 	}
 
@@ -1962,7 +1973,7 @@ static int skl_get_dpll(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int skl_ddi_pll_get_freq(struct intel_display *display,
 				const struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -1973,9 +1984,9 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
 	 * the internal shift for each field
 	 */
 	if (hw_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
-		return skl_ddi_wrpll_get_freq(i915, pll, dpll_hw_state);
+		return skl_ddi_wrpll_get_freq(display, pll, dpll_hw_state);
 	else
-		return skl_ddi_lcpll_get_freq(i915, pll, dpll_hw_state);
+		return skl_ddi_lcpll_get_freq(display, pll, dpll_hw_state);
 }
 
 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -2037,11 +2048,10 @@ static const struct intel_dpll_mgr skl_pll_mgr = {
 	.compare_hw_state = skl_compare_hw_state,
 };
 
-static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_enable(struct intel_display *display,
 			       struct intel_shared_dpll *pll,
 			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
 	const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	enum dpio_phy phy;
@@ -2051,120 +2061,120 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
 	bxt_port_to_phy_channel(display, port, &phy, &ch);
 
 	/* Non-SSC reference */
-	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
+	intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
 
-	if (IS_GEMINILAKE(i915)) {
-		intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+	if (display->platform.geminilake) {
+		intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
 			     0, PORT_PLL_POWER_ENABLE);
 
-		if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+		if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
 				 PORT_PLL_POWER_STATE), 200))
-			drm_err(&i915->drm,
+			drm_err(display->drm,
 				"Power state not set for PLL:%d\n", port);
 	}
 
 	/* Disable 10 bit clock */
-	intel_de_rmw(i915, BXT_PORT_PLL_EBB_4(phy, ch),
+	intel_de_rmw(display, BXT_PORT_PLL_EBB_4(phy, ch),
 		     PORT_PLL_10BIT_CLK_ENABLE, 0);
 
 	/* Write P1 & P2 */
-	intel_de_rmw(i915, BXT_PORT_PLL_EBB_0(phy, ch),
+	intel_de_rmw(display, BXT_PORT_PLL_EBB_0(phy, ch),
 		     PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, hw_state->ebb0);
 
 	/* Write M2 integer */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 0),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0),
 		     PORT_PLL_M2_INT_MASK, hw_state->pll0);
 
 	/* Write N */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 1),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1),
 		     PORT_PLL_N_MASK, hw_state->pll1);
 
 	/* Write M2 fraction */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 2),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2),
 		     PORT_PLL_M2_FRAC_MASK, hw_state->pll2);
 
 	/* Write M2 fraction enable */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 3),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3),
 		     PORT_PLL_M2_FRAC_ENABLE, hw_state->pll3);
 
 	/* Write coeff */
-	temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+	temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
 	temp &= ~PORT_PLL_PROP_COEFF_MASK;
 	temp &= ~PORT_PLL_INT_COEFF_MASK;
 	temp &= ~PORT_PLL_GAIN_CTL_MASK;
 	temp |= hw_state->pll6;
-	intel_de_write(i915, BXT_PORT_PLL(phy, ch, 6), temp);
+	intel_de_write(display, BXT_PORT_PLL(phy, ch, 6), temp);
 
 	/* Write calibration val */
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 8),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8),
 		     PORT_PLL_TARGET_CNT_MASK, hw_state->pll8);
 
-	intel_de_rmw(i915, BXT_PORT_PLL(phy, ch, 9),
+	intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9),
 		     PORT_PLL_LOCK_THRESHOLD_MASK, hw_state->pll9);
 
-	temp = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+	temp = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
 	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
 	temp &= ~PORT_PLL_DCO_AMP_MASK;
 	temp |= hw_state->pll10;
-	intel_de_write(i915, BXT_PORT_PLL(phy, ch, 10), temp);
+	intel_de_write(display, BXT_PORT_PLL(phy, ch, 10), temp);
 
 	/* Recalibrate with new settings */
-	temp = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+	temp = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
 	temp |= PORT_PLL_RECALIBRATE;
-	intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+	intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
 	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
 	temp |= hw_state->ebb4;
-	intel_de_write(i915, BXT_PORT_PLL_EBB_4(phy, ch), temp);
+	intel_de_write(display, BXT_PORT_PLL_EBB_4(phy, ch), temp);
 
 	/* Enable PLL */
-	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
-	intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+	intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
+	intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
 
-	if (wait_for_us((intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
+	if (wait_for_us((intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
 			200))
-		drm_err(&i915->drm, "PLL %d not locked\n", port);
+		drm_err(display->drm, "PLL %d not locked\n", port);
 
-	if (IS_GEMINILAKE(i915)) {
-		temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
+	if (display->platform.geminilake) {
+		temp = intel_de_read(display, BXT_PORT_TX_DW5_LN(phy, ch, 0));
 		temp |= DCC_DELAY_RANGE_2;
-		intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
+		intel_de_write(display, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
 	}
 
 	/*
 	 * While we write to the group register to program all lanes at once we
 	 * can read only lane registers and we pick lanes 0/1 for that.
 	 */
-	temp = intel_de_read(i915, BXT_PORT_PCS_DW12_LN01(phy, ch));
+	temp = intel_de_read(display, BXT_PORT_PCS_DW12_LN01(phy, ch));
 	temp &= ~LANE_STAGGER_MASK;
 	temp &= ~LANESTAGGER_STRAP_OVRD;
 	temp |= hw_state->pcsdw12;
-	intel_de_write(i915, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
+	intel_de_write(display, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
 }
 
-static void bxt_ddi_pll_disable(struct drm_i915_private *i915,
+static void bxt_ddi_pll_disable(struct intel_display *display,
 				struct intel_shared_dpll *pll)
 {
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 
-	intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
-	intel_de_posting_read(i915, BXT_PORT_PLL_ENABLE(port));
+	intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
+	intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
 
-	if (IS_GEMINILAKE(i915)) {
-		intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port),
+	if (display->platform.geminilake) {
+		intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
 			     PORT_PLL_POWER_ENABLE, 0);
 
-		if (wait_for_us(!(intel_de_read(i915, BXT_PORT_PLL_ENABLE(port)) &
+		if (wait_for_us(!(intel_de_read(display, BXT_PORT_PLL_ENABLE(port)) &
 				  PORT_PLL_POWER_STATE), 200))
-			drm_err(&i915->drm,
+			drm_err(display->drm,
 				"Power state not reset for PLL:%d\n", port);
 	}
 }
 
-static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
+static bool bxt_ddi_pll_get_hw_state(struct intel_display *display,
 				     struct intel_shared_dpll *pll,
 				     struct intel_dpll_hw_state *dpll_hw_state)
 {
-	struct intel_display *display = &i915->display;
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
 	intel_wakeref_t wakeref;
@@ -2182,40 +2192,40 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 
 	ret = false;
 
-	val = intel_de_read(i915, BXT_PORT_PLL_ENABLE(port));
+	val = intel_de_read(display, BXT_PORT_PLL_ENABLE(port));
 	if (!(val & PORT_PLL_ENABLE))
 		goto out;
 
-	hw_state->ebb0 = intel_de_read(i915, BXT_PORT_PLL_EBB_0(phy, ch));
+	hw_state->ebb0 = intel_de_read(display, BXT_PORT_PLL_EBB_0(phy, ch));
 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
 
-	hw_state->ebb4 = intel_de_read(i915, BXT_PORT_PLL_EBB_4(phy, ch));
+	hw_state->ebb4 = intel_de_read(display, BXT_PORT_PLL_EBB_4(phy, ch));
 	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
 
-	hw_state->pll0 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 0));
+	hw_state->pll0 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 0));
 	hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
 
-	hw_state->pll1 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 1));
+	hw_state->pll1 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 1));
 	hw_state->pll1 &= PORT_PLL_N_MASK;
 
-	hw_state->pll2 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 2));
+	hw_state->pll2 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 2));
 	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
 
-	hw_state->pll3 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 3));
+	hw_state->pll3 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 3));
 	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
 
-	hw_state->pll6 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 6));
+	hw_state->pll6 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 6));
 	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
 			  PORT_PLL_INT_COEFF_MASK |
 			  PORT_PLL_GAIN_CTL_MASK;
 
-	hw_state->pll8 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 8));
+	hw_state->pll8 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 8));
 	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
 
-	hw_state->pll9 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 9));
+	hw_state->pll9 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 9));
 	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
 
-	hw_state->pll10 = intel_de_read(i915, BXT_PORT_PLL(phy, ch, 10));
+	hw_state->pll10 = intel_de_read(display, BXT_PORT_PLL(phy, ch, 10));
 	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
 			   PORT_PLL_DCO_AMP_MASK;
 
@@ -2224,13 +2234,13 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
 	 * can read only lane registers. We configure all lanes the same way, so
 	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
 	 */
-	hw_state->pcsdw12 = intel_de_read(i915,
+	hw_state->pcsdw12 = intel_de_read(display,
 					  BXT_PORT_PCS_DW12_LN01(phy, ch));
-	if (intel_de_read(i915, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
-		drm_dbg(&i915->drm,
+	if (intel_de_read(display, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
+		drm_dbg(display->drm,
 			"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
 			hw_state->pcsdw12,
-			intel_de_read(i915,
+			intel_de_read(display,
 				      BXT_PORT_PCS_DW12_LN23(phy, ch)));
 	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
 
@@ -2361,7 +2371,7 @@ static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
+static int bxt_ddi_pll_get_freq(struct intel_display *display,
 				const struct intel_shared_dpll *pll,
 				const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -2377,7 +2387,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
 	clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, hw_state->ebb0);
 	clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, hw_state->ebb0);
 
-	return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
+	return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);
 }
 
 static int
@@ -2393,7 +2403,7 @@ bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 static int
 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct dpll clk_div = {};
 	int ret;
 
@@ -2403,7 +2413,7 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
 	if (ret)
 		return ret;
 
-	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
+	crtc_state->port_clock = bxt_ddi_pll_get_freq(display, NULL,
 						      &crtc_state->dpll_hw_state);
 
 	return 0;
@@ -2428,17 +2438,17 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
 			struct intel_crtc *crtc,
 			struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum intel_dpll_id id;
 
 	/* 1:1 mapping between ports and PLLs */
 	id = (enum intel_dpll_id) encoder->port;
-	pll = intel_get_shared_dpll_by_id(i915, id);
+	pll = intel_get_shared_dpll_by_id(display, id);
 
-	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
+	drm_dbg_kms(display->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
 		    crtc->base.base.id, crtc->base.name, pll->info->name);
 
 	intel_reference_shared_dpll(state, crtc,
@@ -2604,12 +2614,14 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
  * Program half of the nominal DCO divider fraction value.
  */
 static bool
-ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
+ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
 {
-	return ((IS_ELKHARTLAKE(i915) &&
-		 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
-		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
-		 i915->display.dpll.ref_clks.nssc == 38400;
+	return ((display->platform.elkhartlake &&
+		 IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) ||
+		 display->platform.tigerlake ||
+		 display->platform.alderlake_s ||
+		 display->platform.alderlake_p) &&
+		 display->dpll.ref_clks.nssc == 38400;
 }
 
 struct icl_combo_pll_params {
@@ -2756,7 +2768,7 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_tbt_pll_get_freq(struct intel_display *display,
 				    const struct intel_shared_dpll *pll,
 				    const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -2764,14 +2776,14 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
 	 * The PLL outputs multiple frequencies at the same time, selection is
 	 * made at DDI clock mux level.
 	 */
-	drm_WARN_ON(&i915->drm, 1);
+	drm_WARN_ON(display->drm, 1);
 
 	return 0;
 }
 
-static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
+static int icl_wrpll_ref_clock(struct intel_display *display)
 {
-	int ref_clock = i915->display.dpll.ref_clks.nssc;
+	int ref_clock = display->dpll.ref_clks.nssc;
 
 	/*
 	 * For ICL+, the spec states: if reference frequency is 38.4,
@@ -2787,8 +2799,8 @@ static int
 icl_calc_wrpll(struct intel_crtc_state *crtc_state,
 	       struct skl_wrpll_params *wrpll_params)
 {
-	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
-	int ref_clock = icl_wrpll_ref_clock(i915);
+	struct intel_display *display = to_intel_display(crtc_state);
+	int ref_clock = icl_wrpll_ref_clock(display);
 	u32 afe_clock = crtc_state->port_clock * 5;
 	u32 dco_min = 7998000;
 	u32 dco_max = 10000000;
@@ -2827,12 +2839,12 @@ icl_calc_wrpll(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_combo_pll_get_freq(struct intel_display *display,
 				      const struct intel_shared_dpll *pll,
 				      const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	int ref_clock = icl_wrpll_ref_clock(i915);
+	int ref_clock = icl_wrpll_ref_clock(display);
 	u32 dco_fraction;
 	u32 p0, p1, p2, dco_freq;
 
@@ -2878,25 +2890,25 @@ static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
 	dco_fraction = (hw_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
 		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
 
-	if (ehl_combo_pll_div_frac_wa_needed(i915))
+	if (ehl_combo_pll_div_frac_wa_needed(display))
 		dco_fraction *= 2;
 
 	dco_freq += (dco_fraction * ref_clock) / 0x8000;
 
-	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
+	if (drm_WARN_ON(display->drm, p0 == 0 || p1 == 0 || p2 == 0))
 		return 0;
 
 	return dco_freq / (p0 * p1 * p2 * 5);
 }
 
-static void icl_calc_dpll_state(struct drm_i915_private *i915,
+static void icl_calc_dpll_state(struct intel_display *display,
 				const struct skl_wrpll_params *pll_params,
 				struct intel_dpll_hw_state *dpll_hw_state)
 {
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	u32 dco_fraction = pll_params->dco_fraction;
 
-	if (ehl_combo_pll_div_frac_wa_needed(i915))
+	if (ehl_combo_pll_div_frac_wa_needed(display))
 		dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
 
 	hw_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
@@ -2907,13 +2919,13 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
 			    DPLL_CFGCR1_KDIV(pll_params->kdiv) |
 			    DPLL_CFGCR1_PDIV(pll_params->pdiv);
 
-	if (DISPLAY_VER(i915) >= 12)
+	if (DISPLAY_VER(display) >= 12)
 		hw_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
 	else
 		hw_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
 
-	if (i915->display.vbt.override_afc_startup)
-		hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
+	if (display->vbt.override_afc_startup)
+		hw_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(display->vbt.override_afc_startup_val);
 }
 
 static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -3200,7 +3212,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
 	return 0;
 }
 
-static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
+static int icl_ddi_mg_pll_get_freq(struct intel_display *display,
 				   const struct intel_shared_dpll *pll,
 				   const struct intel_dpll_hw_state *dpll_hw_state)
 {
@@ -3208,9 +3220,9 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915,
 	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
 	u64 tmp;
 
-	ref_clock = i915->display.dpll.ref_clks.nssc;
+	ref_clock = display->dpll.ref_clks.nssc;
 
-	if (DISPLAY_VER(i915) >= 12) {
+	if (DISPLAY_VER(display) >= 12) {
 		m1 = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
 		m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
 		m2_int = hw_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
@@ -3315,7 +3327,7 @@ static void icl_update_active_dpll(struct intel_atomic_state *state,
 static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct icl_port_dpll *port_dpll =
@@ -3332,12 +3344,12 @@ static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+	icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
 
 	/* this is mainly for the fastset check */
 	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
 
-	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(i915, NULL,
+	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(display, NULL,
 							    &port_dpll->hw_state);
 
 	return 0;
@@ -3407,7 +3419,7 @@ static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
 static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct intel_crtc_state *old_crtc_state =
@@ -3422,7 +3434,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	icl_calc_dpll_state(i915, &pll_params, &port_dpll->hw_state);
+	icl_calc_dpll_state(display, &pll_params, &port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
@@ -3436,7 +3448,7 @@ static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	else
 		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
 
-	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(i915, NULL,
+	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(display, NULL,
 							 &port_dpll->hw_state);
 
 	return 0;
@@ -3540,10 +3552,11 @@ static void icl_put_dplls(struct intel_atomic_state *state,
 	}
 }
 
-static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
+static bool mg_pll_get_hw_state(struct intel_display *display,
 				struct intel_shared_dpll *pll,
 				struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3551,18 +3564,18 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
 	bool ret = false;
 	u32 val;
 
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
 	wakeref = intel_display_power_get_if_enabled(i915,
 						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, enable_reg);
+	val = intel_de_read(display, enable_reg);
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	hw_state->mg_refclkin_ctl = intel_de_read(i915,
+	hw_state->mg_refclkin_ctl = intel_de_read(display,
 						  MG_REFCLKIN_CTL(tc_port));
 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
 
@@ -3572,23 +3585,23 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
 		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
 
 	hw_state->mg_clktop2_hsclkctl =
-		intel_de_read(i915, MG_CLKTOP2_HSCLKCTL(tc_port));
+		intel_de_read(display, MG_CLKTOP2_HSCLKCTL(tc_port));
 	hw_state->mg_clktop2_hsclkctl &=
 		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
 		MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
 
-	hw_state->mg_pll_div0 = intel_de_read(i915, MG_PLL_DIV0(tc_port));
-	hw_state->mg_pll_div1 = intel_de_read(i915, MG_PLL_DIV1(tc_port));
-	hw_state->mg_pll_lf = intel_de_read(i915, MG_PLL_LF(tc_port));
-	hw_state->mg_pll_frac_lock = intel_de_read(i915,
+	hw_state->mg_pll_div0 = intel_de_read(display, MG_PLL_DIV0(tc_port));
+	hw_state->mg_pll_div1 = intel_de_read(display, MG_PLL_DIV1(tc_port));
+	hw_state->mg_pll_lf = intel_de_read(display, MG_PLL_LF(tc_port));
+	hw_state->mg_pll_frac_lock = intel_de_read(display,
 						   MG_PLL_FRAC_LOCK(tc_port));
-	hw_state->mg_pll_ssc = intel_de_read(i915, MG_PLL_SSC(tc_port));
+	hw_state->mg_pll_ssc = intel_de_read(display, MG_PLL_SSC(tc_port));
 
-	hw_state->mg_pll_bias = intel_de_read(i915, MG_PLL_BIAS(tc_port));
+	hw_state->mg_pll_bias = intel_de_read(display, MG_PLL_BIAS(tc_port));
 	hw_state->mg_pll_tdc_coldst_bias =
-		intel_de_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+		intel_de_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
 
 	if (i915->display.dpll.ref_clks.nssc == 38400) {
 		hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
@@ -3607,10 +3620,11 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool dkl_pll_get_hw_state(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
@@ -3623,7 +3637,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, intel_tc_pll_enable_reg(i915, pll));
+	val = intel_de_read(display, intel_tc_pll_enable_reg(display, pll));
 	if (!(val & PLL_ENABLE))
 		goto out;
 
@@ -3631,12 +3645,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 	 * All registers read here have the same HIP_INDEX_REG even though
 	 * they are on different building blocks
 	 */
-	hw_state->mg_refclkin_ctl = intel_dkl_phy_read(i915,
+	hw_state->mg_refclkin_ctl = intel_dkl_phy_read(display,
 						       DKL_REFCLKIN_CTL(tc_port));
 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
 
 	hw_state->mg_clktop2_hsclkctl =
-		intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+		intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
 	hw_state->mg_clktop2_hsclkctl &=
 		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
@@ -3644,32 +3658,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
 
 	hw_state->mg_clktop2_coreclkctl1 =
-		intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+		intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
 	hw_state->mg_clktop2_coreclkctl1 &=
 		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
 
-	hw_state->mg_pll_div0 = intel_dkl_phy_read(i915, DKL_PLL_DIV0(tc_port));
+	hw_state->mg_pll_div0 = intel_dkl_phy_read(display, DKL_PLL_DIV0(tc_port));
 	val = DKL_PLL_DIV0_MASK;
-	if (i915->display.vbt.override_afc_startup)
+	if (display->vbt.override_afc_startup)
 		val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
 	hw_state->mg_pll_div0 &= val;
 
-	hw_state->mg_pll_div1 = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+	hw_state->mg_pll_div1 = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
 	hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
 				  DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
 
-	hw_state->mg_pll_ssc = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+	hw_state->mg_pll_ssc = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
 	hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
 				 DKL_PLL_SSC_STEP_LEN_MASK |
 				 DKL_PLL_SSC_STEP_NUM_MASK |
 				 DKL_PLL_SSC_EN);
 
-	hw_state->mg_pll_bias = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+	hw_state->mg_pll_bias = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
 	hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
 				  DKL_PLL_BIAS_FBDIV_FRAC_MASK);
 
 	hw_state->mg_pll_tdc_coldst_bias =
-		intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+		intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
 	hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
 					     DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
 
@@ -3679,11 +3693,12 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
+static bool icl_pll_get_hw_state(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state,
 				 i915_reg_t enable_reg)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 	const enum intel_dpll_id id = pll->info->id;
 	intel_wakeref_t wakeref;
@@ -3695,41 +3710,41 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(i915, enable_reg);
+	val = intel_de_read(display, enable_reg);
 	if (!(val & PLL_ENABLE))
 		goto out;
 
-	if (IS_ALDERLAKE_S(i915)) {
-		hw_state->cfgcr0 = intel_de_read(i915, ADLS_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915, ADLS_DPLL_CFGCR1(id));
-	} else if (IS_DG1(i915)) {
-		hw_state->cfgcr0 = intel_de_read(i915, DG1_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915, DG1_DPLL_CFGCR1(id));
-	} else if (IS_ROCKETLAKE(i915)) {
-		hw_state->cfgcr0 = intel_de_read(i915,
+	if (display->platform.alderlake_s) {
+		hw_state->cfgcr0 = intel_de_read(display, ADLS_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(display, ADLS_DPLL_CFGCR1(id));
+	} else if (display->platform.dg1) {
+		hw_state->cfgcr0 = intel_de_read(display, DG1_DPLL_CFGCR0(id));
+		hw_state->cfgcr1 = intel_de_read(display, DG1_DPLL_CFGCR1(id));
+	} else if (display->platform.rocketlake) {
+		hw_state->cfgcr0 = intel_de_read(display,
 						 RKL_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915,
+		hw_state->cfgcr1 = intel_de_read(display,
 						 RKL_DPLL_CFGCR1(id));
-	} else if (DISPLAY_VER(i915) >= 12) {
-		hw_state->cfgcr0 = intel_de_read(i915,
+	} else if (DISPLAY_VER(display) >= 12) {
+		hw_state->cfgcr0 = intel_de_read(display,
 						 TGL_DPLL_CFGCR0(id));
-		hw_state->cfgcr1 = intel_de_read(i915,
+		hw_state->cfgcr1 = intel_de_read(display,
 						 TGL_DPLL_CFGCR1(id));
 		if (i915->display.vbt.override_afc_startup) {
-			hw_state->div0 = intel_de_read(i915, TGL_DPLL0_DIV0(id));
+			hw_state->div0 = intel_de_read(display, TGL_DPLL0_DIV0(id));
 			hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
 		}
 	} else {
-		if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+		if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		    id == DPLL_ID_EHL_DPLL4) {
-			hw_state->cfgcr0 = intel_de_read(i915,
+			hw_state->cfgcr0 = intel_de_read(display,
 							 ICL_DPLL_CFGCR0(4));
-			hw_state->cfgcr1 = intel_de_read(i915,
+			hw_state->cfgcr1 = intel_de_read(display,
 							 ICL_DPLL_CFGCR1(4));
 		} else {
-			hw_state->cfgcr0 = intel_de_read(i915,
+			hw_state->cfgcr0 = intel_de_read(display,
 							 ICL_DPLL_CFGCR0(id));
-			hw_state->cfgcr1 = intel_de_read(i915,
+			hw_state->cfgcr1 = intel_de_read(display,
 							 ICL_DPLL_CFGCR1(id));
 		}
 	}
@@ -3740,44 +3755,44 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *i915,
 	return ret;
 }
 
-static bool combo_pll_get_hw_state(struct drm_i915_private *i915,
+static bool combo_pll_get_hw_state(struct intel_display *display,
 				   struct intel_shared_dpll *pll,
 				   struct intel_dpll_hw_state *dpll_hw_state)
 {
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
-	return icl_pll_get_hw_state(i915, pll, dpll_hw_state, enable_reg);
+	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
 }
 
-static bool tbt_pll_get_hw_state(struct drm_i915_private *i915,
+static bool tbt_pll_get_hw_state(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 struct intel_dpll_hw_state *dpll_hw_state)
 {
-	return icl_pll_get_hw_state(i915, pll, dpll_hw_state, TBT_PLL_ENABLE);
+	return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
 }
 
-static void icl_dpll_write(struct drm_i915_private *i915,
+static void icl_dpll_write(struct intel_display *display,
 			   struct intel_shared_dpll *pll,
 			   const struct icl_dpll_hw_state *hw_state)
 {
 	const enum intel_dpll_id id = pll->info->id;
 	i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
 
-	if (IS_ALDERLAKE_S(i915)) {
+	if (display->platform.alderlake_s) {
 		cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
 		cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
-	} else if (IS_DG1(i915)) {
+	} else if (display->platform.dg1) {
 		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
 		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
-	} else if (IS_ROCKETLAKE(i915)) {
+	} else if (display->platform.rocketlake) {
 		cfgcr0_reg = RKL_DPLL_CFGCR0(id);
 		cfgcr1_reg = RKL_DPLL_CFGCR1(id);
-	} else if (DISPLAY_VER(i915) >= 12) {
+	} else if (DISPLAY_VER(display) >= 12) {
 		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
 		div0_reg = TGL_DPLL0_DIV0(id);
 	} else {
-		if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
+		if ((display->platform.jasperlake || display->platform.elkhartlake) &&
 		    id == DPLL_ID_EHL_DPLL4) {
 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
@@ -3787,18 +3802,18 @@ static void icl_dpll_write(struct drm_i915_private *i915,
 		}
 	}
 
-	intel_de_write(i915, cfgcr0_reg, hw_state->cfgcr0);
-	intel_de_write(i915, cfgcr1_reg, hw_state->cfgcr1);
-	drm_WARN_ON_ONCE(&i915->drm, i915->display.vbt.override_afc_startup &&
+	intel_de_write(display, cfgcr0_reg, hw_state->cfgcr0);
+	intel_de_write(display, cfgcr1_reg, hw_state->cfgcr1);
+	drm_WARN_ON_ONCE(display->drm, display->vbt.override_afc_startup &&
 			 !i915_mmio_reg_valid(div0_reg));
-	if (i915->display.vbt.override_afc_startup &&
+	if (display->vbt.override_afc_startup &&
 	    i915_mmio_reg_valid(div0_reg))
-		intel_de_rmw(i915, div0_reg,
+		intel_de_rmw(display, div0_reg,
 			     TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
-	intel_de_posting_read(i915, cfgcr1_reg);
+	intel_de_posting_read(display, cfgcr1_reg);
 }
 
-static void icl_mg_pll_write(struct drm_i915_private *i915,
+static void icl_mg_pll_write(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     const struct icl_dpll_hw_state *hw_state)
 {
@@ -3810,38 +3825,38 @@ static void icl_mg_pll_write(struct drm_i915_private *i915,
 	 * during the calc/readout phase if the mask depends on some other HW
 	 * state like refclk, see icl_calc_mg_pll_state().
 	 */
-	intel_de_rmw(i915, MG_REFCLKIN_CTL(tc_port),
+	intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port),
 		     MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
 
-	intel_de_rmw(i915, MG_CLKTOP2_CORECLKCTL1(tc_port),
+	intel_de_rmw(display, MG_CLKTOP2_CORECLKCTL1(tc_port),
 		     MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
 		     hw_state->mg_clktop2_coreclkctl1);
 
-	intel_de_rmw(i915, MG_CLKTOP2_HSCLKCTL(tc_port),
+	intel_de_rmw(display, MG_CLKTOP2_HSCLKCTL(tc_port),
 		     MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		     MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
 		     MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
 		     MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
 		     hw_state->mg_clktop2_hsclkctl);
 
-	intel_de_write(i915, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
-	intel_de_write(i915, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
-	intel_de_write(i915, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
-	intel_de_write(i915, MG_PLL_FRAC_LOCK(tc_port),
+	intel_de_write(display, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
+	intel_de_write(display, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
+	intel_de_write(display, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
+	intel_de_write(display, MG_PLL_FRAC_LOCK(tc_port),
 		       hw_state->mg_pll_frac_lock);
-	intel_de_write(i915, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
+	intel_de_write(display, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
 
-	intel_de_rmw(i915, MG_PLL_BIAS(tc_port),
+	intel_de_rmw(display, MG_PLL_BIAS(tc_port),
 		     hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
 
-	intel_de_rmw(i915, MG_PLL_TDC_COLDST_BIAS(tc_port),
+	intel_de_rmw(display, MG_PLL_TDC_COLDST_BIAS(tc_port),
 		     hw_state->mg_pll_tdc_coldst_bias_mask,
 		     hw_state->mg_pll_tdc_coldst_bias);
 
-	intel_de_posting_read(i915, MG_PLL_TDC_COLDST_BIAS(tc_port));
+	intel_de_posting_read(display, MG_PLL_TDC_COLDST_BIAS(tc_port));
 }
 
-static void dkl_pll_write(struct drm_i915_private *i915,
+static void dkl_pll_write(struct intel_display *display,
 			  struct intel_shared_dpll *pll,
 			  const struct icl_dpll_hw_state *hw_state)
 {
@@ -3853,90 +3868,90 @@ static void dkl_pll_write(struct drm_i915_private *i915,
 	 * though on different building block
 	 */
 	/* All the registers are RMW */
-	val = intel_dkl_phy_read(i915, DKL_REFCLKIN_CTL(tc_port));
+	val = intel_dkl_phy_read(display, DKL_REFCLKIN_CTL(tc_port));
 	val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
 	val |= hw_state->mg_refclkin_ctl;
-	intel_dkl_phy_write(i915, DKL_REFCLKIN_CTL(tc_port), val);
+	intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port));
+	val = intel_dkl_phy_read(display, DKL_CLKTOP2_CORECLKCTL1(tc_port));
 	val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
 	val |= hw_state->mg_clktop2_coreclkctl1;
-	intel_dkl_phy_write(i915, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
+	intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_CLKTOP2_HSCLKCTL(tc_port));
+	val = intel_dkl_phy_read(display, DKL_CLKTOP2_HSCLKCTL(tc_port));
 	val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
 		 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
 		 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
 		 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
 	val |= hw_state->mg_clktop2_hsclkctl;
-	intel_dkl_phy_write(i915, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
+	intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
 
 	val = DKL_PLL_DIV0_MASK;
-	if (i915->display.vbt.override_afc_startup)
+	if (display->vbt.override_afc_startup)
 		val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
-	intel_dkl_phy_rmw(i915, DKL_PLL_DIV0(tc_port), val,
+	intel_dkl_phy_rmw(display, DKL_PLL_DIV0(tc_port), val,
 			  hw_state->mg_pll_div0);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_DIV1(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_DIV1(tc_port));
 	val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
 		 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
 	val |= hw_state->mg_pll_div1;
-	intel_dkl_phy_write(i915, DKL_PLL_DIV1(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_SSC(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_SSC(tc_port));
 	val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
 		 DKL_PLL_SSC_STEP_LEN_MASK |
 		 DKL_PLL_SSC_STEP_NUM_MASK |
 		 DKL_PLL_SSC_EN);
 	val |= hw_state->mg_pll_ssc;
-	intel_dkl_phy_write(i915, DKL_PLL_SSC(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_BIAS(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_BIAS(tc_port));
 	val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
 		 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
 	val |= hw_state->mg_pll_bias;
-	intel_dkl_phy_write(i915, DKL_PLL_BIAS(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val);
 
-	val = intel_dkl_phy_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+	val = intel_dkl_phy_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
 	val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
 		 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
 	val |= hw_state->mg_pll_tdc_coldst_bias;
-	intel_dkl_phy_write(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
+	intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
 
-	intel_dkl_phy_posting_read(i915, DKL_PLL_TDC_COLDST_BIAS(tc_port));
+	intel_dkl_phy_posting_read(display, DKL_PLL_TDC_COLDST_BIAS(tc_port));
 }
 
-static void icl_pll_power_enable(struct drm_i915_private *i915,
+static void icl_pll_power_enable(struct intel_display *display,
 				 struct intel_shared_dpll *pll,
 				 i915_reg_t enable_reg)
 {
-	intel_de_rmw(i915, enable_reg, 0, PLL_POWER_ENABLE);
+	intel_de_rmw(display, enable_reg, 0, PLL_POWER_ENABLE);
 
 	/*
 	 * The spec says we need to "wait" but it also says it should be
 	 * immediate.
 	 */
-	if (intel_de_wait_for_set(i915, enable_reg, PLL_POWER_STATE, 1))
-		drm_err(&i915->drm, "PLL %d Power not enabled\n",
+	if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1))
+		drm_err(display->drm, "PLL %d Power not enabled\n",
 			pll->info->id);
 }
 
-static void icl_pll_enable(struct drm_i915_private *i915,
+static void icl_pll_enable(struct intel_display *display,
 			   struct intel_shared_dpll *pll,
 			   i915_reg_t enable_reg)
 {
-	intel_de_rmw(i915, enable_reg, 0, PLL_ENABLE);
+	intel_de_rmw(display, enable_reg, 0, PLL_ENABLE);
 
 	/* Timeout is actually 600us. */
-	if (intel_de_wait_for_set(i915, enable_reg, PLL_LOCK, 1))
-		drm_err(&i915->drm, "PLL %d not locked\n", pll->info->id);
+	if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1))
+		drm_err(display->drm, "PLL %d not locked\n", pll->info->id);
 }
 
-static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
+static void adlp_cmtg_clock_gating_wa(struct intel_display *display, struct intel_shared_dpll *pll)
 {
 	u32 val;
 
-	if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
+	if (!(display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) ||
 	    pll->info->id != DPLL_ID_ICL_DPLL0)
 		return;
 	/*
@@ -3950,22 +3965,22 @@ static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct inte
 	 * Instead of the usual place for workarounds we apply this one here,
 	 * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
 	 */
-	val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
-	val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
-	if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
-		drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
+	val = intel_de_read(display, TRANS_CMTG_CHICKEN);
+	val = intel_de_rmw(display, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
+	if (drm_WARN_ON(display->drm, val & ~DISABLE_DPT_CLK_GATING))
+		drm_dbg_kms(display->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
 }
 
-static void combo_pll_enable(struct drm_i915_private *i915,
+static void combo_pll_enable(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
-	icl_pll_power_enable(i915, pll, enable_reg);
+	icl_pll_power_enable(display, pll, enable_reg);
 
-	icl_dpll_write(i915, pll, hw_state);
+	icl_dpll_write(display, pll, hw_state);
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3973,22 +3988,22 @@ static void combo_pll_enable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	icl_pll_enable(i915, pll, enable_reg);
+	icl_pll_enable(display, pll, enable_reg);
 
-	adlp_cmtg_clock_gating_wa(i915, pll);
+	adlp_cmtg_clock_gating_wa(display, pll);
 
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void tbt_pll_enable(struct drm_i915_private *i915,
+static void tbt_pll_enable(struct intel_display *display,
 			   struct intel_shared_dpll *pll,
 			   const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 
-	icl_pll_power_enable(i915, pll, TBT_PLL_ENABLE);
+	icl_pll_power_enable(display, pll, TBT_PLL_ENABLE);
 
-	icl_dpll_write(i915, pll, hw_state);
+	icl_dpll_write(display, pll, hw_state);
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
@@ -3996,24 +4011,24 @@ static void tbt_pll_enable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	icl_pll_enable(i915, pll, TBT_PLL_ENABLE);
+	icl_pll_enable(display, pll, TBT_PLL_ENABLE);
 
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void mg_pll_enable(struct drm_i915_private *i915,
+static void mg_pll_enable(struct intel_display *display,
 			  struct intel_shared_dpll *pll,
 			  const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
-	icl_pll_power_enable(i915, pll, enable_reg);
+	icl_pll_power_enable(display, pll, enable_reg);
 
-	if (DISPLAY_VER(i915) >= 12)
-		dkl_pll_write(i915, pll, hw_state);
+	if (DISPLAY_VER(display) >= 12)
+		dkl_pll_write(display, pll, hw_state);
 	else
-		icl_mg_pll_write(i915, pll, hw_state);
+		icl_mg_pll_write(display, pll, hw_state);
 
 	/*
 	 * DVFS pre sequence would be here, but in our driver the cdclk code
@@ -4021,12 +4036,12 @@ static void mg_pll_enable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	icl_pll_enable(i915, pll, enable_reg);
+	icl_pll_enable(display, pll, enable_reg);
 
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void icl_pll_disable(struct drm_i915_private *i915,
+static void icl_pll_disable(struct intel_display *display,
 			    struct intel_shared_dpll *pll,
 			    i915_reg_t enable_reg)
 {
@@ -4038,45 +4053,45 @@ static void icl_pll_disable(struct drm_i915_private *i915,
 	 * nothing here.
 	 */
 
-	intel_de_rmw(i915, enable_reg, PLL_ENABLE, 0);
+	intel_de_rmw(display, enable_reg, PLL_ENABLE, 0);
 
 	/* Timeout is actually 1us. */
-	if (intel_de_wait_for_clear(i915, enable_reg, PLL_LOCK, 1))
-		drm_err(&i915->drm, "PLL %d locked\n", pll->info->id);
+	if (intel_de_wait_for_clear(display, enable_reg, PLL_LOCK, 1))
+		drm_err(display->drm, "PLL %d locked\n", pll->info->id);
 
 	/* DVFS post sequence would be here. See the comment above. */
 
-	intel_de_rmw(i915, enable_reg, PLL_POWER_ENABLE, 0);
+	intel_de_rmw(display, enable_reg, PLL_POWER_ENABLE, 0);
 
 	/*
 	 * The spec says we need to "wait" but it also says it should be
 	 * immediate.
 	 */
-	if (intel_de_wait_for_clear(i915, enable_reg, PLL_POWER_STATE, 1))
-		drm_err(&i915->drm, "PLL %d Power not disabled\n",
+	if (intel_de_wait_for_clear(display, enable_reg, PLL_POWER_STATE, 1))
+		drm_err(display->drm, "PLL %d Power not disabled\n",
 			pll->info->id);
 }
 
-static void combo_pll_disable(struct drm_i915_private *i915,
+static void combo_pll_disable(struct intel_display *display,
 			      struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg = intel_combo_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_combo_pll_enable_reg(display, pll);
 
-	icl_pll_disable(i915, pll, enable_reg);
+	icl_pll_disable(display, pll, enable_reg);
 }
 
-static void tbt_pll_disable(struct drm_i915_private *i915,
+static void tbt_pll_disable(struct intel_display *display,
 			    struct intel_shared_dpll *pll)
 {
-	icl_pll_disable(i915, pll, TBT_PLL_ENABLE);
+	icl_pll_disable(display, pll, TBT_PLL_ENABLE);
 }
 
-static void mg_pll_disable(struct drm_i915_private *i915,
+static void mg_pll_disable(struct intel_display *display,
 			   struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg = intel_tc_pll_enable_reg(i915, pll);
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(display, pll);
 
-	icl_pll_disable(i915, pll, enable_reg);
+	icl_pll_disable(display, pll, enable_reg);
 }
 
 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
@@ -4477,49 +4492,50 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
 
 /**
  * intel_dpll_get_freq - calculate the DPLL's output frequency
- * @i915: i915 device
+ * @display: intel_display device
  * @pll: DPLL for which to calculate the output frequency
  * @dpll_hw_state: DPLL state from which to calculate the output frequency
  *
  * Return the output frequency corresponding to @pll's passed in @dpll_hw_state.
  */
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
 			const struct intel_shared_dpll *pll,
 			const struct intel_dpll_hw_state *dpll_hw_state)
 {
-	if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
+	if (drm_WARN_ON(display->drm, !pll->info->funcs->get_freq))
 		return 0;
 
-	return pll->info->funcs->get_freq(i915, pll, dpll_hw_state);
+	return pll->info->funcs->get_freq(display, pll, dpll_hw_state);
 }
 
 /**
  * intel_dpll_get_hw_state - readout the DPLL's hardware state
- * @i915: i915 device
+ * @display: intel_display device instance
  * @pll: DPLL for which to calculate the output frequency
  * @dpll_hw_state: DPLL's hardware state
  *
  * Read out @pll's hardware state into @dpll_hw_state.
  */
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *dpll_hw_state)
 {
-	return pll->info->funcs->get_hw_state(i915, pll, dpll_hw_state);
+	return pll->info->funcs->get_hw_state(display, pll, dpll_hw_state);
 }
 
-static void readout_dpll_hw_state(struct drm_i915_private *i915,
+static void readout_dpll_hw_state(struct intel_display *display,
 				  struct intel_shared_dpll *pll)
 {
+	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_crtc *crtc;
 
-	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
+	pll->on = intel_dpll_get_hw_state(display, pll, &pll->state.hw_state);
 
 	if (pll->on && pll->info->power_domain)
 		pll->wakeref = intel_display_power_get(i915, pll->info->power_domain);
 
 	pll->state.pipe_mask = 0;
-	for_each_intel_crtc(&i915->drm, crtc) {
+	for_each_intel_crtc(display->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 
@@ -4528,7 +4544,7 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
 	}
 	pll->active_mask = pll->state.pipe_mask;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "%s hw state readout: pipe_mask 0x%x, on %i\n",
 		    pll->info->name, pll->state.pipe_mask, pll->on);
 }
@@ -4539,42 +4555,40 @@ void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
 		i915->display.dpll.mgr->update_ref_clks(i915);
 }
 
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
+void intel_dpll_readout_hw_state(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
 	for_each_shared_dpll(display, pll, i)
-		readout_dpll_hw_state(i915, pll);
+		readout_dpll_hw_state(display, pll);
 }
 
-static void sanitize_dpll_state(struct drm_i915_private *i915,
+static void sanitize_dpll_state(struct intel_display *display,
 				struct intel_shared_dpll *pll)
 {
 	if (!pll->on)
 		return;
 
-	adlp_cmtg_clock_gating_wa(i915, pll);
+	adlp_cmtg_clock_gating_wa(display, pll);
 
 	if (pll->active_mask)
 		return;
 
-	drm_dbg_kms(&i915->drm,
+	drm_dbg_kms(display->drm,
 		    "%s enabled but not in use, disabling\n",
 		    pll->info->name);
 
-	_intel_disable_shared_dpll(i915, pll);
+	_intel_disable_shared_dpll(display, pll);
 }
 
-void intel_dpll_sanitize_state(struct drm_i915_private *i915)
+void intel_dpll_sanitize_state(struct intel_display *display)
 {
-	struct intel_display *display = to_intel_display(&i915->drm);
 	struct intel_shared_dpll *pll;
 	int i;
 
 	for_each_shared_dpll(display, pll, i)
-		sanitize_dpll_state(i915, pll);
+		sanitize_dpll_state(display, pll);
 }
 
 /**
@@ -4624,17 +4638,16 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
 }
 
 static void
-verify_single_dpll_state(struct drm_i915_private *i915,
+verify_single_dpll_state(struct intel_display *display,
 			 struct intel_shared_dpll *pll,
 			 struct intel_crtc *crtc,
 			 const struct intel_crtc_state *new_crtc_state)
 {
-	struct intel_display *display = &i915->display;
 	struct intel_dpll_hw_state dpll_hw_state = {};
 	u8 pipe_mask;
 	bool active;
 
-	active = intel_dpll_get_hw_state(i915, pll, &dpll_hw_state);
+	active = intel_dpll_get_hw_state(display, pll, &dpll_hw_state);
 
 	if (!pll->info->always_on) {
 		INTEL_DISPLAY_STATE_WARN(display, !pll->on && pll->active_mask,
@@ -4690,14 +4703,13 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	const struct intel_crtc_state *old_crtc_state =
 		intel_atomic_get_old_crtc_state(state, crtc);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 
 	if (new_crtc_state->shared_dpll)
-		verify_single_dpll_state(i915, new_crtc_state->shared_dpll,
+		verify_single_dpll_state(display, new_crtc_state->shared_dpll,
 					 crtc, new_crtc_state);
 
 	if (old_crtc_state->shared_dpll &&
@@ -4721,10 +4733,9 @@ void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
 void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
 	struct intel_shared_dpll *pll;
 	int i;
 
 	for_each_shared_dpll(display, pll, i)
-		verify_single_dpll_state(i915, pll, NULL, NULL);
+		verify_single_dpll_state(display, pll, NULL, NULL);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 42379494f347..ebd0ed79d2b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -390,7 +390,7 @@ struct intel_shared_dpll {
 
 /* shared dpll functions */
 struct intel_shared_dpll *
-intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
+intel_get_shared_dpll_by_id(struct intel_display *display,
 			    enum intel_dpll_id id);
 void assert_shared_dpll(struct drm_i915_private *i915,
 			struct intel_shared_dpll *pll,
@@ -413,10 +413,10 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
 void intel_update_active_dpll(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc,
 			      struct intel_encoder *encoder);
-int intel_dpll_get_freq(struct drm_i915_private *i915,
+int intel_dpll_get_freq(struct intel_display *display,
 			const struct intel_shared_dpll *pll,
 			const struct intel_dpll_hw_state *dpll_hw_state);
-bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
+bool intel_dpll_get_hw_state(struct intel_display *display,
 			     struct intel_shared_dpll *pll,
 			     struct intel_dpll_hw_state *dpll_hw_state);
 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
@@ -424,8 +424,8 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
 void intel_shared_dpll_init(struct drm_i915_private *i915);
 void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
-void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
-void intel_dpll_sanitize_state(struct drm_i915_private *i915);
+void intel_dpll_readout_hw_state(struct intel_display *display);
+void intel_dpll_sanitize_state(struct intel_display *display);
 
 void intel_dpll_dump_hw_state(struct intel_display *display,
 			      struct drm_printer *p,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 10cdfdad82e4..4a6dd0d99e3e 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -795,7 +795,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 			    pipe_name(pipe));
 	}
 
-	intel_dpll_readout_hw_state(i915);
+	intel_dpll_readout_hw_state(display);
 
 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 	for_each_intel_connector_iter(connector, &conn_iter) {
@@ -1014,7 +1014,7 @@ void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 
 	intel_sanitize_all_crtcs(i915, ctx);
 
-	intel_dpll_sanitize_state(i915);
+	intel_dpll_sanitize_state(display);
 
 	intel_wm_get_hw_state(i915);
 
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 8fa5a6334d10..e874a577b7d1 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -249,6 +249,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
 static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	i915_reg_t reg;
@@ -263,7 +264,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 
 	if (HAS_PCH_CPT(dev_priv)) {
 		reg = TRANS_CHICKEN2(pipe);
-		val = intel_de_read(dev_priv, reg);
+		val = intel_de_read(display, reg);
 		/*
 		 * Workaround: Set the timing override bit
 		 * before enabling the pch transcoder.
@@ -272,12 +273,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		/* Configure frame start delay to match the CPU */
 		val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
 		val |= TRANS_CHICKEN2_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
-		intel_de_write(dev_priv, reg, val);
+		intel_de_write(display, reg, val);
 	}
 
 	reg = PCH_TRANSCONF(pipe);
-	val = intel_de_read(dev_priv, reg);
-	pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe));
+	val = intel_de_read(display, reg);
+	pipeconf_val = intel_de_read(display, TRANSCONF(display, pipe));
 
 	if (HAS_PCH_IBX(dev_priv)) {
 		/* Configure frame start delay to match the CPU */
@@ -307,9 +308,9 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 		val |= TRANS_INTERLACE_PROGRESSIVE;
 	}
 
-	intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
-	if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100))
-		drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",
+	intel_de_write(display, reg, val | TRANS_ENABLE);
+	if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100))
+		drm_err(display->drm, "failed to enable transcoder %c\n",
 			pipe_name(pipe));
 }
 
@@ -383,15 +384,15 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 	if (HAS_PCH_CPT(dev_priv)) {
 		u32 sel;
 
-		temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+		temp = intel_de_read(display, PCH_DPLL_SEL);
 		temp |= TRANS_DPLL_ENABLE(pipe);
 		sel = TRANS_DPLLB_SEL(pipe);
 		if (crtc_state->shared_dpll ==
-		    intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
+		    intel_get_shared_dpll_by_id(display, DPLL_ID_PCH_PLL_B))
 			temp |= sel;
 		else
 			temp &= ~sel;
-		intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+		intel_de_write(display, PCH_DPLL_SEL, temp);
 	}
 
 	/*
@@ -420,11 +421,12 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 	    intel_crtc_has_dp_encoder(crtc_state)) {
 		const struct drm_display_mode *adjusted_mode =
 			&crtc_state->hw.adjusted_mode;
-		u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5;
+		u32 bpc = (intel_de_read(display, TRANSCONF(display, pipe))
+			   & TRANSCONF_BPC_MASK) >> 5;
 		i915_reg_t reg = TRANS_DP_CTL(pipe);
 		enum port port;
 
-		temp = intel_de_read(dev_priv, reg);
+		temp = intel_de_read(display, reg);
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
 			  TRANS_DP_VSYNC_ACTIVE_HIGH |
 			  TRANS_DP_HSYNC_ACTIVE_HIGH |
@@ -438,10 +440,10 @@ void ilk_pch_enable(struct intel_atomic_state *state,
 			temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
 
 		port = intel_get_crtc_new_encoder(state, crtc_state)->port;
-		drm_WARN_ON(&dev_priv->drm, port < PORT_B || port > PORT_D);
+		drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D);
 		temp |= TRANS_DP_PORT_SEL(port);
 
-		intel_de_write(dev_priv, reg, temp);
+		intel_de_write(display, reg, temp);
 	}
 
 	ilk_enable_pch_transcoder(crtc_state);
@@ -496,6 +498,7 @@ static void ilk_pch_clock_get(struct intel_crtc_state *crtc_state)
 void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_display *display = to_intel_display(crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct intel_shared_dpll *pll;
 	enum pipe pipe = crtc->pipe;
@@ -503,12 +506,12 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 	bool pll_active;
 	u32 tmp;
 
-	if ((intel_de_read(dev_priv, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
+	if ((intel_de_read(display, PCH_TRANSCONF(pipe)) & TRANS_ENABLE) == 0)
 		return;
 
 	crtc_state->has_pch_encoder = true;
 
-	tmp = intel_de_read(dev_priv, FDI_RX_CTL(pipe));
+	tmp = intel_de_read(display, FDI_RX_CTL(pipe));
 	crtc_state->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
 				 FDI_DP_PORT_WIDTH_SHIFT) + 1;
 
@@ -522,19 +525,19 @@ void ilk_pch_get_config(struct intel_crtc_state *crtc_state)
 		 */
 		pll_id = (enum intel_dpll_id) pipe;
 	} else {
-		tmp = intel_de_read(dev_priv, PCH_DPLL_SEL);
+		tmp = intel_de_read(display, PCH_DPLL_SEL);
 		if (tmp & TRANS_DPLLB_SEL(pipe))
 			pll_id = DPLL_ID_PCH_PLL_B;
 		else
 			pll_id = DPLL_ID_PCH_PLL_A;
 	}
 
-	crtc_state->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
+	crtc_state->shared_dpll = intel_get_shared_dpll_by_id(display, pll_id);
 	pll = crtc_state->shared_dpll;
 
-	pll_active = intel_dpll_get_hw_state(dev_priv, pll,
+	pll_active = intel_dpll_get_hw_state(display, pll,
 					     &crtc_state->dpll_hw_state);
-	drm_WARN_ON(&dev_priv->drm, !pll_active);
+	drm_WARN_ON(display->drm, !pll_active);
 
 	tmp = crtc_state->dpll_hw_state.i9xx.dpll;
 	crtc_state->pixel_multiplier =
-- 
2.34.1