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* [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA
@ 2024-09-10  2:59 Ashutosh Dixit
  2024-09-10  3:16 ` ✓ CI.Patch_applied: success for drm/xe/oa: Insert wmb/sfence before enabling OA (rev6) Patchwork
                   ` (9 more replies)
  0 siblings, 10 replies; 18+ messages in thread
From: Ashutosh Dixit @ 2024-09-10  2:59 UTC (permalink / raw)
  To: intel-xe; +Cc: Umesh Nerlige Ramappa

We are occasionally seeing that OA Buffer register is not programmed (has
value 0) when OA is enabled. This means OA has been enabled before it has
been fully configured. Or, the register write enabling OA has overtaken
previous OA configuration register writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

v2: s/wmb()/xe_device_wmb()/

Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 63286ed8457fa..4fb7aae37a94f 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	xe_device_wmb(stream->oa->xe);
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA
@ 2024-09-10  1:39 Ashutosh Dixit
  0 siblings, 0 replies; 18+ messages in thread
From: Ashutosh Dixit @ 2024-09-10  1:39 UTC (permalink / raw)
  To: intel-xe; +Cc: Umesh Nerlige Ramappa

We are occasionally seeing that OA Buffer register is not programmed (has
value 0) when OA is enabled. This means OA has been enabled before it has
been fully configured. Or, the register write enabling OA has overtaken
previous OA configuration register writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

v2: s/wmb()/xe_device_wmb()/

Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 63286ed8457fa..4fb7aae37a94f 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	xe_device_wmb(stream->oa->xe);
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA
@ 2024-09-10  0:43 Ashutosh Dixit
  0 siblings, 0 replies; 18+ messages in thread
From: Ashutosh Dixit @ 2024-09-10  0:43 UTC (permalink / raw)
  To: intel-xe; +Cc: Umesh Nerlige Ramappa

We are occasionally seeing warnings such as "OAG Buffer register is not
programmed (has value 0). Register offset db08".  This means OA has been
enabled before it has been fully configured. Or, the register write
enabling OA has overtaken previous OA configuration register writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

v2: s/wmb()/xe_device_wmb()/

Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 63286ed8457fa..4fb7aae37a94f 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	xe_device_wmb(stream->oa->xe);
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA
@ 2024-08-28 15:55 Ashutosh Dixit
  0 siblings, 0 replies; 18+ messages in thread
From: Ashutosh Dixit @ 2024-08-28 15:55 UTC (permalink / raw)
  To: intel-xe

In some simulation environments, we occasionally see warnings such as "OAG
Buffer register is not programmed (has value 0). Register offset db08".
This means OA has been enabled before it has been fully configured. Or, the
register write enabling OA has overtaken previous OA configuration register
writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

v2: s/wmb()/xe_device_wmb()/

Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 4d4541e0b24c0..b02e92c27871e 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	xe_device_wmb(stream->oa->xe);
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA
@ 2024-08-26 23:34 Ashutosh Dixit
  0 siblings, 0 replies; 18+ messages in thread
From: Ashutosh Dixit @ 2024-08-26 23:34 UTC (permalink / raw)
  To: intel-xe; +Cc: Umesh Nerlige Ramappa, Guy Zadicario

In some simulation environments, we occasionally see warnings such as "OAG
Buffer register is not programmed (has value 0). Register offset db08".
This means OA has been enabled before it has been fully configured. Or, the
register write enabling OA has overtaken previous OA configuration register
writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

Fixes: e936f885f1e9 ("drm/xe/oa/uapi: Expose OA stream fd")
Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 4d4541e0b24c0..02a6baa3c37d9 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	wmb();
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA
@ 2024-08-26 23:29 Ashutosh Dixit
  0 siblings, 0 replies; 18+ messages in thread
From: Ashutosh Dixit @ 2024-08-26 23:29 UTC (permalink / raw)
  To: intel-xe; +Cc: Umesh Nerlige Ramappa, Guy Zadicario

In some simulation environments, we occasionally see warnings such as "OAG
Buffer register is not programmed (has value 0). Register offset db08".
This means OA has been enabled before it has been fully configured. Or, the
register write enabling OA has overtaken previous OA configuration register
writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 4d4541e0b24c0..02a6baa3c37d9 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	wmb();
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0


^ permalink raw reply related	[flat|nested] 18+ messages in thread
end of thread, other threads:[~2024-09-10 20:28 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-09-10  2:59 [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA Ashutosh Dixit
2024-09-10  3:16 ` ✓ CI.Patch_applied: success for drm/xe/oa: Insert wmb/sfence before enabling OA (rev6) Patchwork
2024-09-10  3:16 ` ✗ CI.checkpatch: warning " Patchwork
2024-09-10  3:19 ` ✓ CI.KUnit: success " Patchwork
2024-09-10  3:31 ` ✓ CI.Build: " Patchwork
2024-09-10  3:34 ` ✓ CI.Hooks: " Patchwork
2024-09-10  3:35 ` ✓ CI.checksparse: " Patchwork
2024-09-10  4:37 ` ✗ CI.BAT: failure " Patchwork
2024-09-10  6:36 ` ✗ CI.FULL: " Patchwork
2024-09-10 10:14 ` [PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA Jani Nikula
2024-09-10 16:17   ` Dixit, Ashutosh
2024-09-10 16:14 ` Matthew Brost
2024-09-10 20:28   ` Dixit, Ashutosh
  -- strict thread matches above, loose matches on Subject: below --
2024-09-10  1:39 Ashutosh Dixit
2024-09-10  0:43 Ashutosh Dixit
2024-08-28 15:55 Ashutosh Dixit
2024-08-26 23:34 Ashutosh Dixit
2024-08-26 23:29 Ashutosh Dixit

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