[PATCH 0/7] drm/xe: LRC refactors

[PATCH 0/7] drm/xe: LRC refactors

[Lucas De Marchi]

A few refactors while investigating the LRC corruption that
were happening before commit 3d85ab36bcb ("Revert "drm/xe/xe2: Enable
Indirect Ring State support for Xe2"").

They probably conflict with some other refactors by Tvrtko from
https://lore.kernel.org/all/20250703082059.61597-1-tvrtko.ursulin@igalia.com/

I'm reviewing that one and will figure out the conflicts. I already got
one of those cleanups from another series and added here on top.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
Lucas De Marchi (6):
      drm/xe/lrc: Reduce scope of empty lrc data
      drm/xe: Count dwords before allocating
      drm/xe/gt: Extract emit_job_sync()
      drm/xe/lrc: Add table with LRC layout
      drm/xe/lrc: Remove leftover TODO
      drm/xe/gt: Drop third submission for default context

Tvrtko Ursulin (1):
      drm/xe: Waste fewer instructions in emit_wa_job()

 drivers/gpu/drm/xe/xe_gt.c  | 172 ++++++++++++++++++++++----------------------
 drivers/gpu/drm/xe/xe_lrc.c |  57 ++++++++++-----
 drivers/gpu/drm/xe/xe_lrc.h |   2 +-
 3 files changed, 124 insertions(+), 107 deletions(-)

base-commit: 05fd9cf9ba87dcf4428adbca5237845f2c04d8ac
change-id: 20250625-lrc-refactors-82b10b576547

Lucas De Marchi

[PATCH 1/7] drm/xe/lrc: Reduce scope of empty lrc data

[Lucas De Marchi]

The only case in which new lrc data is created from scratch is when it's
called prior to recording the default lrc. There's no need to check for
NULL init_data since in that case the function already failed: just move
the allocation where it's needed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index d2ad8fe737eb3..7cde827ddbec9 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1044,7 +1044,6 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
 	struct xe_tile *tile = gt_to_tile(gt);
 	struct xe_device *xe = gt_to_xe(gt);
 	struct iosys_map map;
-	void *init_data = NULL;
 	u32 arb_enable;
 	u32 bo_flags;
 	int err;
@@ -1076,25 +1075,26 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
 	xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
 			     hwe->fence_irq, hwe->name);
 
-	if (!gt->default_lrc[hwe->class]) {
-		init_data = empty_lrc_data(hwe);
-		if (!init_data) {
-			err = -ENOMEM;
-			goto err_lrc_finish;
-		}
-	}
-
 	/*
 	 * Init Per-Process of HW status Page, LRC / context state to known
-	 * values
+	 * values. If there's already a primed default_lrc, just copy it, otherwise
+	 * it's the early submission to record the lrc: build a new empty one from
+	 * scratch.
 	 */
 	map = __xe_lrc_pphwsp_map(lrc);
-	if (!init_data) {
+	if (gt->default_lrc[hwe->class]) {
 		xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */
 		xe_map_memcpy_to(xe, &map, LRC_PPHWSP_SIZE,
 				 gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE,
 				 lrc_size - LRC_PPHWSP_SIZE);
 	} else {
+		void *init_data = empty_lrc_data(hwe);
+
+		if (!init_data) {
+			err = -ENOMEM;
+			goto err_lrc_finish;
+		}
+
 		xe_map_memcpy_to(xe, &map, 0, init_data, lrc_size);
 		kfree(init_data);
 	}

-- 
2.49.0

Re: [PATCH 1/7] drm/xe/lrc: Reduce scope of empty lrc data

[Tvrtko Ursulin]

On 03/07/2025 23:41, Lucas De Marchi wrote:
> The only case in which new lrc data is created from scratch is when it's
> called prior to recording the default lrc. There's no need to check for
> NULL init_data since in that case the function already failed: just move
> the allocation where it's needed.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_lrc.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index d2ad8fe737eb3..7cde827ddbec9 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1044,7 +1044,6 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>   	struct xe_tile *tile = gt_to_tile(gt);
>   	struct xe_device *xe = gt_to_xe(gt);
>   	struct iosys_map map;
> -	void *init_data = NULL;
>   	u32 arb_enable;
>   	u32 bo_flags;
>   	int err;
> @@ -1076,25 +1075,26 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>   	xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
>   			     hwe->fence_irq, hwe->name);
>   
> -	if (!gt->default_lrc[hwe->class]) {
> -		init_data = empty_lrc_data(hwe);
> -		if (!init_data) {
> -			err = -ENOMEM;
> -			goto err_lrc_finish;
> -		}
> -	}
> -
>   	/*
>   	 * Init Per-Process of HW status Page, LRC / context state to known
> -	 * values
> +	 * values. If there's already a primed default_lrc, just copy it, otherwise
> +	 * it's the early submission to record the lrc: build a new empty one from
> +	 * scratch.
>   	 */
>   	map = __xe_lrc_pphwsp_map(lrc);
> -	if (!init_data) {
> +	if (gt->default_lrc[hwe->class]) {
>   		xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */
>   		xe_map_memcpy_to(xe, &map, LRC_PPHWSP_SIZE,
>   				 gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE,
>   				 lrc_size - LRC_PPHWSP_SIZE);
>   	} else {
> +		void *init_data = empty_lrc_data(hwe);
> +
> +		if (!init_data) {
> +			err = -ENOMEM;
> +			goto err_lrc_finish;
> +		}
> +
>   		xe_map_memcpy_to(xe, &map, 0, init_data, lrc_size);
>   		kfree(init_data);
>   	}
> 

That was indeed a bit roundabout, good cleanup.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Regards,

Tvrtko

Re: [PATCH 1/7] drm/xe/lrc: Reduce scope of empty lrc data

[Matthew Brost]

On Thu, Jul 03, 2025 at 03:41:10PM -0700, Lucas De Marchi wrote:
> The only case in which new lrc data is created from scratch is when it's
> called prior to recording the default lrc. There's no need to check for
> NULL init_data since in that case the function already failed: just move
> the allocation where it's needed.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> ---
>  drivers/gpu/drm/xe/xe_lrc.c | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index d2ad8fe737eb3..7cde827ddbec9 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1044,7 +1044,6 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>  	struct xe_tile *tile = gt_to_tile(gt);
>  	struct xe_device *xe = gt_to_xe(gt);
>  	struct iosys_map map;
> -	void *init_data = NULL;
>  	u32 arb_enable;
>  	u32 bo_flags;
>  	int err;
> @@ -1076,25 +1075,26 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
>  	xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt,
>  			     hwe->fence_irq, hwe->name);
>  
> -	if (!gt->default_lrc[hwe->class]) {
> -		init_data = empty_lrc_data(hwe);
> -		if (!init_data) {
> -			err = -ENOMEM;
> -			goto err_lrc_finish;
> -		}
> -	}
> -
>  	/*
>  	 * Init Per-Process of HW status Page, LRC / context state to known
> -	 * values
> +	 * values. If there's already a primed default_lrc, just copy it, otherwise
> +	 * it's the early submission to record the lrc: build a new empty one from
> +	 * scratch.
>  	 */
>  	map = __xe_lrc_pphwsp_map(lrc);
> -	if (!init_data) {
> +	if (gt->default_lrc[hwe->class]) {
>  		xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE);	/* PPHWSP */
>  		xe_map_memcpy_to(xe, &map, LRC_PPHWSP_SIZE,
>  				 gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE,
>  				 lrc_size - LRC_PPHWSP_SIZE);
>  	} else {
> +		void *init_data = empty_lrc_data(hwe);
> +
> +		if (!init_data) {
> +			err = -ENOMEM;
> +			goto err_lrc_finish;
> +		}
> +
>  		xe_map_memcpy_to(xe, &map, 0, init_data, lrc_size);
>  		kfree(init_data);
>  	}
> 
> -- 
> 2.49.0
> 

[PATCH 2/7] drm/xe: Count dwords before allocating

[Lucas De Marchi]

The bb allocation in emit_wa_job() is wrong in 2 ways: first it's
allocating enough space for the 3DSTATE or hardcoding 4k depending on
the engine. In the first case it doesn't account for the WAs and in the
former it may not be sufficient. Secondly it's using the size instead of
number of dwords, causing the buffer to be 4x bigger than needed.

While it's unlikely this is causing any real issue, let's calculate the
needed space and allocate just enough.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.c | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index d397df056e4cd..a926f560f2e36 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -189,16 +189,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 	long timeout;
 	int count_rmw = 0;
 	int count = 0;
-
-	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
-		/* Big enough to emit all of the context's 3DSTATE */
-		bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false);
-	else
-		/* Just pick a large BB size */
-		bb = xe_bb_new(gt, SZ_4K, false);
-
-	if (IS_ERR(bb))
-		return PTR_ERR(bb);
+	size_t bb_len;
 
 	/* count RMW registers as those will be handled separately */
 	xa_for_each(&sr->xa, idx, entry) {
@@ -211,8 +202,26 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 	if (count || count_rmw)
 		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
 
+	bb_len = count * 2;
+	if (count_rmw)
+		bb_len += count_rmw * 20 + 7;
+
+	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
+		/*
+		 * Big enough to emit all of the context's 3DSTATE via
+		 * xe_lrc_emit_hwe_state_instructions()
+		 */
+		bb_len += xe_gt_lrc_size(gt, q->hwe->class) / sizeof(u32);
+
+	/* Make sure accounting offsets downward is also aligned */
+	bb_len = ALIGN(bb_len, SZ_4K);
+
+	bb = xe_bb_new(gt, bb_len, false);
+	if (IS_ERR(bb))
+		return PTR_ERR(bb);
+
 	if (count) {
-		/* emit single LRI with all non RMW regs */
+		/* Emit single LRI with all non RMW regs: 2 dw per reg */
 
 		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
 
@@ -236,7 +245,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 	}
 
 	if (count_rmw) {
-		/* emit MI_MATH for each RMW reg */
+		/* Emit MI_MATH for each RMW reg: 20dw per reg + 7 trailing dw */
 
 		xa_for_each(&sr->xa, idx, entry) {
 			if (entry->reg.masked || entry->clr_bits == ~0)

-- 
2.49.0

Re: [PATCH 2/7] drm/xe: Count dwords before allocating

[Tvrtko Ursulin]

On 03/07/2025 23:41, Lucas De Marchi wrote:
> The bb allocation in emit_wa_job() is wrong in 2 ways: first it's
> allocating enough space for the 3DSTATE or hardcoding 4k depending on
> the engine. In the first case it doesn't account for the WAs and in the
> former it may not be sufficient. Secondly it's using the size instead of
> number of dwords, causing the buffer to be 4x bigger than needed.
> 
> While it's unlikely this is causing any real issue, let's calculate the
> needed space and allocate just enough.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_gt.c | 33 +++++++++++++++++++++------------
>   1 file changed, 21 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index d397df056e4cd..a926f560f2e36 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -189,16 +189,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   	long timeout;
>   	int count_rmw = 0;
>   	int count = 0;
> -
> -	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
> -		/* Big enough to emit all of the context's 3DSTATE */
> -		bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false);
> -	else
> -		/* Just pick a large BB size */
> -		bb = xe_bb_new(gt, SZ_4K, false);
> -
> -	if (IS_ERR(bb))
> -		return PTR_ERR(bb);
> +	size_t bb_len;
>   
>   	/* count RMW registers as those will be handled separately */
>   	xa_for_each(&sr->xa, idx, entry) {
> @@ -211,8 +202,26 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   	if (count || count_rmw)
>   		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
>   
> +	bb_len = count * 2;

Shouldn't this be count * 2 + 1 ?

> +	if (count_rmw)
> +		bb_len += count_rmw * 20 + 7;

1)
This one is good. For both hardcoded value are a bit fragile maintenance 
wise but it can be improved later.

2)
Until now bb_len is in dwords, but below it is in bytes, right? In which 
case here there should be one, at this point exactly:

  bb_len *= sizeof(u32);

> +
> +	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
> +		/*
> +		 * Big enough to emit all of the context's 3DSTATE via
> +		 * xe_lrc_emit_hwe_state_instructions()
> +		 */
> +		bb_len += xe_gt_lrc_size(gt, q->hwe->class) / sizeof(u32);
> +
> +	/* Make sure accounting offsets downward is also aligned */
> +	bb_len = ALIGN(bb_len, SZ_4K);

I did not get what you mean by "accounting offsets downward"?

Regards,

Tvrtko

> +
> +	bb = xe_bb_new(gt, bb_len, false);
> +	if (IS_ERR(bb))
> +		return PTR_ERR(bb);
> +
>   	if (count) {
> -		/* emit single LRI with all non RMW regs */
> +		/* Emit single LRI with all non RMW regs: 2 dw per reg */
>   
>   		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
>   
> @@ -236,7 +245,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   	}
>   
>   	if (count_rmw) {
> -		/* emit MI_MATH for each RMW reg */
> +		/* Emit MI_MATH for each RMW reg: 20dw per reg + 7 trailing dw */
>   
>   		xa_for_each(&sr->xa, idx, entry) {
>   			if (entry->reg.masked || entry->clr_bits == ~0)
> 

Re: [PATCH 2/7] drm/xe: Count dwords before allocating

[Lucas De Marchi]

On Fri, Jul 04, 2025 at 11:20:08AM +0100, Tvrtko Ursulin wrote:
>
>On 03/07/2025 23:41, Lucas De Marchi wrote:
>>The bb allocation in emit_wa_job() is wrong in 2 ways: first it's
>>allocating enough space for the 3DSTATE or hardcoding 4k depending on
>>the engine. In the first case it doesn't account for the WAs and in the
>>former it may not be sufficient. Secondly it's using the size instead of
>>number of dwords, causing the buffer to be 4x bigger than needed.
>>
>>While it's unlikely this is causing any real issue, let's calculate the
>>needed space and allocate just enough.
>>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>>  drivers/gpu/drm/xe/xe_gt.c | 33 +++++++++++++++++++++------------
>>  1 file changed, 21 insertions(+), 12 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>>index d397df056e4cd..a926f560f2e36 100644
>>--- a/drivers/gpu/drm/xe/xe_gt.c
>>+++ b/drivers/gpu/drm/xe/xe_gt.c
>>@@ -189,16 +189,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  	long timeout;
>>  	int count_rmw = 0;
>>  	int count = 0;
>>-
>>-	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
>>-		/* Big enough to emit all of the context's 3DSTATE */
>>-		bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false);
>>-	else
>>-		/* Just pick a large BB size */
>>-		bb = xe_bb_new(gt, SZ_4K, false);
>>-
>>-	if (IS_ERR(bb))
>>-		return PTR_ERR(bb);
>>+	size_t bb_len;
>>  	/* count RMW registers as those will be handled separately */
>>  	xa_for_each(&sr->xa, idx, entry) {
>>@@ -211,8 +202,26 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  	if (count || count_rmw)
>>  		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
>>+	bb_len = count * 2;
>
>Shouldn't this be count * 2 + 1 ?

right, but then we also need a `if (count)`, like we have for count_rmw.

>
>>+	if (count_rmw)
>>+		bb_len += count_rmw * 20 + 7;
>
>1)
>This one is good. For both hardcoded value are a bit fragile 
>maintenance wise but it can be improved later.
>
>2)
>Until now bb_len is in dwords, but below it is in bytes, right? In 
>which case here there should be one, at this point exactly:
>
> bb_len *= sizeof(u32);

not at this point exactly... xe_bb_new() arg is number of dwords.
What we are missing is to make sure the size is 4k aligned...

>
>>+
>>+	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
>>+		/*
>>+		 * Big enough to emit all of the context's 3DSTATE via
>>+		 * xe_lrc_emit_hwe_state_instructions()
>>+		 */
>>+		bb_len += xe_gt_lrc_size(gt, q->hwe->class) / sizeof(u32);
>>+
>>+	/* Make sure accounting offsets downward is also aligned */
>>+	bb_len = ALIGN(bb_len, SZ_4K);
>
>I did not get what you mean by "accounting offsets downward"?

we use e.g. `xe_bo_size(lrc->bo) - 4K` to get the offset to "the last
page" in the buffer. However if the overall size is not a multiple, it
will return a non-aligned value which is not allowed here: the
bb_per_ctx_ptr for example needs to be 4k-aligned.

thanks
Lucas De Marchi

>
>Regards,
>
>Tvrtko
>
>>+
>>+	bb = xe_bb_new(gt, bb_len, false);
>>+	if (IS_ERR(bb))
>>+		return PTR_ERR(bb);
>>+
>>  	if (count) {
>>-		/* emit single LRI with all non RMW regs */
>>+		/* Emit single LRI with all non RMW regs: 2 dw per reg */
>>  		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
>>@@ -236,7 +245,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  	}
>>  	if (count_rmw) {
>>-		/* emit MI_MATH for each RMW reg */
>>+		/* Emit MI_MATH for each RMW reg: 20dw per reg + 7 trailing dw */
>>  		xa_for_each(&sr->xa, idx, entry) {
>>  			if (entry->reg.masked || entry->clr_bits == ~0)
>>
>

Re: [PATCH 2/7] drm/xe: Count dwords before allocating

[Lucas De Marchi]

On Sun, Jul 06, 2025 at 10:30:11PM -0500, Lucas De Marchi wrote:
>On Fri, Jul 04, 2025 at 11:20:08AM +0100, Tvrtko Ursulin wrote:
>>
>>On 03/07/2025 23:41, Lucas De Marchi wrote:
>>>The bb allocation in emit_wa_job() is wrong in 2 ways: first it's
>>>allocating enough space for the 3DSTATE or hardcoding 4k depending on
>>>the engine. In the first case it doesn't account for the WAs and in the
>>>former it may not be sufficient. Secondly it's using the size instead of
>>>number of dwords, causing the buffer to be 4x bigger than needed.
>>>
>>>While it's unlikely this is causing any real issue, let's calculate the
>>>needed space and allocate just enough.
>>>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>---
>>> drivers/gpu/drm/xe/xe_gt.c | 33 +++++++++++++++++++++------------
>>> 1 file changed, 21 insertions(+), 12 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>>>index d397df056e4cd..a926f560f2e36 100644
>>>--- a/drivers/gpu/drm/xe/xe_gt.c
>>>+++ b/drivers/gpu/drm/xe/xe_gt.c
>>>@@ -189,16 +189,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>> 	long timeout;
>>> 	int count_rmw = 0;
>>> 	int count = 0;
>>>-
>>>-	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
>>>-		/* Big enough to emit all of the context's 3DSTATE */
>>>-		bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false);
>>>-	else
>>>-		/* Just pick a large BB size */
>>>-		bb = xe_bb_new(gt, SZ_4K, false);
>>>-
>>>-	if (IS_ERR(bb))
>>>-		return PTR_ERR(bb);
>>>+	size_t bb_len;
>>> 	/* count RMW registers as those will be handled separately */
>>> 	xa_for_each(&sr->xa, idx, entry) {
>>>@@ -211,8 +202,26 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>> 	if (count || count_rmw)
>>> 		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
>>>+	bb_len = count * 2;
>>
>>Shouldn't this be count * 2 + 1 ?
>
>right, but then we also need a `if (count)`, like we have for count_rmw.
>
>>
>>>+	if (count_rmw)
>>>+		bb_len += count_rmw * 20 + 7;
>>
>>1)
>>This one is good. For both hardcoded value are a bit fragile 
>>maintenance wise but it can be improved later.
>>
>>2)
>>Until now bb_len is in dwords, but below it is in bytes, right? In 
>>which case here there should be one, at this point exactly:
>>
>>bb_len *= sizeof(u32);
>
>not at this point exactly... xe_bb_new() arg is number of dwords.

actually not at this point and not below neither. the 4k align is
completely bogus there.

>What we are missing is to make sure the size is 4k aligned...
>
>>
>>>+
>>>+	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)
>>>+		/*
>>>+		 * Big enough to emit all of the context's 3DSTATE via
>>>+		 * xe_lrc_emit_hwe_state_instructions()
>>>+		 */
>>>+		bb_len += xe_gt_lrc_size(gt, q->hwe->class) / sizeof(u32);
>>>+
>>>+	/* Make sure accounting offsets downward is also aligned */
>>>+	bb_len = ALIGN(bb_len, SZ_4K);
>>
>>I did not get what you mean by "accounting offsets downward"?
>
>we use e.g. `xe_bo_size(lrc->bo) - 4K` to get the offset to "the last
>page" in the buffer. However if the overall size is not a multiple, it
>will return a non-aligned value which is not allowed here: the
>bb_per_ctx_ptr for example needs to be 4k-aligned.

my bad... this is the bb from xe_bb_new(), not the bo. It will already
not be aligned due to xe_bb_new() and it also doesn't matter.

Lucas De Marchi

[PATCH 3/7] drm/xe/gt: Extract emit_job_sync()

[Lucas De Marchi]

Both the nop and wa jobs are going through the same boiler plate calls
to emit the job with a timeout and handling error for both bb and job.
Extract emit_job_sync() so those functions create the bb, handling
possible errors and delegate the part about really emitting the job
and waiting for its completion.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.c | 59 +++++++++++++++++++---------------------------
 1 file changed, 24 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index a926f560f2e36..67425e37c2187 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -146,30 +146,23 @@ static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
 
 static void gt_reset_worker(struct work_struct *w);
 
-static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
+static int emit_job_sync(struct xe_exec_queue *q, struct xe_bb *bb,
+			 long timeout_jiffies)
 {
 	struct xe_sched_job *job;
-	struct xe_bb *bb;
 	struct dma_fence *fence;
 	long timeout;
 
-	bb = xe_bb_new(gt, 4, false);
-	if (IS_ERR(bb))
-		return PTR_ERR(bb);
-
 	job = xe_bb_create_job(q, bb);
-	if (IS_ERR(job)) {
-		xe_bb_free(bb, NULL);
+	if (IS_ERR(job))
 		return PTR_ERR(job);
-	}
 
 	xe_sched_job_arm(job);
 	fence = dma_fence_get(&job->drm.s_fence->finished);
 	xe_sched_job_push(job);
 
-	timeout = dma_fence_wait_timeout(fence, false, HZ);
+	timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies);
 	dma_fence_put(fence);
-	xe_bb_free(bb, NULL);
 	if (timeout < 0)
 		return timeout;
 	else if (!timeout)
@@ -178,17 +171,28 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
 	return 0;
 }
 
+static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
+{
+	struct xe_bb *bb;
+	int ret;
+
+	bb = xe_bb_new(gt, 4, false);
+	if (IS_ERR(bb))
+		return PTR_ERR(bb);
+
+	ret = emit_job_sync(q, bb, HZ);
+	xe_bb_free(bb, NULL);
+
+	return ret;
+}
+
 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 {
 	struct xe_reg_sr *sr = &q->hwe->reg_lrc;
 	struct xe_reg_sr_entry *entry;
+	int count_rmw = 0, count = 0, ret;
 	unsigned long idx;
-	struct xe_sched_job *job;
 	struct xe_bb *bb;
-	struct dma_fence *fence;
-	long timeout;
-	int count_rmw = 0;
-	int count = 0;
 	size_t bb_len;
 
 	/* count RMW registers as those will be handled separately */
@@ -199,9 +203,6 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 			++count_rmw;
 	}
 
-	if (count || count_rmw)
-		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
-
 	bb_len = count * 2;
 	if (count_rmw)
 		bb_len += count_rmw * 20 + 7;
@@ -292,25 +293,13 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 
 	xe_lrc_emit_hwe_state_instructions(q, bb);
 
-	job = xe_bb_create_job(q, bb);
-	if (IS_ERR(job)) {
-		xe_bb_free(bb, NULL);
-		return PTR_ERR(job);
-	}
+	if (bb->len)
+		xe_gt_dbg(gt, "LRC WA %s save-restore batch: %u dw", sr->name, bb->len);
 
-	xe_sched_job_arm(job);
-	fence = dma_fence_get(&job->drm.s_fence->finished);
-	xe_sched_job_push(job);
-
-	timeout = dma_fence_wait_timeout(fence, false, HZ);
-	dma_fence_put(fence);
+	ret = emit_job_sync(q, bb, HZ);
 	xe_bb_free(bb, NULL);
-	if (timeout < 0)
-		return timeout;
-	else if (!timeout)
-		return -ETIME;
 
-	return 0;
+	return ret;
 }
 
 int xe_gt_record_default_lrcs(struct xe_gt *gt)

-- 
2.49.0

Re: [PATCH 3/7] drm/xe/gt: Extract emit_job_sync()

[Tvrtko Ursulin]

On 03/07/2025 23:41, Lucas De Marchi wrote:
> Both the nop and wa jobs are going through the same boiler plate calls
> to emit the job with a timeout and handling error for both bb and job.
> Extract emit_job_sync() so those functions create the bb, handling
> possible errors and delegate the part about really emitting the job
> and waiting for its completion.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_gt.c | 59 +++++++++++++++++++---------------------------
>   1 file changed, 24 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index a926f560f2e36..67425e37c2187 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -146,30 +146,23 @@ static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
>   
>   static void gt_reset_worker(struct work_struct *w);
>   
> -static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
> +static int emit_job_sync(struct xe_exec_queue *q, struct xe_bb *bb,
> +			 long timeout_jiffies)
>   {
>   	struct xe_sched_job *job;
> -	struct xe_bb *bb;
>   	struct dma_fence *fence;
>   	long timeout;
>   
> -	bb = xe_bb_new(gt, 4, false);
> -	if (IS_ERR(bb))
> -		return PTR_ERR(bb);
> -
>   	job = xe_bb_create_job(q, bb);
> -	if (IS_ERR(job)) {
> -		xe_bb_free(bb, NULL);
> +	if (IS_ERR(job))
>   		return PTR_ERR(job);
> -	}
>   
>   	xe_sched_job_arm(job);
>   	fence = dma_fence_get(&job->drm.s_fence->finished);
>   	xe_sched_job_push(job);
>   
> -	timeout = dma_fence_wait_timeout(fence, false, HZ);
> +	timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies);
>   	dma_fence_put(fence);
> -	xe_bb_free(bb, NULL);
>   	if (timeout < 0)
>   		return timeout;
>   	else if (!timeout)
> @@ -178,17 +171,28 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   	return 0;
>   }
>   
> +static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
> +{
> +	struct xe_bb *bb;
> +	int ret;
> +
> +	bb = xe_bb_new(gt, 4, false);
> +	if (IS_ERR(bb))
> +		return PTR_ERR(bb);
> +
> +	ret = emit_job_sync(q, bb, HZ);
> +	xe_bb_free(bb, NULL);
> +
> +	return ret;
> +}
> +
>   static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   {
>   	struct xe_reg_sr *sr = &q->hwe->reg_lrc;
>   	struct xe_reg_sr_entry *entry;
> +	int count_rmw = 0, count = 0, ret;

Nit - might as well width sort the declarations while touching. Up to you.

>   	unsigned long idx;
> -	struct xe_sched_job *job;
>   	struct xe_bb *bb;
> -	struct dma_fence *fence;
> -	long timeout;
> -	int count_rmw = 0;
> -	int count = 0;
>   	size_t bb_len;
>   
>   	/* count RMW registers as those will be handled separately */
> @@ -199,9 +203,6 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   			++count_rmw;
>   	}
>   
> -	if (count || count_rmw)
> -		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
> -
>   	bb_len = count * 2;
>   	if (count_rmw)
>   		bb_len += count_rmw * 20 + 7;
> @@ -292,25 +293,13 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>   
>   	xe_lrc_emit_hwe_state_instructions(q, bb);
>   
> -	job = xe_bb_create_job(q, bb);
> -	if (IS_ERR(job)) {
> -		xe_bb_free(bb, NULL);
> -		return PTR_ERR(job);
> -	}
> +	if (bb->len)
> +		xe_gt_dbg(gt, "LRC WA %s save-restore batch: %u dw", sr->name, bb->len);
>   
> -	xe_sched_job_arm(job);
> -	fence = dma_fence_get(&job->drm.s_fence->finished);
> -	xe_sched_job_push(job);
> -
> -	timeout = dma_fence_wait_timeout(fence, false, HZ);
> -	dma_fence_put(fence);
> +	ret = emit_job_sync(q, bb, HZ);
>   	xe_bb_free(bb, NULL);
> -	if (timeout < 0)
> -		return timeout;
> -	else if (!timeout)
> -		return -ETIME;
>   
> -	return 0;
> +	return ret;
>   }
>   
>   int xe_gt_record_default_lrcs(struct xe_gt *gt)
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Regards,

Tvrtko

Re: [PATCH 3/7] drm/xe/gt: Extract emit_job_sync()

[Lucas De Marchi]

On Fri, Jul 04, 2025 at 11:35:02AM +0100, Tvrtko Ursulin wrote:
>
>On 03/07/2025 23:41, Lucas De Marchi wrote:
>>Both the nop and wa jobs are going through the same boiler plate calls
>>to emit the job with a timeout and handling error for both bb and job.
>>Extract emit_job_sync() so those functions create the bb, handling
>>possible errors and delegate the part about really emitting the job
>>and waiting for its completion.
>>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>>  drivers/gpu/drm/xe/xe_gt.c | 59 +++++++++++++++++++---------------------------
>>  1 file changed, 24 insertions(+), 35 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>>index a926f560f2e36..67425e37c2187 100644
>>--- a/drivers/gpu/drm/xe/xe_gt.c
>>+++ b/drivers/gpu/drm/xe/xe_gt.c
>>@@ -146,30 +146,23 @@ static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
>>  static void gt_reset_worker(struct work_struct *w);
>>-static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>+static int emit_job_sync(struct xe_exec_queue *q, struct xe_bb *bb,
>>+			 long timeout_jiffies)
>>  {
>>  	struct xe_sched_job *job;
>>-	struct xe_bb *bb;
>>  	struct dma_fence *fence;
>>  	long timeout;
>>-	bb = xe_bb_new(gt, 4, false);
>>-	if (IS_ERR(bb))
>>-		return PTR_ERR(bb);
>>-
>>  	job = xe_bb_create_job(q, bb);
>>-	if (IS_ERR(job)) {
>>-		xe_bb_free(bb, NULL);
>>+	if (IS_ERR(job))
>>  		return PTR_ERR(job);
>>-	}
>>  	xe_sched_job_arm(job);
>>  	fence = dma_fence_get(&job->drm.s_fence->finished);
>>  	xe_sched_job_push(job);
>>-	timeout = dma_fence_wait_timeout(fence, false, HZ);
>>+	timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies);
>>  	dma_fence_put(fence);
>>-	xe_bb_free(bb, NULL);
>>  	if (timeout < 0)
>>  		return timeout;
>>  	else if (!timeout)
>>@@ -178,17 +171,28 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  	return 0;
>>  }
>>+static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>+{
>>+	struct xe_bb *bb;
>>+	int ret;
>>+
>>+	bb = xe_bb_new(gt, 4, false);
>>+	if (IS_ERR(bb))
>>+		return PTR_ERR(bb);
>>+
>>+	ret = emit_job_sync(q, bb, HZ);
>>+	xe_bb_free(bb, NULL);
>>+
>>+	return ret;
>>+}
>>+
>>  static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  {
>>  	struct xe_reg_sr *sr = &q->hwe->reg_lrc;
>>  	struct xe_reg_sr_entry *entry;
>>+	int count_rmw = 0, count = 0, ret;
>
>Nit - might as well width sort the declarations while touching. Up to you.

it's for very few chars, and  would separate the related
xe_reg_sr{,_entry} variables.... so in this case I'd rather leave it
like that.

>
>>  	unsigned long idx;
>>-	struct xe_sched_job *job;
>>  	struct xe_bb *bb;
>>-	struct dma_fence *fence;
>>-	long timeout;
>>-	int count_rmw = 0;
>>-	int count = 0;
>>  	size_t bb_len;
>>  	/* count RMW registers as those will be handled separately */
>>@@ -199,9 +203,6 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  			++count_rmw;
>>  	}
>>-	if (count || count_rmw)
>>-		xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name);
>>-
>>  	bb_len = count * 2;
>>  	if (count_rmw)
>>  		bb_len += count_rmw * 20 + 7;
>>@@ -292,25 +293,13 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>>  	xe_lrc_emit_hwe_state_instructions(q, bb);
>>-	job = xe_bb_create_job(q, bb);
>>-	if (IS_ERR(job)) {
>>-		xe_bb_free(bb, NULL);
>>-		return PTR_ERR(job);
>>-	}
>>+	if (bb->len)
>>+		xe_gt_dbg(gt, "LRC WA %s save-restore batch: %u dw", sr->name, bb->len);
>>-	xe_sched_job_arm(job);
>>-	fence = dma_fence_get(&job->drm.s_fence->finished);
>>-	xe_sched_job_push(job);
>>-
>>-	timeout = dma_fence_wait_timeout(fence, false, HZ);
>>-	dma_fence_put(fence);
>>+	ret = emit_job_sync(q, bb, HZ);
>>  	xe_bb_free(bb, NULL);
>>-	if (timeout < 0)
>>-		return timeout;
>>-	else if (!timeout)
>>-		return -ETIME;
>>-	return 0;
>>+	return ret;
>>  }
>>  int xe_gt_record_default_lrcs(struct xe_gt *gt)
>>
>
>Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

thanks
Lucas De Marchi

>
>Regards,
>
>Tvrtko
>

[PATCH 4/7] drm/xe/lrc: Add table with LRC layout

[Lucas De Marchi]

Add a table to document the LRC's BO layout to make it easier to
visualize how each region stacks on top of each other.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 7cde827ddbec9..75f4678cb090a 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -42,6 +42,27 @@
 #define LRC_INDIRECT_RING_STATE_SIZE		SZ_4K
 #define LRC_WA_BB_SIZE				SZ_4K
 
+/*
+ * Layout of the LRC and associated data allocated as
+ * lrc->bo:
+ *
+ *   Region                       Size
+ *  +============================+=================+ <- __xe_lrc_ring_offset()
+ *  | Ring                       | ring_size, see  |
+ *  |                            | xe_lrc_init()   |
+ *  +============================+=================+ <- __xe_lrc_pphwsp_offset()
+ *  | PPHWSP (includes SW state) | 4K              |
+ *  +----------------------------+-----------------+ <- __xe_lrc_ring_offset()
+ *  | Engine Context Image       | n * 4K, see     |
+ *  |                            | xe_gt_lrc_size()|
+ *  +----------------------------+-----------------+ <- __xe_lrc_indirect_ring_offset()
+ *  | Indirect Ring State Page   | 0 or 4k, see    |
+ *  |                            | xe_gt_lrc_size()|
+ *  +============================+=================+ <- __xe_lrc_wa_bb_offset()
+ *  | WA BB Per Ctx              | 4k              |
+ *  +============================+=================+ <- xe_bo_size(lrc->bo)
+ */
+
 static struct xe_device *
 lrc_to_xe(struct xe_lrc *lrc)
 {

-- 
2.49.0

Re: [PATCH 4/7] drm/xe/lrc: Add table with LRC layout

[Tvrtko Ursulin]

On 03/07/2025 23:41, Lucas De Marchi wrote:
> Add a table to document the LRC's BO layout to make it easier to
> visualize how each region stacks on top of each other.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_lrc.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 7cde827ddbec9..75f4678cb090a 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -42,6 +42,27 @@
>   #define LRC_INDIRECT_RING_STATE_SIZE		SZ_4K
>   #define LRC_WA_BB_SIZE				SZ_4K
>   
> +/*
> + * Layout of the LRC and associated data allocated as
> + * lrc->bo:
> + *
> + *   Region                       Size
> + *  +============================+=================+ <- __xe_lrc_ring_offset()
> + *  | Ring                       | ring_size, see  |
> + *  |                            | xe_lrc_init()   |
> + *  +============================+=================+ <- __xe_lrc_pphwsp_offset()
> + *  | PPHWSP (includes SW state) | 4K              |
> + *  +----------------------------+-----------------+ <- __xe_lrc_ring_offset()
> + *  | Engine Context Image       | n * 4K, see     |
> + *  |                            | xe_gt_lrc_size()|
> + *  +----------------------------+-----------------+ <- __xe_lrc_indirect_ring_offset()
> + *  | Indirect Ring State Page   | 0 or 4k, see    |
> + *  |                            | xe_gt_lrc_size()|
> + *  +============================+=================+ <- __xe_lrc_wa_bb_offset()
> + *  | WA BB Per Ctx              | 4k              |
> + *  +============================+=================+ <- xe_bo_size(lrc->bo)
> + */

I assume '---' separates parts which are considered engine lrc state, 
while '===' is for other data which happens to be in the same BO. So for 
indirect ctx I will use '==='. Just unsure if indirect ring state should 
in that case also be '==='? Looks like LRC image points to it's ggtt 
address which would suggest it is equally separate.

> +
>   static struct xe_device *
>   lrc_to_xe(struct xe_lrc *lrc)
>   {
> 

Modulo the above:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Regards,

Tvrtko

Re: [PATCH 4/7] drm/xe/lrc: Add table with LRC layout

[Lucas De Marchi]

On Fri, Jul 04, 2025 at 11:41:17AM +0100, Tvrtko Ursulin wrote:
>
>On 03/07/2025 23:41, Lucas De Marchi wrote:
>>Add a table to document the LRC's BO layout to make it easier to
>>visualize how each region stacks on top of each other.
>>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>>  drivers/gpu/drm/xe/xe_lrc.c | 21 +++++++++++++++++++++
>>  1 file changed, 21 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>>index 7cde827ddbec9..75f4678cb090a 100644
>>--- a/drivers/gpu/drm/xe/xe_lrc.c
>>+++ b/drivers/gpu/drm/xe/xe_lrc.c
>>@@ -42,6 +42,27 @@
>>  #define LRC_INDIRECT_RING_STATE_SIZE		SZ_4K
>>  #define LRC_WA_BB_SIZE				SZ_4K
>>+/*
>>+ * Layout of the LRC and associated data allocated as
>>+ * lrc->bo:
>>+ *
>>+ *   Region                       Size
>>+ *  +============================+=================+ <- __xe_lrc_ring_offset()
>>+ *  | Ring                       | ring_size, see  |
>>+ *  |                            | xe_lrc_init()   |
>>+ *  +============================+=================+ <- __xe_lrc_pphwsp_offset()
>>+ *  | PPHWSP (includes SW state) | 4K              |
>>+ *  +----------------------------+-----------------+ <- __xe_lrc_ring_offset()
>>+ *  | Engine Context Image       | n * 4K, see     |
>>+ *  |                            | xe_gt_lrc_size()|
>>+ *  +----------------------------+-----------------+ <- __xe_lrc_indirect_ring_offset()
>>+ *  | Indirect Ring State Page   | 0 or 4k, see    |
>>+ *  |                            | xe_gt_lrc_size()|
>>+ *  +============================+=================+ <- __xe_lrc_wa_bb_offset()
>>+ *  | WA BB Per Ctx              | 4k              |
>>+ *  +============================+=================+ <- xe_bo_size(lrc->bo)
>>+ */
>
>I assume '---' separates parts which are considered engine lrc state, 
>while '===' is for other data which happens to be in the same BO. So 

yes

>for indirect ctx I will use '==='. Just unsure if indirect ring state 
>should in that case also be '==='? Looks like LRC image points to it's 
>ggtt address which would suggest it is equally separate.

correct, indirect state would be another page, separate by ===, since
it's not really part of the LRC, just kept in the same bo.

>
>>+
>>  static struct xe_device *
>>  lrc_to_xe(struct xe_lrc *lrc)
>>  {
>>
>
>Modulo the above:
>
>Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

thanks
Lucas De Marchi

>
>Regards,
>
>Tvrtko
>

[PATCH 5/7] drm/xe/lrc: Remove leftover TODO

[Lucas De Marchi]

There isn't anything to set for CTX_TIMESTAMP handling in the empty
LRC, that is set on every LRC init since it should always start from 0
rather than the value saved in the image after first submission.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 75f4678cb090a..2c735b3679f86 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -603,8 +603,6 @@ static void set_context_control(u32 *regs, struct xe_hw_engine *hwe)
 	if (xe_gt_has_indirect_ring_state(hwe->gt))
 		regs[CTX_CONTEXT_CONTROL] |=
 			_MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE);
-
-	/* TODO: Timestamp */
 }
 
 static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)

-- 
2.49.0

Re: [PATCH 5/7] drm/xe/lrc: Remove leftover TODO

[Matthew Brost]

On Thu, Jul 03, 2025 at 03:41:14PM -0700, Lucas De Marchi wrote:
> There isn't anything to set for CTX_TIMESTAMP handling in the empty
> LRC, that is set on every LRC init since it should always start from 0
> rather than the value saved in the image after first submission.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_lrc.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 75f4678cb090a..2c735b3679f86 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -603,8 +603,6 @@ static void set_context_control(u32 *regs, struct xe_hw_engine *hwe)
>  	if (xe_gt_has_indirect_ring_state(hwe->gt))
>  		regs[CTX_CONTEXT_CONTROL] |=
>  			_MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE);
> -
> -	/* TODO: Timestamp */

While we are here, we can also remove this one:

1066         /*
1067          * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
1068          * via VM bind calls.
1069          */

This was from very early in Xe when we thought we'd maybe not pin kernel
BOs, I don't think we'd ever not pin them. Also the comment actually
doesn't make sense either, as GGTT mapping have nothing to do with VM
bind.

Anyways this patch LGTM:
Reviewed-by: Matthew Brost <matthew.brost@intel.com> 

>  }
>  
>  static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)
> 
> -- 
> 2.49.0
> 

Re: [PATCH 5/7] drm/xe/lrc: Remove leftover TODO

[Lucas De Marchi]

On Mon, Jul 07, 2025 at 10:08:33PM -0700, Matthew Brost wrote:
>On Thu, Jul 03, 2025 at 03:41:14PM -0700, Lucas De Marchi wrote:
>> There isn't anything to set for CTX_TIMESTAMP handling in the empty
>> LRC, that is set on every LRC init since it should always start from 0
>> rather than the value saved in the image after first submission.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_lrc.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>> index 75f4678cb090a..2c735b3679f86 100644
>> --- a/drivers/gpu/drm/xe/xe_lrc.c
>> +++ b/drivers/gpu/drm/xe/xe_lrc.c
>> @@ -603,8 +603,6 @@ static void set_context_control(u32 *regs, struct xe_hw_engine *hwe)
>>  	if (xe_gt_has_indirect_ring_state(hwe->gt))
>>  		regs[CTX_CONTEXT_CONTROL] |=
>>  			_MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STATE_ENABLE);
>> -
>> -	/* TODO: Timestamp */
>
>While we are here, we can also remove this one:
>
>1066         /*
>1067          * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address
>1068          * via VM bind calls.
>1069          */
>
>This was from very early in Xe when we thought we'd maybe not pin kernel
>BOs, I don't think we'd ever not pin them. Also the comment actually
>doesn't make sense either, as GGTT mapping have nothing to do with VM
>bind.
>
>Anyways this patch LGTM:
>Reviewed-by: Matthew Brost <matthew.brost@intel.com>

I will add this comment removal and keep the r-b. Thanks.

Lucas De Marchi

>
>>  }
>>
>>  static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)
>>
>> --
>> 2.49.0
>>

Re: [PATCH 5/7] drm/xe/lrc: Remove leftover TODO

[Summers, Stuart]

On Thu, 2025-07-03 at 15:41 -0700, Lucas De Marchi wrote:
> There isn't anything to set for CTX_TIMESTAMP handling in the empty
> LRC, that is set on every LRC init since it should always start from
> 0
> rather than the value saved in the image after first submission.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_lrc.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> b/drivers/gpu/drm/xe/xe_lrc.c
> index 75f4678cb090a..2c735b3679f86 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -603,8 +603,6 @@ static void set_context_control(u32 *regs, struct
> xe_hw_engine *hwe)
>         if (xe_gt_has_indirect_ring_state(hwe->gt))
>                 regs[CTX_CONTEXT_CONTROL] |=
>                         _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STA
> TE_ENABLE);
> -
> -       /* TODO: Timestamp */

Seems interesting to add your commit comment here instead of the TODO
unless we're already documenting that somewhere else.

Thanks,
Stuart

>  }
>  
>  static void set_memory_based_intr(u32 *regs, struct xe_hw_engine
> *hwe)
> 

Re: [PATCH 5/7] drm/xe/lrc: Remove leftover TODO

[Lucas De Marchi]

On Wed, Jul 09, 2025 at 07:37:02PM +0000, Stuart Summers wrote:
>On Thu, 2025-07-03 at 15:41 -0700, Lucas De Marchi wrote:
>> There isn't anything to set for CTX_TIMESTAMP handling in the empty
>> LRC, that is set on every LRC init since it should always start from
>> 0
>> rather than the value saved in the image after first submission.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_lrc.c | 2 --
>>  1 file changed, 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_lrc.c
>> b/drivers/gpu/drm/xe/xe_lrc.c
>> index 75f4678cb090a..2c735b3679f86 100644
>> --- a/drivers/gpu/drm/xe/xe_lrc.c
>> +++ b/drivers/gpu/drm/xe/xe_lrc.c
>> @@ -603,8 +603,6 @@ static void set_context_control(u32 *regs, struct
>> xe_hw_engine *hwe)
>>         if (xe_gt_has_indirect_ring_state(hwe->gt))
>>                 regs[CTX_CONTEXT_CONTROL] |=
>>                         _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING_STA
>> TE_ENABLE);
>> -
>> -       /* TODO: Timestamp */
>
>Seems interesting to add your commit comment here instead of the TODO
>unless we're already documenting that somewhere else.

It seems counter productive to add a comment in a random place about
things that are done elsewhere. If this was "the normal place to do it,
but handled elsewhere", ok. But this is not and it's still here because
it went unnoticed when the timestamp handling was added.

Lucas De Marchi

Re: [PATCH 5/7] drm/xe/lrc: Remove leftover TODO

[Summers, Stuart]

On Wed, 2025-07-09 at 16:24 -0500, Lucas De Marchi wrote:
> On Wed, Jul 09, 2025 at 07:37:02PM +0000, Stuart Summers wrote:
> > On Thu, 2025-07-03 at 15:41 -0700, Lucas De Marchi wrote:
> > > There isn't anything to set for CTX_TIMESTAMP handling in the
> > > empty
> > > LRC, that is set on every LRC init since it should always start
> > > from
> > > 0
> > > rather than the value saved in the image after first submission.
> > > 
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_lrc.c | 2 --
> > >  1 file changed, 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c
> > > b/drivers/gpu/drm/xe/xe_lrc.c
> > > index 75f4678cb090a..2c735b3679f86 100644
> > > --- a/drivers/gpu/drm/xe/xe_lrc.c
> > > +++ b/drivers/gpu/drm/xe/xe_lrc.c
> > > @@ -603,8 +603,6 @@ static void set_context_control(u32 *regs,
> > > struct
> > > xe_hw_engine *hwe)
> > >         if (xe_gt_has_indirect_ring_state(hwe->gt))
> > >                 regs[CTX_CONTEXT_CONTROL] |=
> > >                         _MASKED_BIT_ENABLE(CTX_CTRL_INDIRECT_RING
> > > _STA
> > > TE_ENABLE);
> > > -
> > > -       /* TODO: Timestamp */
> > 
> > Seems interesting to add your commit comment here instead of the
> > TODO
> > unless we're already documenting that somewhere else.
> 
> It seems counter productive to add a comment in a random place about
> things that are done elsewhere. If this was "the normal place to do
> it,
> but handled elsewhere", ok. But this is not and it's still here
> because
> it went unnoticed when the timestamp handling was added.

I'm just thinking about implicit zeroing, but what you said here makes
sense too. I agree the documentation would be better elsewhere and not
really tied to the TODO:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>

> 
> Lucas De Marchi

[PATCH 6/7] drm/xe/gt: Drop third submission for default context

[Lucas De Marchi]

There's no need to submit the nop job again on the first queue. Any
state needed is already saved when the first LRC is switched out. The
comment is a little misleading regarding indirect W/A: first of all
there's still no indirect W/A enabled and secondly, even after they are,
there's no need to submit this job again for having their state
propagated: the indirect W/A will actually run on every LRC switch.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 67425e37c2187..439e7c703ed84 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -361,14 +361,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
 			goto put_nop_q;
 		}
 
-		/* Reload golden LRC to record the effect of any indirect W/A */
-		err = emit_nop_job(gt, q);
-		if (err) {
-			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",
-				  hwe->name, ERR_PTR(err), q->guc->id);
-			goto put_nop_q;
-		}
-
 		xe_map_memcpy_from(xe, default_lrc,
 				   &q->lrc[0]->bo->vmap,
 				   xe_lrc_pphwsp_offset(q->lrc[0]),

-- 
2.49.0

Re: [PATCH 6/7] drm/xe/gt: Drop third submission for default context

[Tvrtko Ursulin]

On 03/07/2025 23:41, Lucas De Marchi wrote:
> There's no need to submit the nop job again on the first queue. Any
> state needed is already saved when the first LRC is switched out. The
> comment is a little misleading regarding indirect W/A: first of all
> there's still no indirect W/A enabled and secondly, even after they are,
> there's no need to submit this job again for having their state
> propagated: the indirect W/A will actually run on every LRC switch.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>   drivers/gpu/drm/xe/xe_gt.c | 8 --------
>   1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 67425e37c2187..439e7c703ed84 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -361,14 +361,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
>   			goto put_nop_q;
>   		}
>   
> -		/* Reload golden LRC to record the effect of any indirect W/A */
> -		err = emit_nop_job(gt, q);
> -		if (err) {
> -			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",
> -				  hwe->name, ERR_PTR(err), q->guc->id);
> -			goto put_nop_q;
> -		}
> -
>   		xe_map_memcpy_from(xe, default_lrc,
>   				   &q->lrc[0]->bo->vmap,
>   				   xe_lrc_pphwsp_offset(q->lrc[0]),
> 

Wasn't it also racy to memcpy from q's LRC without guaranteeing context 
save had completed? I don't think dma_fence_wait in emit_nop_job 
guarantees it. If that is so this patch should actually have Fixes: 
added and commit message adjusted accordingly.

Regards,

Tvrtko

Re: [PATCH 6/7] drm/xe/gt: Drop third submission for default context

[Lucas De Marchi]

On Fri, Jul 04, 2025 at 12:21:50PM +0100, Tvrtko Ursulin wrote:
>
>On 03/07/2025 23:41, Lucas De Marchi wrote:
>>There's no need to submit the nop job again on the first queue. Any
>>state needed is already saved when the first LRC is switched out. The
>>comment is a little misleading regarding indirect W/A: first of all
>>there's still no indirect W/A enabled and secondly, even after they are,
>>there's no need to submit this job again for having their state
>>propagated: the indirect W/A will actually run on every LRC switch.
>>
>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>---
>>  drivers/gpu/drm/xe/xe_gt.c | 8 --------
>>  1 file changed, 8 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>>index 67425e37c2187..439e7c703ed84 100644
>>--- a/drivers/gpu/drm/xe/xe_gt.c
>>+++ b/drivers/gpu/drm/xe/xe_gt.c
>>@@ -361,14 +361,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
>>  			goto put_nop_q;
>>  		}
>>-		/* Reload golden LRC to record the effect of any indirect W/A */
>>-		err = emit_nop_job(gt, q);
>>-		if (err) {
>>-			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",
>>-				  hwe->name, ERR_PTR(err), q->guc->id);
>>-			goto put_nop_q;
>>-		}
>>-
>>  		xe_map_memcpy_from(xe, default_lrc,
>>  				   &q->lrc[0]->bo->vmap,
>>  				   xe_lrc_pphwsp_offset(q->lrc[0]),
>>
>
>Wasn't it also racy to memcpy from q's LRC without guaranteeing 
>context save had completed? I don't think dma_fence_wait in 
>emit_nop_job guarantees it. If that is so this patch should actually 
>have Fixes: added and commit message adjusted accordingly.

I don't think it really fixes anything, it's just pointless to do it.
It would just save the same information from the first time it executed
even if there was a race.

Lucas De Marchi

>
>Regards,
>
>Tvrtko
>

Re: [PATCH 6/7] drm/xe/gt: Drop third submission for default context

[Matthew Brost]

On Mon, Jul 07, 2025 at 09:55:58PM -0500, Lucas De Marchi wrote:
> On Fri, Jul 04, 2025 at 12:21:50PM +0100, Tvrtko Ursulin wrote:
> > 
> > On 03/07/2025 23:41, Lucas De Marchi wrote:
> > > There's no need to submit the nop job again on the first queue. Any
> > > state needed is already saved when the first LRC is switched out. The
> > > comment is a little misleading regarding indirect W/A: first of all
> > > there's still no indirect W/A enabled and secondly, even after they are,
> > > there's no need to submit this job again for having their state
> > > propagated: the indirect W/A will actually run on every LRC switch.
> > > 
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_gt.c | 8 --------
> > >  1 file changed, 8 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > > index 67425e37c2187..439e7c703ed84 100644
> > > --- a/drivers/gpu/drm/xe/xe_gt.c
> > > +++ b/drivers/gpu/drm/xe/xe_gt.c
> > > @@ -361,14 +361,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
> > >  			goto put_nop_q;
> > >  		}
> > > -		/* Reload golden LRC to record the effect of any indirect W/A */
> > > -		err = emit_nop_job(gt, q);
> > > -		if (err) {
> > > -			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",
> > > -				  hwe->name, ERR_PTR(err), q->guc->id);
> > > -			goto put_nop_q;
> > > -		}
> > > -
> > >  		xe_map_memcpy_from(xe, default_lrc,
> > >  				   &q->lrc[0]->bo->vmap,
> > >  				   xe_lrc_pphwsp_offset(q->lrc[0]),
> > > 
> > 
> > Wasn't it also racy to memcpy from q's LRC without guaranteeing context
> > save had completed? I don't think dma_fence_wait in emit_nop_job
> > guarantees it. If that is so this patch should actually have Fixes:
> > added and commit message adjusted accordingly.
> 
> I don't think it really fixes anything, it's just pointless to do it.
> It would just save the same information from the first time it executed
> even if there was a race.
> 

Agree with Lucas, this pointless yet harmless.

Matt

> Lucas De Marchi
> 
> > 
> > Regards,
> > 
> > Tvrtko
> > 

Re: [PATCH 6/7] drm/xe/gt: Drop third submission for default context

[Matthew Brost]

On Mon, Jul 07, 2025 at 09:59:57PM -0700, Matthew Brost wrote:
> On Mon, Jul 07, 2025 at 09:55:58PM -0500, Lucas De Marchi wrote:
> > On Fri, Jul 04, 2025 at 12:21:50PM +0100, Tvrtko Ursulin wrote:
> > > 
> > > On 03/07/2025 23:41, Lucas De Marchi wrote:
> > > > There's no need to submit the nop job again on the first queue. Any
> > > > state needed is already saved when the first LRC is switched out. The
> > > > comment is a little misleading regarding indirect W/A: first of all
> > > > there's still no indirect W/A enabled and secondly, even after they are,
> > > > there's no need to submit this job again for having their state
> > > > propagated: the indirect W/A will actually run on every LRC switch.
> > > > 
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/xe/xe_gt.c | 8 --------
> > > >  1 file changed, 8 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> > > > index 67425e37c2187..439e7c703ed84 100644
> > > > --- a/drivers/gpu/drm/xe/xe_gt.c
> > > > +++ b/drivers/gpu/drm/xe/xe_gt.c
> > > > @@ -361,14 +361,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
> > > >  			goto put_nop_q;
> > > >  		}
> > > > -		/* Reload golden LRC to record the effect of any indirect W/A */
> > > > -		err = emit_nop_job(gt, q);
> > > > -		if (err) {
> > > > -			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",
> > > > -				  hwe->name, ERR_PTR(err), q->guc->id);
> > > > -			goto put_nop_q;
> > > > -		}
> > > > -
> > > >  		xe_map_memcpy_from(xe, default_lrc,
> > > >  				   &q->lrc[0]->bo->vmap,
> > > >  				   xe_lrc_pphwsp_offset(q->lrc[0]),
> > > > 
> > > 
> > > Wasn't it also racy to memcpy from q's LRC without guaranteeing context
> > > save had completed? I don't think dma_fence_wait in emit_nop_job
> > > guarantees it. If that is so this patch should actually have Fixes:
> > > added and commit message adjusted accordingly.
> > 
> > I don't think it really fixes anything, it's just pointless to do it.
> > It would just save the same information from the first time it executed
> > even if there was a race.
> > 
> 
> Agree with Lucas, this pointless yet harmless.
> 

Forgot to include:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

> Matt
> 
> > Lucas De Marchi
> > 
> > > 
> > > Regards,
> > > 
> > > Tvrtko
> > > 

Re: [PATCH 6/7] drm/xe/gt: Drop third submission for default context

[Tvrtko Ursulin]

On 08/07/2025 05:59, Matthew Brost wrote:
> On Mon, Jul 07, 2025 at 09:55:58PM -0500, Lucas De Marchi wrote:
>> On Fri, Jul 04, 2025 at 12:21:50PM +0100, Tvrtko Ursulin wrote:
>>>
>>> On 03/07/2025 23:41, Lucas De Marchi wrote:
>>>> There's no need to submit the nop job again on the first queue. Any
>>>> state needed is already saved when the first LRC is switched out. The
>>>> comment is a little misleading regarding indirect W/A: first of all
>>>> there's still no indirect W/A enabled and secondly, even after they are,
>>>> there's no need to submit this job again for having their state
>>>> propagated: the indirect W/A will actually run on every LRC switch.
>>>>
>>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> ---
>>>>   drivers/gpu/drm/xe/xe_gt.c | 8 --------
>>>>   1 file changed, 8 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>>>> index 67425e37c2187..439e7c703ed84 100644
>>>> --- a/drivers/gpu/drm/xe/xe_gt.c
>>>> +++ b/drivers/gpu/drm/xe/xe_gt.c
>>>> @@ -361,14 +361,6 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt)
>>>>   			goto put_nop_q;
>>>>   		}
>>>> -		/* Reload golden LRC to record the effect of any indirect W/A */
>>>> -		err = emit_nop_job(gt, q);
>>>> -		if (err) {
>>>> -			xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n",
>>>> -				  hwe->name, ERR_PTR(err), q->guc->id);
>>>> -			goto put_nop_q;
>>>> -		}
>>>> -
>>>>   		xe_map_memcpy_from(xe, default_lrc,
>>>>   				   &q->lrc[0]->bo->vmap,
>>>>   				   xe_lrc_pphwsp_offset(q->lrc[0]),
>>>>
>>>
>>> Wasn't it also racy to memcpy from q's LRC without guaranteeing context
>>> save had completed? I don't think dma_fence_wait in emit_nop_job
>>> guarantees it. If that is so this patch should actually have Fixes:
>>> added and commit message adjusted accordingly.
>>
>> I don't think it really fixes anything, it's just pointless to do it.
>> It would just save the same information from the first time it executed
>> even if there was a race.
>>
> 
> Agree with Lucas, this pointless yet harmless.

If you guys are certain the way hardware saves the context has no 
opportunity to make the memcpy see a "corrupt" state then okay.

Otherwise I was thinking split/incomplete qw writes when context save 
races with the memcpy. If for example they would be written by 2x dw by 
the hw. Or whether context save has any guarantees on the order of 
writes. Might be all sprinkled out by units randomly. Something along 
those lines.

Regards,

Tvrtko

[PATCH 7/7] drm/xe: Waste fewer instructions in emit_wa_job()

[Lucas De Marchi]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

I was debugging some unrelated issue and noticed the current code was
very verbose. We can improve it easily by using the more common batch
buffer building pattern.

Before:
                bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
     c4d:       41 8b 56 10             mov    0x10(%r14),%edx
     c51:       49 8b 4e 08             mov    0x8(%r14),%rcx
     c55:       8d 72 01                lea    0x1(%rdx),%esi
     c58:       41 89 76 10             mov    %esi,0x10(%r14)
     c5c:       c7 04 91 01 00 08 15    movl   $0x15080001,(%rcx,%rdx,4)
                        bb->cs[bb->len++] = entry->reg.addr;
     c63:       8b 08                   mov    (%rax),%ecx
     c65:       41 8b 56 10             mov    0x10(%r14),%edx
     c69:       49 8b 76 08             mov    0x8(%r14),%rsi
     c6d:       81 e1 ff ff 3f 00       and    $0x3fffff,%ecx
     c73:       8d 7a 01                lea    0x1(%rdx),%edi
     c76:       41 89 7e 10             mov    %edi,0x10(%r14)
     c7a:       89 0c 96                mov    %ecx,(%rsi,%rdx,4)
 ..etc..

After:
                *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
     c52:       41 c7 04 24 01 00 08    movl   $0x15080001,(%r12)
     c59:       15
                        *cs++ = entry->reg.addr;
     c5a:       8b 10                   mov    (%rax),%edx
 ..etc..

Resulting in the following binary change:

	add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-348 (-348)
	Function                                     old     new   delta
	xe_gt_record_default_lrcs.cold               304     296      -8
	xe_gt_record_default_lrcs                   2200    1860    -340
	Total: Before=13554, After=13206, chg -2.57%

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/xe/xe_gt.c  | 76 ++++++++++++++++++++++++---------------------
 drivers/gpu/drm/xe/xe_lrc.c | 12 ++++---
 drivers/gpu/drm/xe/xe_lrc.h |  2 +-
 3 files changed, 49 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 439e7c703ed84..92c92f8aeae05 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -194,6 +194,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 	unsigned long idx;
 	struct xe_bb *bb;
 	size_t bb_len;
+	u32 *cs;
 
 	/* count RMW registers as those will be handled separately */
 	xa_for_each(&sr->xa, idx, entry) {
@@ -221,10 +222,12 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 	if (IS_ERR(bb))
 		return PTR_ERR(bb);
 
+	cs = bb->cs;
+
 	if (count) {
 		/* Emit single LRI with all non RMW regs: 2 dw per reg */
 
-		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
+		*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
 
 		xa_for_each(&sr->xa, idx, entry) {
 			struct xe_reg reg = entry->reg;
@@ -239,8 +242,8 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 
 			val |= entry->set_bits;
 
-			bb->cs[bb->len++] = reg.addr;
-			bb->cs[bb->len++] = val;
+			*cs++ = reg.addr;
+			*cs++ = val;
 			xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val);
 		}
 	}
@@ -252,46 +255,49 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
 			if (entry->reg.masked || entry->clr_bits == ~0)
 				continue;
 
-			bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
-			bb->cs[bb->len++] = entry->reg.addr;
-			bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
-
-			bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
-					    MI_LRI_LRM_CS_MMIO;
-			bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr;
-			bb->cs[bb->len++] = entry->clr_bits;
-			bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr;
-			bb->cs[bb->len++] = entry->set_bits;
-
-			bb->cs[bb->len++] = MI_MATH(8);
-			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0);
-			bb->cs[bb->len++] = CS_ALU_INSTR_LOADINV(SRCB, REG1);
-			bb->cs[bb->len++] = CS_ALU_INSTR_AND;
-			bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU);
-			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0);
-			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCB, REG2);
-			bb->cs[bb->len++] = CS_ALU_INSTR_OR;
-			bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU);
-
-			bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO;
-			bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
-			bb->cs[bb->len++] = entry->reg.addr;
+			*cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
+			*cs++ = entry->reg.addr;
+			*cs++ = CS_GPR_REG(0, 0).addr;
+
+			*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
+				MI_LRI_LRM_CS_MMIO;
+			*cs++ = CS_GPR_REG(0, 1).addr;
+			*cs++ = entry->clr_bits;
+			*cs++ = CS_GPR_REG(0, 2).addr;
+			*cs++ = entry->set_bits;
+
+			*cs++ = MI_MATH(8);
+			*cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
+			*cs++ = CS_ALU_INSTR_LOADINV(SRCB, REG1);
+			*cs++ = CS_ALU_INSTR_AND;
+			*cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
+			*cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
+			*cs++ = CS_ALU_INSTR_LOAD(SRCB, REG2);
+			*cs++ = CS_ALU_INSTR_OR;
+			*cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
+
+			*cs++ = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO;
+			*cs++ = CS_GPR_REG(0, 0).addr;
+			*cs++ = entry->reg.addr;
 
 			xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x\n",
 				  entry->reg.addr, entry->clr_bits, entry->set_bits);
 		}
 
 		/* reset used GPR */
-		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | MI_LRI_LRM_CS_MMIO;
-		bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
-		bb->cs[bb->len++] = 0;
-		bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr;
-		bb->cs[bb->len++] = 0;
-		bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr;
-		bb->cs[bb->len++] = 0;
+		*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) |
+			MI_LRI_LRM_CS_MMIO;
+		*cs++ = CS_GPR_REG(0, 0).addr;
+		*cs++ = 0;
+		*cs++ = CS_GPR_REG(0, 1).addr;
+		*cs++ = 0;
+		*cs++ = CS_GPR_REG(0, 2).addr;
+		*cs++ = 0;
 	}
 
-	xe_lrc_emit_hwe_state_instructions(q, bb);
+	cs = xe_lrc_emit_hwe_state_instructions(q, cs);
+
+	bb->len = cs - bb->cs;
 
 	if (bb->len)
 		xe_gt_dbg(gt, "LRC WA %s save-restore batch: %u dw", sr->name, bb->len);
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 2c735b3679f86..897aebaf4c1f6 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1790,7 +1790,7 @@ static const struct instr_state xe_hpg_svg_state[] = {
 	{ .instr = CMD_3DSTATE_DRAWING_RECTANGLE, .num_dw = 4 },
 };
 
-void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb)
+u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs)
 {
 	struct xe_gt *gt = q->hwe->gt;
 	struct xe_device *xe = gt_to_xe(gt);
@@ -1825,7 +1825,7 @@ void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *b
 	if (!state_table) {
 		xe_gt_dbg(gt, "No non-register state to emit on graphics ver %d.%02d\n",
 			  GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);
-		return;
+		return cs;
 	}
 
 	for (int i = 0; i < state_table_size; i++) {
@@ -1848,12 +1848,14 @@ void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *b
 		    instr == CMD_3DSTATE_DRAWING_RECTANGLE)
 			instr = CMD_3DSTATE_DRAWING_RECTANGLE_FAST;
 
-		bb->cs[bb->len] = instr;
+		*cs = instr;
 		if (!is_single_dw)
-			bb->cs[bb->len] |= (num_dw - 2);
+			*cs |= (num_dw - 2);
 
-		bb->len += num_dw;
+		cs += num_dw;
 	}
+
+	return cs;
 }
 
 struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc)
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index eb6e8de8c939e..b6c8053c581ba 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -112,7 +112,7 @@ void xe_lrc_dump_default(struct drm_printer *p,
 			 struct xe_gt *gt,
 			 enum xe_engine_class);
 
-void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb);
+u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs);
 
 struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc);
 void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);

-- 
2.49.0

Re: [PATCH 7/7] drm/xe: Waste fewer instructions in emit_wa_job()

[Matthew Brost]

On Thu, Jul 03, 2025 at 03:41:16PM -0700, Lucas De Marchi wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> 
> I was debugging some unrelated issue and noticed the current code was
> very verbose. We can improve it easily by using the more common batch
> buffer building pattern.
> 

This patch doesn't touch a hot path, but it's still a good cleanup.

xe_ring_ops.c uses this coding pattern and is a hot path, so we should
likely apply the same pattern there as well.

Anyway:
Reviewed-by: Matthew Brost matthew.brost@intel.com

Matt

> Before:
>                 bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
>      c4d:       41 8b 56 10             mov    0x10(%r14),%edx
>      c51:       49 8b 4e 08             mov    0x8(%r14),%rcx
>      c55:       8d 72 01                lea    0x1(%rdx),%esi
>      c58:       41 89 76 10             mov    %esi,0x10(%r14)
>      c5c:       c7 04 91 01 00 08 15    movl   $0x15080001,(%rcx,%rdx,4)
>                         bb->cs[bb->len++] = entry->reg.addr;
>      c63:       8b 08                   mov    (%rax),%ecx
>      c65:       41 8b 56 10             mov    0x10(%r14),%edx
>      c69:       49 8b 76 08             mov    0x8(%r14),%rsi
>      c6d:       81 e1 ff ff 3f 00       and    $0x3fffff,%ecx
>      c73:       8d 7a 01                lea    0x1(%rdx),%edi
>      c76:       41 89 7e 10             mov    %edi,0x10(%r14)
>      c7a:       89 0c 96                mov    %ecx,(%rsi,%rdx,4)
>  ..etc..
> 
> After:
>                 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
>      c52:       41 c7 04 24 01 00 08    movl   $0x15080001,(%r12)
>      c59:       15
>                         *cs++ = entry->reg.addr;
>      c5a:       8b 10                   mov    (%rax),%edx
>  ..etc..
> 
> Resulting in the following binary change:
> 
> 	add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-348 (-348)
> 	Function                                     old     new   delta
> 	xe_gt_record_default_lrcs.cold               304     296      -8
> 	xe_gt_record_default_lrcs                   2200    1860    -340
> 	Total: Before=13554, After=13206, chg -2.57%
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt.c  | 76 ++++++++++++++++++++++++---------------------
>  drivers/gpu/drm/xe/xe_lrc.c | 12 ++++---
>  drivers/gpu/drm/xe/xe_lrc.h |  2 +-
>  3 files changed, 49 insertions(+), 41 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
> index 439e7c703ed84..92c92f8aeae05 100644
> --- a/drivers/gpu/drm/xe/xe_gt.c
> +++ b/drivers/gpu/drm/xe/xe_gt.c
> @@ -194,6 +194,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>  	unsigned long idx;
>  	struct xe_bb *bb;
>  	size_t bb_len;
> +	u32 *cs;
>  
>  	/* count RMW registers as those will be handled separately */
>  	xa_for_each(&sr->xa, idx, entry) {
> @@ -221,10 +222,12 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>  	if (IS_ERR(bb))
>  		return PTR_ERR(bb);
>  
> +	cs = bb->cs;
> +
>  	if (count) {
>  		/* Emit single LRI with all non RMW regs: 2 dw per reg */
>  
> -		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
> +		*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count);
>  
>  		xa_for_each(&sr->xa, idx, entry) {
>  			struct xe_reg reg = entry->reg;
> @@ -239,8 +242,8 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>  
>  			val |= entry->set_bits;
>  
> -			bb->cs[bb->len++] = reg.addr;
> -			bb->cs[bb->len++] = val;
> +			*cs++ = reg.addr;
> +			*cs++ = val;
>  			xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val);
>  		}
>  	}
> @@ -252,46 +255,49 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q)
>  			if (entry->reg.masked || entry->clr_bits == ~0)
>  				continue;
>  
> -			bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
> -			bb->cs[bb->len++] = entry->reg.addr;
> -			bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
> -
> -			bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
> -					    MI_LRI_LRM_CS_MMIO;
> -			bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr;
> -			bb->cs[bb->len++] = entry->clr_bits;
> -			bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr;
> -			bb->cs[bb->len++] = entry->set_bits;
> -
> -			bb->cs[bb->len++] = MI_MATH(8);
> -			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0);
> -			bb->cs[bb->len++] = CS_ALU_INSTR_LOADINV(SRCB, REG1);
> -			bb->cs[bb->len++] = CS_ALU_INSTR_AND;
> -			bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU);
> -			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0);
> -			bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCB, REG2);
> -			bb->cs[bb->len++] = CS_ALU_INSTR_OR;
> -			bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU);
> -
> -			bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO;
> -			bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
> -			bb->cs[bb->len++] = entry->reg.addr;
> +			*cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
> +			*cs++ = entry->reg.addr;
> +			*cs++ = CS_GPR_REG(0, 0).addr;
> +
> +			*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
> +				MI_LRI_LRM_CS_MMIO;
> +			*cs++ = CS_GPR_REG(0, 1).addr;
> +			*cs++ = entry->clr_bits;
> +			*cs++ = CS_GPR_REG(0, 2).addr;
> +			*cs++ = entry->set_bits;
> +
> +			*cs++ = MI_MATH(8);
> +			*cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
> +			*cs++ = CS_ALU_INSTR_LOADINV(SRCB, REG1);
> +			*cs++ = CS_ALU_INSTR_AND;
> +			*cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
> +			*cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0);
> +			*cs++ = CS_ALU_INSTR_LOAD(SRCB, REG2);
> +			*cs++ = CS_ALU_INSTR_OR;
> +			*cs++ = CS_ALU_INSTR_STORE(REG0, ACCU);
> +
> +			*cs++ = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO;
> +			*cs++ = CS_GPR_REG(0, 0).addr;
> +			*cs++ = entry->reg.addr;
>  
>  			xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x\n",
>  				  entry->reg.addr, entry->clr_bits, entry->set_bits);
>  		}
>  
>  		/* reset used GPR */
> -		bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | MI_LRI_LRM_CS_MMIO;
> -		bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr;
> -		bb->cs[bb->len++] = 0;
> -		bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr;
> -		bb->cs[bb->len++] = 0;
> -		bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr;
> -		bb->cs[bb->len++] = 0;
> +		*cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) |
> +			MI_LRI_LRM_CS_MMIO;
> +		*cs++ = CS_GPR_REG(0, 0).addr;
> +		*cs++ = 0;
> +		*cs++ = CS_GPR_REG(0, 1).addr;
> +		*cs++ = 0;
> +		*cs++ = CS_GPR_REG(0, 2).addr;
> +		*cs++ = 0;
>  	}
>  
> -	xe_lrc_emit_hwe_state_instructions(q, bb);
> +	cs = xe_lrc_emit_hwe_state_instructions(q, cs);
> +
> +	bb->len = cs - bb->cs;
>  
>  	if (bb->len)
>  		xe_gt_dbg(gt, "LRC WA %s save-restore batch: %u dw", sr->name, bb->len);
> diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
> index 2c735b3679f86..897aebaf4c1f6 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.c
> +++ b/drivers/gpu/drm/xe/xe_lrc.c
> @@ -1790,7 +1790,7 @@ static const struct instr_state xe_hpg_svg_state[] = {
>  	{ .instr = CMD_3DSTATE_DRAWING_RECTANGLE, .num_dw = 4 },
>  };
>  
> -void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb)
> +u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs)
>  {
>  	struct xe_gt *gt = q->hwe->gt;
>  	struct xe_device *xe = gt_to_xe(gt);
> @@ -1825,7 +1825,7 @@ void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *b
>  	if (!state_table) {
>  		xe_gt_dbg(gt, "No non-register state to emit on graphics ver %d.%02d\n",
>  			  GRAPHICS_VER(xe), GRAPHICS_VERx100(xe) % 100);
> -		return;
> +		return cs;
>  	}
>  
>  	for (int i = 0; i < state_table_size; i++) {
> @@ -1848,12 +1848,14 @@ void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *b
>  		    instr == CMD_3DSTATE_DRAWING_RECTANGLE)
>  			instr = CMD_3DSTATE_DRAWING_RECTANGLE_FAST;
>  
> -		bb->cs[bb->len] = instr;
> +		*cs = instr;
>  		if (!is_single_dw)
> -			bb->cs[bb->len] |= (num_dw - 2);
> +			*cs |= (num_dw - 2);
>  
> -		bb->len += num_dw;
> +		cs += num_dw;
>  	}
> +
> +	return cs;
>  }
>  
>  struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc)
> diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
> index eb6e8de8c939e..b6c8053c581ba 100644
> --- a/drivers/gpu/drm/xe/xe_lrc.h
> +++ b/drivers/gpu/drm/xe/xe_lrc.h
> @@ -112,7 +112,7 @@ void xe_lrc_dump_default(struct drm_printer *p,
>  			 struct xe_gt *gt,
>  			 enum xe_engine_class);
>  
> -void xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, struct xe_bb *bb);
> +u32 *xe_lrc_emit_hwe_state_instructions(struct xe_exec_queue *q, u32 *cs);
>  
>  struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc);
>  void xe_lrc_snapshot_capture_delayed(struct xe_lrc_snapshot *snapshot);
> 
> -- 
> 2.49.0
> 

✗ CI.checkpatch: warning for drm/xe: LRC refactors

[Patchwork]

== Series Details ==

Series: drm/xe: LRC refactors
URL   : https://patchwork.freedesktop.org/series/151152/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 305c85360916b124e2cd93ed233df6cc7d56d799
Author: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Date:   Thu Jul 3 15:41:16 2025 -0700

    drm/xe: Waste fewer instructions in emit_wa_job()
    
    I was debugging some unrelated issue and noticed the current code was
    very verbose. We can improve it easily by using the more common batch
    buffer building pattern.
    
    Before:
                    bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
         c4d:       41 8b 56 10             mov    0x10(%r14),%edx
         c51:       49 8b 4e 08             mov    0x8(%r14),%rcx
         c55:       8d 72 01                lea    0x1(%rdx),%esi
         c58:       41 89 76 10             mov    %esi,0x10(%r14)
         c5c:       c7 04 91 01 00 08 15    movl   $0x15080001,(%rcx,%rdx,4)
                            bb->cs[bb->len++] = entry->reg.addr;
         c63:       8b 08                   mov    (%rax),%ecx
         c65:       41 8b 56 10             mov    0x10(%r14),%edx
         c69:       49 8b 76 08             mov    0x8(%r14),%rsi
         c6d:       81 e1 ff ff 3f 00       and    $0x3fffff,%ecx
         c73:       8d 7a 01                lea    0x1(%rdx),%edi
         c76:       41 89 7e 10             mov    %edi,0x10(%r14)
         c7a:       89 0c 96                mov    %ecx,(%rsi,%rdx,4)
     ..etc..
    
    After:
                    *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;
         c52:       41 c7 04 24 01 00 08    movl   $0x15080001,(%r12)
         c59:       15
                            *cs++ = entry->reg.addr;
         c5a:       8b 10                   mov    (%rax),%edx
     ..etc..
    
    Resulting in the following binary change:
    
            add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-348 (-348)
            Function                                     old     new   delta
            xe_gt_record_default_lrcs.cold               304     296      -8
            xe_gt_record_default_lrcs                   2200    1860    -340
            Total: Before=13554, After=13206, chg -2.57%
    
    Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
    Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
    Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
+ /mt/dim checkpatch 5bf9f9da41be2c8562f5d95aba623d27cb2aecf9 drm-intel
6af7e5f55281 drm/xe/lrc: Reduce scope of empty lrc data
5d1424e058d9 drm/xe: Count dwords before allocating
d0cd1b0fba3a drm/xe/gt: Extract emit_job_sync()
4b5e71dcc1c9 drm/xe/lrc: Add table with LRC layout
f1d4a216d666 drm/xe/lrc: Remove leftover TODO
8bcd747d5f0f drm/xe/gt: Drop third submission for default context
305c85360916 drm/xe: Waste fewer instructions in emit_wa_job()
-:11: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#11: 
                bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO;

total: 0 errors, 1 warnings, 0 checks, 152 lines checked

✓ CI.KUnit: success for drm/xe: LRC refactors

[Patchwork]

== Series Details ==

Series: drm/xe: LRC refactors
URL   : https://patchwork.freedesktop.org/series/151152/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:49:51] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:49:55] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:50:22] Starting KUnit Kernel (1/1)...
[22:50:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:50:22] ================== guc_buf (11 subtests) ===================
[22:50:22] [PASSED] test_smallest
[22:50:22] [PASSED] test_largest
[22:50:22] [PASSED] test_granular
[22:50:22] [PASSED] test_unique
[22:50:22] [PASSED] test_overlap
[22:50:22] [PASSED] test_reusable
[22:50:22] [PASSED] test_too_big
[22:50:22] [PASSED] test_flush
[22:50:22] [PASSED] test_lookup
[22:50:22] [PASSED] test_data
[22:50:22] [PASSED] test_class
[22:50:22] ===================== [PASSED] guc_buf =====================
[22:50:22] =================== guc_dbm (7 subtests) ===================
[22:50:22] [PASSED] test_empty
[22:50:22] [PASSED] test_default
[22:50:22] ======================== test_size  ========================
[22:50:22] [PASSED] 4
[22:50:22] [PASSED] 8
[22:50:22] [PASSED] 32
[22:50:22] [PASSED] 256
[22:50:22] ==================== [PASSED] test_size ====================
[22:50:22] ======================= test_reuse  ========================
[22:50:22] [PASSED] 4
[22:50:22] [PASSED] 8
[22:50:22] [PASSED] 32
[22:50:22] [PASSED] 256
[22:50:22] =================== [PASSED] test_reuse ====================
[22:50:22] =================== test_range_overlap  ====================
[22:50:22] [PASSED] 4
[22:50:22] [PASSED] 8
[22:50:22] [PASSED] 32
[22:50:22] [PASSED] 256
[22:50:22] =============== [PASSED] test_range_overlap ================
[22:50:22] =================== test_range_compact  ====================
[22:50:22] [PASSED] 4
[22:50:22] [PASSED] 8
[22:50:22] [PASSED] 32
[22:50:22] [PASSED] 256
[22:50:22] =============== [PASSED] test_range_compact ================
[22:50:22] ==================== test_range_spare  =====================
[22:50:22] [PASSED] 4
[22:50:22] [PASSED] 8
[22:50:22] [PASSED] 32
[22:50:22] [PASSED] 256
[22:50:22] ================ [PASSED] test_range_spare =================
[22:50:22] ===================== [PASSED] guc_dbm =====================
[22:50:22] =================== guc_idm (6 subtests) ===================
[22:50:22] [PASSED] bad_init
[22:50:22] [PASSED] no_init
[22:50:22] [PASSED] init_fini
[22:50:22] [PASSED] check_used
[22:50:22] [PASSED] check_quota
[22:50:22] [PASSED] check_all
[22:50:22] ===================== [PASSED] guc_idm =====================
[22:50:22] ================== no_relay (3 subtests) ===================
[22:50:22] [PASSED] xe_drops_guc2pf_if_not_ready
[22:50:22] [PASSED] xe_drops_guc2vf_if_not_ready
[22:50:22] [PASSED] xe_rejects_send_if_not_ready
[22:50:22] ==================== [PASSED] no_relay =====================
[22:50:22] ================== pf_relay (14 subtests) ==================
[22:50:22] [PASSED] pf_rejects_guc2pf_too_short
[22:50:22] [PASSED] pf_rejects_guc2pf_too_long
[22:50:22] [PASSED] pf_rejects_guc2pf_no_payload
[22:50:22] [PASSED] pf_fails_no_payload
[22:50:22] [PASSED] pf_fails_bad_origin
[22:50:22] [PASSED] pf_fails_bad_type
[22:50:22] [PASSED] pf_txn_reports_error
[22:50:22] [PASSED] pf_txn_sends_pf2guc
[22:50:22] [PASSED] pf_sends_pf2guc
[22:50:22] [SKIPPED] pf_loopback_nop
[22:50:22] [SKIPPED] pf_loopback_echo
[22:50:22] [SKIPPED] pf_loopback_fail
[22:50:22] [SKIPPED] pf_loopback_busy
[22:50:22] [SKIPPED] pf_loopback_retry
[22:50:22] ==================== [PASSED] pf_relay =====================
[22:50:22] ================== vf_relay (3 subtests) ===================
[22:50:22] [PASSED] vf_rejects_guc2vf_too_short
[22:50:22] [PASSED] vf_rejects_guc2vf_too_long
[22:50:22] [PASSED] vf_rejects_guc2vf_no_payload
[22:50:22] ==================== [PASSED] vf_relay =====================
[22:50:22] ================= pf_service (11 subtests) =================
[22:50:22] [PASSED] pf_negotiate_any
[22:50:22] [PASSED] pf_negotiate_base_match
[22:50:22] [PASSED] pf_negotiate_base_newer
[22:50:22] [PASSED] pf_negotiate_base_next
[22:50:22] [SKIPPED] pf_negotiate_base_older
[22:50:22] [PASSED] pf_negotiate_base_prev
[22:50:22] [PASSED] pf_negotiate_latest_match
[22:50:22] [PASSED] pf_negotiate_latest_newer
[22:50:22] [PASSED] pf_negotiate_latest_next
[22:50:22] [SKIPPED] pf_negotiate_latest_older
[22:50:22] [SKIPPED] pf_negotiate_latest_prev
[22:50:22] =================== [PASSED] pf_service ====================
[22:50:22] ===================== lmtt (1 subtest) =====================
[22:50:22] ======================== test_ops  =========================
[22:50:22] [PASSED] 2-level
[22:50:22] [PASSED] multi-level
[22:50:22] ==================== [PASSED] test_ops =====================
[22:50:22] ====================== [PASSED] lmtt =======================
[22:50:22] =================== xe_mocs (2 subtests) ===================
[22:50:22] ================ xe_live_mocs_kernel_kunit  ================
[22:50:22] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:50:22] ================ xe_live_mocs_reset_kunit  =================
[22:50:22] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:50:22] ==================== [SKIPPED] xe_mocs =====================
[22:50:22] ================= xe_migrate (2 subtests) ==================
[22:50:22] ================= xe_migrate_sanity_kunit  =================
[22:50:22] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:50:22] ================== xe_validate_ccs_kunit  ==================
[22:50:22] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:50:22] =================== [SKIPPED] xe_migrate ===================
[22:50:22] ================== xe_dma_buf (1 subtest) ==================
[22:50:22] ==================== xe_dma_buf_kunit  =====================
[22:50:22] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:50:22] =================== [SKIPPED] xe_dma_buf ===================
[22:50:22] ================= xe_bo_shrink (1 subtest) =================
[22:50:22] =================== xe_bo_shrink_kunit  ====================
[22:50:22] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:50:22] ================== [SKIPPED] xe_bo_shrink ==================
[22:50:22] ==================== xe_bo (2 subtests) ====================
[22:50:22] ================== xe_ccs_migrate_kunit  ===================
[22:50:22] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:50:22] ==================== xe_bo_evict_kunit  ====================
[22:50:22] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:50:22] ===================== [SKIPPED] xe_bo ======================
[22:50:22] ==================== args (11 subtests) ====================
[22:50:22] [PASSED] count_args_test
[22:50:22] [PASSED] call_args_example
[22:50:22] [PASSED] call_args_test
[22:50:22] [PASSED] drop_first_arg_example
[22:50:22] [PASSED] drop_first_arg_test
[22:50:22] [PASSED] first_arg_example
[22:50:22] [PASSED] first_arg_test
[22:50:22] [PASSED] last_arg_example
[22:50:22] [PASSED] last_arg_test
[22:50:22] [PASSED] pick_arg_example
[22:50:22] [PASSED] sep_comma_example
[22:50:22] ====================== [PASSED] args =======================
[22:50:22] =================== xe_pci (3 subtests) ====================
[22:50:22] ==================== check_graphics_ip  ====================
[22:50:22] [PASSED] 12.70 Xe_LPG
[22:50:22] [PASSED] 12.71 Xe_LPG
[22:50:22] [PASSED] 12.74 Xe_LPG+
[22:50:22] [PASSED] 20.01 Xe2_HPG
[22:50:22] [PASSED] 20.02 Xe2_HPG
[22:50:22] [PASSED] 20.04 Xe2_LPG
[22:50:22] [PASSED] 30.00 Xe3_LPG
[22:50:22] [PASSED] 30.01 Xe3_LPG
[22:50:22] [PASSED] 30.03 Xe3_LPG
[22:50:22] ================ [PASSED] check_graphics_ip ================
[22:50:22] ===================== check_media_ip  ======================
[22:50:22] [PASSED] 13.00 Xe_LPM+
[22:50:22] [PASSED] 13.01 Xe2_HPM
[22:50:22] [PASSED] 20.00 Xe2_LPM
[22:50:22] [PASSED] 30.00 Xe3_LPM
[22:50:22] [PASSED] 30.02 Xe3_LPM
[22:50:22] ================= [PASSED] check_media_ip ==================
[22:50:22] ================= check_platform_gt_count  =================
[22:50:22] [PASSED] 0x9A60 (TIGERLAKE)
[22:50:22] [PASSED] 0x9A68 (TIGERLAKE)
[22:50:22] [PASSED] 0x9A70 (TIGERLAKE)
[22:50:22] [PASSED] 0x9A40 (TIGERLAKE)
[22:50:22] [PASSED] 0x9A49 (TIGERLAKE)
[22:50:22] [PASSED] 0x9A59 (TIGERLAKE)
[22:50:22] [PASSED] 0x9A78 (TIGERLAKE)
[22:50:22] [PASSED] 0x9AC0 (TIGERLAKE)
[22:50:22] [PASSED] 0x9AC9 (TIGERLAKE)
[22:50:22] [PASSED] 0x9AD9 (TIGERLAKE)
[22:50:22] [PASSED] 0x9AF8 (TIGERLAKE)
[22:50:22] [PASSED] 0x4C80 (ROCKETLAKE)
[22:50:22] [PASSED] 0x4C8A (ROCKETLAKE)
[22:50:22] [PASSED] 0x4C8B (ROCKETLAKE)
[22:50:22] [PASSED] 0x4C8C (ROCKETLAKE)
[22:50:22] [PASSED] 0x4C90 (ROCKETLAKE)
[22:50:22] [PASSED] 0x4C9A (ROCKETLAKE)
[22:50:22] [PASSED] 0x4680 (ALDERLAKE_S)
[22:50:22] [PASSED] 0x4682 (ALDERLAKE_S)
[22:50:22] [PASSED] 0x4688 (ALDERLAKE_S)
[22:50:22] [PASSED] 0x468A (ALDERLAKE_S)
[22:50:22] [PASSED] 0x468B (ALDERLAKE_S)
[22:50:22] [PASSED] 0x4690 (ALDERLAKE_S)
[22:50:22] [PASSED] 0x4692 (ALDERLAKE_S)
[22:50:22] [PASSED] 0x4693 (ALDERLAKE_S)
[22:50:22] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46AA (ALDERLAKE_P)
[22:50:22] [PASSED] 0x462A (ALDERLAKE_P)
[22:50:22] [PASSED] 0x4626 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x4628 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46B0 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:50:22] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:50:22] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:50:22] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:50:22] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:50:22] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:50:22] [PASSED] 0xA721 (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA720 (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:50:22] [PASSED] 0xA780 (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA781 (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA782 (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA783 (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA788 (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA789 (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA78A (ALDERLAKE_S)
[22:50:22] [PASSED] 0xA78B (ALDERLAKE_S)
[22:50:22] [PASSED] 0x4905 (DG1)
[22:50:22] [PASSED] 0x4906 (DG1)
[22:50:22] [PASSED] 0x4907 (DG1)
[22:50:22] [PASSED] 0x4908 (DG1)
[22:50:22] [PASSED] 0x4909 (DG1)
[22:50:22] [PASSED] 0x56C0 (DG2)
[22:50:22] [PASSED] 0x56C2 (DG2)
[22:50:22] [PASSED] 0x56C1 (DG2)
[22:50:22] [PASSED] 0x7D51 (METEORLAKE)
[22:50:22] [PASSED] 0x7DD1 (METEORLAKE)
[22:50:22] [PASSED] 0x7D41 (METEORLAKE)
[22:50:22] [PASSED] 0x7D67 (METEORLAKE)
[22:50:22] [PASSED] 0xB640 (METEORLAKE)
[22:50:22] [PASSED] 0x56A0 (DG2)
[22:50:22] [PASSED] 0x56A1 (DG2)
[22:50:22] [PASSED] 0x56A2 (DG2)
[22:50:22] [PASSED] 0x56BE (DG2)
[22:50:22] [PASSED] 0x56BF (DG2)
[22:50:22] [PASSED] 0x5690 (DG2)
[22:50:22] [PASSED] 0x5691 (DG2)
[22:50:22] [PASSED] 0x5692 (DG2)
[22:50:22] [PASSED] 0x56A5 (DG2)
[22:50:22] [PASSED] 0x56A6 (DG2)
[22:50:22] [PASSED] 0x56B0 (DG2)
[22:50:22] [PASSED] 0x56B1 (DG2)
[22:50:22] [PASSED] 0x56BA (DG2)
[22:50:22] [PASSED] 0x56BB (DG2)
[22:50:22] [PASSED] 0x56BC (DG2)
[22:50:22] [PASSED] 0x56BD (DG2)
[22:50:22] [PASSED] 0x5693 (DG2)
[22:50:22] [PASSED] 0x5694 (DG2)
[22:50:22] [PASSED] 0x5695 (DG2)
[22:50:22] [PASSED] 0x56A3 (DG2)
[22:50:22] [PASSED] 0x56A4 (DG2)
[22:50:22] [PASSED] 0x56B2 (DG2)
[22:50:22] [PASSED] 0x56B3 (DG2)
[22:50:22] [PASSED] 0x5696 (DG2)
[22:50:22] [PASSED] 0x5697 (DG2)
[22:50:22] [PASSED] 0xB69 (PVC)
[22:50:22] [PASSED] 0xB6E (PVC)
[22:50:22] [PASSED] 0xBD4 (PVC)
[22:50:22] [PASSED] 0xBD5 (PVC)
[22:50:22] [PASSED] 0xBD6 (PVC)
[22:50:22] [PASSED] 0xBD7 (PVC)
[22:50:22] [PASSED] 0xBD8 (PVC)
[22:50:22] [PASSED] 0xBD9 (PVC)
[22:50:22] [PASSED] 0xBDA (PVC)
[22:50:22] [PASSED] 0xBDB (PVC)
[22:50:22] [PASSED] 0xBE0 (PVC)
[22:50:22] [PASSED] 0xBE1 (PVC)
[22:50:22] [PASSED] 0xBE5 (PVC)
[22:50:22] [PASSED] 0x7D40 (METEORLAKE)
[22:50:22] [PASSED] 0x7D45 (METEORLAKE)
[22:50:22] [PASSED] 0x7D55 (METEORLAKE)
[22:50:22] [PASSED] 0x7D60 (METEORLAKE)
[22:50:22] [PASSED] 0x7DD5 (METEORLAKE)
[22:50:22] [PASSED] 0x6420 (LUNARLAKE)
[22:50:22] [PASSED] 0x64A0 (LUNARLAKE)
[22:50:22] [PASSED] 0x64B0 (LUNARLAKE)
[22:50:22] [PASSED] 0xE202 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE20B (BATTLEMAGE)
[22:50:22] [PASSED] 0xE20C (BATTLEMAGE)
[22:50:22] [PASSED] 0xE20D (BATTLEMAGE)
[22:50:22] [PASSED] 0xE210 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE211 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE212 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE216 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE220 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE221 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE222 (BATTLEMAGE)
[22:50:22] [PASSED] 0xE223 (BATTLEMAGE)
[22:50:22] [PASSED] 0xB080 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB081 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB082 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB083 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB084 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB085 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB086 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB087 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB08F (PANTHERLAKE)
[22:50:22] [PASSED] 0xB090 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:50:22] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:50:22] [PASSED] 0xFD80 (PANTHERLAKE)
[22:50:22] [PASSED] 0xFD81 (PANTHERLAKE)
[22:50:22] ============= [PASSED] check_platform_gt_count =============
[22:50:22] ===================== [PASSED] xe_pci ======================
[22:50:22] =================== xe_rtp (2 subtests) ====================
[22:50:22] =============== xe_rtp_process_to_sr_tests  ================
[22:50:22] [PASSED] coalesce-same-reg
[22:50:22] [PASSED] no-match-no-add
[22:50:22] [PASSED] match-or
[22:50:22] [PASSED] match-or-xfail
[22:50:22] [PASSED] no-match-no-add-multiple-rules
[22:50:23] [PASSED] two-regs-two-entries
[22:50:23] [PASSED] clr-one-set-other
[22:50:23] [PASSED] set-field
[22:50:23] [PASSED] conflict-duplicate
[22:50:23] [PASSED] conflict-not-disjoint
[22:50:23] [PASSED] conflict-reg-type
[22:50:23] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:50:23] ================== xe_rtp_process_tests  ===================
[22:50:23] [PASSED] active1
[22:50:23] [PASSED] active2
[22:50:23] [PASSED] active-inactive
[22:50:23] [PASSED] inactive-active
[22:50:23] [PASSED] inactive-1st_or_active-inactive
[22:50:23] [PASSED] inactive-2nd_or_active-inactive
[22:50:23] [PASSED] inactive-last_or_active-inactive
[22:50:23] [PASSED] inactive-no_or_active-inactive
[22:50:23] ============== [PASSED] xe_rtp_process_tests ===============
[22:50:23] ===================== [PASSED] xe_rtp ======================
[22:50:23] ==================== xe_wa (1 subtest) =====================
[22:50:23] ======================== xe_wa_gt  =========================
[22:50:23] [PASSED] TIGERLAKE (B0)
[22:50:23] [PASSED] DG1 (A0)
[22:50:23] [PASSED] DG1 (B0)
[22:50:23] [PASSED] ALDERLAKE_S (A0)
[22:50:23] [PASSED] ALDERLAKE_S (B0)
[22:50:23] [PASSED] ALDERLAKE_S (C0)
[22:50:23] [PASSED] ALDERLAKE_S (D0)
[22:50:23] [PASSED] ALDERLAKE_P (A0)
[22:50:23] [PASSED] ALDERLAKE_P (B0)
[22:50:23] [PASSED] ALDERLAKE_P (C0)
[22:50:23] [PASSED] ALDERLAKE_S_RPLS (D0)
[22:50:23] [PASSED] ALDERLAKE_P_RPLU (E0)
[22:50:23] [PASSED] DG2_G10 (C0)
[22:50:23] [PASSED] DG2_G11 (B1)
[22:50:23] [PASSED] DG2_G12 (A1)
[22:50:23] [PASSED] METEORLAKE (g:A0, m:A0)
[22:50:23] [PASSED] METEORLAKE (g:A0, m:A0)
[22:50:23] [PASSED] METEORLAKE (g:A0, m:A0)
[22:50:23] [PASSED] LUNARLAKE (g:A0, m:A0)
[22:50:23] [PASSED] LUNARLAKE (g:B0, m:A0)
[22:50:23] [PASSED] BATTLEMAGE (g:A0, m:A1)
stty: 'standard input': Inappropriate ioctl for device
[22:50:23] ==================== [PASSED] xe_wa_gt =====================
[22:50:23] ====================== [PASSED] xe_wa ======================
[22:50:23] ============================================================
[22:50:23] Testing complete. Ran 296 tests: passed: 280, skipped: 16
[22:50:23] Elapsed time: 31.230s total, 4.170s configuring, 26.743s building, 0.308s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:50:23] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:50:24] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:50:46] Starting KUnit Kernel (1/1)...
[22:50:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:50:46] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[22:50:46] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[22:50:46] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[22:50:46] =========== drm_validate_clone_mode (2 subtests) ===========
[22:50:46] ============== drm_test_check_in_clone_mode  ===============
[22:50:46] [PASSED] in_clone_mode
[22:50:46] [PASSED] not_in_clone_mode
[22:50:46] ========== [PASSED] drm_test_check_in_clone_mode ===========
[22:50:46] =============== drm_test_check_valid_clones  ===============
[22:50:46] [PASSED] not_in_clone_mode
[22:50:46] [PASSED] valid_clone
[22:50:46] [PASSED] invalid_clone
[22:50:46] =========== [PASSED] drm_test_check_valid_clones ===========
[22:50:46] ============= [PASSED] drm_validate_clone_mode =============
[22:50:46] ============= drm_validate_modeset (1 subtest) =============
[22:50:46] [PASSED] drm_test_check_connector_changed_modeset
[22:50:46] ============== [PASSED] drm_validate_modeset ===============
[22:50:46] ====== drm_test_bridge_get_current_state (2 subtests) ======
[22:50:46] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[22:50:46] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[22:50:46] ======== [PASSED] drm_test_bridge_get_current_state ========
[22:50:46] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[22:50:46] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[22:50:46] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[22:50:46] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[22:50:46] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[22:50:46] ============== drm_bridge_alloc (2 subtests) ===============
[22:50:46] [PASSED] drm_test_drm_bridge_alloc_basic
[22:50:46] [PASSED] drm_test_drm_bridge_alloc_get_put
[22:50:46] ================ [PASSED] drm_bridge_alloc =================
[22:50:46] ================== drm_buddy (7 subtests) ==================
[22:50:46] [PASSED] drm_test_buddy_alloc_limit
[22:50:46] [PASSED] drm_test_buddy_alloc_optimistic
[22:50:46] [PASSED] drm_test_buddy_alloc_pessimistic
[22:50:46] [PASSED] drm_test_buddy_alloc_pathological
[22:50:46] [PASSED] drm_test_buddy_alloc_contiguous
[22:50:46] [PASSED] drm_test_buddy_alloc_clear
[22:50:46] [PASSED] drm_test_buddy_alloc_range_bias
[22:50:46] ==================== [PASSED] drm_buddy ====================
[22:50:46] ============= drm_cmdline_parser (40 subtests) =============
[22:50:46] [PASSED] drm_test_cmdline_force_d_only
[22:50:46] [PASSED] drm_test_cmdline_force_D_only_dvi
[22:50:46] [PASSED] drm_test_cmdline_force_D_only_hdmi
[22:50:46] [PASSED] drm_test_cmdline_force_D_only_not_digital
[22:50:46] [PASSED] drm_test_cmdline_force_e_only
[22:50:46] [PASSED] drm_test_cmdline_res
[22:50:46] [PASSED] drm_test_cmdline_res_vesa
[22:50:46] [PASSED] drm_test_cmdline_res_vesa_rblank
[22:50:46] [PASSED] drm_test_cmdline_res_rblank
[22:50:46] [PASSED] drm_test_cmdline_res_bpp
[22:50:46] [PASSED] drm_test_cmdline_res_refresh
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[22:50:46] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[22:50:46] [PASSED] drm_test_cmdline_res_margins_force_on
[22:50:46] [PASSED] drm_test_cmdline_res_vesa_margins
[22:50:46] [PASSED] drm_test_cmdline_name
[22:50:46] [PASSED] drm_test_cmdline_name_bpp
[22:50:46] [PASSED] drm_test_cmdline_name_option
[22:50:46] [PASSED] drm_test_cmdline_name_bpp_option
[22:50:46] [PASSED] drm_test_cmdline_rotate_0
[22:50:46] [PASSED] drm_test_cmdline_rotate_90
[22:50:46] [PASSED] drm_test_cmdline_rotate_180
[22:50:46] [PASSED] drm_test_cmdline_rotate_270
[22:50:46] [PASSED] drm_test_cmdline_hmirror
[22:50:46] [PASSED] drm_test_cmdline_vmirror
[22:50:46] [PASSED] drm_test_cmdline_margin_options
[22:50:46] [PASSED] drm_test_cmdline_multiple_options
[22:50:46] [PASSED] drm_test_cmdline_bpp_extra_and_option
[22:50:46] [PASSED] drm_test_cmdline_extra_and_option
[22:50:46] [PASSED] drm_test_cmdline_freestanding_options
[22:50:46] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[22:50:46] [PASSED] drm_test_cmdline_panel_orientation
[22:50:46] ================ drm_test_cmdline_invalid  =================
[22:50:46] [PASSED] margin_only
[22:50:46] [PASSED] interlace_only
[22:50:46] [PASSED] res_missing_x
[22:50:46] [PASSED] res_missing_y
[22:50:46] [PASSED] res_bad_y
[22:50:46] [PASSED] res_missing_y_bpp
[22:50:46] [PASSED] res_bad_bpp
[22:50:46] [PASSED] res_bad_refresh
[22:50:46] [PASSED] res_bpp_refresh_force_on_off
[22:50:46] [PASSED] res_invalid_mode
[22:50:46] [PASSED] res_bpp_wrong_place_mode
[22:50:46] [PASSED] name_bpp_refresh
[22:50:46] [PASSED] name_refresh
[22:50:46] [PASSED] name_refresh_wrong_mode
[22:50:46] [PASSED] name_refresh_invalid_mode
[22:50:46] [PASSED] rotate_multiple
[22:50:46] [PASSED] rotate_invalid_val
[22:50:46] [PASSED] rotate_truncated
[22:50:46] [PASSED] invalid_option
[22:50:46] [PASSED] invalid_tv_option
[22:50:46] [PASSED] truncated_tv_option
[22:50:46] ============ [PASSED] drm_test_cmdline_invalid =============
[22:50:46] =============== drm_test_cmdline_tv_options  ===============
[22:50:46] [PASSED] NTSC
[22:50:46] [PASSED] NTSC_443
[22:50:46] [PASSED] NTSC_J
[22:50:46] [PASSED] PAL
[22:50:46] [PASSED] PAL_M
[22:50:46] [PASSED] PAL_N
[22:50:46] [PASSED] SECAM
[22:50:46] [PASSED] MONO_525
[22:50:46] [PASSED] MONO_625
[22:50:46] =========== [PASSED] drm_test_cmdline_tv_options ===========
[22:50:46] =============== [PASSED] drm_cmdline_parser ================
[22:50:46] ========== drmm_connector_hdmi_init (20 subtests) ==========
[22:50:46] [PASSED] drm_test_connector_hdmi_init_valid
[22:50:46] [PASSED] drm_test_connector_hdmi_init_bpc_8
[22:50:46] [PASSED] drm_test_connector_hdmi_init_bpc_10
[22:50:46] [PASSED] drm_test_connector_hdmi_init_bpc_12
[22:50:46] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[22:50:46] [PASSED] drm_test_connector_hdmi_init_bpc_null
[22:50:46] [PASSED] drm_test_connector_hdmi_init_formats_empty
[22:50:46] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[22:50:46] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[22:50:46] [PASSED] supported_formats=0x9 yuv420_allowed=1
[22:50:46] [PASSED] supported_formats=0x9 yuv420_allowed=0
[22:50:46] [PASSED] supported_formats=0x3 yuv420_allowed=1
[22:50:46] [PASSED] supported_formats=0x3 yuv420_allowed=0
[22:50:46] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:50:46] [PASSED] drm_test_connector_hdmi_init_null_ddc
[22:50:46] [PASSED] drm_test_connector_hdmi_init_null_product
[22:50:46] [PASSED] drm_test_connector_hdmi_init_null_vendor
[22:50:46] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[22:50:46] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[22:50:46] [PASSED] drm_test_connector_hdmi_init_product_valid
[22:50:46] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[22:50:46] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[22:50:46] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[22:50:46] ========= drm_test_connector_hdmi_init_type_valid  =========
[22:50:46] [PASSED] HDMI-A
[22:50:46] [PASSED] HDMI-B
[22:50:46] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[22:50:46] ======== drm_test_connector_hdmi_init_type_invalid  ========
[22:50:46] [PASSED] Unknown
[22:50:46] [PASSED] VGA
[22:50:46] [PASSED] DVI-I
[22:50:46] [PASSED] DVI-D
[22:50:46] [PASSED] DVI-A
[22:50:46] [PASSED] Composite
[22:50:46] [PASSED] SVIDEO
[22:50:46] [PASSED] LVDS
[22:50:46] [PASSED] Component
[22:50:46] [PASSED] DIN
[22:50:46] [PASSED] DP
[22:50:46] [PASSED] TV
[22:50:46] [PASSED] eDP
[22:50:46] [PASSED] Virtual
[22:50:46] [PASSED] DSI
[22:50:46] [PASSED] DPI
[22:50:46] [PASSED] Writeback
[22:50:46] [PASSED] SPI
[22:50:46] [PASSED] USB
[22:50:46] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[22:50:46] ============ [PASSED] drmm_connector_hdmi_init =============
[22:50:46] ============= drmm_connector_init (3 subtests) =============
[22:50:46] [PASSED] drm_test_drmm_connector_init
[22:50:46] [PASSED] drm_test_drmm_connector_init_null_ddc
[22:50:46] ========= drm_test_drmm_connector_init_type_valid  =========
[22:50:46] [PASSED] Unknown
[22:50:46] [PASSED] VGA
[22:50:46] [PASSED] DVI-I
[22:50:46] [PASSED] DVI-D
[22:50:46] [PASSED] DVI-A
[22:50:46] [PASSED] Composite
[22:50:46] [PASSED] SVIDEO
[22:50:46] [PASSED] LVDS
[22:50:46] [PASSED] Component
[22:50:46] [PASSED] DIN
[22:50:46] [PASSED] DP
[22:50:46] [PASSED] HDMI-A
[22:50:46] [PASSED] HDMI-B
[22:50:46] [PASSED] TV
[22:50:46] [PASSED] eDP
[22:50:46] [PASSED] Virtual
[22:50:46] [PASSED] DSI
[22:50:46] [PASSED] DPI
[22:50:46] [PASSED] Writeback
[22:50:46] [PASSED] SPI
[22:50:46] [PASSED] USB
[22:50:46] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[22:50:46] =============== [PASSED] drmm_connector_init ===============
[22:50:46] ========= drm_connector_dynamic_init (6 subtests) ==========
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_init
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_init_properties
[22:50:46] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[22:50:46] [PASSED] Unknown
[22:50:46] [PASSED] VGA
[22:50:46] [PASSED] DVI-I
[22:50:46] [PASSED] DVI-D
[22:50:46] [PASSED] DVI-A
[22:50:46] [PASSED] Composite
[22:50:46] [PASSED] SVIDEO
[22:50:46] [PASSED] LVDS
[22:50:46] [PASSED] Component
[22:50:46] [PASSED] DIN
[22:50:46] [PASSED] DP
[22:50:46] [PASSED] HDMI-A
[22:50:46] [PASSED] HDMI-B
[22:50:46] [PASSED] TV
[22:50:46] [PASSED] eDP
[22:50:46] [PASSED] Virtual
[22:50:46] [PASSED] DSI
[22:50:46] [PASSED] DPI
[22:50:46] [PASSED] Writeback
[22:50:46] [PASSED] SPI
[22:50:46] [PASSED] USB
[22:50:46] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[22:50:46] ======== drm_test_drm_connector_dynamic_init_name  =========
[22:50:46] [PASSED] Unknown
[22:50:46] [PASSED] VGA
[22:50:46] [PASSED] DVI-I
[22:50:46] [PASSED] DVI-D
[22:50:46] [PASSED] DVI-A
[22:50:46] [PASSED] Composite
[22:50:46] [PASSED] SVIDEO
[22:50:46] [PASSED] LVDS
[22:50:46] [PASSED] Component
[22:50:46] [PASSED] DIN
[22:50:46] [PASSED] DP
[22:50:46] [PASSED] HDMI-A
[22:50:46] [PASSED] HDMI-B
[22:50:46] [PASSED] TV
[22:50:46] [PASSED] eDP
[22:50:46] [PASSED] Virtual
[22:50:46] [PASSED] DSI
[22:50:46] [PASSED] DPI
[22:50:46] [PASSED] Writeback
[22:50:46] [PASSED] SPI
[22:50:46] [PASSED] USB
[22:50:46] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[22:50:46] =========== [PASSED] drm_connector_dynamic_init ============
[22:50:46] ==== drm_connector_dynamic_register_early (4 subtests) =====
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[22:50:46] ====== [PASSED] drm_connector_dynamic_register_early =======
[22:50:46] ======= drm_connector_dynamic_register (7 subtests) ========
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[22:50:46] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[22:50:46] ========= [PASSED] drm_connector_dynamic_register ==========
[22:50:46] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[22:50:46] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[22:50:46] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[22:50:46] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[22:50:46] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[22:50:46] ========== drm_test_get_tv_mode_from_name_valid  ===========
[22:50:46] [PASSED] NTSC
[22:50:46] [PASSED] NTSC-443
[22:50:46] [PASSED] NTSC-J
[22:50:46] [PASSED] PAL
[22:50:46] [PASSED] PAL-M
[22:50:46] [PASSED] PAL-N
[22:50:46] [PASSED] SECAM
[22:50:46] [PASSED] Mono
[22:50:46] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[22:50:46] [PASSED] drm_test_get_tv_mode_from_name_truncated
[22:50:46] ============ [PASSED] drm_get_tv_mode_from_name ============
[22:50:46] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[22:50:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[22:50:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[22:50:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[22:50:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[22:50:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[22:50:46] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[22:50:46] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[22:50:46] [PASSED] VIC 96
[22:50:46] [PASSED] VIC 97
[22:50:46] [PASSED] VIC 101
[22:50:46] [PASSED] VIC 102
[22:50:46] [PASSED] VIC 106
[22:50:46] [PASSED] VIC 107
[22:50:46] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[22:50:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[22:50:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[22:50:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[22:50:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[22:50:46] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[22:50:46] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[22:50:46] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[22:50:46] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[22:50:46] [PASSED] Automatic
[22:50:46] [PASSED] Full
[22:50:46] [PASSED] Limited 16:235
[22:50:46] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[22:50:46] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[22:50:46] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[22:50:46] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[22:50:46] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[22:50:46] [PASSED] RGB
[22:50:46] [PASSED] YUV 4:2:0
[22:50:46] [PASSED] YUV 4:2:2
[22:50:46] [PASSED] YUV 4:4:4
[22:50:46] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[22:50:46] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[22:50:46] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[22:50:46] ============= drm_damage_helper (21 subtests) ==============
[22:50:46] [PASSED] drm_test_damage_iter_no_damage
[22:50:46] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[22:50:46] [PASSED] drm_test_damage_iter_no_damage_src_moved
[22:50:46] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[22:50:46] [PASSED] drm_test_damage_iter_no_damage_not_visible
[22:50:46] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[22:50:46] [PASSED] drm_test_damage_iter_no_damage_no_fb
[22:50:46] [PASSED] drm_test_damage_iter_simple_damage
[22:50:46] [PASSED] drm_test_damage_iter_single_damage
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_outside_src
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_src_moved
[22:50:46] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[22:50:46] [PASSED] drm_test_damage_iter_damage
[22:50:46] [PASSED] drm_test_damage_iter_damage_one_intersect
[22:50:46] [PASSED] drm_test_damage_iter_damage_one_outside
[22:50:46] [PASSED] drm_test_damage_iter_damage_src_moved
[22:50:46] [PASSED] drm_test_damage_iter_damage_not_visible
[22:50:46] ================ [PASSED] drm_damage_helper ================
[22:50:46] ============== drm_dp_mst_helper (3 subtests) ==============
[22:50:46] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[22:50:46] [PASSED] Clock 154000 BPP 30 DSC disabled
[22:50:46] [PASSED] Clock 234000 BPP 30 DSC disabled
[22:50:46] [PASSED] Clock 297000 BPP 24 DSC disabled
[22:50:46] [PASSED] Clock 332880 BPP 24 DSC enabled
[22:50:46] [PASSED] Clock 324540 BPP 24 DSC enabled
[22:50:46] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[22:50:46] ============== drm_test_dp_mst_calc_pbn_div  ===============
[22:50:46] [PASSED] Link rate 2000000 lane count 4
[22:50:46] [PASSED] Link rate 2000000 lane count 2
[22:50:46] [PASSED] Link rate 2000000 lane count 1
[22:50:46] [PASSED] Link rate 1350000 lane count 4
[22:50:46] [PASSED] Link rate 1350000 lane count 2
[22:50:46] [PASSED] Link rate 1350000 lane count 1
[22:50:46] [PASSED] Link rate 1000000 lane count 4
[22:50:46] [PASSED] Link rate 1000000 lane count 2
[22:50:46] [PASSED] Link rate 1000000 lane count 1
[22:50:46] [PASSED] Link rate 810000 lane count 4
[22:50:46] [PASSED] Link rate 810000 lane count 2
[22:50:46] [PASSED] Link rate 810000 lane count 1
[22:50:46] [PASSED] Link rate 540000 lane count 4
[22:50:46] [PASSED] Link rate 540000 lane count 2
[22:50:46] [PASSED] Link rate 540000 lane count 1
[22:50:46] [PASSED] Link rate 270000 lane count 4
[22:50:46] [PASSED] Link rate 270000 lane count 2
[22:50:46] [PASSED] Link rate 270000 lane count 1
[22:50:46] [PASSED] Link rate 162000 lane count 4
[22:50:46] [PASSED] Link rate 162000 lane count 2
[22:50:46] [PASSED] Link rate 162000 lane count 1
[22:50:46] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[22:50:46] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[22:50:46] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[22:50:46] [PASSED] DP_POWER_UP_PHY with port number
[22:50:46] [PASSED] DP_POWER_DOWN_PHY with port number
[22:50:46] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[22:50:46] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[22:50:46] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[22:50:46] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[22:50:46] [PASSED] DP_QUERY_PAYLOAD with port number
[22:50:46] [PASSED] DP_QUERY_PAYLOAD with VCPI
[22:50:46] [PASSED] DP_REMOTE_DPCD_READ with port number
[22:50:46] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[22:50:46] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[22:50:46] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[22:50:46] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[22:50:46] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[22:50:46] [PASSED] DP_REMOTE_I2C_READ with port number
[22:50:46] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[22:50:46] [PASSED] DP_REMOTE_I2C_READ with transactions array
[22:50:46] [PASSED] DP_REMOTE_I2C_WRITE with port number
[22:50:46] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[22:50:46] [PASSED] DP_REMOTE_I2C_WRITE with data array
[22:50:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[22:50:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[22:50:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[22:50:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[22:50:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[22:50:46] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[22:50:46] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[22:50:46] ================ [PASSED] drm_dp_mst_helper ================
[22:50:46] ================== drm_exec (7 subtests) ===================
[22:50:46] [PASSED] sanitycheck
[22:50:46] [PASSED] test_lock
[22:50:46] [PASSED] test_lock_unlock
[22:50:46] [PASSED] test_duplicates
[22:50:46] [PASSED] test_prepare
[22:50:46] [PASSED] test_prepare_array
[22:50:46] [PASSED] test_multiple_loops
[22:50:46] ==================== [PASSED] drm_exec =====================
[22:50:46] =========== drm_format_helper_test (17 subtests) ===========
[22:50:46] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[22:50:46] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[22:50:46] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[22:50:46] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[22:50:46] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[22:50:46] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[22:50:46] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[22:50:46] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[22:50:46] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[22:50:46] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[22:50:46] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[22:50:46] ============== drm_test_fb_xrgb8888_to_mono  ===============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[22:50:46] ==================== drm_test_fb_swab  =====================
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ================ [PASSED] drm_test_fb_swab =================
[22:50:46] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[22:50:46] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[22:50:46] [PASSED] single_pixel_source_buffer
[22:50:46] [PASSED] single_pixel_clip_rectangle
[22:50:46] [PASSED] well_known_colors
[22:50:46] [PASSED] destination_pitch
[22:50:46] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[22:50:46] ================= drm_test_fb_clip_offset  =================
[22:50:46] [PASSED] pass through
[22:50:46] [PASSED] horizontal offset
[22:50:46] [PASSED] vertical offset
[22:50:46] [PASSED] horizontal and vertical offset
[22:50:46] [PASSED] horizontal offset (custom pitch)
[22:50:46] [PASSED] vertical offset (custom pitch)
[22:50:46] [PASSED] horizontal and vertical offset (custom pitch)
[22:50:46] ============= [PASSED] drm_test_fb_clip_offset =============
[22:50:46] =================== drm_test_fb_memcpy  ====================
[22:50:46] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[22:50:46] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[22:50:46] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[22:50:46] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[22:50:46] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[22:50:46] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[22:50:46] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[22:50:46] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[22:50:46] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[22:50:46] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[22:50:46] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[22:50:46] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[22:50:46] =============== [PASSED] drm_test_fb_memcpy ================
[22:50:46] ============= [PASSED] drm_format_helper_test ==============
[22:50:46] ================= drm_format (18 subtests) =================
[22:50:46] [PASSED] drm_test_format_block_width_invalid
[22:50:46] [PASSED] drm_test_format_block_width_one_plane
[22:50:46] [PASSED] drm_test_format_block_width_two_plane
[22:50:46] [PASSED] drm_test_format_block_width_three_plane
[22:50:46] [PASSED] drm_test_format_block_width_tiled
[22:50:46] [PASSED] drm_test_format_block_height_invalid
[22:50:46] [PASSED] drm_test_format_block_height_one_plane
[22:50:46] [PASSED] drm_test_format_block_height_two_plane
[22:50:46] [PASSED] drm_test_format_block_height_three_plane
[22:50:46] [PASSED] drm_test_format_block_height_tiled
[22:50:46] [PASSED] drm_test_format_min_pitch_invalid
[22:50:46] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[22:50:46] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[22:50:46] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[22:50:46] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[22:50:46] [PASSED] drm_test_format_min_pitch_two_plane
[22:50:46] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[22:50:46] [PASSED] drm_test_format_min_pitch_tiled
[22:50:46] =================== [PASSED] drm_format ====================
[22:50:46] ============== drm_framebuffer (10 subtests) ===============
[22:50:46] ========== drm_test_framebuffer_check_src_coords  ==========
[22:50:46] [PASSED] Success: source fits into fb
[22:50:46] [PASSED] Fail: overflowing fb with x-axis coordinate
[22:50:46] [PASSED] Fail: overflowing fb with y-axis coordinate
[22:50:46] [PASSED] Fail: overflowing fb with source width
[22:50:46] [PASSED] Fail: overflowing fb with source height
[22:50:46] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[22:50:46] [PASSED] drm_test_framebuffer_cleanup
[22:50:46] =============== drm_test_framebuffer_create  ===============
[22:50:46] [PASSED] ABGR8888 normal sizes
[22:50:46] [PASSED] ABGR8888 max sizes
[22:50:46] [PASSED] ABGR8888 pitch greater than min required
[22:50:46] [PASSED] ABGR8888 pitch less than min required
[22:50:46] [PASSED] ABGR8888 Invalid width
[22:50:46] [PASSED] ABGR8888 Invalid buffer handle
[22:50:46] [PASSED] No pixel format
[22:50:46] [PASSED] ABGR8888 Width 0
[22:50:46] [PASSED] ABGR8888 Height 0
[22:50:46] [PASSED] ABGR8888 Out of bound height * pitch combination
[22:50:46] [PASSED] ABGR8888 Large buffer offset
[22:50:46] [PASSED] ABGR8888 Buffer offset for inexistent plane
[22:50:46] [PASSED] ABGR8888 Invalid flag
[22:50:46] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[22:50:46] [PASSED] ABGR8888 Valid buffer modifier
[22:50:46] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[22:50:46] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] NV12 Normal sizes
[22:50:46] [PASSED] NV12 Max sizes
[22:50:46] [PASSED] NV12 Invalid pitch
[22:50:46] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[22:50:46] [PASSED] NV12 different  modifier per-plane
[22:50:46] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[22:50:46] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] NV12 Modifier for inexistent plane
[22:50:46] [PASSED] NV12 Handle for inexistent plane
[22:50:46] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[22:50:46] [PASSED] YVU420 Normal sizes
[22:50:46] [PASSED] YVU420 Max sizes
[22:50:46] [PASSED] YVU420 Invalid pitch
[22:50:46] [PASSED] YVU420 Different pitches
[22:50:46] [PASSED] YVU420 Different buffer offsets/pitches
[22:50:46] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[22:50:46] [PASSED] YVU420 Valid modifier
[22:50:46] [PASSED] YVU420 Different modifiers per plane
[22:50:46] [PASSED] YVU420 Modifier for inexistent plane
[22:50:46] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[22:50:46] [PASSED] X0L2 Normal sizes
[22:50:46] [PASSED] X0L2 Max sizes
[22:50:46] [PASSED] X0L2 Invalid pitch
[22:50:46] [PASSED] X0L2 Pitch greater than minimum required
[22:50:46] [PASSED] X0L2 Handle for inexistent plane
[22:50:46] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[22:50:46] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[22:50:46] [PASSED] X0L2 Valid modifier
[22:50:46] [PASSED] X0L2 Modifier for inexistent plane
[22:50:46] =========== [PASSED] drm_test_framebuffer_create ===========
[22:50:46] [PASSED] drm_test_framebuffer_free
[22:50:46] [PASSED] drm_test_framebuffer_init
[22:50:46] [PASSED] drm_test_framebuffer_init_bad_format
[22:50:46] [PASSED] drm_test_framebuffer_init_dev_mismatch
[22:50:46] [PASSED] drm_test_framebuffer_lookup
[22:50:46] [PASSED] drm_test_framebuffer_lookup_inexistent
[22:50:46] [PASSED] drm_test_framebuffer_modifiers_not_supported
[22:50:46] ================= [PASSED] drm_framebuffer =================
[22:50:46] ================ drm_gem_shmem (8 subtests) ================
[22:50:46] [PASSED] drm_gem_shmem_test_obj_create
[22:50:46] [PASSED] drm_gem_shmem_test_obj_create_private
[22:50:46] [PASSED] drm_gem_shmem_test_pin_pages
[22:50:46] [PASSED] drm_gem_shmem_test_vmap
[22:50:46] [PASSED] drm_gem_shmem_test_get_pages_sgt
[22:50:46] [PASSED] drm_gem_shmem_test_get_sg_table
[22:50:46] [PASSED] drm_gem_shmem_test_madvise
[22:50:46] [PASSED] drm_gem_shmem_test_purge
[22:50:46] ================== [PASSED] drm_gem_shmem ==================
[22:50:46] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[22:50:46] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[22:50:46] [PASSED] Automatic
[22:50:46] [PASSED] Full
[22:50:46] [PASSED] Limited 16:235
[22:50:46] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[22:50:46] [PASSED] drm_test_check_disable_connector
[22:50:46] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[22:50:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[22:50:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[22:50:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[22:50:46] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[22:50:46] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[22:50:46] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[22:50:46] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[22:50:46] [PASSED] drm_test_check_output_bpc_dvi
[22:50:46] [PASSED] drm_test_check_output_bpc_format_vic_1
[22:50:46] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[22:50:46] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[22:50:46] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[22:50:46] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[22:50:46] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[22:50:46] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[22:50:46] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[22:50:46] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[22:50:46] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[22:50:46] [PASSED] drm_test_check_broadcast_rgb_value
[22:50:46] [PASSED] drm_test_check_bpc_8_value
[22:50:46] [PASSED] drm_test_check_bpc_10_value
[22:50:46] [PASSED] drm_test_check_bpc_12_value
[22:50:46] [PASSED] drm_test_check_format_value
[22:50:46] [PASSED] drm_test_check_tmds_char_value
[22:50:46] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[22:50:46] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[22:50:46] [PASSED] drm_test_check_mode_valid
[22:50:46] [PASSED] drm_test_check_mode_valid_reject
[22:50:46] [PASSED] drm_test_check_mode_valid_reject_rate
[22:50:46] [PASSED] drm_test_check_mode_valid_reject_max_clock
[22:50:46] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[22:50:46] ================= drm_managed (2 subtests) =================
[22:50:46] [PASSED] drm_test_managed_release_action
[22:50:46] [PASSED] drm_test_managed_run_action
[22:50:46] =================== [PASSED] drm_managed ===================
[22:50:46] =================== drm_mm (6 subtests) ====================
[22:50:46] [PASSED] drm_test_mm_init
[22:50:46] [PASSED] drm_test_mm_debug
[22:50:46] [PASSED] drm_test_mm_align32
[22:50:46] [PASSED] drm_test_mm_align64
[22:50:46] [PASSED] drm_test_mm_lowest
[22:50:46] [PASSED] drm_test_mm_highest
[22:50:46] ===================== [PASSED] drm_mm ======================
[22:50:46] ============= drm_modes_analog_tv (5 subtests) =============
[22:50:46] [PASSED] drm_test_modes_analog_tv_mono_576i
[22:50:46] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[22:50:46] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[22:50:46] [PASSED] drm_test_modes_analog_tv_pal_576i
[22:50:46] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[22:50:46] =============== [PASSED] drm_modes_analog_tv ===============
[22:50:46] ============== drm_plane_helper (2 subtests) ===============
[22:50:46] =============== drm_test_check_plane_state  ================
[22:50:46] [PASSED] clipping_simple
[22:50:46] [PASSED] clipping_rotate_reflect
[22:50:46] [PASSED] positioning_simple
[22:50:46] [PASSED] upscaling
[22:50:46] [PASSED] downscaling
[22:50:46] [PASSED] rounding1
[22:50:46] [PASSED] rounding2
[22:50:46] [PASSED] rounding3
[22:50:46] [PASSED] rounding4
[22:50:46] =========== [PASSED] drm_test_check_plane_state ============
[22:50:46] =========== drm_test_check_invalid_plane_state  ============
[22:50:46] [PASSED] positioning_invalid
[22:50:46] [PASSED] upscaling_invalid
[22:50:46] [PASSED] downscaling_invalid
[22:50:46] ======= [PASSED] drm_test_check_invalid_plane_state ========
[22:50:46] ================ [PASSED] drm_plane_helper =================
[22:50:46] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[22:50:46] ====== drm_test_connector_helper_tv_get_modes_check  =======
[22:50:46] [PASSED] None
[22:50:46] [PASSED] PAL
[22:50:46] [PASSED] NTSC
[22:50:46] [PASSED] Both, NTSC Default
[22:50:46] [PASSED] Both, PAL Default
[22:50:46] [PASSED] Both, NTSC Default, with PAL on command-line
[22:50:46] [PASSED] Both, PAL Default, with NTSC on command-line
[22:50:46] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[22:50:46] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[22:50:46] ================== drm_rect (9 subtests) ===================
[22:50:46] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[22:50:46] [PASSED] drm_test_rect_clip_scaled_not_clipped
[22:50:46] [PASSED] drm_test_rect_clip_scaled_clipped
[22:50:46] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[22:50:46] ================= drm_test_rect_intersect  =================
[22:50:46] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[22:50:46] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[22:50:46] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[22:50:46] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[22:50:46] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[22:50:46] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[22:50:46] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[22:50:46] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[22:50:46] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[22:50:46] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[22:50:46] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[22:50:46] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[22:50:46] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[22:50:46] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[22:50:46] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[22:50:46] ============= [PASSED] drm_test_rect_intersect =============
[22:50:46] ================ drm_test_rect_calc_hscale  ================
[22:50:46] [PASSED] normal use
[22:50:46] [PASSED] out of max range
[22:50:46] [PASSED] out of min range
[22:50:46] [PASSED] zero dst
[22:50:46] [PASSED] negative src
[22:50:46] [PASSED] negative dst
[22:50:46] ============ [PASSED] drm_test_rect_calc_hscale ============
[22:50:46] ================ drm_test_rect_calc_vscale  ================
[22:50:46] [PASSED] normal use
[22:50:46] [PASSED] out of max range
[22:50:46] [PASSED] out of min range
[22:50:46] [PASSED] zero dst
[22:50:46] [PASSED] negative src
[22:50:46] [PASSED] negative dst
[22:50:46] ============ [PASSED] drm_test_rect_calc_vscale ============
[22:50:46] ================== drm_test_rect_rotate  ===================
[22:50:46] [PASSED] reflect-x
[22:50:46] [PASSED] reflect-y
[22:50:46] [PASSED] rotate-0
[22:50:46] [PASSED] rotate-90
[22:50:46] [PASSED] rotate-180
[22:50:46] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[22:50:46] ============== [PASSED] drm_test_rect_rotate ===============
[22:50:46] ================ drm_test_rect_rotate_inv  =================
[22:50:46] [PASSED] reflect-x
[22:50:46] [PASSED] reflect-y
[22:50:46] [PASSED] rotate-0
[22:50:46] [PASSED] rotate-90
[22:50:46] [PASSED] rotate-180
[22:50:46] [PASSED] rotate-270
[22:50:46] ============ [PASSED] drm_test_rect_rotate_inv =============
[22:50:46] ==================== [PASSED] drm_rect =====================
[22:50:46] ============ drm_sysfb_modeset_test (1 subtest) ============
[22:50:46] ============ drm_test_sysfb_build_fourcc_list  =============
[22:50:46] [PASSED] no native formats
[22:50:46] [PASSED] XRGB8888 as native format
[22:50:46] [PASSED] remove duplicates
[22:50:46] [PASSED] convert alpha formats
[22:50:46] [PASSED] random formats
[22:50:46] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[22:50:46] ============= [PASSED] drm_sysfb_modeset_test ==============
[22:50:46] ============================================================
[22:50:46] Testing complete. Ran 616 tests: passed: 616
[22:50:46] Elapsed time: 23.383s total, 1.651s configuring, 21.559s building, 0.143s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[22:50:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:50:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:50:55] Starting KUnit Kernel (1/1)...
[22:50:55] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:50:55] ================= ttm_device (5 subtests) ==================
[22:50:55] [PASSED] ttm_device_init_basic
[22:50:55] [PASSED] ttm_device_init_multiple
[22:50:55] [PASSED] ttm_device_fini_basic
[22:50:55] [PASSED] ttm_device_init_no_vma_man
[22:50:55] ================== ttm_device_init_pools  ==================
[22:50:55] [PASSED] No DMA allocations, no DMA32 required
[22:50:55] [PASSED] DMA allocations, DMA32 required
[22:50:55] [PASSED] No DMA allocations, DMA32 required
[22:50:55] [PASSED] DMA allocations, no DMA32 required
[22:50:55] ============== [PASSED] ttm_device_init_pools ==============
[22:50:55] =================== [PASSED] ttm_device ====================
[22:50:55] ================== ttm_pool (8 subtests) ===================
[22:50:55] ================== ttm_pool_alloc_basic  ===================
[22:50:55] [PASSED] One page
[22:50:55] [PASSED] More than one page
[22:50:55] [PASSED] Above the allocation limit
[22:50:55] [PASSED] One page, with coherent DMA mappings enabled
[22:50:55] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:50:55] ============== [PASSED] ttm_pool_alloc_basic ===============
[22:50:55] ============== ttm_pool_alloc_basic_dma_addr  ==============
[22:50:55] [PASSED] One page
[22:50:55] [PASSED] More than one page
[22:50:55] [PASSED] Above the allocation limit
[22:50:55] [PASSED] One page, with coherent DMA mappings enabled
[22:50:55] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:50:55] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[22:50:55] [PASSED] ttm_pool_alloc_order_caching_match
[22:50:55] [PASSED] ttm_pool_alloc_caching_mismatch
[22:50:55] [PASSED] ttm_pool_alloc_order_mismatch
[22:50:55] [PASSED] ttm_pool_free_dma_alloc
[22:50:55] [PASSED] ttm_pool_free_no_dma_alloc
[22:50:55] [PASSED] ttm_pool_fini_basic
[22:50:55] ==================== [PASSED] ttm_pool =====================
[22:50:55] ================ ttm_resource (8 subtests) =================
[22:50:55] ================= ttm_resource_init_basic  =================
[22:50:55] [PASSED] Init resource in TTM_PL_SYSTEM
[22:50:55] [PASSED] Init resource in TTM_PL_VRAM
[22:50:55] [PASSED] Init resource in a private placement
[22:50:55] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[22:50:55] ============= [PASSED] ttm_resource_init_basic =============
[22:50:55] [PASSED] ttm_resource_init_pinned
[22:50:55] [PASSED] ttm_resource_fini_basic
[22:50:55] [PASSED] ttm_resource_manager_init_basic
[22:50:55] [PASSED] ttm_resource_manager_usage_basic
[22:50:55] [PASSED] ttm_resource_manager_set_used_basic
[22:50:56] [PASSED] ttm_sys_man_alloc_basic
[22:50:56] [PASSED] ttm_sys_man_free_basic
[22:50:56] ================== [PASSED] ttm_resource ===================
[22:50:56] =================== ttm_tt (15 subtests) ===================
[22:50:56] ==================== ttm_tt_init_basic  ====================
[22:50:56] [PASSED] Page-aligned size
[22:50:56] [PASSED] Extra pages requested
[22:50:56] ================ [PASSED] ttm_tt_init_basic ================
[22:50:56] [PASSED] ttm_tt_init_misaligned
[22:50:56] [PASSED] ttm_tt_fini_basic
[22:50:56] [PASSED] ttm_tt_fini_sg
[22:50:56] [PASSED] ttm_tt_fini_shmem
[22:50:56] [PASSED] ttm_tt_create_basic
[22:50:56] [PASSED] ttm_tt_create_invalid_bo_type
[22:50:56] [PASSED] ttm_tt_create_ttm_exists
[22:50:56] [PASSED] ttm_tt_create_failed
[22:50:56] [PASSED] ttm_tt_destroy_basic
[22:50:56] [PASSED] ttm_tt_populate_null_ttm
[22:50:56] [PASSED] ttm_tt_populate_populated_ttm
[22:50:56] [PASSED] ttm_tt_unpopulate_basic
[22:50:56] [PASSED] ttm_tt_unpopulate_empty_ttm
[22:50:56] [PASSED] ttm_tt_swapin_basic
[22:50:56] ===================== [PASSED] ttm_tt ======================
[22:50:56] =================== ttm_bo (14 subtests) ===================
[22:50:56] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[22:50:56] [PASSED] Cannot be interrupted and sleeps
[22:50:56] [PASSED] Cannot be interrupted, locks straight away
[22:50:56] [PASSED] Can be interrupted, sleeps
[22:50:56] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[22:50:56] [PASSED] ttm_bo_reserve_locked_no_sleep
[22:50:56] [PASSED] ttm_bo_reserve_no_wait_ticket
[22:50:56] [PASSED] ttm_bo_reserve_double_resv
[22:50:56] [PASSED] ttm_bo_reserve_interrupted
[22:50:56] [PASSED] ttm_bo_reserve_deadlock
[22:50:56] [PASSED] ttm_bo_unreserve_basic
[22:50:56] [PASSED] ttm_bo_unreserve_pinned
[22:50:56] [PASSED] ttm_bo_unreserve_bulk
[22:50:56] [PASSED] ttm_bo_put_basic
[22:50:56] [PASSED] ttm_bo_put_shared_resv
[22:50:56] [PASSED] ttm_bo_pin_basic
[22:50:56] [PASSED] ttm_bo_pin_unpin_resource
[22:50:56] [PASSED] ttm_bo_multiple_pin_one_unpin
[22:50:56] ===================== [PASSED] ttm_bo ======================
[22:50:56] ============== ttm_bo_validate (22 subtests) ===============
[22:50:56] ============== ttm_bo_init_reserved_sys_man  ===============
[22:50:56] [PASSED] Buffer object for userspace
[22:50:56] [PASSED] Kernel buffer object
[22:50:56] [PASSED] Shared buffer object
[22:50:56] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[22:50:56] ============== ttm_bo_init_reserved_mock_man  ==============
[22:50:56] [PASSED] Buffer object for userspace
[22:50:56] [PASSED] Kernel buffer object
[22:50:56] [PASSED] Shared buffer object
[22:50:56] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[22:50:56] [PASSED] ttm_bo_init_reserved_resv
[22:50:56] ================== ttm_bo_validate_basic  ==================
[22:50:56] [PASSED] Buffer object for userspace
[22:50:56] [PASSED] Kernel buffer object
[22:50:56] [PASSED] Shared buffer object
[22:50:56] ============== [PASSED] ttm_bo_validate_basic ==============
[22:50:56] [PASSED] ttm_bo_validate_invalid_placement
[22:50:56] ============= ttm_bo_validate_same_placement  ==============
[22:50:56] [PASSED] System manager
[22:50:56] [PASSED] VRAM manager
[22:50:56] ========= [PASSED] ttm_bo_validate_same_placement ==========
[22:50:56] [PASSED] ttm_bo_validate_failed_alloc
[22:50:56] [PASSED] ttm_bo_validate_pinned
[22:50:56] [PASSED] ttm_bo_validate_busy_placement
[22:50:56] ================ ttm_bo_validate_multihop  =================
[22:50:56] [PASSED] Buffer object for userspace
[22:50:56] [PASSED] Kernel buffer object
[22:50:56] [PASSED] Shared buffer object
[22:50:56] ============ [PASSED] ttm_bo_validate_multihop =============
[22:50:56] ========== ttm_bo_validate_no_placement_signaled  ==========
[22:50:56] [PASSED] Buffer object in system domain, no page vector
[22:50:56] [PASSED] Buffer object in system domain with an existing page vector
[22:50:56] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[22:50:56] ======== ttm_bo_validate_no_placement_not_signaled  ========
[22:50:56] [PASSED] Buffer object for userspace
[22:50:56] [PASSED] Kernel buffer object
[22:50:56] [PASSED] Shared buffer object
[22:50:56] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[22:50:56] [PASSED] ttm_bo_validate_move_fence_signaled
[22:50:56] ========= ttm_bo_validate_move_fence_not_signaled  =========
[22:50:56] [PASSED] Waits for GPU
[22:50:56] [PASSED] Tries to lock straight away
[22:50:56] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[22:50:56] [PASSED] ttm_bo_validate_swapout
[22:50:56] [PASSED] ttm_bo_validate_happy_evict
[22:50:56] [PASSED] ttm_bo_validate_all_pinned_evict
[22:50:56] [PASSED] ttm_bo_validate_allowed_only_evict
[22:50:56] [PASSED] ttm_bo_validate_deleted_evict
[22:50:56] [PASSED] ttm_bo_validate_busy_domain_evict
[22:50:56] [PASSED] ttm_bo_validate_evict_gutting
[22:50:56] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[22:50:56] ================= [PASSED] ttm_bo_validate =================
[22:50:56] ============================================================
[22:50:56] Testing complete. Ran 102 tests: passed: 102
[22:50:56] Elapsed time: 9.907s total, 1.614s configuring, 7.676s building, 0.532s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: LRC refactors

[Patchwork]

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== Series Details ==

Series: drm/xe: LRC refactors
URL   : https://patchwork.freedesktop.org/series/151152/
State : success

== Summary ==

CI Bug Log - changes from xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3_BAT -> xe-pw-151152v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (9 -> 8)
------------------------------

  Missing    (1): bat-adlp-vm 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3 -> xe-pw-151152v1

  IGT_8438: 8438
  xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3: 9b3696db59b3b683fa74e9a687621672984d69d3
  xe-pw-151152v1: 151152v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/index.html

[-- Attachment #2: Type: text/html, Size: 1385 bytes --]

✗ Xe.CI.Full: failure for drm/xe: LRC refactors

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 32758 bytes --]

== Series Details ==

Series: drm/xe: LRC refactors
URL   : https://patchwork.freedesktop.org/series/151152/
State : failure

== Summary ==

CI Bug Log - changes from xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3_FULL -> xe-pw-151152v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-151152v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-151152v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-151152v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-dp-4.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  
Known issues
------------

  Here are the changes found in xe-pw-151152v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][5] ([Intel XE#316])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-adlp:         [PASS][6] -> [DMESG-FAIL][7] ([Intel XE#4543])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][8] ([Intel XE#1124]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          [PASS][9] -> [SKIP][10] ([Intel XE#2314] / [Intel XE#2894])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#2191]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_bw@connected-linear-tiling-3-displays-3840x2160p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#787]) +195 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-435/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][13] ([Intel XE#455] / [Intel XE#787]) +30 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-432/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-d-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2652] / [Intel XE#787]) +7 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-a-dp-2.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][15] -> [DMESG-WARN][16] ([Intel XE#1727] / [Intel XE#3113])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][17] -> [INCOMPLETE][18] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][19] -> [INCOMPLETE][20] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522]) +1 other test incomplete
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][21] -> [INCOMPLETE][22] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-dp-4.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#306]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#373])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#308])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
    - shard-bmg:          [PASS][26] -> [SKIP][27] ([Intel XE#2291]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2-set2:     NOTRUN -> [SKIP][28] ([Intel XE#323])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-bmg:          [PASS][29] -> [SKIP][30] ([Intel XE#2316]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1:
    - shard-adlp:         [PASS][31] -> [DMESG-WARN][32] ([Intel XE#4543]) +10 other tests dmesg-warn
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-adlp-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-adlp-3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][33] -> [FAIL][34] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate:
    - shard-bmg:          [PASS][35] -> [FAIL][36] ([Intel XE#3098]) +1 other test fail
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_flip@plain-flip-fb-recreate.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-5/igt@kms_flip@plain-flip-fb-recreate.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move:
    - shard-dg2-set2:     NOTRUN -> [SKIP][37] ([Intel XE#651]) +6 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][38] ([Intel XE#653]) +7 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-bmg:          [PASS][39] -> [SKIP][40] ([Intel XE#1503])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-4/igt@kms_hdr@invalid-metadata-sizes.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [PASS][41] -> [SKIP][42] ([Intel XE#3012])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-2/igt@kms_joiner@basic-force-big-joiner.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#4359])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-adlp:         [PASS][44] -> [DMESG-WARN][45] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-adlp-3/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-adlp-6/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [PASS][46] -> [SKIP][47] ([Intel XE#4596])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-4.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-dg2-set2:     NOTRUN -> [SKIP][48] ([Intel XE#5021])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#1489])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@fbc-psr-no-drrs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#2850] / [Intel XE#929]) +3 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_psr@fbc-psr-no-drrs.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2-set2:     NOTRUN -> [SKIP][51] ([Intel XE#1127])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-dg2-set2:     NOTRUN -> [SKIP][52] ([Intel XE#455]) +7 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-lnl:          [PASS][53] -> [FAIL][54] ([Intel XE#2883]) +2 other tests fail
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-lnl-6/igt@kms_setmode@basic@pipe-b-edp-1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-lnl-4/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@xe_copy_basic@mem-copy-linear-0x3fff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#1123])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_copy_basic@mem-copy-linear-0x3fff.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-dg2-set2:     NOTRUN -> [SKIP][56] ([Intel XE#4518])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-dg2-set2:     [PASS][57] -> [SKIP][58] ([Intel XE#1392]) +8 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-464/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_fault_mode@many-userptr-invalidate-imm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#288]) +5 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_exec_fault_mode@many-userptr-invalidate-imm.html

  * igt@xe_exec_sip_eudebug@breakpoint-writesip-twice:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#4837]) +2 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_exec_sip_eudebug@breakpoint-writesip-twice.html

  * igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][61] ([Intel XE#4915]) +61 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_exec_system_allocator@process-many-large-execqueues-mmap-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset:
    - shard-lnl:          [PASS][62] -> [FAIL][63] ([Intel XE#5018])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-lnl-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-new-bo-map-nomemset.html

  * igt@xe_oa@whitelisted-registers-userspace-config:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#2541] / [Intel XE#3573]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_oa@whitelisted-registers-userspace-config.html

  * igt@xe_pm@s2idle-mocs:
    - shard-dg2-set2:     [PASS][65] -> [INCOMPLETE][66] ([Intel XE#4504])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-432/igt@xe_pm@s2idle-mocs.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-466/igt@xe_pm@s2idle-mocs.html

  * igt@xe_pxp@pxp-stale-queue-post-termination-irq:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#4733])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_pxp@pxp-stale-queue-post-termination-irq.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#944])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-463/igt@xe_query@multigpu-query-engines.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-transition-nonblocking:
    - shard-adlp:         [DMESG-WARN][69] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][70] +3 other tests pass
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-adlp-4/igt@kms_atomic_transition@plane-all-transition-nonblocking.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-adlp-8/igt@kms_atomic_transition@plane-all-transition-nonblocking.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][71] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][72] +1 other test pass
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-7/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][73] ([Intel XE#2291]) -> [PASS][74] +4 other tests pass
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-7/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [SKIP][75] ([Intel XE#3009]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_dp_aux_dev.html
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-4/igt@kms_dp_aux_dev.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-bmg:          [SKIP][77] ([Intel XE#2316]) -> [PASS][78] +6 other tests pass
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - shard-adlp:         [DMESG-WARN][79] ([Intel XE#4543]) -> [PASS][80] +10 other tests pass
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-adlp-3/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-adlp-4/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [SKIP][81] ([Intel XE#1435]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@xe_eu_stall@blocking-read:
    - shard-bmg:          [FAIL][83] -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-5/igt@xe_eu_stall@blocking-read.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-7/igt@xe_eu_stall@blocking-read.html

  * igt@xe_exec_basic@multigpu-no-exec-rebind:
    - shard-dg2-set2:     [SKIP][85] ([Intel XE#1392]) -> [PASS][86] +5 other tests pass
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-432/igt@xe_exec_basic@multigpu-no-exec-rebind.html
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-466/igt@xe_exec_basic@multigpu-no-exec-rebind.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset:
    - shard-lnl:          [FAIL][87] ([Intel XE#5018]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-lnl-6/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-lnl-4/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-new-bo-map-nomemset.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     [FAIL][89] ([Intel XE#5166]) -> [PASS][90] +1 other test pass
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-432/igt@xe_pmu@gt-frequency.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-466/igt@xe_pmu@gt-frequency.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][91] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#3124] / [Intel XE#4345]) -> [INCOMPLETE][92] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [FAIL][93] ([Intel XE#1178]) -> [SKIP][94] ([Intel XE#2341])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-4/igt@kms_content_protection@srm.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][95] ([Intel XE#2311]) -> [SKIP][96] ([Intel XE#2312]) +12 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-bmg:          [SKIP][97] ([Intel XE#2312]) -> [SKIP][98] ([Intel XE#4141]) +6 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][99] ([Intel XE#4141]) -> [SKIP][100] ([Intel XE#2312]) +9 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][101] ([Intel XE#2312]) -> [SKIP][102] ([Intel XE#2311]) +14 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][103] ([Intel XE#2313]) -> [SKIP][104] ([Intel XE#2312]) +16 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][105] ([Intel XE#2312]) -> [SKIP][106] ([Intel XE#2313]) +12 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][107] ([Intel XE#5021]) -> [SKIP][108] ([Intel XE#4596])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-yf.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-adlp:         [FAIL][109] ([Intel XE#3325]) -> [SKIP][110] ([Intel XE#734])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-adlp-8/igt@kms_pm_dc@dc9-dpms.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-adlp-2/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     [SKIP][111] ([Intel XE#362]) -> [FAIL][112] ([Intel XE#1729])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/shard-dg2-433/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3124
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3325
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#5018]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5018
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5166]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5166
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#734]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/734
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3 -> xe-pw-151152v1

  IGT_8438: 8438
  xe-3345-9b3696db59b3b683fa74e9a687621672984d69d3: 9b3696db59b3b683fa74e9a687621672984d69d3
  xe-pw-151152v1: 151152v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-151152v1/index.html

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