Re: [PATCH v4 0/3] BMG PCIe Gen5 downgrade attributes and usage

[Raag Jadav <raag.jadav@intel.com>]

On Mon, Apr 28, 2025 at 04:09:05PM -0400, Rodrigo Vivi wrote:
> On Mon, Apr 28, 2025 at 04:00:44PM -0400, Rodrigo Vivi wrote:
> > On Mon, Apr 28, 2025 at 01:12:38PM +0300, Raag Jadav wrote:
> > > On Fri, Apr 25, 2025 at 07:36:23PM +0530, Raag Jadav wrote:
> > > > This series exposes sysfs attributes for BMG PCIe Gen5 downgrade and
> > > > documents their usage.
> > > 
> > > Anything I can do to move this forward?
> > 
> > I almost push it here, but then I noticed that it is gen5_downgrade.
> > Hadn't we agreed to follow what spec says so?
> > 
> > "to then automatically persist the Gen4 downgrade flag in Flash"
> > "Write Gen4 Downgrade bit to MRC Flash File"
> > 
> > == Applying  PCIe Gen4 Downgrade ==
> > 
> > Although I see that there are some mentions calling "Gen5 downgrade", "Gen4 downgrade" seems to be the most used term in the specs, specially when calling bits and
> > sections names...

Which is what I followed until we had a change of preference over gen definition.
https://lore.kernel.org/intel-xe/34b33d3135fc24302db2764ce86a641e7c49054f.camel@intel.com/

> Because of the inconsistencies and our back and forth here and to get prepared
> for future cases where we might need to downgrade from gen6 to gen5, the current
> Architecture recommendation is to simply go with
> 
> so /sys/bus/pci/devices/<bdf>/pcie_gen_downgrade_{status,capable}

I really like Lucas' proposal, which is also consistent with similar existing
attributes.

/sys/bus/pci/devices/<bdf>/auto_link_downgrade_capable

Think we should give it a try?

Raag