Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Raag Jadav <raag.jadav@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"Nilawar, Badal" <badal.nilawar@intel.com>,
	"Tauro, Riana" <riana.tauro@intel.com>,
	"Gupta, Anshuman" <anshuman.gupta@intel.com>
Subject: Re: [PATCH v4 0/3] BMG PCIe Gen5 downgrade attributes and usage
Date: Fri, 2 May 2025 20:27:02 +0300	[thread overview]
Message-ID: <aBUAZmM8XIRCVun3@black.fi.intel.com> (raw)
In-Reply-To: <sh6cpgadw6gk2jufhaoqpmz3mteegl2gnfpqxg7zgwmbm6vu76@kksxyzna74yc>

On Fri, May 02, 2025 at 11:16:02AM -0500, Lucas De Marchi wrote:
> On Thu, May 01, 2025 at 05:19:16AM +0300, Raag Jadav wrote:
> > On Thu, May 01, 2025 at 01:10:49AM +0530, Vivi, Rodrigo wrote:
> > > On Tue, 2025-04-29 at 08:38 +0300, Raag Jadav wrote:
> > > > On Mon, Apr 28, 2025 at 04:09:05PM -0400, Rodrigo Vivi wrote:
> > > > > On Mon, Apr 28, 2025 at 04:00:44PM -0400, Rodrigo Vivi wrote:
> > > > > > On Mon, Apr 28, 2025 at 01:12:38PM +0300, Raag Jadav wrote:
> > > > > > > On Fri, Apr 25, 2025 at 07:36:23PM +0530, Raag Jadav wrote:
> > > > > > > > This series exposes sysfs attributes for BMG PCIe Gen5
> > > > > > > > downgrade and
> > > > > > > > documents their usage.
> > > > > > >
> > > > > > > Anything I can do to move this forward?
> > > > > >
> > > > > > I almost push it here, but then I noticed that it is
> > > > > > gen5_downgrade.
> > > > > > Hadn't we agreed to follow what spec says so?
> > > > > >
> > > > > > "to then automatically persist the Gen4 downgrade flag in Flash"
> > > > > > "Write Gen4 Downgrade bit to MRC Flash File"
> > > > > >
> > > > > > == Applying  PCIe Gen4 Downgrade ==
> > > > > >
> > > > > > Although I see that there are some mentions calling "Gen5
> > > > > > downgrade", "Gen4 downgrade" seems to be the most used term in
> > > > > > the specs, specially when calling bits and
> > > > > > sections names...
> > > >
> > > > Which is what I followed until we had a change of preference over gen
> > > > definition.
> > > > https://lore.kernel.org/intel-xe/34b33d3135fc24302db2764ce86a641e7c49054f.camel@intel.com/
> > > >
> > > > > Because of the inconsistencies and our back and forth here and to
> > > > > get prepared
> > > > > for future cases where we might need to downgrade from gen6 to
> > > > > gen5, the current
> > > > > Architecture recommendation is to simply go with
> > > > >
> > > > > so /sys/bus/pci/devices/<bdf>/pcie_gen_downgrade_{status,capable}
> > > >
> > > > I really like Lucas' proposal, which is also consistent with similar
> > > > existing
> > > > attributes.
> > > >
> > > > /sys/bus/pci/devices/<bdf>/auto_link_downgrade_capable
> > > 
> > > I'm sorry for the delay in the response, it took a while to get
> > > confirmation. We can go with this one. or with the one you sent
> > > already. Your call. Just let me know that I push the version you tell
> > > and tell the architects to update the spec.
> > 
> > I'm okay with either one. But since it was Lucas' idea, let's hear his
> > thoughts.
> > 
> > Lucas, can we move forward with auto_link_downgrade_capable?
> 
> yes, I'm ok with that.

We also have ack from the architecture. Thank you for the suggestion.
I'll add you to the credits :)

Raag

      reply	other threads:[~2025-05-02 17:27 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25 14:06 [PATCH v4 0/3] BMG PCIe Gen5 downgrade attributes and usage Raag Jadav
2025-04-25 14:06 ` [PATCH v4 1/3] drm/xe/pm: s/xe_device_sysfs_init/xe_pm_sysfs_init Raag Jadav
2025-04-25 14:06 ` [PATCH v4 2/3] drm/xe: Expose PCIe Gen5 downgrade attributes Raag Jadav
2025-04-25 14:06 ` [PATCH v4 3/3] drm/xe/doc: Wire up PCIe Gen5 limitations Raag Jadav
2025-04-25 16:03 ` ✓ CI.Patch_applied: success for BMG PCIe Gen5 downgrade attributes and usage Patchwork
2025-04-25 16:03 ` ✓ CI.checkpatch: " Patchwork
2025-04-25 16:04 ` ✓ CI.KUnit: " Patchwork
2025-04-25 16:13 ` ✓ CI.Build: " Patchwork
2025-04-25 16:15 ` ✓ CI.Hooks: " Patchwork
2025-04-25 16:16 ` ✓ CI.checksparse: " Patchwork
2025-04-25 17:10 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-28 10:12 ` [PATCH v4 0/3] " Raag Jadav
2025-04-28 20:00   ` Rodrigo Vivi
2025-04-28 20:09     ` Rodrigo Vivi
2025-04-29  5:38       ` Raag Jadav
2025-04-30 19:40         ` Vivi, Rodrigo
2025-05-01  2:19           ` Raag Jadav
2025-05-02 16:16             ` Lucas De Marchi
2025-05-02 17:27               ` Raag Jadav [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aBUAZmM8XIRCVun3@black.fi.intel.com \
    --to=raag.jadav@intel.com \
    --cc=anshuman.gupta@intel.com \
    --cc=badal.nilawar@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=lucas.demarchi@intel.com \
    --cc=riana.tauro@intel.com \
    --cc=rodrigo.vivi@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox