* [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure
@ 2025-06-20 21:49 Matt Atwood
2025-06-20 21:49 ` [PATCH 1/5] drm/xe: add xe_soc_wa infrastructure Matt Atwood
` (8 more replies)
0 siblings, 9 replies; 16+ messages in thread
From: Matt Atwood @ 2025-06-20 21:49 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Matt Atwood
There currently isnt a way to apply and track workarounds that are
needed ahead of GT init. This series adds another bit field to the
xe_device structure similar to those in the gts to track workarounds
applied at runtime.
SoC workarounds in this new infrastructure are tracked in the existing
sysfs entries gtX/workarounds.
Currently 15015404425 is the only workaround like this, so move this
workaround to this new infrastructure.
Additionally, there is currently no way for us to be able to determine
Compute die stepping before GT initialization. Workaround 15015404425
applies to PTL for only A0 silicon. During probe we will have to apply
it conditionally to the platform. After the workaround use a GT OOB
workaround to toggle the bit in the table if it no longer applies.
Matt Atwood (5):
drm/xe: add xe_soc_wa infrastructure
drm/xe: Add infrastructe for SoC OOB workarounds
drm/xe: Move Wa_15015404425 to use the new EX_SOC_WA macro
drm/xe: extend Wa_15015404425 to apply to PTL
drm/xe: disable wa_15015404425 for PTL B0
drivers/gpu/drm/xe/Makefile | 11 +++++-
drivers/gpu/drm/xe/xe_device_types.h | 8 +++++
drivers/gpu/drm/xe/xe_gen_wa_oob.c | 27 ++++++++++-----
drivers/gpu/drm/xe/xe_mmio.c | 10 +++---
drivers/gpu/drm/xe/xe_pci.c | 10 ++++++
drivers/gpu/drm/xe/xe_rtp.c | 5 +++
drivers/gpu/drm/xe/xe_rtp.h | 3 +-
drivers/gpu/drm/xe/xe_rtp_types.h | 2 ++
drivers/gpu/drm/xe/xe_soc_wa_oob.rules | 2 ++
drivers/gpu/drm/xe/xe_wa.c | 46 ++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_wa.h | 18 ++++++++--
drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
12 files changed, 125 insertions(+), 18 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_soc_wa_oob.rules
--
2.49.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/5] drm/xe: add xe_soc_wa infrastructure
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
@ 2025-06-20 21:49 ` Matt Atwood
2025-06-20 21:49 ` [PATCH 2/5] drm/xe: Add infrastructure for SoC OOB workarounds Matt Atwood
` (7 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Matt Atwood @ 2025-06-20 21:49 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Matt Atwood
There are some workarounds that must be applied before gt init,
wa_150154044425 for example. Instead of sprinkling them conditionally
throughout the driver as we did for i915 generate an oob.rules file
reusing the RTP infrastructure to make these easier to track.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/xe/Makefile | 11 ++++++++++-
drivers/gpu/drm/xe/xe_gen_wa_oob.c | 27 ++++++++++++++++++--------
drivers/gpu/drm/xe/xe_soc_wa_oob.rules | 0
3 files changed, 29 insertions(+), 9 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_soc_wa_oob.rules
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 40d01751b49e..6b22e95002d5 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -21,6 +21,15 @@ $(obj)/generated/%_wa_oob.c $(obj)/generated/%_wa_oob.h: $(obj)/xe_gen_wa_oob \
$(src)/xe_wa_oob.rules
$(call cmd,wa_oob)
+generated_soc_oob := $(obj)/generated/xe_soc_wa_oob.c $(obj)/generated/xe_soc_wa_oob.h
+quiet_cmd_soc_wa_oob = GEN $(notdir $(generated_soc_oob))
+ cmd_soc_wa_oob = mkdir -p $(@D); $^ $(generated_soc_oob)
+$(obj)/generated/%_soc_wa_oob.c $(obj)/generated/%_soc_wa_oob.h: $(obj)/xe_gen_wa_oob \
+ $(src)/xe_soc_wa_oob.rules
+ $(call cmd,soc_wa_oob)
+
+
+
# Please keep these build lists sorted!
# core driver code
@@ -338,4 +347,4 @@ $(obj)/%.hdrtest: $(src)/%.h FORCE
$(call if_changed_dep,hdrtest)
uses_generated_oob := $(addprefix $(obj)/, $(xe-y))
-$(uses_generated_oob): $(obj)/generated/xe_wa_oob.h
+$(uses_generated_oob): $(obj)/generated/xe_wa_oob.h $(obj)/generated/xe_soc_wa_oob.h
diff --git a/drivers/gpu/drm/xe/xe_gen_wa_oob.c b/drivers/gpu/drm/xe/xe_gen_wa_oob.c
index ed9183599e31..0484ed44e5d6 100644
--- a/drivers/gpu/drm/xe/xe_gen_wa_oob.c
+++ b/drivers/gpu/drm/xe/xe_gen_wa_oob.c
@@ -18,8 +18,8 @@
" *\n" \
" * This file was generated from rules: %s\n" \
" */\n" \
- "#ifndef _GENERATED_XE_WA_OOB_\n" \
- "#define _GENERATED_XE_WA_OOB_\n" \
+ "#ifndef _GENERATED_%s_\n" \
+ "#define _GENERATED_%s_\n" \
"\n" \
"enum {\n"
@@ -52,7 +52,7 @@ static char *strip(char *line, size_t linelen)
}
#define MAX_LINE_LEN 4096
-static int parse(FILE *input, FILE *csource, FILE *cheader)
+static int parse(FILE *input, FILE *csource, FILE *cheader, bool soc)
{
char line[MAX_LINE_LEN + 1];
char *name, *prev_name = NULL, *rules;
@@ -96,7 +96,10 @@ static int parse(FILE *input, FILE *csource, FILE *cheader)
}
if (name) {
- fprintf(cheader, "\tXE_WA_OOB_%s = %u,\n", name, idx);
+ if (soc == false)
+ fprintf(cheader, "\tXE_WA_OOB_%s = %u,\n", name, idx);
+ else
+ fprintf(cheader, "\tXE_SOC_WA_OOB_%s = %u,\n", name, idx);
/* Close previous entry before starting a new one */
if (idx)
@@ -117,8 +120,10 @@ static int parse(FILE *input, FILE *csource, FILE *cheader)
/* Close last entry */
if (idx)
fprintf(csource, ") },\n");
-
- fprintf(cheader, "\t_XE_WA_OOB_COUNT = %u\n", idx);
+ if (soc == false)
+ fprintf(cheader, "\t_XE_WA_OOB_COUNT = %u\n", idx);
+ else
+ fprintf(cheader, "\t_XE_SOC_WA_OOB_COUNT = %u\n", idx);
return 0;
}
@@ -157,9 +162,15 @@ int main(int argc, const char *argv[])
}
}
- fprintf(args[ARGS_CHEADER].f, HEADER, args[ARGS_INPUT].fn);
+ char *soc = strstr(args[ARGS_CHEADER].fn, "soc_");
+ if (soc == NULL)
+ fprintf(args[ARGS_CHEADER].f, HEADER, args[ARGS_INPUT].fn, "XE_WA_OOB", "XE_WA_OOB");
+ else
+ fprintf(args[ARGS_CHEADER].f, HEADER, args[ARGS_INPUT].fn, "XE_SOC_WA_OOB", "XE_SOC_WA_OOB");
+
+ bool prefix = soc != NULL ? true : false;
ret = parse(args[ARGS_INPUT].f, args[ARGS_CSOURCE].f,
- args[ARGS_CHEADER].f);
+ args[ARGS_CHEADER].f, prefix);
if (!ret)
fprintf(args[ARGS_CHEADER].f, FOOTER);
diff --git a/drivers/gpu/drm/xe/xe_soc_wa_oob.rules b/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
new file mode 100644
index 000000000000..e69de29bb2d1
--
2.49.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/5] drm/xe: Add infrastructure for SoC OOB workarounds
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
2025-06-20 21:49 ` [PATCH 1/5] drm/xe: add xe_soc_wa infrastructure Matt Atwood
@ 2025-06-20 21:49 ` Matt Atwood
2025-06-20 21:49 ` [PATCH 3/5] drm/xe: Move Wa_15015404425 to use the new EX_SOC_WA macro Matt Atwood
` (6 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Matt Atwood @ 2025-06-20 21:49 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Matt Atwood
Some workarounds need to be able to be applied ahead of any GT
initialization, for example 15015404425. This patches creates a
mechanism simlar to the GT related OOB workarounds where we can more
easily track them, and query them. This should alleviate some of the
complexity that existed in i915, as these types of workarounds were
added overtime.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 8 +++++
drivers/gpu/drm/xe/xe_pci.c | 4 +++
drivers/gpu/drm/xe/xe_rtp.c | 5 +++
drivers/gpu/drm/xe/xe_rtp.h | 3 +-
drivers/gpu/drm/xe/xe_rtp_types.h | 2 ++
drivers/gpu/drm/xe/xe_wa.c | 46 ++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_wa.h | 18 +++++++++--
7 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 003afb279a5e..aa1558369100 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -357,6 +357,14 @@ struct xe_device {
u8 skip_pcode:1;
} info;
+ /** @xe_active.oob: bitmap with active OOB workarounds */
+ unsigned long *oob;
+ /**
+ * @xe_active.oob_initialized: mark oob as initialized to help
+ * detecting misuse of XE_SOC_WA() - it can only be called on
+ * initialization after SOC OOB WAs have been processed */
+ bool oob_initialized;
+
/** @survivability: survivability information for device */
struct xe_survivability survivability;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 5ff2169019ed..ded0f3dc8d73 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -32,6 +32,7 @@
#include "xe_step.h"
#include "xe_survivability_mode.h"
#include "xe_tile.h"
+#include "xe_wa.h"
enum toggle_d3cold {
D3COLD_DISABLE,
@@ -826,6 +827,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if (err)
return err;
+ xe_soc_wa_init(xe);
+ xe_soc_wa_process_oob(xe);
+
err = xe_device_probe_early(xe);
/*
* In Boot Survivability mode, no drm card is exposed and driver
diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
index 29e694bb1219..b074d8b285ab 100644
--- a/drivers/gpu/drm/xe/xe_rtp.c
+++ b/drivers/gpu/drm/xe/xe_rtp.c
@@ -196,6 +196,11 @@ static void rtp_get_context(struct xe_rtp_process_ctx *ctx,
*gt = (*hwe)->gt;
*xe = gt_to_xe(*gt);
break;
+ case XE_RTP_PROCESS_TYPE_SOC:
+ *hwe = NULL;
+ *gt = NULL;
+ *xe = ctx->xe;
+ break;
}
}
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 4fe736a11c42..7b23c3c8c24c 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -422,7 +422,8 @@ struct xe_reg_sr;
#define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__), \
struct xe_hw_engine * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE }, \
- struct xe_gt * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT })
+ struct xe_gt * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT }, \
+ struct xe_device * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_SOC })
void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
unsigned long *active_entries,
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 1b76b947c706..0a36a42fb0c0 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -112,12 +112,14 @@ struct xe_rtp_entry {
enum xe_rtp_process_type {
XE_RTP_PROCESS_TYPE_GT,
XE_RTP_PROCESS_TYPE_ENGINE,
+ XE_RTP_PROCESS_TYPE_SOC,
};
struct xe_rtp_process_ctx {
union {
struct xe_gt *gt;
struct xe_hw_engine *hwe;
+ struct xe_device *xe;
};
enum xe_rtp_process_type type;
unsigned long *active_entries;
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index f51218a7a580..5f4af23b11f3 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -11,6 +11,7 @@
#include <linux/fault-inject.h>
#include <generated/xe_wa_oob.h>
+#include <generated/xe_soc_wa_oob.h>
#include "regs/xe_engine_regs.h"
#include "regs/xe_gt_regs.h"
@@ -876,6 +877,13 @@ static __maybe_unused const struct xe_rtp_entry oob_was[] = {
static_assert(ARRAY_SIZE(oob_was) - 1 == _XE_WA_OOB_COUNT);
+static __maybe_unused const struct xe_rtp_entry soc_oob_was[] = {
+#include <generated/xe_soc_wa_oob.c>
+ {}
+};
+
+static_assert(ARRAY_SIZE(soc_oob_was) -1 == _XE_SOC_WA_OOB_COUNT);
+
__diag_pop();
/**
@@ -895,6 +903,39 @@ void xe_wa_process_oob(struct xe_gt *gt)
xe_rtp_process(&ctx, oob_was);
}
+int xe_soc_wa_init(struct xe_device *xe)
+{
+ unsigned long *p;
+
+ p = drmm_kzalloc(&xe->drm,
+ sizeof(xe->oob) * BITS_TO_LONGS(ARRAY_SIZE(soc_oob_was)),
+ GFP_KERNEL);
+
+ if (!p)
+ return -ENOMEM;
+
+ xe->oob = p;
+
+ return 0;
+}
+
+/**
+ * xe_soc_wa_process_oob - process OOB workaround table
+ * @xe: xe device instance process workarounds for
+ *
+ * Process OOB workaround tbale for this platform, marking in @xe the
+ * workardounds that are active.
+ */
+void xe_soc_wa_process_oob(struct xe_device *xe)
+{
+ struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(xe);
+
+ xe_rtp_process_ctx_enable_active_tracking(&ctx, xe->oob, ARRAY_SIZE(soc_oob_was));
+
+ xe->oob_initialized = true;
+ xe_rtp_process(&ctx, soc_oob_was);
+}
+
/**
* xe_wa_process_gt - process GT workaround table
* @gt: GT instance to process workarounds for
@@ -1000,6 +1041,11 @@ void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p)
for_each_set_bit(idx, gt->wa_active.oob, ARRAY_SIZE(oob_was))
if (oob_was[idx].name)
drm_printf_indent(p, 1, "%s\n", oob_was[idx].name);
+
+ drm_printf(p, "\nSoC OOB Workarounds\n");
+ for_each_set_bit(idx, gt_to_xe(gt)->oob, ARRAY_SIZE(soc_oob_was))
+ if (soc_oob_was[idx].name)
+ drm_printf_indent(p, 1, "%s\n", soc_oob_was[idx].name);
}
/*
diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
index 52337405b5bc..2a609bbc8600 100644
--- a/drivers/gpu/drm/xe/xe_wa.h
+++ b/drivers/gpu/drm/xe/xe_wa.h
@@ -14,7 +14,9 @@ struct xe_hw_engine;
struct xe_tile;
int xe_wa_init(struct xe_gt *gt);
+int xe_soc_wa_init(struct xe_device *xe);
void xe_wa_process_oob(struct xe_gt *gt);
+void xe_soc_wa_process_oob(struct xe_device *xe);
void xe_wa_process_gt(struct xe_gt *gt);
void xe_wa_process_engine(struct xe_hw_engine *hwe);
void xe_wa_process_lrc(struct xe_hw_engine *hwe);
@@ -22,14 +24,24 @@ void xe_wa_apply_tile_workarounds(struct xe_tile *tile);
void xe_wa_dump(struct xe_gt *gt, struct drm_printer *p);
/**
- * XE_WA - Out-of-band workarounds, that don't fit the lifecycle any
- * other more specific type
+ * XE_WA - Out-of-band GT workarounds, that don't fit the lifecycle any
+ * other more specific type,
* @gt__: gt instance
- * @id__: XE_OOB_<id__>, as generated by build system in generated/xe_wa_oob.h
+ * @id__: XE_WA_OOB_<id__>, as generated by build system in generated/xe_wa_oob.h
*/
#define XE_WA(gt__, id__) ({ \
xe_gt_assert(gt__, (gt__)->wa_active.oob_initialized); \
test_bit(XE_WA_OOB_ ## id__, (gt__)->wa_active.oob); \
})
+/**
+ * XE_SOC_WA - Out-of-band SoC workarounds, that don't fit the lifecycle any
+ * other more specific type
+ * @xe__: xe_device
+ * @id__: XE_SOC_WA_OOB_<id__>, as generated by build system in generated/xe_wa_oob.h
+ */
+#define XE_SOC_WA(xe__, id__) ({ \
+ xe_assert(xe__, (xe__)->oob_initialized); \
+ test_bit(XE_SOC_WA_OOB_ ## id__, (xe__)->oob); \
+})
#endif
--
2.49.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/5] drm/xe: Move Wa_15015404425 to use the new EX_SOC_WA macro
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
2025-06-20 21:49 ` [PATCH 1/5] drm/xe: add xe_soc_wa infrastructure Matt Atwood
2025-06-20 21:49 ` [PATCH 2/5] drm/xe: Add infrastructure for SoC OOB workarounds Matt Atwood
@ 2025-06-20 21:49 ` Matt Atwood
2025-06-20 21:49 ` [PATCH 4/5] drm/xe: extend Wa_15015404425 to apply to PTL Matt Atwood
` (5 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Matt Atwood @ 2025-06-20 21:49 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Matt Atwood
Move Wa_15015404425 to use the new implemented OOB macro XE_SOC_WA()
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/xe/xe_mmio.c | 10 +++++-----
drivers/gpu/drm/xe/xe_soc_wa_oob.rules | 1 +
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
index 7357458bc0d2..377fa82d1d13 100644
--- a/drivers/gpu/drm/xe/xe_mmio.c
+++ b/drivers/gpu/drm/xe/xe_mmio.c
@@ -22,6 +22,9 @@
#include "xe_macros.h"
#include "xe_sriov.h"
#include "xe_trace.h"
+#include "xe_wa.h"
+
+#include "generated/xe_soc_wa_oob.h"
static void tiles_fini(void *arg)
{
@@ -163,9 +166,6 @@ static void mmio_flush_pending_writes(struct xe_mmio *mmio)
#define DUMMY_REG_OFFSET 0x130030
int i;
- if (mmio->tile->xe->info.platform != XE_LUNARLAKE)
- return;
-
/* 4 dummy writes */
for (i = 0; i < 4; i++)
writel(0, mmio->regs + DUMMY_REG_OFFSET);
@@ -176,8 +176,8 @@ u8 xe_mmio_read8(struct xe_mmio *mmio, struct xe_reg reg)
u32 addr = xe_mmio_adjusted_addr(mmio, reg.addr);
u8 val;
- /* Wa_15015404425 */
- mmio_flush_pending_writes(mmio);
+ if (XE_SOC_WA(mmio->tile->xe, 15015404425))
+ mmio_flush_pending_writes(mmio);
val = readb(mmio->regs + addr);
trace_xe_reg_rw(mmio, false, addr, val, sizeof(val));
diff --git a/drivers/gpu/drm/xe/xe_soc_wa_oob.rules b/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
index e69de29bb2d1..b7d12ea4d65c 100644
--- a/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
@@ -0,0 +1 @@
+15015404425 PLATFORM(LUNARLAKE)
--
2.49.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/5] drm/xe: extend Wa_15015404425 to apply to PTL
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
` (2 preceding siblings ...)
2025-06-20 21:49 ` [PATCH 3/5] drm/xe: Move Wa_15015404425 to use the new EX_SOC_WA macro Matt Atwood
@ 2025-06-20 21:49 ` Matt Atwood
2025-06-20 21:49 ` [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0 Matt Atwood
` (4 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Matt Atwood @ 2025-06-20 21:49 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Matt Atwood
Wa_15015404425 needs to be applied to PTL A0 to B0, a subsequent patch
will address the complexity required to do this. For now apply to PTL as
a whole.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/xe/xe_soc_wa_oob.rules | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/xe/xe_soc_wa_oob.rules b/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
index b7d12ea4d65c..3a0c4ccc4224 100644
--- a/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_soc_wa_oob.rules
@@ -1 +1,2 @@
15015404425 PLATFORM(LUNARLAKE)
+ PLATFORM(PANTHERLAKE)
--
2.49.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
` (3 preceding siblings ...)
2025-06-20 21:49 ` [PATCH 4/5] drm/xe: extend Wa_15015404425 to apply to PTL Matt Atwood
@ 2025-06-20 21:49 ` Matt Atwood
2025-06-23 21:12 ` Rodrigo Vivi
2025-06-20 21:55 ` ✗ CI.checkpatch: warning for drm/xe: Create and use SoC WA infrastructure Patchwork
` (3 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Matt Atwood @ 2025-06-20 21:49 UTC (permalink / raw)
To: intel-xe; +Cc: matthew.d.roper, Matt Atwood
This workaround only applies to PTL Compute Die A0. However, this
information cannot be determined until after the GT is brought up. This
means that we will assume that it is required for the initial bring up of
the gt. After GT init, the oob workarounds are enabled for the GT. Use
this flag to then manually set the bit in the soc oob bit field to 0
which will help performance after device bring up.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index ded0f3dc8d73..a624c3fb9498 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -34,6 +34,9 @@
#include "xe_tile.h"
#include "xe_wa.h"
+#include "generated/xe_wa_oob.h"
+#include "generated/xe_soc_wa_oob.h"
+
enum toggle_d3cold {
D3COLD_DISABLE,
D3COLD_ENABLE,
@@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
drm_dbg(&xe->drm, "d3cold: capable=%s\n",
str_yes_no(xe->d3cold.capable));
+ if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
+ xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
+
return 0;
err_driver_cleanup:
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 8c2aa48cb33a..822cbff13819 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -71,3 +71,4 @@ no_media_l3 MEDIA_VERSION(3000)
# primary GT GMDID
14022085890 GRAPHICS_VERSION(2001)
16026007364 MEDIA_VERSION(3000)
+15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
--
2.49.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✗ CI.checkpatch: warning for drm/xe: Create and use SoC WA infrastructure
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
` (4 preceding siblings ...)
2025-06-20 21:49 ` [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0 Matt Atwood
@ 2025-06-20 21:55 ` Patchwork
2025-06-20 21:57 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-06-20 21:55 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Create and use SoC WA infrastructure
URL : https://patchwork.freedesktop.org/series/150584/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8d4ecef8b0011b22fa89bd7c2265bdca5c9a4899
Author: Matt Atwood <matthew.s.atwood@intel.com>
Date: Fri Jun 20 14:49:20 2025 -0700
drm/xe: disable wa_15015404425 for PTL B0
This workaround only applies to PTL Compute Die A0. However, this
information cannot be determined until after the GT is brought up. This
means that we will assume that it is required for the initial bring up of
the gt. After GT init, the oob workarounds are enabled for the GT. Use
this flag to then manually set the bit in the soc oob bit field to 0
which will help performance after device bring up.
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
+ /mt/dim checkpatch 3dde2e2646b2619f765de9c226bfe0dda7bf1f17 drm-intel
76d7be70ef65 drm/xe: add xe_soc_wa infrastructure
-:68: CHECK:BOOL_COMPARISON: Using comparison to false is error prone
#68: FILE: drivers/gpu/drm/xe/xe_gen_wa_oob.c:99:
+ if (soc == false)
-:81: CHECK:BOOL_COMPARISON: Using comparison to false is error prone
#81: FILE: drivers/gpu/drm/xe/xe_gen_wa_oob.c:123:
+ if (soc == false)
-:94: WARNING:LINE_SPACING: Missing a blank line after declarations
#94: FILE: drivers/gpu/drm/xe/xe_gen_wa_oob.c:166:
+ char *soc = strstr(args[ARGS_CHEADER].fn, "soc_");
+ if (soc == NULL)
-:94: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!soc"
#94: FILE: drivers/gpu/drm/xe/xe_gen_wa_oob.c:166:
+ if (soc == NULL)
-:99: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "soc"
#99: FILE: drivers/gpu/drm/xe/xe_gen_wa_oob.c:171:
+ bool prefix = soc != NULL ? true : false;
-:107: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#107:
new file mode 100644
total: 0 errors, 2 warnings, 4 checks, 78 lines checked
1db4d1988d2c drm/xe: Add infrastructure for SoC OOB workarounds
-:8: WARNING:TYPO_SPELLING: 'simlar' may be misspelled - perhaps 'similar'?
#8:
mechanism simlar to the GT related OOB workarounds where we can more
^^^^^^
-:28: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#28: FILE: drivers/gpu/drm/xe/xe_device_types.h:365:
+ * initialization after SOC OOB WAs have been processed */
-:81: WARNING:LONG_LINE: line length of 113 exceeds 100 columns
#81: FILE: drivers/gpu/drm/xe/xe_rtp.h:425:
+ struct xe_gt * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT }, \
-:82: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#82: FILE: drivers/gpu/drm/xe/xe_rtp.h:426:
+ struct xe_device * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_SOC })
-:126: CHECK:SPACING: spaces preferred around that '-' (ctx:WxV)
#126: FILE: drivers/gpu/drm/xe/xe_wa.c:885:
+static_assert(ARRAY_SIZE(soc_oob_was) -1 == _XE_SOC_WA_OOB_COUNT);
^
-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/xe/xe_wa.c:911:
+ p = drmm_kzalloc(&xe->drm,
+ sizeof(xe->oob) * BITS_TO_LONGS(ARRAY_SIZE(soc_oob_was)),
-:220: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'xe__' - possible side-effects?
#220: FILE: drivers/gpu/drm/xe/xe_wa.h:43:
+#define XE_SOC_WA(xe__, id__) ({ \
+ xe_assert(xe__, (xe__)->oob_initialized); \
+ test_bit(XE_SOC_WA_OOB_ ## id__, (xe__)->oob); \
+})
total: 0 errors, 4 warnings, 3 checks, 170 lines checked
ee9ca050d3de drm/xe: Move Wa_15015404425 to use the new EX_SOC_WA macro
9cc636479d1f drm/xe: extend Wa_15015404425 to apply to PTL
8d4ecef8b001 drm/xe: disable wa_15015404425 for PTL B0
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✓ CI.KUnit: success for drm/xe: Create and use SoC WA infrastructure
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
` (5 preceding siblings ...)
2025-06-20 21:55 ` ✗ CI.checkpatch: warning for drm/xe: Create and use SoC WA infrastructure Patchwork
@ 2025-06-20 21:57 ` Patchwork
2025-06-20 22:58 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-06-21 6:05 ` ✗ Xe.CI.Full: " Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-06-20 21:57 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-xe
== Series Details ==
Series: drm/xe: Create and use SoC WA infrastructure
URL : https://patchwork.freedesktop.org/series/150584/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[21:55:54] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:55:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:56:25] Starting KUnit Kernel (1/1)...
[21:56:25] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:56:25] ================== guc_buf (11 subtests) ===================
[21:56:25] [PASSED] test_smallest
[21:56:25] [PASSED] test_largest
[21:56:25] [PASSED] test_granular
[21:56:25] [PASSED] test_unique
[21:56:25] [PASSED] test_overlap
[21:56:25] [PASSED] test_reusable
[21:56:25] [PASSED] test_too_big
[21:56:25] [PASSED] test_flush
[21:56:25] [PASSED] test_lookup
[21:56:25] [PASSED] test_data
[21:56:25] [PASSED] test_class
[21:56:25] ===================== [PASSED] guc_buf =====================
[21:56:25] =================== guc_dbm (7 subtests) ===================
[21:56:25] [PASSED] test_empty
[21:56:25] [PASSED] test_default
[21:56:25] ======================== test_size ========================
[21:56:25] [PASSED] 4
[21:56:25] [PASSED] 8
[21:56:25] [PASSED] 32
[21:56:25] [PASSED] 256
[21:56:25] ==================== [PASSED] test_size ====================
[21:56:25] ======================= test_reuse ========================
[21:56:25] [PASSED] 4
[21:56:25] [PASSED] 8
[21:56:25] [PASSED] 32
[21:56:25] [PASSED] 256
[21:56:25] =================== [PASSED] test_reuse ====================
[21:56:25] =================== test_range_overlap ====================
[21:56:25] [PASSED] 4
[21:56:25] [PASSED] 8
[21:56:25] [PASSED] 32
[21:56:25] [PASSED] 256
[21:56:25] =============== [PASSED] test_range_overlap ================
[21:56:25] =================== test_range_compact ====================
[21:56:25] [PASSED] 4
[21:56:25] [PASSED] 8
[21:56:25] [PASSED] 32
[21:56:25] [PASSED] 256
[21:56:25] =============== [PASSED] test_range_compact ================
[21:56:25] ==================== test_range_spare =====================
[21:56:25] [PASSED] 4
[21:56:25] [PASSED] 8
[21:56:25] [PASSED] 32
[21:56:25] [PASSED] 256
[21:56:25] ================ [PASSED] test_range_spare =================
[21:56:25] ===================== [PASSED] guc_dbm =====================
[21:56:25] =================== guc_idm (6 subtests) ===================
[21:56:25] [PASSED] bad_init
[21:56:25] [PASSED] no_init
[21:56:25] [PASSED] init_fini
[21:56:25] [PASSED] check_used
[21:56:25] [PASSED] check_quota
[21:56:25] [PASSED] check_all
[21:56:25] ===================== [PASSED] guc_idm =====================
[21:56:25] ================== no_relay (3 subtests) ===================
[21:56:25] [PASSED] xe_drops_guc2pf_if_not_ready
[21:56:25] [PASSED] xe_drops_guc2vf_if_not_ready
[21:56:25] [PASSED] xe_rejects_send_if_not_ready
[21:56:25] ==================== [PASSED] no_relay =====================
[21:56:25] ================== pf_relay (14 subtests) ==================
[21:56:25] [PASSED] pf_rejects_guc2pf_too_short
[21:56:25] [PASSED] pf_rejects_guc2pf_too_long
[21:56:25] [PASSED] pf_rejects_guc2pf_no_payload
[21:56:25] [PASSED] pf_fails_no_payload
[21:56:25] [PASSED] pf_fails_bad_origin
[21:56:25] [PASSED] pf_fails_bad_type
[21:56:25] [PASSED] pf_txn_reports_error
[21:56:25] [PASSED] pf_txn_sends_pf2guc
[21:56:25] [PASSED] pf_sends_pf2guc
[21:56:25] [SKIPPED] pf_loopback_nop
[21:56:25] [SKIPPED] pf_loopback_echo
[21:56:25] [SKIPPED] pf_loopback_fail
[21:56:25] [SKIPPED] pf_loopback_busy
[21:56:25] [SKIPPED] pf_loopback_retry
[21:56:25] ==================== [PASSED] pf_relay =====================
[21:56:25] ================== vf_relay (3 subtests) ===================
[21:56:25] [PASSED] vf_rejects_guc2vf_too_short
[21:56:25] [PASSED] vf_rejects_guc2vf_too_long
[21:56:25] [PASSED] vf_rejects_guc2vf_no_payload
[21:56:25] ==================== [PASSED] vf_relay =====================
[21:56:25] ================= pf_service (11 subtests) =================
[21:56:25] [PASSED] pf_negotiate_any
[21:56:25] [PASSED] pf_negotiate_base_match
[21:56:25] [PASSED] pf_negotiate_base_newer
[21:56:25] [PASSED] pf_negotiate_base_next
[21:56:25] [SKIPPED] pf_negotiate_base_older
[21:56:25] [PASSED] pf_negotiate_base_prev
[21:56:25] [PASSED] pf_negotiate_latest_match
[21:56:25] [PASSED] pf_negotiate_latest_newer
[21:56:25] [PASSED] pf_negotiate_latest_next
[21:56:25] [SKIPPED] pf_negotiate_latest_older
[21:56:25] [SKIPPED] pf_negotiate_latest_prev
[21:56:25] =================== [PASSED] pf_service ====================
[21:56:25] ===================== lmtt (1 subtest) =====================
[21:56:25] ======================== test_ops =========================
[21:56:25] [PASSED] 2-level
[21:56:25] [PASSED] multi-level
[21:56:25] ==================== [PASSED] test_ops =====================
[21:56:25] ====================== [PASSED] lmtt =======================
[21:56:25] =================== xe_mocs (2 subtests) ===================
[21:56:25] ================ xe_live_mocs_kernel_kunit ================
[21:56:25] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[21:56:25] ================ xe_live_mocs_reset_kunit =================
[21:56:25] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[21:56:25] ==================== [SKIPPED] xe_mocs =====================
[21:56:25] ================= xe_migrate (2 subtests) ==================
[21:56:25] ================= xe_migrate_sanity_kunit =================
[21:56:25] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[21:56:25] ================== xe_validate_ccs_kunit ==================
[21:56:25] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[21:56:25] =================== [SKIPPED] xe_migrate ===================
[21:56:25] ================== xe_dma_buf (1 subtest) ==================
[21:56:25] ==================== xe_dma_buf_kunit =====================
[21:56:25] ================ [SKIPPED] xe_dma_buf_kunit ================
[21:56:25] =================== [SKIPPED] xe_dma_buf ===================
[21:56:25] ================= xe_bo_shrink (1 subtest) =================
[21:56:25] =================== xe_bo_shrink_kunit ====================
[21:56:25] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[21:56:25] ================== [SKIPPED] xe_bo_shrink ==================
[21:56:25] ==================== xe_bo (2 subtests) ====================
[21:56:25] ================== xe_ccs_migrate_kunit ===================
[21:56:25] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[21:56:25] ==================== xe_bo_evict_kunit ====================
[21:56:25] =============== [SKIPPED] xe_bo_evict_kunit ================
[21:56:25] ===================== [SKIPPED] xe_bo ======================
[21:56:25] ==================== args (11 subtests) ====================
[21:56:25] [PASSED] count_args_test
[21:56:25] [PASSED] call_args_example
[21:56:25] [PASSED] call_args_test
[21:56:25] [PASSED] drop_first_arg_example
[21:56:25] [PASSED] drop_first_arg_test
[21:56:25] [PASSED] first_arg_example
[21:56:25] [PASSED] first_arg_test
[21:56:25] [PASSED] last_arg_example
[21:56:25] [PASSED] last_arg_test
[21:56:25] [PASSED] pick_arg_example
[21:56:25] [PASSED] sep_comma_example
[21:56:25] ====================== [PASSED] args =======================
[21:56:25] =================== xe_pci (2 subtests) ====================
[21:56:25] ==================== check_graphics_ip ====================
[21:56:25] [PASSED] 12.70 Xe_LPG
[21:56:25] [PASSED] 12.71 Xe_LPG
[21:56:25] [PASSED] 12.74 Xe_LPG+
[21:56:25] [PASSED] 20.01 Xe2_HPG
[21:56:25] [PASSED] 20.02 Xe2_HPG
[21:56:25] [PASSED] 20.04 Xe2_LPG
[21:56:25] [PASSED] 30.00 Xe3_LPG
[21:56:25] [PASSED] 30.01 Xe3_LPG
[21:56:25] [PASSED] 30.03 Xe3_LPG
[21:56:25] ================ [PASSED] check_graphics_ip ================
[21:56:25] ===================== check_media_ip ======================
[21:56:25] [PASSED] 13.00 Xe_LPM+
[21:56:25] [PASSED] 13.01 Xe2_HPM
[21:56:25] [PASSED] 20.00 Xe2_LPM
[21:56:25] [PASSED] 30.00 Xe3_LPM
[21:56:25] [PASSED] 30.02 Xe3_LPM
stty: 'standard input': Inappropriate ioctl for device
[21:56:25] ================= [PASSED] check_media_ip ==================
[21:56:25] ===================== [PASSED] xe_pci ======================
[21:56:25] =================== xe_rtp (2 subtests) ====================
[21:56:25] =============== xe_rtp_process_to_sr_tests ================
[21:56:25] [PASSED] coalesce-same-reg
[21:56:25] [PASSED] no-match-no-add
[21:56:25] [PASSED] match-or
[21:56:25] [PASSED] match-or-xfail
[21:56:25] [PASSED] no-match-no-add-multiple-rules
[21:56:25] [PASSED] two-regs-two-entries
[21:56:25] [PASSED] clr-one-set-other
[21:56:25] [PASSED] set-field
[21:56:25] [PASSED] conflict-duplicate
[21:56:25] [PASSED] conflict-not-disjoint
[21:56:25] [PASSED] conflict-reg-type
[21:56:25] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[21:56:25] ================== xe_rtp_process_tests ===================
[21:56:25] [PASSED] active1
[21:56:25] [PASSED] active2
[21:56:25] [PASSED] active-inactive
[21:56:25] [PASSED] inactive-active
[21:56:25] [PASSED] inactive-1st_or_active-inactive
[21:56:25] [PASSED] inactive-2nd_or_active-inactive
[21:56:25] [PASSED] inactive-last_or_active-inactive
[21:56:25] [PASSED] inactive-no_or_active-inactive
[21:56:25] ============== [PASSED] xe_rtp_process_tests ===============
[21:56:25] ===================== [PASSED] xe_rtp ======================
[21:56:25] ==================== xe_wa (1 subtest) =====================
[21:56:25] ======================== xe_wa_gt =========================
[21:56:25] [PASSED] TIGERLAKE (B0)
[21:56:25] [PASSED] DG1 (A0)
[21:56:25] [PASSED] DG1 (B0)
[21:56:25] [PASSED] ALDERLAKE_S (A0)
[21:56:25] [PASSED] ALDERLAKE_S (B0)
[21:56:25] [PASSED] ALDERLAKE_S (C0)
[21:56:25] [PASSED] ALDERLAKE_S (D0)
[21:56:25] [PASSED] ALDERLAKE_P (A0)
[21:56:25] [PASSED] ALDERLAKE_P (B0)
[21:56:25] [PASSED] ALDERLAKE_P (C0)
[21:56:25] [PASSED] ALDERLAKE_S_RPLS (D0)
[21:56:25] [PASSED] ALDERLAKE_P_RPLU (E0)
[21:56:25] [PASSED] DG2_G10 (C0)
[21:56:25] [PASSED] DG2_G11 (B1)
[21:56:25] [PASSED] DG2_G12 (A1)
[21:56:25] [PASSED] METEORLAKE (g:A0, m:A0)
[21:56:25] [PASSED] METEORLAKE (g:A0, m:A0)
[21:56:25] [PASSED] METEORLAKE (g:A0, m:A0)
[21:56:25] [PASSED] LUNARLAKE (g:A0, m:A0)
[21:56:25] [PASSED] LUNARLAKE (g:B0, m:A0)
[21:56:25] [PASSED] BATTLEMAGE (g:A0, m:A1)
[21:56:25] ==================== [PASSED] xe_wa_gt =====================
[21:56:25] ====================== [PASSED] xe_wa ======================
[21:56:25] ============================================================
[21:56:25] Testing complete. Ran 145 tests: passed: 129, skipped: 16
[21:56:25] Elapsed time: 31.164s total, 4.127s configuring, 26.719s building, 0.293s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[21:56:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:56:27] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:56:49] Starting KUnit Kernel (1/1)...
[21:56:49] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:56:49] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[21:56:49] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[21:56:49] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[21:56:49] =========== drm_validate_clone_mode (2 subtests) ===========
[21:56:49] ============== drm_test_check_in_clone_mode ===============
[21:56:49] [PASSED] in_clone_mode
[21:56:49] [PASSED] not_in_clone_mode
[21:56:49] ========== [PASSED] drm_test_check_in_clone_mode ===========
[21:56:49] =============== drm_test_check_valid_clones ===============
[21:56:49] [PASSED] not_in_clone_mode
[21:56:49] [PASSED] valid_clone
[21:56:49] [PASSED] invalid_clone
[21:56:49] =========== [PASSED] drm_test_check_valid_clones ===========
[21:56:49] ============= [PASSED] drm_validate_clone_mode =============
[21:56:49] ============= drm_validate_modeset (1 subtest) =============
[21:56:49] [PASSED] drm_test_check_connector_changed_modeset
[21:56:49] ============== [PASSED] drm_validate_modeset ===============
[21:56:49] ====== drm_test_bridge_get_current_state (2 subtests) ======
[21:56:49] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[21:56:49] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[21:56:49] ======== [PASSED] drm_test_bridge_get_current_state ========
[21:56:49] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[21:56:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[21:56:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[21:56:49] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[21:56:49] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[21:56:49] ============== drm_bridge_alloc (2 subtests) ===============
[21:56:49] [PASSED] drm_test_drm_bridge_alloc_basic
[21:56:49] [PASSED] drm_test_drm_bridge_alloc_get_put
[21:56:49] ================ [PASSED] drm_bridge_alloc =================
[21:56:49] ================== drm_buddy (7 subtests) ==================
[21:56:49] [PASSED] drm_test_buddy_alloc_limit
[21:56:49] [PASSED] drm_test_buddy_alloc_optimistic
[21:56:49] [PASSED] drm_test_buddy_alloc_pessimistic
[21:56:49] [PASSED] drm_test_buddy_alloc_pathological
[21:56:49] [PASSED] drm_test_buddy_alloc_contiguous
[21:56:49] [PASSED] drm_test_buddy_alloc_clear
[21:56:49] [PASSED] drm_test_buddy_alloc_range_bias
[21:56:49] ==================== [PASSED] drm_buddy ====================
[21:56:49] ============= drm_cmdline_parser (40 subtests) =============
[21:56:49] [PASSED] drm_test_cmdline_force_d_only
[21:56:49] [PASSED] drm_test_cmdline_force_D_only_dvi
[21:56:49] [PASSED] drm_test_cmdline_force_D_only_hdmi
[21:56:49] [PASSED] drm_test_cmdline_force_D_only_not_digital
[21:56:49] [PASSED] drm_test_cmdline_force_e_only
[21:56:49] [PASSED] drm_test_cmdline_res
[21:56:49] [PASSED] drm_test_cmdline_res_vesa
[21:56:49] [PASSED] drm_test_cmdline_res_vesa_rblank
[21:56:49] [PASSED] drm_test_cmdline_res_rblank
[21:56:49] [PASSED] drm_test_cmdline_res_bpp
[21:56:49] [PASSED] drm_test_cmdline_res_refresh
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[21:56:49] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[21:56:49] [PASSED] drm_test_cmdline_res_margins_force_on
[21:56:49] [PASSED] drm_test_cmdline_res_vesa_margins
[21:56:49] [PASSED] drm_test_cmdline_name
[21:56:49] [PASSED] drm_test_cmdline_name_bpp
[21:56:49] [PASSED] drm_test_cmdline_name_option
[21:56:49] [PASSED] drm_test_cmdline_name_bpp_option
[21:56:49] [PASSED] drm_test_cmdline_rotate_0
[21:56:49] [PASSED] drm_test_cmdline_rotate_90
[21:56:49] [PASSED] drm_test_cmdline_rotate_180
[21:56:49] [PASSED] drm_test_cmdline_rotate_270
[21:56:49] [PASSED] drm_test_cmdline_hmirror
[21:56:49] [PASSED] drm_test_cmdline_vmirror
[21:56:49] [PASSED] drm_test_cmdline_margin_options
[21:56:49] [PASSED] drm_test_cmdline_multiple_options
[21:56:49] [PASSED] drm_test_cmdline_bpp_extra_and_option
[21:56:49] [PASSED] drm_test_cmdline_extra_and_option
[21:56:49] [PASSED] drm_test_cmdline_freestanding_options
[21:56:49] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[21:56:49] [PASSED] drm_test_cmdline_panel_orientation
[21:56:49] ================ drm_test_cmdline_invalid =================
[21:56:49] [PASSED] margin_only
[21:56:49] [PASSED] interlace_only
[21:56:49] [PASSED] res_missing_x
[21:56:49] [PASSED] res_missing_y
[21:56:49] [PASSED] res_bad_y
[21:56:49] [PASSED] res_missing_y_bpp
[21:56:49] [PASSED] res_bad_bpp
[21:56:49] [PASSED] res_bad_refresh
[21:56:49] [PASSED] res_bpp_refresh_force_on_off
[21:56:49] [PASSED] res_invalid_mode
[21:56:49] [PASSED] res_bpp_wrong_place_mode
[21:56:49] [PASSED] name_bpp_refresh
[21:56:49] [PASSED] name_refresh
[21:56:49] [PASSED] name_refresh_wrong_mode
[21:56:49] [PASSED] name_refresh_invalid_mode
[21:56:49] [PASSED] rotate_multiple
[21:56:49] [PASSED] rotate_invalid_val
[21:56:49] [PASSED] rotate_truncated
[21:56:49] [PASSED] invalid_option
[21:56:49] [PASSED] invalid_tv_option
[21:56:49] [PASSED] truncated_tv_option
[21:56:49] ============ [PASSED] drm_test_cmdline_invalid =============
[21:56:49] =============== drm_test_cmdline_tv_options ===============
[21:56:49] [PASSED] NTSC
[21:56:49] [PASSED] NTSC_443
[21:56:49] [PASSED] NTSC_J
[21:56:49] [PASSED] PAL
[21:56:49] [PASSED] PAL_M
[21:56:49] [PASSED] PAL_N
[21:56:49] [PASSED] SECAM
[21:56:49] [PASSED] MONO_525
[21:56:49] [PASSED] MONO_625
[21:56:49] =========== [PASSED] drm_test_cmdline_tv_options ===========
[21:56:49] =============== [PASSED] drm_cmdline_parser ================
[21:56:49] ========== drmm_connector_hdmi_init (20 subtests) ==========
[21:56:49] [PASSED] drm_test_connector_hdmi_init_valid
[21:56:49] [PASSED] drm_test_connector_hdmi_init_bpc_8
[21:56:49] [PASSED] drm_test_connector_hdmi_init_bpc_10
[21:56:49] [PASSED] drm_test_connector_hdmi_init_bpc_12
[21:56:49] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[21:56:49] [PASSED] drm_test_connector_hdmi_init_bpc_null
[21:56:49] [PASSED] drm_test_connector_hdmi_init_formats_empty
[21:56:49] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[21:56:49] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:56:49] [PASSED] supported_formats=0x9 yuv420_allowed=1
[21:56:49] [PASSED] supported_formats=0x9 yuv420_allowed=0
[21:56:49] [PASSED] supported_formats=0x3 yuv420_allowed=1
[21:56:49] [PASSED] supported_formats=0x3 yuv420_allowed=0
[21:56:49] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[21:56:49] [PASSED] drm_test_connector_hdmi_init_null_ddc
[21:56:49] [PASSED] drm_test_connector_hdmi_init_null_product
[21:56:49] [PASSED] drm_test_connector_hdmi_init_null_vendor
[21:56:49] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[21:56:49] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[21:56:49] [PASSED] drm_test_connector_hdmi_init_product_valid
[21:56:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[21:56:49] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[21:56:49] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[21:56:49] ========= drm_test_connector_hdmi_init_type_valid =========
[21:56:49] [PASSED] HDMI-A
[21:56:49] [PASSED] HDMI-B
[21:56:49] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[21:56:49] ======== drm_test_connector_hdmi_init_type_invalid ========
[21:56:49] [PASSED] Unknown
[21:56:49] [PASSED] VGA
[21:56:49] [PASSED] DVI-I
[21:56:49] [PASSED] DVI-D
[21:56:49] [PASSED] DVI-A
[21:56:49] [PASSED] Composite
[21:56:49] [PASSED] SVIDEO
[21:56:49] [PASSED] LVDS
[21:56:49] [PASSED] Component
[21:56:49] [PASSED] DIN
[21:56:49] [PASSED] DP
[21:56:49] [PASSED] TV
[21:56:49] [PASSED] eDP
[21:56:49] [PASSED] Virtual
[21:56:49] [PASSED] DSI
[21:56:49] [PASSED] DPI
[21:56:49] [PASSED] Writeback
[21:56:49] [PASSED] SPI
[21:56:49] [PASSED] USB
[21:56:49] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[21:56:49] ============ [PASSED] drmm_connector_hdmi_init =============
[21:56:49] ============= drmm_connector_init (3 subtests) =============
[21:56:49] [PASSED] drm_test_drmm_connector_init
[21:56:49] [PASSED] drm_test_drmm_connector_init_null_ddc
[21:56:49] ========= drm_test_drmm_connector_init_type_valid =========
[21:56:49] [PASSED] Unknown
[21:56:49] [PASSED] VGA
[21:56:49] [PASSED] DVI-I
[21:56:49] [PASSED] DVI-D
[21:56:49] [PASSED] DVI-A
[21:56:49] [PASSED] Composite
[21:56:49] [PASSED] SVIDEO
[21:56:49] [PASSED] LVDS
[21:56:49] [PASSED] Component
[21:56:49] [PASSED] DIN
[21:56:49] [PASSED] DP
[21:56:49] [PASSED] HDMI-A
[21:56:49] [PASSED] HDMI-B
[21:56:49] [PASSED] TV
[21:56:49] [PASSED] eDP
[21:56:49] [PASSED] Virtual
[21:56:49] [PASSED] DSI
[21:56:49] [PASSED] DPI
[21:56:49] [PASSED] Writeback
[21:56:49] [PASSED] SPI
[21:56:49] [PASSED] USB
[21:56:49] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[21:56:49] =============== [PASSED] drmm_connector_init ===============
[21:56:49] ========= drm_connector_dynamic_init (6 subtests) ==========
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_init
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_init_properties
[21:56:49] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[21:56:49] [PASSED] Unknown
[21:56:49] [PASSED] VGA
[21:56:49] [PASSED] DVI-I
[21:56:49] [PASSED] DVI-D
[21:56:49] [PASSED] DVI-A
[21:56:49] [PASSED] Composite
[21:56:49] [PASSED] SVIDEO
[21:56:49] [PASSED] LVDS
[21:56:49] [PASSED] Component
[21:56:49] [PASSED] DIN
[21:56:49] [PASSED] DP
[21:56:49] [PASSED] HDMI-A
[21:56:49] [PASSED] HDMI-B
[21:56:49] [PASSED] TV
[21:56:49] [PASSED] eDP
[21:56:49] [PASSED] Virtual
[21:56:49] [PASSED] DSI
[21:56:49] [PASSED] DPI
[21:56:49] [PASSED] Writeback
[21:56:49] [PASSED] SPI
[21:56:49] [PASSED] USB
[21:56:49] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[21:56:49] ======== drm_test_drm_connector_dynamic_init_name =========
[21:56:49] [PASSED] Unknown
[21:56:49] [PASSED] VGA
[21:56:49] [PASSED] DVI-I
[21:56:49] [PASSED] DVI-D
[21:56:49] [PASSED] DVI-A
[21:56:49] [PASSED] Composite
[21:56:49] [PASSED] SVIDEO
[21:56:49] [PASSED] LVDS
[21:56:49] [PASSED] Component
[21:56:49] [PASSED] DIN
[21:56:49] [PASSED] DP
[21:56:49] [PASSED] HDMI-A
[21:56:49] [PASSED] HDMI-B
[21:56:49] [PASSED] TV
[21:56:49] [PASSED] eDP
[21:56:49] [PASSED] Virtual
[21:56:49] [PASSED] DSI
[21:56:49] [PASSED] DPI
[21:56:49] [PASSED] Writeback
[21:56:49] [PASSED] SPI
[21:56:49] [PASSED] USB
[21:56:49] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[21:56:49] =========== [PASSED] drm_connector_dynamic_init ============
[21:56:49] ==== drm_connector_dynamic_register_early (4 subtests) =====
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[21:56:49] ====== [PASSED] drm_connector_dynamic_register_early =======
[21:56:49] ======= drm_connector_dynamic_register (7 subtests) ========
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[21:56:49] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[21:56:49] ========= [PASSED] drm_connector_dynamic_register ==========
[21:56:49] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[21:56:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[21:56:49] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[21:56:49] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[21:56:49] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[21:56:49] ========== drm_test_get_tv_mode_from_name_valid ===========
[21:56:49] [PASSED] NTSC
[21:56:49] [PASSED] NTSC-443
[21:56:49] [PASSED] NTSC-J
[21:56:49] [PASSED] PAL
[21:56:49] [PASSED] PAL-M
[21:56:49] [PASSED] PAL-N
[21:56:49] [PASSED] SECAM
[21:56:49] [PASSED] Mono
[21:56:49] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[21:56:49] [PASSED] drm_test_get_tv_mode_from_name_truncated
[21:56:49] ============ [PASSED] drm_get_tv_mode_from_name ============
[21:56:49] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[21:56:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[21:56:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[21:56:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[21:56:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[21:56:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[21:56:49] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[21:56:49] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[21:56:49] [PASSED] VIC 96
[21:56:49] [PASSED] VIC 97
[21:56:49] [PASSED] VIC 101
[21:56:49] [PASSED] VIC 102
[21:56:49] [PASSED] VIC 106
[21:56:49] [PASSED] VIC 107
[21:56:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[21:56:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[21:56:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[21:56:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[21:56:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[21:56:49] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[21:56:49] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[21:56:49] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[21:56:49] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[21:56:49] [PASSED] Automatic
[21:56:49] [PASSED] Full
[21:56:49] [PASSED] Limited 16:235
[21:56:49] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[21:56:49] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[21:56:49] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[21:56:49] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[21:56:49] === drm_test_drm_hdmi_connector_get_output_format_name ====
[21:56:49] [PASSED] RGB
[21:56:49] [PASSED] YUV 4:2:0
[21:56:49] [PASSED] YUV 4:2:2
[21:56:49] [PASSED] YUV 4:4:4
[21:56:49] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[21:56:49] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[21:56:49] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[21:56:49] ============= drm_damage_helper (21 subtests) ==============
[21:56:49] [PASSED] drm_test_damage_iter_no_damage
[21:56:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[21:56:49] [PASSED] drm_test_damage_iter_no_damage_src_moved
[21:56:49] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[21:56:49] [PASSED] drm_test_damage_iter_no_damage_not_visible
[21:56:49] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[21:56:49] [PASSED] drm_test_damage_iter_no_damage_no_fb
[21:56:49] [PASSED] drm_test_damage_iter_simple_damage
[21:56:49] [PASSED] drm_test_damage_iter_single_damage
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_outside_src
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_src_moved
[21:56:49] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[21:56:49] [PASSED] drm_test_damage_iter_damage
[21:56:49] [PASSED] drm_test_damage_iter_damage_one_intersect
[21:56:49] [PASSED] drm_test_damage_iter_damage_one_outside
[21:56:49] [PASSED] drm_test_damage_iter_damage_src_moved
[21:56:49] [PASSED] drm_test_damage_iter_damage_not_visible
[21:56:49] ================ [PASSED] drm_damage_helper ================
[21:56:49] ============== drm_dp_mst_helper (3 subtests) ==============
[21:56:49] ============== drm_test_dp_mst_calc_pbn_mode ==============
[21:56:49] [PASSED] Clock 154000 BPP 30 DSC disabled
[21:56:49] [PASSED] Clock 234000 BPP 30 DSC disabled
[21:56:49] [PASSED] Clock 297000 BPP 24 DSC disabled
[21:56:49] [PASSED] Clock 332880 BPP 24 DSC enabled
[21:56:49] [PASSED] Clock 324540 BPP 24 DSC enabled
[21:56:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[21:56:49] ============== drm_test_dp_mst_calc_pbn_div ===============
[21:56:49] [PASSED] Link rate 2000000 lane count 4
[21:56:49] [PASSED] Link rate 2000000 lane count 2
[21:56:49] [PASSED] Link rate 2000000 lane count 1
[21:56:49] [PASSED] Link rate 1350000 lane count 4
[21:56:49] [PASSED] Link rate 1350000 lane count 2
[21:56:49] [PASSED] Link rate 1350000 lane count 1
[21:56:49] [PASSED] Link rate 1000000 lane count 4
[21:56:49] [PASSED] Link rate 1000000 lane count 2
[21:56:49] [PASSED] Link rate 1000000 lane count 1
[21:56:49] [PASSED] Link rate 810000 lane count 4
[21:56:49] [PASSED] Link rate 810000 lane count 2
[21:56:49] [PASSED] Link rate 810000 lane count 1
[21:56:49] [PASSED] Link rate 540000 lane count 4
[21:56:49] [PASSED] Link rate 540000 lane count 2
[21:56:49] [PASSED] Link rate 540000 lane count 1
[21:56:49] [PASSED] Link rate 270000 lane count 4
[21:56:49] [PASSED] Link rate 270000 lane count 2
[21:56:49] [PASSED] Link rate 270000 lane count 1
[21:56:49] [PASSED] Link rate 162000 lane count 4
[21:56:49] [PASSED] Link rate 162000 lane count 2
[21:56:49] [PASSED] Link rate 162000 lane count 1
[21:56:49] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[21:56:49] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[21:56:49] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[21:56:49] [PASSED] DP_POWER_UP_PHY with port number
[21:56:49] [PASSED] DP_POWER_DOWN_PHY with port number
[21:56:49] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[21:56:49] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[21:56:49] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[21:56:49] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[21:56:49] [PASSED] DP_QUERY_PAYLOAD with port number
[21:56:49] [PASSED] DP_QUERY_PAYLOAD with VCPI
[21:56:49] [PASSED] DP_REMOTE_DPCD_READ with port number
[21:56:49] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[21:56:49] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[21:56:49] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[21:56:49] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[21:56:49] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[21:56:49] [PASSED] DP_REMOTE_I2C_READ with port number
[21:56:49] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[21:56:49] [PASSED] DP_REMOTE_I2C_READ with transactions array
[21:56:49] [PASSED] DP_REMOTE_I2C_WRITE with port number
[21:56:49] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[21:56:49] [PASSED] DP_REMOTE_I2C_WRITE with data array
[21:56:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[21:56:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[21:56:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[21:56:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[21:56:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[21:56:49] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[21:56:49] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[21:56:49] ================ [PASSED] drm_dp_mst_helper ================
[21:56:49] ================== drm_exec (7 subtests) ===================
[21:56:49] [PASSED] sanitycheck
[21:56:49] [PASSED] test_lock
[21:56:49] [PASSED] test_lock_unlock
[21:56:49] [PASSED] test_duplicates
[21:56:49] [PASSED] test_prepare
[21:56:49] [PASSED] test_prepare_array
[21:56:49] [PASSED] test_multiple_loops
[21:56:49] ==================== [PASSED] drm_exec =====================
[21:56:49] =========== drm_format_helper_test (17 subtests) ===========
[21:56:49] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[21:56:49] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[21:56:49] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[21:56:49] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[21:56:49] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[21:56:49] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[21:56:49] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[21:56:49] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[21:56:49] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[21:56:49] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[21:56:49] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[21:56:49] ============== drm_test_fb_xrgb8888_to_mono ===============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[21:56:49] ==================== drm_test_fb_swab =====================
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ================ [PASSED] drm_test_fb_swab =================
[21:56:49] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[21:56:49] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[21:56:49] [PASSED] single_pixel_source_buffer
[21:56:49] [PASSED] single_pixel_clip_rectangle
[21:56:49] [PASSED] well_known_colors
[21:56:49] [PASSED] destination_pitch
[21:56:49] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[21:56:49] ================= drm_test_fb_clip_offset =================
[21:56:49] [PASSED] pass through
[21:56:49] [PASSED] horizontal offset
[21:56:49] [PASSED] vertical offset
[21:56:49] [PASSED] horizontal and vertical offset
[21:56:49] [PASSED] horizontal offset (custom pitch)
[21:56:49] [PASSED] vertical offset (custom pitch)
[21:56:49] [PASSED] horizontal and vertical offset (custom pitch)
[21:56:49] ============= [PASSED] drm_test_fb_clip_offset =============
[21:56:49] =================== drm_test_fb_memcpy ====================
[21:56:49] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[21:56:49] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[21:56:49] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[21:56:49] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[21:56:49] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[21:56:49] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[21:56:49] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[21:56:49] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[21:56:49] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[21:56:49] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[21:56:49] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[21:56:49] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[21:56:49] =============== [PASSED] drm_test_fb_memcpy ================
[21:56:49] ============= [PASSED] drm_format_helper_test ==============
[21:56:49] ================= drm_format (18 subtests) =================
[21:56:49] [PASSED] drm_test_format_block_width_invalid
[21:56:49] [PASSED] drm_test_format_block_width_one_plane
[21:56:49] [PASSED] drm_test_format_block_width_two_plane
[21:56:49] [PASSED] drm_test_format_block_width_three_plane
[21:56:49] [PASSED] drm_test_format_block_width_tiled
[21:56:49] [PASSED] drm_test_format_block_height_invalid
[21:56:49] [PASSED] drm_test_format_block_height_one_plane
[21:56:49] [PASSED] drm_test_format_block_height_two_plane
[21:56:49] [PASSED] drm_test_format_block_height_three_plane
[21:56:49] [PASSED] drm_test_format_block_height_tiled
[21:56:49] [PASSED] drm_test_format_min_pitch_invalid
[21:56:49] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[21:56:49] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[21:56:49] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[21:56:49] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[21:56:49] [PASSED] drm_test_format_min_pitch_two_plane
[21:56:49] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[21:56:49] [PASSED] drm_test_format_min_pitch_tiled
[21:56:49] =================== [PASSED] drm_format ====================
[21:56:49] ============== drm_framebuffer (10 subtests) ===============
[21:56:49] ========== drm_test_framebuffer_check_src_coords ==========
[21:56:49] [PASSED] Success: source fits into fb
[21:56:49] [PASSED] Fail: overflowing fb with x-axis coordinate
[21:56:49] [PASSED] Fail: overflowing fb with y-axis coordinate
[21:56:49] [PASSED] Fail: overflowing fb with source width
[21:56:49] [PASSED] Fail: overflowing fb with source height
[21:56:49] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[21:56:49] [PASSED] drm_test_framebuffer_cleanup
[21:56:49] =============== drm_test_framebuffer_create ===============
[21:56:49] [PASSED] ABGR8888 normal sizes
[21:56:49] [PASSED] ABGR8888 max sizes
[21:56:49] [PASSED] ABGR8888 pitch greater than min required
[21:56:49] [PASSED] ABGR8888 pitch less than min required
[21:56:49] [PASSED] ABGR8888 Invalid width
[21:56:49] [PASSED] ABGR8888 Invalid buffer handle
[21:56:49] [PASSED] No pixel format
[21:56:49] [PASSED] ABGR8888 Width 0
[21:56:49] [PASSED] ABGR8888 Height 0
[21:56:49] [PASSED] ABGR8888 Out of bound height * pitch combination
[21:56:49] [PASSED] ABGR8888 Large buffer offset
[21:56:49] [PASSED] ABGR8888 Buffer offset for inexistent plane
[21:56:49] [PASSED] ABGR8888 Invalid flag
[21:56:49] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[21:56:49] [PASSED] ABGR8888 Valid buffer modifier
[21:56:49] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[21:56:49] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] NV12 Normal sizes
[21:56:49] [PASSED] NV12 Max sizes
[21:56:49] [PASSED] NV12 Invalid pitch
[21:56:49] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[21:56:49] [PASSED] NV12 different modifier per-plane
[21:56:49] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[21:56:49] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] NV12 Modifier for inexistent plane
[21:56:49] [PASSED] NV12 Handle for inexistent plane
[21:56:49] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[21:56:49] [PASSED] YVU420 Normal sizes
[21:56:49] [PASSED] YVU420 Max sizes
[21:56:49] [PASSED] YVU420 Invalid pitch
[21:56:49] [PASSED] YVU420 Different pitches
[21:56:49] [PASSED] YVU420 Different buffer offsets/pitches
[21:56:49] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[21:56:49] [PASSED] YVU420 Valid modifier
[21:56:49] [PASSED] YVU420 Different modifiers per plane
[21:56:49] [PASSED] YVU420 Modifier for inexistent plane
[21:56:49] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[21:56:49] [PASSED] X0L2 Normal sizes
[21:56:49] [PASSED] X0L2 Max sizes
[21:56:49] [PASSED] X0L2 Invalid pitch
[21:56:49] [PASSED] X0L2 Pitch greater than minimum required
[21:56:49] [PASSED] X0L2 Handle for inexistent plane
[21:56:49] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[21:56:49] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[21:56:49] [PASSED] X0L2 Valid modifier
[21:56:49] [PASSED] X0L2 Modifier for inexistent plane
[21:56:49] =========== [PASSED] drm_test_framebuffer_create ===========
[21:56:49] [PASSED] drm_test_framebuffer_free
[21:56:49] [PASSED] drm_test_framebuffer_init
[21:56:49] [PASSED] drm_test_framebuffer_init_bad_format
[21:56:49] [PASSED] drm_test_framebuffer_init_dev_mismatch
[21:56:49] [PASSED] drm_test_framebuffer_lookup
[21:56:49] [PASSED] drm_test_framebuffer_lookup_inexistent
[21:56:49] [PASSED] drm_test_framebuffer_modifiers_not_supported
[21:56:49] ================= [PASSED] drm_framebuffer =================
[21:56:49] ================ drm_gem_shmem (8 subtests) ================
[21:56:49] [PASSED] drm_gem_shmem_test_obj_create
[21:56:49] [PASSED] drm_gem_shmem_test_obj_create_private
[21:56:49] [PASSED] drm_gem_shmem_test_pin_pages
[21:56:49] [PASSED] drm_gem_shmem_test_vmap
[21:56:49] [PASSED] drm_gem_shmem_test_get_pages_sgt
[21:56:49] [PASSED] drm_gem_shmem_test_get_sg_table
[21:56:49] [PASSED] drm_gem_shmem_test_madvise
[21:56:49] [PASSED] drm_gem_shmem_test_purge
[21:56:49] ================== [PASSED] drm_gem_shmem ==================
[21:56:49] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[21:56:49] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[21:56:49] [PASSED] Automatic
[21:56:49] [PASSED] Full
[21:56:49] [PASSED] Limited 16:235
[21:56:49] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[21:56:49] [PASSED] drm_test_check_disable_connector
[21:56:49] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[21:56:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[21:56:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[21:56:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[21:56:49] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[21:56:49] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[21:56:49] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[21:56:49] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[21:56:49] [PASSED] drm_test_check_output_bpc_dvi
[21:56:49] [PASSED] drm_test_check_output_bpc_format_vic_1
[21:56:49] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[21:56:49] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[21:56:49] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[21:56:49] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[21:56:49] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[21:56:49] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[21:56:49] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[21:56:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[21:56:49] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[21:56:49] [PASSED] drm_test_check_broadcast_rgb_value
[21:56:49] [PASSED] drm_test_check_bpc_8_value
[21:56:49] [PASSED] drm_test_check_bpc_10_value
[21:56:49] [PASSED] drm_test_check_bpc_12_value
[21:56:49] [PASSED] drm_test_check_format_value
[21:56:49] [PASSED] drm_test_check_tmds_char_value
[21:56:49] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[21:56:49] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[21:56:49] [PASSED] drm_test_check_mode_valid
[21:56:49] [PASSED] drm_test_check_mode_valid_reject
[21:56:49] [PASSED] drm_test_check_mode_valid_reject_rate
[21:56:49] [PASSED] drm_test_check_mode_valid_reject_max_clock
[21:56:49] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[21:56:49] ================= drm_managed (2 subtests) =================
[21:56:49] [PASSED] drm_test_managed_release_action
[21:56:49] [PASSED] drm_test_managed_run_action
[21:56:49] =================== [PASSED] drm_managed ===================
[21:56:49] =================== drm_mm (6 subtests) ====================
[21:56:49] [PASSED] drm_test_mm_init
[21:56:49] [PASSED] drm_test_mm_debug
[21:56:49] [PASSED] drm_test_mm_align32
[21:56:49] [PASSED] drm_test_mm_align64
[21:56:49] [PASSED] drm_test_mm_lowest
[21:56:49] [PASSED] drm_test_mm_highest
[21:56:49] ===================== [PASSED] drm_mm ======================
[21:56:49] ============= drm_modes_analog_tv (5 subtests) =============
[21:56:49] [PASSED] drm_test_modes_analog_tv_mono_576i
[21:56:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[21:56:49] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[21:56:49] [PASSED] drm_test_modes_analog_tv_pal_576i
[21:56:49] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[21:56:49] =============== [PASSED] drm_modes_analog_tv ===============
[21:56:49] ============== drm_plane_helper (2 subtests) ===============
[21:56:49] =============== drm_test_check_plane_state ================
[21:56:49] [PASSED] clipping_simple
[21:56:49] [PASSED] clipping_rotate_reflect
[21:56:49] [PASSED] positioning_simple
[21:56:49] [PASSED] upscaling
[21:56:49] [PASSED] downscaling
[21:56:49] [PASSED] rounding1
[21:56:49] [PASSED] rounding2
[21:56:49] [PASSED] rounding3
[21:56:49] [PASSED] rounding4
[21:56:49] =========== [PASSED] drm_test_check_plane_state ============
[21:56:49] =========== drm_test_check_invalid_plane_state ============
[21:56:49] [PASSED] positioning_invalid
[21:56:49] [PASSED] upscaling_invalid
[21:56:49] [PASSED] downscaling_invalid
[21:56:49] ======= [PASSED] drm_test_check_invalid_plane_state ========
[21:56:49] ================ [PASSED] drm_plane_helper =================
[21:56:49] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[21:56:49] ====== drm_test_connector_helper_tv_get_modes_check =======
[21:56:49] [PASSED] None
[21:56:49] [PASSED] PAL
[21:56:49] [PASSED] NTSC
[21:56:49] [PASSED] Both, NTSC Default
[21:56:49] [PASSED] Both, PAL Default
[21:56:49] [PASSED] Both, NTSC Default, with PAL on command-line
[21:56:49] [PASSED] Both, PAL Default, with NTSC on command-line
[21:56:49] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[21:56:49] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[21:56:49] ================== drm_rect (9 subtests) ===================
[21:56:49] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[21:56:49] [PASSED] drm_test_rect_clip_scaled_not_clipped
[21:56:49] [PASSED] drm_test_rect_clip_scaled_clipped
[21:56:49] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[21:56:49] ================= drm_test_rect_intersect =================
[21:56:49] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[21:56:49] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[21:56:49] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[21:56:49] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[21:56:49] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[21:56:49] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[21:56:49] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[21:56:49] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[21:56:49] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[21:56:49] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[21:56:49] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[21:56:49] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[21:56:49] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[21:56:49] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[21:56:49] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[21:56:49] ============= [PASSED] drm_test_rect_intersect =============
[21:56:49] ================ drm_test_rect_calc_hscale ================
[21:56:49] [PASSED] normal use
[21:56:49] [PASSED] out of max range
[21:56:49] [PASSED] out of min range
[21:56:49] [PASSED] zero dst
[21:56:49] [PASSED] negative src
[21:56:49] [PASSED] negative dst
[21:56:49] ============ [PASSED] drm_test_rect_calc_hscale ============
[21:56:49] ================ drm_test_rect_calc_vscale ================
[21:56:49] [PASSED] normal use
[21:56:49] [PASSED] out of max range
[21:56:49] [PASSED] out of min range
[21:56:49] [PASSED] zero dst
[21:56:49] [PASSED] negative src
[21:56:49] [PASSED] negative dst
[21:56:49] ============ [PASSED] drm_test_rect_calc_vscale ============
[21:56:49] ================== drm_test_rect_rotate ===================
[21:56:49] [PASSED] reflect-x
[21:56:49] [PASSED] reflect-y
[21:56:49] [PASSED] rotate-0
[21:56:49] [PASSED] rotate-90
[21:56:49] [PASSED] rotate-180
[21:56:49] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[21:56:49] ============== [PASSED] drm_test_rect_rotate ===============
[21:56:49] ================ drm_test_rect_rotate_inv =================
[21:56:49] [PASSED] reflect-x
[21:56:49] [PASSED] reflect-y
[21:56:49] [PASSED] rotate-0
[21:56:49] [PASSED] rotate-90
[21:56:49] [PASSED] rotate-180
[21:56:49] [PASSED] rotate-270
[21:56:49] ============ [PASSED] drm_test_rect_rotate_inv =============
[21:56:49] ==================== [PASSED] drm_rect =====================
[21:56:49] ============ drm_sysfb_modeset_test (1 subtest) ============
[21:56:49] ============ drm_test_sysfb_build_fourcc_list =============
[21:56:49] [PASSED] no native formats
[21:56:49] [PASSED] XRGB8888 as native format
[21:56:49] [PASSED] remove duplicates
[21:56:49] [PASSED] convert alpha formats
[21:56:49] [PASSED] random formats
[21:56:49] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[21:56:49] ============= [PASSED] drm_sysfb_modeset_test ==============
[21:56:49] ============================================================
[21:56:49] Testing complete. Ran 616 tests: passed: 616
[21:56:49] Elapsed time: 23.518s total, 1.668s configuring, 21.680s building, 0.140s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[21:56:49] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[21:56:51] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[21:56:58] Starting KUnit Kernel (1/1)...
[21:56:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[21:56:58] ================= ttm_device (5 subtests) ==================
[21:56:58] [PASSED] ttm_device_init_basic
[21:56:58] [PASSED] ttm_device_init_multiple
[21:56:58] [PASSED] ttm_device_fini_basic
[21:56:58] [PASSED] ttm_device_init_no_vma_man
[21:56:58] ================== ttm_device_init_pools ==================
[21:56:58] [PASSED] No DMA allocations, no DMA32 required
[21:56:58] [PASSED] DMA allocations, DMA32 required
[21:56:58] [PASSED] No DMA allocations, DMA32 required
[21:56:58] [PASSED] DMA allocations, no DMA32 required
[21:56:58] ============== [PASSED] ttm_device_init_pools ==============
[21:56:58] =================== [PASSED] ttm_device ====================
[21:56:58] ================== ttm_pool (8 subtests) ===================
[21:56:58] ================== ttm_pool_alloc_basic ===================
[21:56:58] [PASSED] One page
[21:56:58] [PASSED] More than one page
[21:56:58] [PASSED] Above the allocation limit
[21:56:58] [PASSED] One page, with coherent DMA mappings enabled
[21:56:58] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:56:58] ============== [PASSED] ttm_pool_alloc_basic ===============
[21:56:58] ============== ttm_pool_alloc_basic_dma_addr ==============
[21:56:58] [PASSED] One page
[21:56:58] [PASSED] More than one page
[21:56:58] [PASSED] Above the allocation limit
[21:56:58] [PASSED] One page, with coherent DMA mappings enabled
[21:56:58] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[21:56:58] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[21:56:58] [PASSED] ttm_pool_alloc_order_caching_match
[21:56:58] [PASSED] ttm_pool_alloc_caching_mismatch
[21:56:58] [PASSED] ttm_pool_alloc_order_mismatch
[21:56:58] [PASSED] ttm_pool_free_dma_alloc
[21:56:58] [PASSED] ttm_pool_free_no_dma_alloc
[21:56:58] [PASSED] ttm_pool_fini_basic
[21:56:58] ==================== [PASSED] ttm_pool =====================
[21:56:58] ================ ttm_resource (8 subtests) =================
[21:56:58] ================= ttm_resource_init_basic =================
[21:56:58] [PASSED] Init resource in TTM_PL_SYSTEM
[21:56:58] [PASSED] Init resource in TTM_PL_VRAM
[21:56:58] [PASSED] Init resource in a private placement
[21:56:58] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[21:56:58] ============= [PASSED] ttm_resource_init_basic =============
[21:56:58] [PASSED] ttm_resource_init_pinned
[21:56:58] [PASSED] ttm_resource_fini_basic
[21:56:58] [PASSED] ttm_resource_manager_init_basic
[21:56:58] [PASSED] ttm_resource_manager_usage_basic
[21:56:58] [PASSED] ttm_resource_manager_set_used_basic
[21:56:58] [PASSED] ttm_sys_man_alloc_basic
[21:56:58] [PASSED] ttm_sys_man_free_basic
[21:56:58] ================== [PASSED] ttm_resource ===================
[21:56:58] =================== ttm_tt (15 subtests) ===================
[21:56:58] ==================== ttm_tt_init_basic ====================
[21:56:58] [PASSED] Page-aligned size
[21:56:58] [PASSED] Extra pages requested
[21:56:58] ================ [PASSED] ttm_tt_init_basic ================
[21:56:58] [PASSED] ttm_tt_init_misaligned
[21:56:58] [PASSED] ttm_tt_fini_basic
[21:56:58] [PASSED] ttm_tt_fini_sg
[21:56:58] [PASSED] ttm_tt_fini_shmem
[21:56:58] [PASSED] ttm_tt_create_basic
[21:56:58] [PASSED] ttm_tt_create_invalid_bo_type
[21:56:58] [PASSED] ttm_tt_create_ttm_exists
[21:56:58] [PASSED] ttm_tt_create_failed
[21:56:58] [PASSED] ttm_tt_destroy_basic
[21:56:58] [PASSED] ttm_tt_populate_null_ttm
[21:56:58] [PASSED] ttm_tt_populate_populated_ttm
[21:56:58] [PASSED] ttm_tt_unpopulate_basic
[21:56:58] [PASSED] ttm_tt_unpopulate_empty_ttm
[21:56:58] [PASSED] ttm_tt_swapin_basic
[21:56:58] ===================== [PASSED] ttm_tt ======================
[21:56:58] =================== ttm_bo (14 subtests) ===================
[21:56:58] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[21:56:58] [PASSED] Cannot be interrupted and sleeps
[21:56:58] [PASSED] Cannot be interrupted, locks straight away
[21:56:58] [PASSED] Can be interrupted, sleeps
[21:56:58] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[21:56:58] [PASSED] ttm_bo_reserve_locked_no_sleep
[21:56:58] [PASSED] ttm_bo_reserve_no_wait_ticket
[21:56:58] [PASSED] ttm_bo_reserve_double_resv
[21:56:58] [PASSED] ttm_bo_reserve_interrupted
[21:56:58] [PASSED] ttm_bo_reserve_deadlock
[21:56:58] [PASSED] ttm_bo_unreserve_basic
[21:56:58] [PASSED] ttm_bo_unreserve_pinned
[21:56:58] [PASSED] ttm_bo_unreserve_bulk
[21:56:58] [PASSED] ttm_bo_put_basic
[21:56:58] [PASSED] ttm_bo_put_shared_resv
[21:56:58] [PASSED] ttm_bo_pin_basic
[21:56:58] [PASSED] ttm_bo_pin_unpin_resource
[21:56:58] [PASSED] ttm_bo_multiple_pin_one_unpin
[21:56:58] ===================== [PASSED] ttm_bo ======================
[21:56:58] ============== ttm_bo_validate (22 subtests) ===============
[21:56:58] ============== ttm_bo_init_reserved_sys_man ===============
[21:56:58] [PASSED] Buffer object for userspace
[21:56:58] [PASSED] Kernel buffer object
[21:56:58] [PASSED] Shared buffer object
[21:56:58] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[21:56:58] ============== ttm_bo_init_reserved_mock_man ==============
[21:56:58] [PASSED] Buffer object for userspace
[21:56:58] [PASSED] Kernel buffer object
[21:56:58] [PASSED] Shared buffer object
[21:56:58] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[21:56:58] [PASSED] ttm_bo_init_reserved_resv
[21:56:58] ================== ttm_bo_validate_basic ==================
[21:56:58] [PASSED] Buffer object for userspace
[21:56:58] [PASSED] Kernel buffer object
[21:56:58] [PASSED] Shared buffer object
[21:56:58] ============== [PASSED] ttm_bo_validate_basic ==============
[21:56:58] [PASSED] ttm_bo_validate_invalid_placement
[21:56:58] ============= ttm_bo_validate_same_placement ==============
[21:56:58] [PASSED] System manager
[21:56:58] [PASSED] VRAM manager
[21:56:58] ========= [PASSED] ttm_bo_validate_same_placement ==========
[21:56:58] [PASSED] ttm_bo_validate_failed_alloc
[21:56:58] [PASSED] ttm_bo_validate_pinned
[21:56:58] [PASSED] ttm_bo_validate_busy_placement
[21:56:58] ================ ttm_bo_validate_multihop =================
[21:56:58] [PASSED] Buffer object for userspace
[21:56:58] [PASSED] Kernel buffer object
[21:56:58] [PASSED] Shared buffer object
[21:56:58] ============ [PASSED] ttm_bo_validate_multihop =============
[21:56:58] ========== ttm_bo_validate_no_placement_signaled ==========
[21:56:58] [PASSED] Buffer object in system domain, no page vector
[21:56:58] [PASSED] Buffer object in system domain with an existing page vector
[21:56:58] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[21:56:58] ======== ttm_bo_validate_no_placement_not_signaled ========
[21:56:58] [PASSED] Buffer object for userspace
[21:56:58] [PASSED] Kernel buffer object
[21:56:58] [PASSED] Shared buffer object
[21:56:58] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[21:56:58] [PASSED] ttm_bo_validate_move_fence_signaled
[21:56:58] ========= ttm_bo_validate_move_fence_not_signaled =========
[21:56:58] [PASSED] Waits for GPU
[21:56:58] [PASSED] Tries to lock straight away
[21:56:59] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[21:56:59] [PASSED] ttm_bo_validate_swapout
[21:56:59] [PASSED] ttm_bo_validate_happy_evict
[21:56:59] [PASSED] ttm_bo_validate_all_pinned_evict
[21:56:59] [PASSED] ttm_bo_validate_allowed_only_evict
[21:56:59] [PASSED] ttm_bo_validate_deleted_evict
[21:56:59] [PASSED] ttm_bo_validate_busy_domain_evict
[21:56:59] [PASSED] ttm_bo_validate_evict_gutting
[21:56:59] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[21:56:59] ================= [PASSED] ttm_bo_validate =================
[21:56:59] ============================================================
[21:56:59] Testing complete. Ran 102 tests: passed: 102
[21:56:59] Elapsed time: 10.039s total, 1.678s configuring, 7.744s building, 0.530s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Xe.CI.BAT: failure for drm/xe: Create and use SoC WA infrastructure
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
` (6 preceding siblings ...)
2025-06-20 21:57 ` ✓ CI.KUnit: success " Patchwork
@ 2025-06-20 22:58 ` Patchwork
2025-06-23 16:13 ` Matt Atwood
2025-06-21 6:05 ` ✗ Xe.CI.Full: " Patchwork
8 siblings, 1 reply; 16+ messages in thread
From: Patchwork @ 2025-06-20 22:58 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2558 bytes --]
== Series Details ==
Series: drm/xe: Create and use SoC WA infrastructure
URL : https://patchwork.freedesktop.org/series/150584/
State : failure
== Summary ==
CI Bug Log - changes from xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17_BAT -> xe-pw-150584v1_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-150584v1_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-150584v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 8)
------------------------------
Missing (1): bat-adlp-vm
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-150584v1_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@xe_module_load@load:
- bat-dg2-oem2: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-dg2-oem2/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-dg2-oem2/igt@xe_module_load@load.html
- bat-atsm-2: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-atsm-2/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-atsm-2/igt@xe_module_load@load.html
- bat-pvc-2: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-pvc-2/igt@xe_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-pvc-2/igt@xe_module_load@load.html
- bat-adlp-7: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-adlp-7/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-adlp-7/igt@xe_module_load@load.html
Build changes
-------------
* Linux: xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17 -> xe-pw-150584v1
IGT_8419: 8419
xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17: 3dde2e2646b2619f765de9c226bfe0dda7bf1f17
xe-pw-150584v1: 150584v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/index.html
[-- Attachment #2: Type: text/html, Size: 3167 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Xe.CI.Full: failure for drm/xe: Create and use SoC WA infrastructure
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
` (7 preceding siblings ...)
2025-06-20 22:58 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-06-21 6:05 ` Patchwork
8 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2025-06-21 6:05 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 43680 bytes --]
== Series Details ==
Series: drm/xe: Create and use SoC WA infrastructure
URL : https://patchwork.freedesktop.org/series/150584/
State : failure
== Summary ==
CI Bug Log - changes from xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17_FULL -> xe-pw-150584v1_FULL
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with xe-pw-150584v1_FULL need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-150584v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-150584v1_FULL:
### IGT changes ###
#### Warnings ####
* igt@xe_module_load@load:
- shard-adlp: ([PASS][1], [PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [SKIP][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) ([Intel XE#378]) -> ([ABORT][27], [ABORT][28], [ABORT][29], [ABORT][30], [ABORT][31], [ABORT][32], [ABORT][33], [ABORT][34], [ABORT][35], [ABORT][36], [ABORT][37], [ABORT][38], [ABORT][39], [ABORT][40], [ABORT][41], [ABORT][42], [ABORT][43], [ABORT][44], [ABORT][45], [ABORT][46], [ABORT][47], [ABORT][48], [ABORT][49]) ([Intel XE#2953])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-6/igt@xe_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-6/igt@xe_module_load@load.html
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-2/igt@xe_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-2/igt@xe_module_load@load.html
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-4/igt@xe_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-4/igt@xe_module_load@load.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-3/igt@xe_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-3/igt@xe_module_load@load.html
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-1/igt@xe_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-1/igt@xe_module_load@load.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-3/igt@xe_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-4/igt@xe_module_load@load.html
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-3/igt@xe_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-8/igt@xe_module_load@load.html
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-8/igt@xe_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-8/igt@xe_module_load@load.html
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-2/igt@xe_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-9/igt@xe_module_load@load.html
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-1/igt@xe_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-9/igt@xe_module_load@load.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-1/igt@xe_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-6/igt@xe_module_load@load.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-6/igt@xe_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-8/igt@xe_module_load@load.html
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-9/igt@xe_module_load@load.html
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-adlp-2/igt@xe_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-2/igt@xe_module_load@load.html
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-2/igt@xe_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-2/igt@xe_module_load@load.html
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-3/igt@xe_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-3/igt@xe_module_load@load.html
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-3/igt@xe_module_load@load.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-4/igt@xe_module_load@load.html
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-4/igt@xe_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-4/igt@xe_module_load@load.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-9/igt@xe_module_load@load.html
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-8/igt@xe_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-8/igt@xe_module_load@load.html
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-8/igt@xe_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-6/igt@xe_module_load@load.html
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-6/igt@xe_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-6/igt@xe_module_load@load.html
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-6/igt@xe_module_load@load.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-3/igt@xe_module_load@load.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-1/igt@xe_module_load@load.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-1/igt@xe_module_load@load.html
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-1/igt@xe_module_load@load.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-2/igt@xe_module_load@load.html
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-adlp-1/igt@xe_module_load@load.html
- shard-dg2-set2: ([PASS][50], [PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [SKIP][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66]) ([Intel XE#378]) -> ([ABORT][67], [ABORT][68], [ABORT][69], [ABORT][70], [ABORT][71], [ABORT][72], [ABORT][73], [ABORT][74], [ABORT][75], [ABORT][76], [ABORT][77], [ABORT][78], [ABORT][79], [ABORT][80], [ABORT][81], [ABORT][82], [ABORT][83], [ABORT][84])
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-435/igt@xe_module_load@load.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-466/igt@xe_module_load@load.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-466/igt@xe_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-466/igt@xe_module_load@load.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-434/igt@xe_module_load@load.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-434/igt@xe_module_load@load.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-434/igt@xe_module_load@load.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-434/igt@xe_module_load@load.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-434/igt@xe_module_load@load.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-435/igt@xe_module_load@load.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-435/igt@xe_module_load@load.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-435/igt@xe_module_load@load.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-466/igt@xe_module_load@load.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-466/igt@xe_module_load@load.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-434/igt@xe_module_load@load.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-435/igt@xe_module_load@load.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-dg2-435/igt@xe_module_load@load.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-435/igt@xe_module_load@load.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-466/igt@xe_module_load@load.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-434/igt@xe_module_load@load.html
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-434/igt@xe_module_load@load.html
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-434/igt@xe_module_load@load.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-434/igt@xe_module_load@load.html
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-466/igt@xe_module_load@load.html
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-434/igt@xe_module_load@load.html
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-434/igt@xe_module_load@load.html
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-466/igt@xe_module_load@load.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-466/igt@xe_module_load@load.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-466/igt@xe_module_load@load.html
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-435/igt@xe_module_load@load.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-466/igt@xe_module_load@load.html
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-435/igt@xe_module_load@load.html
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-435/igt@xe_module_load@load.html
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-435/igt@xe_module_load@load.html
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-dg2-435/igt@xe_module_load@load.html
Known issues
------------
Here are the changes found in xe-pw-150584v1_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-16bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][85] ([Intel XE#2327]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-bmg: NOTRUN -> [SKIP][86] ([Intel XE#1124]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][87] ([Intel XE#607])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#2314] / [Intel XE#2894])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_bw@connected-linear-tiling-4-displays-2160x1440p.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2:
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#2652] / [Intel XE#787]) +12 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-b-dp-2.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#3432])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][91] ([Intel XE#2887]) +2 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#2252]) +4 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][93] ([Intel XE#1178])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#2320])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-bmg: NOTRUN -> [SKIP][95] ([Intel XE#2321]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_display_modes@extended-mode-basic:
- shard-bmg: [PASS][96] -> [SKIP][97] ([Intel XE#4302])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@kms_display_modes@extended-mode-basic.html
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#2244])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#2316]) +1 other test skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [PASS][100] -> [SKIP][101] ([Intel XE#2316]) +4 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-4/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-lnl: [PASS][102] -> [FAIL][103] ([Intel XE#886]) +1 other test fail
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-lnl-5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-lnl-1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
- shard-bmg: NOTRUN -> [SKIP][104] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][105] ([Intel XE#2293]) +2 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][106] ([Intel XE#2312]) +4 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render:
- shard-bmg: NOTRUN -> [SKIP][107] ([Intel XE#2311]) +8 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-rgb101010-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][108] ([Intel XE#4141]) +7 other tests skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
- shard-bmg: NOTRUN -> [SKIP][109] ([Intel XE#2313]) +10 other tests skip
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_hdr@static-toggle:
- shard-bmg: [PASS][110] -> [SKIP][111] ([Intel XE#1503])
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-4/igt@kms_hdr@static-toggle.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-6/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-bmg: [PASS][112] -> [SKIP][113] ([Intel XE#3012])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@kms_joiner@basic-force-big-joiner.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_plane_lowres@tiling-y:
- shard-bmg: NOTRUN -> [SKIP][114] ([Intel XE#2393])
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_plane_lowres@tiling-y.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][115] ([Intel XE#1489]) +2 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-bmg: NOTRUN -> [SKIP][116] ([Intel XE#2387])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr-cursor-plane-onoff:
- shard-bmg: NOTRUN -> [SKIP][117] ([Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_psr@psr-cursor-plane-onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: NOTRUN -> [SKIP][118] ([Intel XE#2414])
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-bmg: NOTRUN -> [SKIP][119] ([Intel XE#2413])
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_vrr@max-min:
- shard-bmg: NOTRUN -> [SKIP][120] ([Intel XE#1499])
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_vrr@max-min.html
- shard-lnl: [PASS][121] -> [FAIL][122] ([Intel XE#4227]) +1 other test fail
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-lnl-3/igt@kms_vrr@max-min.html
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-lnl-5/igt@kms_vrr@max-min.html
* igt@xe_create@multigpu-create-massive-size:
- shard-bmg: NOTRUN -> [SKIP][123] ([Intel XE#2504])
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind:
- shard-bmg: NOTRUN -> [SKIP][124] ([Intel XE#2322]) +1 other test skip
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-null-rebind.html
* igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug:
- shard-bmg: NOTRUN -> [SKIP][125] ([Intel XE#4837]) +6 other tests skip
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@xe_exec_sip_eudebug@breakpoint-writesip-nodebug.html
* igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][126] ([Intel XE#4943]) +8 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_exec_system_allocator@process-many-stride-mmap-new-huge.html
* igt@xe_module_load@load:
- shard-bmg: ([PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143], [PASS][144], [PASS][145], [PASS][146], [PASS][147], [PASS][148], [PASS][149], [PASS][150], [PASS][151]) -> ([PASS][152], [PASS][153], [PASS][154], [PASS][155], [PASS][156], [SKIP][157], [PASS][158], [PASS][159], [PASS][160], [PASS][161], [PASS][162], [PASS][163], [PASS][164], [PASS][165], [PASS][166], [PASS][167], [PASS][168], [PASS][169], [PASS][170], [PASS][171], [PASS][172], [PASS][173], [PASS][174], [PASS][175], [PASS][176], [PASS][177]) ([Intel XE#2457])
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@xe_module_load@load.html
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-4/igt@xe_module_load@load.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@xe_module_load@load.html
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@xe_module_load@load.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@xe_module_load@load.html
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-8/igt@xe_module_load@load.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-8/igt@xe_module_load@load.html
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-7/igt@xe_module_load@load.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-7/igt@xe_module_load@load.html
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-4/igt@xe_module_load@load.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-2/igt@xe_module_load@load.html
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@xe_module_load@load.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-2/igt@xe_module_load@load.html
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-2/igt@xe_module_load@load.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-8/igt@xe_module_load@load.html
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@xe_module_load@load.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@xe_module_load@load.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-1/igt@xe_module_load@load.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-1/igt@xe_module_load@load.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-1/igt@xe_module_load@load.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@xe_module_load@load.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@xe_module_load@load.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-8/igt@xe_module_load@load.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@xe_module_load@load.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@xe_module_load@load.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@xe_module_load@load.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-3/igt@xe_module_load@load.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@xe_module_load@load.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_module_load@load.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_module_load@load.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_module_load@load.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-2/igt@xe_module_load@load.html
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-8/igt@xe_module_load@load.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-2/igt@xe_module_load@load.html
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@xe_module_load@load.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@xe_module_load@load.html
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@xe_module_load@load.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@xe_module_load@load.html
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-8/igt@xe_module_load@load.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-8/igt@xe_module_load@load.html
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_module_load@load.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-3/igt@xe_module_load@load.html
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-6/igt@xe_module_load@load.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@xe_module_load@load.html
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-1/igt@xe_module_load@load.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-1/igt@xe_module_load@load.html
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-2/igt@xe_module_load@load.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-2/igt@xe_module_load@load.html
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-1/igt@xe_module_load@load.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-3/igt@xe_module_load@load.html
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-6/igt@xe_module_load@load.html
* igt@xe_pxp@display-pxp-fb:
- shard-bmg: NOTRUN -> [SKIP][178] ([Intel XE#4733]) +1 other test skip
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_pxp@display-pxp-fb.html
* igt@xe_query@multigpu-query-invalid-extension:
- shard-bmg: NOTRUN -> [SKIP][179] ([Intel XE#944])
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_query@multigpu-query-invalid-extension.html
* igt@xe_sriov_auto_provisioning@exclusive-ranges:
- shard-bmg: NOTRUN -> [SKIP][180] ([Intel XE#4130])
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@xe_sriov_auto_provisioning@exclusive-ranges.html
#### Possible fixes ####
* igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
- shard-bmg: [SKIP][181] ([Intel XE#2291]) -> [PASS][182] +6 other tests pass
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-bmg: [SKIP][183] ([Intel XE#2316]) -> [PASS][184] +2 other tests pass
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@kms_flip@2x-flip-vs-dpms.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][185] ([Intel XE#886]) -> [PASS][186]
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-lnl-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-lnl-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@b-edp1.html
* igt@kms_hdr@static-toggle-dpms:
- shard-bmg: [SKIP][187] ([Intel XE#1503]) -> [PASS][188]
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@kms_hdr@static-toggle-dpms.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_plane_multiple@2x-tiling-4:
- shard-bmg: [SKIP][189] ([Intel XE#4596]) -> [PASS][190]
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-4.html
* igt@kms_setmode@basic@pipe-b-edp-1:
- shard-lnl: [FAIL][191] ([Intel XE#2883]) -> [PASS][192] +2 other tests pass
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-lnl-7/igt@kms_setmode@basic@pipe-b-edp-1.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-lnl-5/igt@kms_setmode@basic@pipe-b-edp-1.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-bmg: [SKIP][193] ([Intel XE#1435]) -> [PASS][194]
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@kms_setmode@clone-exclusive-crtc.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-8/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_vrr@negative-basic:
- shard-bmg: [SKIP][195] ([Intel XE#1499]) -> [PASS][196]
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@kms_vrr@negative-basic.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@kms_vrr@negative-basic.html
* igt@xe_pm@s4-vm-bind-unbind-all:
- shard-bmg: [ABORT][197] -> [PASS][198] +1 other test pass
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@xe_pm@s4-vm-bind-unbind-all.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@xe_pm@s4-vm-bind-unbind-all.html
#### Warnings ####
* igt@kms_content_protection@atomic-dpms:
- shard-bmg: [SKIP][199] ([Intel XE#2341]) -> [FAIL][200] ([Intel XE#1178])
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@kms_content_protection@atomic-dpms.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@kms_content_protection@atomic-dpms.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt:
- shard-bmg: [SKIP][201] ([Intel XE#2311]) -> [SKIP][202] ([Intel XE#2312]) +6 other tests skip
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: [SKIP][203] ([Intel XE#4141]) -> [SKIP][204] ([Intel XE#2312]) +5 other tests skip
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
- shard-bmg: [SKIP][205] ([Intel XE#2312]) -> [SKIP][206] ([Intel XE#4141]) +6 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][207] ([Intel XE#2312]) -> [SKIP][208] ([Intel XE#2311]) +14 other tests skip
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw:
- shard-bmg: [SKIP][209] ([Intel XE#2313]) -> [SKIP][210] ([Intel XE#2312]) +7 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-bmg: [SKIP][211] ([Intel XE#2312]) -> [SKIP][212] ([Intel XE#2313]) +16 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][213] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][214] ([Intel XE#3544])
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][215] ([Intel XE#2426]) -> [SKIP][216] ([Intel XE#2509])
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
[Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2883]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2883
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
[Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17 -> xe-pw-150584v1
IGT_8419: 8419
xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17: 3dde2e2646b2619f765de9c226bfe0dda7bf1f17
xe-pw-150584v1: 150584v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/index.html
[-- Attachment #2: Type: text/html, Size: 47061 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: ✗ Xe.CI.BAT: failure for drm/xe: Create and use SoC WA infrastructure
2025-06-20 22:58 ` ✗ Xe.CI.BAT: failure " Patchwork
@ 2025-06-23 16:13 ` Matt Atwood
0 siblings, 0 replies; 16+ messages in thread
From: Matt Atwood @ 2025-06-23 16:13 UTC (permalink / raw)
To: intel-xe
On Fri, Jun 20, 2025 at 10:58:30PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/xe: Create and use SoC WA infrastructure
> URL : https://patchwork.freedesktop.org/series/150584/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17_BAT -> xe-pw-150584v1_BAT
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with xe-pw-150584v1_BAT absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in xe-pw-150584v1_BAT, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (9 -> 8)
> ------------------------------
>
> Missing (1): bat-adlp-vm
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in xe-pw-150584v1_BAT:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@xe_module_load@load:
> - bat-dg2-oem2: [PASS][1] -> [ABORT][2]
> [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-dg2-oem2/igt@xe_module_load@load.html
> [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-dg2-oem2/igt@xe_module_load@load.html
> - bat-atsm-2: [PASS][3] -> [ABORT][4]
> [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-atsm-2/igt@xe_module_load@load.html
> [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-atsm-2/igt@xe_module_load@load.html
> - bat-pvc-2: [PASS][5] -> [ABORT][6]
> [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-pvc-2/igt@xe_module_load@load.html
> [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-pvc-2/igt@xe_module_load@load.html
> - bat-adlp-7: [PASS][7] -> [ABORT][8]
> [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17/bat-adlp-7/igt@xe_module_load@load.html
> [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/bat-adlp-7/igt@xe_module_load@load.html
These are caused by my assumption that tile0 would alwyas have a
media_gt, our call to XE_SOC() needs to have a check into xe_device
to ensure that there is a media gt.
>
>
>
>
> Build changes
> -------------
>
> * Linux: xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17 -> xe-pw-150584v1
>
> IGT_8419: 8419
> xe-3284-3dde2e2646b2619f765de9c226bfe0dda7bf1f17: 3dde2e2646b2619f765de9c226bfe0dda7bf1f17
> xe-pw-150584v1: 150584v1
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150584v1/index.html
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0
2025-06-20 21:49 ` [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0 Matt Atwood
@ 2025-06-23 21:12 ` Rodrigo Vivi
2025-06-23 23:31 ` Matt Roper
0 siblings, 1 reply; 16+ messages in thread
From: Rodrigo Vivi @ 2025-06-23 21:12 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-xe, matthew.d.roper
On Fri, Jun 20, 2025 at 02:49:20PM -0700, Matt Atwood wrote:
> This workaround only applies to PTL Compute Die A0. However, this
> information cannot be determined until after the GT is brought up. This
> means that we will assume that it is required for the initial bring up of
> the gt. After GT init, the oob workarounds are enabled for the GT. Use
> this flag to then manually set the bit in the soc oob bit field to 0
> which will help performance after device bring up.
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
> drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index ded0f3dc8d73..a624c3fb9498 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -34,6 +34,9 @@
> #include "xe_tile.h"
> #include "xe_wa.h"
>
> +#include "generated/xe_wa_oob.h"
> +#include "generated/xe_soc_wa_oob.h"
> +
> enum toggle_d3cold {
> D3COLD_DISABLE,
> D3COLD_ENABLE,
> @@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> drm_dbg(&xe->drm, "d3cold: capable=%s\n",
> str_yes_no(xe->d3cold.capable));
>
> + if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
> + xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
We are discussing this offline, but I need to make it very clear here
that we should not move forward with this as is.
Two unnaceptable points in here:
\
1. _disable. We either enable or we don't. If we need to wait for the gmdid,
let it be and enable the workaround after that. GMDID should be one of the
first things and I confirmed this workaround is so rare that in an a0 situation
you could wait to only enable after you read the gmd-id and confirm the
media is A0.
2. Don't mix SoC with Media. If the Bug is SoC don't wait of the media stepping
and check directly for the SoC that needs this. So, don't create an infra that
already has an exception in it. And if possible, avoid the infra at all. This
might bring even more confusion to the w/a handling.
This w/a in specific here is soc, but it is getting mapped to our media-ip,
so let's use the media check...
> +
> return 0;
>
> err_driver_cleanup:
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 8c2aa48cb33a..822cbff13819 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -71,3 +71,4 @@ no_media_l3 MEDIA_VERSION(3000)
> # primary GT GMDID
> 14022085890 GRAPHICS_VERSION(2001)
> 16026007364 MEDIA_VERSION(3000)
> +15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
> --
> 2.49.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0
2025-06-23 21:12 ` Rodrigo Vivi
@ 2025-06-23 23:31 ` Matt Roper
2025-06-24 19:25 ` Rodrigo Vivi
0 siblings, 1 reply; 16+ messages in thread
From: Matt Roper @ 2025-06-23 23:31 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Matt Atwood, intel-xe
On Mon, Jun 23, 2025 at 05:12:05PM -0400, Rodrigo Vivi wrote:
> On Fri, Jun 20, 2025 at 02:49:20PM -0700, Matt Atwood wrote:
> > This workaround only applies to PTL Compute Die A0. However, this
> > information cannot be determined until after the GT is brought up. This
> > means that we will assume that it is required for the initial bring up of
> > the gt. After GT init, the oob workarounds are enabled for the GT. Use
> > this flag to then manually set the bit in the soc oob bit field to 0
> > which will help performance after device bring up.
> >
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
> > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > index ded0f3dc8d73..a624c3fb9498 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -34,6 +34,9 @@
> > #include "xe_tile.h"
> > #include "xe_wa.h"
> >
> > +#include "generated/xe_wa_oob.h"
> > +#include "generated/xe_soc_wa_oob.h"
> > +
> > enum toggle_d3cold {
> > D3COLD_DISABLE,
> > D3COLD_ENABLE,
> > @@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > drm_dbg(&xe->drm, "d3cold: capable=%s\n",
> > str_yes_no(xe->d3cold.capable));
> >
> > + if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
> > + xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
>
> We are discussing this offline, but I need to make it very clear here
> that we should not move forward with this as is.
>
> Two unnaceptable points in here:
> \
> 1. _disable. We either enable or we don't. If we need to wait for the gmdid,
> let it be and enable the workaround after that. GMDID should be one of the
> first things and I confirmed this workaround is so rare that in an a0 situation
> you could wait to only enable after you read the gmd-id and confirm the
> media is A0.
This is exactly what we *can't* do for this workaround. The requirement
is that on any impacted platform, every single register read must be
preceded by four extra dummy writes. There's no such thing as "early
enough to ignore" --- it's specifically noted that even pre-OS firmware
and such needs to be careful about doing this as well. So this causes a
bit of a chicken-and-egg issue: we cannot read the GMD_ID register
without having the workaround active on impacted platforms, but we
cannot figure out whether the platform is impacted until after we've
read that register[*]. We also do a bunch of other register reads
during early driver probe before the xe_gt is initialized enough to be
able to service workaround lookup queries. So there are a few options
here:
* Mark the platform as always being active on PTL, then come back and
disable it later if/when we confirm that we're on a stepping that
isn't impacted by the issue. This is pretty simple conceptually, and
is quite likely something we'll need in the future for other
workarounds. That's the approach MattA has taken here.
* Add two separate workarounds in the driver: 15015404425_early and
15015404425. 15015404425_early is an SoC workaround that applies
unconditionally on PTL, and 15015404425 is a GT workaround that
applies only on specific media steppings. Both do exactly the same
thing (4 dummy writes before any register read), but
15015404425_early is checked before all early MMIO accesses and
15015404425 is checked on all others. The downside of this approach
is that we'd need to use a completely different set of MMIO
operations for early driver boot (i.e., no xe_mmio_read32 and such).
* Ignore this workaround completely if we can confirm that it only
impacts pre-production steppings. I don't think we have confirmation
yet that A-step hardware is preprod-only, so we can't take this easy
path yet.
>
> 2. Don't mix SoC with Media. If the Bug is SoC don't wait of the media stepping
> and check directly for the SoC that needs this. So, don't create an infra that
> already has an exception in it. And if possible, avoid the infra at all. This
> might bring even more confusion to the w/a handling.
>
> This w/a in specific here is soc, but it is getting mapped to our media-ip,
> so let's use the media check...
I think more explanation needs to be added to the patches to clarify
exactly what's going on since it's still a bit non-obvious. The reality
is that our modern platforms aren't actually "SOCs" at all anymore;
they're technically MCP's --- Multi Chip Packages with logic (and
sometimes hardware issues) spread across the various dies. The hardware
teams still refer certain things to be "SoC" logic for historical
reasons, even though that logic is technically distributed across
multiple chips these days.
We absolutely need some kind of "device" workaround framework that isn't
tied to the GT and that can be used before GTs are even up; we have some
non-GT workarounds today that we're not really handling properly, and we
know there are more coming. I think when this workaround first came up
I suggested a "device workaround" infrastructure and using the same
general XE_WA() calls, with a _Generic() implementation to lookup the
status of a workaround in either the xe_device or the xe_gt depending on
which is passed (with the xe_device workaround table being initialized
much earlier in the probe sequence).
Issues outside of the GT can live in different places: the GCD die, the
compute (aka CPU) die, the IO die, etc. Each of these have their own
steppings, and the MCP itself has a stepping too. In some of these
cases, the proper way to determine a stepping is to map PCI revid into a
die stepping. In other cases the proper approach is to "fingerprint" a
die's stepping by inspecting some other IP that lives on the same die
(similar to how we used to fingerprint the PCH back in the day by
inspecting the ISA bus device). For this workaround the stepping we
care about is the compute (CPU) die stepping, and since standalone media
happens to live on that same die, the bspec tells us how to figure out
compute die stepping from media stepping (A-step compute die <=> A-step
media IP in this case, although that isn't something that's guaranteed
to always be true).
[*] An alternative to fingerprinting compute die based on media stepping
would probably be to check the CPU stepping through whatever
mechanism is used to print the stepping in /proc/cpuinfo. We'd have
to find separate documentation on how to map the numeric value there
into somthing like "B0;" I don't know off the top of my head where
that documentation would be but the core kernel guys could probably
point us in the right direction.
Matt
>
> > +
> > return 0;
> >
> > err_driver_cleanup:
> > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > index 8c2aa48cb33a..822cbff13819 100644
> > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > @@ -71,3 +71,4 @@ no_media_l3 MEDIA_VERSION(3000)
> > # primary GT GMDID
> > 14022085890 GRAPHICS_VERSION(2001)
> > 16026007364 MEDIA_VERSION(3000)
> > +15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
> > --
> > 2.49.0
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0
2025-06-23 23:31 ` Matt Roper
@ 2025-06-24 19:25 ` Rodrigo Vivi
2025-06-24 19:39 ` Matt Atwood
0 siblings, 1 reply; 16+ messages in thread
From: Rodrigo Vivi @ 2025-06-24 19:25 UTC (permalink / raw)
To: Matt Roper; +Cc: Matt Atwood, intel-xe
On Mon, Jun 23, 2025 at 04:31:30PM -0700, Matt Roper wrote:
> On Mon, Jun 23, 2025 at 05:12:05PM -0400, Rodrigo Vivi wrote:
> > On Fri, Jun 20, 2025 at 02:49:20PM -0700, Matt Atwood wrote:
> > > This workaround only applies to PTL Compute Die A0. However, this
> > > information cannot be determined until after the GT is brought up. This
> > > means that we will assume that it is required for the initial bring up of
> > > the gt. After GT init, the oob workarounds are enabled for the GT. Use
> > > this flag to then manually set the bit in the soc oob bit field to 0
> > > which will help performance after device bring up.
> > >
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
> > > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
> > > 2 files changed, 7 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > index ded0f3dc8d73..a624c3fb9498 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -34,6 +34,9 @@
> > > #include "xe_tile.h"
> > > #include "xe_wa.h"
> > >
> > > +#include "generated/xe_wa_oob.h"
> > > +#include "generated/xe_soc_wa_oob.h"
> > > +
> > > enum toggle_d3cold {
> > > D3COLD_DISABLE,
> > > D3COLD_ENABLE,
> > > @@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > > drm_dbg(&xe->drm, "d3cold: capable=%s\n",
> > > str_yes_no(xe->d3cold.capable));
> > >
> > > + if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
> > > + xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
> >
> > We are discussing this offline, but I need to make it very clear here
> > that we should not move forward with this as is.
> >
> > Two unnaceptable points in here:
> > \
> > 1. _disable. We either enable or we don't. If we need to wait for the gmdid,
> > let it be and enable the workaround after that. GMDID should be one of the
> > first things and I confirmed this workaround is so rare that in an a0 situation
> > you could wait to only enable after you read the gmd-id and confirm the
> > media is A0.
>
> This is exactly what we *can't* do for this workaround. The requirement
> is that on any impacted platform, every single register read must be
> preceded by four extra dummy writes. There's no such thing as "early
> enough to ignore" ---
What I got from the Architects on this is that it would be safe enough to
read the GMDID without this workaround since the condition for the issue
to manifest is not on a single read like this, although the protection is
global.
But okay, let's work with the assumption that it is better to protect
anyway.
> it's specifically noted that even pre-OS firmware
> and such needs to be careful about doing this as well. So this causes a
> bit of a chicken-and-egg issue: we cannot read the GMD_ID register
> without having the workaround active on impacted platforms, but we
> cannot figure out whether the platform is impacted until after we've
> read that register[*]. We also do a bunch of other register reads
> during early driver probe before the xe_gt is initialized enough to be
> able to service workaround lookup queries. So there are a few options
> here:
>
> * Mark the platform as always being active on PTL, then come back and
> disable it later if/when we confirm that we're on a stepping that
> isn't impacted by the issue. This is pretty simple conceptually, and
> is quite likely something we'll need in the future for other
> workarounds. That's the approach MattA has taken here.
ack.
>
> * Add two separate workarounds in the driver: 15015404425_early and
> 15015404425. 15015404425_early is an SoC workaround that applies
> unconditionally on PTL, and 15015404425 is a GT workaround that
> applies only on specific media steppings. Both do exactly the same
> thing (4 dummy writes before any register read), but
> 15015404425_early is checked before all early MMIO accesses and
> 15015404425 is checked on all others. The downside of this approach
> is that we'd need to use a completely different set of MMIO
> operations for early driver boot (i.e., no xe_mmio_read32 and such).
>
> * Ignore this workaround completely if we can confirm that it only
> impacts pre-production steppings. I don't think we have confirmation
> yet that A-step hardware is preprod-only, so we can't take this easy
> path yet.
>
> >
> > 2. Don't mix SoC with Media. If the Bug is SoC don't wait of the media stepping
> > and check directly for the SoC that needs this. So, don't create an infra that
> > already has an exception in it. And if possible, avoid the infra at all. This
> > might bring even more confusion to the w/a handling.
> >
> > This w/a in specific here is soc, but it is getting mapped to our media-ip,
> > so let's use the media check...
>
> I think more explanation needs to be added to the patches to clarify
> exactly what's going on since it's still a bit non-obvious. The reality
> is that our modern platforms aren't actually "SOCs" at all anymore;
> they're technically MCP's --- Multi Chip Packages with logic (and
> sometimes hardware issues) spread across the various dies. The hardware
> teams still refer certain things to be "SoC" logic for historical
> reasons, even though that logic is technically distributed across
> multiple chips these days.
Well, I still see the glue of all the chips as the SoC. It is easier to
understand.
>
> We absolutely need some kind of "device" workaround framework that isn't
> tied to the GT and that can be used before GTs are even up; we have some
> non-GT workarounds today that we're not really handling properly, and we
> know there are more coming. I think when this workaround first came up
> I suggested a "device workaround" infrastructure and using the same
> general XE_WA() calls, with a _Generic() implementation to lookup the
> status of a workaround in either the xe_device or the xe_gt depending on
> which is passed (with the xe_device workaround table being initialized
> much earlier in the probe sequence).
If we split in device_wa and gt_wa that would make much more sense with
our Xe design indeed.
>
> Issues outside of the GT can live in different places: the GCD die, the
> compute (aka CPU) die, the IO die, etc. Each of these have their own
> steppings, and the MCP itself has a stepping too. In some of these
> cases, the proper way to determine a stepping is to map PCI revid into a
> die stepping. In other cases the proper approach is to "fingerprint" a
> die's stepping by inspecting some other IP that lives on the same die
> (similar to how we used to fingerprint the PCH back in the day by
> inspecting the ISA bus device). For this workaround the stepping we
> care about is the compute (CPU) die stepping, and since standalone media
> happens to live on that same die, the bspec tells us how to figure out
> compute die stepping from media stepping (A-step compute die <=> A-step
> media IP in this case, although that isn't something that's guaranteed
> to always be true).
>
>
> [*] An alternative to fingerprinting compute die based on media stepping
> would probably be to check the CPU stepping through whatever
> mechanism is used to print the stepping in /proc/cpuinfo. We'd have
> to find separate documentation on how to map the numeric value there
> into somthing like "B0;" I don't know off the top of my head where
> that documentation would be but the core kernel guys could probably
> point us in the right direction.
Yeap, in this case it would be the combination of the pci id + cpu-revid.
This makes much more sense for this w/a, but it is hard to generalize indeed.
But also, any device_wa is hard to generalize anyway, since we won't have
a device stepping or anything like that.
So, okay, 15015404425 in xe_device_wa enables it and
15015404425_disable in xe_gt_wa disables it for MEDIA_STEP(B0, FOREVER)
>
>
> Matt
>
> >
> > > +
> > > return 0;
> > >
> > > err_driver_cleanup:
> > > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > index 8c2aa48cb33a..822cbff13819 100644
> > > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > @@ -71,3 +71,4 @@ no_media_l3 MEDIA_VERSION(3000)
> > > # primary GT GMDID
> > > 14022085890 GRAPHICS_VERSION(2001)
> > > 16026007364 MEDIA_VERSION(3000)
> > > +15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
> > > --
> > > 2.49.0
> > >
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0
2025-06-24 19:25 ` Rodrigo Vivi
@ 2025-06-24 19:39 ` Matt Atwood
2025-06-24 20:53 ` Rodrigo Vivi
0 siblings, 1 reply; 16+ messages in thread
From: Matt Atwood @ 2025-06-24 19:39 UTC (permalink / raw)
To: Rodrigo Vivi, matthew.d.roper, intel-xe; +Cc: Matt Roper, intel-xe
On Tue, Jun 24, 2025 at 03:25:37PM -0400, Rodrigo Vivi wrote:
> On Mon, Jun 23, 2025 at 04:31:30PM -0700, Matt Roper wrote:
> > On Mon, Jun 23, 2025 at 05:12:05PM -0400, Rodrigo Vivi wrote:
> > > On Fri, Jun 20, 2025 at 02:49:20PM -0700, Matt Atwood wrote:
> > > > This workaround only applies to PTL Compute Die A0. However, this
> > > > information cannot be determined until after the GT is brought up. This
> > > > means that we will assume that it is required for the initial bring up of
> > > > the gt. After GT init, the oob workarounds are enabled for the GT. Use
> > > > this flag to then manually set the bit in the soc oob bit field to 0
> > > > which will help performance after device bring up.
> > > >
> > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > > ---
> > > > drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
> > > > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
> > > > 2 files changed, 7 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > > index ded0f3dc8d73..a624c3fb9498 100644
> > > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > > @@ -34,6 +34,9 @@
> > > > #include "xe_tile.h"
> > > > #include "xe_wa.h"
> > > >
> > > > +#include "generated/xe_wa_oob.h"
> > > > +#include "generated/xe_soc_wa_oob.h"
> > > > +
> > > > enum toggle_d3cold {
> > > > D3COLD_DISABLE,
> > > > D3COLD_ENABLE,
> > > > @@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > > > drm_dbg(&xe->drm, "d3cold: capable=%s\n",
> > > > str_yes_no(xe->d3cold.capable));
> > > >
> > > > + if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
> > > > + xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
> > >
> > > We are discussing this offline, but I need to make it very clear here
> > > that we should not move forward with this as is.
> > >
> > > Two unnaceptable points in here:
> > > \
> > > 1. _disable. We either enable or we don't. If we need to wait for the gmdid,
> > > let it be and enable the workaround after that. GMDID should be one of the
> > > first things and I confirmed this workaround is so rare that in an a0 situation
> > > you could wait to only enable after you read the gmd-id and confirm the
> > > media is A0.
> >
> > This is exactly what we *can't* do for this workaround. The requirement
> > is that on any impacted platform, every single register read must be
> > preceded by four extra dummy writes. There's no such thing as "early
> > enough to ignore" ---
>
> What I got from the Architects on this is that it would be safe enough to
> read the GMDID without this workaround since the condition for the issue
> to manifest is not on a single read like this, although the protection is
> global.
>
> But okay, let's work with the assumption that it is better to protect
> anyway.
>
> > it's specifically noted that even pre-OS firmware
> > and such needs to be careful about doing this as well. So this causes a
> > bit of a chicken-and-egg issue: we cannot read the GMD_ID register
> > without having the workaround active on impacted platforms, but we
> > cannot figure out whether the platform is impacted until after we've
> > read that register[*]. We also do a bunch of other register reads
> > during early driver probe before the xe_gt is initialized enough to be
> > able to service workaround lookup queries. So there are a few options
> > here:
> >
> > * Mark the platform as always being active on PTL, then come back and
> > disable it later if/when we confirm that we're on a stepping that
> > isn't impacted by the issue. This is pretty simple conceptually, and
> > is quite likely something we'll need in the future for other
> > workarounds. That's the approach MattA has taken here.
>
> ack.
>
> >
> > * Add two separate workarounds in the driver: 15015404425_early and
> > 15015404425. 15015404425_early is an SoC workaround that applies
> > unconditionally on PTL, and 15015404425 is a GT workaround that
> > applies only on specific media steppings. Both do exactly the same
> > thing (4 dummy writes before any register read), but
> > 15015404425_early is checked before all early MMIO accesses and
> > 15015404425 is checked on all others. The downside of this approach
> > is that we'd need to use a completely different set of MMIO
> > operations for early driver boot (i.e., no xe_mmio_read32 and such).
> >
> > * Ignore this workaround completely if we can confirm that it only
> > impacts pre-production steppings. I don't think we have confirmation
> > yet that A-step hardware is preprod-only, so we can't take this easy
> > path yet.
> >
> > >
> > > 2. Don't mix SoC with Media. If the Bug is SoC don't wait of the media stepping
> > > and check directly for the SoC that needs this. So, don't create an infra that
> > > already has an exception in it. And if possible, avoid the infra at all. This
> > > might bring even more confusion to the w/a handling.
> > >
> > > This w/a in specific here is soc, but it is getting mapped to our media-ip,
> > > so let's use the media check...
> >
> > I think more explanation needs to be added to the patches to clarify
> > exactly what's going on since it's still a bit non-obvious. The reality
> > is that our modern platforms aren't actually "SOCs" at all anymore;
> > they're technically MCP's --- Multi Chip Packages with logic (and
> > sometimes hardware issues) spread across the various dies. The hardware
> > teams still refer certain things to be "SoC" logic for historical
> > reasons, even though that logic is technically distributed across
> > multiple chips these days.
>
> Well, I still see the glue of all the chips as the SoC. It is easier to
> understand.
>
> >
> > We absolutely need some kind of "device" workaround framework that isn't
> > tied to the GT and that can be used before GTs are even up; we have some
> > non-GT workarounds today that we're not really handling properly, and we
> > know there are more coming. I think when this workaround first came up
> > I suggested a "device workaround" infrastructure and using the same
> > general XE_WA() calls, with a _Generic() implementation to lookup the
> > status of a workaround in either the xe_device or the xe_gt depending on
> > which is passed (with the xe_device workaround table being initialized
> > much earlier in the probe sequence).
>
> If we split in device_wa and gt_wa that would make much more sense with
> our Xe design indeed.
Is the ask here to change the name from XE_SOC_WA -> XE_DEVICE_WA?
>
> >
> > Issues outside of the GT can live in different places: the GCD die, the
> > compute (aka CPU) die, the IO die, etc. Each of these have their own
> > steppings, and the MCP itself has a stepping too. In some of these
> > cases, the proper way to determine a stepping is to map PCI revid into a
> > die stepping. In other cases the proper approach is to "fingerprint" a
> > die's stepping by inspecting some other IP that lives on the same die
> > (similar to how we used to fingerprint the PCH back in the day by
> > inspecting the ISA bus device). For this workaround the stepping we
> > care about is the compute (CPU) die stepping, and since standalone media
> > happens to live on that same die, the bspec tells us how to figure out
> > compute die stepping from media stepping (A-step compute die <=> A-step
> > media IP in this case, although that isn't something that's guaranteed
> > to always be true).
> >
> >
> > [*] An alternative to fingerprinting compute die based on media stepping
> > would probably be to check the CPU stepping through whatever
> > mechanism is used to print the stepping in /proc/cpuinfo. We'd have
> > to find separate documentation on how to map the numeric value there
> > into somthing like "B0;" I don't know off the top of my head where
> > that documentation would be but the core kernel guys could probably
> > point us in the right direction.
>
> Yeap, in this case it would be the combination of the pci id + cpu-revid.
> This makes much more sense for this w/a, but it is hard to generalize indeed.
>
> But also, any device_wa is hard to generalize anyway, since we won't have
> a device stepping or anything like that.
>
> So, okay, 15015404425 in xe_device_wa enables it and
> 15015404425_disable in xe_gt_wa disables it for MEDIA_STEP(B0, FOREVER)
>
> >
> >
> > Matt
> >
> > >
> > > > +
> > > > return 0;
> > > >
> > > > err_driver_cleanup:
> > > > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > > index 8c2aa48cb33a..822cbff13819 100644
> > > > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > > @@ -71,3 +71,4 @@ no_media_l3 MEDIA_VERSION(3000)
> > > > # primary GT GMDID
> > > > 14022085890 GRAPHICS_VERSION(2001)
> > > > 16026007364 MEDIA_VERSION(3000)
> > > > +15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
> > > > --
> > > > 2.49.0
> > > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
MattA
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0
2025-06-24 19:39 ` Matt Atwood
@ 2025-06-24 20:53 ` Rodrigo Vivi
0 siblings, 0 replies; 16+ messages in thread
From: Rodrigo Vivi @ 2025-06-24 20:53 UTC (permalink / raw)
To: Matt Atwood; +Cc: matthew.d.roper, intel-xe
On Tue, Jun 24, 2025 at 12:39:03PM -0700, Matt Atwood wrote:
> On Tue, Jun 24, 2025 at 03:25:37PM -0400, Rodrigo Vivi wrote:
> > On Mon, Jun 23, 2025 at 04:31:30PM -0700, Matt Roper wrote:
> > > On Mon, Jun 23, 2025 at 05:12:05PM -0400, Rodrigo Vivi wrote:
> > > > On Fri, Jun 20, 2025 at 02:49:20PM -0700, Matt Atwood wrote:
> > > > > This workaround only applies to PTL Compute Die A0. However, this
> > > > > information cannot be determined until after the GT is brought up. This
> > > > > means that we will assume that it is required for the initial bring up of
> > > > > the gt. After GT init, the oob workarounds are enabled for the GT. Use
> > > > > this flag to then manually set the bit in the soc oob bit field to 0
> > > > > which will help performance after device bring up.
> > > > >
> > > > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/xe/xe_pci.c | 6 ++++++
> > > > > drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
> > > > > 2 files changed, 7 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > > > index ded0f3dc8d73..a624c3fb9498 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > > > @@ -34,6 +34,9 @@
> > > > > #include "xe_tile.h"
> > > > > #include "xe_wa.h"
> > > > >
> > > > > +#include "generated/xe_wa_oob.h"
> > > > > +#include "generated/xe_soc_wa_oob.h"
> > > > > +
> > > > > enum toggle_d3cold {
> > > > > D3COLD_DISABLE,
> > > > > D3COLD_ENABLE,
> > > > > @@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > > > > drm_dbg(&xe->drm, "d3cold: capable=%s\n",
> > > > > str_yes_no(xe->d3cold.capable));
> > > > >
> > > > > + if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
> > > > > + xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
> > > >
> > > > We are discussing this offline, but I need to make it very clear here
> > > > that we should not move forward with this as is.
> > > >
> > > > Two unnaceptable points in here:
> > > > \
> > > > 1. _disable. We either enable or we don't. If we need to wait for the gmdid,
> > > > let it be and enable the workaround after that. GMDID should be one of the
> > > > first things and I confirmed this workaround is so rare that in an a0 situation
> > > > you could wait to only enable after you read the gmd-id and confirm the
> > > > media is A0.
> > >
> > > This is exactly what we *can't* do for this workaround. The requirement
> > > is that on any impacted platform, every single register read must be
> > > preceded by four extra dummy writes. There's no such thing as "early
> > > enough to ignore" ---
> >
> > What I got from the Architects on this is that it would be safe enough to
> > read the GMDID without this workaround since the condition for the issue
> > to manifest is not on a single read like this, although the protection is
> > global.
> >
> > But okay, let's work with the assumption that it is better to protect
> > anyway.
> >
> > > it's specifically noted that even pre-OS firmware
> > > and such needs to be careful about doing this as well. So this causes a
> > > bit of a chicken-and-egg issue: we cannot read the GMD_ID register
> > > without having the workaround active on impacted platforms, but we
> > > cannot figure out whether the platform is impacted until after we've
> > > read that register[*]. We also do a bunch of other register reads
> > > during early driver probe before the xe_gt is initialized enough to be
> > > able to service workaround lookup queries. So there are a few options
> > > here:
> > >
> > > * Mark the platform as always being active on PTL, then come back and
> > > disable it later if/when we confirm that we're on a stepping that
> > > isn't impacted by the issue. This is pretty simple conceptually, and
> > > is quite likely something we'll need in the future for other
> > > workarounds. That's the approach MattA has taken here.
> >
> > ack.
> >
> > >
> > > * Add two separate workarounds in the driver: 15015404425_early and
> > > 15015404425. 15015404425_early is an SoC workaround that applies
> > > unconditionally on PTL, and 15015404425 is a GT workaround that
> > > applies only on specific media steppings. Both do exactly the same
> > > thing (4 dummy writes before any register read), but
> > > 15015404425_early is checked before all early MMIO accesses and
> > > 15015404425 is checked on all others. The downside of this approach
> > > is that we'd need to use a completely different set of MMIO
> > > operations for early driver boot (i.e., no xe_mmio_read32 and such).
> > >
> > > * Ignore this workaround completely if we can confirm that it only
> > > impacts pre-production steppings. I don't think we have confirmation
> > > yet that A-step hardware is preprod-only, so we can't take this easy
> > > path yet.
> > >
> > > >
> > > > 2. Don't mix SoC with Media. If the Bug is SoC don't wait of the media stepping
> > > > and check directly for the SoC that needs this. So, don't create an infra that
> > > > already has an exception in it. And if possible, avoid the infra at all. This
> > > > might bring even more confusion to the w/a handling.
> > > >
> > > > This w/a in specific here is soc, but it is getting mapped to our media-ip,
> > > > so let's use the media check...
> > >
> > > I think more explanation needs to be added to the patches to clarify
> > > exactly what's going on since it's still a bit non-obvious. The reality
> > > is that our modern platforms aren't actually "SOCs" at all anymore;
> > > they're technically MCP's --- Multi Chip Packages with logic (and
> > > sometimes hardware issues) spread across the various dies. The hardware
> > > teams still refer certain things to be "SoC" logic for historical
> > > reasons, even though that logic is technically distributed across
> > > multiple chips these days.
> >
> > Well, I still see the glue of all the chips as the SoC. It is easier to
> > understand.
> >
> > >
> > > We absolutely need some kind of "device" workaround framework that isn't
> > > tied to the GT and that can be used before GTs are even up; we have some
> > > non-GT workarounds today that we're not really handling properly, and we
> > > know there are more coming. I think when this workaround first came up
> > > I suggested a "device workaround" infrastructure and using the same
> > > general XE_WA() calls, with a _Generic() implementation to lookup the
> > > status of a workaround in either the xe_device or the xe_gt depending on
> > > which is passed (with the xe_device workaround table being initialized
> > > much earlier in the probe sequence).
> >
> > If we split in device_wa and gt_wa that would make much more sense with
> > our Xe design indeed.
> Is the ask here to change the name from XE_SOC_WA -> XE_DEVICE_WA?
yes, please.
Then as a follow-up we change the other one from xe_wa to xe_gt_wa...
> >
> > >
> > > Issues outside of the GT can live in different places: the GCD die, the
> > > compute (aka CPU) die, the IO die, etc. Each of these have their own
> > > steppings, and the MCP itself has a stepping too. In some of these
> > > cases, the proper way to determine a stepping is to map PCI revid into a
> > > die stepping. In other cases the proper approach is to "fingerprint" a
> > > die's stepping by inspecting some other IP that lives on the same die
> > > (similar to how we used to fingerprint the PCH back in the day by
> > > inspecting the ISA bus device). For this workaround the stepping we
> > > care about is the compute (CPU) die stepping, and since standalone media
> > > happens to live on that same die, the bspec tells us how to figure out
> > > compute die stepping from media stepping (A-step compute die <=> A-step
> > > media IP in this case, although that isn't something that's guaranteed
> > > to always be true).
> > >
> > >
> > > [*] An alternative to fingerprinting compute die based on media stepping
> > > would probably be to check the CPU stepping through whatever
> > > mechanism is used to print the stepping in /proc/cpuinfo. We'd have
> > > to find separate documentation on how to map the numeric value there
> > > into somthing like "B0;" I don't know off the top of my head where
> > > that documentation would be but the core kernel guys could probably
> > > point us in the right direction.
> >
> > Yeap, in this case it would be the combination of the pci id + cpu-revid.
> > This makes much more sense for this w/a, but it is hard to generalize indeed.
> >
> > But also, any device_wa is hard to generalize anyway, since we won't have
> > a device stepping or anything like that.
> >
> > So, okay, 15015404425 in xe_device_wa enables it and
> > 15015404425_disable in xe_gt_wa disables it for MEDIA_STEP(B0, FOREVER)
> >
> > >
> > >
> > > Matt
> > >
> > > >
> > > > > +
> > > > > return 0;
> > > > >
> > > > > err_driver_cleanup:
> > > > > diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > > > index 8c2aa48cb33a..822cbff13819 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > > > +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> > > > > @@ -71,3 +71,4 @@ no_media_l3 MEDIA_VERSION(3000)
> > > > > # primary GT GMDID
> > > > > 14022085890 GRAPHICS_VERSION(2001)
> > > > > 16026007364 MEDIA_VERSION(3000)
> > > > > +15015404425_disable PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
> > > > > --
> > > > > 2.49.0
> > > > >
> > >
> > > --
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation
> MattA
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2025-06-24 20:53 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-06-20 21:49 [PATCH 0/5] drm/xe: Create and use SoC WA infrastructure Matt Atwood
2025-06-20 21:49 ` [PATCH 1/5] drm/xe: add xe_soc_wa infrastructure Matt Atwood
2025-06-20 21:49 ` [PATCH 2/5] drm/xe: Add infrastructure for SoC OOB workarounds Matt Atwood
2025-06-20 21:49 ` [PATCH 3/5] drm/xe: Move Wa_15015404425 to use the new EX_SOC_WA macro Matt Atwood
2025-06-20 21:49 ` [PATCH 4/5] drm/xe: extend Wa_15015404425 to apply to PTL Matt Atwood
2025-06-20 21:49 ` [PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0 Matt Atwood
2025-06-23 21:12 ` Rodrigo Vivi
2025-06-23 23:31 ` Matt Roper
2025-06-24 19:25 ` Rodrigo Vivi
2025-06-24 19:39 ` Matt Atwood
2025-06-24 20:53 ` Rodrigo Vivi
2025-06-20 21:55 ` ✗ CI.checkpatch: warning for drm/xe: Create and use SoC WA infrastructure Patchwork
2025-06-20 21:57 ` ✓ CI.KUnit: success " Patchwork
2025-06-20 22:58 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-06-23 16:13 ` Matt Atwood
2025-06-21 6:05 ` ✗ Xe.CI.Full: " Patchwork
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