[PATCH 0/5] Fix Adaptive Sync SDP for Panel Replay

[PATCH 0/5] Fix Adaptive Sync SDP for Panel Replay

[Ankit Nautiyal]

Enable Adaptive Sync SDP always when Panel replay + auxless ALPM is
supported. Ensure AS SDP is sent on line which is within the SCL +
guardband region.

This series is in continuation from discussions in [1] [2].

[1] https://lore.kernel.org/all/1b8c6c6de1e5fe0db83e6ae942dfee7e6f950767.camel@intel.com/
[2] https://lore.kernel.org/all/aPtqdAxDwiuQZbrn@intel.com/

Rev2:
Add few fixes in AS_SDP and Lobf.

Ankit Nautiyal (4):
  drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP
  drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is
    supported
  drm/i915/alpm: Compute LOBF late after guardband is already determined
  drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines

Jouni Högander (1):
  drm/i915/display: Take into account AS SDP in
    intel_dp_sdp_min_guardband

 drivers/gpu/drm/i915/display/intel_alpm.c | 41 ++++++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_alpm.h |  6 ++--
 drivers/gpu/drm/i915/display/intel_dp.c   | 35 ++++++++++++++-----
 3 files changed, 62 insertions(+), 20 deletions(-)

-- 
2.45.2

[PATCH 1/5] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ankit Nautiyal]

Correct the bit-shift logic to properly readback the 10 bit target_rr from
DB3 and DB4.

Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 475518b4048b..c013eb2e18a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4996,7 +4996,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
-	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)(sdp->db[4] & 0x3) << 8);
 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
-- 
2.45.2

[PATCH 2/5] drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is supported

[Ankit Nautiyal]

Adaptive Sync SDP is required when Panel replay is active and for
supporting VRR on PCON.

Since VRR on PCON still needs some effort, enable adaptive sync SDP only
when Panel replay with ALPM-Auxless is supported.

Set the AS_SDP mode for Fixed Vtotal mode for fixed refresh rate case.

v2: Remove redundant target_rr assignments. (Ville)

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c013eb2e18a1..b5b855453845 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2934,7 +2934,15 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
 
-	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
+	if (!intel_dp->as_sdp_supported)
+		return;
+
+	/*
+	 * Support Adaptive-Sync SDP only for PR+AUX-less ALPM for now.
+	 * It can be enabled for PCON + VRR, but that is currently not supported.
+	 */
+	if (!CAN_PANEL_REPLAY(intel_dp) ||
+	    !intel_alpm_aux_less_wake_supported(intel_dp))
 		return;
 
 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
@@ -2948,9 +2956,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
 		as_sdp->target_rr_divider = true;
-	} else {
+	} else if (crtc_state->vrr.enable) {
 		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
-		as_sdp->target_rr = 0;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
 	}
 }
 
-- 
2.45.2

[PATCH 3/5] drm/i915/display: Take into account AS SDP in intel_dp_sdp_min_guardband

[Ankit Nautiyal]

From: Jouni Högander <jouni.hogander@intel.com>

We started seeing "[drm] *ERROR* Timed out waiting PSR idle state" after
taking optimized guardband into use. These are seen because VSC SDPs are
sent on same line as AS SDPs when AS SDP is enabled. AS SDP is sent on line
configured in EMP_AS_SDP_TL register. We are configuring
crtc_state->vrr.vsync_start into that register.

Fix this by ensuring AS SDP is sent on line which is within
guardband. From the bspec:

EMP_AS_SDP_TL < SCL + Guardband

v2: check HAS_AS_SDP
v3: Remove assume_all_enabled check for AS_SDP. (Ville)

Bspec: 71197
Fixes: 52ecd48b8d3f ("drm/i915/dp: Add helper to get min sdp guardband")
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (#v2)
---
 drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b5b855453845..d68a2cde15f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7032,7 +7032,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 }
 
 static
-int intel_dp_get_lines_for_sdp(u32 type)
+int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type)
 {
 	switch (type) {
 	case DP_SDP_VSC_EXT_VESA:
@@ -7042,6 +7042,8 @@ int intel_dp_get_lines_for_sdp(u32 type)
 		return 8;
 	case DP_SDP_PPS:
 		return 7;
+	case DP_SDP_ADAPTIVE_SYNC:
+		return crtc_state->vrr.vsync_start + 1;
 	default:
 		break;
 	}
@@ -7058,11 +7060,18 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 	    crtc_state->infoframes.enable &
 	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
 		sdp_guardband = max(sdp_guardband,
-				    intel_dp_get_lines_for_sdp(HDMI_PACKET_TYPE_GAMUT_METADATA));
+				    intel_dp_get_lines_for_sdp(crtc_state,
+							       HDMI_PACKET_TYPE_GAMUT_METADATA));
 
 	if (assume_all_enabled ||
 	    crtc_state->dsc.compression_enable)
-		sdp_guardband = max(sdp_guardband, intel_dp_get_lines_for_sdp(DP_SDP_PPS));
+		sdp_guardband = max(sdp_guardband,
+				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
+
+	if (crtc_state->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
+		sdp_guardband = max(sdp_guardband,
+				    intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
 
 	return sdp_guardband;
 }
-- 
2.45.2

[PATCH 4/5] drm/i915/alpm: Compute LOBF late after guardband is already determined

[Ankit Nautiyal]

Currently intel_alpm_lobf_compute_config() tries to account for
guardband +SCL requirements during encoder->compute_config() phase,
even before guardband is computed.
Also, LOBF depends on crtc_state->has_psr which can be modified in
encoder->compute_config_late().

Move the  lobf computation in encoder->compute_config_late() phase after
the guardband and the final state of crtc_state->has_psr are already
computed.

Use crtc_state->vrr.guardband and crtc_state->set_context_latency for
the computation and add more documentation for the dependency of first
sdp position, guardband, set context latency and wake lines.

Bspec:71041
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 28 +++++++++++++++--------
 drivers/gpu/drm/i915/display/intel_alpm.h |  6 ++---
 drivers/gpu/drm/i915/display/intel_dp.c   |  3 ++-
 3 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 6372f533f65b..1c240dd8d668 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -248,14 +248,13 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 	return true;
 }
 
-void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state,
-				    struct drm_connector_state *conn_state)
+void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state,
+					 struct drm_connector_state *conn_state)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int waketime_in_lines, first_sdp_position;
-	int context_latency, guardband;
 
 	if (intel_dp->alpm.lobf_disable_debug) {
 		drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
@@ -288,17 +287,28 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (!intel_alpm_compute_params(intel_dp, crtc_state))
 		return;
 
-	context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
-	guardband = adjusted_mode->crtc_vtotal -
-		    adjusted_mode->crtc_vdisplay - context_latency;
+	/*
+	 * LOBF can only be enabled if the time from the start of the SCL+Guardband
+	 * window to the position of the first SDP is greater than the time it takes
+	 * to wake the main link.
+	 *
+	 * Position of first sdp : vsync_start
+	 * start of scl + guardband : vtotal - (scl + guardband)
+	 * time in lines to wake main link : waketime_in_lines
+	 *
+	 * Position of first sdp - start of (scl + guardband) > time in lines to wake main link
+	 * vsync_start - (vtotal - (scl + guardband)) > waketime_in_lines
+	 * vsync_start - vtotal + scl + guardband > waketime_in_lines
+	 * scl + guardband > waketime_in_lines + (vtotal - vsync_start)
+	 */
 	first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
 	if (intel_alpm_aux_less_wake_supported(intel_dp))
 		waketime_in_lines = crtc_state->alpm_state.io_wake_lines;
 	else
 		waketime_in_lines = crtc_state->alpm_state.aux_less_wake_lines;
 
-	crtc_state->has_lobf = (context_latency + guardband) >
-		(first_sdp_position + waketime_in_lines);
+	crtc_state->has_lobf = (crtc_state->set_context_latency + crtc_state->vrr.guardband) >
+			       (first_sdp_position + waketime_in_lines);
 }
 
 static void lnl_alpm_configure(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 53599b464dea..138d56a499ee 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -18,9 +18,9 @@ struct intel_crtc;
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
-void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state,
-				    struct drm_connector_state *conn_state);
+void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
+					 struct intel_crtc_state *crtc_state,
+					 struct drm_connector_state *conn_state);
 void intel_alpm_configure(struct intel_dp *intel_dp,
 			  const struct intel_crtc_state *crtc_state);
 void intel_alpm_enable_sink(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d68a2cde15f1..176b0efb40f1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -3424,7 +3424,6 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_dp_compute_as_sdp(intel_dp, pipe_config);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
-	intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state);
 	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
 	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
@@ -7028,6 +7027,8 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
+	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state, conn_state);
+
 	return 0;
 }
 
-- 
2.45.2

[PATCH 5/5] drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines

[Ankit Nautiyal]

LOBF must be disabled if the number of lines within Window 1 is not greater
than ALPM_CTL[ALPM Entry Check]

Bspec:71041
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 1c240dd8d668..58cd0d2a4395 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -255,6 +255,7 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 	int waketime_in_lines, first_sdp_position;
+	int window1;
 
 	if (intel_dp->alpm.lobf_disable_debug) {
 		drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
@@ -287,6 +288,18 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
 	if (!intel_alpm_compute_params(intel_dp, crtc_state))
 		return;
 
+	/*
+	 * LOBF must be disabled if the number of lines within Window 1 is not
+	 * greater than ALPM_CTL[ALPM Entry Check]
+	 */
+	window1 = adjusted_mode->crtc_vtotal -
+		  (adjusted_mode->crtc_vdisplay +
+		   crtc_state->vrr.guardband +
+		   crtc_state->set_context_latency);
+
+	if (window1 <= crtc_state->alpm_state.check_entry_lines)
+		return;
+
 	/*
 	 * LOBF can only be enabled if the time from the start of the SCL+Guardband
 	 * window to the position of the first SDP is greater than the time it takes
-- 
2.45.2

Re: [PATCH 1/5] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Ville Syrjälä]

On Thu, Oct 30, 2025 at 10:47:51AM +0530, Ankit Nautiyal wrote:
> Correct the bit-shift logic to properly readback the 10 bit target_rr from
> DB3 and DB4.
> 
> Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
> Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 475518b4048b..c013eb2e18a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4996,7 +4996,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>  	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
>  	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
>  	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
> -	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
> +	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)(sdp->db[4] & 0x3) << 8);

The (u64) casts are completely pointless. And I would try to write this
in a styple that is more consistent with the vtotal assignment right
above it. Eg.: target_rr = ((db[4] & 0x3) << 8) | db[3];

>  	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
>  
>  	return 0;
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 2/5] drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is supported

[Ville Syrjälä]

On Thu, Oct 30, 2025 at 10:47:52AM +0530, Ankit Nautiyal wrote:
> Adaptive Sync SDP is required when Panel replay is active and for
> supporting VRR on PCON.
> 
> Since VRR on PCON still needs some effort, enable adaptive sync SDP only
> when Panel replay with ALPM-Auxless is supported.

AFAICS we don't actually check for PCON vs. not anywhere, and thus
we are in fact allowing VRR with PCON. Or am I missign some check
somewhere?

> 
> Set the AS_SDP mode for Fixed Vtotal mode for fixed refresh rate case.
> 
> v2: Remove redundant target_rr assignments. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c013eb2e18a1..b5b855453845 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2934,7 +2934,15 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  
> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
> +	if (!intel_dp->as_sdp_supported)
> +		return;
> +
> +	/*
> +	 * Support Adaptive-Sync SDP only for PR+AUX-less ALPM for now.
> +	 * It can be enabled for PCON + VRR, but that is currently not supported.
> +	 */
> +	if (!CAN_PANEL_REPLAY(intel_dp) ||
> +	    !intel_alpm_aux_less_wake_supported(intel_dp))
>  		return;
>  
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
> @@ -2948,9 +2956,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>  		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>  		as_sdp->target_rr_divider = true;
> -	} else {
> +	} else if (crtc_state->vrr.enable) {
>  		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
> -		as_sdp->target_rr = 0;
> +	} else {
> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>  	}
>  }
>  
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 1/5] drm/i915/dp: Fix readback for target_rr in Adaptive Sync SDP

[Nautiyal, Ankit K]

On 10/30/2025 1:48 PM, Ville Syrjälä wrote:
> On Thu, Oct 30, 2025 at 10:47:51AM +0530, Ankit Nautiyal wrote:
>> Correct the bit-shift logic to properly readback the 10 bit target_rr from
>> DB3 and DB4.
>>
>> Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync SDP")
>> Cc: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
>> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 475518b4048b..c013eb2e18a1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -4996,7 +4996,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
>>   	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
>>   	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
>>   	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
>> -	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
>> +	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)(sdp->db[4] & 0x3) << 8);
> The (u64) casts are completely pointless. And I would try to write this
> in a styple that is more consistent with the vtotal assignment right
> above it. Eg.: target_rr = ((db[4] & 0x3) << 8) | db[3];


Makes sense. Will change this as suggested.


Regards,

Ankit

>
>>   	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
>>   
>>   	return 0;
>> -- 
>> 2.45.2

Re: [PATCH 2/5] drm/i915/dp: Allow AS_SDP only if panel replay + auxless alpm is supported

[Nautiyal, Ankit K]

On 10/30/2025 1:53 PM, Ville Syrjälä wrote:
> On Thu, Oct 30, 2025 at 10:47:52AM +0530, Ankit Nautiyal wrote:
>> Adaptive Sync SDP is required when Panel replay is active and for
>> supporting VRR on PCON.
>>
>> Since VRR on PCON still needs some effort, enable adaptive sync SDP only
>> when Panel replay with ALPM-Auxless is supported.
> AFAICS we don't actually check for PCON vs. not anywhere, and thus
> we are in fact allowing VRR with PCON. Or am I missign some check
> somewhere?

No you are in fact right. I had a patch to avoid vrr on PCON  in 
intel_vrr_is_capable() in the VRR timing generator series, but 
missed/dropped somewhere.

I will add that patch before this change.


Regards,

Ankit

>
>> Set the AS_SDP mode for Fixed Vtotal mode for fixed refresh rate case.
>>
>> v2: Remove redundant target_rr assignments. (Ville)
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++++++---
>>   1 file changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index c013eb2e18a1..b5b855453845 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -2934,7 +2934,15 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   	const struct drm_display_mode *adjusted_mode =
>>   		&crtc_state->hw.adjusted_mode;
>>   
>> -	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
>> +	if (!intel_dp->as_sdp_supported)
>> +		return;
>> +
>> +	/*
>> +	 * Support Adaptive-Sync SDP only for PR+AUX-less ALPM for now.
>> +	 * It can be enabled for PCON + VRR, but that is currently not supported.
>> +	 */
>> +	if (!CAN_PANEL_REPLAY(intel_dp) ||
>> +	    !intel_alpm_aux_less_wake_supported(intel_dp))
>>   		return;
>>   
>>   	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
>> @@ -2948,9 +2956,10 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>>   		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
>>   		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
>>   		as_sdp->target_rr_divider = true;
>> -	} else {
>> +	} else if (crtc_state->vrr.enable) {
>>   		as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
>> -		as_sdp->target_rr = 0;
>> +	} else {
>> +		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
>>   	}
>>   }
>>   
>> -- 
>> 2.45.2

Re: [PATCH 5/5] drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines

[Ville Syrjälä]

On Thu, Oct 30, 2025 at 10:47:55AM +0530, Ankit Nautiyal wrote:
> LOBF must be disabled if the number of lines within Window 1 is not greater
> than ALPM_CTL[ALPM Entry Check]
> 
> Bspec:71041
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 1c240dd8d668..58cd0d2a4395 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -255,6 +255,7 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>  	int waketime_in_lines, first_sdp_position;
> +	int window1;
>  
>  	if (intel_dp->alpm.lobf_disable_debug) {
>  		drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
> @@ -287,6 +288,18 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
>  	if (!intel_alpm_compute_params(intel_dp, crtc_state))
>  		return;
>  
> +	/*
> +	 * LOBF must be disabled if the number of lines within Window 1 is not
> +	 * greater than ALPM_CTL[ALPM Entry Check]
> +	 */
> +	window1 = adjusted_mode->crtc_vtotal -
> +		  (adjusted_mode->crtc_vdisplay +
> +		   crtc_state->vrr.guardband +
> +		   crtc_state->set_context_latency);

vdisplay+guardband+scl isn't a value that means anything.
So the extra parentheses make this rather confusing.

This also doesn't account for the case where SCL would start already
in vertical active on PTL+. I know we don't do that currently, but we
should probably write this in a way that accounts for that so that we
don't have to rewrite this yet again.

Apparently this lobf stuff depends on actually having a window1,
which means it can only be used if we're using the VRR timing generator
with an optimized guardband. That means it never did anything (or it
did things wrong) until you enabled the optimized guardband.

It sort of looks like intel_alpm_{pre,post}_plane_update() might
allow us to enable this even for the 'vrr.enable==true &&
always_use_vrr_tg()==false' case. Either that or we should just
enable it for the always_use_vrr_tg()==true case. Whatever the
case, we definitely seem to be missing some kind of a VRR check
here.

I'm also 90% sure that alpm pre/post plane stuff isn't handling
DRRS/LRR/etc correctly...

> +
> +	if (window1 <= crtc_state->alpm_state.check_entry_lines)
> +		return;
> +
>  	/*
>  	 * LOBF can only be enabled if the time from the start of the SCL+Guardband
>  	 * window to the position of the first SDP is greater than the time it takes
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Re: [PATCH 5/5] drm/i915/alpm: Allow LOBF only if window1 > alpm check_entry lines

[Nautiyal, Ankit K]

On 10/30/2025 4:05 PM, Ville Syrjälä wrote:
> On Thu, Oct 30, 2025 at 10:47:55AM +0530, Ankit Nautiyal wrote:
>> LOBF must be disabled if the number of lines within Window 1 is not greater
>> than ALPM_CTL[ALPM Entry Check]
>>
>> Bspec:71041
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_alpm.c | 13 +++++++++++++
>>   1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
>> index 1c240dd8d668..58cd0d2a4395 100644
>> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
>> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
>> @@ -255,6 +255,7 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
>>   	struct intel_display *display = to_intel_display(intel_dp);
>>   	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>   	int waketime_in_lines, first_sdp_position;
>> +	int window1;
>>   
>>   	if (intel_dp->alpm.lobf_disable_debug) {
>>   		drm_dbg_kms(display->drm, "LOBF is disabled by debug flag\n");
>> @@ -287,6 +288,18 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
>>   	if (!intel_alpm_compute_params(intel_dp, crtc_state))
>>   		return;
>>   
>> +	/*
>> +	 * LOBF must be disabled if the number of lines within Window 1 is not
>> +	 * greater than ALPM_CTL[ALPM Entry Check]
>> +	 */
>> +	window1 = adjusted_mode->crtc_vtotal -
>> +		  (adjusted_mode->crtc_vdisplay +
>> +		   crtc_state->vrr.guardband +
>> +		   crtc_state->set_context_latency);
> vdisplay+guardband+scl isn't a value that means anything.
> So the extra parentheses make this rather confusing.

Yes true, vdisplay+guardband+scl doesnt make any sense in itself. What I 
intended was:

vblank = (adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay);
window1 = vblank - (crtc_state->vrr.guardband + 
crtc_state->set_context_latency);

>
> This also doesn't account for the case where SCL would start already
> in vertical active on PTL+. I know we don't do that currently, but we
> should probably write this in a way that accounts for that so that we
> don't have to rewrite this yet again.

Fair point. Then something like:

vblank = (adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay);

scl_gb_region = min(vblank, crtc_state->vrr.guardband + 
crtc_state->set_context_latency)
window1 = vblank - scl_gb_region;

>
> Apparently this lobf stuff depends on actually having a window1,
> which means it can only be used if we're using the VRR timing generator
> with an optimized guardband. That means it never did anything (or it
> did things wrong) until you enabled the optimized guardband.

Yeah right. Without optimized guardband, window1 would be always 0 so no 
scope to use this.


>
> It sort of looks like intel_alpm_{pre,post}_plane_update() might
> allow us to enable this even for the 'vrr.enable==true &&
> always_use_vrr_tg()==false' case. Either that or we should just
> enable it for the always_use_vrr_tg()==true case. Whatever the
> case, we definitely seem to be missing some kind of a VRR check
> here.

I was just short of adding check for always_use_vrr_tg() && 
intel_vrr_is_fixed_rr()

Bspec says that lobf can be enabled only with fixed refresh rate and 
mentions flipline = vmin =vmax.

I was not sure if its implicit to enable this only with VRR TG and not 
with legacy timing generator.

Makes sense to replace the existing check with for flipline=vmin=vmax with:

intel_vrr_always_use_vrr_tg() && intel_vrr_is_fixed_rr()


>
> I'm also 90% sure that alpm pre/post plane stuff isn't handling
> DRRS/LRR/etc correctly...

Hmm... ｡oO( need to check how DRRS and LRR interact with ALPM pre/post 
plane handling... )


Regards,

Ankit

>
>> +
>> +	if (window1 <= crtc_state->alpm_state.check_entry_lines)
>> +		return;
>> +
>>   	/*
>>   	 * LOBF can only be enabled if the time from the start of the SCL+Guardband
>>   	 * window to the position of the first SDP is greater than the time it takes
>> -- 
>> 2.45.2