Re: [PATCH 01/16] drm/xe/multi_queue: Add multi_queue_enable_mask to gt information

[Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>]

On Sat, Nov 01, 2025 at 05:01:44PM -0700, Matthew Brost wrote:
>On Fri, Oct 31, 2025 at 11:29:21AM -0700, Niranjana Vishwanathapura wrote:
>> Add multi_queue_enable_mask field to the gt information structure
>> which is bitmask of all engine classes with multi queue support
>> enabled.
>>
>> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_debugfs.c   | 2 ++
>>  drivers/gpu/drm/xe/xe_gt_types.h  | 5 +++++
>>  drivers/gpu/drm/xe/xe_pci.c       | 1 +
>>  drivers/gpu/drm/xe/xe_pci_types.h | 1 +
>>  4 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
>> index e91da9589c5f..34460d7ef71c 100644
>> --- a/drivers/gpu/drm/xe/xe_debugfs.c
>> +++ b/drivers/gpu/drm/xe/xe_debugfs.c
>> @@ -93,6 +93,8 @@ static int info(struct seq_file *m, void *data)
>>  			   xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));
>>  		drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,
>>  			   gt->info.engine_mask);
>> +		drm_printf(&p, "gt%d multi_queue_enable_mask 0x%x\n", id,
>> +			   gt->info.multi_queue_enable_mask);
>>  	}
>>
>>  	xe_pm_runtime_put(xe);
>> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>> index 0b525643a048..4a18bf772b22 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_types.h
>> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
>> @@ -140,6 +140,11 @@ struct xe_gt {
>>  		u64 engine_mask;
>>  		/** @info.gmdid: raw GMD_ID value from hardware */
>>  		u32 gmdid;
>> +		/**
>> +		 * @multi_queue_enable_mask: Bitmask of engine classes with
>> +		 * multi queue support enabled.
>> +		 */
>> +		u16 multi_queue_enable_mask;
>
>s/multi_queue_enable_mask/multi_queue_class_enable_mask ?
>

Ok, will rename it as 'multi_queue_engine_class_mask'.

Niranjana

>Matt
>
>>  		/** @info.id: Unique ID of this GT within the PCI Device */
>>  		u8 id;
>>  		/** @info.has_indirect_ring_state: GT has indirect ring state support */
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 6e59642e7820..b5eaf0fc105c 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -754,6 +754,7 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
>>  	gt->info.type = XE_GT_TYPE_MAIN;
>>  	gt->info.id = tile->id * xe->info.max_gt_per_tile;
>>  	gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
>> +	gt->info.multi_queue_enable_mask = graphics_desc->multi_queue_enable_mask;
>>  	gt->info.engine_mask = graphics_desc->hw_engine_mask;
>>
>>  	/*
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>> index 9892c063a9c5..77e09a53da64 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -58,6 +58,7 @@ struct xe_device_desc {
>>
>>  struct xe_graphics_desc {
>>  	u64 hw_engine_mask;	/* hardware engines provided by graphics IP */
>> +	u16 multi_queue_enable_mask; /* bitmask of engine classes which support multi queue */
>>
>>  	u8 has_asid:1;
>>  	u8 has_atomic_enable_pte_bit:1;
>> --
>> 2.43.0
>>