[PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework

[PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Mika Kahola]

This is v2 of [1], with the following changes

- commit message updates
- Use of BUILD_BUGON() wherever possible instead of WARN_ON()

[1] https://lore.kernel.org/intel-gfx/20251031103549.173208-1-mika.kahola@intel.com/

Imre Deak (15):
  drm/i915/cx0: Factor out C10 msgbus access start/end helpers
  drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
  drm/i915/cx0: Sanitize calculating C20 PLL state from tables
  drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
  drm/i915/cx0: Move definition of Cx0 PHY functions earlier
  drm/i915/cx0: Add macro to get DDI port width from a register value
  drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
  drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
  drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
  drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
  drm/i915/cx0: Determine Cx0 PLL port clock from PLL state
  drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
  drm/i915/cx0: Print additional Cx0 PLL HW state
  drm/i915/cx0: PLL verify debug state print
  drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

Mika Kahola (17):
  drm/i915/cx0: Rename TBT functions to be ICL specific
  drm/i915/cx0: Remove state verification
  drm/i915/cx0: Add PLL information for MTL+
  drm/i915/cx0: Update C10/C20 state calculation
  drm/i915/cx0: Compute plls for MTL+ platform
  drm/i915/cx0: Add MTL+ .get_dplls hook
  drm/i915/cx0: Add MTL+ .put_dplls hook
  drm/i915/cx0: Add MTL+ .update_active_dpll hook
  drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
  drm/i915/cx0: Add MTL+ .dump_hw_state hook
  drm/i915/cx0: Add .compare_hw_state hook
  drm/i915/cx0: Add MTL+ .get_hw_state hook
  drm/i915/cx0: Add MTL+ .get_freq hook
  drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
  drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
  drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
  drm/i915/cx0: Enable dpll framework for MTL+

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 870 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  29 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  87 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  30 -
 .../gpu/drm/i915/display/intel_display_regs.h |   7 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  24 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 315 ++++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   7 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |   4 +-
 .../drm/i915/display/intel_modeset_verify.c   |   1 -
 10 files changed, 893 insertions(+), 481 deletions(-)

-- 
2.34.1

[PATCH v2 01/32] drm/i915/cx0: Rename TBT functions to be ICL specific

[Mika Kahola]

Rename pll functions to include ICL platform as these are
used from ICL onwards.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9c7cf03cf022..8c345e1bdd94 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3753,9 +3753,9 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
 }
 
-static bool tbt_pll_get_hw_state(struct intel_display *display,
-				 struct intel_dpll *pll,
-				 struct intel_dpll_hw_state *dpll_hw_state)
+static bool icl_tbt_pll_get_hw_state(struct intel_display *display,
+				     struct intel_dpll *pll,
+				     struct intel_dpll_hw_state *dpll_hw_state)
 {
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
 }
@@ -3984,9 +3984,9 @@ static void combo_pll_enable(struct intel_display *display,
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void tbt_pll_enable(struct intel_display *display,
-			   struct intel_dpll *pll,
-			   const struct intel_dpll_hw_state *dpll_hw_state)
+static void icl_tbt_pll_enable(struct intel_display *display,
+			       struct intel_dpll *pll,
+			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 
@@ -4069,8 +4069,8 @@ static void combo_pll_disable(struct intel_display *display,
 	icl_pll_disable(display, pll, enable_reg);
 }
 
-static void tbt_pll_disable(struct intel_display *display,
-			    struct intel_dpll *pll)
+static void icl_tbt_pll_disable(struct intel_display *display,
+				struct intel_dpll *pll)
 {
 	icl_pll_disable(display, pll, TBT_PLL_ENABLE);
 }
@@ -4142,10 +4142,10 @@ static const struct intel_dpll_funcs combo_pll_funcs = {
 	.get_freq = icl_ddi_combo_pll_get_freq,
 };
 
-static const struct intel_dpll_funcs tbt_pll_funcs = {
-	.enable = tbt_pll_enable,
-	.disable = tbt_pll_disable,
-	.get_hw_state = tbt_pll_get_hw_state,
+static const struct intel_dpll_funcs icl_tbt_pll_funcs = {
+	.enable = icl_tbt_pll_enable,
+	.disable = icl_tbt_pll_disable,
+	.get_hw_state = icl_tbt_pll_get_hw_state,
 	.get_freq = icl_ddi_tbt_pll_get_freq,
 };
 
@@ -4159,7 +4159,7 @@ static const struct intel_dpll_funcs mg_pll_funcs = {
 static const struct dpll_info icl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4207,7 +4207,7 @@ static const struct intel_dpll_funcs dkl_pll_funcs = {
 static const struct dpll_info tgl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4285,7 +4285,7 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
 static const struct dpll_info adlp_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
-- 
2.34.1

[PATCH v2 02/32] drm/i915/cx0: Factor out C10 msgbus access start/end helpers

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Factor out functions to begin and complete C10 PHY programming
sequences to make the code more concise.

v2: Rename msgbus_update_config() to more descriptive
    msg_bus_access_commit() (Jani)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 62 +++++++++++---------
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d98b4cf6b60e..e130c96d0018 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -444,6 +444,31 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static void intel_c10_msgbus_access_begin(struct intel_encoder *encoder,
+					  u8 lane_mask)
+{
+	if (!intel_encoder_is_c10phy(encoder))
+		return;
+
+	intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1),
+		      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+}
+
+static void intel_c10_msgbus_access_commit(struct intel_encoder *encoder,
+					   u8 lane_mask, bool master_lane)
+{
+	u8 val = C10_VDR_CTRL_UPDATE_CFG;
+
+	if (!intel_encoder_is_c10phy(encoder))
+		return;
+
+	if (master_lane)
+		val |= C10_VDR_CTRL_MASTER_LANE;
+
+	intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1),
+		      0, val, MB_WRITE_COMMITTED);
+}
+
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state)
 {
@@ -467,9 +492,9 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 		return;
 	}
 
+	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
+
 	if (intel_encoder_is_c10phy(encoder)) {
-		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
-			      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3),
 			      C10_CMN3_TXVBOOST_MASK,
 			      C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
@@ -508,9 +533,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
 		      MB_WRITE_COMMITTED);
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
-			      0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
@@ -2114,9 +2137,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	 * According to C10 VDR Register programming Sequence we need
 	 * to do this to read PHY internal registers from MsgBus.
 	 */
-	intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1),
-		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
-		      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, lane);
 
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
 		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
@@ -2135,9 +2156,7 @@ static void intel_c10_pll_program(struct intel_display *display,
 {
 	int i;
 
-	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
-		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
-		      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES);
 
 	/* Program the pll values only for the master lane */
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
@@ -2152,9 +2171,8 @@ static void intel_c10_pll_program(struct intel_display *display,
 	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,
 		      C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,
 		      MB_WRITE_COMMITTED);
-	intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
-		      0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
-		      MB_WRITE_COMMITTED);
+
+	intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);
 }
 
 static void intel_c10pll_dump_hw_state(struct intel_display *display,
@@ -2938,11 +2956,7 @@ static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_c
 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask,
-			      PHY_C10_VDR_CONTROL(1), 0,
-			      C10_VDR_CTRL_MSGBUS_ACCESS,
-			      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
 
 	if (lane_reversal)
 		disables = REG_GENMASK8(3, 0) >> lane_count;
@@ -2967,11 +2981,7 @@ static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_c
 			      MB_WRITE_COMMITTED);
 	}
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask,
-			      PHY_C10_VDR_CONTROL(1), 0,
-			      C10_VDR_CTRL_UPDATE_CFG,
-			      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false);
 }
 
 static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)
@@ -3236,9 +3246,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,
-			      C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
 
 	for (i = 0; i < 4; i++) {
 		int tx = i % 2 + 1;
-- 
2.34.1

[PATCH v2 03/32] drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Sanitize setting the Cx0 PLL use_c10 flag during state computation and
HW readout, making sure they happen the same way in the
intel_c{10,20}pll_calc_state() and intel_c{10,20}pll_readout_hw_state()
functions.

Follow-up changes will add more state computation/HW readout, this
change prepares for those as well.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 23 ++++++++++++--------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e130c96d0018..93b18dc49ee5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2125,12 +2125,15 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
 					const struct intel_c10pll_state *pll_state);
 
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
-					  struct intel_c10pll_state *pll_state)
+					  struct intel_cx0pll_state *cx0pll_state)
 {
+	struct intel_c10pll_state *pll_state = &cx0pll_state->c10;
 	u8 lane = INTEL_CX0_LANE0;
 	intel_wakeref_t wakeref;
 	int i;
 
+	cx0pll_state->use_c10 = true;
+
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
 	/*
@@ -2356,6 +2359,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	const struct intel_c20pll_state * const *tables;
 	int i;
 
+	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
+
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
@@ -2372,7 +2377,6 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 			intel_cx0pll_update_ssc(encoder,
 						&crtc_state->dpll_hw_state.cx0pll,
 						intel_crtc_has_dp_encoder(crtc_state));
-			crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
 			return 0;
 		}
 	}
@@ -2439,13 +2443,16 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
 }
 
 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
-					  struct intel_c20pll_state *pll_state)
+					  struct intel_cx0pll_state *cx0pll_state)
 {
+	struct intel_c20pll_state *pll_state = &cx0pll_state->c20;
 	struct intel_display *display = to_intel_display(encoder);
 	bool cntx;
 	intel_wakeref_t wakeref;
 	int i;
 
+	cx0pll_state->use_c10 = false;
+
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
 	/* 1. Read current context selection */
@@ -3444,12 +3451,10 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 	if (pll_state->tbt_mode)
 		return;
 
-	if (intel_encoder_is_c10phy(encoder)) {
-		intel_c10pll_readout_hw_state(encoder, &pll_state->c10);
-		pll_state->use_c10 = true;
-	} else {
-		intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
-	}
+	if (intel_encoder_is_c10phy(encoder))
+		intel_c10pll_readout_hw_state(encoder, pll_state);
+	else
+		intel_c20pll_readout_hw_state(encoder, pll_state);
 }
 
 static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
-- 
2.34.1

[PATCH v2 04/32] drm/i915/cx0: Sanitize calculating C20 PLL state from tables

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

A follow up change adds a computation for the C20 PLL VDR state, which
is common to both the HDMI algorithmic and DP/HDMI table based method.
To prepare for that streamline the code. The C10 counterpart would
benefit from the same change, leave that for later adding a TODO
comment.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++++++------
 1 file changed, 47 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 93b18dc49ee5..a1f2272fed14 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2072,6 +2072,10 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 		pll_state->c10.pll[i] = 0;
 }
 
+/*
+ * TODO: Convert the following to align with intel_c20pll_find_table() and
+ * intel_c20pll_calc_state_from_table().
+ */
 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 					      const struct intel_c10pll_state * const *tables,
 					      bool is_dp, int port_clock,
@@ -2325,7 +2329,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
 }
 
 static const struct intel_c20pll_state * const *
-intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
+intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -2353,35 +2357,57 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
-static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
-				   struct intel_encoder *encoder)
+static const struct intel_c20pll_state *
+intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
+			 struct intel_encoder *encoder)
 {
 	const struct intel_c20pll_state * const *tables;
 	int i;
 
-	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
-
-	/* try computed C20 HDMI tables before using consolidated tables */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
-		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
-			return 0;
-	}
-
 	tables = intel_c20_pll_tables_get(crtc_state, encoder);
 	if (!tables)
+		return NULL;
+
+	for (i = 0; tables[i]; i++)
+		if (crtc_state->port_clock == tables[i]->clock)
+			return tables[i];
+
+	return NULL;
+}
+
+static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
+					      struct intel_encoder *encoder)
+{
+	const struct intel_c20pll_state *table;
+
+	table = intel_c20_pll_find_table(crtc_state, encoder);
+	if (!table)
 		return -EINVAL;
 
-	for (i = 0; tables[i]; i++) {
-		if (crtc_state->port_clock == tables[i]->clock) {
-			crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
-			intel_cx0pll_update_ssc(encoder,
-						&crtc_state->dpll_hw_state.cx0pll,
-						intel_crtc_has_dp_encoder(crtc_state));
-			return 0;
-		}
-	}
+	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
 
-	return -EINVAL;
+	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
+				intel_crtc_has_dp_encoder(crtc_state));
+
+	return 0;
+}
+
+static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
+				   struct intel_encoder *encoder)
+{
+	int err = -ENOENT;
+
+	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
+
+	/* try computed C20 HDMI tables before using consolidated tables */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		/* TODO: Update SSC state for HDMI as well */
+		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
+
+	if (err)
+		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
+
+	return err;
 }
 
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
-- 
2.34.1

[PATCH v2 05/32] drm/i915/cx0: Track the C20 PHY VDR state in the PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
enable hook, so prepare here for the conversion to use the PLL manager
for Cx0 PHY PLLs by tracking the DP/HDMI mode in the PLL state.

This change has the advantage, that the VDR HW/SW state can be verified
now.

A follow up change will convert the PLL enable function to retrieve the
DP/HDMI mode parameter from the PLL state.

This also allows dropping the is_dp and port clock params from the
intel_c20_pll_program() function, since it can retrieve these now from
the PLL state.

v2: Fix comment to under same multicomment line (Suraj)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 119 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   5 +
 2 files changed, 92 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a1f2272fed14..fd0409565c68 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2357,6 +2357,75 @@ intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
+static u8 intel_c20_get_dp_rate(u32 clock);
+static u8 intel_c20_get_hdmi_rate(u32 clock);
+static int intel_get_c20_custom_width(u32 clock, bool dp);
+
+static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool is_dp,
+				      int port_clock)
+{
+	vdr->custom_width = intel_get_c20_custom_width(port_clock, is_dp);
+
+	vdr->serdes_rate = 0;
+	vdr->hdmi_rate = 0;
+
+	if (is_dp) {
+		vdr->serdes_rate = PHY_C20_IS_DP |
+				   PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
+	} else {
+		if (intel_hdmi_is_frl(port_clock))
+			vdr->serdes_rate = PHY_C20_IS_HDMI_FRL;
+
+		vdr->hdmi_rate = intel_c20_get_hdmi_rate(port_clock);
+	}
+}
+
+#define PHY_C20_SERDES_RATE_MASK	(PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL)
+
+static void intel_c20_readout_vdr_params(struct intel_encoder *encoder,
+					 struct intel_c20pll_vdr_state *vdr, bool *cntx)
+{
+	u8 serdes;
+
+	serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE);
+	*cntx = serdes & PHY_C20_CONTEXT_TOGGLE;
+
+	vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) &
+			    PHY_C20_CUSTOM_WIDTH_MASK;
+
+	vdr->serdes_rate = serdes & PHY_C20_SERDES_RATE_MASK;
+	if (!(vdr->serdes_rate & PHY_C20_IS_DP))
+		vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) &
+				 PHY_C20_HDMI_RATE_MASK;
+	else
+		vdr->hdmi_rate = 0;
+}
+
+static void intel_c20_program_vdr_params(struct intel_encoder *encoder,
+					 const struct intel_c20pll_vdr_state *vdr,
+					 u8 owned_lane_mask)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	drm_WARN_ON(display->drm, vdr->custom_width & ~PHY_C20_CUSTOM_WIDTH_MASK);
+	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
+		      PHY_C20_CUSTOM_WIDTH_MASK, vdr->custom_width,
+		      MB_WRITE_COMMITTED);
+
+	drm_WARN_ON(display->drm, vdr->serdes_rate & ~PHY_C20_SERDES_RATE_MASK);
+	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+		      PHY_C20_SERDES_RATE_MASK, vdr->serdes_rate,
+		      MB_WRITE_COMMITTED);
+
+	if (vdr->serdes_rate & PHY_C20_IS_DP)
+		return;
+
+	drm_WARN_ON(display->drm, vdr->hdmi_rate & ~PHY_C20_HDMI_RATE_MASK);
+	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
+		      PHY_C20_HDMI_RATE_MASK, vdr->hdmi_rate,
+		      MB_WRITE_COMMITTED);
+}
+
 static const struct intel_c20pll_state *
 intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
@@ -2395,19 +2464,26 @@ static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat
 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 				   struct intel_encoder *encoder)
 {
+	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	int err = -ENOENT;
 
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
 
 	/* try computed C20 HDMI tables before using consolidated tables */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+	if (!is_dp)
 		/* TODO: Update SSC state for HDMI as well */
 		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
 
 	if (err)
 		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
 
-	return err;
+	if (err)
+		return err;
+
+	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
+				  is_dp, crtc_state->port_clock);
+
+	return 0;
 }
 
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
@@ -2481,8 +2557,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
-	/* 1. Read current context selection */
-	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+	/* 1. Read VDR params and current context selection */
+	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
 
 	/* Read Tx configuration */
 	for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
@@ -2657,11 +2733,9 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
 
 static void intel_c20_pll_program(struct intel_display *display,
 				  struct intel_encoder *encoder,
-				  const struct intel_c20pll_state *pll_state,
-				  bool is_dp, int port_clock)
+				  const struct intel_c20pll_state *pll_state)
 {
 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
-	u8 serdes;
 	bool cntx;
 	int i;
 
@@ -2730,30 +2804,11 @@ static void intel_c20_pll_program(struct intel_display *display,
 		}
 	}
 
-	/* 4. Program custom width to match the link protocol */
-	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
-		      PHY_C20_CUSTOM_WIDTH_MASK,
-		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)),
-		      MB_WRITE_COMMITTED);
-
-	/* 5. For DP or 6. For HDMI */
-	serdes = 0;
-	if (is_dp)
-		serdes = PHY_C20_IS_DP |
-			 PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
-	else if (intel_hdmi_is_frl(port_clock))
-		serdes = PHY_C20_IS_HDMI_FRL;
-
-	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-		      PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL,
-		      serdes,
-		      MB_WRITE_COMMITTED);
-
-	if (!is_dp)
-		intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
-			      PHY_C20_HDMI_RATE_MASK,
-			      intel_c20_get_hdmi_rate(port_clock),
-			      MB_WRITE_COMMITTED);
+	/*
+	 * 4. Program custom width to match the link protocol.
+	 * 5. For DP or 6. For HDMI
+	 */
+	intel_c20_program_vdr_params(encoder, &pll_state->vdr, owned_lane_mask);
 
 	/*
 	 * 7. Write Vendor specific registers to toggle context setting to load
@@ -3077,7 +3132,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	if (intel_encoder_is_c10phy(encoder))
 		intel_c10_pll_program(display, encoder, &pll_state->c10);
 	else
-		intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock);
+		intel_c20_pll_program(display, encoder, &pll_state->c20);
 
 	/*
 	 * 6. Program the enabled and disabled owned PHY lane
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 6183da90b28d..a0238a3e7288 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -255,6 +255,11 @@ struct intel_c20pll_state {
 		u16 mplla[10];
 		u16 mpllb[11];
 	};
+	struct intel_c20pll_vdr_state {
+		u8 custom_width;
+		u8 serdes_rate;
+		u8 hdmi_rate;
+	} vdr;
 };
 
 struct intel_cx0pll_state {
-- 
2.34.1

RE: [PATCH v2 05/32] drm/i915/cx0: Track the C20 PHY VDR state in the PLL state

[Kandpal, Suraj]

> Subject: [PATCH v2 05/32] drm/i915/cx0: Track the C20 PHY VDR state in the
> PLL state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
> mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
> enable hook, so prepare here for the conversion to use the PLL manager for
> Cx0 PHY PLLs by tracking the DP/HDMI mode in the PLL state.
> 
> This change has the advantage, that the VDR HW/SW state can be verified
> now.
> 
> A follow up change will convert the PLL enable function to retrieve the
> DP/HDMI mode parameter from the PLL state.
> 
> This also allows dropping the is_dp and port clock params from the
> intel_c20_pll_program() function, since it can retrieve these now from the
> PLL state.
> 
> v2: Fix comment to under same multicomment line (Suraj)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 119 +++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   5 +
>  2 files changed, 92 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a1f2272fed14..fd0409565c68 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2357,6 +2357,75 @@ intel_c20_pll_tables_get(const struct
> intel_crtc_state *crtc_state,
>  	return NULL;
>  }
> 
> +static u8 intel_c20_get_dp_rate(u32 clock); static u8
> +intel_c20_get_hdmi_rate(u32 clock); static int
> +intel_get_c20_custom_width(u32 clock, bool dp);
> +
> +static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr,
> bool is_dp,
> +				      int port_clock)
> +{
> +	vdr->custom_width = intel_get_c20_custom_width(port_clock,
> is_dp);
> +
> +	vdr->serdes_rate = 0;
> +	vdr->hdmi_rate = 0;
> +
> +	if (is_dp) {
> +		vdr->serdes_rate = PHY_C20_IS_DP |
> +
> PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
> +	} else {
> +		if (intel_hdmi_is_frl(port_clock))
> +			vdr->serdes_rate = PHY_C20_IS_HDMI_FRL;
> +
> +		vdr->hdmi_rate = intel_c20_get_hdmi_rate(port_clock);
> +	}
> +}
> +
> +#define PHY_C20_SERDES_RATE_MASK	(PHY_C20_IS_DP |
> PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL)
> +
> +static void intel_c20_readout_vdr_params(struct intel_encoder *encoder,
> +					 struct intel_c20pll_vdr_state *vdr,
> bool *cntx) {
> +	u8 serdes;
> +
> +	serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE);
> +	*cntx = serdes & PHY_C20_CONTEXT_TOGGLE;
> +
> +	vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_WIDTH) &
> +			    PHY_C20_CUSTOM_WIDTH_MASK;
> +
> +	vdr->serdes_rate = serdes & PHY_C20_SERDES_RATE_MASK;
> +	if (!(vdr->serdes_rate & PHY_C20_IS_DP))
> +		vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_HDMI_RATE) &
> +				 PHY_C20_HDMI_RATE_MASK;
> +	else
> +		vdr->hdmi_rate = 0;
> +}
> +
> +static void intel_c20_program_vdr_params(struct intel_encoder *encoder,
> +					 const struct intel_c20pll_vdr_state
> *vdr,
> +					 u8 owned_lane_mask)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	drm_WARN_ON(display->drm, vdr->custom_width &
> ~PHY_C20_CUSTOM_WIDTH_MASK);
> +	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_WIDTH,
> +		      PHY_C20_CUSTOM_WIDTH_MASK, vdr->custom_width,
> +		      MB_WRITE_COMMITTED);
> +
> +	drm_WARN_ON(display->drm, vdr->serdes_rate &
> ~PHY_C20_SERDES_RATE_MASK);
> +	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> +		      PHY_C20_SERDES_RATE_MASK, vdr->serdes_rate,
> +		      MB_WRITE_COMMITTED);
> +
> +	if (vdr->serdes_rate & PHY_C20_IS_DP)
> +		return;
> +
> +	drm_WARN_ON(display->drm, vdr->hdmi_rate &
> ~PHY_C20_HDMI_RATE_MASK);
> +	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES,
> PHY_C20_VDR_HDMI_RATE,
> +		      PHY_C20_HDMI_RATE_MASK, vdr->hdmi_rate,
> +		      MB_WRITE_COMMITTED);
> +}
> +
>  static const struct intel_c20pll_state *  intel_c20_pll_find_table(const struct
> intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
> @@ -2395,19 +2464,26 @@ static int
> intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat  static int
> intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
>  				   struct intel_encoder *encoder)
>  {
> +	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	int err = -ENOENT;
> 
>  	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> 
>  	/* try computed C20 HDMI tables before using consolidated tables
> */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +	if (!is_dp)
>  		/* TODO: Update SSC state for HDMI as well */
>  		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> 
>  	if (err)
>  		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> 
> -	return err;
> +	if (err)
> +		return err;
> +
> +	intel_c20_calc_vdr_params(&crtc_state-
> >dpll_hw_state.cx0pll.c20.vdr,
> +				  is_dp, crtc_state->port_clock);
> +
> +	return 0;
>  }
> 
>  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, @@ -2481,8
> +2557,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder
> *encoder,
> 
>  	wakeref = intel_cx0_phy_transaction_begin(encoder);
> 
> -	/* 1. Read current context selection */
> -	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> +	/* 1. Read VDR params and current context selection */
> +	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
> 
>  	/* Read Tx configuration */
>  	for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { @@ -2657,11 +2733,9
> @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
> 
>  static void intel_c20_pll_program(struct intel_display *display,
>  				  struct intel_encoder *encoder,
> -				  const struct intel_c20pll_state *pll_state,
> -				  bool is_dp, int port_clock)
> +				  const struct intel_c20pll_state *pll_state)
>  {
>  	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> -	u8 serdes;
>  	bool cntx;
>  	int i;
> 
> @@ -2730,30 +2804,11 @@ static void intel_c20_pll_program(struct
> intel_display *display,
>  		}
>  	}
> 
> -	/* 4. Program custom width to match the link protocol */
> -	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_WIDTH,
> -		      PHY_C20_CUSTOM_WIDTH_MASK,
> -
> PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)),
> -		      MB_WRITE_COMMITTED);
> -
> -	/* 5. For DP or 6. For HDMI */
> -	serdes = 0;
> -	if (is_dp)
> -		serdes = PHY_C20_IS_DP |
> -
> PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
> -	else if (intel_hdmi_is_frl(port_clock))
> -		serdes = PHY_C20_IS_HDMI_FRL;
> -
> -	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> -		      PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK |
> PHY_C20_IS_HDMI_FRL,
> -		      serdes,
> -		      MB_WRITE_COMMITTED);
> -
> -	if (!is_dp)
> -		intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES,
> PHY_C20_VDR_HDMI_RATE,
> -			      PHY_C20_HDMI_RATE_MASK,
> -			      intel_c20_get_hdmi_rate(port_clock),
> -			      MB_WRITE_COMMITTED);
> +	/*
> +	 * 4. Program custom width to match the link protocol.
> +	 * 5. For DP or 6. For HDMI
> +	 */
> +	intel_c20_program_vdr_params(encoder, &pll_state->vdr,
> +owned_lane_mask);
> 
>  	/*
>  	 * 7. Write Vendor specific registers to toggle context setting to load
> @@ -3077,7 +3132,7 @@ static void __intel_cx0pll_enable(struct
> intel_encoder *encoder,
>  	if (intel_encoder_is_c10phy(encoder))
>  		intel_c10_pll_program(display, encoder, &pll_state->c10);
>  	else
> -		intel_c20_pll_program(display, encoder, &pll_state->c20,
> is_dp, port_clock);
> +		intel_c20_pll_program(display, encoder, &pll_state->c20);
> 
>  	/*
>  	 * 6. Program the enabled and disabled owned PHY lane diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 6183da90b28d..a0238a3e7288 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -255,6 +255,11 @@ struct intel_c20pll_state {
>  		u16 mplla[10];
>  		u16 mpllb[11];
>  	};
> +	struct intel_c20pll_vdr_state {
> +		u8 custom_width;
> +		u8 serdes_rate;
> +		u8 hdmi_rate;
> +	} vdr;
>  };
> 
>  struct intel_cx0pll_state {
> --
> 2.34.1

[PATCH v2 06/32] drm/i915/cx0: Move definition of Cx0 PHY functions earlier

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Move the definitions of the
  intel_c10pll_calc_port_clock()
  intel_c20_get_dp_rate()
  intel_c20_get_hdmi_rate()
  is_hdmi_frl()
  is_dp2()
  intel_get_c20_custom_width()
functions earlier to avoid the forward declarations.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 203 +++++++++----------
 1 file changed, 98 insertions(+), 105 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index fd0409565c68..9515157ee6b3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2126,7 +2126,31 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 }
 
 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c10pll_state *pll_state);
+					const struct intel_c10pll_state *pll_state)
+{
+	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
+	int tmpclk = 0;
+
+	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
+		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
+		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
+		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
+	}
+
+	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
+		      pll_state->pll[2]) / 2 + 16;
+
+	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
+
+	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+				     10 << (tx_clk_div + 16));
+	tmpclk *= (hdmi_div ? 2 : 1);
+
+	return tmpclk;
+}
 
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
@@ -2357,9 +2381,79 @@ intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
-static u8 intel_c20_get_dp_rate(u32 clock);
-static u8 intel_c20_get_hdmi_rate(u32 clock);
-static int intel_get_c20_custom_width(u32 clock, bool dp);
+static u8 intel_c20_get_dp_rate(u32 clock)
+{
+	switch (clock) {
+	case 162000: /* 1.62 Gbps DP1.4 */
+		return 0;
+	case 270000: /* 2.7 Gbps DP1.4 */
+		return 1;
+	case 540000: /* 5.4 Gbps DP 1.4 */
+		return 2;
+	case 810000: /* 8.1 Gbps DP1.4 */
+		return 3;
+	case 216000: /* 2.16 Gbps eDP */
+		return 4;
+	case 243000: /* 2.43 Gbps eDP */
+		return 5;
+	case 324000: /* 3.24 Gbps eDP */
+		return 6;
+	case 432000: /* 4.32 Gbps eDP */
+		return 7;
+	case 1000000: /* 10 Gbps DP2.0 */
+		return 8;
+	case 1350000: /* 13.5 Gbps DP2.0 */
+		return 9;
+	case 2000000: /* 20 Gbps DP2.0 */
+		return 10;
+	case 648000: /* 6.48 Gbps eDP*/
+		return 11;
+	case 675000: /* 6.75 Gbps eDP*/
+		return 12;
+	default:
+		MISSING_CASE(clock);
+		return 0;
+	}
+}
+
+static u8 intel_c20_get_hdmi_rate(u32 clock)
+{
+	if (clock >= 25175 && clock <= 600000)
+		return 0;
+
+	switch (clock) {
+	case 300000: /* 3 Gbps */
+	case 600000: /* 6 Gbps */
+	case 1200000: /* 12 Gbps */
+		return 1;
+	case 800000: /* 8 Gbps */
+		return 2;
+	case 1000000: /* 10 Gbps */
+		return 3;
+	default:
+		MISSING_CASE(clock);
+		return 0;
+	}
+}
+
+static bool is_dp2(u32 clock)
+{
+	/* DP2.0 clock rates */
+	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)
+		return true;
+
+	return false;
+}
+
+static int intel_get_c20_custom_width(u32 clock, bool dp)
+{
+	if (dp && is_dp2(clock))
+		return 2;
+	else if (intel_hdmi_is_frl(clock))
+		return 1;
+	else
+		return 0;
+}
 
 static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool is_dp,
 				      int port_clock)
@@ -2648,70 +2742,6 @@ void intel_cx0pll_dump_hw_state(struct intel_display *display,
 		intel_c20pll_dump_hw_state(display, &hw_state->c20);
 }
 
-static u8 intel_c20_get_dp_rate(u32 clock)
-{
-	switch (clock) {
-	case 162000: /* 1.62 Gbps DP1.4 */
-		return 0;
-	case 270000: /* 2.7 Gbps DP1.4 */
-		return 1;
-	case 540000: /* 5.4 Gbps DP 1.4 */
-		return 2;
-	case 810000: /* 8.1 Gbps DP1.4 */
-		return 3;
-	case 216000: /* 2.16 Gbps eDP */
-		return 4;
-	case 243000: /* 2.43 Gbps eDP */
-		return 5;
-	case 324000: /* 3.24 Gbps eDP */
-		return 6;
-	case 432000: /* 4.32 Gbps eDP */
-		return 7;
-	case 1000000: /* 10 Gbps DP2.0 */
-		return 8;
-	case 1350000: /* 13.5 Gbps DP2.0 */
-		return 9;
-	case 2000000: /* 20 Gbps DP2.0 */
-		return 10;
-	case 648000: /* 6.48 Gbps eDP*/
-		return 11;
-	case 675000: /* 6.75 Gbps eDP*/
-		return 12;
-	default:
-		MISSING_CASE(clock);
-		return 0;
-	}
-}
-
-static u8 intel_c20_get_hdmi_rate(u32 clock)
-{
-	if (clock >= 25175 && clock <= 600000)
-		return 0;
-
-	switch (clock) {
-	case 300000: /* 3 Gbps */
-	case 600000: /* 6 Gbps */
-	case 1200000: /* 12 Gbps */
-		return 1;
-	case 800000: /* 8 Gbps */
-		return 2;
-	case 1000000: /* 10 Gbps */
-		return 3;
-	default:
-		MISSING_CASE(clock);
-		return 0;
-	}
-}
-
-static bool is_dp2(u32 clock)
-{
-	/* DP2.0 clock rates */
-	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)
-		return true;
-
-	return false;
-}
-
 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
@@ -2721,16 +2751,6 @@ static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
 	return intel_tc_port_in_legacy_mode(intel_dig_port);
 }
 
-static int intel_get_c20_custom_width(u32 clock, bool dp)
-{
-	if (dp && is_dp2(clock))
-		return 2;
-	else if (intel_hdmi_is_frl(clock))
-		return 1;
-	else
-		return 0;
-}
-
 static void intel_c20_pll_program(struct intel_display *display,
 				  struct intel_encoder *encoder,
 				  const struct intel_c20pll_state *pll_state)
@@ -2819,33 +2839,6 @@ static void intel_c20_pll_program(struct intel_display *display,
 		      MB_WRITE_COMMITTED);
 }
 
-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c10pll_state *pll_state)
-{
-	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
-	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
-	int tmpclk = 0;
-
-	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
-		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
-		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
-		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
-	}
-
-	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
-		      pll_state->pll[2]) / 2 + 16;
-
-	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
-	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
-
-	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
-				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
-				     10 << (tx_clk_div + 16));
-	tmpclk *= (hdmi_div ? 2 : 1);
-
-	return tmpclk;
-}
-
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 					 const struct intel_cx0pll_state *pll_state,
 					 bool is_dp, int port_clock,
-- 
2.34.1

[PATCH v2 07/32] drm/i915/cx0: Add macro to get DDI port width from a register value

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

A follow-up change will need to retrieve the DDI port field from the
register value, add a macro for this. Make things symmetric with setting
the field in the register.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9d71e26a4fa2..c14d3caa73a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2349,8 +2349,13 @@ enum skl_power_gate {
 #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
 #define  DDI_A_4_LANES				REG_BIT(4)
 #define  DDI_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
+#define  DDI_PORT_WIDTH_ENCODE(width)		((width) == 3 ? 4 : (width) - 1)
+#define  DDI_PORT_WIDTH_DECODE(regval)		((regval) == 4 ? 3 : (regval) + 1)
 #define  DDI_PORT_WIDTH(width)			REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
-							       ((width) == 3 ? 4 : (width) - 1))
+							       DDI_PORT_WIDTH_ENCODE(width))
+#define  DDI_PORT_WIDTH_GET(regval)		DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \
+										    (regval)))
+
 #define  DDI_PORT_WIDTH_SHIFT			1
 #define  DDI_INIT_DISPLAY_DETECTED		REG_BIT(0)
 
-- 
2.34.1

[PATCH v2 08/32] drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The Cx0 PLL enable programming requires the enabled lane count. The PLL
manager framework doesn't pass the CRTC state to the PLL's enable hook,
so prepare here for the conversion to use the PLL manager, by tracking
the enabled lane count in the PLL state as well. This has the advantage,
that the enabled lane count can be verified against the PHY/PLL's
enabled TX lanes.

This also allows dropping the lane count param from the
__intel_cx0pll_enable() function, since it can retrieve this now from
the PLL state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 55 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 2 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9515157ee6b3..2ab93d02fdf1 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -11,6 +11,7 @@
 #include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
+#include "intel_display_regs.h"
 #include "intel_ddi.h"
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
@@ -2078,7 +2079,7 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
  */
 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 					      const struct intel_c10pll_state * const *tables,
-					      bool is_dp, int port_clock,
+					      bool is_dp, int port_clock, int lane_count,
 					      struct intel_cx0pll_state *pll_state)
 {
 	int i;
@@ -2088,7 +2089,9 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 			pll_state->c10 = *tables[i];
 			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
 			intel_c10pll_update_pll(encoder, pll_state);
+
 			pll_state->use_c10 = true;
+			pll_state->lane_count = lane_count;
 
 			return 0;
 		}
@@ -2109,7 +2112,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 
 	err = intel_c10pll_calc_state_from_table(encoder, tables,
 						 intel_crtc_has_dp_encoder(crtc_state),
-						 crtc_state->port_clock,
+						 crtc_state->port_clock, crtc_state->lane_count,
 						 &crtc_state->dpll_hw_state.cx0pll);
 
 	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
@@ -2121,6 +2124,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 	intel_c10pll_update_pll(encoder,
 				&crtc_state->dpll_hw_state.cx0pll);
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
+	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
 
 	return 0;
 }
@@ -2152,6 +2156,37 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
 	return tmpclk;
 }
 
+static int readout_enabled_lane_count(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	u8 enabled_tx_lane_count = 0;
+	int max_tx_lane_count;
+	int tx_lane;
+
+	/*
+	 * TODO: also check inactive TX lanes in all PHY lanes owned by the
+	 * display. For now checking only those PHY lane(s) which are owned
+	 * based on the active TX lane count (i.e.
+	 *   1,2 active TX lanes -> PHY lane#0
+	 *   3,4 active TX lanes -> PHY lane#0 and PHY lane#1).
+	 */
+	max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, DDI_BUF_CTL(encoder->port)));
+	if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0))
+		max_tx_lane_count = roundup_pow_of_two(max_tx_lane_count);
+
+	for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
+		u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+		int tx = tx_lane % 2 + 1;
+		u8 val;
+
+		val = intel_cx0_read(encoder, phy_lane_mask, PHY_CX0_TX_CONTROL(tx, 2));
+		if (!(val & CONTROL2_DISABLE_SINGLE_TX))
+			enabled_tx_lane_count++;
+	}
+
+	return enabled_tx_lane_count;
+}
+
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
 {
@@ -2170,6 +2205,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	 */
 	intel_c10_msgbus_access_begin(encoder, lane);
 
+	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
 		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
 
@@ -2562,6 +2599,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	int err = -ENOENT;
 
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
+	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
 
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (!is_dp)
@@ -2651,6 +2689,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
+	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+
 	/* 1. Read VDR params and current context selection */
 	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
 
@@ -3089,7 +3129,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 
 static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 				  const struct intel_cx0pll_state *pll_state,
-				  bool is_dp, int port_clock, int lane_count)
+				  bool is_dp, int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3131,7 +3171,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 6. Program the enabled and disabled owned PHY lane
 	 * transmitters over message bus
 	 */
-	intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal);
+	intel_cx0_program_phy_lane(encoder, pll_state->lane_count, lane_reversal);
 
 	/*
 	 * 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -3174,7 +3214,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 {
 	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
 			      intel_crtc_has_dp_encoder(crtc_state),
-			      crtc_state->port_clock, crtc_state->lane_count);
+			      crtc_state->port_clock);
 }
 
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
@@ -3700,6 +3740,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 	for_each_intel_encoder(display->drm, encoder) {
 		struct intel_cx0pll_state pll_state = {};
 		int port_clock = 162000;
+		int lane_count = 4;
 
 		if (!intel_encoder_is_dig_port(encoder))
 			continue;
@@ -3712,7 +3753,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 
 		if (intel_c10pll_calc_state_from_table(encoder,
 						       mtl_c10_edp_tables,
-						       true, port_clock,
+						       true, port_clock, lane_count,
 						       &pll_state) < 0) {
 			drm_WARN_ON(display->drm,
 				    "Unable to calc C10 state from the tables\n");
@@ -3723,7 +3764,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
 			    encoder->base.base.id, encoder->base.name);
 
-		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4);
+		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock);
 		intel_cx0pll_disable(encoder);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index a0238a3e7288..a7946ff13cb6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -267,6 +267,7 @@ struct intel_cx0pll_state {
 		struct intel_c10pll_state c10;
 		struct intel_c20pll_state c20;
 	};
+	int lane_count;
 	bool ssc_enabled;
 	bool use_c10;
 	bool tbt_mode;
-- 
2.34.1

[PATCH v2 09/32] drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Define the C10 PLL SSC register range via macros, so the HW/SW state of
these register can be verified by a follow-up change, reusing these
macros.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 2ab93d02fdf1..f190762e4871 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2059,6 +2059,9 @@ static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,
 	}
 }
 
+#define C10_PLL_SSC_REG_START_IDX	4
+#define C10_PLL_SSC_REG_COUNT		5
+
 static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 				    struct intel_cx0pll_state *pll_state)
 {
@@ -2068,8 +2071,11 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 	if (pll_state->ssc_enabled)
 		return;
 
-	drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
-	for (i = 4; i < 9; i++)
+	drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <
+				  C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT);
+	for (i = C10_PLL_SSC_REG_START_IDX;
+	     i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT;
+	     i++)
 		pll_state->c10.pll[i] = 0;
 }
 
-- 
2.34.1

[PATCH v2 10/32] drm/i915/cx0: Read out the Cx0 PHY SSC enabled state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Read out the C10, C20 PHY PLLs SSC enabled state, so the PLL HW/SW state
verification can check this state as well.

C10 PHY PLLs program some PLL registers zeroed out for the non-SSC case,
while programming non-zero values to the same registers for the SSC
case, so check that these PLL registers being zero or non-zero matches
the PLL's overall SSC-enabled state (stored in the
intel_c10pll_state::ssc_enabled flag).

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 ++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f190762e4871..4562e47042d2 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2062,6 +2062,12 @@ static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,
 #define C10_PLL_SSC_REG_START_IDX	4
 #define C10_PLL_SSC_REG_COUNT		5
 
+static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state *pll_state)
+{
+	return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX],
+			  0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT);
+}
+
 static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 				    struct intel_cx0pll_state *pll_state)
 {
@@ -2193,10 +2199,20 @@ static int readout_enabled_lane_count(struct intel_encoder *encoder)
 	return enabled_tx_lane_count;
 }
 
+static bool readout_ssc_state(struct intel_encoder *encoder, bool is_mpll_b)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
+		(is_mpll_b ? XELPDP_SSC_ENABLE_PLLB : XELPDP_SSC_ENABLE_PLLA);
+}
+
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
 {
 	struct intel_c10pll_state *pll_state = &cx0pll_state->c10;
+	struct intel_display *display = to_intel_display(encoder);
+	enum phy phy = intel_encoder_to_phy(encoder);
 	u8 lane = INTEL_CX0_LANE0;
 	intel_wakeref_t wakeref;
 	int i;
@@ -2222,6 +2238,13 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 
 	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
+
+	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
+	drm_WARN(display->drm,
+		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
+		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
+		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
+		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
 }
 
 static void intel_c10_pll_program(struct intel_display *display,
@@ -2753,6 +2776,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 	pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
+
+	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));
 }
 
 static void intel_c20pll_dump_hw_state(struct intel_display *display,
-- 
2.34.1

[PATCH v2 11/32] drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
enable hook, so prepare here for the conversion to use the PLL manager
for Cx0 PHY PLLs by determining the DP/HDMI mode from the PLL state.

For C10 PHYs use the fact that the HDMI divider value in the PLL
registers are set if and only if the PLL is in HDMI mode.

For C20 PHYs use the DP mode flag programmed to the VDR SERDES register,
which is set if and only if the PLL is in DP mode.

Assert that the above PLL/VDR SERDES register values match the DP/HDMI
mode being configured already during state computation.

This also allows dropping the is_dp param from the
__intel_cx0pll_enable() function, since it can retrieve this now from
the PLL state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 43 ++++++++++++++++----
 1 file changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 4562e47042d2..29dfbd60c7ce 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2085,6 +2085,24 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 		pll_state->c10.pll[i] = 0;
 }
 
+static bool c10pll_state_is_dp(const struct intel_c10pll_state *pll_state)
+{
+	return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
+}
+
+static bool c20pll_state_is_dp(const struct intel_c20pll_state *pll_state)
+{
+	return pll_state->vdr.serdes_rate & PHY_C20_IS_DP;
+}
+
+static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state)
+{
+	if (pll_state->use_c10)
+		return c10pll_state_is_dp(&pll_state->c10);
+
+	return c20pll_state_is_dp(&pll_state->c20);
+}
+
 /*
  * TODO: Convert the following to align with intel_c20pll_find_table() and
  * intel_c20pll_calc_state_from_table().
@@ -2094,6 +2112,7 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 					      bool is_dp, int port_clock, int lane_count,
 					      struct intel_cx0pll_state *pll_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	int i;
 
 	for (i = 0; tables[i]; i++) {
@@ -2105,6 +2124,8 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 			pll_state->use_c10 = true;
 			pll_state->lane_count = lane_count;
 
+			drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10));
+
 			return 0;
 		}
 	}
@@ -2115,6 +2136,8 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 				   struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(encoder);
+	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	const struct intel_c10pll_state * const *tables;
 	int err;
 
@@ -2122,8 +2145,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 	if (!tables)
 		return -EINVAL;
 
-	err = intel_c10pll_calc_state_from_table(encoder, tables,
-						 intel_crtc_has_dp_encoder(crtc_state),
+	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
 						 crtc_state->port_clock, crtc_state->lane_count,
 						 &crtc_state->dpll_hw_state.cx0pll);
 
@@ -2138,6 +2160,9 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
 	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
 
+	drm_WARN_ON(display->drm,
+		    is_dp != c10pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c10));
+
 	return 0;
 }
 
@@ -2624,6 +2649,7 @@ static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat
 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 				   struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	int err = -ENOENT;
 
@@ -2644,6 +2670,9 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
 				  is_dp, crtc_state->port_clock);
 
+	drm_WARN_ON(display->drm,
+		    is_dp != c20pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c20));
+
 	return 0;
 }
 
@@ -2912,10 +2941,11 @@ static void intel_c20_pll_program(struct intel_display *display,
 
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 					 const struct intel_cx0pll_state *pll_state,
-					 bool is_dp, int port_clock,
+					 int port_clock,
 					 bool lane_reversal)
 {
 	struct intel_display *display = to_intel_display(encoder);
+	bool is_dp = cx0pll_state_is_dp(pll_state);
 	u32 val = 0;
 
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
@@ -3160,7 +3190,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 
 static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 				  const struct intel_cx0pll_state *pll_state,
-				  bool is_dp, int port_clock)
+				  int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3174,7 +3204,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 1. Program PORT_CLOCK_CTL REGISTER to configure
 	 * clock muxes, gating and SSC
 	 */
-	intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal);
+	intel_program_port_clock_ctl(encoder, pll_state, port_clock, lane_reversal);
 
 	/* 2. Bring PHY out of reset. */
 	intel_cx0_phy_lane_reset(encoder, lane_reversal);
@@ -3244,7 +3274,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
 	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
-			      intel_crtc_has_dp_encoder(crtc_state),
 			      crtc_state->port_clock);
 }
 
@@ -3795,7 +3824,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
 			    encoder->base.base.id, encoder->base.name);
 
-		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock);
+		__intel_cx0pll_enable(encoder, &pll_state, port_clock);
 		intel_cx0pll_disable(encoder);
 	}
 }
-- 
2.34.1

[PATCH v2 12/32] drm/i915/cx0: Determine Cx0 PLL port clock from PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The port clock is tracked in the PLL state, so there is no need to pass
it separately to __intel_cx0pll_enable(). Drop the port clock function
param accordingly.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 29dfbd60c7ce..0ad9fae230c9 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3188,10 +3188,10 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 	return val;
 }
 
-static void __intel_cx0pll_enable(struct intel_encoder *encoder,
-				  const struct intel_cx0pll_state *pll_state,
-				  int port_clock)
+static void intel_cx0pll_enable(struct intel_encoder *encoder,
+				const struct intel_cx0pll_state *pll_state)
 {
+	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock;
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -3270,13 +3270,6 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
-static void intel_cx0pll_enable(struct intel_encoder *encoder,
-				const struct intel_crtc_state *crtc_state)
-{
-	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
-			      crtc_state->port_clock);
-}
-
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -3403,7 +3396,7 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable(encoder, crtc_state);
 	else
-		intel_cx0pll_enable(encoder, crtc_state);
+		intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll);
 }
 
 /*
@@ -3824,7 +3817,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
 			    encoder->base.base.id, encoder->base.name);
 
-		__intel_cx0pll_enable(encoder, &pll_state, port_clock);
+		intel_cx0pll_enable(encoder, &pll_state);
 		intel_cx0pll_disable(encoder);
 	}
 }
-- 
2.34.1

[PATCH v2 13/32] drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Ensure Cx0 pll state is initialized to zero before any computation or HW
readouts, to prevent leaving some parameter in the state uninitialized
in the actual compute/HW readout functions later.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0ad9fae230c9..df3daa81a698 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2679,6 +2679,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
 {
+	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state));
+
 	if (intel_encoder_is_c10phy(encoder))
 		return intel_c10pll_calc_state(crtc_state, encoder);
 	return intel_c20pll_calc_state(crtc_state, encoder);
@@ -3612,7 +3614,7 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state)
 {
-	pll_state->use_c10 = false;
+	memset(pll_state, 0, sizeof(*pll_state));
 
 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
 	if (pll_state->tbt_mode)
-- 
2.34.1

[PATCH v2 14/32] drm/i915/cx0: Print additional Cx0 PLL HW state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Print all the Cx0 PLL state in the PLL state dumper.

v2: Use BUILD_BUG_ON() instead of WARN_ON() (Jani)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index df3daa81a698..763546fe152b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2306,8 +2306,8 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
 	unsigned int multiplier, tx_clk_div;
 
 	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
-	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
-		    str_yes_no(fracen));
+	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
+		    hw_state->clock, str_yes_no(fracen));
 
 	if (fracen) {
 		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
@@ -2816,7 +2816,7 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
 {
 	int i;
 
-	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
+	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
 	drm_dbg_kms(display->drm,
 		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
 		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
@@ -2832,12 +2832,24 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
 		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
 			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
 				    hw_state->mplla[i]);
+
+		/* For full coverage, also print the additional PLL B entry. */
+		BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb));
+		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
 	}
+
+	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
+		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
 }
 
 void intel_cx0pll_dump_hw_state(struct intel_display *display,
 				const struct intel_cx0pll_state *hw_state)
 {
+	drm_dbg_kms(display->drm,
+		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
+		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
+		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
+
 	if (hw_state->use_c10)
 		intel_c10pll_dump_hw_state(display, &hw_state->c10);
 	else
-- 
2.34.1

RE: [PATCH v2 14/32] drm/i915/cx0: Print additional Cx0 PLL HW state

[Kandpal, Suraj]

> Subject: [PATCH v2 14/32] drm/i915/cx0: Print additional Cx0 PLL HW state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Print all the Cx0 PLL state in the PLL state dumper.
> 
> v2: Use BUILD_BUG_ON() instead of WARN_ON() (Jani)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index df3daa81a698..763546fe152b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2306,8 +2306,8 @@ static void intel_c10pll_dump_hw_state(struct
> intel_display *display,
>  	unsigned int multiplier, tx_clk_div;
> 
>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> -	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
> -		    str_yes_no(fracen));
> +	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
> +		    hw_state->clock, str_yes_no(fracen));
> 
>  	if (fracen) {
>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; @@ -
> 2816,7 +2816,7 @@ static void intel_c20pll_dump_hw_state(struct
> intel_display *display,  {
>  	int i;
> 
> -	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
> +	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n",
> +hw_state->clock);
>  	drm_dbg_kms(display->drm,
>  		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
>  		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); @@ -
> 2832,12 +2832,24 @@ static void intel_c20pll_dump_hw_state(struct
> intel_display *display,
>  		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
>  			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
>  				    hw_state->mplla[i]);
> +
> +		/* For full coverage, also print the additional PLL B entry. */
> +		BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 !=
> ARRAY_SIZE(hw_state->mpllb));
> +		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
> +hw_state->mpllb[i]);
>  	}
> +
> +	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate:
> 0x%02x, hdmi rate: 0x%02x\n",
> +		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate,
> +hw_state->vdr.hdmi_rate);
>  }
> 
>  void intel_cx0pll_dump_hw_state(struct intel_display *display,
>  				const struct intel_cx0pll_state *hw_state)  {
> +	drm_dbg_kms(display->drm,
> +		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10:
> %s, tbt_mode: %s\n",
> +		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
> +		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state-
> >tbt_mode));
> +
>  	if (hw_state->use_c10)
>  		intel_c10pll_dump_hw_state(display, &hw_state->c10);
>  	else
> --
> 2.34.1

[PATCH v2 15/32] drm/i915/cx0: Remove state verification

[Mika Kahola]

When pll's are moved to dpll framework we no longer
need Cx0 specific state verification as we can rely
on dpll state verification instead.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 114 ------------------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 -
 .../drm/i915/display/intel_modeset_verify.c   |   1 -
 3 files changed, 117 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 763546fe152b..31db79f0636b 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3594,35 +3594,6 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 		return ICL_PORT_DPLL_DEFAULT;
 }
 
-static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
-				      struct intel_crtc *crtc,
-				      struct intel_encoder *encoder,
-				      struct intel_c10pll_state *mpllb_hw_state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
-		u8 expected = mpllb_sw_state->pll[i];
-
-		INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected,
-					 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
-					 crtc->base.base.id, crtc->base.name, i,
-					 expected, mpllb_hw_state->pll[i]);
-	}
-
-	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx,
-				 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)",
-				 crtc->base.base.id, crtc->base.name,
-				 mpllb_sw_state->tx, mpllb_hw_state->tx);
-
-	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,
-				 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)",
-				 crtc->base.base.id, crtc->base.name,
-				 mpllb_sw_state->cmn, mpllb_hw_state->cmn);
-}
-
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state)
 {
@@ -3699,91 +3670,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
 }
 
-static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
-				      struct intel_crtc *crtc,
-				      struct intel_encoder *encoder,
-				      struct intel_c20pll_state *mpll_hw_state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
-	bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
-	bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
-	int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
-	int i;
-
-	INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,
-				 "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
-				 crtc->base.base.id, crtc->base.name,
-				 mpll_sw_state->clock, mpll_hw_state->clock);
-
-	INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb,
-				 "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
-				 crtc->base.base.id, crtc->base.name,
-				 sw_use_mpllb, hw_use_mpllb);
-
-	if (hw_use_mpllb) {
-		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
-			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],
-						 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
-						 crtc->base.base.id, crtc->base.name, i,
-						 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);
-		}
-	} else {
-		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
-			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
-						 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
-						 crtc->base.base.id, crtc->base.name, i,
-						 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
-		}
-	}
-
-	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {
-		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],
-					 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)",
-					 crtc->base.base.id, crtc->base.name, i,
-					 mpll_sw_state->tx[i], mpll_hw_state->tx[i]);
-	}
-
-	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {
-		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],
-					 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",
-					 crtc->base.base.id, crtc->base.name, i,
-					 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);
-	}
-}
-
-void intel_cx0pll_state_verify(struct intel_atomic_state *state,
-			       struct intel_crtc *crtc)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder;
-	struct intel_cx0pll_state mpll_hw_state = {};
-
-	if (!IS_DISPLAY_VER(display, 14, 30))
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
-	if (!intel_crtc_needs_modeset(new_crtc_state) &&
-	    !intel_crtc_needs_fastset(new_crtc_state))
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);
-
-	if (mpll_hw_state.tbt_mode)
-		return;
-
-	if (intel_encoder_is_c10phy(encoder))
-		intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10);
-	else
-		intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20);
-}
-
 /*
  * WA 14022081154
  * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 84d334b865f7..0b98892ee8ac 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -40,8 +40,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 
 void intel_cx0pll_dump_hw_state(struct intel_display *display,
 				const struct intel_cx0pll_state *hw_state);
-void intel_cx0pll_state_verify(struct intel_atomic_state *state,
-			       struct intel_crtc *crtc);
 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index b361a77cd235..12a00121c274 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -246,7 +246,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
 	verify_crtc_state(state, crtc);
 	intel_dpll_state_verify(state, crtc);
 	intel_mpllb_state_verify(state, crtc);
-	intel_cx0pll_state_verify(state, crtc);
 	intel_lt_phy_pll_state_verify(state, crtc);
 }
 
-- 
2.34.1

[PATCH v2 16/32] drm/i915/cx0: Add PLL information for MTL+

[Mika Kahola]

Start bringing MTL+ platforms as part of PLL framework.
The work is started by adding PLL information and related
function hooks.

BSpec: 55726

v2: Revise commit message and add BSpec ID (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8c345e1bdd94..23f22c495ec7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4305,6 +4305,25 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
 	.compare_hw_state = icl_compare_hw_state,
 };
 
+static const struct intel_dpll_funcs mtl_pll_funcs = {
+};
+
+static const struct dpll_info mtl_plls[] = {
+	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
+	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
+	/* TODO: Add TBT PLL */
+	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
+	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
+	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
+	{ .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
+	{}
+};
+
+__maybe_unused
+static const struct intel_dpll_mgr mtl_pll_mgr = {
+	.dpll_info = mtl_plls,
+};
+
 /**
  * intel_dpll_init - Initialize DPLLs
  * @display: intel_display device
-- 
2.34.1

RE: [PATCH v2 16/32] drm/i915/cx0: Add PLL information for MTL+

[Kandpal, Suraj]

> Subject: [PATCH v2 16/32] drm/i915/cx0: Add PLL information for MTL+
> 
> Start bringing MTL+ platforms as part of PLL framework.
> The work is started by adding PLL information and related function hooks.

Reframe like so
"Bring MTL+ platforms as part of PLL framework.
To do this add PLL information and related function hooks"

Commit messages need to be more like commands.

> 
> BSpec: 55726

Needs to be a trailer right above Signed-off-by
With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> v2: Revise commit message and add BSpec ID (Suraj)
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8c345e1bdd94..23f22c495ec7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4305,6 +4305,25 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>  	.compare_hw_state = icl_compare_hw_state,  };
> 
> +static const struct intel_dpll_funcs mtl_pll_funcs = { };
> +
> +static const struct dpll_info mtl_plls[] = {
> +	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> +	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> +	/* TODO: Add TBT PLL */
> +	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> },
> +	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> },
> +	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> },
> +	{ .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> },
> +	{}
> +};
> +
> +__maybe_unused
> +static const struct intel_dpll_mgr mtl_pll_mgr = {
> +	.dpll_info = mtl_plls,
> +};
> +
>  /**
>   * intel_dpll_init - Initialize DPLLs
>   * @display: intel_display device
> --
> 2.34.1

[PATCH v2 17/32] drm/i915/cx0: Update C10/C20 state calculation

[Mika Kahola]

This patch updates several functions in intel_cx0_phy.c to
make PLL state management more explicit.

Changes include
 * adding 'const' qualifiers to intel_crtc_state parameter for
   cx0 state calculation functions
 * refactoring C10/C20 PLL state calculations helpers to take
   explicit hardware state pointers instead of directly modifying
   'crtc_state->dpll_hw_state'

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +-
 drivers/gpu/drm/i915/display/intel_dpll.c    |  2 +-
 3 files changed, 40 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 31db79f0636b..de71805a065c 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2029,7 +2029,7 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
 };
 
 static const struct intel_c10pll_state * const *
-intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
+intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
 			struct intel_encoder *encoder)
 {
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
@@ -2133,8 +2133,9 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 	return -EINVAL;
 }
 
-static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
-				   struct intel_encoder *encoder)
+static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
+				   struct intel_encoder *encoder,
+				   struct intel_dpll_hw_state *hw_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
@@ -2147,21 +2148,20 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 
 	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
 						 crtc_state->port_clock, crtc_state->lane_count,
-						 &crtc_state->dpll_hw_state.cx0pll);
+						 &hw_state->cx0pll);
 
 	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		return err;
 
 	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */
-	intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10,
+	intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10,
 					   crtc_state->port_clock);
-	intel_c10pll_update_pll(encoder,
-				&crtc_state->dpll_hw_state.cx0pll);
-	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
-	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
+	intel_c10pll_update_pll(encoder, &hw_state->cx0pll);
 
-	drm_WARN_ON(display->drm,
-		    is_dp != c10pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c10));
+	hw_state->cx0pll.use_c10 = true;
+	hw_state->cx0pll.lane_count = crtc_state->lane_count;
+
+	drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&hw_state->cx0pll.c10));
 
 	return 0;
 }
@@ -2350,7 +2350,7 @@ static bool is_arrowlake_s_by_host_bridge(void)
 	return pdev && IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
 }
 
-static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
+static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	u16 tx_misc;
@@ -2374,9 +2374,9 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
 		C20_PHY_TX_DCC_BYPASS | C20_PHY_TX_TERM_CTL(tx_term_ctrl));
 }
 
-static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
+static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_state,
+					   struct intel_c20pll_state *pll_state)
 {
-	struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
 	u64 datarate;
 	u64 mpll_tx_clk_div;
 	u64 vco_freq_shift;
@@ -2629,8 +2629,9 @@ intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
-static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
-					      struct intel_encoder *encoder)
+static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crtc_state,
+					      struct intel_encoder *encoder,
+					      struct intel_cx0pll_state *pll_state)
 {
 	const struct intel_c20pll_state *table;
 
@@ -2638,52 +2639,53 @@ static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat
 	if (!table)
 		return -EINVAL;
 
-	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
+	pll_state->c20 = *table;
 
-	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
-				intel_crtc_has_dp_encoder(crtc_state));
+	intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state));
 
 	return 0;
 }
 
-static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
-				   struct intel_encoder *encoder)
+static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,
+				   struct intel_encoder *encoder,
+				   struct intel_dpll_hw_state *hw_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	int err = -ENOENT;
 
-	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
-	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
+	hw_state->cx0pll.use_c10 = false;
+	hw_state->cx0pll.lane_count = crtc_state->lane_count;
 
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (!is_dp)
 		/* TODO: Update SSC state for HDMI as well */
-		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
+		err = intel_c20_compute_hdmi_tmds_pll(crtc_state, &hw_state->cx0pll.c20);
 
 	if (err)
-		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
+		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
+							 &hw_state->cx0pll);
 
 	if (err)
 		return err;
 
-	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
+	intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr,
 				  is_dp, crtc_state->port_clock);
 
-	drm_WARN_ON(display->drm,
-		    is_dp != c20pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c20));
+	drm_WARN_ON(display->drm, is_dp != c20pll_state_is_dp(&hw_state->cx0pll.c20));
 
 	return 0;
 }
 
-int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
-			    struct intel_encoder *encoder)
+int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder,
+			    struct intel_dpll_hw_state *hw_state)
 {
-	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state));
+	memset(hw_state, 0, sizeof(*hw_state));
 
 	if (intel_encoder_is_c10phy(encoder))
-		return intel_c10pll_calc_state(crtc_state, encoder);
-	return intel_c20pll_calc_state(crtc_state, encoder);
+		return intel_c10pll_calc_state(crtc_state, encoder, hw_state);
+	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);
 }
 
 static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 0b98892ee8ac..d52e864f5e19 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -19,6 +19,7 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_cx0pll_state;
 struct intel_display;
+struct intel_dpll_hw_state;
 struct intel_encoder;
 struct intel_hdmi;
 
@@ -32,7 +33,9 @@ enum icl_port_dpll_id
 intel_mtl_port_pll_type(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state);
 
-int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
+int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder,
+			    struct intel_dpll_hw_state *hw_state);
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state);
 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 4f1db8493a2e..342d46b7b1af 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1221,7 +1221,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_get_crtc_new_encoder(state, crtc_state);
 	int ret;
 
-	ret = intel_cx0pll_calc_state(crtc_state, encoder);
+	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
 	if (ret)
 		return ret;
 
-- 
2.34.1

RE: [PATCH v2 17/32] drm/i915/cx0: Update C10/C20 state calculation

[Kandpal, Suraj]

> Subject: [PATCH v2 17/32] drm/i915/cx0: Update C10/C20 state calculation
> 
> This patch updates several functions in intel_cx0_phy.c to make PLL state
> management more explicit.

Do not say "patch" because after you merge it becomes a commit.

> 
> Changes include
>  * adding 'const' qualifiers to intel_crtc_state parameter for
>    cx0 state calculation functions

*Add 'const' ...

>  * refactoring C10/C20 PLL state calculations helpers to take

*Refactor C10/C20 ...

With that fixed LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

>    explicit hardware state pointers instead of directly modifying
>    'crtc_state->dpll_hw_state'
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +-
>  drivers/gpu/drm/i915/display/intel_dpll.c    |  2 +-
>  3 files changed, 40 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 31db79f0636b..de71805a065c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2029,7 +2029,7 @@ static const struct intel_c20pll_state * const
> mtl_c20_hdmi_tables[] = {  };
> 
>  static const struct intel_c10pll_state * const * -intel_c10pll_tables_get(struct
> intel_crtc_state *crtc_state,
> +intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
>  			struct intel_encoder *encoder)
>  {
>  	if (intel_crtc_has_dp_encoder(crtc_state)) { @@ -2133,8 +2133,9 @@
> static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
>  	return -EINVAL;
>  }
> 
> -static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> -				   struct intel_encoder *encoder)
> +static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
> +				   struct intel_encoder *encoder,
> +				   struct intel_dpll_hw_state *hw_state)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
> @@ -2147,21 +2148,20 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
> 
>  	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
>  						 crtc_state->port_clock,
> crtc_state->lane_count,
> -						 &crtc_state-
> >dpll_hw_state.cx0pll);
> +						 &hw_state->cx0pll);
> 
>  	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		return err;
> 
>  	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed
> tables */
> -	intel_snps_hdmi_pll_compute_c10pll(&crtc_state-
> >dpll_hw_state.cx0pll.c10,
> +	intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10,
>  					   crtc_state->port_clock);
> -	intel_c10pll_update_pll(encoder,
> -				&crtc_state->dpll_hw_state.cx0pll);
> -	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
> -	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> +	intel_c10pll_update_pll(encoder, &hw_state->cx0pll);
> 
> -	drm_WARN_ON(display->drm,
> -		    is_dp != c10pll_state_is_dp(&crtc_state-
> >dpll_hw_state.cx0pll.c10));
> +	hw_state->cx0pll.use_c10 = true;
> +	hw_state->cx0pll.lane_count = crtc_state->lane_count;
> +
> +	drm_WARN_ON(display->drm, is_dp !=
> +c10pll_state_is_dp(&hw_state->cx0pll.c10));
> 
>  	return 0;
>  }
> @@ -2350,7 +2350,7 @@ static bool is_arrowlake_s_by_host_bridge(void)
>  	return pdev &&
> IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
>  }
> 
> -static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
> +static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state
> +*crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	u16 tx_misc;
> @@ -2374,9 +2374,9 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct
> intel_crtc_state *crtc_state)
>  		C20_PHY_TX_DCC_BYPASS |
> C20_PHY_TX_TERM_CTL(tx_term_ctrl));
>  }
> 
> -static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
> +static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state
> *crtc_state,
> +					   struct intel_c20pll_state *pll_state)
>  {
> -	struct intel_c20pll_state *pll_state = &crtc_state-
> >dpll_hw_state.cx0pll.c20;
>  	u64 datarate;
>  	u64 mpll_tx_clk_div;
>  	u64 vco_freq_shift;
> @@ -2629,8 +2629,9 @@ intel_c20_pll_find_table(const struct intel_crtc_state
> *crtc_state,
>  	return NULL;
>  }
> 
> -static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
> -					      struct intel_encoder *encoder)
> +static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state
> *crtc_state,
> +					      struct intel_encoder *encoder,
> +					      struct intel_cx0pll_state *pll_state)
>  {
>  	const struct intel_c20pll_state *table;
> 
> @@ -2638,52 +2639,53 @@ static int intel_c20pll_calc_state_from_table(struct
> intel_crtc_state *crtc_stat
>  	if (!table)
>  		return -EINVAL;
> 
> -	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
> +	pll_state->c20 = *table;
> 
> -	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
> -				intel_crtc_has_dp_encoder(crtc_state));
> +	intel_cx0pll_update_ssc(encoder, pll_state,
> +intel_crtc_has_dp_encoder(crtc_state));
> 
>  	return 0;
>  }
> 
> -static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> -				   struct intel_encoder *encoder)
> +static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,
> +				   struct intel_encoder *encoder,
> +				   struct intel_dpll_hw_state *hw_state)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	int err = -ENOENT;
> 
> -	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> -	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> +	hw_state->cx0pll.use_c10 = false;
> +	hw_state->cx0pll.lane_count = crtc_state->lane_count;
> 
>  	/* try computed C20 HDMI tables before using consolidated tables */
>  	if (!is_dp)
>  		/* TODO: Update SSC state for HDMI as well */
> -		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state,
> +&hw_state->cx0pll.c20);
> 
>  	if (err)
> -		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
> +							 &hw_state->cx0pll);
> 
>  	if (err)
>  		return err;
> 
> -	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
> +	intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr,
>  				  is_dp, crtc_state->port_clock);
> 
> -	drm_WARN_ON(display->drm,
> -		    is_dp != c20pll_state_is_dp(&crtc_state-
> >dpll_hw_state.cx0pll.c20));
> +	drm_WARN_ON(display->drm, is_dp !=
> +c20pll_state_is_dp(&hw_state->cx0pll.c20));
> 
>  	return 0;
>  }
> 
> -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> -			    struct intel_encoder *encoder)
> +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder,
> +			    struct intel_dpll_hw_state *hw_state)
>  {
> -	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state-
> >dpll_hw_state));
> +	memset(hw_state, 0, sizeof(*hw_state));
> 
>  	if (intel_encoder_is_c10phy(encoder))
> -		return intel_c10pll_calc_state(crtc_state, encoder);
> -	return intel_c20pll_calc_state(crtc_state, encoder);
> +		return intel_c10pll_calc_state(crtc_state, encoder, hw_state);
> +	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);
>  }
> 
>  static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) diff --
> git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 0b98892ee8ac..d52e864f5e19 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -19,6 +19,7 @@ struct intel_crtc;
>  struct intel_crtc_state;
>  struct intel_cx0pll_state;
>  struct intel_display;
> +struct intel_dpll_hw_state;
>  struct intel_encoder;
>  struct intel_hdmi;
> 
> @@ -32,7 +33,9 @@ enum icl_port_dpll_id
>  intel_mtl_port_pll_type(struct intel_encoder *encoder,
>  			const struct intel_crtc_state *crtc_state);
> 
> -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct
> intel_encoder *encoder);
> +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder,
> +			    struct intel_dpll_hw_state *hw_state);
>  void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state);  int
> intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 4f1db8493a2e..342d46b7b1af 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1221,7 +1221,7 @@ static int mtl_crtc_compute_clock(struct
> intel_atomic_state *state,
>  		intel_get_crtc_new_encoder(state, crtc_state);
>  	int ret;
> 
> -	ret = intel_cx0pll_calc_state(crtc_state, encoder);
> +	ret = intel_cx0pll_calc_state(crtc_state, encoder,
> +&crtc_state->dpll_hw_state);
>  	if (ret)
>  		return ret;
> 
> --
> 2.34.1

[PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform

[Mika Kahola]

To bring MTL+ platform aligned call and calculate PLL state
from dpll framework.

v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll().
    The state is computed either for a C10 or on the PTL port B eDP on
    TypeC PHY case for a C20 PHY PLL. Hence refer to this case as
    "non_tc_phy" instead of "c10phy".

    Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for
    symmetry with mtl_compute_non_tc_phy_dpll().
v3: Reword commit message (Suraj)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 23f22c495ec7..20f940110faa 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4319,9 +4319,78 @@ static const struct dpll_info mtl_plls[] = {
 	{}
 };
 
+/*
+ * Compute the state for either a C10 PHY PLL, or in the case of the PTL port B,
+ * eDP on TypeC PHY case for a C20 PHY PLL.
+ */
+static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
+				       struct intel_crtc *crtc,
+				       struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	int ret;
+
+	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+	if (ret)
+		return ret;
+
+	/* this is mainly for the fastset check */
+	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+
+	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
+							      &port_dpll->hw_state.cx0pll);
+
+	return 0;
+}
+
+static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc,
+				    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll;
+	int ret;
+
+	/* TODO: Add state calculation for TBT PLL */
+
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
+	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+	if (ret)
+		return ret;
+
+	/* this is mainly for the fastset check */
+	if (old_crtc_state->intel_dpll &&
+	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+	else
+		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
+
+	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
+							      &port_dpll->hw_state.cx0pll);
+
+	return 0;
+}
+
+static int mtl_compute_dplls(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc,
+			     struct intel_encoder *encoder)
+{
+	if (intel_encoder_is_tc(encoder))
+		return mtl_compute_tc_phy_dplls(state, crtc, encoder);
+	else
+		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
+	.compute_dplls = mtl_compute_dplls,
 };
 
 /**
-- 
2.34.1

RE: [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform

[Kandpal, Suraj]

> Subject: [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform
> 
> To bring MTL+ platform aligned call and calculate PLL state from dpll framework.
> 
> v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll().
>     The state is computed either for a C10 or on the PTL port B eDP on
>     TypeC PHY case for a C20 PHY PLL. Hence refer to this case as
>     "non_tc_phy" instead of "c10phy".
> 
>     Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for
>     symmetry with mtl_compute_non_tc_phy_dpll().
> v3: Reword commit message (Suraj)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 +++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 23f22c495ec7..20f940110faa 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4319,9 +4319,78 @@ static const struct dpll_info mtl_plls[] = {
>  	{}
>  };
> 
> +/*
> + * Compute the state for either a C10 PHY PLL, or in the case of the
> +PTL port B,
> + * eDP on TypeC PHY case for a C20 PHY PLL.

I think you missed to change this to eDP over TypeC

Regards,
Suraj Kandpal

> + */
> +static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
> +				       struct intel_crtc *crtc,
> +				       struct intel_encoder *encoder) {
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	int ret;
> +
> +	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> +	if (ret)
> +		return ret;
> +
> +	/* this is mainly for the fastset check */
> +	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> +
> +	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> +							      &port_dpll-
> >hw_state.cx0pll);
> +
> +	return 0;
> +}
> +
> +static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc,
> +				    struct intel_encoder *encoder)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll;
> +	int ret;
> +
> +	/* TODO: Add state calculation for TBT PLL */
> +
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> +	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> +	if (ret)
> +		return ret;
> +
> +	/* this is mainly for the fastset check */
> +	if (old_crtc_state->intel_dpll &&
> +	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> +		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> +	else
> +		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> +
> +	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> +							      &port_dpll-
> >hw_state.cx0pll);
> +
> +	return 0;
> +}
> +
> +static int mtl_compute_dplls(struct intel_atomic_state *state,
> +			     struct intel_crtc *crtc,
> +			     struct intel_encoder *encoder)
> +{
> +	if (intel_encoder_is_tc(encoder))
> +		return mtl_compute_tc_phy_dplls(state, crtc, encoder);
> +	else
> +		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
> +	.compute_dplls = mtl_compute_dplls,
>  };
> 
>  /**
> --
> 2.34.1

RE: [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 18 November 2025 6.04
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Deak, Imre <imre.deak@intel.com>
> Subject: RE: [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform
> 
> > Subject: [PATCH v2 18/32] drm/i915/cx0: Compute plls for MTL+ platform
> >
> > To bring MTL+ platform aligned call and calculate PLL state from dpll framework.
> >
> > v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll().
> >     The state is computed either for a C10 or on the PTL port B eDP on
> >     TypeC PHY case for a C20 PHY PLL. Hence refer to this case as
> >     "non_tc_phy" instead of "c10phy".
> >
> >     Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for
> >     symmetry with mtl_compute_non_tc_phy_dpll().
> > v3: Reword commit message (Suraj)
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69
> > +++++++++++++++++++
> >  1 file changed, 69 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 23f22c495ec7..20f940110faa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4319,9 +4319,78 @@ static const struct dpll_info mtl_plls[] = {
> >  	{}
> >  };
> >
> > +/*
> > + * Compute the state for either a C10 PHY PLL, or in the case of the
> > +PTL port B,
> > + * eDP on TypeC PHY case for a C20 PHY PLL.
> 
> I think you missed to change this to eDP over TypeC

Yes, probably missed to change this. I will update this as well.

Thanks for spotting!

> 
> Regards,
> Suraj Kandpal
> 
> > + */
> > +static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
> > +				       struct intel_crtc *crtc,
> > +				       struct intel_encoder *encoder) {
> > +	struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	struct icl_port_dpll *port_dpll =
> > +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> > +	int ret;
> > +
> > +	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* this is mainly for the fastset check */
> > +	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> > +
> > +	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> > +							      &port_dpll-
> > >hw_state.cx0pll);
> > +
> > +	return 0;
> > +}
> > +
> > +static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> > +				    struct intel_crtc *crtc,
> > +				    struct intel_encoder *encoder) {
> > +	struct intel_crtc_state *crtc_state =
> > +		intel_atomic_get_new_crtc_state(state, crtc);
> > +	const struct intel_crtc_state *old_crtc_state =
> > +		intel_atomic_get_old_crtc_state(state, crtc);
> > +	struct icl_port_dpll *port_dpll;
> > +	int ret;
> > +
> > +	/* TODO: Add state calculation for TBT PLL */
> > +
> > +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> > +	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> > +	if (ret)
> > +		return ret;
> > +
> > +	/* this is mainly for the fastset check */
> > +	if (old_crtc_state->intel_dpll &&
> > +	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> > +		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> > +	else
> > +		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> > +
> > +	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> > +							      &port_dpll-
> > >hw_state.cx0pll);
> > +
> > +	return 0;
> > +}
> > +
> > +static int mtl_compute_dplls(struct intel_atomic_state *state,
> > +			     struct intel_crtc *crtc,
> > +			     struct intel_encoder *encoder) {
> > +	if (intel_encoder_is_tc(encoder))
> > +		return mtl_compute_tc_phy_dplls(state, crtc, encoder);
> > +	else
> > +		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder); }
> > +
> >  __maybe_unused
> >  static const struct intel_dpll_mgr mtl_pll_mgr = {
> >  	.dpll_info = mtl_plls,
> > +	.compute_dplls = mtl_compute_dplls,
> >  };
> >
> >  /**
> > --
> > 2.34.1

[PATCH v2 19/32] drm/i915/cx0: Add MTL+ .get_dplls hook

[Mika Kahola]

Add .get_dplls function pointer for MTL+ platforms
to support dpll framework. Reuse the ICL function
pointer.

v2: Getting configuration either for a C10 or on the PTL port B
    eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
    case as "non_tc_phy" instead of "c10phy".
v3: Fix comment to "eDP over TypeC" (Suraj)
    Fix pll id as separate variable (Suraj)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 57 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 20f940110faa..313cb244d5d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -203,6 +203,22 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
 }
 
+enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
+{
+	if (port >= PORT_TC1)
+		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
+
+	switch (port) {
+	case PORT_A:
+		return DPLL_ID_ICL_DPLL0;
+	case PORT_B:
+		return DPLL_ID_ICL_DPLL1;
+	default:
+		MISSING_CASE(port);
+		return DPLL_ID_ICL_DPLL0;
+	}
+}
+
 static i915_reg_t
 intel_combo_pll_enable_reg(struct intel_display *display,
 			   struct intel_dpll *pll)
@@ -3490,6 +3506,36 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 	return ret;
 }
 
+/*
+ * Get the PLL for either a port using a C10 PHY PLL, or in the
+ * PTL port B eDP over TypeC PHY case, the PLL for a port using
+ * a C20 PHY PLL.
+ */
+static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc,
+				      struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	enum intel_dpll_id pll_id = mtl_port_to_pll_id(display, encoder->port);
+
+	port_dpll->pll = intel_find_dpll(state, crtc,
+					 &port_dpll->hw_state,
+					 BIT(pll_id));
+	if (!port_dpll->pll)
+		return -EINVAL;
+
+	intel_reference_dpll(state, crtc,
+			     port_dpll->pll, &port_dpll->hw_state);
+
+	icl_update_active_dpll(state, crtc, encoder);
+
+	return 0;
+}
+
 static int icl_compute_dplls(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc,
 			     struct intel_encoder *encoder)
@@ -4387,10 +4433,21 @@ static int mtl_compute_dplls(struct intel_atomic_state *state,
 		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder);
 }
 
+static int mtl_get_dplls(struct intel_atomic_state *state,
+			 struct intel_crtc *crtc,
+			 struct intel_encoder *encoder)
+{
+	if (intel_encoder_is_tc(encoder))
+		return icl_get_tc_phy_dplls(state, crtc, encoder);
+	else
+		return mtl_get_non_tc_phy_dpll(state, crtc, encoder);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
+	.get_dplls = mtl_get_dplls,
 };
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index a7946ff13cb6..322af5c55d7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -450,6 +450,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
 				 const struct intel_dpll_hw_state *a,
 				 const struct intel_dpll_hw_state *b);
 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
+enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port);
 bool intel_dpll_is_combophy(enum intel_dpll_id id);
 
 void intel_dpll_state_verify(struct intel_atomic_state *state,
-- 
2.34.1

RE: [PATCH v2 19/32] drm/i915/cx0: Add MTL+ .get_dplls hook

[Kandpal, Suraj]

> Subject: [PATCH v2 19/32] drm/i915/cx0: Add MTL+ .get_dplls hook
> 
> Add .get_dplls function pointer for MTL+ platforms to support dpll framework.
> Reuse the ICL function pointer.
> 
> v2: Getting configuration either for a C10 or on the PTL port B
>     eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
>     case as "non_tc_phy" instead of "c10phy".
> v3: Fix comment to "eDP over TypeC" (Suraj)
>     Fix pll id as separate variable (Suraj)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 57 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
>  2 files changed, 58 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 20f940110faa..313cb244d5d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -203,6 +203,22 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum
> tc_port tc_port)
>  	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;  }
> 
> +enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display,
> +enum port port) {
> +	if (port >= PORT_TC1)
> +		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
> +
> +	switch (port) {
> +	case PORT_A:
> +		return DPLL_ID_ICL_DPLL0;
> +	case PORT_B:
> +		return DPLL_ID_ICL_DPLL1;
> +	default:
> +		MISSING_CASE(port);
> +		return DPLL_ID_ICL_DPLL0;
> +	}
> +}
> +
>  static i915_reg_t
>  intel_combo_pll_enable_reg(struct intel_display *display,
>  			   struct intel_dpll *pll)
> @@ -3490,6 +3506,36 @@ static int icl_get_tc_phy_dplls(struct
> intel_atomic_state *state,
>  	return ret;
>  }
> 
> +/*
> + * Get the PLL for either a port using a C10 PHY PLL, or in the
> + * PTL port B eDP over TypeC PHY case, the PLL for a port using
> + * a C20 PHY PLL.
> + */
> +static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
> +				      struct intel_crtc *crtc,
> +				      struct intel_encoder *encoder) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	enum intel_dpll_id pll_id = mtl_port_to_pll_id(display,
> +encoder->port);
> +
> +	port_dpll->pll = intel_find_dpll(state, crtc,
> +					 &port_dpll->hw_state,
> +					 BIT(pll_id));
> +	if (!port_dpll->pll)
> +		return -EINVAL;
> +
> +	intel_reference_dpll(state, crtc,
> +			     port_dpll->pll, &port_dpll->hw_state);
> +
> +	icl_update_active_dpll(state, crtc, encoder);
> +
> +	return 0;
> +}
> +
>  static int icl_compute_dplls(struct intel_atomic_state *state,
>  			     struct intel_crtc *crtc,
>  			     struct intel_encoder *encoder)
> @@ -4387,10 +4433,21 @@ static int mtl_compute_dplls(struct
> intel_atomic_state *state,
>  		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder);  }
> 
> +static int mtl_get_dplls(struct intel_atomic_state *state,
> +			 struct intel_crtc *crtc,
> +			 struct intel_encoder *encoder)
> +{
> +	if (intel_encoder_is_tc(encoder))
> +		return icl_get_tc_phy_dplls(state, crtc, encoder);
> +	else
> +		return mtl_get_non_tc_phy_dpll(state, crtc, encoder); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
>  	.compute_dplls = mtl_compute_dplls,
> +	.get_dplls = mtl_get_dplls,
>  };
> 
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index a7946ff13cb6..322af5c55d7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -450,6 +450,7 @@ bool intel_dpll_compare_hw_state(struct intel_display
> *display,
>  				 const struct intel_dpll_hw_state *a,
>  				 const struct intel_dpll_hw_state *b);  enum
> intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> +enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display,
> +enum port port);
>  bool intel_dpll_is_combophy(enum intel_dpll_id id);
> 
>  void intel_dpll_state_verify(struct intel_atomic_state *state,
> --
> 2.34.1

[PATCH v2 20/32] drm/i915/cx0: Add MTL+ .put_dplls hook

[Mika Kahola]

Add .put_dplls function pointer to support MTL+ platforms
on dpll framework. Reuse ICL function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 313cb244d5d6..c45f18201ee8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4448,6 +4448,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
 	.get_dplls = mtl_get_dplls,
+	.put_dplls = icl_put_dplls,
 };
 
 /**
-- 
2.34.1

[PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook

[Mika Kahola]

Add .update_active_dpll function pointer to support
dpll framework. Reuse ICL function pointer.

v2: Add check for !HAS_LT_PHY (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 3 +++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 002ccd47856d..6b43d326e50c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3671,6 +3671,9 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
 	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
 		return;
 
+	if (!HAS_LT_PHY(display))
+		return;
+
 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
 					 intel_crtc_joined_pipe_mask(crtc_state))
 		intel_dpll_update_active(state, pipe_crtc, encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c45f18201ee8..e6dd6f1123d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.compute_dplls = mtl_compute_dplls,
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
+	.update_active_dpll = icl_update_active_dpll,
 };
 
 /**
-- 
2.34.1

RE: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook

[Kandpal, Suraj]

> Subject: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook
> 
> Add .update_active_dpll function pointer to support dpll framework. Reuse ICL
> function pointer.
> 
> v2: Add check for !HAS_LT_PHY (Suraj)

I did not comment asking for this change also brings some questions in my mind here

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 3 +++
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 002ccd47856d..6b43d326e50c 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3671,6 +3671,9 @@ void intel_ddi_update_active_dpll(struct
> intel_atomic_state *state,
>  	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))

So this check here will never let you call dpll_mgr->update_active_dpll hook
So do you not what to remove it.
If the answer is you want to keep this check then you do not need (!HAS_LT_PHY)
If the answer is you need to get this removed only then does it make sense to have this check
And the check should be return if (HAS_LT_PHY())

Regards,
Suraj Kandpal

>  		return;
> 
> +	if (!HAS_LT_PHY(display))
> +		return;
> +
>  	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
> 
> intel_crtc_joined_pipe_mask(crtc_state))
>  		intel_dpll_update_active(state, pipe_crtc, encoder); diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c45f18201ee8..e6dd6f1123d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.compute_dplls = mtl_compute_dplls,
>  	.get_dplls = mtl_get_dplls,
>  	.put_dplls = icl_put_dplls,
> +	.update_active_dpll = icl_update_active_dpll,
>  };
> 
>  /**
> --
> 2.34.1

RE: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 18 November 2025 6.21
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: RE: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook
> 
> > Subject: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll
> > hook
> >
> > Add .update_active_dpll function pointer to support dpll framework.
> > Reuse ICL function pointer.
> >
> > v2: Add check for !HAS_LT_PHY (Suraj)
> 
> I did not comment asking for this change also brings some questions in my mind here
> 
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 3 +++
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 002ccd47856d..6b43d326e50c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3671,6 +3671,9 @@ void intel_ddi_update_active_dpll(struct
> > intel_atomic_state *state,
> >  	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
> 
> So this check here will never let you call dpll_mgr->update_active_dpll hook So do you not what to remove it.
> If the answer is you want to keep this check then you do not need (!HAS_LT_PHY) If the answer is you need to get this
> removed only then does it make sense to have this check And the check should be return if (HAS_LT_PHY())

This is removed from the next version. This change caused a regression on mtl that I didn't spot on my own trials.

I'm proposing to change the check something like this

/* FIXME: Add NVL+ pll_mgr */
if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)
         return;

-Mika-
 
> 
> Regards,
> Suraj Kandpal
> 
> >  		return;
> >
> > +	if (!HAS_LT_PHY(display))
> > +		return;
> > +
> >  	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
> >
> > intel_crtc_joined_pipe_mask(crtc_state))
> >  		intel_dpll_update_active(state, pipe_crtc, encoder); diff --git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index c45f18201ee8..e6dd6f1123d6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
> >  	.compute_dplls = mtl_compute_dplls,
> >  	.get_dplls = mtl_get_dplls,
> >  	.put_dplls = icl_put_dplls,
> > +	.update_active_dpll = icl_update_active_dpll,
> >  };
> >
> >  /**
> > --
> > 2.34.1

RE: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 18 November 2025 6.21
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: RE: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook
> 
> > Subject: [PATCH v2 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll
> > hook
> >
> > Add .update_active_dpll function pointer to support dpll framework.
> > Reuse ICL function pointer.
> >
> > v2: Add check for !HAS_LT_PHY (Suraj)
> 
> I did not comment asking for this change also brings some questions in my mind here

Yes that's right. Your comment was for the last patch of the series but I believe that we should add this check on this patch as this patch adds .update_active_dpll hook. However, this check caused a regression on mtl so this patch is about to be updated. I hold your r-b for version 1 but the upcoming third version will need a review.

-Mika-

> 
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 3 +++
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
> >  2 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 002ccd47856d..6b43d326e50c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3671,6 +3671,9 @@ void intel_ddi_update_active_dpll(struct
> > intel_atomic_state *state,
> >  	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
> 
> So this check here will never let you call dpll_mgr->update_active_dpll hook So do you not what to remove it.
> If the answer is you want to keep this check then you do not need (!HAS_LT_PHY) If the answer is you need to get this
> removed only then does it make sense to have this check And the check should be return if (HAS_LT_PHY())
> 
> Regards,
> Suraj Kandpal
> 
> >  		return;
> >
> > +	if (!HAS_LT_PHY(display))
> > +		return;
> > +
> >  	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
> >
> > intel_crtc_joined_pipe_mask(crtc_state))
> >  		intel_dpll_update_active(state, pipe_crtc, encoder); diff --git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index c45f18201ee8..e6dd6f1123d6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
> >  	.compute_dplls = mtl_compute_dplls,
> >  	.get_dplls = mtl_get_dplls,
> >  	.put_dplls = icl_put_dplls,
> > +	.update_active_dpll = icl_update_active_dpll,
> >  };
> >
> >  /**
> > --
> > 2.34.1

[PATCH v3 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook

[Mika Kahola]

Add .update_active_dpll function pointer to support
dpll framework. Reuse ICL function pointer.

v2: Add check for !HAS_LT_PHY (Suraj)
v3: Remove the incorrect !HAS_LT_PHY condition and
    check for existing dpll_mgr

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 4 ++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 002ccd47856d..40ce117bb088 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3667,8 +3667,8 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_crtc *pipe_crtc;
 
-	/* FIXME: Add MTL pll_mgr */
-	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
+	/* FIXME: Add NVL+ pll_mgr */
+	if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)
 		return;
 
 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c45f18201ee8..e6dd6f1123d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.compute_dplls = mtl_compute_dplls,
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
+	.update_active_dpll = icl_update_active_dpll,
 };
 
 /**
-- 
2.34.1

RE: [PATCH v3 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook

[Kandpal, Suraj]

> Subject: [PATCH v3 21/32] drm/i915/cx0: Add MTL+ .update_active_dpll hook
> 
> Add .update_active_dpll function pointer to support dpll framework. Reuse
> ICL function pointer.
> 
> v2: Add check for !HAS_LT_PHY (Suraj)
> v3: Remove the incorrect !HAS_LT_PHY condition and
>     check for existing dpll_mgr
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
For v2
With the below comments addressed

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 4 ++--
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 002ccd47856d..40ce117bb088 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3667,8 +3667,8 @@ void intel_ddi_update_active_dpll(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_crtc *pipe_crtc;
> 
> -	/* FIXME: Add MTL pll_mgr */
> -	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
> +	/* FIXME: Add NVL+ pll_mgr */

This this need to be for NVL+ and DG2 too


> +	if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)
>  		return;
> 
>  	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c45f18201ee8..e6dd6f1123d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.compute_dplls = mtl_compute_dplls,
>  	.get_dplls = mtl_get_dplls,
>  	.put_dplls = icl_put_dplls,
> +	.update_active_dpll = icl_update_active_dpll,
>  };
> 
>  /**
> --
> 2.34.1

[PATCH v2 22/32] drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook

[Mika Kahola]

Add .update_dpll_ref_clks function pointer to MTL+
platforms to support dpll framework. Reuse ICL
function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index e6dd6f1123d6..32e52babf265 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4450,6 +4450,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
+	.update_ref_clks = icl_update_dpll_ref_clks,
 };
 
 /**
-- 
2.34.1

[PATCH v2 23/32] drm/i915/cx0: Add MTL+ .dump_hw_state hook

[Mika Kahola]

Add .dump_hw_state function pointer for MTL+ platforms
to support dpll framework. While at it, switch to use
drm_printer structure to print hw state information.

v2: Keep debug messages on one line if they not
    necessarily needed to split into two or more
    lines (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 70 +++++++++----------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  3 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  5 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 ++
 4 files changed, 45 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index de71805a065c..a88169b76cfa 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2297,7 +2297,7 @@ static void intel_c10_pll_program(struct intel_display *display,
 	intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);
 }
 
-static void intel_c10pll_dump_hw_state(struct intel_display *display,
+static void intel_c10pll_dump_hw_state(struct drm_printer *p,
 				       const struct intel_c10pll_state *hw_state)
 {
 	bool fracen;
@@ -2306,33 +2306,32 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
 	unsigned int multiplier, tx_clk_div;
 
 	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
-	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
-		    hw_state->clock, str_yes_no(fracen));
+	drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
+		   hw_state->clock, str_yes_no(fracen));
 
 	if (fracen) {
 		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
 		frac_rem =  hw_state->pll[14] << 8 | hw_state->pll[13];
 		frac_den =  hw_state->pll[10] << 8 | hw_state->pll[9];
-		drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
-			    frac_quot, frac_rem, frac_den);
+		drm_printf(p, "quot: %u, rem: %u, den: %u,\n",
+			   frac_quot, frac_rem, frac_den);
 	}
 
 	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
 		      hw_state->pll[2]) / 2 + 16;
 	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
-	drm_dbg_kms(display->drm,
-		    "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
+	drm_printf(p,
+		   "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
 
-	drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
-	drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
-		    hw_state->cmn);
+	drm_printf(p, "c10pll_rawhw_state:");
+	drm_printf(p, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
 
 	BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
 	for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
-		drm_dbg_kms(display->drm,
-			    "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
-			    i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
-			    i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
+		drm_printf(p,
+			   "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+			   i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
+			   i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
 }
 
 /*
@@ -2813,49 +2812,48 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));
 }
 
-static void intel_c20pll_dump_hw_state(struct intel_display *display,
+static void intel_c20pll_dump_hw_state(struct drm_printer *p,
 				       const struct intel_c20pll_state *hw_state)
 {
 	int i;
 
-	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
-	drm_dbg_kms(display->drm,
-		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
-		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
-	drm_dbg_kms(display->drm,
-		    "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
-		    hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
+	drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
+	drm_printf(p,
+		   "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
+		   hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
+	drm_printf(p,
+		   "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
+		   hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
 
 	if (intel_c20phy_use_mpllb(hw_state)) {
 		for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
-			drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
-				    hw_state->mpllb[i]);
+			drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
 	} else {
 		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
-			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
-				    hw_state->mplla[i]);
+			drm_printf(p, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
 
 		/* For full coverage, also print the additional PLL B entry. */
 		BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb));
-		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+		drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
 	}
 
-	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
-		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
+	drm_printf(p,
+		   "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
+		   hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
 }
 
-void intel_cx0pll_dump_hw_state(struct intel_display *display,
+void intel_cx0pll_dump_hw_state(struct drm_printer *p,
 				const struct intel_cx0pll_state *hw_state)
 {
-	drm_dbg_kms(display->drm,
-		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
-		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
-		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
+	drm_printf(p,
+		   "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
+		   hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
+		   str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
 
 	if (hw_state->use_c10)
-		intel_c10pll_dump_hw_state(display, &hw_state->c10);
+		intel_c10pll_dump_hw_state(p, &hw_state->c10);
 	else
-		intel_c20pll_dump_hw_state(display, &hw_state->c20);
+		intel_c20pll_dump_hw_state(p, &hw_state->c20);
 }
 
 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index d52e864f5e19..acfbaced22f5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -11,6 +11,7 @@
 #define MB_WRITE_COMMITTED      true
 #define MB_WRITE_UNCOMMITTED    false
 
+struct drm_printer;
 enum icl_port_dpll_id;
 struct intel_atomic_state;
 struct intel_c10pll_state;
@@ -41,7 +42,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_cx0pll_state *pll_state);
 
-void intel_cx0pll_dump_hw_state(struct intel_display *display,
+void intel_cx0pll_dump_hw_state(struct drm_printer *p,
 				const struct intel_cx0pll_state *hw_state);
 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 069967114bd9..e7bb8ec0d6bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4984,15 +4984,14 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
 			    const struct intel_cx0pll_state *a,
 			    const struct intel_cx0pll_state *b)
 {
-	struct intel_display *display = to_intel_display(crtc);
 	char *chipname = a->use_c10 ? "C10" : "C20";
 
 	pipe_config_mismatch(p, fastset, crtc, name, chipname);
 
 	drm_printf(p, "expected:\n");
-	intel_cx0pll_dump_hw_state(display, a);
+	intel_cx0pll_dump_hw_state(p, a);
 	drm_printf(p, "found:\n");
-	intel_cx0pll_dump_hw_state(display, b);
+	intel_cx0pll_dump_hw_state(p, b);
 }
 
 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 32e52babf265..aee8f1a5848a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4443,6 +4443,12 @@ static int mtl_get_dplls(struct intel_atomic_state *state,
 		return mtl_get_non_tc_phy_dpll(state, crtc, encoder);
 }
 
+static void mtl_dump_hw_state(struct drm_printer *p,
+			      const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
@@ -4451,6 +4457,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
 	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = mtl_dump_hw_state,
 };
 
 /**
-- 
2.34.1

[PATCH v2 24/32] drm/i915/cx0: Add .compare_hw_state hook

[Mika Kahola]

Add .compare_hw_state function pointer for MTL+ platforms
to support dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index aee8f1a5848a..c0ba269dc714 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,6 +4449,15 @@ static void mtl_dump_hw_state(struct drm_printer *p,
 	intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll);
 }
 
+static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a,
+				 const struct intel_dpll_hw_state *_b)
+{
+	const struct intel_cx0pll_state *a = &_a->cx0pll;
+	const struct intel_cx0pll_state *b = &_b->cx0pll;
+
+	return intel_cx0pll_compare_hw_state(a, b);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
@@ -4458,6 +4467,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.update_active_dpll = icl_update_active_dpll,
 	.update_ref_clks = icl_update_dpll_ref_clks,
 	.dump_hw_state = mtl_dump_hw_state,
+	.compare_hw_state = mtl_compare_hw_state,
 };
 
 /**
-- 
2.34.1

[PATCH v2 25/32] drm/i915/cx0: Add MTL+ .get_hw_state hook

[Mika Kahola]

Add .get_hw_state hook to MTL+ platforms for dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  9 ++++--
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++++
 3 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a88169b76cfa..bde461878647 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3594,19 +3594,24 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 		return ICL_PORT_DPLL_DEFAULT;
 }
 
-void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
+bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state)
 {
 	memset(pll_state, 0, sizeof(*pll_state));
 
 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
 	if (pll_state->tbt_mode)
-		return;
+		return true;
+
+	if (!intel_cx0_pll_is_enabled(encoder))
+		return false;
 
 	if (intel_encoder_is_c10phy(encoder))
 		intel_c10pll_readout_hw_state(encoder, pll_state);
 	else
 		intel_c20pll_readout_hw_state(encoder, pll_state);
+
+	return true;
 }
 
 static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index acfbaced22f5..37b53faa5e78 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -37,7 +37,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder,
 			    struct intel_dpll_hw_state *hw_state);
-void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
+bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state);
 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_cx0pll_state *pll_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c0ba269dc714..beaf270294ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4351,7 +4351,36 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
 	.compare_hw_state = icl_compare_hw_state,
 };
 
+static struct intel_encoder *get_intel_encoder(struct intel_display *display,
+					       const struct intel_dpll *pll)
+{
+	struct intel_encoder *encoder;
+	enum intel_dpll_id mtl_id;
+
+	for_each_intel_encoder(display->drm, encoder) {
+		mtl_id = mtl_port_to_pll_id(display, encoder->port);
+
+		if (mtl_id == pll->info->id)
+			return encoder;
+	}
+
+	return NULL;
+}
+
+static bool mtl_pll_get_hw_state(struct intel_display *display,
+				 struct intel_dpll *pll,
+				 struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (!encoder)
+		return false;
+
+	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll);
+}
+
 static const struct intel_dpll_funcs mtl_pll_funcs = {
+	.get_hw_state = mtl_pll_get_hw_state,
 };
 
 static const struct dpll_info mtl_plls[] = {
-- 
2.34.1

Re: [PATCH v2 25/32] drm/i915/cx0: Add MTL+ .get_hw_state hook

[Gustavo Sousa]

Mika Kahola <mika.kahola@intel.com> writes:

> Add .get_hw_state hook to MTL+ platforms for dpll framework.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  9 ++++--
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++++
>  3 files changed, 37 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a88169b76cfa..bde461878647 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3594,19 +3594,24 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
>  		return ICL_PORT_DPLL_DEFAULT;
>  }
>  
> -void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state)
>  {
>  	memset(pll_state, 0, sizeof(*pll_state));
>  
>  	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
>  	if (pll_state->tbt_mode)
> -		return;
> +		return true;
> +
> +	if (!intel_cx0_pll_is_enabled(encoder))
> +		return false;
>  
>  	if (intel_encoder_is_c10phy(encoder))
>  		intel_c10pll_readout_hw_state(encoder, pll_state);
>  	else
>  		intel_c20pll_readout_hw_state(encoder, pll_state);
> +
> +	return true;
>  }
>  
>  static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index acfbaced22f5..37b53faa5e78 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -37,7 +37,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
>  int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder,
>  			    struct intel_dpll_hw_state *hw_state);
> -void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state);
>  int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
>  				 const struct intel_cx0pll_state *pll_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c0ba269dc714..beaf270294ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4351,7 +4351,36 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>  	.compare_hw_state = icl_compare_hw_state,
>  };
>  
> +static struct intel_encoder *get_intel_encoder(struct intel_display *display,
> +					       const struct intel_dpll *pll)
> +{
> +	struct intel_encoder *encoder;
> +	enum intel_dpll_id mtl_id;
> +
> +	for_each_intel_encoder(display->drm, encoder) {
> +		mtl_id = mtl_port_to_pll_id(display, encoder->port);
> +
> +		if (mtl_id == pll->info->id)
> +			return encoder;
> +	}
> +
> +	return NULL;
> +}
> +
> +static bool mtl_pll_get_hw_state(struct intel_display *display,
> +				 struct intel_dpll *pll,
> +				 struct intel_dpll_hw_state *dpll_hw_state)
> +{
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (!encoder)
> +		return false;

I came accross this code recently and I'm wondering why we need to have
this null check here.

Are there scenarios where this is possible? If so, are those possible
only starting with Xe_LPDplus?

--
Gustavo Sousa

> +
> +	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll);
> +}
> +
>  static const struct intel_dpll_funcs mtl_pll_funcs = {
> +	.get_hw_state = mtl_pll_get_hw_state,
>  };
>  
>  static const struct dpll_info mtl_plls[] = {
> -- 
> 2.34.1

RE: [PATCH v2 25/32] drm/i915/cx0: Add MTL+ .get_hw_state hook

[Kahola, Mika]

> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Tuesday, 21 April 2026 2.19
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: Re: [PATCH v2 25/32] drm/i915/cx0: Add MTL+ .get_hw_state hook
> 
> Mika Kahola <mika.kahola@intel.com> writes:
> 
> > Add .get_hw_state hook to MTL+ platforms for dpll framework.
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  9 ++++--
> > drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +-
> > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++++
> >  3 files changed, 37 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index a88169b76cfa..bde461878647 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3594,19 +3594,24 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
> >  		return ICL_PORT_DPLL_DEFAULT;
> >  }
> >
> > -void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> > +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> >  				   struct intel_cx0pll_state *pll_state)  {
> >  	memset(pll_state, 0, sizeof(*pll_state));
> >
> >  	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> >  	if (pll_state->tbt_mode)
> > -		return;
> > +		return true;
> > +
> > +	if (!intel_cx0_pll_is_enabled(encoder))
> > +		return false;
> >
> >  	if (intel_encoder_is_c10phy(encoder))
> >  		intel_c10pll_readout_hw_state(encoder, pll_state);
> >  	else
> >  		intel_c20pll_readout_hw_state(encoder, pll_state);
> > +
> > +	return true;
> >  }
> >
> >  static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state
> > *a, diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index acfbaced22f5..37b53faa5e78 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -37,7 +37,7 @@ intel_mtl_port_pll_type(struct intel_encoder
> > *encoder,  int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> >  			    struct intel_encoder *encoder,
> >  			    struct intel_dpll_hw_state *hw_state); -void
> > intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> > +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> >  				   struct intel_cx0pll_state *pll_state);  int
> > intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
> >  				 const struct intel_cx0pll_state *pll_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index c0ba269dc714..beaf270294ca 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4351,7 +4351,36 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
> >  	.compare_hw_state = icl_compare_hw_state,  };
> >
> > +static struct intel_encoder *get_intel_encoder(struct intel_display *display,
> > +					       const struct intel_dpll *pll) {
> > +	struct intel_encoder *encoder;
> > +	enum intel_dpll_id mtl_id;
> > +
> > +	for_each_intel_encoder(display->drm, encoder) {
> > +		mtl_id = mtl_port_to_pll_id(display, encoder->port);
> > +
> > +		if (mtl_id == pll->info->id)
> > +			return encoder;
> > +	}
> > +
> > +	return NULL;
> > +}
> > +
> > +static bool mtl_pll_get_hw_state(struct intel_display *display,
> > +				 struct intel_dpll *pll,
> > +				 struct intel_dpll_hw_state *dpll_hw_state) {
> > +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> > +
> > +	if (!encoder)
> > +		return false;
> 
> I came accross this code recently and I'm wondering why we need to have this null check here.
> 
> Are there scenarios where this is possible? If so, are those possible only starting with Xe_LPDplus?
> 

During the testing I noticed that this .get_hw_state hook gets called a bit too early when encoder is not yet in place. Hence this check was added to bail out early if encoder is not found. Otherwise (without !encoder check), we would see the following error

[   10.756807] xe 0000:00:02.0: [drm:intel_dpll_readout_hw_state [xe]] DPLL 0 hw state readout: pipe_mask 0x1, on 1
[   10.756904] BUG: kernel NULL pointer dereference, address: 0000000000000000
[   10.764090] #PF: supervisor read access in kernel mode
[   10.769274] #PF: error_code(0x0000) - not-present page
[   10.774471] PGD 0 P4D 0
[   10.777035] Oops: Oops: 0000 [#1] SMP NOPTI
[   10.781253] CPU: 3 UID: 0 PID: 394 Comm: (udev-worker) Tainted: G     U              7.0.0-mika+ #2 PREEMPT(full)
[   10.791689] Tainted: [U]=USER
[   10.796079] Hardware name: Intel Corporation Panther Lake Client Platform/PTL-UH LP5 T3 RVP1, BIOS PTLPFWI1.R00.3514.D01.2512291130 12/29/2025
[   10.808947] RIP: 0010:intel_cx0_pll_is_enabled+0x10/0x140 [xe]
[   10.816324] Code: eb 80 0f 1f 84 00 00 00 00 00 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 55 48 89 e5 41 56 41 55 41 54 53 <4c> 8b 2f 48 89 fb 4d 85 ed 74 0b 4c 89 ef e8 7d da 02 00 49 89 c5
[   10.835224] RSP: 0018:ffffc900022eb5a0 EFLAGS: 00010282
[   10.840494] RAX: 0000000000000000 RBX: ffff888107f22e0c RCX: 0000000000000000
[   10.847682] RDX: 0000000000000000 RSI: ffff888107f22e0c RDI: 0000000000000000
[   10.854880] RBP: ffffc900022eb5c0 R08: 0000000000000000 R09: 0000000000000000
[   10.862072] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000000
[   10.869258] R13: 0000000000000001 R14: ffff888107f22070 R15: ffff888107f22000
[   10.876451] FS:  000078583be768c0(0000) GS:ffff8884eb550000(0000) knlGS:0000000000000000
[   10.884602] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[   10.890420] CR2: 0000000000000000 CR3: 0000000114e2a002 CR4: 0000000000f72ef0
[   10.897611] PKRU: 55555554
[   10.900346] Call Trace:
[   10.902816]  <TASK>
[   10.904945]  intel_cx0pll_readout_hw_state+0x4c/0x5b0 [xe]
[   10.911988]  mtl_pll_get_hw_state+0x1d/0x30 [xe]
[   10.916744]  intel_dpll_readout_hw_state+0x78/0x270 [xe]
[   10.922702]  intel_modeset_setup_hw_state+0x451/0x1ee0 [xe]
[   10.928408]  ? drm_modeset_lock+0x90/0x110
[   10.932552]  intel_display_driver_probe_nogem+0x150/0x1c0 [xe]
[   10.938556]  ? intel_display_driver_probe_nogem+0x150/0x1c0 [xe]
[   10.944721]  xe_display_init_early+0xa8/0x130 [xe]
[   10.949686]  xe_device_probe+0x3e1/0xb50 [xe]
[   10.954198]  xe_pci_probe+0xd96/0x10c0 [xe]
[   10.958527]  local_pci_probe+0x47/0xb0
[   10.962321]  pci_device_probe+0xfd/0x260
[   10.966283]  ? sysfs_create_link+0x21/0x50
[   10.970440]  really_probe+0xf1/0x410
[   10.974070]  __driver_probe_device+0x8c/0x190
[   10.978464]  driver_probe_device+0x24/0xd0
[   10.982618]  __driver_attach+0x10b/0x240
[   10.986585]  ? __pfx___driver_attach+0x10/0x10
[   10.991066]  bus_for_each_dev+0x7c/0xe0
[   10.994944]  driver_attach+0x1e/0x30
[   10.998556]  bus_add_driver+0x160/0x2a0
[   11.002434]  driver_register+0x5e/0x130
[   11.006301]  __pci_register_driver+0x5e/0x70
[   11.010604]  xe_register_pci_driver+0x23/0x30 [xe]
[   11.015548]  xe_init+0x2c/0x110 [xe]
[   11.019248]  ? __pfx_xe_init+0x10/0x10 [xe]
[   11.023556]  do_one_initcall+0x4b/0x350
[   11.027429]  ? do_init_module+0x56/0x2b0
[   11.031400]  ? __kmalloc_cache_noprof+0x228/0x450
[   11.036152]  do_init_module+0x97/0x2b0
[   11.039937]  load_module+0x2ce6/0x2ea0
[   11.043727]  ? kernel_read_file+0x2b1/0x320
[   11.047950]  init_module_from_file+0xf4/0x120
[   11.052349]  ? init_module_from_file+0xf4/0x120
[   11.056929]  idempotent_init_module+0xfc/0x2f0
[   11.061417]  __x64_sys_finit_module+0x73/0xf0
[   11.065844]  x64_sys_call+0x106d/0x26e0
[   11.069748]  do_syscall_64+0xcb/0x14d0
[   11.073545]  ? do_syscall_64+0x2c0/0x14d0
[   11.077603]  ? do_syscall_64+0x109/0x14d0
[   11.081649]  ? __x64_sys_newfstatat+0x1c/0x30
[   11.086049]  ? x64_sys_call+0x201d/0x26e0
[   11.090107]  ? do_syscall_64+0x109/0x14d0
[   11.094162]  entry_SYSCALL_64_after_hwframe+0x76/0x7e
[   11.099259] RIP: 0033:0x78583bd2728d
[   11.102865] Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 5b bb 0d 00 f7 d8 64 89 01 48
[   11.121766] RSP: 002b:00007ffe7858abe8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
[   11.129392] RAX: ffffffffffffffda RBX: 000061a0a3e4cab0 RCX: 000078583bd2728d
[   11.136592] RDX: 0000000000000000 RSI: 000061a0a3e492d0 RDI: 000000000000003c
[   11.143800] RBP: 00007ffe7858aca0 R08: 0000000000000040 R09: 00007ffe7858ac30
[   11.150989] R10: 000078583be03b20 R11: 0000000000000246 R12: 000061a0a3e492d0
[   11.158177] R13: 0000000000020000 R14: 000061a0a3e49220 R15: 000061a0a3e4e9c0
[   11.165377]  </TASK>
[   11.167584] Modules linked in: intel_uncore_frequency intel_uncore_frequency_common x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel binfmt_misc cmdlinepart intel_rapl_msr intel_pmc_core spi_nor kvm xe(+) wmi_bmof mtd mei_gsc_proxy drm_gpusvm_helper irqbypass pmt_telemetry drm_gpuvm drm_buddy snd_hda_intel drm_ttm_helper ttm processor_thermal_device_pci gpu_sched snd_intel_dspcfg processor_thermal_device pmt_discovery drm_suballoc_helper processor_thermal_wt_hint ucsi_acpi snd_hda_codec platform_temperature_control drm_exec processor_thermal_soc_slider drm_display_helper snd_hda_core ghash_clmulni_intel intel_skl_int3472_tps68470 platform_profile snd_hwdep tps68470_regulator processor_thermal_rfim cec pmt_class snd_pcm processor_thermal_rapl typec_ucsi aesni_intel intel_rapl_common snd_timer rc_core clk_tps68470 typec processor_thermal_wt_req processor_thermal_power_floor snd int3403_thermal i2c_algo_bit processor_thermal_mbox nls_iso8859_1 video intel_cstate soundcore e1000e thunderbolt intel_vpu
[   11.167613]  int340x_thermal_zone intel_pmc_ssram_telemetry intel_ish_ipc i2c_i801 mei_me wmi int3400_thermal mei intel_skl_int3472_discrete acpi_thermal_rel intel_ishtp intel_skl_int3472_common spi_intel_pci spi_intel igen6_edac i2c_mux pinctrl_intel_platform i2c_smbus intel_hid intel_vsec idma64 sparse_keymap acpi_tad acpi_pad dm_multipath msr fuse efi_pstore nfnetlink autofs4
[   11.290996] CR2: 0000000000000000
[   11.294354] ---[ end trace 0000000000000000 ]---

> --
> Gustavo Sousa
> 
> > +
> > +	return intel_cx0pll_readout_hw_state(encoder,
> > +&dpll_hw_state->cx0pll); }
> > +
> >  static const struct intel_dpll_funcs mtl_pll_funcs = {
> > +	.get_hw_state = mtl_pll_get_hw_state,
> >  };
> >
> >  static const struct dpll_info mtl_plls[] = {
> > --
> > 2.34.1

[PATCH v2 26/32] drm/i915/cx0: Add MTL+ .get_freq hook

[Mika Kahola]

Add .get_freq hook to support dpll framework for MTL+
platforms.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index beaf270294ca..85b3fee2d9b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4379,8 +4379,21 @@ static bool mtl_pll_get_hw_state(struct intel_display *display,
 	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll);
 }
 
+static int mtl_pll_get_freq(struct intel_display *display,
+			    const struct intel_dpll *pll,
+			    const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return -EINVAL;
+
+	return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
+}
+
 static const struct intel_dpll_funcs mtl_pll_funcs = {
 	.get_hw_state = mtl_pll_get_hw_state,
+	.get_freq = mtl_pll_get_freq,
 };
 
 static const struct dpll_info mtl_plls[] = {
-- 
2.34.1

[PATCH v2 27/32] drm/i915/cx0: Add MTL+ .crtc_get_dpll hook

[Mika Kahola]

Add .crtc_get_dpll function pointer to support MTL+
platforms.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 342d46b7b1af..2da65bb20f1c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1720,6 +1720,7 @@ static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
 
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
 	.crtc_compute_clock = mtl_crtc_compute_clock,
+	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
 static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
-- 
2.34.1

[PATCH v2 28/32] drm/i915/cx0: PLL verify debug state print

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Print out hw and sw pll states for better debugging support.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 85b3fee2d9b6..463677014199 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4882,11 +4882,18 @@ verify_single_dpll_state(struct intel_display *display,
 				 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
 				 pll->info->name, pipe_mask, pll->state.pipe_mask);
 
-	INTEL_DISPLAY_STATE_WARN(display,
-				 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
-						   sizeof(dpll_hw_state)),
-				 "%s: pll hw state mismatch\n",
-				 pll->info->name);
+	if (INTEL_DISPLAY_STATE_WARN(display,
+				     pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
+						       sizeof(dpll_hw_state)),
+				     "%s: pll hw state mismatch\n",
+				     pll->info->name)) {
+		struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+
+		drm_printf(&p, "PLL %s HW state:\n", pll->info->name);
+		intel_dpll_dump_hw_state(display, &p, &dpll_hw_state);
+		drm_printf(&p, "PLL %s SW state:\n", pll->info->name);
+		intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
+	}
 }
 
 static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
-- 
2.34.1

[PATCH v2 29/32] drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI

[Mika Kahola]

To enable pll clock on DDI move part of the pll enabling
sequence into a ddi clock enabling function.

Simililarly, do the same for pll disabling sequence.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 34 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  | 11 +++++-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  4 +--
 5 files changed, 64 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index bde461878647..79be234780ba 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3280,7 +3280,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * Frequency Change. We handle this step in bxt_set_cdclk().
 	 */
 
-	/* TODO: enable TBT-ALT mode */
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
@@ -3346,8 +3345,7 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
 	}
 }
 
-void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
-			      const struct intel_crtc_state *crtc_state)
+void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3361,7 +3359,7 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 
 	mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);
 	val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
-					    intel_mtl_tbt_clock_select(display, crtc_state->port_clock));
+					    intel_mtl_tbt_clock_select(display, port_clock));
 
 	mask |= XELPDP_FORWARD_CLOCK_UNGATE;
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
@@ -3399,18 +3397,26 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 	 * clock frequency.
 	 */
 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
-		       crtc_state->port_clock);
+		       port_clock);
 }
 
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
-			  const struct intel_crtc_state *crtc_state)
+			  struct intel_dpll *pll,
+			  const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll);
+}
+
+void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		intel_mtl_tbt_pll_enable(encoder, crtc_state);
+		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
 	else
-		intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll);
+		/* TODO: remove when PLL mgr is in place. */
+		intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 /*
@@ -3525,7 +3531,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
 			     intel_cx0_get_pclk_pll_request(lane);
 }
 
-void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
+void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3564,13 +3570,19 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 }
 
 void intel_mtl_pll_disable(struct intel_encoder *encoder)
+{
+	intel_cx0pll_disable(encoder);
+}
+
+void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		intel_mtl_tbt_pll_disable(encoder);
+		intel_mtl_tbt_pll_disable_clock(encoder);
 	else
-		intel_cx0pll_disable(encoder);
+		/* TODO: remove when PLL mgr is in place. */
+		intel_mtl_pll_disable(encoder);
 }
 
 enum icl_port_dpll_id
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 37b53faa5e78..3745d7081ac7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -20,6 +20,7 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_cx0pll_state;
 struct intel_display;
+struct intel_dpll;
 struct intel_dpll_hw_state;
 struct intel_encoder;
 struct intel_hdmi;
@@ -28,11 +29,19 @@ void intel_clear_response_ready_flag(struct intel_encoder *encoder,
 				     int lane);
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
-			  const struct intel_crtc_state *crtc_state);
+			  struct intel_dpll *pll,
+			  const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_mtl_pll_disable(struct intel_encoder *encoder);
 enum icl_port_dpll_id
 intel_mtl_port_pll_type(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state);
+void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state);
+void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
+void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
+void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder,
+				    int port_clock);
+void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder);
 
 int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6b43d326e50c..be25a6fdd491 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -89,6 +89,8 @@
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 
+struct intel_dpll;
+
 static const u8 index_to_dp_signal_levels[] = {
 	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
 	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
@@ -5255,8 +5257,8 @@ void intel_ddi_init(struct intel_display *display,
 		encoder->port_pll_type = intel_mtl_port_pll_type;
 		encoder->get_config = xe3plpd_ddi_get_config;
 	} else if (DISPLAY_VER(display) >= 14) {
-		encoder->enable_clock = intel_mtl_pll_enable;
-		encoder->disable_clock = intel_mtl_pll_disable;
+		encoder->enable_clock = intel_mtl_pll_enable_clock;
+		encoder->disable_clock = intel_mtl_pll_disable_clock;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
 		encoder->get_config = mtl_ddi_get_config;
 	} else if (display->platform.dg2) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 463677014199..ecb7e3761a5b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4391,7 +4391,32 @@ static int mtl_pll_get_freq(struct intel_display *display,
 	return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
 }
 
+static void mtl_pll_enable(struct intel_display *display,
+			   struct intel_dpll *pll,
+			   const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return;
+
+	intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
+}
+
+static void mtl_pll_disable(struct intel_display *display,
+			    struct intel_dpll *pll)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return;
+
+	intel_mtl_pll_disable(encoder);
+}
+
 static const struct intel_dpll_funcs mtl_pll_funcs = {
+	.enable = mtl_pll_enable,
+	.disable = mtl_pll_disable,
 	.get_hw_state = mtl_pll_get_hw_state,
 	.get_freq = mtl_pll_get_freq,
 };
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index a67eb4f7f897..aaf5a2433690 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2310,7 +2310,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		intel_mtl_tbt_pll_enable(encoder, crtc_state);
+		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
 	else
 		intel_lt_phy_pll_enable(encoder, crtc_state);
 }
@@ -2320,7 +2320,7 @@ void intel_xe3plpd_pll_disable(struct intel_encoder *encoder)
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		intel_mtl_tbt_pll_disable(encoder);
+		intel_mtl_tbt_pll_disable_clock(encoder);
 	else
 		intel_lt_phy_pll_disable(encoder);
 
-- 
2.34.1

[PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs

[Mika Kahola]

For DDI initialization get configuration for C10 and C20
chips.

v2: Getting configuration either for a C10 or on the PTL port B
    eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
    case as "non_tc_phy" instead of "c10phy".

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 81 ++++++++++++++++++++++--
 1 file changed, 75 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index be25a6fdd491..689bd3224919 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4273,6 +4273,77 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
+static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
+{
+	return pll->info->id == DPLL_ID_ICL_TBTPLL;
+}
+
+static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
+				   struct intel_crtc_state *crtc_state,
+				   enum icl_port_dpll_id port_dpll_id,
+				   enum intel_dpll_id pll_id)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct icl_port_dpll *port_dpll;
+	struct intel_dpll *pll;
+	bool pll_active;
+
+	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
+	pll = intel_get_dpll_by_id(display, pll_id);
+
+	if (drm_WARN_ON(display->drm, !pll))
+		return;
+
+	port_dpll->pll = pll;
+	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+	drm_WARN_ON(display->drm, !pll_active);
+
+	icl_set_active_port_dpll(crtc_state, port_dpll_id);
+
+	if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
+		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
+	else
+		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
+							     &crtc_state->dpll_hw_state);
+
+	intel_ddi_get_config(encoder, crtc_state);
+}
+
+/*
+ * Get the configuration for either a port using a C10 PHY PLL, or in the case of
+ * the PTL port B eDP on TypeC PHY case the configuration of a port using a C20
+ * PHY PLL.
+ */
+static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
+					     struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	/* TODO: Remove when the PLL manager is in place. */
+	mtl_ddi_get_config(encoder, crtc_state);
+	return;
+
+	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
+			       mtl_port_to_pll_id(display, encoder->port));
+}
+
+static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
+				      struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	/* TODO: Remove when the PLL manager is in place. */
+	mtl_ddi_get_config(encoder, crtc_state);
+	return;
+
+	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
+		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
+				       DPLL_ID_ICL_TBTPLL);
+	else
+		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY,
+				       mtl_port_to_pll_id(display, encoder->port));
+}
+
 static void dg2_ddi_get_config(struct intel_encoder *encoder,
 				struct intel_crtc_state *crtc_state)
 {
@@ -4310,11 +4381,6 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
-static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
-{
-	return pll->info->id == DPLL_ID_ICL_TBTPLL;
-}
-
 static enum icl_port_dpll_id
 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state)
@@ -5260,7 +5326,10 @@ void intel_ddi_init(struct intel_display *display,
 		encoder->enable_clock = intel_mtl_pll_enable_clock;
 		encoder->disable_clock = intel_mtl_pll_disable_clock;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
-		encoder->get_config = mtl_ddi_get_config;
+		if (intel_encoder_is_tc(encoder))
+			encoder->get_config = mtl_ddi_tc_phy_get_config;
+		else
+			encoder->get_config = mtl_ddi_non_tc_phy_get_config;
 	} else if (display->platform.dg2) {
 		encoder->enable_clock = intel_mpllb_enable;
 		encoder->disable_clock = intel_mpllb_disable;
-- 
2.34.1

RE: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs

[Kandpal, Suraj]

> Subject: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10
> and C20 PHY PLLs
> 
> For DDI initialization get configuration for C10 and C20 chips.
> 
> v2: Getting configuration either for a C10 or on the PTL port B
>     eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
>     case as "non_tc_phy" instead of "c10phy".
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 81 ++++++++++++++++++++++--
>  1 file changed, 75 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index be25a6fdd491..689bd3224919 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4273,6 +4273,77 @@ static void mtl_ddi_get_config(struct intel_encoder
> *encoder,
>  	intel_ddi_get_config(encoder, crtc_state);  }
> 
> +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) {
> +	return pll->info->id == DPLL_ID_ICL_TBTPLL; }
> +
> +static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
> +				   struct intel_crtc_state *crtc_state,
> +				   enum icl_port_dpll_id port_dpll_id,
> +				   enum intel_dpll_id pll_id)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct icl_port_dpll *port_dpll;
> +	struct intel_dpll *pll;
> +	bool pll_active;
> +
> +	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
> +	pll = intel_get_dpll_by_id(display, pll_id);
> +
> +	if (drm_WARN_ON(display->drm, !pll))
> +		return;
> +
> +	port_dpll->pll = pll;
> +	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
> +	drm_WARN_ON(display->drm, !pll_active);
> +
> +	icl_set_active_port_dpll(crtc_state, port_dpll_id);
> +
> +	if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
> +		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> +	else
> +		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> >intel_dpll,
> +							     &crtc_state-
> >dpll_hw_state);
> +
> +	intel_ddi_get_config(encoder, crtc_state); }
> +
> +/*
> + * Get the configuration for either a port using a C10 PHY PLL, or in
> +the case of
> + * the PTL port B eDP on TypeC PHY case the configuration of a port
> +using a C20
> + * PHY PLL.
> + */
> +static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
> +					     struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	/* TODO: Remove when the PLL manager is in place. */

Is the comment needed anymore

> +	mtl_ddi_get_config(encoder, crtc_state);
> +	return;

Why the early return code after this point then serves no purpose.

> +
> +	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
> +			       mtl_port_to_pll_id(display, encoder->port)); }

Have the pll id in its own variable.

> +
> +static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
> +				      struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	/* TODO: Remove when the PLL manager is in place. */

No need for this comment

> +	mtl_ddi_get_config(encoder, crtc_state);
> +	return;

Same question  why the early return ?

> +
> +	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
> +		mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_DEFAULT,
> +				       DPLL_ID_ICL_TBTPLL);
> +	else
> +		mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_MG_PHY,
> +				       mtl_port_to_pll_id(display, encoder-
> >port)); }

You can have the pll id as its one variable
In fact you can call mtl_ddi_cx0_get_config just once if you have both port and pll id variables assigned
After checking if intel_tc_port_in_tbt_alt_mode

Regards,
Suraj Kandpal

> +
>  static void dg2_ddi_get_config(struct intel_encoder *encoder,
>  				struct intel_crtc_state *crtc_state)  { @@ -
> 4310,11 +4381,6 @@ static void icl_ddi_combo_get_config(struct
> intel_encoder *encoder,
>  	intel_ddi_get_config(encoder, crtc_state);  }
> 
> -static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) -{
> -	return pll->info->id == DPLL_ID_ICL_TBTPLL;
> -}
> -
>  static enum icl_port_dpll_id
>  icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
>  			 const struct intel_crtc_state *crtc_state) @@ -5260,7
> +5326,10 @@ void intel_ddi_init(struct intel_display *display,
>  		encoder->enable_clock = intel_mtl_pll_enable_clock;
>  		encoder->disable_clock = intel_mtl_pll_disable_clock;
>  		encoder->port_pll_type = intel_mtl_port_pll_type;
> -		encoder->get_config = mtl_ddi_get_config;
> +		if (intel_encoder_is_tc(encoder))
> +			encoder->get_config = mtl_ddi_tc_phy_get_config;
> +		else
> +			encoder->get_config = mtl_ddi_non_tc_phy_get_config;
>  	} else if (display->platform.dg2) {
>  		encoder->enable_clock = intel_mpllb_enable;
>  		encoder->disable_clock = intel_mpllb_disable;
> --
> 2.34.1

RE: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 18 November 2025 6.33
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: RE: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
> 
> > Subject: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for
> > C10 and C20 PHY PLLs
> >
> > For DDI initialization get configuration for C10 and C20 chips.
> >
> > v2: Getting configuration either for a C10 or on the PTL port B
> >     eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
> >     case as "non_tc_phy" instead of "c10phy".
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_ddi.c | 81
> > ++++++++++++++++++++++--
> >  1 file changed, 75 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index be25a6fdd491..689bd3224919 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -4273,6 +4273,77 @@ static void mtl_ddi_get_config(struct
> > intel_encoder *encoder,
> >  	intel_ddi_get_config(encoder, crtc_state);  }
> >
> > +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) {
> > +	return pll->info->id == DPLL_ID_ICL_TBTPLL; }
> > +
> > +static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
> > +				   struct intel_crtc_state *crtc_state,
> > +				   enum icl_port_dpll_id port_dpll_id,
> > +				   enum intel_dpll_id pll_id)
> > +{
> > +	struct intel_display *display = to_intel_display(encoder);
> > +	struct icl_port_dpll *port_dpll;
> > +	struct intel_dpll *pll;
> > +	bool pll_active;
> > +
> > +	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
> > +	pll = intel_get_dpll_by_id(display, pll_id);
> > +
> > +	if (drm_WARN_ON(display->drm, !pll))
> > +		return;
> > +
> > +	port_dpll->pll = pll;
> > +	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
> > +	drm_WARN_ON(display->drm, !pll_active);
> > +
> > +	icl_set_active_port_dpll(crtc_state, port_dpll_id);
> > +
> > +	if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
> > +		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> > +	else
> > +		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> > >intel_dpll,
> > +							     &crtc_state-
> > >dpll_hw_state);
> > +
> > +	intel_ddi_get_config(encoder, crtc_state); }
> > +
> > +/*
> > + * Get the configuration for either a port using a C10 PHY PLL, or in
> > +the case of
> > + * the PTL port B eDP on TypeC PHY case the configuration of a port
> > +using a C20
> > + * PHY PLL.
> > + */
> > +static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
> > +					     struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(encoder);
> > +
> > +	/* TODO: Remove when the PLL manager is in place. */
> 
> Is the comment needed anymore

At this point of patch series, we don't have pll manager yet in place so we can keep this comment for a while. The last patch that enables pll manager and framework will remove this comment.

> 
> > +	mtl_ddi_get_config(encoder, crtc_state);
> > +	return;
> 
> Why the early return code after this point then serves no purpose.

It serves a purpose that in this way the patch series is bisectable if we need to do that one day. This will be removed by that last patch of the series.

> 
> > +
> > +	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
> > +			       mtl_port_to_pll_id(display, encoder->port)); }
> 
> Have the pll id in its own variable.

I think this change would come down to code readability. In my taste the function call to mtl_port_pll_id() is not too confusing and hence would be ok to use as is.

> 
> > +
> > +static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
> > +				      struct intel_crtc_state *crtc_state) {
> > +	struct intel_display *display = to_intel_display(encoder);
> > +
> > +	/* TODO: Remove when the PLL manager is in place. */
> 
> No need for this comment

This is removed by the last patch.

> 
> > +	mtl_ddi_get_config(encoder, crtc_state);
> > +	return;
> 
> Same question  why the early return ?

This is again for bisectablity of the patch series.

> 
> > +
> > +	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
> > +		mtl_ddi_cx0_get_config(encoder, crtc_state,
> > ICL_PORT_DPLL_DEFAULT,
> > +				       DPLL_ID_ICL_TBTPLL);
> > +	else
> > +		mtl_ddi_cx0_get_config(encoder, crtc_state,
> > ICL_PORT_DPLL_MG_PHY,
> > +				       mtl_port_to_pll_id(display, encoder-
> > >port)); }
> 
> You can have the pll id as its one variable In fact you can call mtl_ddi_cx0_get_config just once if you have both port and pll id
> variables assigned After checking if intel_tc_port_in_tbt_alt_mode

This could be written that way we set these pll and port id's as variables after checking if intel_tc_port_in_tbt_alt_mode().  However, to me this change wouldn't improve code readability but simply would be written differently.

Thanks,
Mika

> 
> Regards,
> Suraj Kandpal
> 
> > +
> >  static void dg2_ddi_get_config(struct intel_encoder *encoder,
> >  				struct intel_crtc_state *crtc_state)  { @@ -
> > 4310,11 +4381,6 @@ static void icl_ddi_combo_get_config(struct
> > intel_encoder *encoder,
> >  	intel_ddi_get_config(encoder, crtc_state);  }
> >
> > -static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) -{
> > -	return pll->info->id == DPLL_ID_ICL_TBTPLL;
> > -}
> > -
> >  static enum icl_port_dpll_id
> >  icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
> >  			 const struct intel_crtc_state *crtc_state) @@ -5260,7
> > +5326,10 @@ void intel_ddi_init(struct intel_display *display,
> >  		encoder->enable_clock = intel_mtl_pll_enable_clock;
> >  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> >  		encoder->port_pll_type = intel_mtl_port_pll_type;
> > -		encoder->get_config = mtl_ddi_get_config;
> > +		if (intel_encoder_is_tc(encoder))
> > +			encoder->get_config = mtl_ddi_tc_phy_get_config;
> > +		else
> > +			encoder->get_config = mtl_ddi_non_tc_phy_get_config;
> >  	} else if (display->platform.dg2) {
> >  		encoder->enable_clock = intel_mpllb_enable;
> >  		encoder->disable_clock = intel_mpllb_disable;
> > --
> > 2.34.1

RE: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs

[Kandpal, Suraj]

> > Subject: RE: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration
> > for C10 and C20 PHY PLLs
> >
> > > Subject: [PATCH v2 30/32] drm/i915/cx0: Get encoder configuration
> > > for
> > > C10 and C20 PHY PLLs
> > >
> > > For DDI initialization get configuration for C10 and C20 chips.
> > >
> > > v2: Getting configuration either for a C10 or on the PTL port B
> > >     eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
> > >     case as "non_tc_phy" instead of "c10phy".
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_ddi.c | 81
> > > ++++++++++++++++++++++--
> > >  1 file changed, 75 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index be25a6fdd491..689bd3224919 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4273,6 +4273,77 @@ static void mtl_ddi_get_config(struct
> > > intel_encoder *encoder,
> > >  	intel_ddi_get_config(encoder, crtc_state);  }
> > >
> > > +static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) {
> > > +	return pll->info->id == DPLL_ID_ICL_TBTPLL; }
> > > +
> > > +static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
> > > +				   struct intel_crtc_state *crtc_state,
> > > +				   enum icl_port_dpll_id port_dpll_id,
> > > +				   enum intel_dpll_id pll_id)
> > > +{
> > > +	struct intel_display *display = to_intel_display(encoder);
> > > +	struct icl_port_dpll *port_dpll;
> > > +	struct intel_dpll *pll;
> > > +	bool pll_active;
> > > +
> > > +	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
> > > +	pll = intel_get_dpll_by_id(display, pll_id);
> > > +
> > > +	if (drm_WARN_ON(display->drm, !pll))
> > > +		return;
> > > +
> > > +	port_dpll->pll = pll;
> > > +	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
> > > +	drm_WARN_ON(display->drm, !pll_active);
> > > +
> > > +	icl_set_active_port_dpll(crtc_state, port_dpll_id);
> > > +
> > > +	if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
> > > +		crtc_state->port_clock =
> intel_mtl_tbt_calc_port_clock(encoder);
> > > +	else
> > > +		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state-
> > > >intel_dpll,
> > > +							     &crtc_state-
> > > >dpll_hw_state);
> > > +
> > > +	intel_ddi_get_config(encoder, crtc_state); }
> > > +
> > > +/*
> > > + * Get the configuration for either a port using a C10 PHY PLL, or
> > > +in the case of
> > > + * the PTL port B eDP on TypeC PHY case the configuration of a port
> > > +using a C20
> > > + * PHY PLL.
> > > + */
> > > +static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
> > > +					     struct intel_crtc_state *crtc_state) {
> > > +	struct intel_display *display = to_intel_display(encoder);
> > > +
> > > +	/* TODO: Remove when the PLL manager is in place. */
> >
> > Is the comment needed anymore
> 
> At this point of patch series, we don't have pll manager yet in place so we can
> keep this comment for a while. The last patch that enables pll manager and
> framework will remove this comment.
> 
> >
> > > +	mtl_ddi_get_config(encoder, crtc_state);
> > > +	return;
> >
> > Why the early return code after this point then serves no purpose.
> 
> It serves a purpose that in this way the patch series is bisectable if we need to
> do that one day. This will be removed by that last patch of the series.
> 
> >
> > > +
> > > +	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
> > > +			       mtl_port_to_pll_id(display, encoder->port)); }
> >
> > Have the pll id in its own variable.
> 
> I think this change would come down to code readability. In my taste the
> function call to mtl_port_pll_id() is not too confusing and hence would be ok to
> use as is.
> 
> >
> > > +
> > > +static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
> > > +				      struct intel_crtc_state *crtc_state) {
> > > +	struct intel_display *display = to_intel_display(encoder);
> > > +
> > > +	/* TODO: Remove when the PLL manager is in place. */
> >
> > No need for this comment
> 
> This is removed by the last patch.
> 
> >
> > > +	mtl_ddi_get_config(encoder, crtc_state);
> > > +	return;
> >
> > Same question  why the early return ?
> 
> This is again for bisectablity of the patch series.
> 
> >
> > > +
> > > +	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
> > > +		mtl_ddi_cx0_get_config(encoder, crtc_state,
> > > ICL_PORT_DPLL_DEFAULT,
> > > +				       DPLL_ID_ICL_TBTPLL);
> > > +	else
> > > +		mtl_ddi_cx0_get_config(encoder, crtc_state,
> > > ICL_PORT_DPLL_MG_PHY,
> > > +				       mtl_port_to_pll_id(display, encoder-
> > > >port)); }
> >
> > You can have the pll id as its one variable In fact you can call
> > mtl_ddi_cx0_get_config just once if you have both port and pll id
> > variables assigned After checking if intel_tc_port_in_tbt_alt_mode
> 
> This could be written that way we set these pll and port id's as variables after
> checking if intel_tc_port_in_tbt_alt_mode().  However, to me this change
> wouldn't improve code readability but simply would be written differently.
> 
> Thanks,
> Mika
> 

Fair enough

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> >
> > Regards,
> > Suraj Kandpal
> >
> > > +
> > >  static void dg2_ddi_get_config(struct intel_encoder *encoder,
> > >  				struct intel_crtc_state *crtc_state)  { @@ -
> > > 4310,11 +4381,6 @@ static void icl_ddi_combo_get_config(struct
> > > intel_encoder *encoder,
> > >  	intel_ddi_get_config(encoder, crtc_state);  }
> > >
> > > -static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll) -{
> > > -	return pll->info->id == DPLL_ID_ICL_TBTPLL;
> > > -}
> > > -
> > >  static enum icl_port_dpll_id
> > >  icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
> > >  			 const struct intel_crtc_state *crtc_state) @@ -5260,7
> > > +5326,10 @@ void intel_ddi_init(struct intel_display *display,
> > >  		encoder->enable_clock = intel_mtl_pll_enable_clock;
> > >  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> > >  		encoder->port_pll_type = intel_mtl_port_pll_type;
> > > -		encoder->get_config = mtl_ddi_get_config;
> > > +		if (intel_encoder_is_tc(encoder))
> > > +			encoder->get_config = mtl_ddi_tc_phy_get_config;
> > > +		else
> > > +			encoder->get_config =
> mtl_ddi_non_tc_phy_get_config;
> > >  	} else if (display->platform.dg2) {
> > >  		encoder->enable_clock = intel_mpllb_enable;
> > >  		encoder->disable_clock = intel_mpllb_disable;
> > > --
> > > 2.34.1

[PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs
similarly to the TBT PLL on earlier platforms, since this PLL is always
on from the display POV - so no PLL enable/disable programming is
required as opposed to the non-TBT PLLs - and the clocks for different
link rates are enabled/disabled at a different level, via the
intel_encoder::enable_clock()/disable_clock() interface.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 18 +++++++++
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  6 +++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 37 ++++++++++++++++++-
 3 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 79be234780ba..9d96e8940838 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3283,6 +3283,24 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
+{
+	memset(hw_state, 0, sizeof(*hw_state));
+
+	hw_state->cx0pll.tbt_mode = true;
+}
+
+bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
+					struct intel_dpll *pll,
+					struct intel_dpll_hw_state *hw_state)
+{
+	memset(hw_state, 0, sizeof(*hw_state));
+
+	hw_state->cx0pll.tbt_mode = true;
+
+	return true;
+}
+
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 3745d7081ac7..9f10113e2d18 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -70,7 +70,13 @@ void intel_cx0_write(struct intel_encoder *encoder,
 int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
 			   int command, int lane, u32 *val);
 void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);
+
+void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state);
+bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
+					struct intel_dpll *pll,
+					struct intel_dpll_hw_state *hw_state);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
+
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ecb7e3761a5b..8fd3b06f393d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4421,10 +4421,42 @@ static const struct intel_dpll_funcs mtl_pll_funcs = {
 	.get_freq = mtl_pll_get_freq,
 };
 
+static void mtl_tbt_pll_enable(struct intel_display *display,
+			       struct intel_dpll *pll,
+			       const struct intel_dpll_hw_state *hw_state)
+{
+}
+
+static void mtl_tbt_pll_disable(struct intel_display *display,
+				struct intel_dpll *pll)
+{
+}
+
+static int mtl_tbt_pll_get_freq(struct intel_display *display,
+				const struct intel_dpll *pll,
+				const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	/*
+	 * The PLL outputs multiple frequencies at the same time, selection is
+	 * made at DDI clock mux level.
+	 */
+	drm_WARN_ON(display->drm, 1);
+
+	return 0;
+}
+
+static const struct intel_dpll_funcs mtl_tbt_pll_funcs = {
+	.enable = mtl_tbt_pll_enable,
+	.disable = mtl_tbt_pll_disable,
+	.get_hw_state = intel_mtl_tbt_pll_readout_hw_state,
+	.get_freq = mtl_tbt_pll_get_freq,
+};
+
 static const struct dpll_info mtl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	/* TODO: Add TBT PLL */
+	{ .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	  .is_alt_port_dpll = true, .always_on = true },
 	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
 	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
@@ -4470,7 +4502,8 @@ static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	struct icl_port_dpll *port_dpll;
 	int ret;
 
-	/* TODO: Add state calculation for TBT PLL */
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
-- 
2.34.1

RE: [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

[Kandpal, Suraj]

> Subject: [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs similarly
> to the TBT PLL on earlier platforms, since this PLL is always on from the display
> POV - so no PLL enable/disable programming is required as opposed to the
> non-TBT PLLs - and the clocks for different link rates are enabled/disabled at a
> different level, via the
> intel_encoder::enable_clock()/disable_clock() interface.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 18 +++++++++
> drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  6 +++
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 37 ++++++++++++++++++-
>  3 files changed, 59 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 79be234780ba..9d96e8940838 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3283,6 +3283,24 @@ static void intel_cx0pll_enable(struct
> intel_encoder *encoder,
>  	intel_cx0_phy_transaction_end(encoder, wakeref);  }
> 
> +void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
> +{
> +	memset(hw_state, 0, sizeof(*hw_state));
> +
> +	hw_state->cx0pll.tbt_mode = true;
> +}
> +
> +bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
> +					struct intel_dpll *pll,
> +					struct intel_dpll_hw_state
> *hw_state) {
> +	memset(hw_state, 0, sizeof(*hw_state));
> +
> +	hw_state->cx0pll.tbt_mode = true;
> +
> +	return true;
> +}
> +
>  int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)  {
>  	struct intel_display *display = to_intel_display(encoder); diff --git
> a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 3745d7081ac7..9f10113e2d18 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -70,7 +70,13 @@ void intel_cx0_write(struct intel_encoder *encoder,
> int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
>  			   int command, int lane, u32 *val);  void
> intel_cx0_bus_reset(struct intel_encoder *encoder, int lane);
> +
> +void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state
> +*hw_state); bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display
> *display,
> +					struct intel_dpll *pll,
> +					struct intel_dpll_hw_state
> *hw_state);
>  int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> +
>  void intel_cx0_pll_power_save_wa(struct intel_display *display);  void
> intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
>  				 const struct intel_crtc_state *crtc_state); diff
> --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ecb7e3761a5b..8fd3b06f393d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4421,10 +4421,42 @@ static const struct intel_dpll_funcs mtl_pll_funcs
> = {
>  	.get_freq = mtl_pll_get_freq,
>  };
> 
> +static void mtl_tbt_pll_enable(struct intel_display *display,
> +			       struct intel_dpll *pll,
> +			       const struct intel_dpll_hw_state *hw_state) { }
> +
> +static void mtl_tbt_pll_disable(struct intel_display *display,
> +				struct intel_dpll *pll)
> +{
> +}
> +
> +static int mtl_tbt_pll_get_freq(struct intel_display *display,
> +				const struct intel_dpll *pll,
> +				const struct intel_dpll_hw_state
> *dpll_hw_state) {
> +	/*
> +	 * The PLL outputs multiple frequencies at the same time, selection is
> +	 * made at DDI clock mux level.
> +	 */
> +	drm_WARN_ON(display->drm, 1);
> +
> +	return 0;
> +}
> +
> +static const struct intel_dpll_funcs mtl_tbt_pll_funcs = {
> +	.enable = mtl_tbt_pll_enable,
> +	.disable = mtl_tbt_pll_disable,
> +	.get_hw_state = intel_mtl_tbt_pll_readout_hw_state,
> +	.get_freq = mtl_tbt_pll_get_freq,
> +};
> +
>  static const struct dpll_info mtl_plls[] = {
>  	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
>  	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> -	/* TODO: Add TBT PLL */
> +	{ .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id =
> DPLL_ID_ICL_TBTPLL,
> +	  .is_alt_port_dpll = true, .always_on = true },
>  	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
>  	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, },
>  	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL3, }, @@ -4470,7 +4502,8 @@ static int
> mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
>  	struct icl_port_dpll *port_dpll;
>  	int ret;
> 
> -	/* TODO: Add state calculation for TBT PLL */
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];

Should this be DPLL_DEFAULT or MG_PHY

Regards,
Suraj Kandpal

> +	intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state);
> 
>  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
>  	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll-
> >hw_state);
> --
> 2.34.1

Re: [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

[Imre Deak]

On Tue, Nov 18, 2025 at 06:38:13AM +0200, Suraj Kandpal wrote:
> [...]
> > +static const struct intel_dpll_funcs mtl_tbt_pll_funcs = {
> > +	.enable = mtl_tbt_pll_enable,
> > +	.disable = mtl_tbt_pll_disable,
> > +	.get_hw_state = intel_mtl_tbt_pll_readout_hw_state,
> > +	.get_freq = mtl_tbt_pll_get_freq,
> > +};
> > +
> >  static const struct dpll_info mtl_plls[] = {
> >  	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> >  	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> > -	/* TODO: Add TBT PLL */
> > +	{ .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
> > +	  .is_alt_port_dpll = true, .always_on = true },
> >  	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
> >  	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
> >  	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
> > @@ -4470,7 +4502,8 @@ static int
> > mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> >  	struct icl_port_dpll *port_dpll;
> >  	int ret;
> > 
> > -	/* TODO: Add state calculation for TBT PLL */
> > +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> 
> Should this be DPLL_DEFAULT or MG_PHY

The Thunderbolt PLL state should be stored to the ICL_PORT_DPLL_DEFAULT
port PLL index, as above.

> 
> Regards,
> Suraj Kandpal
> 
> > +	intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state);
> > 
> >  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> >  	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> > --
> > 2.34.1
> 

RE: [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks

[Kandpal, Suraj]

> Subject: Re: [PATCH v2 31/32] drm/i915/cx0: Add MTL+ Thunderbolt PLL
> hooks
> 
> On Tue, Nov 18, 2025 at 06:38:13AM +0200, Suraj Kandpal wrote:
> > [...]
> > > +static const struct intel_dpll_funcs mtl_tbt_pll_funcs = {
> > > +	.enable = mtl_tbt_pll_enable,
> > > +	.disable = mtl_tbt_pll_disable,
> > > +	.get_hw_state = intel_mtl_tbt_pll_readout_hw_state,
> > > +	.get_freq = mtl_tbt_pll_get_freq,
> > > +};
> > > +
> > >  static const struct dpll_info mtl_plls[] = {
> > >  	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
> > >  	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> > > -	/* TODO: Add TBT PLL */
> > > +	{ .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id =
> DPLL_ID_ICL_TBTPLL,
> > > +	  .is_alt_port_dpll = true, .always_on = true },
> > >  	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
> > >  	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, },
> > >  	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id =
> > > DPLL_ID_ICL_MGPLL3, }, @@ -4470,7 +4502,8 @@ static int
> > > mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> > >  	struct icl_port_dpll *port_dpll;
> > >  	int ret;
> > >
> > > -	/* TODO: Add state calculation for TBT PLL */
> > > +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> >
> > Should this be DPLL_DEFAULT or MG_PHY
> 
> The Thunderbolt PLL state should be stored to the ICL_PORT_DPLL_DEFAULT
> port PLL index, as above.
> 

Got it.
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> >
> > Regards,
> > Suraj Kandpal
> >
> > > +	intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state);
> > >
> > >  	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> > >  	ret = intel_cx0pll_calc_state(crtc_state, encoder,
> > > &port_dpll->hw_state);
> > > --
> > > 2.34.1
> >

[PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+

[Mika Kahola]

Now that MTL+ platforms are supported by dpll framework
remove a separate check for hw comparison and rely solely
on dpll framework hw comparison.

Finally, all required hooks are now in place so initialize
PLL manager for MTL+ platforms and remove the redirections
to the legacy code paths from the following interfaces:

* intel_encoder::clock_enable/disable()
* intel_encoder::get_config()
* intel_dpll_funcs::get_hw_state()
* intel_ddi_update_active_dpll()
* pipe_config_pll_mismatch()

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 -------
 drivers/gpu/drm/i915/display/intel_ddi.c      | 29 ++++---------------
 drivers/gpu/drm/i915/display/intel_display.c  | 29 -------------------
 drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +--------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  5 ++--
 5 files changed, 9 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9d96e8940838..96ab7f3b5539 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3432,9 +3432,6 @@ void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 /*
@@ -3598,9 +3595,6 @@ void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_disable_clock(encoder);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_mtl_pll_disable(encoder);
 }
 
 enum icl_port_dpll_id
@@ -3629,10 +3623,6 @@ bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 {
 	memset(pll_state, 0, sizeof(*pll_state));
 
-	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
-	if (pll_state->tbt_mode)
-		return true;
-
 	if (!intel_cx0_pll_is_enabled(encoder))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 689bd3224919..4e379b0b066d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3669,8 +3669,10 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_crtc *pipe_crtc;
 
-	/* FIXME: Add MTL pll_mgr */
-	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
+	if (!intel_encoder_is_tc(encoder))
+		return;
+
+	if (!HAS_LT_PHY(display))
 		return;
 
 	if (!HAS_LT_PHY(display))
@@ -4260,19 +4262,6 @@ static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
-static void mtl_ddi_get_config(struct intel_encoder *encoder,
-			       struct intel_crtc_state *crtc_state)
-{
-	intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
-		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
-	else
-		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	intel_ddi_get_config(encoder, crtc_state);
-}
-
 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
 {
 	return pll->info->id == DPLL_ID_ICL_TBTPLL;
@@ -4319,10 +4308,6 @@ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	/* TODO: Remove when the PLL manager is in place. */
-	mtl_ddi_get_config(encoder, crtc_state);
-	return;
-
 	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
 			       mtl_port_to_pll_id(display, encoder->port));
 }
@@ -4332,10 +4317,6 @@ static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	/* TODO: Remove when the PLL manager is in place. */
-	mtl_ddi_get_config(encoder, crtc_state);
-	return;
-
 	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
 		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
 				       DPLL_ID_ICL_TBTPLL);
@@ -5325,7 +5306,7 @@ void intel_ddi_init(struct intel_display *display,
 	} else if (DISPLAY_VER(display) >= 14) {
 		encoder->enable_clock = intel_mtl_pll_enable_clock;
 		encoder->disable_clock = intel_mtl_pll_disable_clock;
-		encoder->port_pll_type = intel_mtl_port_pll_type;
+		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
 		if (intel_encoder_is_tc(encoder))
 			encoder->get_config = mtl_ddi_tc_phy_get_config;
 		else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e7bb8ec0d6bb..6c8a7f63111e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4977,23 +4977,6 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
 	intel_dpll_dump_hw_state(display, p, b);
 }
 
-static void
-pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
-			    const struct intel_crtc *crtc,
-			    const char *name,
-			    const struct intel_cx0pll_state *a,
-			    const struct intel_cx0pll_state *b)
-{
-	char *chipname = a->use_c10 ? "C10" : "C20";
-
-	pipe_config_mismatch(p, fastset, crtc, name, chipname);
-
-	drm_printf(p, "expected:\n");
-	intel_cx0pll_dump_hw_state(p, a);
-	drm_printf(p, "found:\n");
-	intel_cx0pll_dump_hw_state(p, b);
-}
-
 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
@@ -5145,16 +5128,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
-#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
-	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
-					   &pipe_config->name)) { \
-		pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
-					    &current_config->name, \
-					    &pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
 #define PIPE_CONF_CHECK_PLL_LT(name) do { \
 	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
 					       &pipe_config->name)) { \
@@ -5394,8 +5367,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	/* FIXME convert MTL+ platforms over to dpll_mgr */
 	if (HAS_LT_PHY(display))
 		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
-	else if (DISPLAY_VER(display) >= 14)
-		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
 
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
 	PIPE_CONF_CHECK_X(dsi_pll.div);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2da65bb20f1c..a4f372c9e6fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1212,27 +1212,6 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
-	int ret;
-
-	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
-	if (ret)
-		return ret;
-
-	/* TODO: Do the readback via intel_dpll_compute() */
-	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
-
-	return 0;
-}
-
 static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc)
 {
@@ -1719,7 +1698,7 @@ static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
 };
 
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
-	.crtc_compute_clock = mtl_crtc_compute_clock,
+	.crtc_compute_clock = hsw_crtc_compute_clock,
 	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8fd3b06f393d..6c94dd2e1a15 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a,
 	return intel_cx0pll_compare_hw_state(a, b);
 }
 
-__maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
@@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display *display)
 
 	mutex_init(&display->dpll.lock);
 
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
+	if (display->platform.dg2)
 		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
 		dpll_mgr = NULL;
+	else if (DISPLAY_VER(display) >= 14)
+		dpll_mgr = &mtl_pll_mgr;
 	else if (display->platform.alderlake_p)
 		dpll_mgr = &adlp_pll_mgr;
 	else if (display->platform.alderlake_s)
-- 
2.34.1

RE: [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+

[Kandpal, Suraj]

> Subject: [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+
> 
> Now that MTL+ platforms are supported by dpll framework remove a separate
> check for hw comparison and rely solely on dpll framework hw comparison.
> 
> Finally, all required hooks are now in place so initialize PLL manager for MTL+
> platforms and remove the redirections to the legacy code paths from the
> following interfaces:
> 
> * intel_encoder::clock_enable/disable()
> * intel_encoder::get_config()
> * intel_dpll_funcs::get_hw_state()
> * intel_ddi_update_active_dpll()
> * pipe_config_pll_mismatch()
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 -------
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 29 ++++---------------
>  drivers/gpu/drm/i915/display/intel_display.c  | 29 -------------------
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +--------------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  5 ++--
>  5 files changed, 9 insertions(+), 87 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9d96e8940838..96ab7f3b5539 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3432,9 +3432,6 @@ void intel_mtl_pll_enable_clock(struct intel_encoder
> *encoder,
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_mtl_pll_enable(encoder, NULL, &crtc_state-
> >dpll_hw_state);
>  }
> 
>  /*
> @@ -3598,9 +3595,6 @@ void intel_mtl_pll_disable_clock(struct intel_encoder
> *encoder)
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_disable_clock(encoder);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_mtl_pll_disable(encoder);
>  }
> 
>  enum icl_port_dpll_id
> @@ -3629,10 +3623,6 @@ bool intel_cx0pll_readout_hw_state(struct
> intel_encoder *encoder,  {
>  	memset(pll_state, 0, sizeof(*pll_state));
> 
> -	pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> -	if (pll_state->tbt_mode)
> -		return true;
> -
>  	if (!intel_cx0_pll_is_enabled(encoder))
>  		return false;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 689bd3224919..4e379b0b066d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3669,8 +3669,10 @@ void intel_ddi_update_active_dpll(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_crtc *pipe_crtc;
> 
> -	/* FIXME: Add MTL pll_mgr */
> -	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
> +	if (!intel_encoder_is_tc(encoder))
> +		return;
> +
> +	if (!HAS_LT_PHY(display))
>  		return;
> 
>  	if (!HAS_LT_PHY(display))
> @@ -4260,19 +4262,6 @@ static void xe3plpd_ddi_get_config(struct
> intel_encoder *encoder,
>  	intel_ddi_get_config(encoder, crtc_state);  }
> 
> -static void mtl_ddi_get_config(struct intel_encoder *encoder,
> -			       struct intel_crtc_state *crtc_state)
> -{
> -	intel_cx0pll_readout_hw_state(encoder, &crtc_state-
> >dpll_hw_state.cx0pll);
> -
> -	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
> -		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> -	else
> -		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> &crtc_state->dpll_hw_state.cx0pll);
> -
> -	intel_ddi_get_config(encoder, crtc_state);
> -}
> -
>  static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)  {
>  	return pll->info->id == DPLL_ID_ICL_TBTPLL; @@ -4319,10 +4308,6
> @@ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
> {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> -	/* TODO: Remove when the PLL manager is in place. */
> -	mtl_ddi_get_config(encoder, crtc_state);
> -	return;
> -
>  	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
>  			       mtl_port_to_pll_id(display, encoder->port));  } @@
> -4332,10 +4317,6 @@ static void mtl_ddi_tc_phy_get_config(struct
> intel_encoder *encoder,  {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> -	/* TODO: Remove when the PLL manager is in place. */
> -	mtl_ddi_get_config(encoder, crtc_state);
> -	return;
> -
>  	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
>  		mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_DEFAULT,
>  				       DPLL_ID_ICL_TBTPLL);
> @@ -5325,7 +5306,7 @@ void intel_ddi_init(struct intel_display *display,
>  	} else if (DISPLAY_VER(display) >= 14) {
>  		encoder->enable_clock = intel_mtl_pll_enable_clock;
>  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> -		encoder->port_pll_type = intel_mtl_port_pll_type;
> +		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
>  		if (intel_encoder_is_tc(encoder))
>  			encoder->get_config = mtl_ddi_tc_phy_get_config;
>  		else
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e7bb8ec0d6bb..6c8a7f63111e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4977,23 +4977,6 @@ pipe_config_pll_mismatch(struct drm_printer *p,
> bool fastset,
>  	intel_dpll_dump_hw_state(display, p, b);  }
> 
> -static void
> -pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> -			    const struct intel_crtc *crtc,
> -			    const char *name,
> -			    const struct intel_cx0pll_state *a,
> -			    const struct intel_cx0pll_state *b)
> -{
> -	char *chipname = a->use_c10 ? "C10" : "C20";
> -
> -	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> -
> -	drm_printf(p, "expected:\n");
> -	intel_cx0pll_dump_hw_state(p, a);
> -	drm_printf(p, "found:\n");
> -	intel_cx0pll_dump_hw_state(p, b);
> -}
> -
>  static bool allow_vblank_delay_fastset(const struct intel_crtc_state
> *old_crtc_state)  {
>  	struct intel_display *display = to_intel_display(old_crtc_state); @@ -
> 5145,16 +5128,6 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	} \
>  } while (0)
> 
> -#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
> -	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
> -					   &pipe_config->name)) { \
> -		pipe_config_cx0pll_mismatch(&p, fastset, crtc,
> __stringify(name), \
> -					    &current_config->name, \
> -					    &pipe_config->name); \
> -		ret = false; \
> -	} \
> -} while (0)
> -
>  #define PIPE_CONF_CHECK_PLL_LT(name) do { \
>  	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
>  					       &pipe_config->name)) { \
> @@ -5394,8 +5367,6 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	/* FIXME convert MTL+ platforms over to dpll_mgr */
>  	if (HAS_LT_PHY(display))
>  		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
> -	else if (DISPLAY_VER(display) >= 14)
> -		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
> 
>  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>  	PIPE_CONF_CHECK_X(dsi_pll.div);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 2da65bb20f1c..a4f372c9e6fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1212,27 +1212,6 @@ static int dg2_crtc_compute_clock(struct
> intel_atomic_state *state,
>  	return 0;
>  }
> 
> -static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> -				  struct intel_crtc *crtc)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_encoder *encoder =
> -		intel_get_crtc_new_encoder(state, crtc_state);
> -	int ret;
> -
> -	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state-
> >dpll_hw_state);
> -	if (ret)
> -		return ret;
> -
> -	/* TODO: Do the readback via intel_dpll_compute() */
> -	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> &crtc_state->dpll_hw_state.cx0pll);
> -
> -	crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
> -
> -	return 0;
> -}
> -
>  static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
>  				      struct intel_crtc *crtc)
>  {
> @@ -1719,7 +1698,7 @@ static const struct intel_dpll_global_funcs
> xe3plpd_dpll_funcs = {  };
> 
>  static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
> -	.crtc_compute_clock = mtl_crtc_compute_clock,
> +	.crtc_compute_clock = hsw_crtc_compute_clock,
>  	.crtc_get_dpll = hsw_crtc_get_dpll,
>  };
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8fd3b06f393d..6c94dd2e1a15 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct
> intel_dpll_hw_state *_a,
>  	return intel_cx0pll_compare_hw_state(a, b);  }
> 
> -__maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
>  	.compute_dplls = mtl_compute_dplls,
> @@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display *display)
> 
>  	mutex_init(&display->dpll.lock);
> 
> -	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> +	if (display->platform.dg2)

This needs to become (HAS_LT_PHY || dg2)
	Dpll_mgr = NULL

Regards,
Suraj Kandpal

>  		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
>  		dpll_mgr = NULL;
> +	else if (DISPLAY_VER(display) >= 14)
> +		dpll_mgr = &mtl_pll_mgr;
>  	else if (display->platform.alderlake_p)
>  		dpll_mgr = &adlp_pll_mgr;
>  	else if (display->platform.alderlake_s)
> --
> 2.34.1

RE: [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Tuesday, 18 November 2025 6.14
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: RE: [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+
> 
> > Subject: [PATCH v2 32/32] drm/i915/cx0: Enable dpll framework for MTL+
> >
> > Now that MTL+ platforms are supported by dpll framework remove a
> > separate check for hw comparison and rely solely on dpll framework hw comparison.
> >
> > Finally, all required hooks are now in place so initialize PLL manager
> > for MTL+ platforms and remove the redirections to the legacy code
> > paths from the following interfaces:
> >
> > * intel_encoder::clock_enable/disable()
> > * intel_encoder::get_config()
> > * intel_dpll_funcs::get_hw_state()
> > * intel_ddi_update_active_dpll()
> > * pipe_config_pll_mismatch()
> >
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 -------
> >  drivers/gpu/drm/i915/display/intel_ddi.c      | 29 ++++---------------
> >  drivers/gpu/drm/i915/display/intel_display.c  | 29 -------------------
> >  drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +--------------
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  5 ++--
> >  5 files changed, 9 insertions(+), 87 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 9d96e8940838..96ab7f3b5539 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -3432,9 +3432,6 @@ void intel_mtl_pll_enable_clock(struct
> > intel_encoder *encoder,
> >
> >  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> >  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
> > -	else
> > -		/* TODO: remove when PLL mgr is in place. */
> > -		intel_mtl_pll_enable(encoder, NULL, &crtc_state-
> > >dpll_hw_state);
> >  }
> >
> >  /*
> > @@ -3598,9 +3595,6 @@ void intel_mtl_pll_disable_clock(struct
> > intel_encoder
> > *encoder)
> >
> >  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> >  		intel_mtl_tbt_pll_disable_clock(encoder);
> > -	else
> > -		/* TODO: remove when PLL mgr is in place. */
> > -		intel_mtl_pll_disable(encoder);
> >  }
> >
> >  enum icl_port_dpll_id
> > @@ -3629,10 +3623,6 @@ bool intel_cx0pll_readout_hw_state(struct
> > intel_encoder *encoder,  {
> >  	memset(pll_state, 0, sizeof(*pll_state));
> >
> > -	pll_state->tbt_mode =
> > intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> > -	if (pll_state->tbt_mode)
> > -		return true;
> > -
> >  	if (!intel_cx0_pll_is_enabled(encoder))
> >  		return false;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index 689bd3224919..4e379b0b066d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -3669,8 +3669,10 @@ void intel_ddi_update_active_dpll(struct
> > intel_atomic_state *state,
> >  		intel_atomic_get_new_crtc_state(state, crtc);
> >  	struct intel_crtc *pipe_crtc;
> >
> > -	/* FIXME: Add MTL pll_mgr */
> > -	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
> > +	if (!intel_encoder_is_tc(encoder))
> > +		return;
> > +
> > +	if (!HAS_LT_PHY(display))
> >  		return;
> >
> >  	if (!HAS_LT_PHY(display))
> > @@ -4260,19 +4262,6 @@ static void xe3plpd_ddi_get_config(struct
> > intel_encoder *encoder,
> >  	intel_ddi_get_config(encoder, crtc_state);  }
> >
> > -static void mtl_ddi_get_config(struct intel_encoder *encoder,
> > -			       struct intel_crtc_state *crtc_state)
> > -{
> > -	intel_cx0pll_readout_hw_state(encoder, &crtc_state-
> > >dpll_hw_state.cx0pll);
> > -
> > -	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
> > -		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
> > -	else
> > -		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> > &crtc_state->dpll_hw_state.cx0pll);
> > -
> > -	intel_ddi_get_config(encoder, crtc_state);
> > -}
> > -
> >  static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)  {
> >  	return pll->info->id == DPLL_ID_ICL_TBTPLL; @@ -4319,10 +4308,6 @@
> > static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder
> > *encoder, {
> >  	struct intel_display *display = to_intel_display(encoder);
> >
> > -	/* TODO: Remove when the PLL manager is in place. */
> > -	mtl_ddi_get_config(encoder, crtc_state);
> > -	return;
> > -
> >  	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
> >  			       mtl_port_to_pll_id(display, encoder->port));  } @@
> > -4332,10 +4317,6 @@ static void mtl_ddi_tc_phy_get_config(struct
> > intel_encoder *encoder,  {
> >  	struct intel_display *display = to_intel_display(encoder);
> >
> > -	/* TODO: Remove when the PLL manager is in place. */
> > -	mtl_ddi_get_config(encoder, crtc_state);
> > -	return;
> > -
> >  	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
> >  		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
> >  				       DPLL_ID_ICL_TBTPLL);
> > @@ -5325,7 +5306,7 @@ void intel_ddi_init(struct intel_display *display,
> >  	} else if (DISPLAY_VER(display) >= 14) {
> >  		encoder->enable_clock = intel_mtl_pll_enable_clock;
> >  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> > -		encoder->port_pll_type = intel_mtl_port_pll_type;
> > +		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
> >  		if (intel_encoder_is_tc(encoder))
> >  			encoder->get_config = mtl_ddi_tc_phy_get_config;
> >  		else
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index e7bb8ec0d6bb..6c8a7f63111e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4977,23 +4977,6 @@ pipe_config_pll_mismatch(struct drm_printer *p,
> > bool fastset,
> >  	intel_dpll_dump_hw_state(display, p, b);  }
> >
> > -static void
> > -pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> > -			    const struct intel_crtc *crtc,
> > -			    const char *name,
> > -			    const struct intel_cx0pll_state *a,
> > -			    const struct intel_cx0pll_state *b)
> > -{
> > -	char *chipname = a->use_c10 ? "C10" : "C20";
> > -
> > -	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> > -
> > -	drm_printf(p, "expected:\n");
> > -	intel_cx0pll_dump_hw_state(p, a);
> > -	drm_printf(p, "found:\n");
> > -	intel_cx0pll_dump_hw_state(p, b);
> > -}
> > -
> >  static bool allow_vblank_delay_fastset(const struct intel_crtc_state
> > *old_crtc_state)  {
> >  	struct intel_display *display = to_intel_display(old_crtc_state); @@
> > -
> > 5145,16 +5128,6 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> >  	} \
> >  } while (0)
> >
> > -#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
> > -	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
> > -					   &pipe_config->name)) { \
> > -		pipe_config_cx0pll_mismatch(&p, fastset, crtc,
> > __stringify(name), \
> > -					    &current_config->name, \
> > -					    &pipe_config->name); \
> > -		ret = false; \
> > -	} \
> > -} while (0)
> > -
> >  #define PIPE_CONF_CHECK_PLL_LT(name) do { \
> >  	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
> >  					       &pipe_config->name)) { \
> > @@ -5394,8 +5367,6 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> >  	/* FIXME convert MTL+ platforms over to dpll_mgr */
> >  	if (HAS_LT_PHY(display))
> >  		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
> > -	else if (DISPLAY_VER(display) >= 14)
> > -		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
> >
> >  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
> >  	PIPE_CONF_CHECK_X(dsi_pll.div);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 2da65bb20f1c..a4f372c9e6fc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1212,27 +1212,6 @@ static int dg2_crtc_compute_clock(struct
> > intel_atomic_state *state,
> >  	return 0;
> >  }
> >
> > -static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> > -				  struct intel_crtc *crtc)
> > -{
> > -	struct intel_crtc_state *crtc_state =
> > -		intel_atomic_get_new_crtc_state(state, crtc);
> > -	struct intel_encoder *encoder =
> > -		intel_get_crtc_new_encoder(state, crtc_state);
> > -	int ret;
> > -
> > -	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state-
> > >dpll_hw_state);
> > -	if (ret)
> > -		return ret;
> > -
> > -	/* TODO: Do the readback via intel_dpll_compute() */
> > -	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> > &crtc_state->dpll_hw_state.cx0pll);
> > -
> > -	crtc_state->hw.adjusted_mode.crtc_clock =
> > intel_crtc_dotclock(crtc_state);
> > -
> > -	return 0;
> > -}
> > -
> >  static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
> >  				      struct intel_crtc *crtc)
> >  {
> > @@ -1719,7 +1698,7 @@ static const struct intel_dpll_global_funcs
> > xe3plpd_dpll_funcs = {  };
> >
> >  static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
> > -	.crtc_compute_clock = mtl_crtc_compute_clock,
> > +	.crtc_compute_clock = hsw_crtc_compute_clock,
> >  	.crtc_get_dpll = hsw_crtc_get_dpll,
> >  };
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > index 8fd3b06f393d..6c94dd2e1a15 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> > @@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct
> > intel_dpll_hw_state *_a,
> >  	return intel_cx0pll_compare_hw_state(a, b);  }
> >
> > -__maybe_unused
> >  static const struct intel_dpll_mgr mtl_pll_mgr = {
> >  	.dpll_info = mtl_plls,
> >  	.compute_dplls = mtl_compute_dplls,
> > @@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display
> > *display)
> >
> >  	mutex_init(&display->dpll.lock);
> >
> > -	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> > +	if (display->platform.dg2)
> 
> This needs to become (HAS_LT_PHY || dg2)
> 	Dpll_mgr = NULL

Right, I missed that while rebasing the series on top of LT PHY series.

Thanks!

-Mika-

> 
> Regards,
> Suraj Kandpal
> 
> >  		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
> >  		dpll_mgr = NULL;
> > +	else if (DISPLAY_VER(display) >= 14)
> > +		dpll_mgr = &mtl_pll_mgr;
> >  	else if (display->platform.alderlake_p)
> >  		dpll_mgr = &adlp_pll_mgr;
> >  	else if (display->platform.alderlake_s)
> > --
> > 2.34.1

[PATCH v3 32/32] drm/i915/cx0: Enable dpll framework for MTL+

[Mika Kahola]

MTL+ platforms are supported by dpll framework remove a separate
check for hw comparison and rely solely on dpll framework
hw comparison.

Finally, all required hooks are now in place so initialize
PLL manager for MTL+ platforms and remove the redirections
to the legacy code paths from the following interfaces:

* intel_encoder::clock_enable/disable()
* intel_encoder::get_config()
* intel_dpll_funcs::get_hw_state()
* intel_ddi_update_active_dpll()
* pipe_config_pll_mismatch()

v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll()
v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll()
    Add check for NVL as the platform is not part of pll framework (Suraj)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 -------
 drivers/gpu/drm/i915/display/intel_ddi.c      | 23 +--------------
 drivers/gpu/drm/i915/display/intel_display.c  | 29 -------------------
 drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +--------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++--
 5 files changed, 6 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 9d96e8940838..96ab7f3b5539 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3432,9 +3432,6 @@ void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 /*
@@ -3598,9 +3595,6 @@ void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_disable_clock(encoder);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_mtl_pll_disable(encoder);
 }
 
 enum icl_port_dpll_id
@@ -3629,10 +3623,6 @@ bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 {
 	memset(pll_state, 0, sizeof(*pll_state));
 
-	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
-	if (pll_state->tbt_mode)
-		return true;
-
 	if (!intel_cx0_pll_is_enabled(encoder))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d024a1073e03..c2e08c453ae1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4257,19 +4257,6 @@ static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
-static void mtl_ddi_get_config(struct intel_encoder *encoder,
-			       struct intel_crtc_state *crtc_state)
-{
-	intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
-		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
-	else
-		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	intel_ddi_get_config(encoder, crtc_state);
-}
-
 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
 {
 	return pll->info->id == DPLL_ID_ICL_TBTPLL;
@@ -4316,10 +4303,6 @@ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	/* TODO: Remove when the PLL manager is in place. */
-	mtl_ddi_get_config(encoder, crtc_state);
-	return;
-
 	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
 			       mtl_port_to_pll_id(display, encoder->port));
 }
@@ -4329,10 +4312,6 @@ static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	/* TODO: Remove when the PLL manager is in place. */
-	mtl_ddi_get_config(encoder, crtc_state);
-	return;
-
 	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
 		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
 				       DPLL_ID_ICL_TBTPLL);
@@ -5322,7 +5301,7 @@ void intel_ddi_init(struct intel_display *display,
 	} else if (DISPLAY_VER(display) >= 14) {
 		encoder->enable_clock = intel_mtl_pll_enable_clock;
 		encoder->disable_clock = intel_mtl_pll_disable_clock;
-		encoder->port_pll_type = intel_mtl_port_pll_type;
+		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
 		if (intel_encoder_is_tc(encoder))
 			encoder->get_config = mtl_ddi_tc_phy_get_config;
 		else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e7bb8ec0d6bb..6c8a7f63111e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4977,23 +4977,6 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
 	intel_dpll_dump_hw_state(display, p, b);
 }
 
-static void
-pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
-			    const struct intel_crtc *crtc,
-			    const char *name,
-			    const struct intel_cx0pll_state *a,
-			    const struct intel_cx0pll_state *b)
-{
-	char *chipname = a->use_c10 ? "C10" : "C20";
-
-	pipe_config_mismatch(p, fastset, crtc, name, chipname);
-
-	drm_printf(p, "expected:\n");
-	intel_cx0pll_dump_hw_state(p, a);
-	drm_printf(p, "found:\n");
-	intel_cx0pll_dump_hw_state(p, b);
-}
-
 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
@@ -5145,16 +5128,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
-#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
-	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
-					   &pipe_config->name)) { \
-		pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
-					    &current_config->name, \
-					    &pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
 #define PIPE_CONF_CHECK_PLL_LT(name) do { \
 	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
 					       &pipe_config->name)) { \
@@ -5394,8 +5367,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	/* FIXME convert MTL+ platforms over to dpll_mgr */
 	if (HAS_LT_PHY(display))
 		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
-	else if (DISPLAY_VER(display) >= 14)
-		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
 
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
 	PIPE_CONF_CHECK_X(dsi_pll.div);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 2da65bb20f1c..a4f372c9e6fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1212,27 +1212,6 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
-	int ret;
-
-	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
-	if (ret)
-		return ret;
-
-	/* TODO: Do the readback via intel_dpll_compute() */
-	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
-
-	return 0;
-}
-
 static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
 				      struct intel_crtc *crtc)
 {
@@ -1719,7 +1698,7 @@ static const struct intel_dpll_global_funcs xe3plpd_dpll_funcs = {
 };
 
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
-	.crtc_compute_clock = mtl_crtc_compute_clock,
+	.crtc_compute_clock = hsw_crtc_compute_clock,
 	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8fd3b06f393d..6d7d5394713d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a,
 	return intel_cx0pll_compare_hw_state(a, b);
 }
 
-__maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
@@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display *display)
 
 	mutex_init(&display->dpll.lock);
 
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
-		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
+	if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
+		/* No shared DPLLs on NVL or DG2; port PLLs are part of the PHY */
 		dpll_mgr = NULL;
+	else if (DISPLAY_VER(display) >= 14)
+		dpll_mgr = &mtl_pll_mgr;
 	else if (display->platform.alderlake_p)
 		dpll_mgr = &adlp_pll_mgr;
 	else if (display->platform.alderlake_s)
-- 
2.34.1

RE: [PATCH v3 32/32] drm/i915/cx0: Enable dpll framework for MTL+

[Kandpal, Suraj]

> Subject: [PATCH v3 32/32] drm/i915/cx0: Enable dpll framework for MTL+
> 
> MTL+ platforms are supported by dpll framework remove a separate
> check for hw comparison and rely solely on dpll framework hw comparison.
> 
> Finally, all required hooks are now in place so initialize PLL manager for MTL+
> platforms and remove the redirections to the legacy code paths from the
> following interfaces:
> 
> * intel_encoder::clock_enable/disable()
> * intel_encoder::get_config()
> * intel_dpll_funcs::get_hw_state()
> * intel_ddi_update_active_dpll()
> * pipe_config_pll_mismatch()
> 
> v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll()
> v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll()
>     Add check for NVL as the platform is not part of pll framework (Suraj)
> 

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>


> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 -------
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 23 +--------------
>  drivers/gpu/drm/i915/display/intel_display.c  | 29 -------------------
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +--------------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 +++--
>  5 files changed, 6 insertions(+), 86 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 9d96e8940838..96ab7f3b5539 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3432,9 +3432,6 @@ void intel_mtl_pll_enable_clock(struct
> intel_encoder *encoder,
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_mtl_pll_enable(encoder, NULL, &crtc_state-
> >dpll_hw_state);
>  }
> 
>  /*
> @@ -3598,9 +3595,6 @@ void intel_mtl_pll_disable_clock(struct
> intel_encoder *encoder)
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_disable_clock(encoder);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_mtl_pll_disable(encoder);
>  }
> 
>  enum icl_port_dpll_id
> @@ -3629,10 +3623,6 @@ bool intel_cx0pll_readout_hw_state(struct
> intel_encoder *encoder,  {
>  	memset(pll_state, 0, sizeof(*pll_state));
> 
> -	pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> -	if (pll_state->tbt_mode)
> -		return true;
> -
>  	if (!intel_cx0_pll_is_enabled(encoder))
>  		return false;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d024a1073e03..c2e08c453ae1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4257,19 +4257,6 @@ static void xe3plpd_ddi_get_config(struct
> intel_encoder *encoder,
>  	intel_ddi_get_config(encoder, crtc_state);  }
> 
> -static void mtl_ddi_get_config(struct intel_encoder *encoder,
> -			       struct intel_crtc_state *crtc_state)
> -{
> -	intel_cx0pll_readout_hw_state(encoder, &crtc_state-
> >dpll_hw_state.cx0pll);
> -
> -	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
> -		crtc_state->port_clock =
> intel_mtl_tbt_calc_port_clock(encoder);
> -	else
> -		crtc_state->port_clock =
> intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
> -
> -	intel_ddi_get_config(encoder, crtc_state);
> -}
> -
>  static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)  {
>  	return pll->info->id == DPLL_ID_ICL_TBTPLL; @@ -4316,10 +4303,6
> @@ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder
> *encoder,  {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> -	/* TODO: Remove when the PLL manager is in place. */
> -	mtl_ddi_get_config(encoder, crtc_state);
> -	return;
> -
>  	mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_DEFAULT,
>  			       mtl_port_to_pll_id(display, encoder->port));  }
> @@ -4329,10 +4312,6 @@ static void mtl_ddi_tc_phy_get_config(struct
> intel_encoder *encoder,  {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> -	/* TODO: Remove when the PLL manager is in place. */
> -	mtl_ddi_get_config(encoder, crtc_state);
> -	return;
> -
>  	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
>  		mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_DEFAULT,
>  				       DPLL_ID_ICL_TBTPLL);
> @@ -5322,7 +5301,7 @@ void intel_ddi_init(struct intel_display *display,
>  	} else if (DISPLAY_VER(display) >= 14) {
>  		encoder->enable_clock = intel_mtl_pll_enable_clock;
>  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> -		encoder->port_pll_type = intel_mtl_port_pll_type;
> +		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
>  		if (intel_encoder_is_tc(encoder))
>  			encoder->get_config = mtl_ddi_tc_phy_get_config;
>  		else
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e7bb8ec0d6bb..6c8a7f63111e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4977,23 +4977,6 @@ pipe_config_pll_mismatch(struct drm_printer *p,
> bool fastset,
>  	intel_dpll_dump_hw_state(display, p, b);  }
> 
> -static void
> -pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> -			    const struct intel_crtc *crtc,
> -			    const char *name,
> -			    const struct intel_cx0pll_state *a,
> -			    const struct intel_cx0pll_state *b)
> -{
> -	char *chipname = a->use_c10 ? "C10" : "C20";
> -
> -	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> -
> -	drm_printf(p, "expected:\n");
> -	intel_cx0pll_dump_hw_state(p, a);
> -	drm_printf(p, "found:\n");
> -	intel_cx0pll_dump_hw_state(p, b);
> -}
> -
>  static bool allow_vblank_delay_fastset(const struct intel_crtc_state
> *old_crtc_state)  {
>  	struct intel_display *display = to_intel_display(old_crtc_state); @@ -
> 5145,16 +5128,6 @@ intel_pipe_config_compare(const struct intel_crtc_state
> *current_config,
>  	} \
>  } while (0)
> 
> -#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
> -	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
> -					   &pipe_config->name)) { \
> -		pipe_config_cx0pll_mismatch(&p, fastset, crtc,
> __stringify(name), \
> -					    &current_config->name, \
> -					    &pipe_config->name); \
> -		ret = false; \
> -	} \
> -} while (0)
> -
>  #define PIPE_CONF_CHECK_PLL_LT(name) do { \
>  	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
>  					       &pipe_config->name)) { \
> @@ -5394,8 +5367,6 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	/* FIXME convert MTL+ platforms over to dpll_mgr */
>  	if (HAS_LT_PHY(display))
>  		PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
> -	else if (DISPLAY_VER(display) >= 14)
> -		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
> 
>  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>  	PIPE_CONF_CHECK_X(dsi_pll.div);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 2da65bb20f1c..a4f372c9e6fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1212,27 +1212,6 @@ static int dg2_crtc_compute_clock(struct
> intel_atomic_state *state,
>  	return 0;
>  }
> 
> -static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> -				  struct intel_crtc *crtc)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_encoder *encoder =
> -		intel_get_crtc_new_encoder(state, crtc_state);
> -	int ret;
> -
> -	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state-
> >dpll_hw_state);
> -	if (ret)
> -		return ret;
> -
> -	/* TODO: Do the readback via intel_dpll_compute() */
> -	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> &crtc_state->dpll_hw_state.cx0pll);
> -
> -	crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
> -
> -	return 0;
> -}
> -
>  static int xe3plpd_crtc_compute_clock(struct intel_atomic_state *state,
>  				      struct intel_crtc *crtc)
>  {
> @@ -1719,7 +1698,7 @@ static const struct intel_dpll_global_funcs
> xe3plpd_dpll_funcs = {  };
> 
>  static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
> -	.crtc_compute_clock = mtl_crtc_compute_clock,
> +	.crtc_compute_clock = hsw_crtc_compute_clock,
>  	.crtc_get_dpll = hsw_crtc_get_dpll,
>  };
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8fd3b06f393d..6d7d5394713d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct
> intel_dpll_hw_state *_a,
>  	return intel_cx0pll_compare_hw_state(a, b);  }
> 
> -__maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
>  	.compute_dplls = mtl_compute_dplls,
> @@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display *display)
> 
>  	mutex_init(&display->dpll.lock);
> 
> -	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> -		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
> +	if (DISPLAY_VER(display) >= 35 || display->platform.dg2)
> +		/* No shared DPLLs on NVL or DG2; port PLLs are part of the
> PHY */
>  		dpll_mgr = NULL;
> +	else if (DISPLAY_VER(display) >= 14)
> +		dpll_mgr = &mtl_pll_mgr;
>  	else if (display->platform.alderlake_p)
>  		dpll_mgr = &adlp_pll_mgr;
>  	else if (display->platform.alderlake_s)
> --
> 2.34.1

✗ CI.checkpatch: warning for drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework
URL   : https://patchwork.freedesktop.org/series/157658/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e11df711629e63976beec4389c5b3ff46ab5bf7a
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Mon Nov 17 12:46:02 2025 +0200

    drm/i915/cx0: Enable dpll framework for MTL+
    
    Now that MTL+ platforms are supported by dpll framework
    remove a separate check for hw comparison and rely solely
    on dpll framework hw comparison.
    
    Finally, all required hooks are now in place so initialize
    PLL manager for MTL+ platforms and remove the redirections
    to the legacy code paths from the following interfaces:
    
    * intel_encoder::clock_enable/disable()
    * intel_encoder::get_config()
    * intel_dpll_funcs::get_hw_state()
    * intel_ddi_update_active_dpll()
    * pipe_config_pll_mismatch()
    
    Signed-off-by: Mika Kahola <mika.kahola@intel.com>
+ /mt/dim checkpatch b2e41c70a5eeddce427dc6df02508b6856eb4a11 drm-intel
ad11fa405863 drm/i915/cx0: Rename TBT functions to be ICL specific
ff9be16f4768 drm/i915/cx0: Factor out C10 msgbus access start/end helpers
f60dc166bfd1 drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
a521df371b14 drm/i915/cx0: Sanitize calculating C20 PLL state from tables
1b757536e3b1 drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
1e92a496de0f drm/i915/cx0: Move definition of Cx0 PHY functions earlier
743e57ef86a5 drm/i915/cx0: Add macro to get DDI port width from a register value
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'width' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2352:
+#define  DDI_PORT_WIDTH_ENCODE(width)		((width) == 3 ? 4 : (width) - 1)

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regval' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2353:
+#define  DDI_PORT_WIDTH_DECODE(regval)		((regval) == 4 ? 3 : (regval) + 1)

-:28: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2356:
+#define  DDI_PORT_WIDTH_GET(regval)		DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \

total: 0 errors, 1 warnings, 2 checks, 14 lines checked
97b7f3f0dad8 drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
32d36e5b18ff drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
b1bebf91fed3 drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
2f00918bf4d0 drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
5f871879bd30 drm/i915/cx0: Determine Cx0 PLL port clock from PLL state
02f76d7e81f9 drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
8fd87871e795 drm/i915/cx0: Print additional Cx0 PLL HW state
9b199ce96069 drm/i915/cx0: Remove state verification
028ead798da8 drm/i915/cx0: Add PLL information for MTL+
f30d5da0eda8 drm/i915/cx0: Update C10/C20 state calculation
d7eb2e2df6df drm/i915/cx0: Compute plls for MTL+ platform
6466b2acbae7 drm/i915/cx0: Add MTL+ .get_dplls hook
-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:3515:
+static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc,

total: 0 errors, 0 warnings, 1 checks, 86 lines checked
1907238460ef drm/i915/cx0: Add MTL+ .put_dplls hook
ece6e0a2eba5 drm/i915/cx0: Add MTL+ .update_active_dpll hook
b5d4d942baee drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
b70c8aa172d2 drm/i915/cx0: Add MTL+ .dump_hw_state hook
229308cb1123 drm/i915/cx0: Add .compare_hw_state hook
12a529fff606 drm/i915/cx0: Add MTL+ .get_hw_state hook
b36b6a9e4d9a drm/i915/cx0: Add MTL+ .get_freq hook
acd56a0721f0 drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
5c9520e59106 drm/i915/cx0: PLL verify debug state print
55393895e719 drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
79c5e7bdba10 drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
-:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4318:
+static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
+					     struct intel_crtc_state *crtc_state)

total: 0 errors, 0 warnings, 1 checks, 99 lines checked
8b508c38bb67 drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
e11df711629e drm/i915/cx0: Enable dpll framework for MTL+

✓ CI.KUnit: success for drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework
URL   : https://patchwork.freedesktop.org/series/157658/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:06:31] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:06:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:07:06] Starting KUnit Kernel (1/1)...
[11:07:06] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:07:06] ================== guc_buf (11 subtests) ===================
[11:07:06] [PASSED] test_smallest
[11:07:06] [PASSED] test_largest
[11:07:06] [PASSED] test_granular
[11:07:06] [PASSED] test_unique
[11:07:06] [PASSED] test_overlap
[11:07:06] [PASSED] test_reusable
[11:07:06] [PASSED] test_too_big
[11:07:06] [PASSED] test_flush
[11:07:06] [PASSED] test_lookup
[11:07:06] [PASSED] test_data
[11:07:06] [PASSED] test_class
[11:07:06] ===================== [PASSED] guc_buf =====================
[11:07:06] =================== guc_dbm (7 subtests) ===================
[11:07:06] [PASSED] test_empty
[11:07:06] [PASSED] test_default
[11:07:06] ======================== test_size  ========================
[11:07:06] [PASSED] 4
[11:07:06] [PASSED] 8
[11:07:06] [PASSED] 32
[11:07:06] [PASSED] 256
[11:07:06] ==================== [PASSED] test_size ====================
[11:07:06] ======================= test_reuse  ========================
[11:07:06] [PASSED] 4
[11:07:06] [PASSED] 8
[11:07:06] [PASSED] 32
[11:07:06] [PASSED] 256
[11:07:06] =================== [PASSED] test_reuse ====================
[11:07:06] =================== test_range_overlap  ====================
[11:07:06] [PASSED] 4
[11:07:06] [PASSED] 8
[11:07:06] [PASSED] 32
[11:07:06] [PASSED] 256
[11:07:06] =============== [PASSED] test_range_overlap ================
[11:07:06] =================== test_range_compact  ====================
[11:07:06] [PASSED] 4
[11:07:06] [PASSED] 8
[11:07:06] [PASSED] 32
[11:07:06] [PASSED] 256
[11:07:06] =============== [PASSED] test_range_compact ================
[11:07:06] ==================== test_range_spare  =====================
[11:07:06] [PASSED] 4
[11:07:06] [PASSED] 8
[11:07:06] [PASSED] 32
[11:07:06] [PASSED] 256
[11:07:06] ================ [PASSED] test_range_spare =================
[11:07:06] ===================== [PASSED] guc_dbm =====================
[11:07:06] =================== guc_idm (6 subtests) ===================
[11:07:06] [PASSED] bad_init
[11:07:06] [PASSED] no_init
[11:07:06] [PASSED] init_fini
[11:07:06] [PASSED] check_used
[11:07:06] [PASSED] check_quota
[11:07:06] [PASSED] check_all
[11:07:06] ===================== [PASSED] guc_idm =====================
[11:07:06] ================== no_relay (3 subtests) ===================
[11:07:06] [PASSED] xe_drops_guc2pf_if_not_ready
[11:07:06] [PASSED] xe_drops_guc2vf_if_not_ready
[11:07:06] [PASSED] xe_rejects_send_if_not_ready
[11:07:06] ==================== [PASSED] no_relay =====================
[11:07:06] ================== pf_relay (14 subtests) ==================
[11:07:06] [PASSED] pf_rejects_guc2pf_too_short
[11:07:06] [PASSED] pf_rejects_guc2pf_too_long
[11:07:06] [PASSED] pf_rejects_guc2pf_no_payload
[11:07:06] [PASSED] pf_fails_no_payload
[11:07:06] [PASSED] pf_fails_bad_origin
[11:07:06] [PASSED] pf_fails_bad_type
[11:07:06] [PASSED] pf_txn_reports_error
[11:07:06] [PASSED] pf_txn_sends_pf2guc
[11:07:06] [PASSED] pf_sends_pf2guc
[11:07:06] [SKIPPED] pf_loopback_nop
[11:07:06] [SKIPPED] pf_loopback_echo
[11:07:06] [SKIPPED] pf_loopback_fail
[11:07:06] [SKIPPED] pf_loopback_busy
[11:07:06] [SKIPPED] pf_loopback_retry
[11:07:06] ==================== [PASSED] pf_relay =====================
[11:07:06] ================== vf_relay (3 subtests) ===================
[11:07:06] [PASSED] vf_rejects_guc2vf_too_short
[11:07:06] [PASSED] vf_rejects_guc2vf_too_long
[11:07:06] [PASSED] vf_rejects_guc2vf_no_payload
[11:07:06] ==================== [PASSED] vf_relay =====================
[11:07:06] ================ pf_gt_config (6 subtests) =================
[11:07:06] [PASSED] fair_contexts_1vf
[11:07:06] [PASSED] fair_doorbells_1vf
[11:07:06] [PASSED] fair_ggtt_1vf
[11:07:06] ====================== fair_contexts  ======================
[11:07:06] [PASSED] 1 VF
[11:07:06] [PASSED] 2 VFs
[11:07:06] [PASSED] 3 VFs
[11:07:06] [PASSED] 4 VFs
[11:07:06] [PASSED] 5 VFs
[11:07:06] [PASSED] 6 VFs
[11:07:06] [PASSED] 7 VFs
[11:07:06] [PASSED] 8 VFs
[11:07:06] [PASSED] 9 VFs
[11:07:06] [PASSED] 10 VFs
[11:07:06] [PASSED] 11 VFs
[11:07:06] [PASSED] 12 VFs
[11:07:06] [PASSED] 13 VFs
[11:07:06] [PASSED] 14 VFs
[11:07:06] [PASSED] 15 VFs
[11:07:06] [PASSED] 16 VFs
[11:07:06] [PASSED] 17 VFs
[11:07:06] [PASSED] 18 VFs
[11:07:06] [PASSED] 19 VFs
[11:07:06] [PASSED] 20 VFs
[11:07:06] [PASSED] 21 VFs
[11:07:06] [PASSED] 22 VFs
[11:07:06] [PASSED] 23 VFs
[11:07:06] [PASSED] 24 VFs
[11:07:06] [PASSED] 25 VFs
[11:07:06] [PASSED] 26 VFs
[11:07:06] [PASSED] 27 VFs
[11:07:06] [PASSED] 28 VFs
[11:07:06] [PASSED] 29 VFs
[11:07:06] [PASSED] 30 VFs
[11:07:06] [PASSED] 31 VFs
[11:07:06] [PASSED] 32 VFs
[11:07:06] [PASSED] 33 VFs
[11:07:06] [PASSED] 34 VFs
[11:07:06] [PASSED] 35 VFs
[11:07:06] [PASSED] 36 VFs
[11:07:06] [PASSED] 37 VFs
[11:07:06] [PASSED] 38 VFs
[11:07:06] [PASSED] 39 VFs
[11:07:06] [PASSED] 40 VFs
[11:07:06] [PASSED] 41 VFs
[11:07:06] [PASSED] 42 VFs
[11:07:06] [PASSED] 43 VFs
[11:07:06] [PASSED] 44 VFs
[11:07:06] [PASSED] 45 VFs
[11:07:06] [PASSED] 46 VFs
[11:07:06] [PASSED] 47 VFs
[11:07:06] [PASSED] 48 VFs
[11:07:06] [PASSED] 49 VFs
[11:07:06] [PASSED] 50 VFs
[11:07:06] [PASSED] 51 VFs
[11:07:06] [PASSED] 52 VFs
[11:07:06] [PASSED] 53 VFs
[11:07:06] [PASSED] 54 VFs
[11:07:06] [PASSED] 55 VFs
[11:07:06] [PASSED] 56 VFs
[11:07:06] [PASSED] 57 VFs
[11:07:06] [PASSED] 58 VFs
[11:07:06] [PASSED] 59 VFs
[11:07:06] [PASSED] 60 VFs
[11:07:06] [PASSED] 61 VFs
[11:07:06] [PASSED] 62 VFs
[11:07:06] [PASSED] 63 VFs
[11:07:06] ================== [PASSED] fair_contexts ==================
[11:07:06] ===================== fair_doorbells  ======================
[11:07:06] [PASSED] 1 VF
[11:07:06] [PASSED] 2 VFs
[11:07:06] [PASSED] 3 VFs
[11:07:06] [PASSED] 4 VFs
[11:07:06] [PASSED] 5 VFs
[11:07:06] [PASSED] 6 VFs
[11:07:06] [PASSED] 7 VFs
[11:07:06] [PASSED] 8 VFs
[11:07:06] [PASSED] 9 VFs
[11:07:06] [PASSED] 10 VFs
[11:07:06] [PASSED] 11 VFs
[11:07:06] [PASSED] 12 VFs
[11:07:06] [PASSED] 13 VFs
[11:07:06] [PASSED] 14 VFs
[11:07:06] [PASSED] 15 VFs
[11:07:06] [PASSED] 16 VFs
[11:07:06] [PASSED] 17 VFs
[11:07:06] [PASSED] 18 VFs
[11:07:06] [PASSED] 19 VFs
[11:07:06] [PASSED] 20 VFs
[11:07:06] [PASSED] 21 VFs
[11:07:06] [PASSED] 22 VFs
[11:07:06] [PASSED] 23 VFs
[11:07:06] [PASSED] 24 VFs
[11:07:06] [PASSED] 25 VFs
[11:07:06] [PASSED] 26 VFs
[11:07:06] [PASSED] 27 VFs
[11:07:06] [PASSED] 28 VFs
[11:07:06] [PASSED] 29 VFs
[11:07:06] [PASSED] 30 VFs
[11:07:06] [PASSED] 31 VFs
[11:07:06] [PASSED] 32 VFs
[11:07:06] [PASSED] 33 VFs
[11:07:06] [PASSED] 34 VFs
[11:07:06] [PASSED] 35 VFs
[11:07:06] [PASSED] 36 VFs
[11:07:06] [PASSED] 37 VFs
[11:07:06] [PASSED] 38 VFs
[11:07:06] [PASSED] 39 VFs
[11:07:06] [PASSED] 40 VFs
[11:07:06] [PASSED] 41 VFs
[11:07:06] [PASSED] 42 VFs
[11:07:06] [PASSED] 43 VFs
[11:07:06] [PASSED] 44 VFs
[11:07:06] [PASSED] 45 VFs
[11:07:06] [PASSED] 46 VFs
[11:07:06] [PASSED] 47 VFs
[11:07:06] [PASSED] 48 VFs
[11:07:06] [PASSED] 49 VFs
[11:07:06] [PASSED] 50 VFs
[11:07:06] [PASSED] 51 VFs
[11:07:06] [PASSED] 52 VFs
[11:07:06] [PASSED] 53 VFs
[11:07:06] [PASSED] 54 VFs
[11:07:06] [PASSED] 55 VFs
[11:07:06] [PASSED] 56 VFs
[11:07:06] [PASSED] 57 VFs
[11:07:06] [PASSED] 58 VFs
[11:07:06] [PASSED] 59 VFs
[11:07:06] [PASSED] 60 VFs
[11:07:06] [PASSED] 61 VFs
[11:07:06] [PASSED] 62 VFs
[11:07:06] [PASSED] 63 VFs
[11:07:06] ================= [PASSED] fair_doorbells ==================
[11:07:06] ======================== fair_ggtt  ========================
[11:07:06] [PASSED] 1 VF
[11:07:06] [PASSED] 2 VFs
[11:07:06] [PASSED] 3 VFs
[11:07:06] [PASSED] 4 VFs
[11:07:06] [PASSED] 5 VFs
[11:07:06] [PASSED] 6 VFs
[11:07:06] [PASSED] 7 VFs
[11:07:06] [PASSED] 8 VFs
[11:07:06] [PASSED] 9 VFs
[11:07:06] [PASSED] 10 VFs
[11:07:06] [PASSED] 11 VFs
[11:07:06] [PASSED] 12 VFs
[11:07:06] [PASSED] 13 VFs
[11:07:06] [PASSED] 14 VFs
[11:07:06] [PASSED] 15 VFs
[11:07:06] [PASSED] 16 VFs
[11:07:06] [PASSED] 17 VFs
[11:07:06] [PASSED] 18 VFs
[11:07:06] [PASSED] 19 VFs
[11:07:06] [PASSED] 20 VFs
[11:07:06] [PASSED] 21 VFs
[11:07:06] [PASSED] 22 VFs
[11:07:06] [PASSED] 23 VFs
[11:07:06] [PASSED] 24 VFs
[11:07:06] [PASSED] 25 VFs
[11:07:06] [PASSED] 26 VFs
[11:07:06] [PASSED] 27 VFs
[11:07:06] [PASSED] 28 VFs
[11:07:06] [PASSED] 29 VFs
[11:07:06] [PASSED] 30 VFs
[11:07:06] [PASSED] 31 VFs
[11:07:06] [PASSED] 32 VFs
[11:07:06] [PASSED] 33 VFs
[11:07:06] [PASSED] 34 VFs
[11:07:06] [PASSED] 35 VFs
[11:07:06] [PASSED] 36 VFs
[11:07:06] [PASSED] 37 VFs
[11:07:06] [PASSED] 38 VFs
[11:07:06] [PASSED] 39 VFs
[11:07:06] [PASSED] 40 VFs
[11:07:06] [PASSED] 41 VFs
[11:07:06] [PASSED] 42 VFs
[11:07:06] [PASSED] 43 VFs
[11:07:06] [PASSED] 44 VFs
[11:07:06] [PASSED] 45 VFs
[11:07:06] [PASSED] 46 VFs
[11:07:06] [PASSED] 47 VFs
[11:07:06] [PASSED] 48 VFs
[11:07:06] [PASSED] 49 VFs
[11:07:06] [PASSED] 50 VFs
[11:07:06] [PASSED] 51 VFs
[11:07:06] [PASSED] 52 VFs
[11:07:06] [PASSED] 53 VFs
[11:07:06] [PASSED] 54 VFs
[11:07:06] [PASSED] 55 VFs
[11:07:06] [PASSED] 56 VFs
[11:07:06] [PASSED] 57 VFs
[11:07:06] [PASSED] 58 VFs
[11:07:06] [PASSED] 59 VFs
[11:07:06] [PASSED] 60 VFs
[11:07:06] [PASSED] 61 VFs
[11:07:06] [PASSED] 62 VFs
[11:07:06] [PASSED] 63 VFs
[11:07:06] ==================== [PASSED] fair_ggtt ====================
[11:07:06] ================== [PASSED] pf_gt_config ===================
[11:07:06] ===================== lmtt (1 subtest) =====================
[11:07:06] ======================== test_ops  =========================
[11:07:06] [PASSED] 2-level
[11:07:06] [PASSED] multi-level
[11:07:06] ==================== [PASSED] test_ops =====================
[11:07:06] ====================== [PASSED] lmtt =======================
[11:07:06] ================= pf_service (11 subtests) =================
[11:07:06] [PASSED] pf_negotiate_any
[11:07:06] [PASSED] pf_negotiate_base_match
[11:07:06] [PASSED] pf_negotiate_base_newer
[11:07:06] [PASSED] pf_negotiate_base_next
[11:07:06] [SKIPPED] pf_negotiate_base_older
[11:07:06] [PASSED] pf_negotiate_base_prev
[11:07:06] [PASSED] pf_negotiate_latest_match
[11:07:06] [PASSED] pf_negotiate_latest_newer
[11:07:06] [PASSED] pf_negotiate_latest_next
[11:07:06] [SKIPPED] pf_negotiate_latest_older
[11:07:06] [SKIPPED] pf_negotiate_latest_prev
[11:07:06] =================== [PASSED] pf_service ====================
[11:07:06] ================= xe_guc_g2g (2 subtests) ==================
[11:07:06] ============== xe_live_guc_g2g_kunit_default  ==============
[11:07:06] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:07:06] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:07:06] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:07:06] =================== [SKIPPED] xe_guc_g2g ===================
[11:07:06] =================== xe_mocs (2 subtests) ===================
[11:07:06] ================ xe_live_mocs_kernel_kunit  ================
[11:07:06] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:07:06] ================ xe_live_mocs_reset_kunit  =================
[11:07:06] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:07:06] ==================== [SKIPPED] xe_mocs =====================
[11:07:06] ================= xe_migrate (2 subtests) ==================
[11:07:06] ================= xe_migrate_sanity_kunit  =================
[11:07:06] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:07:06] ================== xe_validate_ccs_kunit  ==================
[11:07:06] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:07:06] =================== [SKIPPED] xe_migrate ===================
[11:07:06] ================== xe_dma_buf (1 subtest) ==================
[11:07:06] ==================== xe_dma_buf_kunit  =====================
[11:07:06] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:07:06] =================== [SKIPPED] xe_dma_buf ===================
[11:07:06] ================= xe_bo_shrink (1 subtest) =================
[11:07:06] =================== xe_bo_shrink_kunit  ====================
[11:07:06] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:07:06] ================== [SKIPPED] xe_bo_shrink ==================
[11:07:06] ==================== xe_bo (2 subtests) ====================
[11:07:06] ================== xe_ccs_migrate_kunit  ===================
[11:07:06] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:07:06] ==================== xe_bo_evict_kunit  ====================
[11:07:06] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:07:06] ===================== [SKIPPED] xe_bo ======================
[11:07:06] ==================== args (11 subtests) ====================
[11:07:06] [PASSED] count_args_test
[11:07:06] [PASSED] call_args_example
[11:07:06] [PASSED] call_args_test
[11:07:06] [PASSED] drop_first_arg_example
[11:07:06] [PASSED] drop_first_arg_test
[11:07:06] [PASSED] first_arg_example
[11:07:06] [PASSED] first_arg_test
[11:07:06] [PASSED] last_arg_example
[11:07:06] [PASSED] last_arg_test
[11:07:06] [PASSED] pick_arg_example
[11:07:06] [PASSED] sep_comma_example
[11:07:06] ====================== [PASSED] args =======================
[11:07:06] =================== xe_pci (3 subtests) ====================
[11:07:06] ==================== check_graphics_ip  ====================
[11:07:06] [PASSED] 12.00 Xe_LP
[11:07:06] [PASSED] 12.10 Xe_LP+
[11:07:06] [PASSED] 12.55 Xe_HPG
[11:07:06] [PASSED] 12.60 Xe_HPC
[11:07:06] [PASSED] 12.70 Xe_LPG
[11:07:06] [PASSED] 12.71 Xe_LPG
[11:07:06] [PASSED] 12.74 Xe_LPG+
[11:07:06] [PASSED] 20.01 Xe2_HPG
[11:07:06] [PASSED] 20.02 Xe2_HPG
[11:07:06] [PASSED] 20.04 Xe2_LPG
[11:07:06] [PASSED] 30.00 Xe3_LPG
[11:07:06] [PASSED] 30.01 Xe3_LPG
[11:07:06] [PASSED] 30.03 Xe3_LPG
[11:07:06] [PASSED] 30.04 Xe3_LPG
[11:07:06] [PASSED] 30.05 Xe3_LPG
[11:07:06] [PASSED] 35.11 Xe3p_XPC
[11:07:06] ================ [PASSED] check_graphics_ip ================
[11:07:06] ===================== check_media_ip  ======================
[11:07:06] [PASSED] 12.00 Xe_M
[11:07:06] [PASSED] 12.55 Xe_HPM
[11:07:06] [PASSED] 13.00 Xe_LPM+
[11:07:06] [PASSED] 13.01 Xe2_HPM
[11:07:06] [PASSED] 20.00 Xe2_LPM
[11:07:06] [PASSED] 30.00 Xe3_LPM
[11:07:06] [PASSED] 30.02 Xe3_LPM
[11:07:06] [PASSED] 35.00 Xe3p_LPM
[11:07:06] [PASSED] 35.03 Xe3p_HPM
[11:07:06] ================= [PASSED] check_media_ip ==================
[11:07:06] =================== check_platform_desc  ===================
[11:07:06] [PASSED] 0x9A60 (TIGERLAKE)
[11:07:06] [PASSED] 0x9A68 (TIGERLAKE)
[11:07:06] [PASSED] 0x9A70 (TIGERLAKE)
[11:07:06] [PASSED] 0x9A40 (TIGERLAKE)
[11:07:06] [PASSED] 0x9A49 (TIGERLAKE)
[11:07:06] [PASSED] 0x9A59 (TIGERLAKE)
[11:07:06] [PASSED] 0x9A78 (TIGERLAKE)
[11:07:06] [PASSED] 0x9AC0 (TIGERLAKE)
[11:07:06] [PASSED] 0x9AC9 (TIGERLAKE)
[11:07:06] [PASSED] 0x9AD9 (TIGERLAKE)
[11:07:06] [PASSED] 0x9AF8 (TIGERLAKE)
[11:07:06] [PASSED] 0x4C80 (ROCKETLAKE)
[11:07:06] [PASSED] 0x4C8A (ROCKETLAKE)
[11:07:06] [PASSED] 0x4C8B (ROCKETLAKE)
[11:07:06] [PASSED] 0x4C8C (ROCKETLAKE)
[11:07:06] [PASSED] 0x4C90 (ROCKETLAKE)
[11:07:06] [PASSED] 0x4C9A (ROCKETLAKE)
[11:07:06] [PASSED] 0x4680 (ALDERLAKE_S)
[11:07:06] [PASSED] 0x4682 (ALDERLAKE_S)
[11:07:06] [PASSED] 0x4688 (ALDERLAKE_S)
[11:07:06] [PASSED] 0x468A (ALDERLAKE_S)
[11:07:06] [PASSED] 0x468B (ALDERLAKE_S)
[11:07:06] [PASSED] 0x4690 (ALDERLAKE_S)
[11:07:06] [PASSED] 0x4692 (ALDERLAKE_S)
[11:07:06] [PASSED] 0x4693 (ALDERLAKE_S)
[11:07:06] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46AA (ALDERLAKE_P)
[11:07:06] [PASSED] 0x462A (ALDERLAKE_P)
[11:07:06] [PASSED] 0x4626 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x4628 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[11:07:06] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:07:06] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:07:06] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:07:06] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:07:06] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:07:06] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:07:06] [PASSED] 0xA721 (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA720 (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:07:06] [PASSED] 0xA780 (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA781 (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA782 (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA783 (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA788 (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA789 (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA78A (ALDERLAKE_S)
[11:07:06] [PASSED] 0xA78B (ALDERLAKE_S)
[11:07:06] [PASSED] 0x4905 (DG1)
[11:07:06] [PASSED] 0x4906 (DG1)
[11:07:06] [PASSED] 0x4907 (DG1)
[11:07:06] [PASSED] 0x4908 (DG1)
[11:07:06] [PASSED] 0x4909 (DG1)
[11:07:06] [PASSED] 0x56C0 (DG2)
[11:07:06] [PASSED] 0x56C2 (DG2)
[11:07:06] [PASSED] 0x56C1 (DG2)
[11:07:06] [PASSED] 0x7D51 (METEORLAKE)
[11:07:06] [PASSED] 0x7DD1 (METEORLAKE)
[11:07:06] [PASSED] 0x7D41 (METEORLAKE)
[11:07:06] [PASSED] 0x7D67 (METEORLAKE)
[11:07:06] [PASSED] 0xB640 (METEORLAKE)
[11:07:06] [PASSED] 0x56A0 (DG2)
[11:07:06] [PASSED] 0x56A1 (DG2)
[11:07:06] [PASSED] 0x56A2 (DG2)
[11:07:06] [PASSED] 0x56BE (DG2)
[11:07:06] [PASSED] 0x56BF (DG2)
[11:07:06] [PASSED] 0x5690 (DG2)
[11:07:06] [PASSED] 0x5691 (DG2)
[11:07:06] [PASSED] 0x5692 (DG2)
[11:07:06] [PASSED] 0x56A5 (DG2)
[11:07:06] [PASSED] 0x56A6 (DG2)
[11:07:06] [PASSED] 0x56B0 (DG2)
[11:07:06] [PASSED] 0x56B1 (DG2)
[11:07:06] [PASSED] 0x56BA (DG2)
[11:07:06] [PASSED] 0x56BB (DG2)
[11:07:06] [PASSED] 0x56BC (DG2)
[11:07:06] [PASSED] 0x56BD (DG2)
[11:07:06] [PASSED] 0x5693 (DG2)
[11:07:06] [PASSED] 0x5694 (DG2)
[11:07:06] [PASSED] 0x5695 (DG2)
[11:07:06] [PASSED] 0x56A3 (DG2)
[11:07:06] [PASSED] 0x56A4 (DG2)
[11:07:06] [PASSED] 0x56B2 (DG2)
[11:07:06] [PASSED] 0x56B3 (DG2)
[11:07:06] [PASSED] 0x5696 (DG2)
[11:07:06] [PASSED] 0x5697 (DG2)
[11:07:06] [PASSED] 0xB69 (PVC)
[11:07:06] [PASSED] 0xB6E (PVC)
[11:07:06] [PASSED] 0xBD4 (PVC)
[11:07:06] [PASSED] 0xBD5 (PVC)
[11:07:06] [PASSED] 0xBD6 (PVC)
[11:07:06] [PASSED] 0xBD7 (PVC)
[11:07:06] [PASSED] 0xBD8 (PVC)
[11:07:06] [PASSED] 0xBD9 (PVC)
[11:07:06] [PASSED] 0xBDA (PVC)
[11:07:06] [PASSED] 0xBDB (PVC)
[11:07:06] [PASSED] 0xBE0 (PVC)
[11:07:06] [PASSED] 0xBE1 (PVC)
[11:07:06] [PASSED] 0xBE5 (PVC)
[11:07:06] [PASSED] 0x7D40 (METEORLAKE)
[11:07:06] [PASSED] 0x7D45 (METEORLAKE)
[11:07:06] [PASSED] 0x7D55 (METEORLAKE)
[11:07:06] [PASSED] 0x7D60 (METEORLAKE)
[11:07:06] [PASSED] 0x7DD5 (METEORLAKE)
[11:07:06] [PASSED] 0x6420 (LUNARLAKE)
[11:07:06] [PASSED] 0x64A0 (LUNARLAKE)
[11:07:06] [PASSED] 0x64B0 (LUNARLAKE)
[11:07:06] [PASSED] 0xE202 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE209 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE20B (BATTLEMAGE)
[11:07:06] [PASSED] 0xE20C (BATTLEMAGE)
[11:07:06] [PASSED] 0xE20D (BATTLEMAGE)
[11:07:06] [PASSED] 0xE210 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE211 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE212 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE216 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE220 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE221 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE222 (BATTLEMAGE)
[11:07:06] [PASSED] 0xE223 (BATTLEMAGE)
[11:07:06] [PASSED] 0xB080 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB081 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB082 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB083 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB084 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB085 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB086 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB087 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB08F (PANTHERLAKE)
[11:07:06] [PASSED] 0xB090 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:07:06] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:07:06] [PASSED] 0xD740 (NOVALAKE_S)
[11:07:06] [PASSED] 0xD741 (NOVALAKE_S)
[11:07:06] [PASSED] 0xD742 (NOVALAKE_S)
[11:07:06] [PASSED] 0xD743 (NOVALAKE_S)
[11:07:06] [PASSED] 0xD744 (NOVALAKE_S)
[11:07:06] [PASSED] 0xD745 (NOVALAKE_S)
[11:07:06] [PASSED] 0x674C (CRESCENTISLAND)
[11:07:06] [PASSED] 0xFD80 (PANTHERLAKE)
[11:07:06] [PASSED] 0xFD81 (PANTHERLAKE)
[11:07:06] =============== [PASSED] check_platform_desc ===============
[11:07:06] ===================== [PASSED] xe_pci ======================
[11:07:06] =================== xe_rtp (2 subtests) ====================
[11:07:06] =============== xe_rtp_process_to_sr_tests  ================
[11:07:06] [PASSED] coalesce-same-reg
[11:07:06] [PASSED] no-match-no-add
[11:07:06] [PASSED] match-or
[11:07:06] [PASSED] match-or-xfail
[11:07:06] [PASSED] no-match-no-add-multiple-rules
[11:07:06] [PASSED] two-regs-two-entries
[11:07:06] [PASSED] clr-one-set-other
[11:07:06] [PASSED] set-field
[11:07:06] [PASSED] conflict-duplicate
[11:07:06] [PASSED] conflict-not-disjoint
[11:07:06] [PASSED] conflict-reg-type
[11:07:06] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:07:06] ================== xe_rtp_process_tests  ===================
[11:07:06] [PASSED] active1
[11:07:06] [PASSED] active2
[11:07:06] [PASSED] active-inactive
[11:07:06] [PASSED] inactive-active
[11:07:06] [PASSED] inactive-1st_or_active-inactive
[11:07:06] [PASSED] inactive-2nd_or_active-inactive
[11:07:06] [PASSED] inactive-last_or_active-inactive
[11:07:06] [PASSED] inactive-no_or_active-inactive
[11:07:06] ============== [PASSED] xe_rtp_process_tests ===============
[11:07:06] ===================== [PASSED] xe_rtp ======================
[11:07:06] ==================== xe_wa (1 subtest) =====================
[11:07:06] ======================== xe_wa_gt  =========================
[11:07:06] [PASSED] TIGERLAKE B0
[11:07:06] [PASSED] DG1 A0
[11:07:06] [PASSED] DG1 B0
[11:07:06] [PASSED] ALDERLAKE_S A0
[11:07:06] [PASSED] ALDERLAKE_S B0
[11:07:06] [PASSED] ALDERLAKE_S C0
[11:07:06] [PASSED] ALDERLAKE_S D0
[11:07:06] [PASSED] ALDERLAKE_P A0
[11:07:06] [PASSED] ALDERLAKE_P B0
[11:07:06] [PASSED] ALDERLAKE_P C0
[11:07:06] [PASSED] ALDERLAKE_S RPLS D0
[11:07:06] [PASSED] ALDERLAKE_P RPLU E0
[11:07:06] [PASSED] DG2 G10 C0
[11:07:06] [PASSED] DG2 G11 B1
[11:07:06] [PASSED] DG2 G12 A1
[11:07:06] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:07:06] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:07:06] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:07:06] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:07:06] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:07:06] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:07:06] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:07:06] ==================== [PASSED] xe_wa_gt =====================
[11:07:06] ====================== [PASSED] xe_wa ======================
[11:07:06] ============================================================
[11:07:06] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[11:07:06] Elapsed time: 35.194s total, 4.292s configuring, 30.386s building, 0.463s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:07:07] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:07:08] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:07:33] Starting KUnit Kernel (1/1)...
[11:07:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:07:33] ============ drm_test_pick_cmdline (2 subtests) ============
[11:07:33] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:07:33] =============== drm_test_pick_cmdline_named  ===============
[11:07:33] [PASSED] NTSC
[11:07:33] [PASSED] NTSC-J
[11:07:33] [PASSED] PAL
[11:07:33] [PASSED] PAL-M
[11:07:33] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:07:33] ============== [PASSED] drm_test_pick_cmdline ==============
[11:07:33] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:07:33] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:07:33] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:07:33] =========== drm_validate_clone_mode (2 subtests) ===========
[11:07:33] ============== drm_test_check_in_clone_mode  ===============
[11:07:33] [PASSED] in_clone_mode
[11:07:33] [PASSED] not_in_clone_mode
[11:07:33] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:07:33] =============== drm_test_check_valid_clones  ===============
[11:07:33] [PASSED] not_in_clone_mode
[11:07:33] [PASSED] valid_clone
[11:07:33] [PASSED] invalid_clone
[11:07:33] =========== [PASSED] drm_test_check_valid_clones ===========
[11:07:33] ============= [PASSED] drm_validate_clone_mode =============
[11:07:33] ============= drm_validate_modeset (1 subtest) =============
[11:07:33] [PASSED] drm_test_check_connector_changed_modeset
[11:07:33] ============== [PASSED] drm_validate_modeset ===============
[11:07:33] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:07:33] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:07:33] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:07:33] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:07:33] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:07:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:07:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:07:33] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:07:33] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:07:33] ============== drm_bridge_alloc (2 subtests) ===============
[11:07:33] [PASSED] drm_test_drm_bridge_alloc_basic
[11:07:33] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:07:33] ================ [PASSED] drm_bridge_alloc =================
[11:07:33] ================== drm_buddy (8 subtests) ==================
[11:07:33] [PASSED] drm_test_buddy_alloc_limit
[11:07:33] [PASSED] drm_test_buddy_alloc_optimistic
[11:07:33] [PASSED] drm_test_buddy_alloc_pessimistic
[11:07:33] [PASSED] drm_test_buddy_alloc_pathological
[11:07:33] [PASSED] drm_test_buddy_alloc_contiguous
[11:07:33] [PASSED] drm_test_buddy_alloc_clear
[11:07:33] [PASSED] drm_test_buddy_alloc_range_bias
[11:07:33] [PASSED] drm_test_buddy_fragmentation_performance
[11:07:33] ==================== [PASSED] drm_buddy ====================
[11:07:33] ============= drm_cmdline_parser (40 subtests) =============
[11:07:33] [PASSED] drm_test_cmdline_force_d_only
[11:07:33] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:07:33] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:07:33] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:07:33] [PASSED] drm_test_cmdline_force_e_only
[11:07:33] [PASSED] drm_test_cmdline_res
[11:07:33] [PASSED] drm_test_cmdline_res_vesa
[11:07:33] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:07:33] [PASSED] drm_test_cmdline_res_rblank
[11:07:33] [PASSED] drm_test_cmdline_res_bpp
[11:07:33] [PASSED] drm_test_cmdline_res_refresh
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:07:33] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:07:33] [PASSED] drm_test_cmdline_res_margins_force_on
[11:07:33] [PASSED] drm_test_cmdline_res_vesa_margins
[11:07:33] [PASSED] drm_test_cmdline_name
[11:07:33] [PASSED] drm_test_cmdline_name_bpp
[11:07:33] [PASSED] drm_test_cmdline_name_option
[11:07:33] [PASSED] drm_test_cmdline_name_bpp_option
[11:07:33] [PASSED] drm_test_cmdline_rotate_0
[11:07:33] [PASSED] drm_test_cmdline_rotate_90
[11:07:33] [PASSED] drm_test_cmdline_rotate_180
[11:07:33] [PASSED] drm_test_cmdline_rotate_270
[11:07:33] [PASSED] drm_test_cmdline_hmirror
[11:07:33] [PASSED] drm_test_cmdline_vmirror
[11:07:33] [PASSED] drm_test_cmdline_margin_options
[11:07:33] [PASSED] drm_test_cmdline_multiple_options
[11:07:33] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:07:33] [PASSED] drm_test_cmdline_extra_and_option
[11:07:33] [PASSED] drm_test_cmdline_freestanding_options
[11:07:33] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:07:33] [PASSED] drm_test_cmdline_panel_orientation
[11:07:33] ================ drm_test_cmdline_invalid  =================
[11:07:33] [PASSED] margin_only
[11:07:33] [PASSED] interlace_only
[11:07:33] [PASSED] res_missing_x
[11:07:33] [PASSED] res_missing_y
[11:07:33] [PASSED] res_bad_y
[11:07:33] [PASSED] res_missing_y_bpp
[11:07:33] [PASSED] res_bad_bpp
[11:07:33] [PASSED] res_bad_refresh
[11:07:33] [PASSED] res_bpp_refresh_force_on_off
[11:07:33] [PASSED] res_invalid_mode
[11:07:33] [PASSED] res_bpp_wrong_place_mode
[11:07:33] [PASSED] name_bpp_refresh
[11:07:33] [PASSED] name_refresh
[11:07:33] [PASSED] name_refresh_wrong_mode
[11:07:33] [PASSED] name_refresh_invalid_mode
[11:07:33] [PASSED] rotate_multiple
[11:07:33] [PASSED] rotate_invalid_val
[11:07:33] [PASSED] rotate_truncated
[11:07:33] [PASSED] invalid_option
[11:07:33] [PASSED] invalid_tv_option
[11:07:33] [PASSED] truncated_tv_option
[11:07:33] ============ [PASSED] drm_test_cmdline_invalid =============
[11:07:33] =============== drm_test_cmdline_tv_options  ===============
[11:07:33] [PASSED] NTSC
[11:07:33] [PASSED] NTSC_443
[11:07:33] [PASSED] NTSC_J
[11:07:33] [PASSED] PAL
[11:07:33] [PASSED] PAL_M
[11:07:33] [PASSED] PAL_N
[11:07:33] [PASSED] SECAM
[11:07:33] [PASSED] MONO_525
[11:07:33] [PASSED] MONO_625
[11:07:33] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:07:33] =============== [PASSED] drm_cmdline_parser ================
[11:07:33] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:07:33] [PASSED] drm_test_connector_hdmi_init_valid
[11:07:33] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:07:33] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:07:33] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:07:33] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:07:33] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:07:33] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:07:33] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:07:33] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:07:33] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:07:33] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:07:33] [PASSED] supported_formats=0x3 yuv420_allowed=1
[11:07:33] [PASSED] supported_formats=0x3 yuv420_allowed=0
[11:07:33] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:07:33] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:07:33] [PASSED] drm_test_connector_hdmi_init_null_product
[11:07:33] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:07:33] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:07:33] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:07:33] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:07:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:07:33] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:07:33] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:07:33] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:07:33] [PASSED] HDMI-A
[11:07:33] [PASSED] HDMI-B
[11:07:33] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:07:33] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:07:33] [PASSED] Unknown
[11:07:33] [PASSED] VGA
[11:07:33] [PASSED] DVI-I
[11:07:33] [PASSED] DVI-D
[11:07:33] [PASSED] DVI-A
[11:07:33] [PASSED] Composite
[11:07:33] [PASSED] SVIDEO
[11:07:33] [PASSED] LVDS
[11:07:33] [PASSED] Component
[11:07:33] [PASSED] DIN
[11:07:33] [PASSED] DP
[11:07:33] [PASSED] TV
[11:07:33] [PASSED] eDP
[11:07:33] [PASSED] Virtual
[11:07:33] [PASSED] DSI
[11:07:33] [PASSED] DPI
[11:07:33] [PASSED] Writeback
[11:07:33] [PASSED] SPI
[11:07:33] [PASSED] USB
[11:07:33] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:07:33] ============ [PASSED] drmm_connector_hdmi_init =============
[11:07:33] ============= drmm_connector_init (3 subtests) =============
[11:07:33] [PASSED] drm_test_drmm_connector_init
[11:07:33] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:07:33] ========= drm_test_drmm_connector_init_type_valid  =========
[11:07:33] [PASSED] Unknown
[11:07:33] [PASSED] VGA
[11:07:33] [PASSED] DVI-I
[11:07:33] [PASSED] DVI-D
[11:07:33] [PASSED] DVI-A
[11:07:33] [PASSED] Composite
[11:07:33] [PASSED] SVIDEO
[11:07:33] [PASSED] LVDS
[11:07:33] [PASSED] Component
[11:07:33] [PASSED] DIN
[11:07:33] [PASSED] DP
[11:07:33] [PASSED] HDMI-A
[11:07:33] [PASSED] HDMI-B
[11:07:33] [PASSED] TV
[11:07:33] [PASSED] eDP
[11:07:33] [PASSED] Virtual
[11:07:33] [PASSED] DSI
[11:07:33] [PASSED] DPI
[11:07:33] [PASSED] Writeback
[11:07:33] [PASSED] SPI
[11:07:33] [PASSED] USB
[11:07:33] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:07:33] =============== [PASSED] drmm_connector_init ===============
[11:07:33] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_init
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:07:33] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:07:33] [PASSED] Unknown
[11:07:33] [PASSED] VGA
[11:07:33] [PASSED] DVI-I
[11:07:33] [PASSED] DVI-D
[11:07:33] [PASSED] DVI-A
[11:07:33] [PASSED] Composite
[11:07:33] [PASSED] SVIDEO
[11:07:33] [PASSED] LVDS
[11:07:33] [PASSED] Component
[11:07:33] [PASSED] DIN
[11:07:33] [PASSED] DP
[11:07:33] [PASSED] HDMI-A
[11:07:33] [PASSED] HDMI-B
[11:07:33] [PASSED] TV
[11:07:33] [PASSED] eDP
[11:07:33] [PASSED] Virtual
[11:07:33] [PASSED] DSI
[11:07:33] [PASSED] DPI
[11:07:33] [PASSED] Writeback
[11:07:33] [PASSED] SPI
[11:07:33] [PASSED] USB
[11:07:33] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:07:33] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:07:33] [PASSED] Unknown
[11:07:33] [PASSED] VGA
[11:07:33] [PASSED] DVI-I
[11:07:33] [PASSED] DVI-D
[11:07:33] [PASSED] DVI-A
[11:07:33] [PASSED] Composite
[11:07:33] [PASSED] SVIDEO
[11:07:33] [PASSED] LVDS
[11:07:33] [PASSED] Component
[11:07:33] [PASSED] DIN
[11:07:33] [PASSED] DP
[11:07:33] [PASSED] HDMI-A
[11:07:33] [PASSED] HDMI-B
[11:07:33] [PASSED] TV
[11:07:33] [PASSED] eDP
[11:07:33] [PASSED] Virtual
[11:07:33] [PASSED] DSI
[11:07:33] [PASSED] DPI
[11:07:33] [PASSED] Writeback
[11:07:33] [PASSED] SPI
[11:07:33] [PASSED] USB
[11:07:33] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:07:33] =========== [PASSED] drm_connector_dynamic_init ============
[11:07:33] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:07:33] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:07:33] ======= drm_connector_dynamic_register (7 subtests) ========
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:07:33] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:07:33] ========= [PASSED] drm_connector_dynamic_register ==========
[11:07:33] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:07:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:07:33] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:07:33] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:07:33] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:07:33] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:07:33] [PASSED] NTSC
[11:07:33] [PASSED] NTSC-443
[11:07:33] [PASSED] NTSC-J
[11:07:33] [PASSED] PAL
[11:07:33] [PASSED] PAL-M
[11:07:33] [PASSED] PAL-N
[11:07:33] [PASSED] SECAM
[11:07:33] [PASSED] Mono
[11:07:33] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:07:33] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:07:33] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:07:33] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:07:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:07:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:07:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:07:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:07:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:07:33] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:07:33] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:07:33] [PASSED] VIC 96
[11:07:33] [PASSED] VIC 97
[11:07:33] [PASSED] VIC 101
[11:07:33] [PASSED] VIC 102
[11:07:33] [PASSED] VIC 106
[11:07:33] [PASSED] VIC 107
[11:07:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:07:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:07:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:07:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:07:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:07:33] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:07:33] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:07:33] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:07:33] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:07:33] [PASSED] Automatic
[11:07:33] [PASSED] Full
[11:07:33] [PASSED] Limited 16:235
[11:07:33] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:07:33] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:07:33] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:07:33] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:07:33] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:07:33] [PASSED] RGB
[11:07:33] [PASSED] YUV 4:2:0
[11:07:33] [PASSED] YUV 4:2:2
[11:07:33] [PASSED] YUV 4:4:4
[11:07:33] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:07:33] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:07:33] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:07:33] ============= drm_damage_helper (21 subtests) ==============
[11:07:33] [PASSED] drm_test_damage_iter_no_damage
[11:07:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:07:33] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:07:33] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:07:33] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:07:33] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:07:33] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:07:33] [PASSED] drm_test_damage_iter_simple_damage
[11:07:33] [PASSED] drm_test_damage_iter_single_damage
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:07:33] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:07:33] [PASSED] drm_test_damage_iter_damage
[11:07:33] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:07:33] [PASSED] drm_test_damage_iter_damage_one_outside
[11:07:33] [PASSED] drm_test_damage_iter_damage_src_moved
[11:07:33] [PASSED] drm_test_damage_iter_damage_not_visible
[11:07:33] ================ [PASSED] drm_damage_helper ================
[11:07:33] ============== drm_dp_mst_helper (3 subtests) ==============
[11:07:33] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:07:33] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:07:33] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:07:33] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:07:33] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:07:33] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:07:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:07:33] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:07:33] [PASSED] Link rate 2000000 lane count 4
[11:07:33] [PASSED] Link rate 2000000 lane count 2
[11:07:33] [PASSED] Link rate 2000000 lane count 1
[11:07:33] [PASSED] Link rate 1350000 lane count 4
[11:07:33] [PASSED] Link rate 1350000 lane count 2
[11:07:33] [PASSED] Link rate 1350000 lane count 1
[11:07:33] [PASSED] Link rate 1000000 lane count 4
[11:07:33] [PASSED] Link rate 1000000 lane count 2
[11:07:33] [PASSED] Link rate 1000000 lane count 1
[11:07:33] [PASSED] Link rate 810000 lane count 4
[11:07:33] [PASSED] Link rate 810000 lane count 2
[11:07:33] [PASSED] Link rate 810000 lane count 1
[11:07:33] [PASSED] Link rate 540000 lane count 4
[11:07:33] [PASSED] Link rate 540000 lane count 2
[11:07:33] [PASSED] Link rate 540000 lane count 1
[11:07:33] [PASSED] Link rate 270000 lane count 4
[11:07:33] [PASSED] Link rate 270000 lane count 2
[11:07:33] [PASSED] Link rate 270000 lane count 1
[11:07:33] [PASSED] Link rate 162000 lane count 4
[11:07:33] [PASSED] Link rate 162000 lane count 2
[11:07:33] [PASSED] Link rate 162000 lane count 1
[11:07:33] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:07:33] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:07:33] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:07:33] [PASSED] DP_POWER_UP_PHY with port number
[11:07:33] [PASSED] DP_POWER_DOWN_PHY with port number
[11:07:33] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:07:33] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:07:33] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:07:33] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:07:33] [PASSED] DP_QUERY_PAYLOAD with port number
[11:07:33] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:07:33] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:07:33] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:07:33] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:07:33] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:07:33] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:07:33] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:07:33] [PASSED] DP_REMOTE_I2C_READ with port number
[11:07:33] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:07:33] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:07:33] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:07:33] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:07:33] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:07:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:07:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:07:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:07:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:07:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:07:33] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:07:33] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:07:33] ================ [PASSED] drm_dp_mst_helper ================
[11:07:33] ================== drm_exec (7 subtests) ===================
[11:07:33] [PASSED] sanitycheck
[11:07:33] [PASSED] test_lock
[11:07:33] [PASSED] test_lock_unlock
[11:07:33] [PASSED] test_duplicates
[11:07:33] [PASSED] test_prepare
[11:07:33] [PASSED] test_prepare_array
[11:07:33] [PASSED] test_multiple_loops
[11:07:33] ==================== [PASSED] drm_exec =====================
[11:07:33] =========== drm_format_helper_test (17 subtests) ===========
[11:07:33] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:07:33] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:07:33] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:07:33] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:07:33] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:07:33] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:07:33] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:07:33] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:07:33] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:07:33] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:07:33] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:07:33] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:07:33] ==================== drm_test_fb_swab  =====================
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ================ [PASSED] drm_test_fb_swab =================
[11:07:33] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:07:33] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:07:33] [PASSED] single_pixel_source_buffer
[11:07:33] [PASSED] single_pixel_clip_rectangle
[11:07:33] [PASSED] well_known_colors
[11:07:33] [PASSED] destination_pitch
[11:07:33] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:07:33] ================= drm_test_fb_clip_offset  =================
[11:07:33] [PASSED] pass through
[11:07:33] [PASSED] horizontal offset
[11:07:33] [PASSED] vertical offset
[11:07:33] [PASSED] horizontal and vertical offset
[11:07:33] [PASSED] horizontal offset (custom pitch)
[11:07:33] [PASSED] vertical offset (custom pitch)
[11:07:33] [PASSED] horizontal and vertical offset (custom pitch)
[11:07:33] ============= [PASSED] drm_test_fb_clip_offset =============
[11:07:33] =================== drm_test_fb_memcpy  ====================
[11:07:33] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:07:33] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:07:33] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:07:33] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:07:33] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:07:33] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:07:33] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:07:33] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:07:33] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:07:33] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:07:33] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:07:33] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:07:33] =============== [PASSED] drm_test_fb_memcpy ================
[11:07:33] ============= [PASSED] drm_format_helper_test ==============
[11:07:33] ================= drm_format (18 subtests) =================
[11:07:33] [PASSED] drm_test_format_block_width_invalid
[11:07:33] [PASSED] drm_test_format_block_width_one_plane
[11:07:33] [PASSED] drm_test_format_block_width_two_plane
[11:07:33] [PASSED] drm_test_format_block_width_three_plane
[11:07:33] [PASSED] drm_test_format_block_width_tiled
[11:07:33] [PASSED] drm_test_format_block_height_invalid
[11:07:33] [PASSED] drm_test_format_block_height_one_plane
[11:07:33] [PASSED] drm_test_format_block_height_two_plane
[11:07:33] [PASSED] drm_test_format_block_height_three_plane
[11:07:33] [PASSED] drm_test_format_block_height_tiled
[11:07:33] [PASSED] drm_test_format_min_pitch_invalid
[11:07:33] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:07:33] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:07:33] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:07:33] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:07:33] [PASSED] drm_test_format_min_pitch_two_plane
[11:07:33] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:07:33] [PASSED] drm_test_format_min_pitch_tiled
[11:07:33] =================== [PASSED] drm_format ====================
[11:07:33] ============== drm_framebuffer (10 subtests) ===============
[11:07:33] ========== drm_test_framebuffer_check_src_coords  ==========
[11:07:33] [PASSED] Success: source fits into fb
[11:07:33] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:07:33] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:07:33] [PASSED] Fail: overflowing fb with source width
[11:07:33] [PASSED] Fail: overflowing fb with source height
[11:07:33] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:07:33] [PASSED] drm_test_framebuffer_cleanup
[11:07:33] =============== drm_test_framebuffer_create  ===============
[11:07:33] [PASSED] ABGR8888 normal sizes
[11:07:33] [PASSED] ABGR8888 max sizes
[11:07:33] [PASSED] ABGR8888 pitch greater than min required
[11:07:33] [PASSED] ABGR8888 pitch less than min required
[11:07:33] [PASSED] ABGR8888 Invalid width
[11:07:33] [PASSED] ABGR8888 Invalid buffer handle
[11:07:33] [PASSED] No pixel format
[11:07:33] [PASSED] ABGR8888 Width 0
[11:07:33] [PASSED] ABGR8888 Height 0
[11:07:33] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:07:33] [PASSED] ABGR8888 Large buffer offset
[11:07:33] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:07:33] [PASSED] ABGR8888 Invalid flag
[11:07:33] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:07:33] [PASSED] ABGR8888 Valid buffer modifier
[11:07:33] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:07:33] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] NV12 Normal sizes
[11:07:33] [PASSED] NV12 Max sizes
[11:07:33] [PASSED] NV12 Invalid pitch
[11:07:33] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:07:33] [PASSED] NV12 different  modifier per-plane
[11:07:33] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:07:33] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] NV12 Modifier for inexistent plane
[11:07:33] [PASSED] NV12 Handle for inexistent plane
[11:07:33] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:07:33] [PASSED] YVU420 Normal sizes
[11:07:33] [PASSED] YVU420 Max sizes
[11:07:33] [PASSED] YVU420 Invalid pitch
[11:07:33] [PASSED] YVU420 Different pitches
[11:07:33] [PASSED] YVU420 Different buffer offsets/pitches
[11:07:33] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:07:33] [PASSED] YVU420 Valid modifier
[11:07:33] [PASSED] YVU420 Different modifiers per plane
[11:07:33] [PASSED] YVU420 Modifier for inexistent plane
[11:07:33] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:07:33] [PASSED] X0L2 Normal sizes
[11:07:33] [PASSED] X0L2 Max sizes
[11:07:33] [PASSED] X0L2 Invalid pitch
[11:07:33] [PASSED] X0L2 Pitch greater than minimum required
[11:07:33] [PASSED] X0L2 Handle for inexistent plane
[11:07:33] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:07:33] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:07:33] [PASSED] X0L2 Valid modifier
[11:07:33] [PASSED] X0L2 Modifier for inexistent plane
[11:07:33] =========== [PASSED] drm_test_framebuffer_create ===========
[11:07:33] [PASSED] drm_test_framebuffer_free
[11:07:33] [PASSED] drm_test_framebuffer_init
[11:07:33] [PASSED] drm_test_framebuffer_init_bad_format
[11:07:33] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:07:33] [PASSED] drm_test_framebuffer_lookup
[11:07:33] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:07:33] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:07:33] ================= [PASSED] drm_framebuffer =================
[11:07:33] ================ drm_gem_shmem (8 subtests) ================
[11:07:33] [PASSED] drm_gem_shmem_test_obj_create
[11:07:33] [PASSED] drm_gem_shmem_test_obj_create_private
[11:07:33] [PASSED] drm_gem_shmem_test_pin_pages
[11:07:33] [PASSED] drm_gem_shmem_test_vmap
[11:07:33] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:07:33] [PASSED] drm_gem_shmem_test_get_sg_table
[11:07:33] [PASSED] drm_gem_shmem_test_madvise
[11:07:33] [PASSED] drm_gem_shmem_test_purge
[11:07:33] ================== [PASSED] drm_gem_shmem ==================
[11:07:33] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:07:33] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:07:33] [PASSED] Automatic
[11:07:33] [PASSED] Full
[11:07:33] [PASSED] Limited 16:235
[11:07:33] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:07:33] [PASSED] drm_test_check_disable_connector
[11:07:33] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:07:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:07:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:07:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:07:33] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:07:33] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:07:33] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:07:33] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:07:33] [PASSED] drm_test_check_output_bpc_dvi
[11:07:33] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:07:33] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:07:33] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:07:33] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:07:33] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:07:33] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:07:33] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:07:33] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:07:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:07:33] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:07:33] [PASSED] drm_test_check_broadcast_rgb_value
[11:07:33] [PASSED] drm_test_check_bpc_8_value
[11:07:33] [PASSED] drm_test_check_bpc_10_value
[11:07:33] [PASSED] drm_test_check_bpc_12_value
[11:07:33] [PASSED] drm_test_check_format_value
[11:07:33] [PASSED] drm_test_check_tmds_char_value
[11:07:33] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:07:33] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:07:33] [PASSED] drm_test_check_mode_valid
[11:07:33] [PASSED] drm_test_check_mode_valid_reject
[11:07:33] [PASSED] drm_test_check_mode_valid_reject_rate
[11:07:33] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:07:33] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:07:33] ================= drm_managed (2 subtests) =================
[11:07:33] [PASSED] drm_test_managed_release_action
[11:07:33] [PASSED] drm_test_managed_run_action
[11:07:33] =================== [PASSED] drm_managed ===================
[11:07:33] =================== drm_mm (6 subtests) ====================
[11:07:33] [PASSED] drm_test_mm_init
[11:07:33] [PASSED] drm_test_mm_debug
[11:07:33] [PASSED] drm_test_mm_align32
[11:07:33] [PASSED] drm_test_mm_align64
[11:07:33] [PASSED] drm_test_mm_lowest
[11:07:33] [PASSED] drm_test_mm_highest
[11:07:33] ===================== [PASSED] drm_mm ======================
[11:07:33] ============= drm_modes_analog_tv (5 subtests) =============
[11:07:33] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:07:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:07:33] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:07:33] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:07:33] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:07:33] =============== [PASSED] drm_modes_analog_tv ===============
[11:07:33] ============== drm_plane_helper (2 subtests) ===============
[11:07:33] =============== drm_test_check_plane_state  ================
[11:07:33] [PASSED] clipping_simple
[11:07:33] [PASSED] clipping_rotate_reflect
[11:07:33] [PASSED] positioning_simple
[11:07:33] [PASSED] upscaling
[11:07:33] [PASSED] downscaling
[11:07:33] [PASSED] rounding1
[11:07:33] [PASSED] rounding2
[11:07:33] [PASSED] rounding3
[11:07:33] [PASSED] rounding4
[11:07:33] =========== [PASSED] drm_test_check_plane_state ============
[11:07:33] =========== drm_test_check_invalid_plane_state  ============
[11:07:33] [PASSED] positioning_invalid
[11:07:33] [PASSED] upscaling_invalid
[11:07:33] [PASSED] downscaling_invalid
[11:07:33] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:07:33] ================ [PASSED] drm_plane_helper =================
[11:07:33] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:07:33] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:07:33] [PASSED] None
[11:07:33] [PASSED] PAL
[11:07:33] [PASSED] NTSC
[11:07:33] [PASSED] Both, NTSC Default
[11:07:33] [PASSED] Both, PAL Default
[11:07:33] [PASSED] Both, NTSC Default, with PAL on command-line
[11:07:33] [PASSED] Both, PAL Default, with NTSC on command-line
[11:07:33] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:07:33] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:07:33] ================== drm_rect (9 subtests) ===================
[11:07:33] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:07:33] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:07:33] [PASSED] drm_test_rect_clip_scaled_clipped
[11:07:33] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:07:33] ================= drm_test_rect_intersect  =================
[11:07:33] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:07:33] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:07:33] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:07:33] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:07:33] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:07:33] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:07:33] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:07:33] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:07:33] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:07:33] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:07:33] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:07:33] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:07:33] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:07:33] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:07:33] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:07:33] ============= [PASSED] drm_test_rect_intersect =============
[11:07:33] ================ drm_test_rect_calc_hscale  ================
[11:07:33] [PASSED] normal use
[11:07:33] [PASSED] out of max range
[11:07:33] [PASSED] out of min range
[11:07:33] [PASSED] zero dst
[11:07:33] [PASSED] negative src
[11:07:33] [PASSED] negative dst
[11:07:33] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:07:33] ================ drm_test_rect_calc_vscale  ================
[11:07:33] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[11:07:33] [PASSED] out of max range
[11:07:33] [PASSED] out of min range
[11:07:33] [PASSED] zero dst
[11:07:33] [PASSED] negative src
[11:07:33] [PASSED] negative dst
[11:07:33] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:07:33] ================== drm_test_rect_rotate  ===================
[11:07:33] [PASSED] reflect-x
[11:07:33] [PASSED] reflect-y
[11:07:33] [PASSED] rotate-0
[11:07:33] [PASSED] rotate-90
[11:07:33] [PASSED] rotate-180
[11:07:33] [PASSED] rotate-270
[11:07:33] ============== [PASSED] drm_test_rect_rotate ===============
[11:07:33] ================ drm_test_rect_rotate_inv  =================
[11:07:33] [PASSED] reflect-x
[11:07:33] [PASSED] reflect-y
[11:07:33] [PASSED] rotate-0
[11:07:33] [PASSED] rotate-90
[11:07:33] [PASSED] rotate-180
[11:07:33] [PASSED] rotate-270
[11:07:33] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:07:33] ==================== [PASSED] drm_rect =====================
[11:07:33] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:07:33] ============ drm_test_sysfb_build_fourcc_list  =============
[11:07:33] [PASSED] no native formats
[11:07:33] [PASSED] XRGB8888 as native format
[11:07:33] [PASSED] remove duplicates
[11:07:33] [PASSED] convert alpha formats
[11:07:33] [PASSED] random formats
[11:07:33] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:07:33] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:07:33] ============================================================
[11:07:33] Testing complete. Ran 622 tests: passed: 622
[11:07:34] Elapsed time: 26.951s total, 1.719s configuring, 24.759s building, 0.437s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:07:34] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:07:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:07:45] Starting KUnit Kernel (1/1)...
[11:07:45] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:07:45] ================= ttm_device (5 subtests) ==================
[11:07:45] [PASSED] ttm_device_init_basic
[11:07:45] [PASSED] ttm_device_init_multiple
[11:07:45] [PASSED] ttm_device_fini_basic
[11:07:45] [PASSED] ttm_device_init_no_vma_man
[11:07:45] ================== ttm_device_init_pools  ==================
[11:07:45] [PASSED] No DMA allocations, no DMA32 required
[11:07:45] [PASSED] DMA allocations, DMA32 required
[11:07:45] [PASSED] No DMA allocations, DMA32 required
[11:07:45] [PASSED] DMA allocations, no DMA32 required
[11:07:45] ============== [PASSED] ttm_device_init_pools ==============
[11:07:45] =================== [PASSED] ttm_device ====================
[11:07:45] ================== ttm_pool (8 subtests) ===================
[11:07:45] ================== ttm_pool_alloc_basic  ===================
[11:07:45] [PASSED] One page
[11:07:45] [PASSED] More than one page
[11:07:45] [PASSED] Above the allocation limit
[11:07:45] [PASSED] One page, with coherent DMA mappings enabled
[11:07:45] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:07:45] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:07:45] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:07:45] [PASSED] One page
[11:07:45] [PASSED] More than one page
[11:07:45] [PASSED] Above the allocation limit
[11:07:45] [PASSED] One page, with coherent DMA mappings enabled
[11:07:45] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:07:45] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:07:45] [PASSED] ttm_pool_alloc_order_caching_match
[11:07:45] [PASSED] ttm_pool_alloc_caching_mismatch
[11:07:45] [PASSED] ttm_pool_alloc_order_mismatch
[11:07:45] [PASSED] ttm_pool_free_dma_alloc
[11:07:45] [PASSED] ttm_pool_free_no_dma_alloc
[11:07:45] [PASSED] ttm_pool_fini_basic
[11:07:45] ==================== [PASSED] ttm_pool =====================
[11:07:45] ================ ttm_resource (8 subtests) =================
[11:07:45] ================= ttm_resource_init_basic  =================
[11:07:45] [PASSED] Init resource in TTM_PL_SYSTEM
[11:07:45] [PASSED] Init resource in TTM_PL_VRAM
[11:07:45] [PASSED] Init resource in a private placement
[11:07:45] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:07:45] ============= [PASSED] ttm_resource_init_basic =============
[11:07:45] [PASSED] ttm_resource_init_pinned
[11:07:45] [PASSED] ttm_resource_fini_basic
[11:07:45] [PASSED] ttm_resource_manager_init_basic
[11:07:45] [PASSED] ttm_resource_manager_usage_basic
[11:07:45] [PASSED] ttm_resource_manager_set_used_basic
[11:07:45] [PASSED] ttm_sys_man_alloc_basic
[11:07:45] [PASSED] ttm_sys_man_free_basic
[11:07:45] ================== [PASSED] ttm_resource ===================
[11:07:45] =================== ttm_tt (15 subtests) ===================
[11:07:45] ==================== ttm_tt_init_basic  ====================
[11:07:45] [PASSED] Page-aligned size
[11:07:45] [PASSED] Extra pages requested
[11:07:45] ================ [PASSED] ttm_tt_init_basic ================
[11:07:45] [PASSED] ttm_tt_init_misaligned
[11:07:45] [PASSED] ttm_tt_fini_basic
[11:07:45] [PASSED] ttm_tt_fini_sg
[11:07:45] [PASSED] ttm_tt_fini_shmem
[11:07:45] [PASSED] ttm_tt_create_basic
[11:07:45] [PASSED] ttm_tt_create_invalid_bo_type
[11:07:45] [PASSED] ttm_tt_create_ttm_exists
[11:07:45] [PASSED] ttm_tt_create_failed
[11:07:45] [PASSED] ttm_tt_destroy_basic
[11:07:45] [PASSED] ttm_tt_populate_null_ttm
[11:07:45] [PASSED] ttm_tt_populate_populated_ttm
[11:07:45] [PASSED] ttm_tt_unpopulate_basic
[11:07:45] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:07:45] [PASSED] ttm_tt_swapin_basic
[11:07:45] ===================== [PASSED] ttm_tt ======================
[11:07:45] =================== ttm_bo (14 subtests) ===================
[11:07:45] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:07:45] [PASSED] Cannot be interrupted and sleeps
[11:07:45] [PASSED] Cannot be interrupted, locks straight away
[11:07:45] [PASSED] Can be interrupted, sleeps
[11:07:45] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:07:45] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:07:45] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:07:45] [PASSED] ttm_bo_reserve_double_resv
[11:07:45] [PASSED] ttm_bo_reserve_interrupted
[11:07:45] [PASSED] ttm_bo_reserve_deadlock
[11:07:45] [PASSED] ttm_bo_unreserve_basic
[11:07:45] [PASSED] ttm_bo_unreserve_pinned
[11:07:45] [PASSED] ttm_bo_unreserve_bulk
[11:07:45] [PASSED] ttm_bo_fini_basic
[11:07:45] [PASSED] ttm_bo_fini_shared_resv
[11:07:45] [PASSED] ttm_bo_pin_basic
[11:07:45] [PASSED] ttm_bo_pin_unpin_resource
[11:07:45] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:07:45] ===================== [PASSED] ttm_bo ======================
[11:07:45] ============== ttm_bo_validate (21 subtests) ===============
[11:07:45] ============== ttm_bo_init_reserved_sys_man  ===============
[11:07:45] [PASSED] Buffer object for userspace
[11:07:45] [PASSED] Kernel buffer object
[11:07:45] [PASSED] Shared buffer object
[11:07:45] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:07:45] ============== ttm_bo_init_reserved_mock_man  ==============
[11:07:45] [PASSED] Buffer object for userspace
[11:07:45] [PASSED] Kernel buffer object
[11:07:45] [PASSED] Shared buffer object
[11:07:45] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:07:45] [PASSED] ttm_bo_init_reserved_resv
[11:07:45] ================== ttm_bo_validate_basic  ==================
[11:07:45] [PASSED] Buffer object for userspace
[11:07:45] [PASSED] Kernel buffer object
[11:07:45] [PASSED] Shared buffer object
[11:07:45] ============== [PASSED] ttm_bo_validate_basic ==============
[11:07:45] [PASSED] ttm_bo_validate_invalid_placement
[11:07:45] ============= ttm_bo_validate_same_placement  ==============
[11:07:45] [PASSED] System manager
[11:07:45] [PASSED] VRAM manager
[11:07:45] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:07:45] [PASSED] ttm_bo_validate_failed_alloc
[11:07:45] [PASSED] ttm_bo_validate_pinned
[11:07:45] [PASSED] ttm_bo_validate_busy_placement
[11:07:45] ================ ttm_bo_validate_multihop  =================
[11:07:45] [PASSED] Buffer object for userspace
[11:07:45] [PASSED] Kernel buffer object
[11:07:45] [PASSED] Shared buffer object
[11:07:45] ============ [PASSED] ttm_bo_validate_multihop =============
[11:07:45] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:07:45] [PASSED] Buffer object in system domain, no page vector
[11:07:45] [PASSED] Buffer object in system domain with an existing page vector
[11:07:45] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:07:45] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:07:45] [PASSED] Buffer object for userspace
[11:07:45] [PASSED] Kernel buffer object
[11:07:45] [PASSED] Shared buffer object
[11:07:45] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:07:45] [PASSED] ttm_bo_validate_move_fence_signaled
[11:07:45] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:07:45] [PASSED] Waits for GPU
[11:07:45] [PASSED] Tries to lock straight away
[11:07:45] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:07:45] [PASSED] ttm_bo_validate_happy_evict
[11:07:45] [PASSED] ttm_bo_validate_all_pinned_evict
[11:07:45] [PASSED] ttm_bo_validate_allowed_only_evict
[11:07:45] [PASSED] ttm_bo_validate_deleted_evict
[11:07:45] [PASSED] ttm_bo_validate_busy_domain_evict
[11:07:45] [PASSED] ttm_bo_validate_evict_gutting
[11:07:45] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:07:45] ================= [PASSED] ttm_bo_validate =================
[11:07:45] ============================================================
[11:07:45] Testing complete. Ran 101 tests: passed: 101
[11:07:45] Elapsed time: 11.349s total, 1.724s configuring, 9.409s building, 0.186s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework
URL   : https://patchwork.freedesktop.org/series/157658/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
+ cd /kernel
+ git config --global --add safe.directory /kernel
make: Leaving directory '/root/linux/maintainer-tools'
+ /root/linux/maintainer-tools/dim sparse --fast b2e41c70a5eeddce427dc6df02508b6856eb4a11
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2085:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1935:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2406 bytes --]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework
URL   : https://patchwork.freedesktop.org/series/157658/
State : success

== Summary ==

CI Bug Log - changes from xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11_BAT -> xe-pw-157658v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-157658v1_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#1727] / [Intel XE#4760])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html

  * igt@xe_module_load@load:
    - bat-bmg-1:          [PASS][3] -> [ABORT][4] ([Intel XE#4760])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/bat-bmg-1/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/bat-bmg-1/igt@xe_module_load@load.html

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][5] -> [TIMEOUT][6] ([Intel XE#6506])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506


Build changes
-------------

  * IGT: IGT_8626 -> IGT_8628
  * Linux: xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11 -> xe-pw-157658v1

  IGT_8626: 8626
  IGT_8628: 8628
  xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11: b2e41c70a5eeddce427dc6df02508b6856eb4a11
  xe-pw-157658v1: 157658v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/index.html

[-- Attachment #2: Type: text/html, Size: 3113 bytes --]

✗ Xe.CI.Full: failure for drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 55361 bytes --]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework
URL   : https://patchwork.freedesktop.org/series/157658/
State : failure

== Summary ==

CI Bug Log - changes from xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11_FULL -> xe-pw-157658v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-157658v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-157658v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-157658v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_create@create-execqueues-noleak:
    - shard-adlp:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-2/igt@xe_create@create-execqueues-noleak.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-2/igt@xe_create@create-execqueues-noleak.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22]) -> ([DMESG-WARN][23], [DMESG-WARN][24], [DMESG-WARN][25], [DMESG-WARN][26], [DMESG-WARN][27], [DMESG-WARN][28], [DMESG-WARN][29], [DMESG-WARN][30], [DMESG-WARN][31], [DMESG-WARN][32], [DMESG-WARN][33], [DMESG-WARN][34], [DMESG-WARN][35], [DMESG-WARN][36], [DMESG-WARN][37], [DMESG-WARN][38], [DMESG-WARN][39], [DMESG-WARN][40], [DMESG-WARN][41], [DMESG-WARN][42], [DMESG-WARN][43], [DMESG-WARN][44])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-6/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-7/igt@xe_module_load@load.html
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-1/igt@xe_module_load@load.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-1/igt@xe_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-1/igt@xe_module_load@load.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-5/igt@xe_module_load@load.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-5/igt@xe_module_load@load.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-2/igt@xe_module_load@load.html
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-7/igt@xe_module_load@load.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-2/igt@xe_module_load@load.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-4/igt@xe_module_load@load.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-4/igt@xe_module_load@load.html
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-8/igt@xe_module_load@load.html
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-6/igt@xe_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-7/igt@xe_module_load@load.html
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-6/igt@xe_module_load@load.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-4/igt@xe_module_load@load.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-8/igt@xe_module_load@load.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-8/igt@xe_module_load@load.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-bmg-5/igt@xe_module_load@load.html
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-6/igt@xe_module_load@load.html
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-6/igt@xe_module_load@load.html
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-6/igt@xe_module_load@load.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-6/igt@xe_module_load@load.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-2/igt@xe_module_load@load.html
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-2/igt@xe_module_load@load.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-5/igt@xe_module_load@load.html
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-2/igt@xe_module_load@load.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-5/igt@xe_module_load@load.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-5/igt@xe_module_load@load.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-7/igt@xe_module_load@load.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-7/igt@xe_module_load@load.html
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-7/igt@xe_module_load@load.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-7/igt@xe_module_load@load.html
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-4/igt@xe_module_load@load.html
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-4/igt@xe_module_load@load.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-4/igt@xe_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-4/igt@xe_module_load@load.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-1/igt@xe_module_load@load.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-1/igt@xe_module_load@load.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-8/igt@xe_module_load@load.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-bmg-8/igt@xe_module_load@load.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-adlp:         [PASS][45] -> [INCOMPLETE][46]
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-6/igt@xe_pm@s4-vm-bind-unbind-all.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-2/igt@xe_pm@s4-vm-bind-unbind-all.html

  
Known issues
------------

  Here are the changes found in xe-pw-157658v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-d-hdmi-a-1-y:
    - shard-adlp:         NOTRUN -> [DMESG-WARN][47] ([Intel XE#4543]) +3 other tests dmesg-warn
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_async_flips@async-flip-with-page-flip-events-tiled-atomic@pipe-d-hdmi-a-1-y.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-adlp:         [PASS][48] -> [FAIL][49] ([Intel XE#3908]) +1 other test fail
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-8/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][50] ([Intel XE#316]) +3 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-434/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#1407]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][52] ([Intel XE#3658])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-adlp:         [PASS][53] -> [DMESG-FAIL][54] ([Intel XE#4543]) +4 other tests dmesg-fail
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-adlp:         [PASS][55] -> [FAIL][56] ([Intel XE#1874])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-adlp:         [PASS][57] -> [ABORT][58] ([Intel XE#3970])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][59] ([Intel XE#619])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#1124]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-433/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#1124]) +3 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
    - shard-adlp:         NOTRUN -> [SKIP][62] ([Intel XE#1124])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-9/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][63] ([Intel XE#2191]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-4-displays-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#1512])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-7/igt@kms_bw@linear-tiling-4-displays-2560x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#455] / [Intel XE#787]) +5 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][66] ([Intel XE#455] / [Intel XE#787]) +11 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-432/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-rc-ccs-cc@pipe-d-dp-4.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#2669] / [Intel XE#3433]) +3 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#787]) +41 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-464/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#2887]) +4 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][70] ([Intel XE#787]) +8 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][71] ([Intel XE#2907])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#2907])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#2669]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-5/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][74] -> [INCOMPLETE][75] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][76] -> [INCOMPLETE][77] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4345] / [Intel XE#4522])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4:
    - shard-dg2-set2:     [PASS][78] -> [INCOMPLETE][79] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4212] / [Intel XE#4522])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-limited-range:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#306])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_chamelium_color@ctm-limited-range.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#306]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-436/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][82] ([Intel XE#373]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-464/igt@kms_chamelium_edid@vga-edid-read.html
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#373]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-5/igt@kms_chamelium_edid@vga-edid-read.html
    - shard-adlp:         NOTRUN -> [SKIP][84] ([Intel XE#373])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][85] ([Intel XE#6507])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-466/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#307])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-lnl:          NOTRUN -> [SKIP][87] ([Intel XE#307])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-1/igt@kms_content_protection@dp-mst-lic-type-0.html
    - shard-adlp:         NOTRUN -> [SKIP][88] ([Intel XE#307])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#1424]) +2 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-5/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-adlp:         NOTRUN -> [SKIP][90] ([Intel XE#455]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-4/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#4354])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-432/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#2244]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-adlp:         NOTRUN -> [SKIP][93] ([Intel XE#310])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-3/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#1421]) +2 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-adlp:         [PASS][95] -> [DMESG-WARN][96] ([Intel XE#4543]) +9 other tests dmesg-warn
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-6/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#1397] / [Intel XE#1745])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1397])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#455]) +7 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#1401] / [Intel XE#1745])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#1401])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling:
    - shard-lnl:          NOTRUN -> [FAIL][102] ([Intel XE#4683]) +1 other test fail
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][103] ([Intel XE#651])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][104] ([Intel XE#651]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen:
    - shard-dg2-set2:     NOTRUN -> [SKIP][105] ([Intel XE#651]) +13 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][106] ([Intel XE#1151])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#656]) +13 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#6312])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-433/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-adlp:         NOTRUN -> [SKIP][109] ([Intel XE#653]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
    - shard-adlp:         NOTRUN -> [SKIP][110] ([Intel XE#656]) +4 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][111] ([Intel XE#653]) +13 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_hdr@static-swap:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#1503])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@kms_hdr@static-swap.html

  * igt@kms_plane_lowres@tiling-none@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#599]) +3 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-4/igt@kms_plane_lowres@tiling-none@pipe-b-edp-1.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-adlp:         NOTRUN -> [SKIP][114] ([Intel XE#4596])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-9/igt@kms_plane_multiple@2x-tiling-x.html
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#4596])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#2763]) +7 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-20x20:
    - shard-adlp:         [PASS][117] -> [DMESG-WARN][118] ([Intel XE#2953] / [Intel XE#4173]) +3 other tests dmesg-warn
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-1/igt@kms_plane_scaling@planes-upscale-20x20.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@kms_plane_scaling@planes-upscale-20x20.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][119] ([Intel XE#908]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-464/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-adlp:         NOTRUN -> [SKIP][120] ([Intel XE#1129])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-9/igt@kms_pm_dc@dc6-psr.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][121] ([Intel XE#1129])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-433/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][122] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-466/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@psr2-cursor-plane-update-sf:
    - shard-adlp:         NOTRUN -> [SKIP][125] ([Intel XE#1406] / [Intel XE#1489])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_psr2_sf@psr2-cursor-plane-update-sf.html

  * igt@kms_psr@fbc-pr-dpms:
    - shard-lnl:          NOTRUN -> [SKIP][126] ([Intel XE#1406]) +3 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-4/igt@kms_psr@fbc-pr-dpms.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-adlp:         NOTRUN -> [SKIP][127] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-dpms@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][128] ([Intel XE#1406] / [Intel XE#4609]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-7/igt@kms_psr@fbc-psr2-dpms@edp-1.html

  * igt@kms_psr@psr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][129] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +6 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-463/igt@kms_psr@psr-dpms.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][130] ([Intel XE#3414]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2-set2:     NOTRUN -> [SKIP][131] ([Intel XE#330])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-466/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][132] -> [FAIL][133] ([Intel XE#2142]) +1 other test fail
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-lnl-1/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_ccs@large-ctrl-surf-copy:
    - shard-adlp:         NOTRUN -> [SKIP][134] ([Intel XE#3576] / [Intel XE#5610])
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-3/igt@xe_ccs@large-ctrl-surf-copy.html

  * igt@xe_compute_preempt@compute-preempt-many-vram:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#5191])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@xe_compute_preempt@compute-preempt-many-vram.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#6360])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-434/igt@xe_compute_preempt@compute-threadgroup-preempt.html

  * igt@xe_copy_basic@mem-copy-linear-0x369:
    - shard-dg2-set2:     NOTRUN -> [SKIP][137] ([Intel XE#1123])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-436/igt@xe_copy_basic@mem-copy-linear-0x369.html

  * igt@xe_eu_stall@blocking-re-enable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][138] ([Intel XE#5626])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-464/igt@xe_eu_stall@blocking-re-enable.html

  * igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram:
    - shard-dg2-set2:     NOTRUN -> [SKIP][139] ([Intel XE#4837]) +5 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-463/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#4837]) +2 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html
    - shard-adlp:         NOTRUN -> [SKIP][141] ([Intel XE#4837] / [Intel XE#5565])
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-3/igt@xe_eudebug_online@writes-caching-sram-bb-vram-target-sram.html

  * igt@xe_evict@evict-beng-cm-threads-small-multi-vm:
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#688]) +4 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@xe_evict@evict-beng-cm-threads-small-multi-vm.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][143] ([Intel XE#261]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen:
    - shard-adlp:         NOTRUN -> [SKIP][144] ([Intel XE#688])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-adlp:         NOTRUN -> [SKIP][145] ([Intel XE#1392] / [Intel XE#5575]) +1 other test skip
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#1392]) +4 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@xe_exec_basic@multigpu-once-userptr.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race:
    - shard-dg2-set2:     NOTRUN -> [SKIP][147] ([Intel XE#288]) +11 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-466/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@twice-userptr-invalidate:
    - shard-adlp:         NOTRUN -> [SKIP][148] ([Intel XE#288] / [Intel XE#5561]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-4/igt@xe_exec_fault_mode@twice-userptr-invalidate.html

  * igt@xe_exec_system_allocator@fault-threads-same-page-benchmark:
    - shard-dg2-set2:     NOTRUN -> [SKIP][149] ([Intel XE#4915]) +166 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-463/igt@xe_exec_system_allocator@fault-threads-same-page-benchmark.html

  * igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#5007])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-1/igt@xe_exec_system_allocator@many-64k-mmap-new-huge-nomemset.html

  * igt@xe_exec_system_allocator@many-stride-free:
    - shard-adlp:         NOTRUN -> [SKIP][151] ([Intel XE#4915]) +40 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@xe_exec_system_allocator@many-stride-free.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-single-vma:
    - shard-lnl:          NOTRUN -> [SKIP][152] ([Intel XE#6196])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-single-vma.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-huge:
    - shard-lnl:          NOTRUN -> [SKIP][153] ([Intel XE#4943]) +9 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-1/igt@xe_exec_system_allocator@process-many-stride-mmap-huge.html

  * igt@xe_media_fill@media-fill:
    - shard-lnl:          NOTRUN -> [SKIP][154] ([Intel XE#560])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@xe_media_fill@media-fill.html

  * igt@xe_module_load@force-load:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#378])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@xe_module_load@force-load.html

  * igt@xe_oa@invalid-create-userspace-config:
    - shard-adlp:         NOTRUN -> [SKIP][156] ([Intel XE#3573])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@xe_oa@invalid-create-userspace-config.html

  * igt@xe_oa@syncs-userptr-wait-cfg:
    - shard-dg2-set2:     NOTRUN -> [SKIP][157] ([Intel XE#3573]) +4 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@xe_oa@syncs-userptr-wait-cfg.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-dg2-set2:     NOTRUN -> [SKIP][158] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-adlp:         NOTRUN -> [SKIP][159] ([Intel XE#2284] / [Intel XE#366])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-4/igt@xe_pm@s3-d3cold-basic-exec.html
    - shard-lnl:          NOTRUN -> [SKIP][160] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-7/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pm_residency@idle-residency:
    - shard-dg2-set2:     [PASS][161] -> [FAIL][162] ([Intel XE#6362]) +1 other test fail
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-434/igt@xe_pm_residency@idle-residency.html
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-464/igt@xe_pm_residency@idle-residency.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [PASS][163] -> [FAIL][164] ([Intel XE#6251]) +1 other test fail
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_video_decode0.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-lnl:          NOTRUN -> [SKIP][165] ([Intel XE#4650])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-4/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pmu@gt-c6-idle:
    - shard-dg2-set2:     [PASS][166] -> [FAIL][167] ([Intel XE#6366])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-434/igt@xe_pmu@gt-c6-idle.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-464/igt@xe_pmu@gt-c6-idle.html

  * igt@xe_pxp@pxp-termination-key-update-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][168] ([Intel XE#4733]) +2 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@xe_pxp@pxp-termination-key-update-post-rpm.html

  * igt@xe_query@multigpu-query-invalid-cs-cycles:
    - shard-dg2-set2:     NOTRUN -> [SKIP][169] ([Intel XE#944])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-436/igt@xe_query@multigpu-query-invalid-cs-cycles.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-lnl:          NOTRUN -> [SKIP][170] ([Intel XE#4273])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@xe_sriov_flr@flr-vfs-parallel.html

  * igt@xe_sriov_vram@vf-access-provisioned:
    - shard-lnl:          NOTRUN -> [SKIP][171] ([Intel XE#6376])
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-1/igt@xe_sriov_vram@vf-access-provisioned.html

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-adlp:         [FAIL][172] ([Intel XE#3908]) -> [PASS][173] +1 other test pass
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-adlp:         [DMESG-FAIL][174] ([Intel XE#4543]) -> [PASS][175] +10 other tests pass
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][176] ([Intel XE#3862]) -> [PASS][177] +1 other test pass
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-dp-4.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-adlp:         [FAIL][178] -> [PASS][179]
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-9/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_flip@flip-vs-panning-interruptible:
    - shard-adlp:         [DMESG-WARN][180] ([Intel XE#4543] / [Intel XE#5208]) -> [PASS][181] +1 other test pass
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-8/igt@kms_flip@flip-vs-panning-interruptible.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible.html

  * igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][182] ([Intel XE#4543]) -> [PASS][183] +13 other tests pass
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-8/igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_flip@flip-vs-panning-interruptible@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-adlp:         [DMESG-WARN][184] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][185] +1 other test pass
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-adlp:         [DMESG-FAIL][186] ([Intel XE#4543] / [Intel XE#4921]) -> [PASS][187] +3 other tests pass
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_pm_dc@dc5-dpms:
    - shard-lnl:          [FAIL][188] ([Intel XE#718]) -> [PASS][189] +1 other test pass
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-lnl-8/igt@kms_pm_dc@dc5-dpms.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-2/igt@kms_pm_dc@dc5-dpms.html

  * {igt@kms_sharpness_filter@invalid-plane-with-filter@pipe-a-edp-1-invalid-plane-with-filter}:
    - shard-lnl:          [DMESG-WARN][190] ([Intel XE#4537]) -> [PASS][191] +1 other test pass
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-lnl-3/igt@kms_sharpness_filter@invalid-plane-with-filter@pipe-a-edp-1-invalid-plane-with-filter.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-8/igt@kms_sharpness_filter@invalid-plane-with-filter@pipe-a-edp-1-invalid-plane-with-filter.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][192] ([Intel XE#4459]) -> [PASS][193] +1 other test pass
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_pm@d3hot-multiple-execs:
    - shard-adlp:         [TIMEOUT][194] -> [PASS][195]
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-6/igt@xe_pm@d3hot-multiple-execs.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@xe_pm@d3hot-multiple-execs.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0:
    - shard-lnl:          [FAIL][196] ([Intel XE#6251]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html

  
#### Warnings ####

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][198] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345]) -> [INCOMPLETE][199] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-dg2-435/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-adlp:         [DMESG-WARN][200] ([Intel XE#2953] / [Intel XE#4173]) -> [DMESG-WARN][201] ([Intel XE#4543]) +1 other test dmesg-warn
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@xe_exec_reset@cm-cat-error:
    - shard-adlp:         [DMESG-WARN][202] ([Intel XE#3868]) -> [DMESG-FAIL][203] ([Intel XE#3868])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11/shard-adlp-3/igt@xe_exec_reset@cm-cat-error.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/shard-adlp-6/igt@xe_exec_reset@cm-cat-error.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1151]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1151
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3433]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3433
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#3576]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3576
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4273]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4273
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4522]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4522
  [Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4683]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4683
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
  [Intel XE#5191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5191
  [Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#5610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5610
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6360
  [Intel XE#6362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6362
  [Intel XE#6366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6366
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * IGT: IGT_8626 -> IGT_8628
  * Linux: xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11 -> xe-pw-157658v1

  IGT_8626: 8626
  IGT_8628: 8628
  xe-4116-b2e41c70a5eeddce427dc6df02508b6856eb4a11: b2e41c70a5eeddce427dc6df02508b6856eb4a11
  xe-pw-157658v1: 157658v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v1/index.html

[-- Attachment #2: Type: text/html, Size: 64279 bytes --]

✗ CI.checkpatch: warning for drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)
URL   : https://patchwork.freedesktop.org/series/157658/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 4f6d565cd96e665e2cd44640ae6d2f694c62aa7c
Author: Mika Kahola <mika.kahola@intel.com>
Date:   Tue Nov 18 15:28:59 2025 +0200

    drm/i915/cx0: Enable dpll framework for MTL+
    
    MTL+ platforms are supported by dpll framework remove a separate
    check for hw comparison and rely solely on dpll framework
    hw comparison.
    
    Finally, all required hooks are now in place so initialize
    PLL manager for MTL+ platforms and remove the redirections
    to the legacy code paths from the following interfaces:
    
    * intel_encoder::clock_enable/disable()
    * intel_encoder::get_config()
    * intel_dpll_funcs::get_hw_state()
    * intel_ddi_update_active_dpll()
    * pipe_config_pll_mismatch()
    
    v2: Rebase on !HAS_LT_PHY check in intel_ddi_update_active_dpll()
    v3: Rebase on !display->dpll.mgr check in intel_ddi_update_active_dpll()
        Add check for NVL as the platform is not part of pll framework (Suraj)
    
    Signed-off-by: Mika Kahola <mika.kahola@intel.com>
+ /mt/dim checkpatch b603326a067916accf680fd623f4fc3c22bba487 drm-intel
5a9dd14375e7 drm/i915/cx0: Rename TBT functions to be ICL specific
555184ff150a drm/i915/cx0: Factor out C10 msgbus access start/end helpers
896112d3ec9e drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
6f4d4d4a80b6 drm/i915/cx0: Sanitize calculating C20 PLL state from tables
077c57b01a43 drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
207ded286196 drm/i915/cx0: Move definition of Cx0 PHY functions earlier
104662f03b13 drm/i915/cx0: Add macro to get DDI port width from a register value
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'width' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2352:
+#define  DDI_PORT_WIDTH_ENCODE(width)		((width) == 3 ? 4 : (width) - 1)

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regval' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2353:
+#define  DDI_PORT_WIDTH_DECODE(regval)		((regval) == 4 ? 3 : (regval) + 1)

-:28: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:2356:
+#define  DDI_PORT_WIDTH_GET(regval)		DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \

total: 0 errors, 1 warnings, 2 checks, 14 lines checked
b2955d3bb8a1 drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
4a9adca5a3c7 drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
2d54ea7c065a drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
a62ada4bef06 drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
8c859c877867 drm/i915/cx0: Determine Cx0 PLL port clock from PLL state
83e26c8668a9 drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
c23d6704aeb8 drm/i915/cx0: Print additional Cx0 PLL HW state
9baeeecd1053 drm/i915/cx0: Remove state verification
825a397f9614 drm/i915/cx0: Add PLL information for MTL+
ab8518b83871 drm/i915/cx0: Update C10/C20 state calculation
1dfc05ba365e drm/i915/cx0: Compute plls for MTL+ platform
aeaae2456b50 drm/i915/cx0: Add MTL+ .get_dplls hook
-:57: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#57: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:3515:
+static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc,

total: 0 errors, 0 warnings, 1 checks, 86 lines checked
1ef36b0cb3da drm/i915/cx0: Add MTL+ .put_dplls hook
9fdd2a369587 drm/i915/cx0: Add MTL+ .update_active_dpll hook
b462f6e69666 drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
fa40b1ad523b drm/i915/cx0: Add MTL+ .dump_hw_state hook
09c2cc4b5c98 drm/i915/cx0: Add .compare_hw_state hook
7c6607a5508a drm/i915/cx0: Add MTL+ .get_hw_state hook
15daadb1b1c9 drm/i915/cx0: Add MTL+ .get_freq hook
dbdbd2d0f30d drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
e6402537ce89 drm/i915/cx0: PLL verify debug state print
ce6965134f7f drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
2bf972e23d6d drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
-:67: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#67: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:4315:
+static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
+					     struct intel_crtc_state *crtc_state)

total: 0 errors, 0 warnings, 1 checks, 99 lines checked
35a49e981d36 drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
4f6d565cd96e drm/i915/cx0: Enable dpll framework for MTL+

✓ CI.KUnit: success for drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)
URL   : https://patchwork.freedesktop.org/series/157658/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:17:41] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:17:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:18:15] Starting KUnit Kernel (1/1)...
[17:18:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:18:16] ================== guc_buf (11 subtests) ===================
[17:18:16] [PASSED] test_smallest
[17:18:16] [PASSED] test_largest
[17:18:16] [PASSED] test_granular
[17:18:16] [PASSED] test_unique
[17:18:16] [PASSED] test_overlap
[17:18:16] [PASSED] test_reusable
[17:18:16] [PASSED] test_too_big
[17:18:16] [PASSED] test_flush
[17:18:16] [PASSED] test_lookup
[17:18:16] [PASSED] test_data
[17:18:16] [PASSED] test_class
[17:18:16] ===================== [PASSED] guc_buf =====================
[17:18:16] =================== guc_dbm (7 subtests) ===================
[17:18:16] [PASSED] test_empty
[17:18:16] [PASSED] test_default
[17:18:16] ======================== test_size  ========================
[17:18:16] [PASSED] 4
[17:18:16] [PASSED] 8
[17:18:16] [PASSED] 32
[17:18:16] [PASSED] 256
[17:18:16] ==================== [PASSED] test_size ====================
[17:18:16] ======================= test_reuse  ========================
[17:18:16] [PASSED] 4
[17:18:16] [PASSED] 8
[17:18:16] [PASSED] 32
[17:18:16] [PASSED] 256
[17:18:16] =================== [PASSED] test_reuse ====================
[17:18:16] =================== test_range_overlap  ====================
[17:18:16] [PASSED] 4
[17:18:16] [PASSED] 8
[17:18:16] [PASSED] 32
[17:18:16] [PASSED] 256
[17:18:16] =============== [PASSED] test_range_overlap ================
[17:18:16] =================== test_range_compact  ====================
[17:18:16] [PASSED] 4
[17:18:16] [PASSED] 8
[17:18:16] [PASSED] 32
[17:18:16] [PASSED] 256
[17:18:16] =============== [PASSED] test_range_compact ================
[17:18:16] ==================== test_range_spare  =====================
[17:18:16] [PASSED] 4
[17:18:16] [PASSED] 8
[17:18:16] [PASSED] 32
[17:18:16] [PASSED] 256
[17:18:16] ================ [PASSED] test_range_spare =================
[17:18:16] ===================== [PASSED] guc_dbm =====================
[17:18:16] =================== guc_idm (6 subtests) ===================
[17:18:16] [PASSED] bad_init
[17:18:16] [PASSED] no_init
[17:18:16] [PASSED] init_fini
[17:18:16] [PASSED] check_used
[17:18:16] [PASSED] check_quota
[17:18:16] [PASSED] check_all
[17:18:16] ===================== [PASSED] guc_idm =====================
[17:18:16] ================== no_relay (3 subtests) ===================
[17:18:16] [PASSED] xe_drops_guc2pf_if_not_ready
[17:18:16] [PASSED] xe_drops_guc2vf_if_not_ready
[17:18:16] [PASSED] xe_rejects_send_if_not_ready
[17:18:16] ==================== [PASSED] no_relay =====================
[17:18:16] ================== pf_relay (14 subtests) ==================
[17:18:16] [PASSED] pf_rejects_guc2pf_too_short
[17:18:16] [PASSED] pf_rejects_guc2pf_too_long
[17:18:16] [PASSED] pf_rejects_guc2pf_no_payload
[17:18:16] [PASSED] pf_fails_no_payload
[17:18:16] [PASSED] pf_fails_bad_origin
[17:18:16] [PASSED] pf_fails_bad_type
[17:18:16] [PASSED] pf_txn_reports_error
[17:18:16] [PASSED] pf_txn_sends_pf2guc
[17:18:16] [PASSED] pf_sends_pf2guc
[17:18:16] [SKIPPED] pf_loopback_nop
[17:18:16] [SKIPPED] pf_loopback_echo
[17:18:16] [SKIPPED] pf_loopback_fail
[17:18:16] [SKIPPED] pf_loopback_busy
[17:18:16] [SKIPPED] pf_loopback_retry
[17:18:16] ==================== [PASSED] pf_relay =====================
[17:18:16] ================== vf_relay (3 subtests) ===================
[17:18:16] [PASSED] vf_rejects_guc2vf_too_short
[17:18:16] [PASSED] vf_rejects_guc2vf_too_long
[17:18:16] [PASSED] vf_rejects_guc2vf_no_payload
[17:18:16] ==================== [PASSED] vf_relay =====================
[17:18:16] ================ pf_gt_config (6 subtests) =================
[17:18:16] [PASSED] fair_contexts_1vf
[17:18:16] [PASSED] fair_doorbells_1vf
[17:18:16] [PASSED] fair_ggtt_1vf
[17:18:16] ====================== fair_contexts  ======================
[17:18:16] [PASSED] 1 VF
[17:18:16] [PASSED] 2 VFs
[17:18:16] [PASSED] 3 VFs
[17:18:16] [PASSED] 4 VFs
[17:18:16] [PASSED] 5 VFs
[17:18:16] [PASSED] 6 VFs
[17:18:16] [PASSED] 7 VFs
[17:18:16] [PASSED] 8 VFs
[17:18:16] [PASSED] 9 VFs
[17:18:16] [PASSED] 10 VFs
[17:18:16] [PASSED] 11 VFs
[17:18:16] [PASSED] 12 VFs
[17:18:16] [PASSED] 13 VFs
[17:18:16] [PASSED] 14 VFs
[17:18:16] [PASSED] 15 VFs
[17:18:16] [PASSED] 16 VFs
[17:18:16] [PASSED] 17 VFs
[17:18:16] [PASSED] 18 VFs
[17:18:16] [PASSED] 19 VFs
[17:18:16] [PASSED] 20 VFs
[17:18:16] [PASSED] 21 VFs
[17:18:16] [PASSED] 22 VFs
[17:18:16] [PASSED] 23 VFs
[17:18:16] [PASSED] 24 VFs
[17:18:16] [PASSED] 25 VFs
[17:18:16] [PASSED] 26 VFs
[17:18:16] [PASSED] 27 VFs
[17:18:16] [PASSED] 28 VFs
[17:18:16] [PASSED] 29 VFs
[17:18:16] [PASSED] 30 VFs
[17:18:16] [PASSED] 31 VFs
[17:18:16] [PASSED] 32 VFs
[17:18:16] [PASSED] 33 VFs
[17:18:16] [PASSED] 34 VFs
[17:18:16] [PASSED] 35 VFs
[17:18:16] [PASSED] 36 VFs
[17:18:16] [PASSED] 37 VFs
[17:18:16] [PASSED] 38 VFs
[17:18:16] [PASSED] 39 VFs
[17:18:16] [PASSED] 40 VFs
[17:18:16] [PASSED] 41 VFs
[17:18:16] [PASSED] 42 VFs
[17:18:16] [PASSED] 43 VFs
[17:18:16] [PASSED] 44 VFs
[17:18:16] [PASSED] 45 VFs
[17:18:16] [PASSED] 46 VFs
[17:18:16] [PASSED] 47 VFs
[17:18:16] [PASSED] 48 VFs
[17:18:16] [PASSED] 49 VFs
[17:18:16] [PASSED] 50 VFs
[17:18:16] [PASSED] 51 VFs
[17:18:16] [PASSED] 52 VFs
[17:18:16] [PASSED] 53 VFs
[17:18:16] [PASSED] 54 VFs
[17:18:16] [PASSED] 55 VFs
[17:18:16] [PASSED] 56 VFs
[17:18:16] [PASSED] 57 VFs
[17:18:16] [PASSED] 58 VFs
[17:18:16] [PASSED] 59 VFs
[17:18:16] [PASSED] 60 VFs
[17:18:16] [PASSED] 61 VFs
[17:18:16] [PASSED] 62 VFs
[17:18:16] [PASSED] 63 VFs
[17:18:16] ================== [PASSED] fair_contexts ==================
[17:18:16] ===================== fair_doorbells  ======================
[17:18:16] [PASSED] 1 VF
[17:18:16] [PASSED] 2 VFs
[17:18:16] [PASSED] 3 VFs
[17:18:16] [PASSED] 4 VFs
[17:18:16] [PASSED] 5 VFs
[17:18:16] [PASSED] 6 VFs
[17:18:16] [PASSED] 7 VFs
[17:18:16] [PASSED] 8 VFs
[17:18:16] [PASSED] 9 VFs
[17:18:16] [PASSED] 10 VFs
[17:18:16] [PASSED] 11 VFs
[17:18:16] [PASSED] 12 VFs
[17:18:16] [PASSED] 13 VFs
[17:18:16] [PASSED] 14 VFs
[17:18:16] [PASSED] 15 VFs
[17:18:16] [PASSED] 16 VFs
[17:18:16] [PASSED] 17 VFs
[17:18:16] [PASSED] 18 VFs
[17:18:16] [PASSED] 19 VFs
[17:18:16] [PASSED] 20 VFs
[17:18:16] [PASSED] 21 VFs
[17:18:16] [PASSED] 22 VFs
[17:18:16] [PASSED] 23 VFs
[17:18:16] [PASSED] 24 VFs
[17:18:16] [PASSED] 25 VFs
[17:18:16] [PASSED] 26 VFs
[17:18:16] [PASSED] 27 VFs
[17:18:16] [PASSED] 28 VFs
[17:18:16] [PASSED] 29 VFs
[17:18:16] [PASSED] 30 VFs
[17:18:16] [PASSED] 31 VFs
[17:18:16] [PASSED] 32 VFs
[17:18:16] [PASSED] 33 VFs
[17:18:16] [PASSED] 34 VFs
[17:18:16] [PASSED] 35 VFs
[17:18:16] [PASSED] 36 VFs
[17:18:16] [PASSED] 37 VFs
[17:18:16] [PASSED] 38 VFs
[17:18:16] [PASSED] 39 VFs
[17:18:16] [PASSED] 40 VFs
[17:18:16] [PASSED] 41 VFs
[17:18:16] [PASSED] 42 VFs
[17:18:16] [PASSED] 43 VFs
[17:18:16] [PASSED] 44 VFs
[17:18:16] [PASSED] 45 VFs
[17:18:16] [PASSED] 46 VFs
[17:18:16] [PASSED] 47 VFs
[17:18:16] [PASSED] 48 VFs
[17:18:16] [PASSED] 49 VFs
[17:18:16] [PASSED] 50 VFs
[17:18:16] [PASSED] 51 VFs
[17:18:16] [PASSED] 52 VFs
[17:18:16] [PASSED] 53 VFs
[17:18:16] [PASSED] 54 VFs
[17:18:16] [PASSED] 55 VFs
[17:18:16] [PASSED] 56 VFs
[17:18:16] [PASSED] 57 VFs
[17:18:16] [PASSED] 58 VFs
[17:18:16] [PASSED] 59 VFs
[17:18:16] [PASSED] 60 VFs
[17:18:16] [PASSED] 61 VFs
[17:18:16] [PASSED] 62 VFs
[17:18:16] [PASSED] 63 VFs
[17:18:16] ================= [PASSED] fair_doorbells ==================
[17:18:16] ======================== fair_ggtt  ========================
[17:18:16] [PASSED] 1 VF
[17:18:16] [PASSED] 2 VFs
[17:18:16] [PASSED] 3 VFs
[17:18:16] [PASSED] 4 VFs
[17:18:16] [PASSED] 5 VFs
[17:18:16] [PASSED] 6 VFs
[17:18:16] [PASSED] 7 VFs
[17:18:16] [PASSED] 8 VFs
[17:18:16] [PASSED] 9 VFs
[17:18:16] [PASSED] 10 VFs
[17:18:16] [PASSED] 11 VFs
[17:18:16] [PASSED] 12 VFs
[17:18:16] [PASSED] 13 VFs
[17:18:16] [PASSED] 14 VFs
[17:18:16] [PASSED] 15 VFs
[17:18:16] [PASSED] 16 VFs
[17:18:16] [PASSED] 17 VFs
[17:18:16] [PASSED] 18 VFs
[17:18:16] [PASSED] 19 VFs
[17:18:16] [PASSED] 20 VFs
[17:18:16] [PASSED] 21 VFs
[17:18:16] [PASSED] 22 VFs
[17:18:16] [PASSED] 23 VFs
[17:18:16] [PASSED] 24 VFs
[17:18:16] [PASSED] 25 VFs
[17:18:16] [PASSED] 26 VFs
[17:18:16] [PASSED] 27 VFs
[17:18:16] [PASSED] 28 VFs
[17:18:16] [PASSED] 29 VFs
[17:18:16] [PASSED] 30 VFs
[17:18:16] [PASSED] 31 VFs
[17:18:16] [PASSED] 32 VFs
[17:18:16] [PASSED] 33 VFs
[17:18:16] [PASSED] 34 VFs
[17:18:16] [PASSED] 35 VFs
[17:18:16] [PASSED] 36 VFs
[17:18:16] [PASSED] 37 VFs
[17:18:16] [PASSED] 38 VFs
[17:18:16] [PASSED] 39 VFs
[17:18:16] [PASSED] 40 VFs
[17:18:16] [PASSED] 41 VFs
[17:18:16] [PASSED] 42 VFs
[17:18:16] [PASSED] 43 VFs
[17:18:16] [PASSED] 44 VFs
[17:18:16] [PASSED] 45 VFs
[17:18:16] [PASSED] 46 VFs
[17:18:16] [PASSED] 47 VFs
[17:18:16] [PASSED] 48 VFs
[17:18:16] [PASSED] 49 VFs
[17:18:16] [PASSED] 50 VFs
[17:18:16] [PASSED] 51 VFs
[17:18:16] [PASSED] 52 VFs
[17:18:16] [PASSED] 53 VFs
[17:18:16] [PASSED] 54 VFs
[17:18:16] [PASSED] 55 VFs
[17:18:16] [PASSED] 56 VFs
[17:18:16] [PASSED] 57 VFs
[17:18:16] [PASSED] 58 VFs
[17:18:16] [PASSED] 59 VFs
[17:18:16] [PASSED] 60 VFs
[17:18:16] [PASSED] 61 VFs
[17:18:16] [PASSED] 62 VFs
[17:18:16] [PASSED] 63 VFs
[17:18:16] ==================== [PASSED] fair_ggtt ====================
[17:18:16] ================== [PASSED] pf_gt_config ===================
[17:18:16] ===================== lmtt (1 subtest) =====================
[17:18:16] ======================== test_ops  =========================
[17:18:16] [PASSED] 2-level
[17:18:16] [PASSED] multi-level
[17:18:16] ==================== [PASSED] test_ops =====================
[17:18:16] ====================== [PASSED] lmtt =======================
[17:18:16] ================= pf_service (11 subtests) =================
[17:18:16] [PASSED] pf_negotiate_any
[17:18:16] [PASSED] pf_negotiate_base_match
[17:18:16] [PASSED] pf_negotiate_base_newer
[17:18:16] [PASSED] pf_negotiate_base_next
[17:18:16] [SKIPPED] pf_negotiate_base_older
[17:18:16] [PASSED] pf_negotiate_base_prev
[17:18:16] [PASSED] pf_negotiate_latest_match
[17:18:16] [PASSED] pf_negotiate_latest_newer
[17:18:16] [PASSED] pf_negotiate_latest_next
[17:18:16] [SKIPPED] pf_negotiate_latest_older
[17:18:16] [SKIPPED] pf_negotiate_latest_prev
[17:18:16] =================== [PASSED] pf_service ====================
[17:18:16] ================= xe_guc_g2g (2 subtests) ==================
[17:18:16] ============== xe_live_guc_g2g_kunit_default  ==============
[17:18:16] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:18:16] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:18:16] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:18:16] =================== [SKIPPED] xe_guc_g2g ===================
[17:18:16] =================== xe_mocs (2 subtests) ===================
[17:18:16] ================ xe_live_mocs_kernel_kunit  ================
[17:18:16] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:18:16] ================ xe_live_mocs_reset_kunit  =================
[17:18:16] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:18:16] ==================== [SKIPPED] xe_mocs =====================
[17:18:16] ================= xe_migrate (2 subtests) ==================
[17:18:16] ================= xe_migrate_sanity_kunit  =================
[17:18:16] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:18:16] ================== xe_validate_ccs_kunit  ==================
[17:18:16] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:18:16] =================== [SKIPPED] xe_migrate ===================
[17:18:16] ================== xe_dma_buf (1 subtest) ==================
[17:18:16] ==================== xe_dma_buf_kunit  =====================
[17:18:16] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:18:16] =================== [SKIPPED] xe_dma_buf ===================
[17:18:16] ================= xe_bo_shrink (1 subtest) =================
[17:18:16] =================== xe_bo_shrink_kunit  ====================
[17:18:16] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:18:16] ================== [SKIPPED] xe_bo_shrink ==================
[17:18:16] ==================== xe_bo (2 subtests) ====================
[17:18:16] ================== xe_ccs_migrate_kunit  ===================
[17:18:16] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:18:16] ==================== xe_bo_evict_kunit  ====================
[17:18:16] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:18:16] ===================== [SKIPPED] xe_bo ======================
[17:18:16] ==================== args (11 subtests) ====================
[17:18:16] [PASSED] count_args_test
[17:18:16] [PASSED] call_args_example
[17:18:16] [PASSED] call_args_test
[17:18:16] [PASSED] drop_first_arg_example
[17:18:16] [PASSED] drop_first_arg_test
[17:18:16] [PASSED] first_arg_example
[17:18:16] [PASSED] first_arg_test
[17:18:16] [PASSED] last_arg_example
[17:18:16] [PASSED] last_arg_test
[17:18:16] [PASSED] pick_arg_example
[17:18:16] [PASSED] sep_comma_example
[17:18:16] ====================== [PASSED] args =======================
[17:18:16] =================== xe_pci (3 subtests) ====================
[17:18:16] ==================== check_graphics_ip  ====================
[17:18:16] [PASSED] 12.00 Xe_LP
[17:18:16] [PASSED] 12.10 Xe_LP+
[17:18:16] [PASSED] 12.55 Xe_HPG
[17:18:16] [PASSED] 12.60 Xe_HPC
[17:18:16] [PASSED] 12.70 Xe_LPG
[17:18:16] [PASSED] 12.71 Xe_LPG
[17:18:16] [PASSED] 12.74 Xe_LPG+
[17:18:16] [PASSED] 20.01 Xe2_HPG
[17:18:16] [PASSED] 20.02 Xe2_HPG
[17:18:16] [PASSED] 20.04 Xe2_LPG
[17:18:16] [PASSED] 30.00 Xe3_LPG
[17:18:16] [PASSED] 30.01 Xe3_LPG
[17:18:16] [PASSED] 30.03 Xe3_LPG
[17:18:16] [PASSED] 30.04 Xe3_LPG
[17:18:16] [PASSED] 30.05 Xe3_LPG
[17:18:16] [PASSED] 35.11 Xe3p_XPC
[17:18:16] ================ [PASSED] check_graphics_ip ================
[17:18:16] ===================== check_media_ip  ======================
[17:18:16] [PASSED] 12.00 Xe_M
[17:18:16] [PASSED] 12.55 Xe_HPM
[17:18:16] [PASSED] 13.00 Xe_LPM+
[17:18:16] [PASSED] 13.01 Xe2_HPM
[17:18:16] [PASSED] 20.00 Xe2_LPM
[17:18:16] [PASSED] 30.00 Xe3_LPM
[17:18:16] [PASSED] 30.02 Xe3_LPM
[17:18:16] [PASSED] 35.00 Xe3p_LPM
[17:18:16] [PASSED] 35.03 Xe3p_HPM
[17:18:16] ================= [PASSED] check_media_ip ==================
[17:18:16] =================== check_platform_desc  ===================
[17:18:16] [PASSED] 0x9A60 (TIGERLAKE)
[17:18:16] [PASSED] 0x9A68 (TIGERLAKE)
[17:18:16] [PASSED] 0x9A70 (TIGERLAKE)
[17:18:16] [PASSED] 0x9A40 (TIGERLAKE)
[17:18:16] [PASSED] 0x9A49 (TIGERLAKE)
[17:18:16] [PASSED] 0x9A59 (TIGERLAKE)
[17:18:16] [PASSED] 0x9A78 (TIGERLAKE)
[17:18:16] [PASSED] 0x9AC0 (TIGERLAKE)
[17:18:16] [PASSED] 0x9AC9 (TIGERLAKE)
[17:18:16] [PASSED] 0x9AD9 (TIGERLAKE)
[17:18:16] [PASSED] 0x9AF8 (TIGERLAKE)
[17:18:16] [PASSED] 0x4C80 (ROCKETLAKE)
[17:18:16] [PASSED] 0x4C8A (ROCKETLAKE)
[17:18:16] [PASSED] 0x4C8B (ROCKETLAKE)
[17:18:16] [PASSED] 0x4C8C (ROCKETLAKE)
[17:18:16] [PASSED] 0x4C90 (ROCKETLAKE)
[17:18:16] [PASSED] 0x4C9A (ROCKETLAKE)
[17:18:16] [PASSED] 0x4680 (ALDERLAKE_S)
[17:18:16] [PASSED] 0x4682 (ALDERLAKE_S)
[17:18:16] [PASSED] 0x4688 (ALDERLAKE_S)
[17:18:16] [PASSED] 0x468A (ALDERLAKE_S)
[17:18:16] [PASSED] 0x468B (ALDERLAKE_S)
[17:18:16] [PASSED] 0x4690 (ALDERLAKE_S)
[17:18:16] [PASSED] 0x4692 (ALDERLAKE_S)
[17:18:16] [PASSED] 0x4693 (ALDERLAKE_S)
[17:18:16] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46AA (ALDERLAKE_P)
[17:18:16] [PASSED] 0x462A (ALDERLAKE_P)
[17:18:16] [PASSED] 0x4626 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x4628 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[17:18:16] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:18:16] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:18:16] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:18:16] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:18:16] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:18:16] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:18:16] [PASSED] 0xA721 (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA720 (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:18:16] [PASSED] 0xA780 (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA781 (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA782 (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA783 (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA788 (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA789 (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA78A (ALDERLAKE_S)
[17:18:16] [PASSED] 0xA78B (ALDERLAKE_S)
[17:18:16] [PASSED] 0x4905 (DG1)
[17:18:16] [PASSED] 0x4906 (DG1)
[17:18:16] [PASSED] 0x4907 (DG1)
[17:18:16] [PASSED] 0x4908 (DG1)
[17:18:16] [PASSED] 0x4909 (DG1)
[17:18:16] [PASSED] 0x56C0 (DG2)
[17:18:16] [PASSED] 0x56C2 (DG2)
[17:18:16] [PASSED] 0x56C1 (DG2)
[17:18:16] [PASSED] 0x7D51 (METEORLAKE)
[17:18:16] [PASSED] 0x7DD1 (METEORLAKE)
[17:18:16] [PASSED] 0x7D41 (METEORLAKE)
[17:18:16] [PASSED] 0x7D67 (METEORLAKE)
[17:18:16] [PASSED] 0xB640 (METEORLAKE)
[17:18:16] [PASSED] 0x56A0 (DG2)
[17:18:16] [PASSED] 0x56A1 (DG2)
[17:18:16] [PASSED] 0x56A2 (DG2)
[17:18:16] [PASSED] 0x56BE (DG2)
[17:18:16] [PASSED] 0x56BF (DG2)
[17:18:16] [PASSED] 0x5690 (DG2)
[17:18:16] [PASSED] 0x5691 (DG2)
[17:18:16] [PASSED] 0x5692 (DG2)
[17:18:16] [PASSED] 0x56A5 (DG2)
[17:18:16] [PASSED] 0x56A6 (DG2)
[17:18:16] [PASSED] 0x56B0 (DG2)
[17:18:16] [PASSED] 0x56B1 (DG2)
[17:18:16] [PASSED] 0x56BA (DG2)
[17:18:16] [PASSED] 0x56BB (DG2)
[17:18:16] [PASSED] 0x56BC (DG2)
[17:18:16] [PASSED] 0x56BD (DG2)
[17:18:16] [PASSED] 0x5693 (DG2)
[17:18:16] [PASSED] 0x5694 (DG2)
[17:18:16] [PASSED] 0x5695 (DG2)
[17:18:16] [PASSED] 0x56A3 (DG2)
[17:18:16] [PASSED] 0x56A4 (DG2)
[17:18:16] [PASSED] 0x56B2 (DG2)
[17:18:16] [PASSED] 0x56B3 (DG2)
[17:18:16] [PASSED] 0x5696 (DG2)
[17:18:16] [PASSED] 0x5697 (DG2)
[17:18:16] [PASSED] 0xB69 (PVC)
[17:18:16] [PASSED] 0xB6E (PVC)
[17:18:16] [PASSED] 0xBD4 (PVC)
[17:18:16] [PASSED] 0xBD5 (PVC)
[17:18:16] [PASSED] 0xBD6 (PVC)
[17:18:16] [PASSED] 0xBD7 (PVC)
[17:18:16] [PASSED] 0xBD8 (PVC)
[17:18:16] [PASSED] 0xBD9 (PVC)
[17:18:16] [PASSED] 0xBDA (PVC)
[17:18:16] [PASSED] 0xBDB (PVC)
[17:18:16] [PASSED] 0xBE0 (PVC)
[17:18:16] [PASSED] 0xBE1 (PVC)
[17:18:16] [PASSED] 0xBE5 (PVC)
[17:18:16] [PASSED] 0x7D40 (METEORLAKE)
[17:18:16] [PASSED] 0x7D45 (METEORLAKE)
[17:18:16] [PASSED] 0x7D55 (METEORLAKE)
[17:18:16] [PASSED] 0x7D60 (METEORLAKE)
[17:18:16] [PASSED] 0x7DD5 (METEORLAKE)
[17:18:16] [PASSED] 0x6420 (LUNARLAKE)
[17:18:16] [PASSED] 0x64A0 (LUNARLAKE)
[17:18:16] [PASSED] 0x64B0 (LUNARLAKE)
[17:18:16] [PASSED] 0xE202 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE209 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE20B (BATTLEMAGE)
[17:18:16] [PASSED] 0xE20C (BATTLEMAGE)
[17:18:16] [PASSED] 0xE20D (BATTLEMAGE)
[17:18:16] [PASSED] 0xE210 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE211 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE212 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE216 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE220 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE221 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE222 (BATTLEMAGE)
[17:18:16] [PASSED] 0xE223 (BATTLEMAGE)
[17:18:16] [PASSED] 0xB080 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB081 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB082 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB083 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB084 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB085 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB086 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB087 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB08F (PANTHERLAKE)
[17:18:16] [PASSED] 0xB090 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:18:16] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:18:16] [PASSED] 0xD740 (NOVALAKE_S)
[17:18:16] [PASSED] 0xD741 (NOVALAKE_S)
[17:18:16] [PASSED] 0xD742 (NOVALAKE_S)
[17:18:16] [PASSED] 0xD743 (NOVALAKE_S)
[17:18:16] [PASSED] 0xD744 (NOVALAKE_S)
[17:18:16] [PASSED] 0xD745 (NOVALAKE_S)
[17:18:16] [PASSED] 0x674C (CRESCENTISLAND)
[17:18:16] [PASSED] 0xFD80 (PANTHERLAKE)
[17:18:16] [PASSED] 0xFD81 (PANTHERLAKE)
[17:18:16] =============== [PASSED] check_platform_desc ===============
[17:18:16] ===================== [PASSED] xe_pci ======================
[17:18:16] =================== xe_rtp (2 subtests) ====================
[17:18:16] =============== xe_rtp_process_to_sr_tests  ================
[17:18:16] [PASSED] coalesce-same-reg
[17:18:16] [PASSED] no-match-no-add
[17:18:16] [PASSED] match-or
[17:18:16] [PASSED] match-or-xfail
[17:18:16] [PASSED] no-match-no-add-multiple-rules
[17:18:16] [PASSED] two-regs-two-entries
[17:18:16] [PASSED] clr-one-set-other
[17:18:16] [PASSED] set-field
[17:18:16] [PASSED] conflict-duplicate
[17:18:16] [PASSED] conflict-not-disjoint
[17:18:16] [PASSED] conflict-reg-type
[17:18:16] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:18:16] ================== xe_rtp_process_tests  ===================
[17:18:16] [PASSED] active1
[17:18:16] [PASSED] active2
[17:18:16] [PASSED] active-inactive
[17:18:16] [PASSED] inactive-active
[17:18:16] [PASSED] inactive-1st_or_active-inactive
[17:18:16] [PASSED] inactive-2nd_or_active-inactive
[17:18:16] [PASSED] inactive-last_or_active-inactive
[17:18:16] [PASSED] inactive-no_or_active-inactive
[17:18:16] ============== [PASSED] xe_rtp_process_tests ===============
[17:18:16] ===================== [PASSED] xe_rtp ======================
[17:18:16] ==================== xe_wa (1 subtest) =====================
[17:18:16] ======================== xe_wa_gt  =========================
[17:18:16] [PASSED] TIGERLAKE B0
[17:18:16] [PASSED] DG1 A0
[17:18:16] [PASSED] DG1 B0
[17:18:16] [PASSED] ALDERLAKE_S A0
[17:18:16] [PASSED] ALDERLAKE_S B0
[17:18:16] [PASSED] ALDERLAKE_S C0
[17:18:16] [PASSED] ALDERLAKE_S D0
[17:18:16] [PASSED] ALDERLAKE_P A0
[17:18:16] [PASSED] ALDERLAKE_P B0
[17:18:16] [PASSED] ALDERLAKE_P C0
[17:18:16] [PASSED] ALDERLAKE_S RPLS D0
[17:18:16] [PASSED] ALDERLAKE_P RPLU E0
[17:18:16] [PASSED] DG2 G10 C0
[17:18:16] [PASSED] DG2 G11 B1
[17:18:16] [PASSED] DG2 G12 A1
[17:18:16] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:18:16] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:18:16] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:18:16] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:18:16] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:18:16] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:18:16] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:18:16] ==================== [PASSED] xe_wa_gt =====================
[17:18:16] ====================== [PASSED] xe_wa ======================
[17:18:16] ============================================================
[17:18:16] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[17:18:16] Elapsed time: 35.090s total, 4.250s configuring, 30.323s building, 0.460s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:18:16] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:18:18] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:18:42] Starting KUnit Kernel (1/1)...
[17:18:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:18:43] ============ drm_test_pick_cmdline (2 subtests) ============
[17:18:43] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:18:43] =============== drm_test_pick_cmdline_named  ===============
[17:18:43] [PASSED] NTSC
[17:18:43] [PASSED] NTSC-J
[17:18:43] [PASSED] PAL
[17:18:43] [PASSED] PAL-M
[17:18:43] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:18:43] ============== [PASSED] drm_test_pick_cmdline ==============
[17:18:43] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:18:43] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:18:43] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:18:43] =========== drm_validate_clone_mode (2 subtests) ===========
[17:18:43] ============== drm_test_check_in_clone_mode  ===============
[17:18:43] [PASSED] in_clone_mode
[17:18:43] [PASSED] not_in_clone_mode
[17:18:43] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:18:43] =============== drm_test_check_valid_clones  ===============
[17:18:43] [PASSED] not_in_clone_mode
[17:18:43] [PASSED] valid_clone
[17:18:43] [PASSED] invalid_clone
[17:18:43] =========== [PASSED] drm_test_check_valid_clones ===========
[17:18:43] ============= [PASSED] drm_validate_clone_mode =============
[17:18:43] ============= drm_validate_modeset (1 subtest) =============
[17:18:43] [PASSED] drm_test_check_connector_changed_modeset
[17:18:43] ============== [PASSED] drm_validate_modeset ===============
[17:18:43] ====== drm_test_bridge_get_current_state (2 subtests) ======
[17:18:43] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:18:43] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[17:18:43] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:18:43] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:18:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:18:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:18:43] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[17:18:43] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:18:43] ============== drm_bridge_alloc (2 subtests) ===============
[17:18:43] [PASSED] drm_test_drm_bridge_alloc_basic
[17:18:43] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:18:43] ================ [PASSED] drm_bridge_alloc =================
[17:18:43] ================== drm_buddy (8 subtests) ==================
[17:18:43] [PASSED] drm_test_buddy_alloc_limit
[17:18:43] [PASSED] drm_test_buddy_alloc_optimistic
[17:18:43] [PASSED] drm_test_buddy_alloc_pessimistic
[17:18:43] [PASSED] drm_test_buddy_alloc_pathological
[17:18:43] [PASSED] drm_test_buddy_alloc_contiguous
[17:18:43] [PASSED] drm_test_buddy_alloc_clear
[17:18:43] [PASSED] drm_test_buddy_alloc_range_bias
[17:18:43] [PASSED] drm_test_buddy_fragmentation_performance
[17:18:43] ==================== [PASSED] drm_buddy ====================
[17:18:43] ============= drm_cmdline_parser (40 subtests) =============
[17:18:43] [PASSED] drm_test_cmdline_force_d_only
[17:18:43] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:18:43] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:18:43] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:18:43] [PASSED] drm_test_cmdline_force_e_only
[17:18:43] [PASSED] drm_test_cmdline_res
[17:18:43] [PASSED] drm_test_cmdline_res_vesa
[17:18:43] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:18:43] [PASSED] drm_test_cmdline_res_rblank
[17:18:43] [PASSED] drm_test_cmdline_res_bpp
[17:18:43] [PASSED] drm_test_cmdline_res_refresh
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:18:43] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:18:43] [PASSED] drm_test_cmdline_res_margins_force_on
[17:18:43] [PASSED] drm_test_cmdline_res_vesa_margins
[17:18:43] [PASSED] drm_test_cmdline_name
[17:18:43] [PASSED] drm_test_cmdline_name_bpp
[17:18:43] [PASSED] drm_test_cmdline_name_option
[17:18:43] [PASSED] drm_test_cmdline_name_bpp_option
[17:18:43] [PASSED] drm_test_cmdline_rotate_0
[17:18:43] [PASSED] drm_test_cmdline_rotate_90
[17:18:43] [PASSED] drm_test_cmdline_rotate_180
[17:18:43] [PASSED] drm_test_cmdline_rotate_270
[17:18:43] [PASSED] drm_test_cmdline_hmirror
[17:18:43] [PASSED] drm_test_cmdline_vmirror
[17:18:43] [PASSED] drm_test_cmdline_margin_options
[17:18:43] [PASSED] drm_test_cmdline_multiple_options
[17:18:43] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:18:43] [PASSED] drm_test_cmdline_extra_and_option
[17:18:43] [PASSED] drm_test_cmdline_freestanding_options
[17:18:43] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:18:43] [PASSED] drm_test_cmdline_panel_orientation
[17:18:43] ================ drm_test_cmdline_invalid  =================
[17:18:43] [PASSED] margin_only
[17:18:43] [PASSED] interlace_only
[17:18:43] [PASSED] res_missing_x
[17:18:43] [PASSED] res_missing_y
[17:18:43] [PASSED] res_bad_y
[17:18:43] [PASSED] res_missing_y_bpp
[17:18:43] [PASSED] res_bad_bpp
[17:18:43] [PASSED] res_bad_refresh
[17:18:43] [PASSED] res_bpp_refresh_force_on_off
[17:18:43] [PASSED] res_invalid_mode
[17:18:43] [PASSED] res_bpp_wrong_place_mode
[17:18:43] [PASSED] name_bpp_refresh
[17:18:43] [PASSED] name_refresh
[17:18:43] [PASSED] name_refresh_wrong_mode
[17:18:43] [PASSED] name_refresh_invalid_mode
[17:18:43] [PASSED] rotate_multiple
[17:18:43] [PASSED] rotate_invalid_val
[17:18:43] [PASSED] rotate_truncated
[17:18:43] [PASSED] invalid_option
[17:18:43] [PASSED] invalid_tv_option
[17:18:43] [PASSED] truncated_tv_option
[17:18:43] ============ [PASSED] drm_test_cmdline_invalid =============
[17:18:43] =============== drm_test_cmdline_tv_options  ===============
[17:18:43] [PASSED] NTSC
[17:18:43] [PASSED] NTSC_443
[17:18:43] [PASSED] NTSC_J
[17:18:43] [PASSED] PAL
[17:18:43] [PASSED] PAL_M
[17:18:43] [PASSED] PAL_N
[17:18:43] [PASSED] SECAM
[17:18:43] [PASSED] MONO_525
[17:18:43] [PASSED] MONO_625
[17:18:43] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:18:43] =============== [PASSED] drm_cmdline_parser ================
[17:18:43] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:18:43] [PASSED] drm_test_connector_hdmi_init_valid
[17:18:43] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:18:43] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:18:43] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:18:43] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:18:43] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:18:43] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:18:43] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:18:43] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:18:43] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:18:43] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:18:43] [PASSED] supported_formats=0x3 yuv420_allowed=1
[17:18:43] [PASSED] supported_formats=0x3 yuv420_allowed=0
[17:18:43] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:18:43] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:18:43] [PASSED] drm_test_connector_hdmi_init_null_product
[17:18:43] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:18:43] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:18:43] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:18:43] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:18:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:18:43] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:18:43] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:18:43] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:18:43] [PASSED] HDMI-A
[17:18:43] [PASSED] HDMI-B
[17:18:43] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:18:43] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:18:43] [PASSED] Unknown
[17:18:43] [PASSED] VGA
[17:18:43] [PASSED] DVI-I
[17:18:43] [PASSED] DVI-D
[17:18:43] [PASSED] DVI-A
[17:18:43] [PASSED] Composite
[17:18:43] [PASSED] SVIDEO
[17:18:43] [PASSED] LVDS
[17:18:43] [PASSED] Component
[17:18:43] [PASSED] DIN
[17:18:43] [PASSED] DP
[17:18:43] [PASSED] TV
[17:18:43] [PASSED] eDP
[17:18:43] [PASSED] Virtual
[17:18:43] [PASSED] DSI
[17:18:43] [PASSED] DPI
[17:18:43] [PASSED] Writeback
[17:18:43] [PASSED] SPI
[17:18:43] [PASSED] USB
[17:18:43] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:18:43] ============ [PASSED] drmm_connector_hdmi_init =============
[17:18:43] ============= drmm_connector_init (3 subtests) =============
[17:18:43] [PASSED] drm_test_drmm_connector_init
[17:18:43] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:18:43] ========= drm_test_drmm_connector_init_type_valid  =========
[17:18:43] [PASSED] Unknown
[17:18:43] [PASSED] VGA
[17:18:43] [PASSED] DVI-I
[17:18:43] [PASSED] DVI-D
[17:18:43] [PASSED] DVI-A
[17:18:43] [PASSED] Composite
[17:18:43] [PASSED] SVIDEO
[17:18:43] [PASSED] LVDS
[17:18:43] [PASSED] Component
[17:18:43] [PASSED] DIN
[17:18:43] [PASSED] DP
[17:18:43] [PASSED] HDMI-A
[17:18:43] [PASSED] HDMI-B
[17:18:43] [PASSED] TV
[17:18:43] [PASSED] eDP
[17:18:43] [PASSED] Virtual
[17:18:43] [PASSED] DSI
[17:18:43] [PASSED] DPI
[17:18:43] [PASSED] Writeback
[17:18:43] [PASSED] SPI
[17:18:43] [PASSED] USB
[17:18:43] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:18:43] =============== [PASSED] drmm_connector_init ===============
[17:18:43] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_init
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:18:43] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:18:43] [PASSED] Unknown
[17:18:43] [PASSED] VGA
[17:18:43] [PASSED] DVI-I
[17:18:43] [PASSED] DVI-D
[17:18:43] [PASSED] DVI-A
[17:18:43] [PASSED] Composite
[17:18:43] [PASSED] SVIDEO
[17:18:43] [PASSED] LVDS
[17:18:43] [PASSED] Component
[17:18:43] [PASSED] DIN
[17:18:43] [PASSED] DP
[17:18:43] [PASSED] HDMI-A
[17:18:43] [PASSED] HDMI-B
[17:18:43] [PASSED] TV
[17:18:43] [PASSED] eDP
[17:18:43] [PASSED] Virtual
[17:18:43] [PASSED] DSI
[17:18:43] [PASSED] DPI
[17:18:43] [PASSED] Writeback
[17:18:43] [PASSED] SPI
[17:18:43] [PASSED] USB
[17:18:43] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:18:43] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:18:43] [PASSED] Unknown
[17:18:43] [PASSED] VGA
[17:18:43] [PASSED] DVI-I
[17:18:43] [PASSED] DVI-D
[17:18:43] [PASSED] DVI-A
[17:18:43] [PASSED] Composite
[17:18:43] [PASSED] SVIDEO
[17:18:43] [PASSED] LVDS
[17:18:43] [PASSED] Component
[17:18:43] [PASSED] DIN
[17:18:43] [PASSED] DP
[17:18:43] [PASSED] HDMI-A
[17:18:43] [PASSED] HDMI-B
[17:18:43] [PASSED] TV
[17:18:43] [PASSED] eDP
[17:18:43] [PASSED] Virtual
[17:18:43] [PASSED] DSI
[17:18:43] [PASSED] DPI
[17:18:43] [PASSED] Writeback
[17:18:43] [PASSED] SPI
[17:18:43] [PASSED] USB
[17:18:43] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:18:43] =========== [PASSED] drm_connector_dynamic_init ============
[17:18:43] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:18:43] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:18:43] ======= drm_connector_dynamic_register (7 subtests) ========
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:18:43] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:18:43] ========= [PASSED] drm_connector_dynamic_register ==========
[17:18:43] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:18:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:18:43] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:18:43] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:18:43] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:18:43] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:18:43] [PASSED] NTSC
[17:18:43] [PASSED] NTSC-443
[17:18:43] [PASSED] NTSC-J
[17:18:43] [PASSED] PAL
[17:18:43] [PASSED] PAL-M
[17:18:43] [PASSED] PAL-N
[17:18:43] [PASSED] SECAM
[17:18:43] [PASSED] Mono
[17:18:43] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:18:43] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:18:43] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:18:43] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:18:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:18:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:18:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:18:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:18:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:18:43] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:18:43] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:18:43] [PASSED] VIC 96
[17:18:43] [PASSED] VIC 97
[17:18:43] [PASSED] VIC 101
[17:18:43] [PASSED] VIC 102
[17:18:43] [PASSED] VIC 106
[17:18:43] [PASSED] VIC 107
[17:18:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:18:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:18:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:18:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:18:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:18:43] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:18:43] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:18:43] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:18:43] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:18:43] [PASSED] Automatic
[17:18:43] [PASSED] Full
[17:18:43] [PASSED] Limited 16:235
[17:18:43] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:18:43] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:18:43] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:18:43] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:18:43] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:18:43] [PASSED] RGB
[17:18:43] [PASSED] YUV 4:2:0
[17:18:43] [PASSED] YUV 4:2:2
[17:18:43] [PASSED] YUV 4:4:4
[17:18:43] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:18:43] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:18:43] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:18:43] ============= drm_damage_helper (21 subtests) ==============
[17:18:43] [PASSED] drm_test_damage_iter_no_damage
[17:18:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:18:43] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:18:43] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:18:43] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:18:43] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:18:43] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:18:43] [PASSED] drm_test_damage_iter_simple_damage
[17:18:43] [PASSED] drm_test_damage_iter_single_damage
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:18:43] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:18:43] [PASSED] drm_test_damage_iter_damage
[17:18:43] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:18:43] [PASSED] drm_test_damage_iter_damage_one_outside
[17:18:43] [PASSED] drm_test_damage_iter_damage_src_moved
[17:18:43] [PASSED] drm_test_damage_iter_damage_not_visible
[17:18:43] ================ [PASSED] drm_damage_helper ================
[17:18:43] ============== drm_dp_mst_helper (3 subtests) ==============
[17:18:43] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:18:43] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:18:43] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:18:43] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:18:43] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:18:43] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:18:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:18:43] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:18:43] [PASSED] Link rate 2000000 lane count 4
[17:18:43] [PASSED] Link rate 2000000 lane count 2
[17:18:43] [PASSED] Link rate 2000000 lane count 1
[17:18:43] [PASSED] Link rate 1350000 lane count 4
[17:18:43] [PASSED] Link rate 1350000 lane count 2
[17:18:43] [PASSED] Link rate 1350000 lane count 1
[17:18:43] [PASSED] Link rate 1000000 lane count 4
[17:18:43] [PASSED] Link rate 1000000 lane count 2
[17:18:43] [PASSED] Link rate 1000000 lane count 1
[17:18:43] [PASSED] Link rate 810000 lane count 4
[17:18:43] [PASSED] Link rate 810000 lane count 2
[17:18:43] [PASSED] Link rate 810000 lane count 1
[17:18:43] [PASSED] Link rate 540000 lane count 4
[17:18:43] [PASSED] Link rate 540000 lane count 2
[17:18:43] [PASSED] Link rate 540000 lane count 1
[17:18:43] [PASSED] Link rate 270000 lane count 4
[17:18:43] [PASSED] Link rate 270000 lane count 2
[17:18:43] [PASSED] Link rate 270000 lane count 1
[17:18:43] [PASSED] Link rate 162000 lane count 4
[17:18:43] [PASSED] Link rate 162000 lane count 2
[17:18:43] [PASSED] Link rate 162000 lane count 1
[17:18:43] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:18:43] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:18:43] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:18:43] [PASSED] DP_POWER_UP_PHY with port number
[17:18:43] [PASSED] DP_POWER_DOWN_PHY with port number
[17:18:43] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:18:43] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:18:43] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:18:43] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:18:43] [PASSED] DP_QUERY_PAYLOAD with port number
[17:18:43] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:18:43] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:18:43] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:18:43] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:18:43] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:18:43] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:18:43] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:18:43] [PASSED] DP_REMOTE_I2C_READ with port number
[17:18:43] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:18:43] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:18:43] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:18:43] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:18:43] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:18:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:18:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:18:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:18:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:18:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:18:43] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:18:43] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:18:43] ================ [PASSED] drm_dp_mst_helper ================
[17:18:43] ================== drm_exec (7 subtests) ===================
[17:18:43] [PASSED] sanitycheck
[17:18:43] [PASSED] test_lock
[17:18:43] [PASSED] test_lock_unlock
[17:18:43] [PASSED] test_duplicates
[17:18:43] [PASSED] test_prepare
[17:18:43] [PASSED] test_prepare_array
[17:18:43] [PASSED] test_multiple_loops
[17:18:43] ==================== [PASSED] drm_exec =====================
[17:18:43] =========== drm_format_helper_test (17 subtests) ===========
[17:18:43] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:18:43] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:18:43] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:18:43] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:18:43] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:18:43] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:18:43] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:18:43] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:18:43] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:18:43] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:18:43] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:18:43] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:18:43] ==================== drm_test_fb_swab  =====================
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ================ [PASSED] drm_test_fb_swab =================
[17:18:43] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:18:43] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:18:43] [PASSED] single_pixel_source_buffer
[17:18:43] [PASSED] single_pixel_clip_rectangle
[17:18:43] [PASSED] well_known_colors
[17:18:43] [PASSED] destination_pitch
[17:18:43] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:18:43] ================= drm_test_fb_clip_offset  =================
[17:18:43] [PASSED] pass through
[17:18:43] [PASSED] horizontal offset
[17:18:43] [PASSED] vertical offset
[17:18:43] [PASSED] horizontal and vertical offset
[17:18:43] [PASSED] horizontal offset (custom pitch)
[17:18:43] [PASSED] vertical offset (custom pitch)
[17:18:43] [PASSED] horizontal and vertical offset (custom pitch)
[17:18:43] ============= [PASSED] drm_test_fb_clip_offset =============
[17:18:43] =================== drm_test_fb_memcpy  ====================
[17:18:43] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:18:43] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:18:43] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:18:43] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:18:43] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:18:43] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:18:43] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:18:43] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:18:43] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:18:43] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:18:43] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:18:43] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:18:43] =============== [PASSED] drm_test_fb_memcpy ================
[17:18:43] ============= [PASSED] drm_format_helper_test ==============
[17:18:43] ================= drm_format (18 subtests) =================
[17:18:43] [PASSED] drm_test_format_block_width_invalid
[17:18:43] [PASSED] drm_test_format_block_width_one_plane
[17:18:43] [PASSED] drm_test_format_block_width_two_plane
[17:18:43] [PASSED] drm_test_format_block_width_three_plane
[17:18:43] [PASSED] drm_test_format_block_width_tiled
[17:18:43] [PASSED] drm_test_format_block_height_invalid
[17:18:43] [PASSED] drm_test_format_block_height_one_plane
[17:18:43] [PASSED] drm_test_format_block_height_two_plane
[17:18:43] [PASSED] drm_test_format_block_height_three_plane
[17:18:43] [PASSED] drm_test_format_block_height_tiled
[17:18:43] [PASSED] drm_test_format_min_pitch_invalid
[17:18:43] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:18:43] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:18:43] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:18:43] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:18:43] [PASSED] drm_test_format_min_pitch_two_plane
[17:18:43] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:18:43] [PASSED] drm_test_format_min_pitch_tiled
[17:18:43] =================== [PASSED] drm_format ====================
[17:18:43] ============== drm_framebuffer (10 subtests) ===============
[17:18:43] ========== drm_test_framebuffer_check_src_coords  ==========
[17:18:43] [PASSED] Success: source fits into fb
[17:18:43] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:18:43] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:18:43] [PASSED] Fail: overflowing fb with source width
[17:18:43] [PASSED] Fail: overflowing fb with source height
[17:18:43] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:18:43] [PASSED] drm_test_framebuffer_cleanup
[17:18:43] =============== drm_test_framebuffer_create  ===============
[17:18:43] [PASSED] ABGR8888 normal sizes
[17:18:43] [PASSED] ABGR8888 max sizes
[17:18:43] [PASSED] ABGR8888 pitch greater than min required
[17:18:43] [PASSED] ABGR8888 pitch less than min required
[17:18:43] [PASSED] ABGR8888 Invalid width
[17:18:43] [PASSED] ABGR8888 Invalid buffer handle
[17:18:43] [PASSED] No pixel format
[17:18:43] [PASSED] ABGR8888 Width 0
[17:18:43] [PASSED] ABGR8888 Height 0
[17:18:43] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:18:43] [PASSED] ABGR8888 Large buffer offset
[17:18:43] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:18:43] [PASSED] ABGR8888 Invalid flag
[17:18:43] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:18:43] [PASSED] ABGR8888 Valid buffer modifier
[17:18:43] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:18:43] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] NV12 Normal sizes
[17:18:43] [PASSED] NV12 Max sizes
[17:18:43] [PASSED] NV12 Invalid pitch
[17:18:43] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:18:43] [PASSED] NV12 different  modifier per-plane
[17:18:43] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:18:43] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] NV12 Modifier for inexistent plane
[17:18:43] [PASSED] NV12 Handle for inexistent plane
[17:18:43] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:18:43] [PASSED] YVU420 Normal sizes
[17:18:43] [PASSED] YVU420 Max sizes
[17:18:43] [PASSED] YVU420 Invalid pitch
[17:18:43] [PASSED] YVU420 Different pitches
[17:18:43] [PASSED] YVU420 Different buffer offsets/pitches
[17:18:43] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:18:43] [PASSED] YVU420 Valid modifier
[17:18:43] [PASSED] YVU420 Different modifiers per plane
[17:18:43] [PASSED] YVU420 Modifier for inexistent plane
[17:18:43] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:18:43] [PASSED] X0L2 Normal sizes
[17:18:43] [PASSED] X0L2 Max sizes
[17:18:43] [PASSED] X0L2 Invalid pitch
[17:18:43] [PASSED] X0L2 Pitch greater than minimum required
[17:18:43] [PASSED] X0L2 Handle for inexistent plane
[17:18:43] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:18:43] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:18:43] [PASSED] X0L2 Valid modifier
[17:18:43] [PASSED] X0L2 Modifier for inexistent plane
[17:18:43] =========== [PASSED] drm_test_framebuffer_create ===========
[17:18:43] [PASSED] drm_test_framebuffer_free
[17:18:43] [PASSED] drm_test_framebuffer_init
[17:18:43] [PASSED] drm_test_framebuffer_init_bad_format
[17:18:43] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:18:43] [PASSED] drm_test_framebuffer_lookup
[17:18:43] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:18:43] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:18:43] ================= [PASSED] drm_framebuffer =================
[17:18:43] ================ drm_gem_shmem (8 subtests) ================
[17:18:43] [PASSED] drm_gem_shmem_test_obj_create
[17:18:43] [PASSED] drm_gem_shmem_test_obj_create_private
[17:18:43] [PASSED] drm_gem_shmem_test_pin_pages
[17:18:43] [PASSED] drm_gem_shmem_test_vmap
[17:18:43] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:18:43] [PASSED] drm_gem_shmem_test_get_sg_table
[17:18:43] [PASSED] drm_gem_shmem_test_madvise
[17:18:43] [PASSED] drm_gem_shmem_test_purge
[17:18:43] ================== [PASSED] drm_gem_shmem ==================
[17:18:43] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:18:43] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:18:43] [PASSED] Automatic
[17:18:43] [PASSED] Full
[17:18:43] [PASSED] Limited 16:235
[17:18:43] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:18:43] [PASSED] drm_test_check_disable_connector
[17:18:43] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:18:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:18:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:18:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:18:43] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:18:43] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:18:43] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:18:43] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:18:43] [PASSED] drm_test_check_output_bpc_dvi
[17:18:43] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:18:43] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:18:43] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:18:43] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:18:43] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:18:43] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:18:43] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:18:43] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:18:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:18:43] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:18:43] [PASSED] drm_test_check_broadcast_rgb_value
[17:18:43] [PASSED] drm_test_check_bpc_8_value
[17:18:43] [PASSED] drm_test_check_bpc_10_value
[17:18:43] [PASSED] drm_test_check_bpc_12_value
[17:18:43] [PASSED] drm_test_check_format_value
[17:18:43] [PASSED] drm_test_check_tmds_char_value
[17:18:43] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:18:43] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[17:18:43] [PASSED] drm_test_check_mode_valid
[17:18:43] [PASSED] drm_test_check_mode_valid_reject
[17:18:43] [PASSED] drm_test_check_mode_valid_reject_rate
[17:18:43] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:18:43] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:18:43] ================= drm_managed (2 subtests) =================
[17:18:43] [PASSED] drm_test_managed_release_action
[17:18:43] [PASSED] drm_test_managed_run_action
[17:18:43] =================== [PASSED] drm_managed ===================
[17:18:43] =================== drm_mm (6 subtests) ====================
[17:18:43] [PASSED] drm_test_mm_init
[17:18:43] [PASSED] drm_test_mm_debug
[17:18:43] [PASSED] drm_test_mm_align32
[17:18:43] [PASSED] drm_test_mm_align64
[17:18:43] [PASSED] drm_test_mm_lowest
[17:18:43] [PASSED] drm_test_mm_highest
[17:18:43] ===================== [PASSED] drm_mm ======================
[17:18:43] ============= drm_modes_analog_tv (5 subtests) =============
[17:18:43] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:18:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:18:43] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:18:43] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:18:43] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:18:43] =============== [PASSED] drm_modes_analog_tv ===============
[17:18:43] ============== drm_plane_helper (2 subtests) ===============
[17:18:43] =============== drm_test_check_plane_state  ================
[17:18:43] [PASSED] clipping_simple
[17:18:43] [PASSED] clipping_rotate_reflect
[17:18:43] [PASSED] positioning_simple
[17:18:43] [PASSED] upscaling
[17:18:43] [PASSED] downscaling
[17:18:43] [PASSED] rounding1
[17:18:43] [PASSED] rounding2
[17:18:43] [PASSED] rounding3
[17:18:43] [PASSED] rounding4
[17:18:43] =========== [PASSED] drm_test_check_plane_state ============
[17:18:43] =========== drm_test_check_invalid_plane_state  ============
[17:18:43] [PASSED] positioning_invalid
[17:18:43] [PASSED] upscaling_invalid
[17:18:43] [PASSED] downscaling_invalid
[17:18:43] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:18:43] ================ [PASSED] drm_plane_helper =================
[17:18:43] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:18:43] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:18:43] [PASSED] None
[17:18:43] [PASSED] PAL
[17:18:43] [PASSED] NTSC
[17:18:43] [PASSED] Both, NTSC Default
[17:18:43] [PASSED] Both, PAL Default
[17:18:43] [PASSED] Both, NTSC Default, with PAL on command-line
[17:18:43] [PASSED] Both, PAL Default, with NTSC on command-line
[17:18:43] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:18:43] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:18:43] ================== drm_rect (9 subtests) ===================
[17:18:43] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:18:43] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:18:43] [PASSED] drm_test_rect_clip_scaled_clipped
[17:18:43] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:18:43] ================= drm_test_rect_intersect  =================
[17:18:43] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:18:43] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:18:43] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:18:43] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:18:43] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:18:43] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:18:43] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:18:43] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:18:43] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:18:43] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:18:43] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:18:43] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:18:43] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:18:43] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:18:43] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:18:43] ============= [PASSED] drm_test_rect_intersect =============
[17:18:43] ================ drm_test_rect_calc_hscale  ================
[17:18:43] [PASSED] normal use
[17:18:43] [PASSED] out of max range
[17:18:43] [PASSED] out of min range
[17:18:43] [PASSED] zero dst
[17:18:43] [PASSED] negative src
[17:18:43] [PASSED] negative dst
[17:18:43] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:18:43] ================ drm_test_rect_calc_vscale  ================
[17:18:43] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[17:18:43] [PASSED] out of max range
[17:18:43] [PASSED] out of min range
[17:18:43] [PASSED] zero dst
[17:18:43] [PASSED] negative src
[17:18:43] [PASSED] negative dst
[17:18:43] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:18:43] ================== drm_test_rect_rotate  ===================
[17:18:43] [PASSED] reflect-x
[17:18:43] [PASSED] reflect-y
[17:18:43] [PASSED] rotate-0
[17:18:43] [PASSED] rotate-90
[17:18:43] [PASSED] rotate-180
[17:18:43] [PASSED] rotate-270
[17:18:43] ============== [PASSED] drm_test_rect_rotate ===============
[17:18:43] ================ drm_test_rect_rotate_inv  =================
[17:18:43] [PASSED] reflect-x
[17:18:43] [PASSED] reflect-y
[17:18:43] [PASSED] rotate-0
[17:18:43] [PASSED] rotate-90
[17:18:43] [PASSED] rotate-180
[17:18:43] [PASSED] rotate-270
[17:18:43] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:18:43] ==================== [PASSED] drm_rect =====================
[17:18:43] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:18:43] ============ drm_test_sysfb_build_fourcc_list  =============
[17:18:43] [PASSED] no native formats
[17:18:43] [PASSED] XRGB8888 as native format
[17:18:43] [PASSED] remove duplicates
[17:18:43] [PASSED] convert alpha formats
[17:18:43] [PASSED] random formats
[17:18:43] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:18:43] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:18:43] ============================================================
[17:18:43] Testing complete. Ran 622 tests: passed: 622
[17:18:43] Elapsed time: 26.883s total, 1.734s configuring, 24.732s building, 0.395s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:18:43] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:18:45] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:18:54] Starting KUnit Kernel (1/1)...
[17:18:54] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:18:54] ================= ttm_device (5 subtests) ==================
[17:18:54] [PASSED] ttm_device_init_basic
[17:18:54] [PASSED] ttm_device_init_multiple
[17:18:54] [PASSED] ttm_device_fini_basic
[17:18:54] [PASSED] ttm_device_init_no_vma_man
[17:18:54] ================== ttm_device_init_pools  ==================
[17:18:54] [PASSED] No DMA allocations, no DMA32 required
[17:18:54] [PASSED] DMA allocations, DMA32 required
[17:18:54] [PASSED] No DMA allocations, DMA32 required
[17:18:54] [PASSED] DMA allocations, no DMA32 required
[17:18:54] ============== [PASSED] ttm_device_init_pools ==============
[17:18:54] =================== [PASSED] ttm_device ====================
[17:18:54] ================== ttm_pool (8 subtests) ===================
[17:18:54] ================== ttm_pool_alloc_basic  ===================
[17:18:54] [PASSED] One page
[17:18:54] [PASSED] More than one page
[17:18:54] [PASSED] Above the allocation limit
[17:18:54] [PASSED] One page, with coherent DMA mappings enabled
[17:18:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:18:54] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:18:54] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:18:54] [PASSED] One page
[17:18:54] [PASSED] More than one page
[17:18:54] [PASSED] Above the allocation limit
[17:18:54] [PASSED] One page, with coherent DMA mappings enabled
[17:18:54] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:18:54] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:18:54] [PASSED] ttm_pool_alloc_order_caching_match
[17:18:54] [PASSED] ttm_pool_alloc_caching_mismatch
[17:18:54] [PASSED] ttm_pool_alloc_order_mismatch
[17:18:54] [PASSED] ttm_pool_free_dma_alloc
[17:18:54] [PASSED] ttm_pool_free_no_dma_alloc
[17:18:54] [PASSED] ttm_pool_fini_basic
[17:18:54] ==================== [PASSED] ttm_pool =====================
[17:18:54] ================ ttm_resource (8 subtests) =================
[17:18:54] ================= ttm_resource_init_basic  =================
[17:18:54] [PASSED] Init resource in TTM_PL_SYSTEM
[17:18:54] [PASSED] Init resource in TTM_PL_VRAM
[17:18:54] [PASSED] Init resource in a private placement
[17:18:54] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:18:54] ============= [PASSED] ttm_resource_init_basic =============
[17:18:54] [PASSED] ttm_resource_init_pinned
[17:18:54] [PASSED] ttm_resource_fini_basic
[17:18:54] [PASSED] ttm_resource_manager_init_basic
[17:18:54] [PASSED] ttm_resource_manager_usage_basic
[17:18:54] [PASSED] ttm_resource_manager_set_used_basic
[17:18:54] [PASSED] ttm_sys_man_alloc_basic
[17:18:54] [PASSED] ttm_sys_man_free_basic
[17:18:54] ================== [PASSED] ttm_resource ===================
[17:18:54] =================== ttm_tt (15 subtests) ===================
[17:18:54] ==================== ttm_tt_init_basic  ====================
[17:18:54] [PASSED] Page-aligned size
[17:18:54] [PASSED] Extra pages requested
[17:18:54] ================ [PASSED] ttm_tt_init_basic ================
[17:18:54] [PASSED] ttm_tt_init_misaligned
[17:18:54] [PASSED] ttm_tt_fini_basic
[17:18:54] [PASSED] ttm_tt_fini_sg
[17:18:54] [PASSED] ttm_tt_fini_shmem
[17:18:54] [PASSED] ttm_tt_create_basic
[17:18:54] [PASSED] ttm_tt_create_invalid_bo_type
[17:18:54] [PASSED] ttm_tt_create_ttm_exists
[17:18:54] [PASSED] ttm_tt_create_failed
[17:18:54] [PASSED] ttm_tt_destroy_basic
[17:18:54] [PASSED] ttm_tt_populate_null_ttm
[17:18:54] [PASSED] ttm_tt_populate_populated_ttm
[17:18:54] [PASSED] ttm_tt_unpopulate_basic
[17:18:54] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:18:54] [PASSED] ttm_tt_swapin_basic
[17:18:54] ===================== [PASSED] ttm_tt ======================
[17:18:54] =================== ttm_bo (14 subtests) ===================
[17:18:54] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:18:54] [PASSED] Cannot be interrupted and sleeps
[17:18:54] [PASSED] Cannot be interrupted, locks straight away
[17:18:54] [PASSED] Can be interrupted, sleeps
[17:18:54] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:18:54] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:18:54] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:18:54] [PASSED] ttm_bo_reserve_double_resv
[17:18:54] [PASSED] ttm_bo_reserve_interrupted
[17:18:54] [PASSED] ttm_bo_reserve_deadlock
[17:18:54] [PASSED] ttm_bo_unreserve_basic
[17:18:54] [PASSED] ttm_bo_unreserve_pinned
[17:18:54] [PASSED] ttm_bo_unreserve_bulk
[17:18:54] [PASSED] ttm_bo_fini_basic
[17:18:54] [PASSED] ttm_bo_fini_shared_resv
[17:18:54] [PASSED] ttm_bo_pin_basic
[17:18:54] [PASSED] ttm_bo_pin_unpin_resource
[17:18:54] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:18:54] ===================== [PASSED] ttm_bo ======================
[17:18:54] ============== ttm_bo_validate (21 subtests) ===============
[17:18:54] ============== ttm_bo_init_reserved_sys_man  ===============
[17:18:54] [PASSED] Buffer object for userspace
[17:18:54] [PASSED] Kernel buffer object
[17:18:54] [PASSED] Shared buffer object
[17:18:54] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:18:54] ============== ttm_bo_init_reserved_mock_man  ==============
[17:18:54] [PASSED] Buffer object for userspace
[17:18:54] [PASSED] Kernel buffer object
[17:18:54] [PASSED] Shared buffer object
[17:18:54] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:18:54] [PASSED] ttm_bo_init_reserved_resv
[17:18:54] ================== ttm_bo_validate_basic  ==================
[17:18:54] [PASSED] Buffer object for userspace
[17:18:54] [PASSED] Kernel buffer object
[17:18:54] [PASSED] Shared buffer object
[17:18:54] ============== [PASSED] ttm_bo_validate_basic ==============
[17:18:54] [PASSED] ttm_bo_validate_invalid_placement
[17:18:54] ============= ttm_bo_validate_same_placement  ==============
[17:18:54] [PASSED] System manager
[17:18:54] [PASSED] VRAM manager
[17:18:54] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:18:54] [PASSED] ttm_bo_validate_failed_alloc
[17:18:54] [PASSED] ttm_bo_validate_pinned
[17:18:54] [PASSED] ttm_bo_validate_busy_placement
[17:18:54] ================ ttm_bo_validate_multihop  =================
[17:18:54] [PASSED] Buffer object for userspace
[17:18:54] [PASSED] Kernel buffer object
[17:18:54] [PASSED] Shared buffer object
[17:18:54] ============ [PASSED] ttm_bo_validate_multihop =============
[17:18:54] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:18:54] [PASSED] Buffer object in system domain, no page vector
[17:18:54] [PASSED] Buffer object in system domain with an existing page vector
[17:18:54] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:18:54] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:18:54] [PASSED] Buffer object for userspace
[17:18:54] [PASSED] Kernel buffer object
[17:18:54] [PASSED] Shared buffer object
[17:18:54] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:18:54] [PASSED] ttm_bo_validate_move_fence_signaled
[17:18:54] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:18:54] [PASSED] Waits for GPU
[17:18:54] [PASSED] Tries to lock straight away
[17:18:54] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:18:54] [PASSED] ttm_bo_validate_happy_evict
[17:18:54] [PASSED] ttm_bo_validate_all_pinned_evict
[17:18:54] [PASSED] ttm_bo_validate_allowed_only_evict
[17:18:54] [PASSED] ttm_bo_validate_deleted_evict
[17:18:54] [PASSED] ttm_bo_validate_busy_domain_evict
[17:18:54] [PASSED] ttm_bo_validate_evict_gutting
[17:18:54] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:18:54] ================= [PASSED] ttm_bo_validate =================
[17:18:54] ============================================================
[17:18:54] Testing complete. Ran 101 tests: passed: 101
[17:18:54] Elapsed time: 11.256s total, 1.716s configuring, 9.324s building, 0.188s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)
URL   : https://patchwork.freedesktop.org/series/157658/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast b603326a067916accf680fd623f4fc3c22bba487
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2072:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2085:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1935:35: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2873 bytes --]

== Series Details ==

Series: drm/i915/cx0: Add MTL+ platforms to support dpll framework (rev3)
URL   : https://patchwork.freedesktop.org/series/157658/
State : success

== Summary ==

CI Bug Log - changes from xe-4124-b603326a067916accf680fd623f4fc3c22bba487_BAT -> xe-pw-157658v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-157658v3_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_force_connector_basic@force-connector-state:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#1727] / [Intel XE#4760])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4124-b603326a067916accf680fd623f4fc3c22bba487/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v3/bat-bmg-2/igt@kms_force_connector_basic@force-connector-state.html

  * igt@xe_module_load@load:
    - bat-bmg-1:          [PASS][3] -> [ABORT][4] ([Intel XE#4760])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4124-b603326a067916accf680fd623f4fc3c22bba487/bat-bmg-1/igt@xe_module_load@load.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v3/bat-bmg-1/igt@xe_module_load@load.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-plain-flip@b-edp1:
    - bat-adlp-7:         [DMESG-WARN][5] ([Intel XE#4543]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4124-b603326a067916accf680fd623f4fc3c22bba487/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v3/bat-adlp-7/igt@kms_flip@basic-plain-flip@b-edp1.html

  * igt@xe_waitfence@reltime:
    - bat-dg2-oem2:       [FAIL][7] ([Intel XE#6520]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4124-b603326a067916accf680fd623f4fc3c22bba487/bat-dg2-oem2/igt@xe_waitfence@reltime.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v3/bat-dg2-oem2/igt@xe_waitfence@reltime.html

  
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
  [Intel XE#6520]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6520


Build changes
-------------

  * Linux: xe-4124-b603326a067916accf680fd623f4fc3c22bba487 -> xe-pw-157658v3

  IGT_8631: 8631
  xe-4124-b603326a067916accf680fd623f4fc3c22bba487: b603326a067916accf680fd623f4fc3c22bba487
  xe-pw-157658v3: 157658v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157658v3/index.html

[-- Attachment #2: Type: text/html, Size: 3597 bytes --]

RE: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Kahola, Mika]

> -----Original Message-----
> From: Kahola, Mika <mika.kahola@intel.com>
> Sent: Monday, 17 November 2025 12.46
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework
> 
> This is v2 of [1], with the following changes
> 
> - commit message updates
> - Use of BUILD_BUGON() wherever possible instead of WARN_ON()
> 
> [1] https://lore.kernel.org/intel-gfx/20251031103549.173208-1-mika.kahola@intel.com/

This pll refactoring series is now merged. Thank you, Suraj, for taking time and effort to review this big series.

-Mika-

> 
> Imre Deak (15):
>   drm/i915/cx0: Factor out C10 msgbus access start/end helpers
>   drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
>   drm/i915/cx0: Sanitize calculating C20 PLL state from tables
>   drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
>   drm/i915/cx0: Move definition of Cx0 PHY functions earlier
>   drm/i915/cx0: Add macro to get DDI port width from a register value
>   drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
>   drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
>   drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
>   drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
>   drm/i915/cx0: Determine Cx0 PLL port clock from PLL state
>   drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
>   drm/i915/cx0: Print additional Cx0 PLL HW state
>   drm/i915/cx0: PLL verify debug state print
>   drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
> 
> Mika Kahola (17):
>   drm/i915/cx0: Rename TBT functions to be ICL specific
>   drm/i915/cx0: Remove state verification
>   drm/i915/cx0: Add PLL information for MTL+
>   drm/i915/cx0: Update C10/C20 state calculation
>   drm/i915/cx0: Compute plls for MTL+ platform
>   drm/i915/cx0: Add MTL+ .get_dplls hook
>   drm/i915/cx0: Add MTL+ .put_dplls hook
>   drm/i915/cx0: Add MTL+ .update_active_dpll hook
>   drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
>   drm/i915/cx0: Add MTL+ .dump_hw_state hook
>   drm/i915/cx0: Add .compare_hw_state hook
>   drm/i915/cx0: Add MTL+ .get_hw_state hook
>   drm/i915/cx0: Add MTL+ .get_freq hook
>   drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
>   drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
>   drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
>   drm/i915/cx0: Enable dpll framework for MTL+
> 
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 870 ++++++++++--------  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |
> 29 +-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  87 +-
>  drivers/gpu/drm/i915/display/intel_display.c  |  30 -
>  .../gpu/drm/i915/display/intel_display_regs.h |   7 +-
>  drivers/gpu/drm/i915/display/intel_dpll.c     |  24 +-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 315 ++++++-
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   7 +
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   4 +-
>  .../drm/i915/display/intel_modeset_verify.c   |   1 -
>  10 files changed, 893 insertions(+), 481 deletions(-)
> 
> --
> 2.34.1

Re: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Matt Roper]

On Wed, Nov 19, 2025 at 11:59:49AM +0000, Kahola, Mika wrote:
> > -----Original Message-----
> > From: Kahola, Mika <mika.kahola@intel.com>
> > Sent: Monday, 17 November 2025 12.46
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: Kahola, Mika <mika.kahola@intel.com>
> > Subject: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework
> > 
> > This is v2 of [1], with the following changes
> > 
> > - commit message updates
> > - Use of BUILD_BUGON() wherever possible instead of WARN_ON()
> > 
> > [1] https://lore.kernel.org/intel-gfx/20251031103549.173208-1-mika.kahola@intel.com/
> 
> This pll refactoring series is now merged. Thank you, Suraj, for taking time and effort to review this big series.

It looks like Xe.CI.Full reported some BMG driver load warnings that may
have been overlooked:

  https://lore.kernel.org/all/176338618409.2038.14088991238815121493@a3b018990fe9/

Now that this has been merged, those same driver load issues are
starting to show up on premerge CI for other series.  Can you take a
look?


Matt

> 
> -Mika-
> 
> > 
> > Imre Deak (15):
> >   drm/i915/cx0: Factor out C10 msgbus access start/end helpers
> >   drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
> >   drm/i915/cx0: Sanitize calculating C20 PLL state from tables
> >   drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
> >   drm/i915/cx0: Move definition of Cx0 PHY functions earlier
> >   drm/i915/cx0: Add macro to get DDI port width from a register value
> >   drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
> >   drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
> >   drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
> >   drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
> >   drm/i915/cx0: Determine Cx0 PLL port clock from PLL state
> >   drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
> >   drm/i915/cx0: Print additional Cx0 PLL HW state
> >   drm/i915/cx0: PLL verify debug state print
> >   drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
> > 
> > Mika Kahola (17):
> >   drm/i915/cx0: Rename TBT functions to be ICL specific
> >   drm/i915/cx0: Remove state verification
> >   drm/i915/cx0: Add PLL information for MTL+
> >   drm/i915/cx0: Update C10/C20 state calculation
> >   drm/i915/cx0: Compute plls for MTL+ platform
> >   drm/i915/cx0: Add MTL+ .get_dplls hook
> >   drm/i915/cx0: Add MTL+ .put_dplls hook
> >   drm/i915/cx0: Add MTL+ .update_active_dpll hook
> >   drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
> >   drm/i915/cx0: Add MTL+ .dump_hw_state hook
> >   drm/i915/cx0: Add .compare_hw_state hook
> >   drm/i915/cx0: Add MTL+ .get_hw_state hook
> >   drm/i915/cx0: Add MTL+ .get_freq hook
> >   drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
> >   drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
> >   drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
> >   drm/i915/cx0: Enable dpll framework for MTL+
> > 
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 870 ++++++++++--------  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |
> > 29 +-
> >  drivers/gpu/drm/i915/display/intel_ddi.c      |  87 +-
> >  drivers/gpu/drm/i915/display/intel_display.c  |  30 -
> >  .../gpu/drm/i915/display/intel_display_regs.h |   7 +-
> >  drivers/gpu/drm/i915/display/intel_dpll.c     |  24 +-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 315 ++++++-
> >  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   7 +
> >  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   4 +-
> >  .../drm/i915/display/intel_modeset_verify.c   |   1 -
> >  10 files changed, 893 insertions(+), 481 deletions(-)
> > 
> > --
> > 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

RE: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework

[Kahola, Mika]

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Wednesday, 19 November 2025 20.12
> To: Kahola, Mika <mika.kahola@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: Re: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to support dpll framework
> 
> On Wed, Nov 19, 2025 at 11:59:49AM +0000, Kahola, Mika wrote:
> > > -----Original Message-----
> > > From: Kahola, Mika <mika.kahola@intel.com>
> > > Sent: Monday, 17 November 2025 12.46
> > > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Cc: Kahola, Mika <mika.kahola@intel.com>
> > > Subject: [PATCH v2 00/32] drm/i915/cx0: Add MTL+ platforms to
> > > support dpll framework
> > >
> > > This is v2 of [1], with the following changes
> > >
> > > - commit message updates
> > > - Use of BUILD_BUGON() wherever possible instead of WARN_ON()
> > >
> > > [1]
> > > https://lore.kernel.org/intel-gfx/20251031103549.173208-1-mika.kahol
> > > a@intel.com/
> >
> > This pll refactoring series is now merged. Thank you, Suraj, for taking time and effort to review this big series.
> 
> It looks like Xe.CI.Full reported some BMG driver load warnings that may have been overlooked:
> 
>   https://lore.kernel.org/all/176338618409.2038.14088991238815121493@a3b018990fe9/
> 
> Now that this has been merged, those same driver load issues are starting to show up on premerge CI for other series.  Can
> you take a look?

We noticed that as well. It was my bad as even the CI looked green, I didn't check that actual results any further. Anyway,  Imre has already a fix for this

https://patchwork.freedesktop.org/series/157824/

-Mika-

> 
> 
> Matt
> 
> >
> > -Mika-
> >
> > >
> > > Imre Deak (15):
> > >   drm/i915/cx0: Factor out C10 msgbus access start/end helpers
> > >   drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
> > >   drm/i915/cx0: Sanitize calculating C20 PLL state from tables
> > >   drm/i915/cx0: Track the C20 PHY VDR state in the PLL state
> > >   drm/i915/cx0: Move definition of Cx0 PHY functions earlier
> > >   drm/i915/cx0: Add macro to get DDI port width from a register value
> > >   drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state
> > >   drm/i915/cx0: Sanitize C10 PHY PLL SSC register setup
> > >   drm/i915/cx0: Read out the Cx0 PHY SSC enabled state
> > >   drm/i915/cx0: Determine Cx0 PLL DP mode from PLL state
> > >   drm/i915/cx0: Determine Cx0 PLL port clock from PLL state
> > >   drm/i915/cx0: Zero Cx0 PLL state before compute and HW readout
> > >   drm/i915/cx0: Print additional Cx0 PLL HW state
> > >   drm/i915/cx0: PLL verify debug state print
> > >   drm/i915/cx0: Add MTL+ Thunderbolt PLL hooks
> > >
> > > Mika Kahola (17):
> > >   drm/i915/cx0: Rename TBT functions to be ICL specific
> > >   drm/i915/cx0: Remove state verification
> > >   drm/i915/cx0: Add PLL information for MTL+
> > >   drm/i915/cx0: Update C10/C20 state calculation
> > >   drm/i915/cx0: Compute plls for MTL+ platform
> > >   drm/i915/cx0: Add MTL+ .get_dplls hook
> > >   drm/i915/cx0: Add MTL+ .put_dplls hook
> > >   drm/i915/cx0: Add MTL+ .update_active_dpll hook
> > >   drm/i915/cx0: Add MTL+ .update_dpll_ref_clks hook
> > >   drm/i915/cx0: Add MTL+ .dump_hw_state hook
> > >   drm/i915/cx0: Add .compare_hw_state hook
> > >   drm/i915/cx0: Add MTL+ .get_hw_state hook
> > >   drm/i915/cx0: Add MTL+ .get_freq hook
> > >   drm/i915/cx0: Add MTL+ .crtc_get_dpll hook
> > >   drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDI
> > >   drm/i915/cx0: Get encoder configuration for C10 and C20 PHY PLLs
> > >   drm/i915/cx0: Enable dpll framework for MTL+
> > >
> > >  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 870
> > > ++++++++++--------  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |
> > > 29 +-
> > >  drivers/gpu/drm/i915/display/intel_ddi.c      |  87 +-
> > >  drivers/gpu/drm/i915/display/intel_display.c  |  30 -
> > >  .../gpu/drm/i915/display/intel_display_regs.h |   7 +-
> > >  drivers/gpu/drm/i915/display/intel_dpll.c     |  24 +-
> > >  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 315 ++++++-
> > >  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   7 +
> > >  drivers/gpu/drm/i915/display/intel_lt_phy.c   |   4 +-
> > >  .../drm/i915/display/intel_modeset_verify.c   |   1 -
> > >  10 files changed, 893 insertions(+), 481 deletions(-)
> > >
> > > --
> > > 2.34.1
> >
> 
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation