[PATCH v15 00/10] AuxCCS handling and render compression modifiers

[PATCH v15 00/10] AuxCCS handling and render compression modifiers

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

A series to add support for compressed surface scanout under xe with
Alderlake-P.

Currently the auxiliary buffer data isn't mapped into the page tables at all so
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
had to disable the support.

On top of that there are missing flushes, invalidations and similar.

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

  [PLANE:32:plane 1A]: type=PRI
          uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
          hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)

Display working fine - no artefacts, no DMAR/PIPE faults.

All IGTs pass for me locally.

v2:
 * More patches added to fix kms_flip_tiling.

v3:
 * Rebased after some cleanup patches from v2 were merged.
 * Added people to Cc as suggested by Rodrigo.
 * Adjusted last patch title. (Rodrigo)
 * Apply GGTT flushing only to iomapped system memory buffers.

v4:
 * Added patch for potentially misplaced Wa_14016712196.
 * Fixed (hopefully) MAX_JOB_SIZE_DW on Meteorlake.

v5:
 * Split out ring emission changes to smaller patches.
 * Fixed MAX_JOB_SIZE_DW even more.
 * Don't emit MI_FLUSH_DW_CCS on !BCS. This should fix Meteorlake.

 v6:
 * Added AuxCCS invalidation to indirect context workarounds.
 * Also added the indirect context handling and some other workarounds. They are
   unrelated but the series depends on it.
 * Dropped DPT pin alignment reduction since BMG appears not to be liking it for
   some reason.

v7:
 * Rebased on top of recent xe_fb_pin.c refactoring and also the indirect
   context workarounds series.

v8:
 * Rebased for bo->size removal.
 * Corrected PIPE_CONTROL_FLUSH_L3 to bit 30. (Jose)

v9:
 * Fixed fb remapping changes.
 * Dropped two not required patches from the series.
 * Fixed criteria for GGTT flushing.
 * Limit clflush to the compression metadata area.
 * Rebased for indirect context workarounds landing upstream.

v10:
 * Rebase for XE_GT_WA().

v11:
 * Do not use stolen for DPT on IGFX + AuxCCS.

v12:
 * Rebased for some ringbuf and LRC code changes.

v13:
 * Rebased for various upstream changes.
 * Dropped clflush and stolen avoidance patches after merging IGT MOCS 61 usage.

 v14:
 * MMIO 0x4248 and MI_FLUSH_DW_CCS are MTL+. (Matt)
 * Consolidate engine feature checks. (Ville)
 * Brought back the patch to put DPT tables in system memory for 100% CI pass
   rate. It looks like MOCS 61 is not enough to avoid sporadic pipecrc
   mismatches.

v15:
 * Limited to enabling on Alderlake-P only. (Dropped all Meteorlake patches.)
 * Dropped unrelated GGTT alignment fix. (Sent standalone.)
 * Use display parent interface for probing AuxCCS driver support.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Tvrtko Ursulin (10):
  drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
  drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
  drm/xe/xelp: Wait for AuxCCS invalidation to complete
  drm/xe: Export xe_emit_aux_table_inv
  drm/xe/xelp: Add AuxCCS invalidation to the indirect context
    workarounds
  drm/xe: Handle DPT in system memory
  drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS
  drm/xe/display: Add support for AuxCCS
  drm/i915/display: Detect AuxCCS support via display parent interface
  drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

 .../drm/i915/display/intel_display_device.h   |   1 -
 drivers/gpu/drm/i915/display/intel_fb.c       |   3 +-
 drivers/gpu/drm/i915/display/intel_parent.c   |   5 +
 drivers/gpu/drm/i915/display/intel_parent.h   |   2 +
 .../drm/i915/display/skl_universal_plane.c    |   9 +-
 drivers/gpu/drm/i915/i915_driver.c            |  10 ++
 drivers/gpu/drm/xe/display/xe_display.c       |   8 ++
 drivers/gpu/drm/xe/display/xe_fb_pin.c        | 131 +++++++++++++-----
 .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
 drivers/gpu/drm/xe/xe_hw_engine.h             |  24 ++++
 drivers/gpu/drm/xe/xe_lrc.c                   |  27 ++++
 drivers/gpu/drm/xe/xe_ring_ops.c              |  84 +++++++----
 drivers/gpu/drm/xe/xe_ring_ops.h              |   3 +
 drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
 include/drm/intel/display_parent_interface.h  |   3 +
 15 files changed, 247 insertions(+), 71 deletions(-)

-- 
2.52.0

[PATCH v15 01/10] drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

At the moment the driver does not support AuxCCS at all due respective
modifiers being hidden from userspace.

As we are about to start enabling them, starting with Alderlake, let us
begin by limiting the ring buffer support to just that initial platform.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_ring_ops.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index ac0c6dcffe15..5336ea626031 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -289,9 +289,9 @@ static bool has_aux_ccs(struct xe_device *xe)
 	 * PVC is a special case that has no compression of either type
 	 * (FlatCCS or AuxCCS).  Also, AuxCCS is no longer used from Xe2
 	 * onward, so any future platforms with no FlatCCS will not have
-	 * AuxCCS either.
+	 * AuxCCS, and we explicity do not want to support it on MTL.
 	 */
-	if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
+	if (GRAPHICS_VERx100(xe) >= 1270 || xe->info.platform == XE_PVC)
 		return false;
 
 	return !xe->info.has_flat_ccs;
-- 
2.52.0

[PATCH v15 02/10] drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

According to i915 commit
ad8ebf12217e ("drm/i915/gt: Ensure memory quiesced before invalidation")
quiescing of the memory traffic is required before invalidating the AuxCCS
tables.

Add an extra pipe control flush to achieve that.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_ring_ops.c       | 10 +++++++++-
 drivers/gpu/drm/xe/xe_ring_ops_types.h |  2 +-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 5336ea626031..bc806cabb5c3 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -358,12 +358,20 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	struct xe_gt *gt = job->q->gt;
 	struct xe_device *xe = gt_to_xe(gt);
 	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
+	const bool aux_ccs = has_aux_ccs(xe);
 	u32 mask_flags = 0;
 
 	*head = lrc->ring.tail;
 
 	i = emit_copy_timestamp(lrc, dw, i);
 
+	/*
+	 * On AuxCCS platforms the invalidation of the Aux table requires
+	 * quiescing the memory traffic beforehand.
+	 */
+	if (aux_ccs)
+		i = emit_render_cache_flush(job, dw, i);
+
 	dw[i++] = preparser_disable(true);
 	if (lacks_render)
 		mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS;
@@ -374,7 +382,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	i = emit_pipe_invalidate(mask_flags, job->ring_ops_flush_tlb, dw, i);
 
 	/* hsdes: 1809175790 */
-	if (has_aux_ccs(xe))
+	if (aux_ccs)
 		i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
 
 	dw[i++] = preparser_disable(false);
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index d7e3e150a9a5..477dc7defd72 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
 
 struct xe_sched_job;
 
-#define MAX_JOB_SIZE_DW 58
+#define MAX_JOB_SIZE_DW 70
 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
 
 /**
-- 
2.52.0

[PATCH v15 03/10] drm/xe/xelp: Wait for AuxCCS invalidation to complete

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

On AuxCCS platforms we need to wait for AuxCCS invalidations to complete.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 6 ++++++
 drivers/gpu/drm/xe/xe_ring_ops.c                 | 9 ++++++++-
 drivers/gpu/drm/xe/xe_ring_ops_types.h           | 2 +-
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
index c47b290e0e9f..49d8ffd026d5 100644
--- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
+++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
@@ -81,4 +81,10 @@
 #define MI_SET_APPID_SESSION_ID_MASK	REG_GENMASK(6, 0)
 #define MI_SET_APPID_SESSION_ID(x)	REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)
 
+#define MI_SEMAPHORE_WAIT_TOKEN		(__MI_INSTR(0x1c) | XE_INSTR_NUM_DW(5)) /* XeLP+ */
+#define   MI_SEMAPHORE_REGISTER_POLL	REG_BIT(16)
+#define   MI_SEMAPHORE_POLL		REG_BIT(15)
+#define   MI_SEMAPHORE_CMP_OP_MASK	REG_GENMASK(14, 12)
+#define   MI_SEMAPHORE_SAD_EQ_SDD	REG_FIELD_PREP(MI_SEMAPHORE_CMP_OP_MASK, 4)
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index bc806cabb5c3..a8d1854dd8e9 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -56,7 +56,14 @@ static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
 	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
 	dw[i++] = reg.addr + gt->mmio.adj_offset;
 	dw[i++] = AUX_INV;
-	dw[i++] = MI_NOOP;
+	dw[i++] = MI_SEMAPHORE_WAIT_TOKEN |
+		  MI_SEMAPHORE_REGISTER_POLL |
+		  MI_SEMAPHORE_POLL |
+		  MI_SEMAPHORE_SAD_EQ_SDD;
+	dw[i++] = 0;
+	dw[i++] = reg.addr + gt->mmio.adj_offset;
+	dw[i++] = 0;
+	dw[i++] = 0;
 
 	return i;
 }
diff --git a/drivers/gpu/drm/xe/xe_ring_ops_types.h b/drivers/gpu/drm/xe/xe_ring_ops_types.h
index 477dc7defd72..1197fc0bf2af 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops_types.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops_types.h
@@ -8,7 +8,7 @@
 
 struct xe_sched_job;
 
-#define MAX_JOB_SIZE_DW 70
+#define MAX_JOB_SIZE_DW 74
 #define MAX_JOB_SIZE_BYTES (MAX_JOB_SIZE_DW * 4)
 
 /**
-- 
2.52.0

[PATCH v15 04/10] drm/xe: Export xe_emit_aux_table_inv

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Export the existing AuxCCS invalidation ring buffer programming helper
which we will need to use to setup the indirect context workaround in the
next patch.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_ring_ops.c | 67 +++++++++++++++++++++-----------
 drivers/gpu/drm/xe/xe_ring_ops.h |  3 ++
 2 files changed, 48 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index a8d1854dd8e9..953723eaa237 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -14,6 +14,7 @@
 #include "regs/xe_lrc_layout.h"
 #include "xe_exec_queue_types.h"
 #include "xe_gt.h"
+#include "xe_gt_printk.h"
 #include "xe_lrc.h"
 #include "xe_macros.h"
 #include "xe_sched_job.h"
@@ -50,22 +51,49 @@ static u32 preparser_disable(bool state)
 	return MI_ARB_CHECK | BIT(8) | state;
 }
 
-static int emit_aux_table_inv(struct xe_gt *gt, struct xe_reg reg,
-			      u32 *dw, int i)
+u32 *xe_emit_aux_table_inv(struct xe_hw_engine *hwe, u32 *cmd)
 {
-	dw[i++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) | MI_LRI_MMIO_REMAP_EN;
-	dw[i++] = reg.addr + gt->mmio.adj_offset;
-	dw[i++] = AUX_INV;
-	dw[i++] = MI_SEMAPHORE_WAIT_TOKEN |
-		  MI_SEMAPHORE_REGISTER_POLL |
-		  MI_SEMAPHORE_POLL |
-		  MI_SEMAPHORE_SAD_EQ_SDD;
-	dw[i++] = 0;
-	dw[i++] = reg.addr + gt->mmio.adj_offset;
-	dw[i++] = 0;
-	dw[i++] = 0;
+	struct xe_gt *gt = hwe->gt;
+	struct xe_reg reg;
 
-	return i;
+	switch (hwe->class) {
+	case XE_ENGINE_CLASS_RENDER:
+	case XE_ENGINE_CLASS_COMPUTE:
+		reg = CCS_AUX_INV;
+		break;
+	case XE_ENGINE_CLASS_VIDEO_DECODE:
+		reg = VD0_AUX_INV;
+		break;
+	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
+		reg = VE0_AUX_INV;
+		break;
+	default:
+		xe_gt_err_once(gt, "AuxCCS invalidation not implemented!\n");
+		return cmd;
+	};
+
+	*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1) |
+		 MI_LRI_MMIO_REMAP_EN;
+	*cmd++ = reg.addr + gt->mmio.adj_offset;
+	*cmd++ = AUX_INV;
+	*cmd++ = MI_SEMAPHORE_WAIT_TOKEN | MI_SEMAPHORE_REGISTER_POLL |
+		 MI_SEMAPHORE_POLL | MI_SEMAPHORE_SAD_EQ_SDD;
+	*cmd++ = 0;
+	*cmd++ = reg.addr + gt->mmio.adj_offset;
+	*cmd++ = 0;
+	*cmd++ = 0;
+
+	return cmd;
+}
+
+static int emit_aux_table_inv(struct xe_hw_engine *hwe, u32 *dw, int i)
+{
+	u32 *start, *end;
+
+	start = dw + i;
+	end = xe_emit_aux_table_inv(hwe, start);
+
+	return i + (end - start);
 }
 
 static int emit_user_interrupt(u32 *dw, int i)
@@ -311,7 +339,6 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 	u32 ppgtt_flag = get_ppgtt_flag(job);
 	struct xe_gt *gt = job->q->gt;
 	struct xe_device *xe = gt_to_xe(gt);
-	bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE;
 
 	*head = lrc->ring.tail;
 
@@ -320,12 +347,8 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 	dw[i++] = preparser_disable(true);
 
 	/* hsdes: 1809175790 */
-	if (has_aux_ccs(xe)) {
-		if (decode)
-			i = emit_aux_table_inv(gt, VD0_AUX_INV, dw, i);
-		else
-			i = emit_aux_table_inv(gt, VE0_AUX_INV, dw, i);
-	}
+	if (has_aux_ccs(xe))
+		i = emit_aux_table_inv(job->q->hwe, dw, i);
 
 	if (job->ring_ops_flush_tlb)
 		i = emit_flush_imm_ggtt(xe_lrc_start_seqno_ggtt_addr(lrc),
@@ -390,7 +413,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 
 	/* hsdes: 1809175790 */
 	if (aux_ccs)
-		i = emit_aux_table_inv(gt, CCS_AUX_INV, dw, i);
+		i = emit_aux_table_inv(job->q->hwe, dw, i);
 
 	dw[i++] = preparser_disable(false);
 
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.h b/drivers/gpu/drm/xe/xe_ring_ops.h
index e942735d76a6..5a2d32f9bb25 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.h
+++ b/drivers/gpu/drm/xe/xe_ring_ops.h
@@ -10,8 +10,11 @@
 #include "xe_ring_ops_types.h"
 
 struct xe_gt;
+struct xe_hw_engine;
 
 const struct xe_ring_ops *
 xe_ring_ops_get(struct xe_gt *gt, enum xe_engine_class class);
 
+u32 *xe_emit_aux_table_inv(struct xe_hw_engine *hwe, u32 *cmd);
+
 #endif
-- 
2.52.0

[PATCH v15 05/10] drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Following from the i915 reference implementation, we add the AuxCCS
invalidation to the indirect context workarounds page.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/xe_hw_engine.h | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_lrc.c       | 27 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_ring_ops.c  | 18 ++----------------
 3 files changed, 53 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h
index 6b5f9fa2a594..725467b5877c 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine.h
@@ -6,6 +6,7 @@
 #ifndef _XE_HW_ENGINE_H_
 #define _XE_HW_ENGINE_H_
 
+#include "xe_device_types.h"
 #include "xe_hw_engine_types.h"
 
 struct drm_printer;
@@ -79,4 +80,27 @@ enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe);
 void xe_hw_engine_mmio_write32(struct xe_hw_engine *hwe, struct xe_reg reg, u32 val);
 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg);
 
+static inline bool
+xe_engine_class_has_auxccs(struct xe_device *xe, enum xe_engine_class class)
+{
+	/*
+	 * PVC is a special case that has no compression of either type
+	 * (FlatCCS or AuxCCS).  Also, AuxCCS is no longer used from Xe2
+	 * onward, so any future platforms with no FlatCCS will not have
+	 * AuxCCS, and we explicity do not want to support it on MTL.
+	 */
+	if (GRAPHICS_VERx100(xe) >= 1270 ||
+	    xe->info.platform == XE_PVC ||
+	    xe->info.has_flat_ccs)
+		return false;
+
+	if (class == XE_ENGINE_CLASS_RENDER ||
+	    class == XE_ENGINE_CLASS_COMPUTE ||
+	    class == XE_ENGINE_CLASS_VIDEO_DECODE ||
+	    class == XE_ENGINE_CLASS_VIDEO_ENHANCE)
+		return true;
+
+	return false;
+}
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index a05060f75e7e..27b3834208ab 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -23,10 +23,12 @@
 #include "xe_exec_queue_types.h"
 #include "xe_gt.h"
 #include "xe_gt_printk.h"
+#include "xe_hw_engine.h"
 #include "xe_hw_fence.h"
 #include "xe_map.h"
 #include "xe_memirq.h"
 #include "xe_mmio.h"
+#include "xe_ring_ops.h"
 #include "xe_sriov.h"
 #include "xe_trace_lrc.h"
 #include "xe_vm.h"
@@ -88,6 +90,10 @@ gt_engine_needs_indirect_ctx(struct xe_gt *gt, enum xe_engine_class class)
 					       class, NULL))
 		return true;
 
+	/* For AuxCCS invalidation */
+	if (xe_engine_class_has_auxccs(xe, class))
+		return true;
+
 	return false;
 }
 
@@ -1201,6 +1207,25 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
 	return cmd - batch;
 }
 
+static ssize_t setup_invalidate_auxccs_wa(struct xe_lrc *lrc,
+					  struct xe_hw_engine *hwe,
+					  u32 *batch, size_t max_len)
+{
+	struct xe_gt *gt = lrc->gt;
+	struct xe_device *xe = gt_to_xe(gt);
+	u32 *cmd;
+
+	if (!xe_engine_class_has_auxccs(xe, hwe->class))
+		return 0;
+
+	if (xe_gt_WARN_ON(gt, max_len < 8))
+		return -ENOSPC;
+
+	cmd = xe_emit_aux_table_inv(hwe, batch);
+
+	return cmd - batch;
+}
+
 struct bo_setup {
 	ssize_t (*setup)(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
 			 u32 *batch, size_t max_size);
@@ -1333,9 +1358,11 @@ setup_indirect_ctx(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
 {
 	static const struct bo_setup rcs_funcs[] = {
 		{ .setup = setup_timestamp_wa },
+		{ .setup = setup_invalidate_auxccs_wa },
 		{ .setup = setup_configfs_mid_ctx_restore_bb },
 	};
 	static const struct bo_setup xcs_funcs[] = {
+		{ .setup = setup_invalidate_auxccs_wa },
 		{ .setup = setup_configfs_mid_ctx_restore_bb },
 	};
 	struct bo_setup_state state = {
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 953723eaa237..004cc5c44128 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -318,20 +318,6 @@ static void __emit_job_gen12_simple(struct xe_sched_job *job, struct xe_lrc *lrc
 	xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));
 }
 
-static bool has_aux_ccs(struct xe_device *xe)
-{
-	/*
-	 * PVC is a special case that has no compression of either type
-	 * (FlatCCS or AuxCCS).  Also, AuxCCS is no longer used from Xe2
-	 * onward, so any future platforms with no FlatCCS will not have
-	 * AuxCCS, and we explicity do not want to support it on MTL.
-	 */
-	if (GRAPHICS_VERx100(xe) >= 1270 || xe->info.platform == XE_PVC)
-		return false;
-
-	return !xe->info.has_flat_ccs;
-}
-
 static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 				   u64 batch_addr, u32 *head, u32 seqno)
 {
@@ -347,7 +333,7 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc,
 	dw[i++] = preparser_disable(true);
 
 	/* hsdes: 1809175790 */
-	if (has_aux_ccs(xe))
+	if (xe_engine_class_has_auxccs(xe, job->q->class))
 		i = emit_aux_table_inv(job->q->hwe, dw, i);
 
 	if (job->ring_ops_flush_tlb)
@@ -388,7 +374,7 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 	struct xe_gt *gt = job->q->gt;
 	struct xe_device *xe = gt_to_xe(gt);
 	bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK);
-	const bool aux_ccs = has_aux_ccs(xe);
+	const bool aux_ccs = xe_engine_class_has_auxccs(xe, job->q->class);
 	u32 mask_flags = 0;
 
 	*head = lrc->ring.tail;
-- 
2.52.0

[PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

If DPT is allocated from system memory it will be created in the default
write-back cached mode. This means we need to flush it after populating
otherwise nothing works.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index a22a9182dadb..89ee68c40329 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -3,6 +3,7 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include <drm/drm_cache.h>
 #include <drm/ttm/ttm_bo.h>
 
 #include "i915_vma.h"
@@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
 					  rot_info->plane[i].dst_stride);
 	}
 
+	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
+		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
+
 	vma->dpt = dpt;
 	vma->node = dpt->ggtt_node[tile0->id];
 
-- 
2.52.0

Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Ville Syrjälä]

On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> 
> If DPT is allocated from system memory it will be created in the default
> write-back cached mode. This means we need to flush it after populating
> otherwise nothing works.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index a22a9182dadb..89ee68c40329 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -3,6 +3,7 @@
>   * Copyright © 2021 Intel Corporation
>   */
>  
> +#include <drm/drm_cache.h>
>  #include <drm/ttm/ttm_bo.h>
>  
>  #include "i915_vma.h"
> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>  					  rot_info->plane[i].dst_stride);
>  	}
>  
> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);

How is anything working currently if the DPT is being
created with the wrong caching mode?

Sounds like someone should fix the DPT creation to correctly
ask for UC/WC. But I suppose someone should measure if WB+flush
is actually faster...

> +
>  	vma->dpt = dpt;
>  	vma->node = dpt->ggtt_node[tile0->id];
>  
> -- 
> 2.52.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Tvrtko Ursulin]

On 09/12/2025 10:54, Ville Syrjälä wrote:
> On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>
>> If DPT is allocated from system memory it will be created in the default
>> write-back cached mode. This means we need to flush it after populating
>> otherwise nothing works.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>> index a22a9182dadb..89ee68c40329 100644
>> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>> @@ -3,6 +3,7 @@
>>    * Copyright © 2021 Intel Corporation
>>    */
>>   
>> +#include <drm/drm_cache.h>
>>   #include <drm/ttm/ttm_bo.h>
>>   
>>   #include "i915_vma.h"
>> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>>   					  rot_info->plane[i].dst_stride);
>>   	}
>>   
>> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
>> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
> How is anything working currently if the DPT is being
> created with the wrong caching mode?

I suspect the stolen allocation never fails in practice (or almost 
never, or at least not in CI).
> Sounds like someone should fix the DPT creation to correctly
> ask for UC/WC. But I suppose someone should measure if WB+flush
> is actually faster...

I am not sure what is desired here. System memory buffers defaulting to 
cached is the xe default, so should DPT be an exception I do not know.

In any case AuxCCS seems to only work with DPT in system memory and this 
clflush. DPT in stolen with GTT access and GTT flushing (as i915 does 
it) does not seem to work for xe. I guess the entity doing the DPT reads 
is somehow special coherency wise.

Regards,

Tvrtko

>> +
>>   	vma->dpt = dpt;
>>   	vma->node = dpt->ggtt_node[tile0->id];
>>   
>> -- 
>> 2.52.0

Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Ville Syrjälä]

On Tue, Dec 09, 2025 at 03:10:03PM +0100, Tvrtko Ursulin wrote:
> 
> On 09/12/2025 10:54, Ville Syrjälä wrote:
> > On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
> >> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>
> >> If DPT is allocated from system memory it will be created in the default
> >> write-back cached mode. This means we need to flush it after populating
> >> otherwise nothing works.
> >>
> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> ---
> >>   drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
> >>   1 file changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >> index a22a9182dadb..89ee68c40329 100644
> >> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >> @@ -3,6 +3,7 @@
> >>    * Copyright © 2021 Intel Corporation
> >>    */
> >>   
> >> +#include <drm/drm_cache.h>
> >>   #include <drm/ttm/ttm_bo.h>
> >>   
> >>   #include "i915_vma.h"
> >> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
> >>   					  rot_info->plane[i].dst_stride);
> >>   	}
> >>   
> >> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
> >> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
> > How is anything working currently if the DPT is being
> > created with the wrong caching mode?
> 
> I suspect the stolen allocation never fails in practice (or almost 
> never, or at least not in CI).
> > Sounds like someone should fix the DPT creation to correctly
> > ask for UC/WC. But I suppose someone should measure if WB+flush
> > is actually faster...
> 
> I am not sure what is desired here. System memory buffers defaulting to 
> cached is the xe default, so should DPT be an exception I do not know.

Anything meant for the display engine is supposed to be uncached.

> 
> In any case AuxCCS seems to only work with DPT in system memory and this 
> clflush. DPT in stolen with GTT access and GTT flushing (as i915 does 
> it) does not seem to work for xe. I guess the entity doing the DPT reads 
> is somehow special coherency wise.

Sounds like there is still something broken in xe.

-- 
Ville Syrjälä
Intel

Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Tvrtko Ursulin]

On 09/12/2025 15:25, Ville Syrjälä wrote:
> On Tue, Dec 09, 2025 at 03:10:03PM +0100, Tvrtko Ursulin wrote:
>> On 09/12/2025 10:54, Ville Syrjälä wrote:
>>> On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>>>
>>>> If DPT is allocated from system memory it will be created in the default
>>>> write-back cached mode. This means we need to flush it after populating
>>>> otherwise nothing works.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
>>>>    1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>> index a22a9182dadb..89ee68c40329 100644
>>>> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>> @@ -3,6 +3,7 @@
>>>>     * Copyright © 2021 Intel Corporation
>>>>     */
>>>>    
>>>> +#include <drm/drm_cache.h>
>>>>    #include <drm/ttm/ttm_bo.h>
>>>>    
>>>>    #include "i915_vma.h"
>>>> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>>>>    					  rot_info->plane[i].dst_stride);
>>>>    	}
>>>>    
>>>> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
>>>> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
>>> How is anything working currently if the DPT is being
>>> created with the wrong caching mode?
>> I suspect the stolen allocation never fails in practice (or almost
>> never, or at least not in CI).
>>> Sounds like someone should fix the DPT creation to correctly
>>> ask for UC/WC. But I suppose someone should measure if WB+flush
>>> is actually faster...
>> I am not sure what is desired here. System memory buffers defaulting to
>> cached is the xe default, so should DPT be an exception I do not know.
> Anything meant for the display engine is supposed to be uncached.

I can add XE_BO_FLAG_SCANOUT to the system memory buffer creation and 
that would handle this aspect. Acceptable to you?

  But..

>
>> In any case AuxCCS seems to only work with DPT in system memory and this
>> clflush. DPT in stolen with GTT access and GTT flushing (as i915 does
>> it) does not seem to work for xe. I guess the entity doing the DPT reads
>> is somehow special coherency wise.
> Sounds like there is still something broken in xe.

... Issue is when you found the magic mocs 61 the CI still saw a 
sporadic failure. 3 out of 44 new tests failed. These sporadic CI fails 
I was never able to reproduce locally. (It was always ADL-P, and I have 
an ADL-P as well.)

Above coupled with the fact i915 has this clflush on the first pin, I 
assumed CCS is just special enough that it is required. For certain with 
it there are no sporadic CI fails.

I even tried removing the clflush from i915 but I wasn't able to repro 
any failures there. This may make it sound like the clflush isn't 
required, but given I am not able to repro failures with xe either I 
think we cannot assume this.

On the overall ADL is not a supported platform with xe. So one option 
could simply be to not complicate my series, allow for sporadic CI fails 
(record them in CI bug log as expected), and revisit the topic 
*if*/*when* a problem outside of CI is found.

Also annoying is that ADL machines are in the xe CI and not i915. If 
they were in i915 I would be able to do some CI runs to see if i915 can 
be made to fail sporadically without the initial clflush.

Regards,

Tvrtko

>

Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Ville Syrjälä]

On Wed, Dec 10, 2025 at 11:07:48AM +0100, Tvrtko Ursulin wrote:
> 
> On 09/12/2025 15:25, Ville Syrjälä wrote:
> > On Tue, Dec 09, 2025 at 03:10:03PM +0100, Tvrtko Ursulin wrote:
> >> On 09/12/2025 10:54, Ville Syrjälä wrote:
> >>> On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
> >>>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>>>
> >>>> If DPT is allocated from system memory it will be created in the default
> >>>> write-back cached mode. This means we need to flush it after populating
> >>>> otherwise nothing works.
> >>>>
> >>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>>> ---
> >>>>    drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
> >>>>    1 file changed, 4 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> index a22a9182dadb..89ee68c40329 100644
> >>>> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> @@ -3,6 +3,7 @@
> >>>>     * Copyright © 2021 Intel Corporation
> >>>>     */
> >>>>    
> >>>> +#include <drm/drm_cache.h>
> >>>>    #include <drm/ttm/ttm_bo.h>
> >>>>    
> >>>>    #include "i915_vma.h"
> >>>> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
> >>>>    					  rot_info->plane[i].dst_stride);
> >>>>    	}
> >>>>    
> >>>> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
> >>>> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
> >>> How is anything working currently if the DPT is being
> >>> created with the wrong caching mode?
> >> I suspect the stolen allocation never fails in practice (or almost
> >> never, or at least not in CI).
> >>> Sounds like someone should fix the DPT creation to correctly
> >>> ask for UC/WC. But I suppose someone should measure if WB+flush
> >>> is actually faster...
> >> I am not sure what is desired here. System memory buffers defaulting to
> >> cached is the xe default, so should DPT be an exception I do not know.
> > Anything meant for the display engine is supposed to be uncached.
> 
> I can add XE_BO_FLAG_SCANOUT to the system memory buffer creation and 
> that would handle this aspect. Acceptable to you?
> 
>   But..
> 
> >
> >> In any case AuxCCS seems to only work with DPT in system memory and this
> >> clflush. DPT in stolen with GTT access and GTT flushing (as i915 does
> >> it) does not seem to work for xe. I guess the entity doing the DPT reads
> >> is somehow special coherency wise.
> > Sounds like there is still something broken in xe.
> 
> ... Issue is when you found the magic mocs 61 the CI still saw a 
> sporadic failure. 3 out of 44 new tests failed. These sporadic CI fails 
> I was never able to reproduce locally. (It was always ADL-P, and I have 
> an ADL-P as well.)
> 
> Above coupled with the fact i915 has this clflush on the first pin, I 
> assumed CCS is just special enough that it is required. For certain with 
> it there are no sporadic CI fails.

clflush does nothing for the display engine. If it helps then
I think there must be dirty cachelines around. I don't see how
anything else could explain it.

One would think it should be possible to even see such dirt right
after allocating a new BO and handing it to the display engine
without touching it in any way (IIRC even reads through the GMADR
aperture trigger cache flushes).

-- 
Ville Syrjälä
Intel

RE: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Saarinen, Jani]

Hi, 

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Tvrtko
> Ursulin
> Sent: Wednesday, 10 December 2025 12.08
> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: intel-xe@lists.freedesktop.org; kernel-dev@igalia.com; Tvrtko Ursulin
> <tvrtko.ursulin@igalia.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory
> 
> 
> On 09/12/2025 15:25, Ville Syrjälä wrote:
> > On Tue, Dec 09, 2025 at 03:10:03PM +0100, Tvrtko Ursulin wrote:
> >> On 09/12/2025 10:54, Ville Syrjälä wrote:
> >>> On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
> >>>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>>>
> >>>> If DPT is allocated from system memory it will be created in the
> >>>> default write-back cached mode. This means we need to flush it
> >>>> after populating otherwise nothing works.
> >>>>
> >>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>>> ---
> >>>>    drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
> >>>>    1 file changed, 4 insertions(+)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> index a22a9182dadb..89ee68c40329 100644
> >>>> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>> @@ -3,6 +3,7 @@
> >>>>     * Copyright © 2021 Intel Corporation
> >>>>     */
> >>>>
> >>>> +#include <drm/drm_cache.h>
> >>>>    #include <drm/ttm/ttm_bo.h>
> >>>>
> >>>>    #include "i915_vma.h"
> >>>> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct
> intel_framebuffer *fb,
> >>>>    					  rot_info->plane[i].dst_stride);
> >>>>    	}
> >>>>
> >>>> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
> >>>> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
> >>> How is anything working currently if the DPT is being created with
> >>> the wrong caching mode?
> >> I suspect the stolen allocation never fails in practice (or almost
> >> never, or at least not in CI).
> >>> Sounds like someone should fix the DPT creation to correctly ask for
> >>> UC/WC. But I suppose someone should measure if WB+flush is actually
> >>> faster...
> >> I am not sure what is desired here. System memory buffers defaulting
> >> to cached is the xe default, so should DPT be an exception I do not know.
> > Anything meant for the display engine is supposed to be uncached.
> 
> I can add XE_BO_FLAG_SCANOUT to the system memory buffer creation and
> that would handle this aspect. Acceptable to you?
> 
>   But..
> 
> >
> >> In any case AuxCCS seems to only work with DPT in system memory and
> >> this clflush. DPT in stolen with GTT access and GTT flushing (as i915
> >> does
> >> it) does not seem to work for xe. I guess the entity doing the DPT
> >> reads is somehow special coherency wise.
> > Sounds like there is still something broken in xe.
> 
> ... Issue is when you found the magic mocs 61 the CI still saw a sporadic
> failure. 3 out of 44 new tests failed. These sporadic CI fails I was never able
> to reproduce locally. (It was always ADL-P, and I have an ADL-P as well.)
> 
> Above coupled with the fact i915 has this clflush on the first pin, I assumed
> CCS is just special enough that it is required. For certain with it there are no
> sporadic CI fails.
> 
> I even tried removing the clflush from i915 but I wasn't able to repro any
> failures there. This may make it sound like the clflush isn't required, but
> given I am not able to repro failures with xe either I think we cannot assume
> this.
> 
> On the overall ADL is not a supported platform with xe. So one option could
> simply be to not complicate my series, allow for sporadic CI fails (record
> them in CI bug log as expected), and revisit the topic
> *if*/*when* a problem outside of CI is found.
> 
> Also annoying is that ADL machines are in the xe CI and not i915. If they were
> in i915 I would be able to do some CI runs to see if i915 can be made to fail
> sporadically without the initial clflush.
There are systems in i915 BAT but not in shards. Perhaps modify test list (BAT) and use that IGT for your kernel changes? 

> 
> Regards,
> 
> Tvrtko
> 
> >

Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Tvrtko Ursulin]

On 10/12/2025 12:17, Saarinen, Jani wrote:
> Hi,
>
>> -----Original Message-----
>> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Tvrtko
>> Ursulin
>> Sent: Wednesday, 10 December 2025 12.08
>> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> Cc: intel-xe@lists.freedesktop.org; kernel-dev@igalia.com; Tvrtko Ursulin
>> <tvrtko.ursulin@igalia.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> Subject: Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory
>>
>>
>> On 09/12/2025 15:25, Ville Syrjälä wrote:
>>> On Tue, Dec 09, 2025 at 03:10:03PM +0100, Tvrtko Ursulin wrote:
>>>> On 09/12/2025 10:54, Ville Syrjälä wrote:
>>>>> On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
>>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>>>>>
>>>>>> If DPT is allocated from system memory it will be created in the
>>>>>> default write-back cached mode. This means we need to flush it
>>>>>> after populating otherwise nothing works.
>>>>>>
>>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>>>>> ---
>>>>>>     drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
>>>>>>     1 file changed, 4 insertions(+)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>>>> b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>>>> index a22a9182dadb..89ee68c40329 100644
>>>>>> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>>>> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>>>>>> @@ -3,6 +3,7 @@
>>>>>>      * Copyright © 2021 Intel Corporation
>>>>>>      */
>>>>>>
>>>>>> +#include <drm/drm_cache.h>
>>>>>>     #include <drm/ttm/ttm_bo.h>
>>>>>>
>>>>>>     #include "i915_vma.h"
>>>>>> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct
>> intel_framebuffer *fb,
>>>>>>     					  rot_info->plane[i].dst_stride);
>>>>>>     	}
>>>>>>
>>>>>> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
>>>>>> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
>>>>> How is anything working currently if the DPT is being created with
>>>>> the wrong caching mode?
>>>> I suspect the stolen allocation never fails in practice (or almost
>>>> never, or at least not in CI).
>>>>> Sounds like someone should fix the DPT creation to correctly ask for
>>>>> UC/WC. But I suppose someone should measure if WB+flush is actually
>>>>> faster...
>>>> I am not sure what is desired here. System memory buffers defaulting
>>>> to cached is the xe default, so should DPT be an exception I do not know.
>>> Anything meant for the display engine is supposed to be uncached.
>> I can add XE_BO_FLAG_SCANOUT to the system memory buffer creation and
>> that would handle this aspect. Acceptable to you?
>>
>>    But..
>>
>>>> In any case AuxCCS seems to only work with DPT in system memory and
>>>> this clflush. DPT in stolen with GTT access and GTT flushing (as i915
>>>> does
>>>> it) does not seem to work for xe. I guess the entity doing the DPT
>>>> reads is somehow special coherency wise.
>>> Sounds like there is still something broken in xe.
>> ... Issue is when you found the magic mocs 61 the CI still saw a sporadic
>> failure. 3 out of 44 new tests failed. These sporadic CI fails I was never able
>> to reproduce locally. (It was always ADL-P, and I have an ADL-P as well.)
>>
>> Above coupled with the fact i915 has this clflush on the first pin, I assumed
>> CCS is just special enough that it is required. For certain with it there are no
>> sporadic CI fails.
>>
>> I even tried removing the clflush from i915 but I wasn't able to repro any
>> failures there. This may make it sound like the clflush isn't required, but
>> given I am not able to repro failures with xe either I think we cannot assume
>> this.
>>
>> On the overall ADL is not a supported platform with xe. So one option could
>> simply be to not complicate my series, allow for sporadic CI fails (record
>> them in CI bug log as expected), and revisit the topic
>> *if*/*when* a problem outside of CI is found.
>>
>> Also annoying is that ADL machines are in the xe CI and not i915. If they were
>> in i915 I would be able to do some CI runs to see if i915 can be made to fail
>> sporadically without the initial clflush.
> There are systems in i915 BAT but not in shards. Perhaps modify test list (BAT) and use that IGT for your kernel changes?

Okay I will try, thanks for the green light Jani. :)

Are they the same type machines/Alderlakes both in the i915 BAT and xe 
shards? Problem could be, as long as something is different, failure to 
trigger the sporadic fails in i915 BAT will not confirm i915 is immune 
to it.

Regards,

Tvrtko

RE: [PATCH v15 06/10] drm/xe: Handle DPT in system memory

[Saarinen, Jani]

Hi, 
> -----Original Message-----
> From: Tvrtko Ursulin <tursulin@igalia.com>
> Sent: Wednesday, 10 December 2025 16.51
> To: Saarinen, Jani <jani.saarinen@intel.com>; Ville Syrjälä
> <ville.syrjala@linux.intel.com>
> Cc: intel-xe@lists.freedesktop.org; kernel-dev@igalia.com; Tvrtko Ursulin
> <tvrtko.ursulin@igalia.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory
> 
> 
> On 10/12/2025 12:17, Saarinen, Jani wrote:
> > Hi,
> >
> >> -----Original Message-----
> >> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of
> >> Tvrtko Ursulin
> >> Sent: Wednesday, 10 December 2025 12.08
> >> To: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> Cc: intel-xe@lists.freedesktop.org; kernel-dev@igalia.com; Tvrtko
> >> Ursulin <tvrtko.ursulin@igalia.com>; Vivi, Rodrigo
> >> <rodrigo.vivi@intel.com>
> >> Subject: Re: [PATCH v15 06/10] drm/xe: Handle DPT in system memory
> >>
> >>
> >> On 09/12/2025 15:25, Ville Syrjälä wrote:
> >>> On Tue, Dec 09, 2025 at 03:10:03PM +0100, Tvrtko Ursulin wrote:
> >>>> On 09/12/2025 10:54, Ville Syrjälä wrote:
> >>>>> On Mon, Dec 08, 2025 at 08:17:17PM +0100, Tvrtko Ursulin wrote:
> >>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>>>>>
> >>>>>> If DPT is allocated from system memory it will be created in the
> >>>>>> default write-back cached mode. This means we need to flush it
> >>>>>> after populating otherwise nothing works.
> >>>>>>
> >>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> >>>>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >>>>>> ---
> >>>>>>     drivers/gpu/drm/xe/display/xe_fb_pin.c | 4 ++++
> >>>>>>     1 file changed, 4 insertions(+)
> >>>>>>
> >>>>>> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>>>> b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>>>> index a22a9182dadb..89ee68c40329 100644
> >>>>>> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>>>> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> >>>>>> @@ -3,6 +3,7 @@
> >>>>>>      * Copyright © 2021 Intel Corporation
> >>>>>>      */
> >>>>>>
> >>>>>> +#include <drm/drm_cache.h>
> >>>>>>     #include <drm/ttm/ttm_bo.h>
> >>>>>>
> >>>>>>     #include "i915_vma.h"
> >>>>>> @@ -162,6 +163,9 @@ static int __xe_pin_fb_vma_dpt(const struct
> >> intel_framebuffer *fb,
> >>>>>>     					  rot_info-
> >plane[i].dst_stride);
> >>>>>>     	}
> >>>>>>
> >>>>>> +	if (!xe_bo_is_vram(dpt) && !xe_bo_is_stolen(dpt))
> >>>>>> +		drm_clflush_virt_range(dpt->vmap.vaddr, dpt_size);
> >>>>> How is anything working currently if the DPT is being created with
> >>>>> the wrong caching mode?
> >>>> I suspect the stolen allocation never fails in practice (or almost
> >>>> never, or at least not in CI).
> >>>>> Sounds like someone should fix the DPT creation to correctly ask
> >>>>> for UC/WC. But I suppose someone should measure if WB+flush is
> >>>>> actually faster...
> >>>> I am not sure what is desired here. System memory buffers
> >>>> defaulting to cached is the xe default, so should DPT be an exception I
> do not know.
> >>> Anything meant for the display engine is supposed to be uncached.
> >> I can add XE_BO_FLAG_SCANOUT to the system memory buffer creation
> and
> >> that would handle this aspect. Acceptable to you?
> >>
> >>    But..
> >>
> >>>> In any case AuxCCS seems to only work with DPT in system memory and
> >>>> this clflush. DPT in stolen with GTT access and GTT flushing (as
> >>>> i915 does
> >>>> it) does not seem to work for xe. I guess the entity doing the DPT
> >>>> reads is somehow special coherency wise.
> >>> Sounds like there is still something broken in xe.
> >> ... Issue is when you found the magic mocs 61 the CI still saw a
> >> sporadic failure. 3 out of 44 new tests failed. These sporadic CI
> >> fails I was never able to reproduce locally. (It was always ADL-P,
> >> and I have an ADL-P as well.)
> >>
> >> Above coupled with the fact i915 has this clflush on the first pin, I
> >> assumed CCS is just special enough that it is required. For certain
> >> with it there are no sporadic CI fails.
> >>
> >> I even tried removing the clflush from i915 but I wasn't able to
> >> repro any failures there. This may make it sound like the clflush
> >> isn't required, but given I am not able to repro failures with xe
> >> either I think we cannot assume this.
> >>
> >> On the overall ADL is not a supported platform with xe. So one option
> >> could simply be to not complicate my series, allow for sporadic CI
> >> fails (record them in CI bug log as expected), and revisit the topic
> >> *if*/*when* a problem outside of CI is found.
> >>
> >> Also annoying is that ADL machines are in the xe CI and not i915. If
> >> they were in i915 I would be able to do some CI runs to see if i915
> >> can be made to fail sporadically without the initial clflush.
> > There are systems in i915 BAT but not in shards. Perhaps modify test list
> (BAT) and use that IGT for your kernel changes?
> 
> Okay I will try, thanks for the green light Jani. :)
Well anyone can send CI patches : ) 

> Are they the same type machines/Alderlakes both in the i915 BAT and xe
> shards? Problem could be, as long as something is different, failure to trigger
> the sporadic fails in i915 BAT will not confirm i915 is immune to it.
Not sure but I see this 
I915 BAT:  https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17656/bat-adlp-6/boot0.txt
<6>[    0.000000] DMI: Intel Corporation Alder Lake Client Platform/AlderLake-P DDR4 RVP, BIOS RPLPFWI1.R00.4035.A00.2301200723 01/20/2023
<6>[    0.149935] smpboot: CPU0: Genuine Intel(R) 0000 (family: 0x6, model: 0x9a, stepping: 0x3)

Xe shards: 
https://intel-gfx-ci.01.org/tree/intel-xe/xe-4211-12271f632915efe0c5d4171b9c0e90f57ecdfe01/shard-adlp-6/boot14.txt
<6>[    0.000000] DMI: Intel Corporation Alder Lake Client Platform/AlderLake-P DDR5 RVP, BIOS RPLPFWI1.R00.4035.A00.2301200723 01/20/2023
<6>[    0.105682] smpboot: CPU0: Genuine Intel(R) 0000 (family: 0x6, model: 0x9a, stepping: 0x3)
Looks boards are different but.. go and figure out. 

> 
> Regards,
> 
> Tvrtko

Br,
Jani

[PATCH v15 07/10] drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

With DPT in stolen memory there are occasional pipe crc IGT failures in
tests such as kms_flip_tiling. Allocate a normal system memory object
instead.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 89ee68c40329..ce9750da57e7 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -80,6 +80,20 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
 	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
 }
 
+static bool try_dpt_stolen(const struct intel_framebuffer *fb, struct xe_bo *bo)
+{
+	/*
+	 * XXX: DPT in stolen memory on IGFX platforms (at least Alderlake)
+	 * suffers from occasional pipe crc IGT failures in tests such as
+	 * kms_flip_tiling.
+	 */
+	if (intel_fb_is_ccs_modifier(fb->base.modifier) &&
+	    !xe_bo_is_vram(bo) && !xe_bo_is_stolen(bo))
+		return false;
+
+	return true;
+}
+
 static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
 			       const struct i915_gtt_view *view,
 			       struct i915_vma *vma,
@@ -89,7 +103,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
 	struct xe_tile *tile0 = xe_device_get_root_tile(xe);
 	struct xe_ggtt *ggtt = tile0->mem.ggtt;
 	struct drm_gem_object *obj = intel_fb_bo(&fb->base);
-	struct xe_bo *bo = gem_to_xe_bo(obj), *dpt;
+	struct xe_bo *bo = gem_to_xe_bo(obj), *dpt = ERR_PTR(-EINVAL);
 	u32 dpt_size, size = bo->ttm.base.size;
 
 	if (view->type == I915_GTT_VIEW_NORMAL)
@@ -110,7 +124,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
 						   XE_BO_FLAG_GGTT |
 						   XE_BO_FLAG_PAGETABLE,
 						   alignment, false);
-	else
+	else if (try_dpt_stolen(fb, bo))
 		dpt = xe_bo_create_pin_map_at_novm(xe, tile0,
 						   dpt_size,  ~0ull,
 						   ttm_bo_type_kernel,
-- 
2.52.0

[PATCH v15 08/10] drm/xe/display: Add support for AuxCCS

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Add support for mapping the auxiliary CCS buffer into the DPT page tables.

This will allow for better power efficiency by enabling the render
compression frame buffer modifiers such as
I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS in a following patch.

We do this by refactoring the code a bit so handling for the linear
auxiliary frame buffer can be added in a tidy way. Also replace some
hardcoded constants.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Michael J. Ruhl <michael.j.ruhl@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/xe/display/xe_fb_pin.c | 111 ++++++++++++++++++-------
 1 file changed, 81 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index ce9750da57e7..e9f77b22862c 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -51,33 +51,94 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
 	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
 }
 
+static unsigned int
+write_dpt_padding(struct iosys_map *map, unsigned int dest, unsigned int pad)
+{
+	/* The DE ignores the PTEs for the padding tiles */
+	return dest + pad * sizeof(u64);
+}
+
+static unsigned int
+write_dpt_remapped_linear(struct xe_bo *bo, struct iosys_map *map,
+			  unsigned int dest,
+			  const struct intel_remapped_plane_info *plane)
+{
+	struct xe_device *xe = xe_bo_device(bo);
+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
+	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
+						 xe->pat.idx[XE_CACHE_NONE]);
+	unsigned int offset = plane->offset * XE_PAGE_SIZE;
+	unsigned int size = plane->size;
+
+	while (size--) {
+		u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE);
+
+		iosys_map_wr(map, dest, u64, addr | pte);
+		dest += sizeof(u64);
+		offset += XE_PAGE_SIZE;
+	}
+
+	return dest;
+}
+
+static unsigned int
+write_dpt_remapped_tiled(struct xe_bo *bo, struct iosys_map *map,
+			 unsigned int dest,
+			 const struct intel_remapped_plane_info *plane)
+{
+	struct xe_device *xe = xe_bo_device(bo);
+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
+	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
+						 xe->pat.idx[XE_CACHE_NONE]);
+	unsigned int offset, column, row;
+
+	for (row = 0; row < plane->height; row++) {
+		offset = (plane->offset + plane->src_stride * row) *
+			 XE_PAGE_SIZE;
+
+		for (column = 0; column < plane->width; column++) {
+			u64 addr = xe_bo_addr(bo, offset, XE_PAGE_SIZE);
+
+			iosys_map_wr(map, dest, u64, addr | pte);
+			dest += sizeof(u64);
+			offset += XE_PAGE_SIZE;
+		}
+
+		dest = write_dpt_padding(map, dest,
+					 plane->dst_stride - plane->width);
+	}
+
+	return dest;
+}
+
 static void
-write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs,
-		   u32 bo_ofs, u32 width, u32 height, u32 src_stride,
-		   u32 dst_stride)
+write_dpt_remapped(struct xe_bo *bo,
+		   const struct intel_remapped_info *remap_info,
+		   struct iosys_map *map)
 {
-	struct xe_device *xe = xe_bo_device(bo);
-	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
-	u32 column, row;
-	u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
+	unsigned int i, dest = 0;
 
-	for (row = 0; row < height; row++) {
-		u32 src_idx = src_stride * row + bo_ofs;
+	for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++) {
+		const struct intel_remapped_plane_info *plane =
+						&remap_info->plane[i];
 
-		for (column = 0; column < width; column++) {
-			u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE);
-			iosys_map_wr(map, *dpt_ofs, u64, pte | addr);
+		if (!plane->width && !plane->height && !plane->linear)
+			continue;
 
-			*dpt_ofs += 8;
-			src_idx++;
+		if (remap_info->plane_alignment) {
+			const unsigned int index = dest / sizeof(u64);
+			const unsigned int pad =
+				ALIGN(index, remap_info->plane_alignment) -
+				index;
+
+			dest = write_dpt_padding(map, dest, pad);
 		}
 
-		/* The DE ignores the PTEs for the padding tiles */
-		*dpt_ofs += (dst_stride - width) * 8;
+		if (plane->linear)
+			dest = write_dpt_remapped_linear(bo, map, dest, plane);
+		else
+			dest = write_dpt_remapped_tiled(bo, map, dest, plane);
 	}
-
-	/* Align to next page */
-	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
 }
 
 static bool try_dpt_stolen(const struct intel_framebuffer *fb, struct xe_bo *bo)
@@ -153,17 +214,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
 			iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr);
 		}
 	} else if (view->type == I915_GTT_VIEW_REMAPPED) {
-		const struct intel_remapped_info *remap_info = &view->remapped;
-		u32 i, dpt_ofs = 0;
-
-		for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++)
-			write_dpt_remapped(bo, &dpt->vmap, &dpt_ofs,
-					   remap_info->plane[i].offset,
-					   remap_info->plane[i].width,
-					   remap_info->plane[i].height,
-					   remap_info->plane[i].src_stride,
-					   remap_info->plane[i].dst_stride);
-
+		write_dpt_remapped(bo, &view->remapped, &dpt->vmap);
 	} else {
 		const struct intel_rotation_info *rot_info = &view->rotated;
 		u32 i, dpt_ofs = 0;
-- 
2.52.0

[PATCH v15 09/10] drm/i915/display: Detect AuxCCS support via display parent interface

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Whether AuxCCS can be properly supported depends on the support both from
the display side and non-display side of the driver.

Let us therefore allow for the non-display part to be queried via the
display parent interface.

The new interface replaces the HAS_AUX_CCS macro and we also remove the
FIXME from skl_universal_plane_create since now the xe will not advertise
the AuxCCS caps to start with so they do not need to be removed after
enumeration.

Also, by removing this build specific FIXME we come a step closer to fully
de-coupling display and non-display.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h |  1 -
 drivers/gpu/drm/i915/display/intel_fb.c             |  3 ++-
 drivers/gpu/drm/i915/display/intel_parent.c         |  5 +++++
 drivers/gpu/drm/i915/display/intel_parent.h         |  2 ++
 drivers/gpu/drm/i915/display/skl_universal_plane.c  |  9 ++-------
 drivers/gpu/drm/i915/i915_driver.c                  | 10 ++++++++++
 include/drm/intel/display_parent_interface.h        |  3 +++
 7 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 11c2b2883f35..dc61c6560015 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -149,7 +149,6 @@ struct intel_display_platforms {
 #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
 #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
 #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
-#define HAS_AUX_CCS(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
 #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
 #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
 #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index b34b4961fe1c..5b8e02ca2faf 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -21,6 +21,7 @@
 #include "intel_fb_bo.h"
 #include "intel_frontbuffer.h"
 #include "intel_panic.h"
+#include "intel_parent.h"
 #include "intel_plane.h"
 
 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
@@ -558,7 +559,7 @@ static bool plane_has_modifier(struct intel_display *display,
 	 * where supported.
 	 */
 	if (intel_fb_is_ccs_modifier(md->modifier) &&
-	    HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes)
+	    intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
 		return false;
 
 	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
index 2ea310cc3509..7a55def19836 100644
--- a/drivers/gpu/drm/i915/display/intel_parent.c
+++ b/drivers/gpu/drm/i915/display/intel_parent.c
@@ -94,3 +94,8 @@ void intel_parent_fence_priority_display(struct intel_display *display, struct d
 	if (display->parent->fence_priority_display)
 		display->parent->fence_priority_display(fence);
 }
+
+bool intel_parent_has_auxccs(struct intel_display *display)
+{
+	return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
index 8f91a6f75c53..f34ee81ed7a1 100644
--- a/drivers/gpu/drm/i915/display/intel_parent.h
+++ b/drivers/gpu/drm/i915/display/intel_parent.h
@@ -33,4 +33,6 @@ bool intel_parent_has_fenced_regions(struct intel_display *display);
 
 void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
 
+bool intel_parent_has_auxccs(struct intel_display *display);
+
 #endif /* __INTEL_PARENT_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6cd94f400e3f..7e5dce8cfec0 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -22,6 +22,7 @@
 #include "intel_fbc.h"
 #include "intel_frontbuffer.h"
 #include "intel_panic.h"
+#include "intel_parent.h"
 #include "intel_plane.h"
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
@@ -1602,7 +1603,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
 	}
 
 	/* FLAT CCS doesn't need to program AUX_DIST */
-	if (HAS_AUX_CCS(display))
+	if (intel_parent_has_auxccs(display))
 		intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
 				   skl_plane_aux_dist(plane_state, color_plane));
 
@@ -2972,12 +2973,6 @@ skl_universal_plane_create(struct intel_display *display,
 	else
 		caps = skl_plane_caps(display, pipe, plane_id);
 
-	/* FIXME: xe has problems with AUX */
-	if (!IS_ENABLED(I915) && HAS_AUX_CCS(display))
-		caps &= ~(INTEL_PLANE_CAP_CCS_RC |
-			  INTEL_PLANE_CAP_CCS_RC_CC |
-			  INTEL_PLANE_CAP_CCS_MC);
-
 	modifiers = intel_fb_plane_get_modifiers(display, caps);
 
 	ret = drm_universal_plane_init(display->drm, &plane->base,
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d98839427ef9..59e396a74ca4 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -757,6 +757,15 @@ static void fence_priority_display(struct dma_fence *fence)
 		i915_gem_fence_wait_priority_display(fence);
 }
 
+static bool has_auxccs(struct drm_device *drm)
+{
+	struct drm_i915_private *i915 = to_i915(drm);
+
+	return IS_GRAPHICS_VER(i915, 9, 12) ||
+	       IS_ALDERLAKE_P(i915) ||
+	       IS_METEORLAKE(i915);
+}
+
 static const struct intel_display_parent_interface parent = {
 	.hdcp = &i915_display_hdcp_interface,
 	.rpm = &i915_display_rpm_interface,
@@ -765,6 +774,7 @@ static const struct intel_display_parent_interface parent = {
 	.vgpu_active = vgpu_active,
 	.has_fenced_regions = has_fenced_regions,
 	.fence_priority_display = fence_priority_display,
+	.has_auxccs = has_auxccs,
 };
 
 const struct intel_display_parent_interface *i915_driver_parent_interface(void)
diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h
index 61d1b22adc83..0d79f3c189c3 100644
--- a/include/drm/intel/display_parent_interface.h
+++ b/include/drm/intel/display_parent_interface.h
@@ -80,6 +80,9 @@ struct intel_display_parent_interface {
 
 	/** @fence_priority_display: Set display priority. Optional. */
 	void (*fence_priority_display)(struct dma_fence *fence);
+
+	/** @has_auxcss: Are AuxCCS formats supported by the parent. Optional. */
+	bool (*has_auxccs)(struct drm_device *drm);
 };
 
 #endif
-- 
2.52.0

Re: [PATCH v15 09/10] drm/i915/display: Detect AuxCCS support via display parent interface

[Jani Nikula]

On Mon, 08 Dec 2025, Tvrtko Ursulin <tursulin@igalia.com> wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>
> Whether AuxCCS can be properly supported depends on the support both from
> the display side and non-display side of the driver.
>
> Let us therefore allow for the non-display part to be queried via the
> display parent interface.
>
> The new interface replaces the HAS_AUX_CCS macro and we also remove the
> FIXME from skl_universal_plane_create since now the xe will not advertise
> the AuxCCS caps to start with so they do not need to be removed after
> enumeration.
>
> Also, by removing this build specific FIXME we come a step closer to fully
> de-coupling display and non-display.

This could even be a separate prep patch.

Acked-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h |  1 -
>  drivers/gpu/drm/i915/display/intel_fb.c             |  3 ++-
>  drivers/gpu/drm/i915/display/intel_parent.c         |  5 +++++
>  drivers/gpu/drm/i915/display/intel_parent.h         |  2 ++
>  drivers/gpu/drm/i915/display/skl_universal_plane.c  |  9 ++-------
>  drivers/gpu/drm/i915/i915_driver.c                  | 10 ++++++++++
>  include/drm/intel/display_parent_interface.h        |  3 +++
>  7 files changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 11c2b2883f35..dc61c6560015 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -149,7 +149,6 @@ struct intel_display_platforms {
>  #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>  #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
>  #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
> -#define HAS_AUX_CCS(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
>  #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
>  #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
>  #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index b34b4961fe1c..5b8e02ca2faf 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -21,6 +21,7 @@
>  #include "intel_fb_bo.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_panic.h"
> +#include "intel_parent.h"
>  #include "intel_plane.h"
>  
>  #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
> @@ -558,7 +559,7 @@ static bool plane_has_modifier(struct intel_display *display,
>  	 * where supported.
>  	 */
>  	if (intel_fb_is_ccs_modifier(md->modifier) &&
> -	    HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes)
> +	    intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
>  		return false;
>  
>  	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
> diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
> index 2ea310cc3509..7a55def19836 100644
> --- a/drivers/gpu/drm/i915/display/intel_parent.c
> +++ b/drivers/gpu/drm/i915/display/intel_parent.c
> @@ -94,3 +94,8 @@ void intel_parent_fence_priority_display(struct intel_display *display, struct d
>  	if (display->parent->fence_priority_display)
>  		display->parent->fence_priority_display(fence);
>  }
> +
> +bool intel_parent_has_auxccs(struct intel_display *display)
> +{
> +	return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
> index 8f91a6f75c53..f34ee81ed7a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_parent.h
> +++ b/drivers/gpu/drm/i915/display/intel_parent.h
> @@ -33,4 +33,6 @@ bool intel_parent_has_fenced_regions(struct intel_display *display);
>  
>  void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
>  
> +bool intel_parent_has_auxccs(struct intel_display *display);
> +
>  #endif /* __INTEL_PARENT_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6cd94f400e3f..7e5dce8cfec0 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -22,6 +22,7 @@
>  #include "intel_fbc.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_panic.h"
> +#include "intel_parent.h"
>  #include "intel_plane.h"
>  #include "intel_psr.h"
>  #include "intel_psr_regs.h"
> @@ -1602,7 +1603,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
>  	}
>  
>  	/* FLAT CCS doesn't need to program AUX_DIST */
> -	if (HAS_AUX_CCS(display))
> +	if (intel_parent_has_auxccs(display))
>  		intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
>  				   skl_plane_aux_dist(plane_state, color_plane));
>  
> @@ -2972,12 +2973,6 @@ skl_universal_plane_create(struct intel_display *display,
>  	else
>  		caps = skl_plane_caps(display, pipe, plane_id);
>  
> -	/* FIXME: xe has problems with AUX */
> -	if (!IS_ENABLED(I915) && HAS_AUX_CCS(display))
> -		caps &= ~(INTEL_PLANE_CAP_CCS_RC |
> -			  INTEL_PLANE_CAP_CCS_RC_CC |
> -			  INTEL_PLANE_CAP_CCS_MC);
> -
>  	modifiers = intel_fb_plane_get_modifiers(display, caps);
>  
>  	ret = drm_universal_plane_init(display->drm, &plane->base,
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index d98839427ef9..59e396a74ca4 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -757,6 +757,15 @@ static void fence_priority_display(struct dma_fence *fence)
>  		i915_gem_fence_wait_priority_display(fence);
>  }
>  
> +static bool has_auxccs(struct drm_device *drm)
> +{
> +	struct drm_i915_private *i915 = to_i915(drm);
> +
> +	return IS_GRAPHICS_VER(i915, 9, 12) ||
> +	       IS_ALDERLAKE_P(i915) ||
> +	       IS_METEORLAKE(i915);
> +}
> +
>  static const struct intel_display_parent_interface parent = {
>  	.hdcp = &i915_display_hdcp_interface,
>  	.rpm = &i915_display_rpm_interface,
> @@ -765,6 +774,7 @@ static const struct intel_display_parent_interface parent = {
>  	.vgpu_active = vgpu_active,
>  	.has_fenced_regions = has_fenced_regions,
>  	.fence_priority_display = fence_priority_display,
> +	.has_auxccs = has_auxccs,
>  };
>  
>  const struct intel_display_parent_interface *i915_driver_parent_interface(void)
> diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h
> index 61d1b22adc83..0d79f3c189c3 100644
> --- a/include/drm/intel/display_parent_interface.h
> +++ b/include/drm/intel/display_parent_interface.h
> @@ -80,6 +80,9 @@ struct intel_display_parent_interface {
>  
>  	/** @fence_priority_display: Set display priority. Optional. */
>  	void (*fence_priority_display)(struct dma_fence *fence);
> +
> +	/** @has_auxcss: Are AuxCCS formats supported by the parent. Optional. */
> +	bool (*has_auxccs)(struct drm_device *drm);
>  };
>  
>  #endif

-- 
Jani Nikula, Intel

Re: [PATCH v15 09/10] drm/i915/display: Detect AuxCCS support via display parent interface

[Tvrtko Ursulin]

On 09/12/2025 09:31, Jani Nikula wrote:
> On Mon, 08 Dec 2025, Tvrtko Ursulin <tursulin@igalia.com> wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>
>> Whether AuxCCS can be properly supported depends on the support both from
>> the display side and non-display side of the driver.
>>
>> Let us therefore allow for the non-display part to be queried via the
>> display parent interface.
>>
>> The new interface replaces the HAS_AUX_CCS macro and we also remove the
>> FIXME from skl_universal_plane_create since now the xe will not advertise
>> the AuxCCS caps to start with so they do not need to be removed after
>> enumeration.
>>
>> Also, by removing this build specific FIXME we come a step closer to fully
>> de-coupling display and non-display.
> This could even be a separate prep patch.

It is standalone anyway so I could easily send it out on its own. 
Actually, to complete the cleanup it will need to be together with the 
HAS_AUX_DIST rename Ville suggested in 9/10. I'll do that then.

Regards,

Tvrtko

>
> Acked-by: Jani Nikula <jani.nikula@intel.com>
>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>> References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: José Roberto de Souza <jose.souza@intel.com>
>> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_device.h |  1 -
>>   drivers/gpu/drm/i915/display/intel_fb.c             |  3 ++-
>>   drivers/gpu/drm/i915/display/intel_parent.c         |  5 +++++
>>   drivers/gpu/drm/i915/display/intel_parent.h         |  2 ++
>>   drivers/gpu/drm/i915/display/skl_universal_plane.c  |  9 ++-------
>>   drivers/gpu/drm/i915/i915_driver.c                  | 10 ++++++++++
>>   include/drm/intel/display_parent_interface.h        |  3 +++
>>   7 files changed, 24 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index 11c2b2883f35..dc61c6560015 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -149,7 +149,6 @@ struct intel_display_platforms {
>>   #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>>   #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
>>   #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
>> -#define HAS_AUX_CCS(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
>>   #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
>>   #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
>>   #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
>> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
>> index b34b4961fe1c..5b8e02ca2faf 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fb.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
>> @@ -21,6 +21,7 @@
>>   #include "intel_fb_bo.h"
>>   #include "intel_frontbuffer.h"
>>   #include "intel_panic.h"
>> +#include "intel_parent.h"
>>   #include "intel_plane.h"
>>   
>>   #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
>> @@ -558,7 +559,7 @@ static bool plane_has_modifier(struct intel_display *display,
>>   	 * where supported.
>>   	 */
>>   	if (intel_fb_is_ccs_modifier(md->modifier) &&
>> -	    HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes)
>> +	    intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
>>   		return false;
>>   
>>   	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
>> diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
>> index 2ea310cc3509..7a55def19836 100644
>> --- a/drivers/gpu/drm/i915/display/intel_parent.c
>> +++ b/drivers/gpu/drm/i915/display/intel_parent.c
>> @@ -94,3 +94,8 @@ void intel_parent_fence_priority_display(struct intel_display *display, struct d
>>   	if (display->parent->fence_priority_display)
>>   		display->parent->fence_priority_display(fence);
>>   }
>> +
>> +bool intel_parent_has_auxccs(struct intel_display *display)
>> +{
>> +	return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
>> index 8f91a6f75c53..f34ee81ed7a1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_parent.h
>> +++ b/drivers/gpu/drm/i915/display/intel_parent.h
>> @@ -33,4 +33,6 @@ bool intel_parent_has_fenced_regions(struct intel_display *display);
>>   
>>   void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
>>   
>> +bool intel_parent_has_auxccs(struct intel_display *display);
>> +
>>   #endif /* __INTEL_PARENT_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> index 6cd94f400e3f..7e5dce8cfec0 100644
>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>> @@ -22,6 +22,7 @@
>>   #include "intel_fbc.h"
>>   #include "intel_frontbuffer.h"
>>   #include "intel_panic.h"
>> +#include "intel_parent.h"
>>   #include "intel_plane.h"
>>   #include "intel_psr.h"
>>   #include "intel_psr_regs.h"
>> @@ -1602,7 +1603,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
>>   	}
>>   
>>   	/* FLAT CCS doesn't need to program AUX_DIST */
>> -	if (HAS_AUX_CCS(display))
>> +	if (intel_parent_has_auxccs(display))
>>   		intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
>>   				   skl_plane_aux_dist(plane_state, color_plane));
>>   
>> @@ -2972,12 +2973,6 @@ skl_universal_plane_create(struct intel_display *display,
>>   	else
>>   		caps = skl_plane_caps(display, pipe, plane_id);
>>   
>> -	/* FIXME: xe has problems with AUX */
>> -	if (!IS_ENABLED(I915) && HAS_AUX_CCS(display))
>> -		caps &= ~(INTEL_PLANE_CAP_CCS_RC |
>> -			  INTEL_PLANE_CAP_CCS_RC_CC |
>> -			  INTEL_PLANE_CAP_CCS_MC);
>> -
>>   	modifiers = intel_fb_plane_get_modifiers(display, caps);
>>   
>>   	ret = drm_universal_plane_init(display->drm, &plane->base,
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> index d98839427ef9..59e396a74ca4 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -757,6 +757,15 @@ static void fence_priority_display(struct dma_fence *fence)
>>   		i915_gem_fence_wait_priority_display(fence);
>>   }
>>   
>> +static bool has_auxccs(struct drm_device *drm)
>> +{
>> +	struct drm_i915_private *i915 = to_i915(drm);
>> +
>> +	return IS_GRAPHICS_VER(i915, 9, 12) ||
>> +	       IS_ALDERLAKE_P(i915) ||
>> +	       IS_METEORLAKE(i915);
>> +}
>> +
>>   static const struct intel_display_parent_interface parent = {
>>   	.hdcp = &i915_display_hdcp_interface,
>>   	.rpm = &i915_display_rpm_interface,
>> @@ -765,6 +774,7 @@ static const struct intel_display_parent_interface parent = {
>>   	.vgpu_active = vgpu_active,
>>   	.has_fenced_regions = has_fenced_regions,
>>   	.fence_priority_display = fence_priority_display,
>> +	.has_auxccs = has_auxccs,
>>   };
>>   
>>   const struct intel_display_parent_interface *i915_driver_parent_interface(void)
>> diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h
>> index 61d1b22adc83..0d79f3c189c3 100644
>> --- a/include/drm/intel/display_parent_interface.h
>> +++ b/include/drm/intel/display_parent_interface.h
>> @@ -80,6 +80,9 @@ struct intel_display_parent_interface {
>>   
>>   	/** @fence_priority_display: Set display priority. Optional. */
>>   	void (*fence_priority_display)(struct dma_fence *fence);
>> +
>> +	/** @has_auxcss: Are AuxCCS formats supported by the parent. Optional. */
>> +	bool (*has_auxccs)(struct drm_device *drm);
>>   };
>>   
>>   #endif

Re: [PATCH v15 09/10] drm/i915/display: Detect AuxCCS support via display parent interface

[Ville Syrjälä]

On Mon, Dec 08, 2025 at 08:17:20PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> 
> Whether AuxCCS can be properly supported depends on the support both from
> the display side and non-display side of the driver.
> 
> Let us therefore allow for the non-display part to be queried via the
> display parent interface.
> 
> The new interface replaces the HAS_AUX_CCS macro and we also remove the
> FIXME from skl_universal_plane_create since now the xe will not advertise
> the AuxCCS caps to start with so they do not need to be removed after
> enumeration.
> 
> Also, by removing this build specific FIXME we come a step closer to fully
> de-coupling display and non-display.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h |  1 -
>  drivers/gpu/drm/i915/display/intel_fb.c             |  3 ++-
>  drivers/gpu/drm/i915/display/intel_parent.c         |  5 +++++
>  drivers/gpu/drm/i915/display/intel_parent.h         |  2 ++
>  drivers/gpu/drm/i915/display/skl_universal_plane.c  |  9 ++-------
>  drivers/gpu/drm/i915/i915_driver.c                  | 10 ++++++++++
>  include/drm/intel/display_parent_interface.h        |  3 +++
>  7 files changed, 24 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 11c2b2883f35..dc61c6560015 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -149,7 +149,6 @@ struct intel_display_platforms {
>  #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>  #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
>  #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
> -#define HAS_AUX_CCS(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
>  #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
>  #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
>  #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index b34b4961fe1c..5b8e02ca2faf 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -21,6 +21,7 @@
>  #include "intel_fb_bo.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_panic.h"
> +#include "intel_parent.h"
>  #include "intel_plane.h"
>  
>  #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
> @@ -558,7 +559,7 @@ static bool plane_has_modifier(struct intel_display *display,
>  	 * where supported.
>  	 */
>  	if (intel_fb_is_ccs_modifier(md->modifier) &&
> -	    HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes)
> +	    intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
>  		return false;
>  
>  	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
> diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
> index 2ea310cc3509..7a55def19836 100644
> --- a/drivers/gpu/drm/i915/display/intel_parent.c
> +++ b/drivers/gpu/drm/i915/display/intel_parent.c
> @@ -94,3 +94,8 @@ void intel_parent_fence_priority_display(struct intel_display *display, struct d
>  	if (display->parent->fence_priority_display)
>  		display->parent->fence_priority_display(fence);
>  }
> +
> +bool intel_parent_has_auxccs(struct intel_display *display)
> +{
> +	return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
> index 8f91a6f75c53..f34ee81ed7a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_parent.h
> +++ b/drivers/gpu/drm/i915/display/intel_parent.h
> @@ -33,4 +33,6 @@ bool intel_parent_has_fenced_regions(struct intel_display *display);
>  
>  void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
>  
> +bool intel_parent_has_auxccs(struct intel_display *display);
> +
>  #endif /* __INTEL_PARENT_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6cd94f400e3f..7e5dce8cfec0 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -22,6 +22,7 @@
>  #include "intel_fbc.h"
>  #include "intel_frontbuffer.h"
>  #include "intel_panic.h"
> +#include "intel_parent.h"
>  #include "intel_plane.h"
>  #include "intel_psr.h"
>  #include "intel_psr_regs.h"
> @@ -1602,7 +1603,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
>  	}
>  
>  	/* FLAT CCS doesn't need to program AUX_DIST */
> -	if (HAS_AUX_CCS(display))
> +	if (intel_parent_has_auxccs(display))

This is wrong. This is also used for planar formats on
pre-icl. I'd just leave it be so that we always write sensible
o PLANE_AUX_DIST.

>  		intel_de_write_dsb(display, dsb, PLANE_AUX_DIST(pipe, plane_id),
>  				   skl_plane_aux_dist(plane_state, color_plane));
>  
> @@ -2972,12 +2973,6 @@ skl_universal_plane_create(struct intel_display *display,
>  	else
>  		caps = skl_plane_caps(display, pipe, plane_id);
>  
> -	/* FIXME: xe has problems with AUX */
> -	if (!IS_ENABLED(I915) && HAS_AUX_CCS(display))
> -		caps &= ~(INTEL_PLANE_CAP_CCS_RC |
> -			  INTEL_PLANE_CAP_CCS_RC_CC |
> -			  INTEL_PLANE_CAP_CCS_MC);
> -
>  	modifiers = intel_fb_plane_get_modifiers(display, caps);
>  
>  	ret = drm_universal_plane_init(display->drm, &plane->base,
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index d98839427ef9..59e396a74ca4 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -757,6 +757,15 @@ static void fence_priority_display(struct dma_fence *fence)
>  		i915_gem_fence_wait_priority_display(fence);
>  }
>  
> +static bool has_auxccs(struct drm_device *drm)
> +{
> +	struct drm_i915_private *i915 = to_i915(drm);
> +
> +	return IS_GRAPHICS_VER(i915, 9, 12) ||
> +	       IS_ALDERLAKE_P(i915) ||
> +	       IS_METEORLAKE(i915);
> +}
> +
>  static const struct intel_display_parent_interface parent = {
>  	.hdcp = &i915_display_hdcp_interface,
>  	.rpm = &i915_display_rpm_interface,
> @@ -765,6 +774,7 @@ static const struct intel_display_parent_interface parent = {
>  	.vgpu_active = vgpu_active,
>  	.has_fenced_regions = has_fenced_regions,
>  	.fence_priority_display = fence_priority_display,
> +	.has_auxccs = has_auxccs,
>  };
>  
>  const struct intel_display_parent_interface *i915_driver_parent_interface(void)
> diff --git a/include/drm/intel/display_parent_interface.h b/include/drm/intel/display_parent_interface.h
> index 61d1b22adc83..0d79f3c189c3 100644
> --- a/include/drm/intel/display_parent_interface.h
> +++ b/include/drm/intel/display_parent_interface.h
> @@ -80,6 +80,9 @@ struct intel_display_parent_interface {
>  
>  	/** @fence_priority_display: Set display priority. Optional. */
>  	void (*fence_priority_display)(struct dma_fence *fence);
> +
> +	/** @has_auxcss: Are AuxCCS formats supported by the parent. Optional. */
> +	bool (*has_auxccs)(struct drm_device *drm);
>  };
>  
>  #endif
> -- 
> 2.52.0

-- 
Ville Syrjälä
Intel

Re: [PATCH v15 09/10] drm/i915/display: Detect AuxCCS support via display parent interface

[Ville Syrjälä]

On Tue, Dec 09, 2025 at 11:42:35AM +0200, Ville Syrjälä wrote:
> On Mon, Dec 08, 2025 at 08:17:20PM +0100, Tvrtko Ursulin wrote:
> > From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> > 
> > Whether AuxCCS can be properly supported depends on the support both from
> > the display side and non-display side of the driver.
> > 
> > Let us therefore allow for the non-display part to be queried via the
> > display parent interface.
> > 
> > The new interface replaces the HAS_AUX_CCS macro and we also remove the
> > FIXME from skl_universal_plane_create since now the xe will not advertise
> > the AuxCCS caps to start with so they do not need to be removed after
> > enumeration.
> > 
> > Also, by removing this build specific FIXME we come a step closer to fully
> > de-coupling display and non-display.
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
> > References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_device.h |  1 -
> >  drivers/gpu/drm/i915/display/intel_fb.c             |  3 ++-
> >  drivers/gpu/drm/i915/display/intel_parent.c         |  5 +++++
> >  drivers/gpu/drm/i915/display/intel_parent.h         |  2 ++
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c  |  9 ++-------
> >  drivers/gpu/drm/i915/i915_driver.c                  | 10 ++++++++++
> >  include/drm/intel/display_parent_interface.h        |  3 +++
> >  7 files changed, 24 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index 11c2b2883f35..dc61c6560015 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -149,7 +149,6 @@ struct intel_display_platforms {
> >  #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
> >  #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
> >  #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
> > -#define HAS_AUX_CCS(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
> >  #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
> >  #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
> >  #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index b34b4961fe1c..5b8e02ca2faf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -21,6 +21,7 @@
> >  #include "intel_fb_bo.h"
> >  #include "intel_frontbuffer.h"
> >  #include "intel_panic.h"
> > +#include "intel_parent.h"
> >  #include "intel_plane.h"
> >  
> >  #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
> > @@ -558,7 +559,7 @@ static bool plane_has_modifier(struct intel_display *display,
> >  	 * where supported.
> >  	 */
> >  	if (intel_fb_is_ccs_modifier(md->modifier) &&
> > -	    HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes)
> > +	    intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
> >  		return false;
> >  
> >  	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
> > diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
> > index 2ea310cc3509..7a55def19836 100644
> > --- a/drivers/gpu/drm/i915/display/intel_parent.c
> > +++ b/drivers/gpu/drm/i915/display/intel_parent.c
> > @@ -94,3 +94,8 @@ void intel_parent_fence_priority_display(struct intel_display *display, struct d
> >  	if (display->parent->fence_priority_display)
> >  		display->parent->fence_priority_display(fence);
> >  }
> > +
> > +bool intel_parent_has_auxccs(struct intel_display *display)
> > +{
> > +	return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
> > index 8f91a6f75c53..f34ee81ed7a1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_parent.h
> > +++ b/drivers/gpu/drm/i915/display/intel_parent.h
> > @@ -33,4 +33,6 @@ bool intel_parent_has_fenced_regions(struct intel_display *display);
> >  
> >  void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
> >  
> > +bool intel_parent_has_auxccs(struct intel_display *display);
> > +
> >  #endif /* __INTEL_PARENT_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 6cd94f400e3f..7e5dce8cfec0 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -22,6 +22,7 @@
> >  #include "intel_fbc.h"
> >  #include "intel_frontbuffer.h"
> >  #include "intel_panic.h"
> > +#include "intel_parent.h"
> >  #include "intel_plane.h"
> >  #include "intel_psr.h"
> >  #include "intel_psr_regs.h"
> > @@ -1602,7 +1603,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
> >  	}
> >  
> >  	/* FLAT CCS doesn't need to program AUX_DIST */
> > -	if (HAS_AUX_CCS(display))
> > +	if (intel_parent_has_auxccs(display))
> 
> This is wrong. This is also used for planar formats on
> pre-icl. I'd just leave it be so that we always write sensible
> o PLANE_AUX_DIST.

And maybe s/HAS_AUX_CCS/HAS_AUX_DIST/ or something?

-- 
Ville Syrjälä
Intel

Re: [PATCH v15 09/10] drm/i915/display: Detect AuxCCS support via display parent interface

[Tvrtko Ursulin]

On 09/12/2025 10:56, Ville Syrjälä wrote:
> On Tue, Dec 09, 2025 at 11:42:35AM +0200, Ville Syrjälä wrote:
>> On Mon, Dec 08, 2025 at 08:17:20PM +0100, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>>
>>> Whether AuxCCS can be properly supported depends on the support both from
>>> the display side and non-display side of the driver.
>>>
>>> Let us therefore allow for the non-display part to be queried via the
>>> display parent interface.
>>>
>>> The new interface replaces the HAS_AUX_CCS macro and we also remove the
>>> FIXME from skl_universal_plane_create since now the xe will not advertise
>>> the AuxCCS caps to start with so they do not need to be removed after
>>> enumeration.
>>>
>>> Also, by removing this build specific FIXME we come a step closer to fully
>>> de-coupling display and non-display.
>>>
>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
>>> References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>> Cc: José Roberto de Souza <jose.souza@intel.com>
>>> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> ---
>>>   drivers/gpu/drm/i915/display/intel_display_device.h |  1 -
>>>   drivers/gpu/drm/i915/display/intel_fb.c             |  3 ++-
>>>   drivers/gpu/drm/i915/display/intel_parent.c         |  5 +++++
>>>   drivers/gpu/drm/i915/display/intel_parent.h         |  2 ++
>>>   drivers/gpu/drm/i915/display/skl_universal_plane.c  |  9 ++-------
>>>   drivers/gpu/drm/i915/i915_driver.c                  | 10 ++++++++++
>>>   include/drm/intel/display_parent_interface.h        |  3 +++
>>>   7 files changed, 24 insertions(+), 9 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>>> index 11c2b2883f35..dc61c6560015 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>>> @@ -149,7 +149,6 @@ struct intel_display_platforms {
>>>   #define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>>>   #define HAS_ASYNC_FLIPS(__display)	(DISPLAY_VER(__display) >= 5)
>>>   #define HAS_AS_SDP(__display)		(DISPLAY_VER(__display) >= 13)
>>> -#define HAS_AUX_CCS(__display)		(IS_DISPLAY_VER(__display, 9, 12) || (__display)->platform.alderlake_p || (__display)->platform.meteorlake)
>>>   #define HAS_BIGJOINER(__display)	(DISPLAY_VER(__display) >= 11 && HAS_DSC(__display))
>>>   #define HAS_CASF(__display)		(DISPLAY_VER(__display) >= 20)
>>>   #define HAS_CDCLK_CRAWL(__display)	(DISPLAY_INFO(__display)->has_cdclk_crawl)
>>> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
>>> index b34b4961fe1c..5b8e02ca2faf 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_fb.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
>>> @@ -21,6 +21,7 @@
>>>   #include "intel_fb_bo.h"
>>>   #include "intel_frontbuffer.h"
>>>   #include "intel_panic.h"
>>> +#include "intel_parent.h"
>>>   #include "intel_plane.h"
>>>   
>>>   #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a))
>>> @@ -558,7 +559,7 @@ static bool plane_has_modifier(struct intel_display *display,
>>>   	 * where supported.
>>>   	 */
>>>   	if (intel_fb_is_ccs_modifier(md->modifier) &&
>>> -	    HAS_AUX_CCS(display) != !!md->ccs.packed_aux_planes)
>>> +	    intel_parent_has_auxccs(display) != !!md->ccs.packed_aux_planes)
>>>   		return false;
>>>   
>>>   	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
>>> diff --git a/drivers/gpu/drm/i915/display/intel_parent.c b/drivers/gpu/drm/i915/display/intel_parent.c
>>> index 2ea310cc3509..7a55def19836 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_parent.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_parent.c
>>> @@ -94,3 +94,8 @@ void intel_parent_fence_priority_display(struct intel_display *display, struct d
>>>   	if (display->parent->fence_priority_display)
>>>   		display->parent->fence_priority_display(fence);
>>>   }
>>> +
>>> +bool intel_parent_has_auxccs(struct intel_display *display)
>>> +{
>>> +	return display->parent->has_auxccs && display->parent->has_auxccs(display->drm);
>>> +}
>>> diff --git a/drivers/gpu/drm/i915/display/intel_parent.h b/drivers/gpu/drm/i915/display/intel_parent.h
>>> index 8f91a6f75c53..f34ee81ed7a1 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_parent.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_parent.h
>>> @@ -33,4 +33,6 @@ bool intel_parent_has_fenced_regions(struct intel_display *display);
>>>   
>>>   void intel_parent_fence_priority_display(struct intel_display *display, struct dma_fence *fence);
>>>   
>>> +bool intel_parent_has_auxccs(struct intel_display *display);
>>> +
>>>   #endif /* __INTEL_PARENT_H__ */
>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> index 6cd94f400e3f..7e5dce8cfec0 100644
>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> @@ -22,6 +22,7 @@
>>>   #include "intel_fbc.h"
>>>   #include "intel_frontbuffer.h"
>>>   #include "intel_panic.h"
>>> +#include "intel_parent.h"
>>>   #include "intel_plane.h"
>>>   #include "intel_psr.h"
>>>   #include "intel_psr_regs.h"
>>> @@ -1602,7 +1603,7 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
>>>   	}
>>>   
>>>   	/* FLAT CCS doesn't need to program AUX_DIST */
>>> -	if (HAS_AUX_CCS(display))
>>> +	if (intel_parent_has_auxccs(display))
>> This is wrong. This is also used for planar formats on
>> pre-icl. I'd just leave it be so that we always write sensible
>> o PLANE_AUX_DIST.
> And maybe s/HAS_AUX_CCS/HAS_AUX_DIST/ or something?

Sure - rename as a separate patch or everything in this one?

Regards,

Tvrtko

[PATCH v15 10/10] drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>

Now that we have implemented all the related missing bits we can enable
the AuxCCS compressed modifiers which were disabled in
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe").

Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:

        [PLANE:32:plane 1A]: type=PRI
                uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=28
                hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000

Display is working fine - no artefacts, no DMAR/PIPE faults.

v2:
 * Adjust patch title. (Rodrigo)

v3:
 * Complete rewrite based on the display parent interface.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> # v2
---
 drivers/gpu/drm/xe/display/xe_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 9d2aa69ea428..807fc93fb6ae 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -534,10 +534,18 @@ static const struct intel_display_irq_interface xe_display_irq_interface = {
 	.synchronize = irq_synchronize,
 };
 
+static bool has_auxccs(struct drm_device *drm)
+{
+	struct xe_device *xe = to_xe_device(drm);
+
+	return xe->info.platform == XE_ALDERLAKE_P;
+}
+
 static const struct intel_display_parent_interface parent = {
 	.hdcp = &xe_display_hdcp_interface,
 	.rpm = &xe_display_rpm_interface,
 	.irq = &xe_display_irq_interface,
+	.has_auxccs = has_auxccs,
 };
 
 /**
-- 
2.52.0

✗ CI.checkpatch: warning for AuxCCS handling and render compression modifiers

[Patchwork]

== Series Details ==

Series: AuxCCS handling and render compression modifiers
URL   : https://patchwork.freedesktop.org/series/158654/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
8f50e69d0ce3656564bbdf8b3e213d61470d463f
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 12c4f5d2f534d2bcaf2f666d45e91c0c774dc60e
Author: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Date:   Mon Dec 8 20:17:21 2025 +0100

    drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P
    
    Now that we have implemented all the related missing bits we can enable
    the AuxCCS compressed modifiers which were disabled in
    cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe").
    
    Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:
    
            [PLANE:32:plane 1A]: type=PRI
                    uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=28
                    hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000
    
    Display is working fine - no artefacts, no DMAR/PIPE faults.
    
    v2:
     * Adjust patch title. (Rodrigo)
    
    v3:
     * Complete rewrite based on the display parent interface.
    
    Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
    References: cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
    Cc: Jani Nikula <jani.nikula@intel.com>
    Cc: José Roberto de Souza <jose.souza@intel.com>
    Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
    Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
    Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> # v2
+ /mt/dim checkpatch ae947e88cadd48481a08b630fc9bbb9ddcbe1340 drm-intel
7bd53b198f72 drm/xe/xelpg: Limit AuxCCS ring buffer programming to Alderlake
-:25: WARNING:TYPO_SPELLING: 'explicity' may be misspelled - perhaps 'explicitly'?
#25: FILE: drivers/gpu/drm/xe/xe_ring_ops.c:292:
+	 * AuxCCS, and we explicity do not want to support it on MTL.
 	                  ^^^^^^^^^

total: 0 errors, 1 warnings, 0 checks, 11 lines checked
3a2bf6444c11 drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
7f4148103291 drm/xe/xelp: Wait for AuxCCS invalidation to complete
49ce5ab510be drm/xe: Export xe_emit_aux_table_inv
ed9544b6e1a8 drm/xe/xelp: Add AuxCCS invalidation to the indirect context workarounds
-:36: WARNING:TYPO_SPELLING: 'explicity' may be misspelled - perhaps 'explicitly'?
#36: FILE: drivers/gpu/drm/xe/xe_hw_engine.h:90:
+	 * AuxCCS, and we explicity do not want to support it on MTL.
 	                  ^^^^^^^^^

total: 0 errors, 1 warnings, 0 checks, 128 lines checked
befd9d29a50f drm/xe: Handle DPT in system memory
a2709d9ba138 drm/xe: Do not use stolen memory for DPT on IGFX and AuxCCS
cce54e63c871 drm/xe/display: Add support for AuxCCS
f4809b604b80 drm/i915/display: Detect AuxCCS support via display parent interface
12c4f5d2f534 drm/xe/xelp: Expose AuxCCS frame buffer modifiers on Alderlake-P
-:12: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#12: 
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe").

-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")'
#12: 
cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe").

total: 1 errors, 1 warnings, 0 checks, 18 lines checked

✓ CI.KUnit: success for AuxCCS handling and render compression modifiers

[Patchwork]

== Series Details ==

Series: AuxCCS handling and render compression modifiers
URL   : https://patchwork.freedesktop.org/series/158654/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[20:27:02] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:27:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:27:36] Starting KUnit Kernel (1/1)...
[20:27:36] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:27:36] ================== guc_buf (11 subtests) ===================
[20:27:36] [PASSED] test_smallest
[20:27:36] [PASSED] test_largest
[20:27:36] [PASSED] test_granular
[20:27:36] [PASSED] test_unique
[20:27:36] [PASSED] test_overlap
[20:27:36] [PASSED] test_reusable
[20:27:36] [PASSED] test_too_big
[20:27:36] [PASSED] test_flush
[20:27:36] [PASSED] test_lookup
[20:27:36] [PASSED] test_data
[20:27:36] [PASSED] test_class
[20:27:36] ===================== [PASSED] guc_buf =====================
[20:27:36] =================== guc_dbm (7 subtests) ===================
[20:27:36] [PASSED] test_empty
[20:27:36] [PASSED] test_default
[20:27:36] ======================== test_size  ========================
[20:27:36] [PASSED] 4
[20:27:36] [PASSED] 8
[20:27:36] [PASSED] 32
[20:27:36] [PASSED] 256
[20:27:36] ==================== [PASSED] test_size ====================
[20:27:36] ======================= test_reuse  ========================
[20:27:36] [PASSED] 4
[20:27:36] [PASSED] 8
[20:27:36] [PASSED] 32
[20:27:36] [PASSED] 256
[20:27:36] =================== [PASSED] test_reuse ====================
[20:27:36] =================== test_range_overlap  ====================
[20:27:36] [PASSED] 4
[20:27:36] [PASSED] 8
[20:27:36] [PASSED] 32
[20:27:36] [PASSED] 256
[20:27:36] =============== [PASSED] test_range_overlap ================
[20:27:36] =================== test_range_compact  ====================
[20:27:36] [PASSED] 4
[20:27:36] [PASSED] 8
[20:27:36] [PASSED] 32
[20:27:36] [PASSED] 256
[20:27:36] =============== [PASSED] test_range_compact ================
[20:27:36] ==================== test_range_spare  =====================
[20:27:36] [PASSED] 4
[20:27:36] [PASSED] 8
[20:27:36] [PASSED] 32
[20:27:36] [PASSED] 256
[20:27:36] ================ [PASSED] test_range_spare =================
[20:27:36] ===================== [PASSED] guc_dbm =====================
[20:27:36] =================== guc_idm (6 subtests) ===================
[20:27:36] [PASSED] bad_init
[20:27:36] [PASSED] no_init
[20:27:36] [PASSED] init_fini
[20:27:36] [PASSED] check_used
[20:27:37] [PASSED] check_quota
[20:27:37] [PASSED] check_all
[20:27:37] ===================== [PASSED] guc_idm =====================
[20:27:37] ================== no_relay (3 subtests) ===================
[20:27:37] [PASSED] xe_drops_guc2pf_if_not_ready
[20:27:37] [PASSED] xe_drops_guc2vf_if_not_ready
[20:27:37] [PASSED] xe_rejects_send_if_not_ready
[20:27:37] ==================== [PASSED] no_relay =====================
[20:27:37] ================== pf_relay (14 subtests) ==================
[20:27:37] [PASSED] pf_rejects_guc2pf_too_short
[20:27:37] [PASSED] pf_rejects_guc2pf_too_long
[20:27:37] [PASSED] pf_rejects_guc2pf_no_payload
[20:27:37] [PASSED] pf_fails_no_payload
[20:27:37] [PASSED] pf_fails_bad_origin
[20:27:37] [PASSED] pf_fails_bad_type
[20:27:37] [PASSED] pf_txn_reports_error
[20:27:37] [PASSED] pf_txn_sends_pf2guc
[20:27:37] [PASSED] pf_sends_pf2guc
[20:27:37] [SKIPPED] pf_loopback_nop
[20:27:37] [SKIPPED] pf_loopback_echo
[20:27:37] [SKIPPED] pf_loopback_fail
[20:27:37] [SKIPPED] pf_loopback_busy
[20:27:37] [SKIPPED] pf_loopback_retry
[20:27:37] ==================== [PASSED] pf_relay =====================
[20:27:37] ================== vf_relay (3 subtests) ===================
[20:27:37] [PASSED] vf_rejects_guc2vf_too_short
[20:27:37] [PASSED] vf_rejects_guc2vf_too_long
[20:27:37] [PASSED] vf_rejects_guc2vf_no_payload
[20:27:37] ==================== [PASSED] vf_relay =====================
[20:27:37] ================ pf_gt_config (6 subtests) =================
[20:27:37] [PASSED] fair_contexts_1vf
[20:27:37] [PASSED] fair_doorbells_1vf
[20:27:37] [PASSED] fair_ggtt_1vf
[20:27:37] ====================== fair_contexts  ======================
[20:27:37] [PASSED] 1 VF
[20:27:37] [PASSED] 2 VFs
[20:27:37] [PASSED] 3 VFs
[20:27:37] [PASSED] 4 VFs
[20:27:37] [PASSED] 5 VFs
[20:27:37] [PASSED] 6 VFs
[20:27:37] [PASSED] 7 VFs
[20:27:37] [PASSED] 8 VFs
[20:27:37] [PASSED] 9 VFs
[20:27:37] [PASSED] 10 VFs
[20:27:37] [PASSED] 11 VFs
[20:27:37] [PASSED] 12 VFs
[20:27:37] [PASSED] 13 VFs
[20:27:37] [PASSED] 14 VFs
[20:27:37] [PASSED] 15 VFs
[20:27:37] [PASSED] 16 VFs
[20:27:37] [PASSED] 17 VFs
[20:27:37] [PASSED] 18 VFs
[20:27:37] [PASSED] 19 VFs
[20:27:37] [PASSED] 20 VFs
[20:27:37] [PASSED] 21 VFs
[20:27:37] [PASSED] 22 VFs
[20:27:37] [PASSED] 23 VFs
[20:27:37] [PASSED] 24 VFs
[20:27:37] [PASSED] 25 VFs
[20:27:37] [PASSED] 26 VFs
[20:27:37] [PASSED] 27 VFs
[20:27:37] [PASSED] 28 VFs
[20:27:37] [PASSED] 29 VFs
[20:27:37] [PASSED] 30 VFs
[20:27:37] [PASSED] 31 VFs
[20:27:37] [PASSED] 32 VFs
[20:27:37] [PASSED] 33 VFs
[20:27:37] [PASSED] 34 VFs
[20:27:37] [PASSED] 35 VFs
[20:27:37] [PASSED] 36 VFs
[20:27:37] [PASSED] 37 VFs
[20:27:37] [PASSED] 38 VFs
[20:27:37] [PASSED] 39 VFs
[20:27:37] [PASSED] 40 VFs
[20:27:37] [PASSED] 41 VFs
[20:27:37] [PASSED] 42 VFs
[20:27:37] [PASSED] 43 VFs
[20:27:37] [PASSED] 44 VFs
[20:27:37] [PASSED] 45 VFs
[20:27:37] [PASSED] 46 VFs
[20:27:37] [PASSED] 47 VFs
[20:27:37] [PASSED] 48 VFs
[20:27:37] [PASSED] 49 VFs
[20:27:37] [PASSED] 50 VFs
[20:27:37] [PASSED] 51 VFs
[20:27:37] [PASSED] 52 VFs
[20:27:37] [PASSED] 53 VFs
[20:27:37] [PASSED] 54 VFs
[20:27:37] [PASSED] 55 VFs
[20:27:37] [PASSED] 56 VFs
[20:27:37] [PASSED] 57 VFs
[20:27:37] [PASSED] 58 VFs
[20:27:37] [PASSED] 59 VFs
[20:27:37] [PASSED] 60 VFs
[20:27:37] [PASSED] 61 VFs
[20:27:37] [PASSED] 62 VFs
[20:27:37] [PASSED] 63 VFs
[20:27:37] ================== [PASSED] fair_contexts ==================
[20:27:37] ===================== fair_doorbells  ======================
[20:27:37] [PASSED] 1 VF
[20:27:37] [PASSED] 2 VFs
[20:27:37] [PASSED] 3 VFs
[20:27:37] [PASSED] 4 VFs
[20:27:37] [PASSED] 5 VFs
[20:27:37] [PASSED] 6 VFs
[20:27:37] [PASSED] 7 VFs
[20:27:37] [PASSED] 8 VFs
[20:27:37] [PASSED] 9 VFs
[20:27:37] [PASSED] 10 VFs
[20:27:37] [PASSED] 11 VFs
[20:27:37] [PASSED] 12 VFs
[20:27:37] [PASSED] 13 VFs
[20:27:37] [PASSED] 14 VFs
[20:27:37] [PASSED] 15 VFs
[20:27:37] [PASSED] 16 VFs
[20:27:37] [PASSED] 17 VFs
[20:27:37] [PASSED] 18 VFs
[20:27:37] [PASSED] 19 VFs
[20:27:37] [PASSED] 20 VFs
[20:27:37] [PASSED] 21 VFs
[20:27:37] [PASSED] 22 VFs
[20:27:37] [PASSED] 23 VFs
[20:27:37] [PASSED] 24 VFs
[20:27:37] [PASSED] 25 VFs
[20:27:37] [PASSED] 26 VFs
[20:27:37] [PASSED] 27 VFs
[20:27:37] [PASSED] 28 VFs
[20:27:37] [PASSED] 29 VFs
[20:27:37] [PASSED] 30 VFs
[20:27:37] [PASSED] 31 VFs
[20:27:37] [PASSED] 32 VFs
[20:27:37] [PASSED] 33 VFs
[20:27:37] [PASSED] 34 VFs
[20:27:37] [PASSED] 35 VFs
[20:27:37] [PASSED] 36 VFs
[20:27:37] [PASSED] 37 VFs
[20:27:37] [PASSED] 38 VFs
[20:27:37] [PASSED] 39 VFs
[20:27:37] [PASSED] 40 VFs
[20:27:37] [PASSED] 41 VFs
[20:27:37] [PASSED] 42 VFs
[20:27:37] [PASSED] 43 VFs
[20:27:37] [PASSED] 44 VFs
[20:27:37] [PASSED] 45 VFs
[20:27:37] [PASSED] 46 VFs
[20:27:37] [PASSED] 47 VFs
[20:27:37] [PASSED] 48 VFs
[20:27:37] [PASSED] 49 VFs
[20:27:37] [PASSED] 50 VFs
[20:27:37] [PASSED] 51 VFs
[20:27:37] [PASSED] 52 VFs
[20:27:37] [PASSED] 53 VFs
[20:27:37] [PASSED] 54 VFs
[20:27:37] [PASSED] 55 VFs
[20:27:37] [PASSED] 56 VFs
[20:27:37] [PASSED] 57 VFs
[20:27:37] [PASSED] 58 VFs
[20:27:37] [PASSED] 59 VFs
[20:27:37] [PASSED] 60 VFs
[20:27:37] [PASSED] 61 VFs
[20:27:37] [PASSED] 62 VFs
[20:27:37] [PASSED] 63 VFs
[20:27:37] ================= [PASSED] fair_doorbells ==================
[20:27:37] ======================== fair_ggtt  ========================
[20:27:37] [PASSED] 1 VF
[20:27:37] [PASSED] 2 VFs
[20:27:37] [PASSED] 3 VFs
[20:27:37] [PASSED] 4 VFs
[20:27:37] [PASSED] 5 VFs
[20:27:37] [PASSED] 6 VFs
[20:27:37] [PASSED] 7 VFs
[20:27:37] [PASSED] 8 VFs
[20:27:37] [PASSED] 9 VFs
[20:27:37] [PASSED] 10 VFs
[20:27:37] [PASSED] 11 VFs
[20:27:37] [PASSED] 12 VFs
[20:27:37] [PASSED] 13 VFs
[20:27:37] [PASSED] 14 VFs
[20:27:37] [PASSED] 15 VFs
[20:27:37] [PASSED] 16 VFs
[20:27:37] [PASSED] 17 VFs
[20:27:37] [PASSED] 18 VFs
[20:27:37] [PASSED] 19 VFs
[20:27:37] [PASSED] 20 VFs
[20:27:37] [PASSED] 21 VFs
[20:27:37] [PASSED] 22 VFs
[20:27:37] [PASSED] 23 VFs
[20:27:37] [PASSED] 24 VFs
[20:27:37] [PASSED] 25 VFs
[20:27:37] [PASSED] 26 VFs
[20:27:37] [PASSED] 27 VFs
[20:27:37] [PASSED] 28 VFs
[20:27:37] [PASSED] 29 VFs
[20:27:37] [PASSED] 30 VFs
[20:27:37] [PASSED] 31 VFs
[20:27:37] [PASSED] 32 VFs
[20:27:37] [PASSED] 33 VFs
[20:27:37] [PASSED] 34 VFs
[20:27:37] [PASSED] 35 VFs
[20:27:37] [PASSED] 36 VFs
[20:27:37] [PASSED] 37 VFs
[20:27:37] [PASSED] 38 VFs
[20:27:37] [PASSED] 39 VFs
[20:27:37] [PASSED] 40 VFs
[20:27:37] [PASSED] 41 VFs
[20:27:37] [PASSED] 42 VFs
[20:27:37] [PASSED] 43 VFs
[20:27:37] [PASSED] 44 VFs
[20:27:37] [PASSED] 45 VFs
[20:27:37] [PASSED] 46 VFs
[20:27:37] [PASSED] 47 VFs
[20:27:37] [PASSED] 48 VFs
[20:27:37] [PASSED] 49 VFs
[20:27:37] [PASSED] 50 VFs
[20:27:37] [PASSED] 51 VFs
[20:27:37] [PASSED] 52 VFs
[20:27:37] [PASSED] 53 VFs
[20:27:37] [PASSED] 54 VFs
[20:27:37] [PASSED] 55 VFs
[20:27:37] [PASSED] 56 VFs
[20:27:37] [PASSED] 57 VFs
[20:27:37] [PASSED] 58 VFs
[20:27:37] [PASSED] 59 VFs
[20:27:37] [PASSED] 60 VFs
[20:27:37] [PASSED] 61 VFs
[20:27:37] [PASSED] 62 VFs
[20:27:37] [PASSED] 63 VFs
[20:27:37] ==================== [PASSED] fair_ggtt ====================
[20:27:37] ================== [PASSED] pf_gt_config ===================
[20:27:37] ===================== lmtt (1 subtest) =====================
[20:27:37] ======================== test_ops  =========================
[20:27:37] [PASSED] 2-level
[20:27:37] [PASSED] multi-level
[20:27:37] ==================== [PASSED] test_ops =====================
[20:27:37] ====================== [PASSED] lmtt =======================
[20:27:37] ================= pf_service (11 subtests) =================
[20:27:37] [PASSED] pf_negotiate_any
[20:27:37] [PASSED] pf_negotiate_base_match
[20:27:37] [PASSED] pf_negotiate_base_newer
[20:27:37] [PASSED] pf_negotiate_base_next
[20:27:37] [SKIPPED] pf_negotiate_base_older
[20:27:37] [PASSED] pf_negotiate_base_prev
[20:27:37] [PASSED] pf_negotiate_latest_match
[20:27:37] [PASSED] pf_negotiate_latest_newer
[20:27:37] [PASSED] pf_negotiate_latest_next
[20:27:37] [SKIPPED] pf_negotiate_latest_older
[20:27:37] [SKIPPED] pf_negotiate_latest_prev
[20:27:37] =================== [PASSED] pf_service ====================
[20:27:37] ================= xe_guc_g2g (2 subtests) ==================
[20:27:37] ============== xe_live_guc_g2g_kunit_default  ==============
[20:27:37] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[20:27:37] ============== xe_live_guc_g2g_kunit_allmem  ===============
[20:27:37] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[20:27:37] =================== [SKIPPED] xe_guc_g2g ===================
[20:27:37] =================== xe_mocs (2 subtests) ===================
[20:27:37] ================ xe_live_mocs_kernel_kunit  ================
[20:27:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[20:27:37] ================ xe_live_mocs_reset_kunit  =================
[20:27:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[20:27:37] ==================== [SKIPPED] xe_mocs =====================
[20:27:37] ================= xe_migrate (2 subtests) ==================
[20:27:37] ================= xe_migrate_sanity_kunit  =================
[20:27:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[20:27:37] ================== xe_validate_ccs_kunit  ==================
[20:27:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[20:27:37] =================== [SKIPPED] xe_migrate ===================
[20:27:37] ================== xe_dma_buf (1 subtest) ==================
[20:27:37] ==================== xe_dma_buf_kunit  =====================
[20:27:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[20:27:37] =================== [SKIPPED] xe_dma_buf ===================
[20:27:37] ================= xe_bo_shrink (1 subtest) =================
[20:27:37] =================== xe_bo_shrink_kunit  ====================
[20:27:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[20:27:37] ================== [SKIPPED] xe_bo_shrink ==================
[20:27:37] ==================== xe_bo (2 subtests) ====================
[20:27:37] ================== xe_ccs_migrate_kunit  ===================
[20:27:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[20:27:37] ==================== xe_bo_evict_kunit  ====================
[20:27:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[20:27:37] ===================== [SKIPPED] xe_bo ======================
[20:27:37] ==================== args (11 subtests) ====================
[20:27:37] [PASSED] count_args_test
[20:27:37] [PASSED] call_args_example
[20:27:37] [PASSED] call_args_test
[20:27:37] [PASSED] drop_first_arg_example
[20:27:37] [PASSED] drop_first_arg_test
[20:27:37] [PASSED] first_arg_example
[20:27:37] [PASSED] first_arg_test
[20:27:37] [PASSED] last_arg_example
[20:27:37] [PASSED] last_arg_test
[20:27:37] [PASSED] pick_arg_example
[20:27:37] [PASSED] sep_comma_example
[20:27:37] ====================== [PASSED] args =======================
[20:27:37] =================== xe_pci (3 subtests) ====================
[20:27:37] ==================== check_graphics_ip  ====================
[20:27:37] [PASSED] 12.00 Xe_LP
[20:27:37] [PASSED] 12.10 Xe_LP+
[20:27:37] [PASSED] 12.55 Xe_HPG
[20:27:37] [PASSED] 12.60 Xe_HPC
[20:27:37] [PASSED] 12.70 Xe_LPG
[20:27:37] [PASSED] 12.71 Xe_LPG
[20:27:37] [PASSED] 12.74 Xe_LPG+
[20:27:37] [PASSED] 20.01 Xe2_HPG
[20:27:37] [PASSED] 20.02 Xe2_HPG
[20:27:37] [PASSED] 20.04 Xe2_LPG
[20:27:37] [PASSED] 30.00 Xe3_LPG
[20:27:37] [PASSED] 30.01 Xe3_LPG
[20:27:37] [PASSED] 30.03 Xe3_LPG
[20:27:37] [PASSED] 30.04 Xe3_LPG
[20:27:37] [PASSED] 30.05 Xe3_LPG
[20:27:37] [PASSED] 35.11 Xe3p_XPC
[20:27:37] ================ [PASSED] check_graphics_ip ================
[20:27:37] ===================== check_media_ip  ======================
[20:27:37] [PASSED] 12.00 Xe_M
[20:27:37] [PASSED] 12.55 Xe_HPM
[20:27:37] [PASSED] 13.00 Xe_LPM+
[20:27:37] [PASSED] 13.01 Xe2_HPM
[20:27:37] [PASSED] 20.00 Xe2_LPM
[20:27:37] [PASSED] 30.00 Xe3_LPM
[20:27:37] [PASSED] 30.02 Xe3_LPM
[20:27:37] [PASSED] 35.00 Xe3p_LPM
[20:27:37] [PASSED] 35.03 Xe3p_HPM
[20:27:37] ================= [PASSED] check_media_ip ==================
[20:27:37] =================== check_platform_desc  ===================
[20:27:37] [PASSED] 0x9A60 (TIGERLAKE)
[20:27:37] [PASSED] 0x9A68 (TIGERLAKE)
[20:27:37] [PASSED] 0x9A70 (TIGERLAKE)
[20:27:37] [PASSED] 0x9A40 (TIGERLAKE)
[20:27:37] [PASSED] 0x9A49 (TIGERLAKE)
[20:27:37] [PASSED] 0x9A59 (TIGERLAKE)
[20:27:37] [PASSED] 0x9A78 (TIGERLAKE)
[20:27:37] [PASSED] 0x9AC0 (TIGERLAKE)
[20:27:37] [PASSED] 0x9AC9 (TIGERLAKE)
[20:27:37] [PASSED] 0x9AD9 (TIGERLAKE)
[20:27:37] [PASSED] 0x9AF8 (TIGERLAKE)
[20:27:37] [PASSED] 0x4C80 (ROCKETLAKE)
[20:27:37] [PASSED] 0x4C8A (ROCKETLAKE)
[20:27:37] [PASSED] 0x4C8B (ROCKETLAKE)
[20:27:37] [PASSED] 0x4C8C (ROCKETLAKE)
[20:27:37] [PASSED] 0x4C90 (ROCKETLAKE)
[20:27:37] [PASSED] 0x4C9A (ROCKETLAKE)
[20:27:37] [PASSED] 0x4680 (ALDERLAKE_S)
[20:27:37] [PASSED] 0x4682 (ALDERLAKE_S)
[20:27:37] [PASSED] 0x4688 (ALDERLAKE_S)
[20:27:37] [PASSED] 0x468A (ALDERLAKE_S)
[20:27:37] [PASSED] 0x468B (ALDERLAKE_S)
[20:27:37] [PASSED] 0x4690 (ALDERLAKE_S)
[20:27:37] [PASSED] 0x4692 (ALDERLAKE_S)
[20:27:37] [PASSED] 0x4693 (ALDERLAKE_S)
[20:27:37] [PASSED] 0x46A0 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46A1 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46A2 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46A3 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46A6 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46A8 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46AA (ALDERLAKE_P)
[20:27:37] [PASSED] 0x462A (ALDERLAKE_P)
[20:27:37] [PASSED] 0x4626 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x4628 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[20:27:37] [PASSED] 0x46B1 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46B2 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46B3 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46C0 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46C1 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46C2 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46C3 (ALDERLAKE_P)
[20:27:37] [PASSED] 0x46D0 (ALDERLAKE_N)
[20:27:37] [PASSED] 0x46D1 (ALDERLAKE_N)
[20:27:37] [PASSED] 0x46D2 (ALDERLAKE_N)
[20:27:37] [PASSED] 0x46D3 (ALDERLAKE_N)
[20:27:37] [PASSED] 0x46D4 (ALDERLAKE_N)
[20:27:37] [PASSED] 0xA721 (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7A1 (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7A9 (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7AC (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7AD (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA720 (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7A0 (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7A8 (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7AA (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA7AB (ALDERLAKE_P)
[20:27:37] [PASSED] 0xA780 (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA781 (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA782 (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA783 (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA788 (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA789 (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA78A (ALDERLAKE_S)
[20:27:37] [PASSED] 0xA78B (ALDERLAKE_S)
[20:27:37] [PASSED] 0x4905 (DG1)
[20:27:37] [PASSED] 0x4906 (DG1)
[20:27:37] [PASSED] 0x4907 (DG1)
[20:27:37] [PASSED] 0x4908 (DG1)
[20:27:37] [PASSED] 0x4909 (DG1)
[20:27:37] [PASSED] 0x56C0 (DG2)
[20:27:37] [PASSED] 0x56C2 (DG2)
[20:27:37] [PASSED] 0x56C1 (DG2)
[20:27:37] [PASSED] 0x7D51 (METEORLAKE)
[20:27:37] [PASSED] 0x7DD1 (METEORLAKE)
[20:27:37] [PASSED] 0x7D41 (METEORLAKE)
[20:27:37] [PASSED] 0x7D67 (METEORLAKE)
[20:27:37] [PASSED] 0xB640 (METEORLAKE)
[20:27:37] [PASSED] 0x56A0 (DG2)
[20:27:37] [PASSED] 0x56A1 (DG2)
[20:27:37] [PASSED] 0x56A2 (DG2)
[20:27:37] [PASSED] 0x56BE (DG2)
[20:27:37] [PASSED] 0x56BF (DG2)
[20:27:37] [PASSED] 0x5690 (DG2)
[20:27:37] [PASSED] 0x5691 (DG2)
[20:27:37] [PASSED] 0x5692 (DG2)
[20:27:37] [PASSED] 0x56A5 (DG2)
[20:27:37] [PASSED] 0x56A6 (DG2)
[20:27:37] [PASSED] 0x56B0 (DG2)
[20:27:37] [PASSED] 0x56B1 (DG2)
[20:27:37] [PASSED] 0x56BA (DG2)
[20:27:37] [PASSED] 0x56BB (DG2)
[20:27:37] [PASSED] 0x56BC (DG2)
[20:27:37] [PASSED] 0x56BD (DG2)
[20:27:37] [PASSED] 0x5693 (DG2)
[20:27:37] [PASSED] 0x5694 (DG2)
[20:27:37] [PASSED] 0x5695 (DG2)
[20:27:37] [PASSED] 0x56A3 (DG2)
[20:27:37] [PASSED] 0x56A4 (DG2)
[20:27:37] [PASSED] 0x56B2 (DG2)
[20:27:37] [PASSED] 0x56B3 (DG2)
[20:27:37] [PASSED] 0x5696 (DG2)
[20:27:37] [PASSED] 0x5697 (DG2)
[20:27:37] [PASSED] 0xB69 (PVC)
[20:27:37] [PASSED] 0xB6E (PVC)
[20:27:37] [PASSED] 0xBD4 (PVC)
[20:27:37] [PASSED] 0xBD5 (PVC)
[20:27:37] [PASSED] 0xBD6 (PVC)
[20:27:37] [PASSED] 0xBD7 (PVC)
[20:27:37] [PASSED] 0xBD8 (PVC)
[20:27:37] [PASSED] 0xBD9 (PVC)
[20:27:37] [PASSED] 0xBDA (PVC)
[20:27:37] [PASSED] 0xBDB (PVC)
[20:27:37] [PASSED] 0xBE0 (PVC)
[20:27:37] [PASSED] 0xBE1 (PVC)
[20:27:37] [PASSED] 0xBE5 (PVC)
[20:27:37] [PASSED] 0x7D40 (METEORLAKE)
[20:27:37] [PASSED] 0x7D45 (METEORLAKE)
[20:27:37] [PASSED] 0x7D55 (METEORLAKE)
[20:27:37] [PASSED] 0x7D60 (METEORLAKE)
[20:27:37] [PASSED] 0x7DD5 (METEORLAKE)
[20:27:37] [PASSED] 0x6420 (LUNARLAKE)
[20:27:37] [PASSED] 0x64A0 (LUNARLAKE)
[20:27:37] [PASSED] 0x64B0 (LUNARLAKE)
[20:27:37] [PASSED] 0xE202 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE209 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE20B (BATTLEMAGE)
[20:27:37] [PASSED] 0xE20C (BATTLEMAGE)
[20:27:37] [PASSED] 0xE20D (BATTLEMAGE)
[20:27:37] [PASSED] 0xE210 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE211 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE212 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE216 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE220 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE221 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE222 (BATTLEMAGE)
[20:27:37] [PASSED] 0xE223 (BATTLEMAGE)
[20:27:37] [PASSED] 0xB080 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB081 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB082 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB083 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB084 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB085 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB086 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB087 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB08F (PANTHERLAKE)
[20:27:37] [PASSED] 0xB090 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB0A0 (PANTHERLAKE)
[20:27:37] [PASSED] 0xB0B0 (PANTHERLAKE)
[20:27:37] [PASSED] 0xD740 (NOVALAKE_S)
[20:27:37] [PASSED] 0xD741 (NOVALAKE_S)
[20:27:37] [PASSED] 0xD742 (NOVALAKE_S)
[20:27:37] [PASSED] 0xD743 (NOVALAKE_S)
[20:27:37] [PASSED] 0xD744 (NOVALAKE_S)
[20:27:37] [PASSED] 0xD745 (NOVALAKE_S)
[20:27:37] [PASSED] 0x674C (CRESCENTISLAND)
[20:27:37] [PASSED] 0xFD80 (PANTHERLAKE)
[20:27:37] [PASSED] 0xFD81 (PANTHERLAKE)
[20:27:37] =============== [PASSED] check_platform_desc ===============
[20:27:37] ===================== [PASSED] xe_pci ======================
[20:27:37] =================== xe_rtp (2 subtests) ====================
[20:27:37] =============== xe_rtp_process_to_sr_tests  ================
[20:27:37] [PASSED] coalesce-same-reg
[20:27:37] [PASSED] no-match-no-add
[20:27:37] [PASSED] match-or
[20:27:37] [PASSED] match-or-xfail
[20:27:37] [PASSED] no-match-no-add-multiple-rules
[20:27:37] [PASSED] two-regs-two-entries
[20:27:37] [PASSED] clr-one-set-other
[20:27:37] [PASSED] set-field
[20:27:37] [PASSED] conflict-duplicate
[20:27:37] [PASSED] conflict-not-disjoint
[20:27:37] [PASSED] conflict-reg-type
[20:27:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[20:27:37] ================== xe_rtp_process_tests  ===================
[20:27:37] [PASSED] active1
[20:27:37] [PASSED] active2
[20:27:37] [PASSED] active-inactive
[20:27:37] [PASSED] inactive-active
[20:27:37] [PASSED] inactive-1st_or_active-inactive
[20:27:37] [PASSED] inactive-2nd_or_active-inactive
[20:27:37] [PASSED] inactive-last_or_active-inactive
[20:27:37] [PASSED] inactive-no_or_active-inactive
[20:27:37] ============== [PASSED] xe_rtp_process_tests ===============
[20:27:37] ===================== [PASSED] xe_rtp ======================
[20:27:37] ==================== xe_wa (1 subtest) =====================
[20:27:37] ======================== xe_wa_gt  =========================
[20:27:37] [PASSED] TIGERLAKE B0
[20:27:37] [PASSED] DG1 A0
[20:27:37] [PASSED] DG1 B0
[20:27:37] [PASSED] ALDERLAKE_S A0
[20:27:37] [PASSED] ALDERLAKE_S B0
[20:27:37] [PASSED] ALDERLAKE_S C0
[20:27:37] [PASSED] ALDERLAKE_S D0
[20:27:37] [PASSED] ALDERLAKE_P A0
[20:27:37] [PASSED] ALDERLAKE_P B0
[20:27:37] [PASSED] ALDERLAKE_P C0
[20:27:37] [PASSED] ALDERLAKE_S RPLS D0
[20:27:37] [PASSED] ALDERLAKE_P RPLU E0
[20:27:37] [PASSED] DG2 G10 C0
[20:27:37] [PASSED] DG2 G11 B1
[20:27:37] [PASSED] DG2 G12 A1
[20:27:37] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:27:37] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[20:27:37] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[20:27:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[20:27:37] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[20:27:37] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[20:27:37] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[20:27:37] ==================== [PASSED] xe_wa_gt =====================
[20:27:37] ====================== [PASSED] xe_wa ======================
[20:27:37] ============================================================
[20:27:37] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[20:27:37] Elapsed time: 35.087s total, 4.231s configuring, 30.380s building, 0.457s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[20:27:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:27:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:28:03] Starting KUnit Kernel (1/1)...
[20:28:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:28:03] ============ drm_test_pick_cmdline (2 subtests) ============
[20:28:03] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[20:28:03] =============== drm_test_pick_cmdline_named  ===============
[20:28:03] [PASSED] NTSC
[20:28:03] [PASSED] NTSC-J
[20:28:03] [PASSED] PAL
[20:28:03] [PASSED] PAL-M
[20:28:03] =========== [PASSED] drm_test_pick_cmdline_named ===========
[20:28:03] ============== [PASSED] drm_test_pick_cmdline ==============
[20:28:03] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[20:28:03] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[20:28:03] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[20:28:03] =========== drm_validate_clone_mode (2 subtests) ===========
[20:28:03] ============== drm_test_check_in_clone_mode  ===============
[20:28:03] [PASSED] in_clone_mode
[20:28:03] [PASSED] not_in_clone_mode
[20:28:03] ========== [PASSED] drm_test_check_in_clone_mode ===========
[20:28:03] =============== drm_test_check_valid_clones  ===============
[20:28:03] [PASSED] not_in_clone_mode
[20:28:03] [PASSED] valid_clone
[20:28:03] [PASSED] invalid_clone
[20:28:03] =========== [PASSED] drm_test_check_valid_clones ===========
[20:28:03] ============= [PASSED] drm_validate_clone_mode =============
[20:28:03] ============= drm_validate_modeset (1 subtest) =============
[20:28:03] [PASSED] drm_test_check_connector_changed_modeset
[20:28:03] ============== [PASSED] drm_validate_modeset ===============
[20:28:03] ====== drm_test_bridge_get_current_state (2 subtests) ======
[20:28:03] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[20:28:03] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[20:28:03] ======== [PASSED] drm_test_bridge_get_current_state ========
[20:28:03] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[20:28:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[20:28:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[20:28:03] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[20:28:03] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[20:28:03] ============== drm_bridge_alloc (2 subtests) ===============
[20:28:03] [PASSED] drm_test_drm_bridge_alloc_basic
[20:28:03] [PASSED] drm_test_drm_bridge_alloc_get_put
[20:28:03] ================ [PASSED] drm_bridge_alloc =================
[20:28:03] ================== drm_buddy (8 subtests) ==================
[20:28:03] [PASSED] drm_test_buddy_alloc_limit
[20:28:03] [PASSED] drm_test_buddy_alloc_optimistic
[20:28:03] [PASSED] drm_test_buddy_alloc_pessimistic
[20:28:03] [PASSED] drm_test_buddy_alloc_pathological
[20:28:03] [PASSED] drm_test_buddy_alloc_contiguous
[20:28:03] [PASSED] drm_test_buddy_alloc_clear
[20:28:03] [PASSED] drm_test_buddy_alloc_range_bias
[20:28:04] [PASSED] drm_test_buddy_fragmentation_performance
[20:28:04] ==================== [PASSED] drm_buddy ====================
[20:28:04] ============= drm_cmdline_parser (40 subtests) =============
[20:28:04] [PASSED] drm_test_cmdline_force_d_only
[20:28:04] [PASSED] drm_test_cmdline_force_D_only_dvi
[20:28:04] [PASSED] drm_test_cmdline_force_D_only_hdmi
[20:28:04] [PASSED] drm_test_cmdline_force_D_only_not_digital
[20:28:04] [PASSED] drm_test_cmdline_force_e_only
[20:28:04] [PASSED] drm_test_cmdline_res
[20:28:04] [PASSED] drm_test_cmdline_res_vesa
[20:28:04] [PASSED] drm_test_cmdline_res_vesa_rblank
[20:28:04] [PASSED] drm_test_cmdline_res_rblank
[20:28:04] [PASSED] drm_test_cmdline_res_bpp
[20:28:04] [PASSED] drm_test_cmdline_res_refresh
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[20:28:04] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[20:28:04] [PASSED] drm_test_cmdline_res_margins_force_on
[20:28:04] [PASSED] drm_test_cmdline_res_vesa_margins
[20:28:04] [PASSED] drm_test_cmdline_name
[20:28:04] [PASSED] drm_test_cmdline_name_bpp
[20:28:04] [PASSED] drm_test_cmdline_name_option
[20:28:04] [PASSED] drm_test_cmdline_name_bpp_option
[20:28:04] [PASSED] drm_test_cmdline_rotate_0
[20:28:04] [PASSED] drm_test_cmdline_rotate_90
[20:28:04] [PASSED] drm_test_cmdline_rotate_180
[20:28:04] [PASSED] drm_test_cmdline_rotate_270
[20:28:04] [PASSED] drm_test_cmdline_hmirror
[20:28:04] [PASSED] drm_test_cmdline_vmirror
[20:28:04] [PASSED] drm_test_cmdline_margin_options
[20:28:04] [PASSED] drm_test_cmdline_multiple_options
[20:28:04] [PASSED] drm_test_cmdline_bpp_extra_and_option
[20:28:04] [PASSED] drm_test_cmdline_extra_and_option
[20:28:04] [PASSED] drm_test_cmdline_freestanding_options
[20:28:04] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[20:28:04] [PASSED] drm_test_cmdline_panel_orientation
[20:28:04] ================ drm_test_cmdline_invalid  =================
[20:28:04] [PASSED] margin_only
[20:28:04] [PASSED] interlace_only
[20:28:04] [PASSED] res_missing_x
[20:28:04] [PASSED] res_missing_y
[20:28:04] [PASSED] res_bad_y
[20:28:04] [PASSED] res_missing_y_bpp
[20:28:04] [PASSED] res_bad_bpp
[20:28:04] [PASSED] res_bad_refresh
[20:28:04] [PASSED] res_bpp_refresh_force_on_off
[20:28:04] [PASSED] res_invalid_mode
[20:28:04] [PASSED] res_bpp_wrong_place_mode
[20:28:04] [PASSED] name_bpp_refresh
[20:28:04] [PASSED] name_refresh
[20:28:04] [PASSED] name_refresh_wrong_mode
[20:28:04] [PASSED] name_refresh_invalid_mode
[20:28:04] [PASSED] rotate_multiple
[20:28:04] [PASSED] rotate_invalid_val
[20:28:04] [PASSED] rotate_truncated
[20:28:04] [PASSED] invalid_option
[20:28:04] [PASSED] invalid_tv_option
[20:28:04] [PASSED] truncated_tv_option
[20:28:04] ============ [PASSED] drm_test_cmdline_invalid =============
[20:28:04] =============== drm_test_cmdline_tv_options  ===============
[20:28:04] [PASSED] NTSC
[20:28:04] [PASSED] NTSC_443
[20:28:04] [PASSED] NTSC_J
[20:28:04] [PASSED] PAL
[20:28:04] [PASSED] PAL_M
[20:28:04] [PASSED] PAL_N
[20:28:04] [PASSED] SECAM
[20:28:04] [PASSED] MONO_525
[20:28:04] [PASSED] MONO_625
[20:28:04] =========== [PASSED] drm_test_cmdline_tv_options ===========
[20:28:04] =============== [PASSED] drm_cmdline_parser ================
[20:28:04] ========== drmm_connector_hdmi_init (20 subtests) ==========
[20:28:04] [PASSED] drm_test_connector_hdmi_init_valid
[20:28:04] [PASSED] drm_test_connector_hdmi_init_bpc_8
[20:28:04] [PASSED] drm_test_connector_hdmi_init_bpc_10
[20:28:04] [PASSED] drm_test_connector_hdmi_init_bpc_12
[20:28:04] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[20:28:04] [PASSED] drm_test_connector_hdmi_init_bpc_null
[20:28:04] [PASSED] drm_test_connector_hdmi_init_formats_empty
[20:28:04] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[20:28:04] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[20:28:04] [PASSED] supported_formats=0x9 yuv420_allowed=1
[20:28:04] [PASSED] supported_formats=0x9 yuv420_allowed=0
[20:28:04] [PASSED] supported_formats=0x3 yuv420_allowed=1
[20:28:04] [PASSED] supported_formats=0x3 yuv420_allowed=0
[20:28:04] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[20:28:04] [PASSED] drm_test_connector_hdmi_init_null_ddc
[20:28:04] [PASSED] drm_test_connector_hdmi_init_null_product
[20:28:04] [PASSED] drm_test_connector_hdmi_init_null_vendor
[20:28:04] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[20:28:04] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[20:28:04] [PASSED] drm_test_connector_hdmi_init_product_valid
[20:28:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[20:28:04] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[20:28:04] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[20:28:04] ========= drm_test_connector_hdmi_init_type_valid  =========
[20:28:04] [PASSED] HDMI-A
[20:28:04] [PASSED] HDMI-B
[20:28:04] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[20:28:04] ======== drm_test_connector_hdmi_init_type_invalid  ========
[20:28:04] [PASSED] Unknown
[20:28:04] [PASSED] VGA
[20:28:04] [PASSED] DVI-I
[20:28:04] [PASSED] DVI-D
[20:28:04] [PASSED] DVI-A
[20:28:04] [PASSED] Composite
[20:28:04] [PASSED] SVIDEO
[20:28:04] [PASSED] LVDS
[20:28:04] [PASSED] Component
[20:28:04] [PASSED] DIN
[20:28:04] [PASSED] DP
[20:28:04] [PASSED] TV
[20:28:04] [PASSED] eDP
[20:28:04] [PASSED] Virtual
[20:28:04] [PASSED] DSI
[20:28:04] [PASSED] DPI
[20:28:04] [PASSED] Writeback
[20:28:04] [PASSED] SPI
[20:28:04] [PASSED] USB
[20:28:04] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[20:28:04] ============ [PASSED] drmm_connector_hdmi_init =============
[20:28:04] ============= drmm_connector_init (3 subtests) =============
[20:28:04] [PASSED] drm_test_drmm_connector_init
[20:28:04] [PASSED] drm_test_drmm_connector_init_null_ddc
[20:28:04] ========= drm_test_drmm_connector_init_type_valid  =========
[20:28:04] [PASSED] Unknown
[20:28:04] [PASSED] VGA
[20:28:04] [PASSED] DVI-I
[20:28:04] [PASSED] DVI-D
[20:28:04] [PASSED] DVI-A
[20:28:04] [PASSED] Composite
[20:28:04] [PASSED] SVIDEO
[20:28:04] [PASSED] LVDS
[20:28:04] [PASSED] Component
[20:28:04] [PASSED] DIN
[20:28:04] [PASSED] DP
[20:28:04] [PASSED] HDMI-A
[20:28:04] [PASSED] HDMI-B
[20:28:04] [PASSED] TV
[20:28:04] [PASSED] eDP
[20:28:04] [PASSED] Virtual
[20:28:04] [PASSED] DSI
[20:28:04] [PASSED] DPI
[20:28:04] [PASSED] Writeback
[20:28:04] [PASSED] SPI
[20:28:04] [PASSED] USB
[20:28:04] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[20:28:04] =============== [PASSED] drmm_connector_init ===============
[20:28:04] ========= drm_connector_dynamic_init (6 subtests) ==========
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_init
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_init_properties
[20:28:04] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[20:28:04] [PASSED] Unknown
[20:28:04] [PASSED] VGA
[20:28:04] [PASSED] DVI-I
[20:28:04] [PASSED] DVI-D
[20:28:04] [PASSED] DVI-A
[20:28:04] [PASSED] Composite
[20:28:04] [PASSED] SVIDEO
[20:28:04] [PASSED] LVDS
[20:28:04] [PASSED] Component
[20:28:04] [PASSED] DIN
[20:28:04] [PASSED] DP
[20:28:04] [PASSED] HDMI-A
[20:28:04] [PASSED] HDMI-B
[20:28:04] [PASSED] TV
[20:28:04] [PASSED] eDP
[20:28:04] [PASSED] Virtual
[20:28:04] [PASSED] DSI
[20:28:04] [PASSED] DPI
[20:28:04] [PASSED] Writeback
[20:28:04] [PASSED] SPI
[20:28:04] [PASSED] USB
[20:28:04] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[20:28:04] ======== drm_test_drm_connector_dynamic_init_name  =========
[20:28:04] [PASSED] Unknown
[20:28:04] [PASSED] VGA
[20:28:04] [PASSED] DVI-I
[20:28:04] [PASSED] DVI-D
[20:28:04] [PASSED] DVI-A
[20:28:04] [PASSED] Composite
[20:28:04] [PASSED] SVIDEO
[20:28:04] [PASSED] LVDS
[20:28:04] [PASSED] Component
[20:28:04] [PASSED] DIN
[20:28:04] [PASSED] DP
[20:28:04] [PASSED] HDMI-A
[20:28:04] [PASSED] HDMI-B
[20:28:04] [PASSED] TV
[20:28:04] [PASSED] eDP
[20:28:04] [PASSED] Virtual
[20:28:04] [PASSED] DSI
[20:28:04] [PASSED] DPI
[20:28:04] [PASSED] Writeback
[20:28:04] [PASSED] SPI
[20:28:04] [PASSED] USB
[20:28:04] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[20:28:04] =========== [PASSED] drm_connector_dynamic_init ============
[20:28:04] ==== drm_connector_dynamic_register_early (4 subtests) =====
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[20:28:04] ====== [PASSED] drm_connector_dynamic_register_early =======
[20:28:04] ======= drm_connector_dynamic_register (7 subtests) ========
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[20:28:04] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[20:28:04] ========= [PASSED] drm_connector_dynamic_register ==========
[20:28:04] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[20:28:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[20:28:04] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[20:28:04] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[20:28:04] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[20:28:04] ========== drm_test_get_tv_mode_from_name_valid  ===========
[20:28:04] [PASSED] NTSC
[20:28:04] [PASSED] NTSC-443
[20:28:04] [PASSED] NTSC-J
[20:28:04] [PASSED] PAL
[20:28:04] [PASSED] PAL-M
[20:28:04] [PASSED] PAL-N
[20:28:04] [PASSED] SECAM
[20:28:04] [PASSED] Mono
[20:28:04] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[20:28:04] [PASSED] drm_test_get_tv_mode_from_name_truncated
[20:28:04] ============ [PASSED] drm_get_tv_mode_from_name ============
[20:28:04] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[20:28:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[20:28:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[20:28:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[20:28:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[20:28:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[20:28:04] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[20:28:04] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[20:28:04] [PASSED] VIC 96
[20:28:04] [PASSED] VIC 97
[20:28:04] [PASSED] VIC 101
[20:28:04] [PASSED] VIC 102
[20:28:04] [PASSED] VIC 106
[20:28:04] [PASSED] VIC 107
[20:28:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[20:28:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[20:28:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[20:28:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[20:28:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[20:28:04] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[20:28:04] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[20:28:04] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[20:28:04] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[20:28:04] [PASSED] Automatic
[20:28:04] [PASSED] Full
[20:28:04] [PASSED] Limited 16:235
[20:28:04] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[20:28:04] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[20:28:04] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[20:28:04] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[20:28:04] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[20:28:04] [PASSED] RGB
[20:28:04] [PASSED] YUV 4:2:0
[20:28:04] [PASSED] YUV 4:2:2
[20:28:04] [PASSED] YUV 4:4:4
[20:28:04] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[20:28:04] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[20:28:04] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[20:28:04] ============= drm_damage_helper (21 subtests) ==============
[20:28:04] [PASSED] drm_test_damage_iter_no_damage
[20:28:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[20:28:04] [PASSED] drm_test_damage_iter_no_damage_src_moved
[20:28:04] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[20:28:04] [PASSED] drm_test_damage_iter_no_damage_not_visible
[20:28:04] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[20:28:04] [PASSED] drm_test_damage_iter_no_damage_no_fb
[20:28:04] [PASSED] drm_test_damage_iter_simple_damage
[20:28:04] [PASSED] drm_test_damage_iter_single_damage
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_outside_src
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_src_moved
[20:28:04] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[20:28:04] [PASSED] drm_test_damage_iter_damage
[20:28:04] [PASSED] drm_test_damage_iter_damage_one_intersect
[20:28:04] [PASSED] drm_test_damage_iter_damage_one_outside
[20:28:04] [PASSED] drm_test_damage_iter_damage_src_moved
[20:28:04] [PASSED] drm_test_damage_iter_damage_not_visible
[20:28:04] ================ [PASSED] drm_damage_helper ================
[20:28:04] ============== drm_dp_mst_helper (3 subtests) ==============
[20:28:04] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[20:28:04] [PASSED] Clock 154000 BPP 30 DSC disabled
[20:28:04] [PASSED] Clock 234000 BPP 30 DSC disabled
[20:28:04] [PASSED] Clock 297000 BPP 24 DSC disabled
[20:28:04] [PASSED] Clock 332880 BPP 24 DSC enabled
[20:28:04] [PASSED] Clock 324540 BPP 24 DSC enabled
[20:28:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[20:28:04] ============== drm_test_dp_mst_calc_pbn_div  ===============
[20:28:04] [PASSED] Link rate 2000000 lane count 4
[20:28:04] [PASSED] Link rate 2000000 lane count 2
[20:28:04] [PASSED] Link rate 2000000 lane count 1
[20:28:04] [PASSED] Link rate 1350000 lane count 4
[20:28:04] [PASSED] Link rate 1350000 lane count 2
[20:28:04] [PASSED] Link rate 1350000 lane count 1
[20:28:04] [PASSED] Link rate 1000000 lane count 4
[20:28:04] [PASSED] Link rate 1000000 lane count 2
[20:28:04] [PASSED] Link rate 1000000 lane count 1
[20:28:04] [PASSED] Link rate 810000 lane count 4
[20:28:04] [PASSED] Link rate 810000 lane count 2
[20:28:04] [PASSED] Link rate 810000 lane count 1
[20:28:04] [PASSED] Link rate 540000 lane count 4
[20:28:04] [PASSED] Link rate 540000 lane count 2
[20:28:04] [PASSED] Link rate 540000 lane count 1
[20:28:04] [PASSED] Link rate 270000 lane count 4
[20:28:04] [PASSED] Link rate 270000 lane count 2
[20:28:04] [PASSED] Link rate 270000 lane count 1
[20:28:04] [PASSED] Link rate 162000 lane count 4
[20:28:04] [PASSED] Link rate 162000 lane count 2
[20:28:04] [PASSED] Link rate 162000 lane count 1
[20:28:04] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[20:28:04] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[20:28:04] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[20:28:04] [PASSED] DP_POWER_UP_PHY with port number
[20:28:04] [PASSED] DP_POWER_DOWN_PHY with port number
[20:28:04] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[20:28:04] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[20:28:04] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[20:28:04] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[20:28:04] [PASSED] DP_QUERY_PAYLOAD with port number
[20:28:04] [PASSED] DP_QUERY_PAYLOAD with VCPI
[20:28:04] [PASSED] DP_REMOTE_DPCD_READ with port number
[20:28:04] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[20:28:04] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[20:28:04] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[20:28:04] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[20:28:04] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[20:28:04] [PASSED] DP_REMOTE_I2C_READ with port number
[20:28:04] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[20:28:04] [PASSED] DP_REMOTE_I2C_READ with transactions array
[20:28:04] [PASSED] DP_REMOTE_I2C_WRITE with port number
[20:28:04] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[20:28:04] [PASSED] DP_REMOTE_I2C_WRITE with data array
[20:28:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[20:28:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[20:28:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[20:28:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[20:28:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[20:28:04] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[20:28:04] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[20:28:04] ================ [PASSED] drm_dp_mst_helper ================
[20:28:04] ================== drm_exec (7 subtests) ===================
[20:28:04] [PASSED] sanitycheck
[20:28:04] [PASSED] test_lock
[20:28:04] [PASSED] test_lock_unlock
[20:28:04] [PASSED] test_duplicates
[20:28:04] [PASSED] test_prepare
[20:28:04] [PASSED] test_prepare_array
[20:28:04] [PASSED] test_multiple_loops
[20:28:04] ==================== [PASSED] drm_exec =====================
[20:28:04] =========== drm_format_helper_test (17 subtests) ===========
[20:28:04] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[20:28:04] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[20:28:04] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[20:28:04] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[20:28:04] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[20:28:04] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[20:28:04] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[20:28:04] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[20:28:04] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[20:28:04] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[20:28:04] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[20:28:04] ============== drm_test_fb_xrgb8888_to_mono  ===============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[20:28:04] ==================== drm_test_fb_swab  =====================
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ================ [PASSED] drm_test_fb_swab =================
[20:28:04] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[20:28:04] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[20:28:04] [PASSED] single_pixel_source_buffer
[20:28:04] [PASSED] single_pixel_clip_rectangle
[20:28:04] [PASSED] well_known_colors
[20:28:04] [PASSED] destination_pitch
[20:28:04] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[20:28:04] ================= drm_test_fb_clip_offset  =================
[20:28:04] [PASSED] pass through
[20:28:04] [PASSED] horizontal offset
[20:28:04] [PASSED] vertical offset
[20:28:04] [PASSED] horizontal and vertical offset
[20:28:04] [PASSED] horizontal offset (custom pitch)
[20:28:04] [PASSED] vertical offset (custom pitch)
[20:28:04] [PASSED] horizontal and vertical offset (custom pitch)
[20:28:04] ============= [PASSED] drm_test_fb_clip_offset =============
[20:28:04] =================== drm_test_fb_memcpy  ====================
[20:28:04] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[20:28:04] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[20:28:04] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[20:28:04] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[20:28:04] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[20:28:04] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[20:28:04] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[20:28:04] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[20:28:04] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[20:28:04] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[20:28:04] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[20:28:04] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[20:28:04] =============== [PASSED] drm_test_fb_memcpy ================
[20:28:04] ============= [PASSED] drm_format_helper_test ==============
[20:28:04] ================= drm_format (18 subtests) =================
[20:28:04] [PASSED] drm_test_format_block_width_invalid
[20:28:04] [PASSED] drm_test_format_block_width_one_plane
[20:28:04] [PASSED] drm_test_format_block_width_two_plane
[20:28:04] [PASSED] drm_test_format_block_width_three_plane
[20:28:04] [PASSED] drm_test_format_block_width_tiled
[20:28:04] [PASSED] drm_test_format_block_height_invalid
[20:28:04] [PASSED] drm_test_format_block_height_one_plane
[20:28:04] [PASSED] drm_test_format_block_height_two_plane
[20:28:04] [PASSED] drm_test_format_block_height_three_plane
[20:28:04] [PASSED] drm_test_format_block_height_tiled
[20:28:04] [PASSED] drm_test_format_min_pitch_invalid
[20:28:04] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[20:28:04] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[20:28:04] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[20:28:04] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[20:28:04] [PASSED] drm_test_format_min_pitch_two_plane
[20:28:04] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[20:28:04] [PASSED] drm_test_format_min_pitch_tiled
[20:28:04] =================== [PASSED] drm_format ====================
[20:28:04] ============== drm_framebuffer (10 subtests) ===============
[20:28:04] ========== drm_test_framebuffer_check_src_coords  ==========
[20:28:04] [PASSED] Success: source fits into fb
[20:28:04] [PASSED] Fail: overflowing fb with x-axis coordinate
[20:28:04] [PASSED] Fail: overflowing fb with y-axis coordinate
[20:28:04] [PASSED] Fail: overflowing fb with source width
[20:28:04] [PASSED] Fail: overflowing fb with source height
[20:28:04] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[20:28:04] [PASSED] drm_test_framebuffer_cleanup
[20:28:04] =============== drm_test_framebuffer_create  ===============
[20:28:04] [PASSED] ABGR8888 normal sizes
[20:28:04] [PASSED] ABGR8888 max sizes
[20:28:04] [PASSED] ABGR8888 pitch greater than min required
[20:28:04] [PASSED] ABGR8888 pitch less than min required
[20:28:04] [PASSED] ABGR8888 Invalid width
[20:28:04] [PASSED] ABGR8888 Invalid buffer handle
[20:28:04] [PASSED] No pixel format
[20:28:04] [PASSED] ABGR8888 Width 0
[20:28:04] [PASSED] ABGR8888 Height 0
[20:28:04] [PASSED] ABGR8888 Out of bound height * pitch combination
[20:28:04] [PASSED] ABGR8888 Large buffer offset
[20:28:04] [PASSED] ABGR8888 Buffer offset for inexistent plane
[20:28:04] [PASSED] ABGR8888 Invalid flag
[20:28:04] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[20:28:04] [PASSED] ABGR8888 Valid buffer modifier
[20:28:04] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[20:28:04] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] NV12 Normal sizes
[20:28:04] [PASSED] NV12 Max sizes
[20:28:04] [PASSED] NV12 Invalid pitch
[20:28:04] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[20:28:04] [PASSED] NV12 different  modifier per-plane
[20:28:04] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[20:28:04] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] NV12 Modifier for inexistent plane
[20:28:04] [PASSED] NV12 Handle for inexistent plane
[20:28:04] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[20:28:04] [PASSED] YVU420 Normal sizes
[20:28:04] [PASSED] YVU420 Max sizes
[20:28:04] [PASSED] YVU420 Invalid pitch
[20:28:04] [PASSED] YVU420 Different pitches
[20:28:04] [PASSED] YVU420 Different buffer offsets/pitches
[20:28:04] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[20:28:04] [PASSED] YVU420 Valid modifier
[20:28:04] [PASSED] YVU420 Different modifiers per plane
[20:28:04] [PASSED] YVU420 Modifier for inexistent plane
[20:28:04] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[20:28:04] [PASSED] X0L2 Normal sizes
[20:28:04] [PASSED] X0L2 Max sizes
[20:28:04] [PASSED] X0L2 Invalid pitch
[20:28:04] [PASSED] X0L2 Pitch greater than minimum required
[20:28:04] [PASSED] X0L2 Handle for inexistent plane
[20:28:04] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[20:28:04] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[20:28:04] [PASSED] X0L2 Valid modifier
[20:28:04] [PASSED] X0L2 Modifier for inexistent plane
[20:28:04] =========== [PASSED] drm_test_framebuffer_create ===========
[20:28:04] [PASSED] drm_test_framebuffer_free
[20:28:04] [PASSED] drm_test_framebuffer_init
[20:28:04] [PASSED] drm_test_framebuffer_init_bad_format
[20:28:04] [PASSED] drm_test_framebuffer_init_dev_mismatch
[20:28:04] [PASSED] drm_test_framebuffer_lookup
[20:28:04] [PASSED] drm_test_framebuffer_lookup_inexistent
[20:28:04] [PASSED] drm_test_framebuffer_modifiers_not_supported
[20:28:04] ================= [PASSED] drm_framebuffer =================
[20:28:04] ================ drm_gem_shmem (8 subtests) ================
[20:28:04] [PASSED] drm_gem_shmem_test_obj_create
[20:28:04] [PASSED] drm_gem_shmem_test_obj_create_private
[20:28:04] [PASSED] drm_gem_shmem_test_pin_pages
[20:28:04] [PASSED] drm_gem_shmem_test_vmap
[20:28:04] [PASSED] drm_gem_shmem_test_get_pages_sgt
[20:28:04] [PASSED] drm_gem_shmem_test_get_sg_table
[20:28:04] [PASSED] drm_gem_shmem_test_madvise
[20:28:04] [PASSED] drm_gem_shmem_test_purge
[20:28:04] ================== [PASSED] drm_gem_shmem ==================
[20:28:04] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[20:28:04] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[20:28:04] [PASSED] Automatic
[20:28:04] [PASSED] Full
[20:28:04] [PASSED] Limited 16:235
[20:28:04] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[20:28:04] [PASSED] drm_test_check_disable_connector
[20:28:04] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[20:28:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[20:28:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[20:28:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[20:28:04] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[20:28:04] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[20:28:04] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[20:28:04] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[20:28:04] [PASSED] drm_test_check_output_bpc_dvi
[20:28:04] [PASSED] drm_test_check_output_bpc_format_vic_1
[20:28:04] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[20:28:04] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[20:28:04] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[20:28:04] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[20:28:04] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[20:28:04] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[20:28:04] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[20:28:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[20:28:04] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[20:28:04] [PASSED] drm_test_check_broadcast_rgb_value
[20:28:04] [PASSED] drm_test_check_bpc_8_value
[20:28:04] [PASSED] drm_test_check_bpc_10_value
[20:28:04] [PASSED] drm_test_check_bpc_12_value
[20:28:04] [PASSED] drm_test_check_format_value
[20:28:04] [PASSED] drm_test_check_tmds_char_value
[20:28:04] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[20:28:04] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[20:28:04] [PASSED] drm_test_check_mode_valid
[20:28:04] [PASSED] drm_test_check_mode_valid_reject
[20:28:04] [PASSED] drm_test_check_mode_valid_reject_rate
[20:28:04] [PASSED] drm_test_check_mode_valid_reject_max_clock
[20:28:04] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[20:28:04] ================= drm_managed (2 subtests) =================
[20:28:04] [PASSED] drm_test_managed_release_action
[20:28:04] [PASSED] drm_test_managed_run_action
[20:28:04] =================== [PASSED] drm_managed ===================
[20:28:04] =================== drm_mm (6 subtests) ====================
[20:28:04] [PASSED] drm_test_mm_init
[20:28:04] [PASSED] drm_test_mm_debug
[20:28:04] [PASSED] drm_test_mm_align32
[20:28:04] [PASSED] drm_test_mm_align64
[20:28:04] [PASSED] drm_test_mm_lowest
[20:28:04] [PASSED] drm_test_mm_highest
[20:28:04] ===================== [PASSED] drm_mm ======================
[20:28:04] ============= drm_modes_analog_tv (5 subtests) =============
[20:28:04] [PASSED] drm_test_modes_analog_tv_mono_576i
[20:28:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[20:28:04] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[20:28:04] [PASSED] drm_test_modes_analog_tv_pal_576i
[20:28:04] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[20:28:04] =============== [PASSED] drm_modes_analog_tv ===============
[20:28:04] ============== drm_plane_helper (2 subtests) ===============
[20:28:04] =============== drm_test_check_plane_state  ================
[20:28:04] [PASSED] clipping_simple
[20:28:04] [PASSED] clipping_rotate_reflect
[20:28:04] [PASSED] positioning_simple
[20:28:04] [PASSED] upscaling
[20:28:04] [PASSED] downscaling
[20:28:04] [PASSED] rounding1
[20:28:04] [PASSED] rounding2
[20:28:04] [PASSED] rounding3
[20:28:04] [PASSED] rounding4
[20:28:04] =========== [PASSED] drm_test_check_plane_state ============
[20:28:04] =========== drm_test_check_invalid_plane_state  ============
[20:28:04] [PASSED] positioning_invalid
[20:28:04] [PASSED] upscaling_invalid
[20:28:04] [PASSED] downscaling_invalid
[20:28:04] ======= [PASSED] drm_test_check_invalid_plane_state ========
[20:28:04] ================ [PASSED] drm_plane_helper =================
[20:28:04] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[20:28:04] ====== drm_test_connector_helper_tv_get_modes_check  =======
[20:28:04] [PASSED] None
[20:28:04] [PASSED] PAL
[20:28:04] [PASSED] NTSC
[20:28:04] [PASSED] Both, NTSC Default
[20:28:04] [PASSED] Both, PAL Default
[20:28:04] [PASSED] Both, NTSC Default, with PAL on command-line
[20:28:04] [PASSED] Both, PAL Default, with NTSC on command-line
[20:28:04] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[20:28:04] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[20:28:04] ================== drm_rect (9 subtests) ===================
[20:28:04] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[20:28:04] [PASSED] drm_test_rect_clip_scaled_not_clipped
[20:28:04] [PASSED] drm_test_rect_clip_scaled_clipped
[20:28:04] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[20:28:04] ================= drm_test_rect_intersect  =================
[20:28:04] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[20:28:04] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[20:28:04] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[20:28:04] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[20:28:04] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[20:28:04] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[20:28:04] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[20:28:04] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[20:28:04] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[20:28:04] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[20:28:04] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[20:28:04] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[20:28:04] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[20:28:04] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[20:28:04] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[20:28:04] ============= [PASSED] drm_test_rect_intersect =============
[20:28:04] ================ drm_test_rect_calc_hscale  ================
[20:28:04] [PASSED] normal use
[20:28:04] [PASSED] out of max range
[20:28:04] [PASSED] out of min range
[20:28:04] [PASSED] zero dst
[20:28:04] [PASSED] negative src
[20:28:04] [PASSED] negative dst
[20:28:04] ============ [PASSED] drm_test_rect_calc_hscale ============
[20:28:04] ================ drm_test_rect_calc_vscale  ================
[20:28:04] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[20:28:04] [PASSED] out of max range
[20:28:04] [PASSED] out of min range
[20:28:04] [PASSED] zero dst
[20:28:04] [PASSED] negative src
[20:28:04] [PASSED] negative dst
[20:28:04] ============ [PASSED] drm_test_rect_calc_vscale ============
[20:28:04] ================== drm_test_rect_rotate  ===================
[20:28:04] [PASSED] reflect-x
[20:28:04] [PASSED] reflect-y
[20:28:04] [PASSED] rotate-0
[20:28:04] [PASSED] rotate-90
[20:28:04] [PASSED] rotate-180
[20:28:04] [PASSED] rotate-270
[20:28:04] ============== [PASSED] drm_test_rect_rotate ===============
[20:28:04] ================ drm_test_rect_rotate_inv  =================
[20:28:04] [PASSED] reflect-x
[20:28:04] [PASSED] reflect-y
[20:28:04] [PASSED] rotate-0
[20:28:04] [PASSED] rotate-90
[20:28:04] [PASSED] rotate-180
[20:28:04] [PASSED] rotate-270
[20:28:04] ============ [PASSED] drm_test_rect_rotate_inv =============
[20:28:04] ==================== [PASSED] drm_rect =====================
[20:28:04] ============ drm_sysfb_modeset_test (1 subtest) ============
[20:28:04] ============ drm_test_sysfb_build_fourcc_list  =============
[20:28:04] [PASSED] no native formats
[20:28:04] [PASSED] XRGB8888 as native format
[20:28:04] [PASSED] remove duplicates
[20:28:04] [PASSED] convert alpha formats
[20:28:04] [PASSED] random formats
[20:28:04] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[20:28:04] ============= [PASSED] drm_sysfb_modeset_test ==============
[20:28:04] ================== drm_fixp (2 subtests) ===================
[20:28:04] [PASSED] drm_test_int2fixp
[20:28:04] [PASSED] drm_test_sm2fixp
[20:28:04] ==================== [PASSED] drm_fixp =====================
[20:28:04] ============================================================
[20:28:04] Testing complete. Ran 624 tests: passed: 624
[20:28:04] Elapsed time: 26.829s total, 1.691s configuring, 24.717s building, 0.400s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[20:28:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[20:28:05] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[20:28:15] Starting KUnit Kernel (1/1)...
[20:28:15] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[20:28:15] ================= ttm_device (5 subtests) ==================
[20:28:15] [PASSED] ttm_device_init_basic
[20:28:15] [PASSED] ttm_device_init_multiple
[20:28:15] [PASSED] ttm_device_fini_basic
[20:28:15] [PASSED] ttm_device_init_no_vma_man
[20:28:15] ================== ttm_device_init_pools  ==================
[20:28:15] [PASSED] No DMA allocations, no DMA32 required
[20:28:15] [PASSED] DMA allocations, DMA32 required
[20:28:15] [PASSED] No DMA allocations, DMA32 required
[20:28:15] [PASSED] DMA allocations, no DMA32 required
[20:28:15] ============== [PASSED] ttm_device_init_pools ==============
[20:28:15] =================== [PASSED] ttm_device ====================
[20:28:15] ================== ttm_pool (8 subtests) ===================
[20:28:15] ================== ttm_pool_alloc_basic  ===================
[20:28:15] [PASSED] One page
[20:28:15] [PASSED] More than one page
[20:28:15] [PASSED] Above the allocation limit
[20:28:15] [PASSED] One page, with coherent DMA mappings enabled
[20:28:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:28:15] ============== [PASSED] ttm_pool_alloc_basic ===============
[20:28:15] ============== ttm_pool_alloc_basic_dma_addr  ==============
[20:28:15] [PASSED] One page
[20:28:15] [PASSED] More than one page
[20:28:15] [PASSED] Above the allocation limit
[20:28:15] [PASSED] One page, with coherent DMA mappings enabled
[20:28:15] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[20:28:15] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[20:28:15] [PASSED] ttm_pool_alloc_order_caching_match
[20:28:15] [PASSED] ttm_pool_alloc_caching_mismatch
[20:28:15] [PASSED] ttm_pool_alloc_order_mismatch
[20:28:15] [PASSED] ttm_pool_free_dma_alloc
[20:28:15] [PASSED] ttm_pool_free_no_dma_alloc
[20:28:15] [PASSED] ttm_pool_fini_basic
[20:28:15] ==================== [PASSED] ttm_pool =====================
[20:28:15] ================ ttm_resource (8 subtests) =================
[20:28:15] ================= ttm_resource_init_basic  =================
[20:28:15] [PASSED] Init resource in TTM_PL_SYSTEM
[20:28:15] [PASSED] Init resource in TTM_PL_VRAM
[20:28:15] [PASSED] Init resource in a private placement
[20:28:15] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[20:28:15] ============= [PASSED] ttm_resource_init_basic =============
[20:28:15] [PASSED] ttm_resource_init_pinned
[20:28:15] [PASSED] ttm_resource_fini_basic
[20:28:15] [PASSED] ttm_resource_manager_init_basic
[20:28:15] [PASSED] ttm_resource_manager_usage_basic
[20:28:15] [PASSED] ttm_resource_manager_set_used_basic
[20:28:15] [PASSED] ttm_sys_man_alloc_basic
[20:28:15] [PASSED] ttm_sys_man_free_basic
[20:28:15] ================== [PASSED] ttm_resource ===================
[20:28:15] =================== ttm_tt (15 subtests) ===================
[20:28:15] ==================== ttm_tt_init_basic  ====================
[20:28:15] [PASSED] Page-aligned size
[20:28:15] [PASSED] Extra pages requested
[20:28:15] ================ [PASSED] ttm_tt_init_basic ================
[20:28:15] [PASSED] ttm_tt_init_misaligned
[20:28:15] [PASSED] ttm_tt_fini_basic
[20:28:15] [PASSED] ttm_tt_fini_sg
[20:28:15] [PASSED] ttm_tt_fini_shmem
[20:28:15] [PASSED] ttm_tt_create_basic
[20:28:15] [PASSED] ttm_tt_create_invalid_bo_type
[20:28:15] [PASSED] ttm_tt_create_ttm_exists
[20:28:15] [PASSED] ttm_tt_create_failed
[20:28:15] [PASSED] ttm_tt_destroy_basic
[20:28:15] [PASSED] ttm_tt_populate_null_ttm
[20:28:15] [PASSED] ttm_tt_populate_populated_ttm
[20:28:15] [PASSED] ttm_tt_unpopulate_basic
[20:28:15] [PASSED] ttm_tt_unpopulate_empty_ttm
[20:28:15] [PASSED] ttm_tt_swapin_basic
[20:28:15] ===================== [PASSED] ttm_tt ======================
[20:28:15] =================== ttm_bo (14 subtests) ===================
[20:28:15] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[20:28:15] [PASSED] Cannot be interrupted and sleeps
[20:28:15] [PASSED] Cannot be interrupted, locks straight away
[20:28:15] [PASSED] Can be interrupted, sleeps
[20:28:15] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[20:28:15] [PASSED] ttm_bo_reserve_locked_no_sleep
[20:28:15] [PASSED] ttm_bo_reserve_no_wait_ticket
[20:28:15] [PASSED] ttm_bo_reserve_double_resv
[20:28:15] [PASSED] ttm_bo_reserve_interrupted
[20:28:15] [PASSED] ttm_bo_reserve_deadlock
[20:28:15] [PASSED] ttm_bo_unreserve_basic
[20:28:15] [PASSED] ttm_bo_unreserve_pinned
[20:28:15] [PASSED] ttm_bo_unreserve_bulk
[20:28:15] [PASSED] ttm_bo_fini_basic
[20:28:15] [PASSED] ttm_bo_fini_shared_resv
[20:28:15] [PASSED] ttm_bo_pin_basic
[20:28:15] [PASSED] ttm_bo_pin_unpin_resource
[20:28:15] [PASSED] ttm_bo_multiple_pin_one_unpin
[20:28:15] ===================== [PASSED] ttm_bo ======================
[20:28:15] ============== ttm_bo_validate (21 subtests) ===============
[20:28:15] ============== ttm_bo_init_reserved_sys_man  ===============
[20:28:15] [PASSED] Buffer object for userspace
[20:28:15] [PASSED] Kernel buffer object
[20:28:15] [PASSED] Shared buffer object
[20:28:15] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[20:28:15] ============== ttm_bo_init_reserved_mock_man  ==============
[20:28:15] [PASSED] Buffer object for userspace
[20:28:15] [PASSED] Kernel buffer object
[20:28:15] [PASSED] Shared buffer object
[20:28:15] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[20:28:15] [PASSED] ttm_bo_init_reserved_resv
[20:28:15] ================== ttm_bo_validate_basic  ==================
[20:28:15] [PASSED] Buffer object for userspace
[20:28:15] [PASSED] Kernel buffer object
[20:28:15] [PASSED] Shared buffer object
[20:28:15] ============== [PASSED] ttm_bo_validate_basic ==============
[20:28:15] [PASSED] ttm_bo_validate_invalid_placement
[20:28:15] ============= ttm_bo_validate_same_placement  ==============
[20:28:15] [PASSED] System manager
[20:28:15] [PASSED] VRAM manager
[20:28:15] ========= [PASSED] ttm_bo_validate_same_placement ==========
[20:28:15] [PASSED] ttm_bo_validate_failed_alloc
[20:28:15] [PASSED] ttm_bo_validate_pinned
[20:28:15] [PASSED] ttm_bo_validate_busy_placement
[20:28:15] ================ ttm_bo_validate_multihop  =================
[20:28:15] [PASSED] Buffer object for userspace
[20:28:15] [PASSED] Kernel buffer object
[20:28:15] [PASSED] Shared buffer object
[20:28:15] ============ [PASSED] ttm_bo_validate_multihop =============
[20:28:15] ========== ttm_bo_validate_no_placement_signaled  ==========
[20:28:15] [PASSED] Buffer object in system domain, no page vector
[20:28:15] [PASSED] Buffer object in system domain with an existing page vector
[20:28:15] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[20:28:15] ======== ttm_bo_validate_no_placement_not_signaled  ========
[20:28:15] [PASSED] Buffer object for userspace
[20:28:15] [PASSED] Kernel buffer object
[20:28:15] [PASSED] Shared buffer object
[20:28:15] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[20:28:15] [PASSED] ttm_bo_validate_move_fence_signaled
[20:28:15] ========= ttm_bo_validate_move_fence_not_signaled  =========
[20:28:15] [PASSED] Waits for GPU
[20:28:15] [PASSED] Tries to lock straight away
[20:28:15] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[20:28:15] [PASSED] ttm_bo_validate_happy_evict
[20:28:15] [PASSED] ttm_bo_validate_all_pinned_evict
[20:28:15] [PASSED] ttm_bo_validate_allowed_only_evict
[20:28:15] [PASSED] ttm_bo_validate_deleted_evict
[20:28:15] [PASSED] ttm_bo_validate_busy_domain_evict
[20:28:15] [PASSED] ttm_bo_validate_evict_gutting
[20:28:15] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[20:28:15] ================= [PASSED] ttm_bo_validate =================
[20:28:15] ============================================================
[20:28:15] Testing complete. Ran 101 tests: passed: 101
[20:28:15] Elapsed time: 11.173s total, 1.680s configuring, 9.276s building, 0.178s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for AuxCCS handling and render compression modifiers

[Patchwork]

== Series Details ==

Series: AuxCCS handling and render compression modifiers
URL   : https://patchwork.freedesktop.org/series/158654/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast ae947e88cadd48481a08b630fc9bbb9ddcbe1340
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_casf.c:147:21: error: too long token expansion
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2101:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2114:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2114:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2114:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_lt_phy.c:1935:39: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:467:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:475:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:480:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:518:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:526:16: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:531:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:575:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:578:15: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:582:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/i915_irq.c:589:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1932:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1933:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1999:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2000:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2021:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2022:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for AuxCCS handling and render compression modifiers

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1413 bytes --]

== Series Details ==

Series: AuxCCS handling and render compression modifiers
URL   : https://patchwork.freedesktop.org/series/158654/
State : success

== Summary ==

CI Bug Log - changes from xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343_BAT -> xe-pw-158654v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-158654v1_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-dg2-oem2:       [FAIL][1] ([Intel XE#6519]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/bat-dg2-oem2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/bat-dg2-oem2/igt@xe_waitfence@engine.html

  
  [Intel XE#6519]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6519


Build changes
-------------

  * Linux: xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343 -> xe-pw-158654v1

  IGT_8659: 8659
  xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343: 97efabfcf7e97d1b34327b2fbbc2050a6b77e343
  xe-pw-158654v1: 158654v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/index.html

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✗ Xe.CI.Full: failure for AuxCCS handling and render compression modifiers

[Patchwork]

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== Series Details ==

Series: AuxCCS handling and render compression modifiers
URL   : https://patchwork.freedesktop.org/series/158654/
State : failure

== Summary ==

CI Bug Log - changes from xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343_FULL -> xe-pw-158654v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-158654v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-158654v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-158654v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_dp_link_training@non-uhbr-sst.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html

  
New tests
---------

  New tests have been introduced between xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343_FULL and xe-pw-158654v1_FULL:

### New IGT tests (44) ###

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-linear-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-x-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-mc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-mc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-mc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-mc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-rc-ccs-cc-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-rc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-y-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-linear-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-mc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-mc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.23] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-mc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-mc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-rc-ccs-cc-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-rc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-linear-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-mc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-mc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.24] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-mc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-mc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-rc-ccs-cc-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-rc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-linear-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-mc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-mc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.26] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-mc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-mc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-rc-ccs-cc-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-rc-ccs-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.12] s

  

Known issues
------------

  Here are the changes found in xe-pw-158654v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-dg2-set2:     NOTRUN -> [SKIP][4] ([Intel XE#316]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#1124]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#1124]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#367])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-bmg:          [PASS][8] -> [SKIP][9] ([Intel XE#367])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#367])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][12] ([Intel XE#787]) +27 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2887]) +3 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#3442])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#3432])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_cdclk@mode-transition@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][16] ([Intel XE#4417]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-dg2-set2:     NOTRUN -> [SKIP][17] ([Intel XE#306])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-dg2-set2:     NOTRUN -> [SKIP][18] ([Intel XE#373]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-fast:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#2252]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_chamelium_hpd@hdmi-hpd-fast.html

  * igt@kms_colorop@plane-xr24-xr24-bt2020_oetf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][20] ([Intel XE#6704])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_colorop@plane-xr24-xr24-bt2020_oetf.html

  * igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#6704])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_overdrive.html

  * igt@kms_content_protection@suspend-resume@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [FAIL][22] ([Intel XE#1178]) +1 other test fail
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_content_protection@suspend-resume@pipe-a-dp-4.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#308])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2320]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][25] -> [FAIL][26] ([Intel XE#5299])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#1508])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-8/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1340])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][29] ([Intel XE#776])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][30] ([Intel XE#1137])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][31] -> [FAIL][32] ([Intel XE#301]) +1 other test fail
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [PASS][33] -> [FAIL][34] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1:
    - shard-adlp:         [PASS][35] -> [DMESG-WARN][36] ([Intel XE#6766])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@kms_flip@flip-vs-suspend-interruptible@d-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2293] / [Intel XE#2380])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2293]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][39] ([Intel XE#651]) +8 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#4141]) +4 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2311]) +3 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][42] ([Intel XE#6312]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][43] ([Intel XE#653]) +8 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#2313]) +8 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg2-set2:     NOTRUN -> [SKIP][45] ([Intel XE#455]) +2 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-set2:     [PASS][46] -> [SKIP][47] ([Intel XE#455])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-463/igt@kms_hdr@invalid-hdr.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-436/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#4090] / [Intel XE#6590])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers:
    - shard-adlp:         [PASS][49] -> [DMESG-WARN][50] ([Intel XE#2953] / [Intel XE#4173]) +2 other tests dmesg-warn
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-2/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - shard-dg2-set2:     [PASS][51] -> [FAIL][52] ([Intel XE#4741])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-432/igt@kms_pm_rpm@basic-pci-d3-state.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-bmg:          NOTRUN -> [SKIP][54] ([Intel XE#1406] / [Intel XE#1489])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][55] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-bmg:          NOTRUN -> [SKIP][56] ([Intel XE#1406] / [Intel XE#2387])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-pr-primary-render:
    - shard-bmg:          NOTRUN -> [SKIP][57] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_psr@fbc-pr-primary-render.html

  * igt@kms_psr@fbc-psr-sprite-plane-onoff:
    - shard-dg2-set2:     NOTRUN -> [SKIP][58] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_psr@fbc-psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#3414] / [Intel XE#3904])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-set2:     NOTRUN -> [FAIL][60] ([Intel XE#1729])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@kms_tiled_display@basic-test-pattern.html

  * igt@testdisplay:
    - shard-bmg:          [PASS][61] -> [ABORT][62] ([Intel XE#6740])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-6/igt@testdisplay.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-5/igt@testdisplay.html

  * igt@xe_create@multigpu-create-massive-size:
    - shard-bmg:          NOTRUN -> [SKIP][63] ([Intel XE#2504])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_create@multigpu-create-massive-size.html

  * igt@xe_eu_stall@invalid-gt-id:
    - shard-dg2-set2:     NOTRUN -> [SKIP][64] ([Intel XE#5626])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@xe_eu_stall@invalid-gt-id.html

  * igt@xe_eudebug@basic-exec-queues:
    - shard-dg2-set2:     NOTRUN -> [SKIP][65] ([Intel XE#4837]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@xe_eudebug@basic-exec-queues.html

  * igt@xe_eudebug@sysfs-toggle:
    - shard-bmg:          NOTRUN -> [SKIP][66] ([Intel XE#4837]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_eudebug@sysfs-toggle.html

  * igt@xe_eudebug_online@single-step-one:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#4837] / [Intel XE#6665])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@xe_eudebug_online@single-step-one.html

  * igt@xe_eudebug_sriov@deny-sriov:
    - shard-dg2-set2:     NOTRUN -> [SKIP][68] ([Intel XE#4518])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@xe_eudebug_sriov@deny-sriov.html

  * igt@xe_exec_balancer@many-parallel-userptr-rebind:
    - shard-adlp:         [PASS][69] -> [DMESG-FAIL][70] ([Intel XE#3876])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@xe_exec_balancer@many-parallel-userptr-rebind.html
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@xe_exec_balancer@many-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][71] ([Intel XE#2322]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_compute_mode@once-bindexecqueue-rebind:
    - shard-adlp:         [PASS][72] -> [FAIL][73] ([Intel XE#5625])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@xe_exec_compute_mode@once-bindexecqueue-rebind.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@xe_exec_compute_mode@once-bindexecqueue-rebind.html

  * igt@xe_exec_fault_mode@twice-userptr-prefetch:
    - shard-dg2-set2:     NOTRUN -> [SKIP][74] ([Intel XE#288]) +8 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@xe_exec_fault_mode@twice-userptr-prefetch.html

  * igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared:
    - shard-dg2-set2:     NOTRUN -> [SKIP][75] ([Intel XE#4915]) +128 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@xe_exec_system_allocator@process-many-stride-mmap-prefetch-shared.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [SKIP][76] ([Intel XE#4943]) +7 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_exec_system_allocator@threads-shared-vm-many-mmap-new-huge.html

  * igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate:
    - shard-dg2-set2:     [PASS][77] -> [ABORT][78] ([Intel XE#6752])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-435/igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate.html
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-463/igt@xe_exec_threads@threads-bal-mixed-userptr-invalidate.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          NOTRUN -> [SKIP][79] ([Intel XE#6281])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_mmap@small-bar:
    - shard-dg2-set2:     NOTRUN -> [SKIP][80] ([Intel XE#512])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@xe_mmap@small-bar.html

  * igt@xe_oa@disabled-read-error:
    - shard-dg2-set2:     NOTRUN -> [SKIP][81] ([Intel XE#3573]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@xe_oa@disabled-read-error.html

  * igt@xe_pm@d3cold-i2c:
    - shard-dg2-set2:     NOTRUN -> [SKIP][82] ([Intel XE#5694])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0:
    - shard-lnl:          [PASS][83] -> [FAIL][84] ([Intel XE#6251]) +1 other test fail
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-lnl-8/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-50@engine-drm_xe_engine_class_video_decode0.html

  * igt@xe_pmu@gt-frequency:
    - shard-dg2-set2:     NOTRUN -> [FAIL][85] ([Intel XE#4819]) +1 other test fail
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-435/igt@xe_pmu@gt-frequency.html

  * igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#4733])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-rpm:
    - shard-dg2-set2:     NOTRUN -> [SKIP][87] ([Intel XE#4733]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@xe_pxp@pxp-stale-bo-bind-post-rpm.html

  * igt@xe_query@multigpu-query-mem-usage:
    - shard-dg2-set2:     NOTRUN -> [SKIP][88] ([Intel XE#944])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@xe_query@multigpu-query-mem-usage.html

  * igt@xe_query@multigpu-query-uc-fw-version-guc:
    - shard-bmg:          NOTRUN -> [SKIP][89] ([Intel XE#944])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@xe_query@multigpu-query-uc-fw-version-guc.html

  * igt@xe_sriov_flr@flr-each-isolation:
    - shard-dg2-set2:     NOTRUN -> [SKIP][90] ([Intel XE#3342])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@xe_sriov_flr@flr-each-isolation.html

  * igt@xe_survivability@i2c-functionality:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#6529])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@xe_survivability@i2c-functionality.html

  * igt@xe_vm@bind-execqueues-conflict:
    - shard-adlp:         [PASS][92] -> [TIMEOUT][93] ([Intel XE#3876]) +1 other test timeout
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@xe_vm@bind-execqueues-conflict.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@xe_vm@bind-execqueues-conflict.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotrebind:
    - shard-bmg:          [SKIP][94] ([Intel XE#6779]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@core_hotunplug@hotrebind.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@core_hotunplug@hotrebind.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-bmg:          [SKIP][96] -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@device_reset@unbind-reset-rebind.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@device_reset@unbind-reset-rebind.html

  * igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs:
    - shard-bmg:          [DMESG-FAIL][98] ([Intel XE#5545]) -> [PASS][99] +2 other tests pass
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_atomic_transition@modeset-transition-nonblocking-fencing@1x-outputs.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-adlp:         [FAIL][100] ([Intel XE#3908]) -> [PASS][101] +1 other test pass
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-adlp:         [DMESG-WARN][102] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][103] +5 other tests pass
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-4/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][104] ([Intel XE#3862]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][106] ([Intel XE#3862] / [Intel XE#4345]) -> [PASS][107]
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-435/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-adlp:         [SKIP][108] ([Intel XE#787]) -> [PASS][109] +89 other tests pass
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-4/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs:
    - shard-adlp:         [SKIP][110] ([Intel XE#455] / [Intel XE#787]) -> [PASS][111] +59 other tests pass
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][112] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][114] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-434/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_cursor_crc@cursor-sliding-256x256:
    - shard-bmg:          [FAIL][116] ([Intel XE#6747]) -> [PASS][117] +1 other test pass
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-256x256.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-4/igt@kms_cursor_crc@cursor-sliding-256x256.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
    - shard-bmg:          [DMESG-WARN][118] ([Intel XE#5354]) -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][120] ([Intel XE#6715]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [FAIL][122] ([Intel XE#4633]) -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][124] ([Intel XE#6766]) -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@kms_flip@flip-vs-suspend-interruptible@c-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-adlp:         [SKIP][126] ([Intel XE#455]) -> [PASS][127] +7 other tests pass
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y:
    - shard-adlp:         [FAIL][128] ([Intel XE#1874]) -> [PASS][129] +2 other tests pass
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-9/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-y-to-y.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-bmg:          [ABORT][130] ([Intel XE#6740]) -> [PASS][131] +1 other test pass
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-3/igt@kms_hdr@bpc-switch-suspend.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_lease@setcrtc-implicit-plane:
    - shard-bmg:          [SKIP][132] ([Intel XE#6557] / [Intel XE#6703]) -> [PASS][133] +8 other tests pass
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_lease@setcrtc-implicit-plane.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_lease@setcrtc-implicit-plane.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [DMESG-FAIL][134] ([Intel XE#5175]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-x.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-malloc-madvise:
    - shard-bmg:          [SKIP][136] ([Intel XE#6703]) -> [PASS][137] +188 other tests pass
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-malloc-madvise.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-malloc-madvise.html

  * igt@xe_pm@s2idle-multiple-execs:
    - shard-adlp:         [DMESG-WARN][138] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-3/igt@xe_pm@s2idle-multiple-execs.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-4/igt@xe_pm@s2idle-multiple-execs.html

  * igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0:
    - shard-lnl:          [FAIL][140] ([Intel XE#6251]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-lnl-4/igt@xe_pmu@engine-activity-accuracy-90@engine-drm_xe_engine_class_copy0.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-adlp:         [DMESG-WARN][142] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#6766]) -> [DMESG-WARN][143] ([Intel XE#6766]) +1 other test dmesg-warn
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-3/igt@kms_async_flips@async-flip-suspend-resume.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-4/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-bmg:          [SKIP][144] ([Intel XE#6703]) -> [SKIP][145] ([Intel XE#2327])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-bmg:          [SKIP][146] ([Intel XE#6703]) -> [SKIP][147] ([Intel XE#1124]) +3 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-bmg:          [SKIP][148] ([Intel XE#6703]) -> [SKIP][149] ([Intel XE#610])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@linear-tiling-4-displays-1920x1080p:
    - shard-bmg:          [SKIP][150] ([Intel XE#6703]) -> [SKIP][151] ([Intel XE#367]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_bw@linear-tiling-4-displays-1920x1080p.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-bmg:          [SKIP][152] ([Intel XE#6703]) -> [SKIP][153] ([Intel XE#2887]) +7 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-bmg:          [SKIP][154] ([Intel XE#6703]) -> [SKIP][155] ([Intel XE#2724])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_cdclk@mode-transition-all-outputs.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-bmg:          [SKIP][156] ([Intel XE#6703]) -> [SKIP][157] ([Intel XE#2252]) +2 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-dg2-set2:     [INCOMPLETE][158] ([Intel XE#2594]) -> [SKIP][159] ([Intel XE#373])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-dg2-436/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-dg2-432/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_colorop@plane-xr30-xr30-ctm_3x4_bt709_dec:
    - shard-bmg:          [SKIP][160] ([Intel XE#6703]) -> [SKIP][161] ([Intel XE#6704]) +2 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_bt709_dec.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_colorop@plane-xr30-xr30-ctm_3x4_bt709_dec.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-bmg:          [SKIP][162] ([Intel XE#6703]) -> [SKIP][163] ([Intel XE#2390])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_content_protection@dp-mst-type-1.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          [SKIP][164] ([Intel XE#6703]) -> [SKIP][165] ([Intel XE#2341])
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_content_protection@mei-interface.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-bmg:          [SKIP][166] ([Intel XE#6703]) -> [SKIP][167] ([Intel XE#2320])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-max-size:
    - shard-bmg:          [SKIP][168] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][169] ([Intel XE#2320])
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_cursor_crc@cursor-onscreen-max-size.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_cursor_crc@cursor-onscreen-max-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
    - shard-bmg:          [SKIP][170] ([Intel XE#6703]) -> [SKIP][171] ([Intel XE#4210])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-bmg:          [SKIP][172] ([Intel XE#6703]) -> [SKIP][173] ([Intel XE#4354])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-mst.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          [SKIP][174] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][175] ([Intel XE#2374])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_feature_discovery@psr1.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-bmg:          [SKIP][176] ([Intel XE#6703]) -> [SKIP][177] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt:
    - shard-bmg:          [SKIP][178] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][179] ([Intel XE#2311])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][180] ([Intel XE#6703]) -> [SKIP][181] ([Intel XE#4141]) +4 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][182] ([Intel XE#6703]) -> [SKIP][183] ([Intel XE#2311]) +7 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][184] ([Intel XE#6703]) -> [SKIP][185] ([Intel XE#2313]) +9 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-bmg:          [SKIP][186] ([Intel XE#6703]) -> [SKIP][187] ([Intel XE#2352])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][188] ([Intel XE#3544]) -> [SKIP][189] ([Intel XE#3374] / [Intel XE#3544])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-6/igt@kms_hdr@brightness-with-hdr.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-bmg:          [SKIP][190] ([Intel XE#6703]) -> [SKIP][191] ([Intel XE#346] / [Intel XE#6590])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_joiner@basic-big-joiner.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][192] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][193] ([Intel XE#5021])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          [SKIP][194] ([Intel XE#6703]) -> [SKIP][195] ([Intel XE#3309])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_pm_dc@dc5-retention-flops.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          [SKIP][196] ([Intel XE#6703]) -> [SKIP][197] ([Intel XE#2392])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_pm_dc@dc6-psr.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-bmg:          [SKIP][198] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][199] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr@pr-sprite-plane-onoff:
    - shard-bmg:          [SKIP][200] ([Intel XE#1406] / [Intel XE#6703]) -> [SKIP][201] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +5 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_psr@pr-sprite-plane-onoff.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@kms_psr@pr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-bmg:          [SKIP][202] ([Intel XE#6703]) -> [DMESG-FAIL][203] ([Intel XE#5545])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_rotation_crc@multiplane-rotation.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_rotation_crc@multiplane-rotation.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-bmg:          [SKIP][204] ([Intel XE#6703]) -> [SKIP][205] ([Intel XE#6503])
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_sharpness_filter@filter-scaler-downscale.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][206] ([Intel XE#2426]) -> [FAIL][207] ([Intel XE#1729])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][208] ([Intel XE#2426]) -> [SKIP][209] ([Intel XE#2509])
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-dpms:
    - shard-bmg:          [SKIP][210] ([Intel XE#6703]) -> [SKIP][211] ([Intel XE#1499])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@kms_vrr@flip-dpms.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@kms_vrr@flip-dpms.html

  * igt@xe_eudebug@basic-vm-access-parameters-faultable:
    - shard-bmg:          [SKIP][212] ([Intel XE#6703]) -> [SKIP][213] ([Intel XE#4837]) +2 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_eudebug@basic-vm-access-parameters-faultable.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@xe_eudebug@basic-vm-access-parameters-faultable.html

  * igt@xe_eudebug_online@resume-one:
    - shard-bmg:          [SKIP][214] ([Intel XE#6703]) -> [SKIP][215] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_eudebug_online@resume-one.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@xe_eudebug_online@resume-one.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
    - shard-bmg:          [SKIP][216] ([Intel XE#6703]) -> [SKIP][217] ([Intel XE#2322]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html

  * igt@xe_exec_reset@cm-cat-error:
    - shard-adlp:         [DMESG-WARN][218] ([Intel XE#3868]) -> [DMESG-FAIL][219] ([Intel XE#3868])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-adlp-6/igt@xe_exec_reset@cm-cat-error.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-adlp-8/igt@xe_exec_reset@cm-cat-error.html

  * igt@xe_exec_system_allocator@once-large-mmap-free-huge-nomemset:
    - shard-bmg:          [SKIP][220] ([Intel XE#6557] / [Intel XE#6703]) -> [SKIP][221] ([Intel XE#4943])
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_exec_system_allocator@once-large-mmap-free-huge-nomemset.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@xe_exec_system_allocator@once-large-mmap-free-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset:
    - shard-bmg:          [SKIP][222] ([Intel XE#6703]) -> [SKIP][223] ([Intel XE#4943]) +8 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@xe_exec_system_allocator@threads-many-mmap-new-huge-nomemset.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq:
    - shard-bmg:          [SKIP][224] ([Intel XE#6703]) -> [SKIP][225] ([Intel XE#4733])
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-2/igt@xe_pxp@pxp-stale-bo-bind-post-termination-irq.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-bmg:          [SKIP][226] ([Intel XE#6703]) -> [SKIP][227] ([Intel XE#944]) +1 other test skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343/shard-bmg-2/igt@xe_query@multigpu-query-cs-cycles.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/shard-bmg-3/igt@xe_query@multigpu-query-cs-cycles.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
  [Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2594
  [Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3862]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3862
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
  [Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4210]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4210
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4417
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4518]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4518
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4633]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4633
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4741
  [Intel XE#4819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4819
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/512
  [Intel XE#5175]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5175
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5694]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5694
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6529]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6529
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#6557]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6557
  [Intel XE#6590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6590
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6703
  [Intel XE#6704]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6704
  [Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
  [Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
  [Intel XE#6747]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6747
  [Intel XE#6752]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6752
  [Intel XE#6766]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6766
  [Intel XE#6779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6779
  [Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343 -> xe-pw-158654v1

  IGT_8659: 8659
  xe-4206-97efabfcf7e97d1b34327b2fbbc2050a6b77e343: 97efabfcf7e97d1b34327b2fbbc2050a6b77e343
  xe-pw-158654v1: 158654v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-158654v1/index.html

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