Re: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates

[Imre Deak <imre.deak@intel.com>]

On Tue, Jan 06, 2026 at 06:04:18AM +0000, Kandpal, Suraj wrote:
> > Subject: [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates
> > 
> > HDMI FRL clock rates are incorrectly defined. Fix these rates.
> 
> Patch can be dropped, you remove the .clock member anyway no point in
> having a patch whose code fix won't see Light of day by end of series.

Please don't drop this patch. The fix should be recorded in the git
history, even if the changed lines will be removed.

> 
> Regards,
> Suraj Kandpal
> 
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 4d006c14c049..0f28d02b7a69 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -1923,7 +1923,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_594 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
> > -	.clock = 3000000,
> > +	.clock = 300000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1948,7 +1948,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_300 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
> > -	.clock = 6000000,
> > +	.clock = 600000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1973,7 +1973,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_600 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
> > -	.clock = 8000000,
> > +	.clock = 800000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -1998,7 +1998,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_800 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
> > -	.clock = 10000000,
> > +	.clock = 1000000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > @@ -2023,7 +2023,7 @@ static const struct intel_c20pll_state
> > mtl_c20_hdmi_1000 = {  };
> > 
> >  static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
> > -	.clock = 12000000,
> > +	.clock = 1200000,
> >  	.tx = {  0xbe98, /* tx cfg0 */
> >  		  0x8800, /* tx cfg1 */
> >  		  0x0000, /* tx cfg2 */
> > --
> > 2.34.1
>