Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers

[Imre Deak <imre.deak@intel.com>]

On Fri, Jan 09, 2026 at 06:12:25AM +0200, Kandpal, Suraj wrote:
> 
> 
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Thursday, January 8, 2026 8:06 PM
> > To: Kandpal, Suraj <suraj.kandpal@intel.com>
> > Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> > intel-xe@lists.freedesktop.org
> > Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll
> > dividers
> > 
> > On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> > > ...
> > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > index e33f6f48a6ce..13acfc7c0469 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > > >
> > > > ...
> > > >
> > > > +void intel_lt_phy_verify_plls(struct intel_display *display) {
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > > > +	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); }
> > >
> > > Same thing as the previous patch this is not needed.  Moreover we do
> > > not go through any algorithm for edp and dp tables for LT PHY hence
> > > the Rate always matches. This patch should be dropped.
> > 
> > Similarly to my comment on the previous patch, the tables entries should be
> > kept correct even after they were initially added. So please don't drop this
> > patch.
> 
> But testing DP eDP tables still does not make sense here since they
> don't go through the traditional HDMI algo that CX0 go through the
> clock rate in a way is signalled just by a single entry of VDR0_CONFIG
> So other than verifying table for HDMI the rest need not be done.

The LT PHY DP/eDP PLL determination of the PLL clock from the PLL state
and the inverse determination of the PLL state from the PLL clock is
just the same as for HDMI. The fact that the PLL state is just the
VDR0_CONFIG register value for eDP/DP vs. the PLL divider values for
HDMI is odd and should be looked into and fixed in my opinion (so that
we know that the rest of the eDP/DP PLL state is actually correct), but
this difference between eDP/DP vs. HDMI is irrelevant. What matters is
that the PLL clock is calculated from the PLL state and we do need a way
to verify that the PLL clock matches the PLL state and the functions
converting between the two are also correct (and all these things stay
correct even after the initial addition of the table entries and the
functions).

> > 
> > > Regards,
> > > Suraj Kandpal