From: Imre Deak <imre.deak@intel.com>
To: "Kandpal, Suraj" <suraj.kandpal@intel.com>
Cc: "Kahola, Mika" <mika.kahola@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy pll dividers
Date: Thu, 8 Jan 2026 16:35:36 +0200 [thread overview]
Message-ID: <aV_AuH7hzqOfr8ev@ideak-desk> (raw)
In-Reply-To: <IA3PR11MB893722B40977A210F1E94BD4E387A@IA3PR11MB8937.namprd11.prod.outlook.com>
On Tue, Jan 06, 2026 at 05:07:25AM +0000, Kandpal, Suraj wrote:
> ...
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index e33f6f48a6ce..13acfc7c0469 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> >
> > ...
> >
> > +void intel_lt_phy_verify_plls(struct intel_display *display)
> > +{
> > + intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables);
> > + intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
> > + intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
> > +}
>
> Same thing as the previous patch this is not needed. Moreover we do
> not go through any algorithm for edp and dp tables for LT PHY hence
> the Rate always matches. This patch should be dropped.
Similarly to my comment on the previous patch, the tables entries should
be kept correct even after they were initially added. So please don't
drop this patch.
> Regards,
> Suraj Kandpal
next prev parent reply other threads:[~2026-01-08 14:35 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 15:19 [PATCH v2 00/15] drm/i915/pll: Verify pll dividers and remove redundant .clock member Mika Kahola
2025-12-17 15:19 ` [PATCH v2 01/15] drm/i915/c10: Move C10 port clock calculation Mika Kahola
2026-01-06 5:08 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 02/15] drm/i915/c20: Move C20 " Mika Kahola
2026-01-06 5:10 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 03/15] drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider calculation Mika Kahola
2026-01-06 5:13 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 04/15] drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation Mika Kahola
2026-01-06 5:49 ` Kandpal, Suraj
2026-01-08 14:15 ` Imre Deak
2026-01-14 5:25 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 05/15] drm/i915/cx0: Drop encoder from port clock calculation Mika Kahola
2026-01-06 6:02 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 06/15] drm/i915/cx0: Create macro around pll tables Mika Kahola
2026-01-06 5:54 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 07/15] drm/i915/lt_phy: Create macro for lt phy pll state Mika Kahola
2026-01-06 5:56 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 08/15] drm/i915/display: Add helper function for fuzzy clock check Mika Kahola
2026-01-08 3:53 ` Kandpal, Suraj
2026-01-14 13:01 ` Kahola, Mika
2025-12-17 15:19 ` [PATCH v2 09/15] drm/i915/cx0: Fix HDMI FRL clock rates Mika Kahola
2026-01-06 6:04 ` Kandpal, Suraj
2026-01-08 14:19 ` Imre Deak
2026-01-09 4:09 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 10/15] drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming Mika Kahola
2026-01-14 5:32 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 11/15] drm/i915/cx0: Verify C10/C20 pll dividers Mika Kahola
2026-01-06 5:04 ` Kandpal, Suraj
2026-01-08 14:30 ` Imre Deak
2026-01-14 5:24 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 12/15] drm/i915/lt_phy: Add verification for lt phy " Mika Kahola
2026-01-06 5:07 ` Kandpal, Suraj
2026-01-08 14:35 ` Imre Deak [this message]
2026-01-09 4:12 ` Kandpal, Suraj
2026-01-09 9:39 ` Kahola, Mika
2026-01-13 14:36 ` Imre Deak
2026-01-13 14:57 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 13/15] drm/i915/cx0: Drop C20 25.175 MHz rate Mika Kahola
2026-01-06 6:15 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 14/15] drm/i915/lt_phy: Drop 27.2 " Mika Kahola
2026-01-06 6:16 ` Kandpal, Suraj
2025-12-17 15:19 ` [PATCH v2 15/15] drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables Mika Kahola
2026-01-06 5:51 ` Kandpal, Suraj
2026-01-06 6:01 ` Kandpal, Suraj
2025-12-17 17:34 ` ✗ CI.checkpatch: warning for drm/i915/pll: Verify pll dividers and remove redundant .clock member (rev2) Patchwork
2025-12-17 17:36 ` ✓ CI.KUnit: success " Patchwork
2025-12-17 18:16 ` ✓ Xe.CI.BAT: " Patchwork
2025-12-18 16:39 ` ✗ Xe.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=aV_AuH7hzqOfr8ev@ideak-desk \
--to=imre.deak@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=mika.kahola@intel.com \
--cc=suraj.kandpal@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox