Re: [PATCH v3 3/4] drm/xe/xe_hw_error: Add support for GT hardware errors

[Raag Jadav <raag.jadav@intel.com>]

On Mon, Jan 12, 2026 at 09:11:05AM +0530, Riana Tauro wrote:
> On 12/10/2025 11:48 PM, Raag Jadav wrote:
> > On Fri, Dec 05, 2025 at 02:09:35PM +0530, Riana Tauro wrote:
> > > PVC supports GT error reporting via vector registers along with
> > > error status register. Add support to report these errors and
> > > update respective counters. Incase of Subslice error reported
> > > by vector register, process the error status register
> > > for applicable bits.
> > > 
> > > Incorporate the counter inside the driver itself and start
> > > using the drm_ras generic netlink to report them.

...

> > > +		vector = xe_mmio_read32(mmio, ERR_STAT_GT_VECTOR_REG(severity, i));
> > > +		if (!vector)
> > > +			continue;
> > > +
> > > +		switch (i) {
> > > +		case ERR_STAT_GT_VECTOR0:
> > > +		case ERR_STAT_GT_VECTOR1:
> > > +			u32 errbit;
> > > +
> > > +			val = hweight32(vector);
> > > +			atomic64_add(val, &info[error_id].counter);
> > > +			log_gt_err(tile, "Subslice", i, vector, severity);
> > > +
> > > +			if (err_stat)
> > > +				break;
> > 
> > So we won't ever be getting past this point, is that right?
> 
> err stat will be read only once. The first time we will not hit this.

Right, so let's explain it with a small comment.

...

> > > @@ -96,11 +240,39 @@ static void hw_error_source_handler(struct xe_tile *tile, enum drm_xe_ras_error_
> > >   		goto unlock;
> > >   	}
> > > -	if (err_src & XE_CSC_ERROR)
> > > +	if (err_src & XE_CSC_ERROR) {
> > 
> > Shouldn't this be inside the loop below?
> 
> We do not have a separate type for CSC. And once we get a CSC error, the
> driver will be wedged and only way to recover is firmware flash.
> 
> So there is no point of keeping count or checking other bits.

Ditto for a small comment.

Raag