* [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines
@ 2026-02-24 2:33 Xin Wang
2026-02-24 2:40 ` ✓ CI.KUnit: success for drm/xe: restrict multi-lrc to VCS/VECS engines (rev2) Patchwork
2026-02-24 22:05 ` [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Matt Roper
0 siblings, 2 replies; 7+ messages in thread
From: Xin Wang @ 2026-02-24 2:33 UTC (permalink / raw)
To: intel-xe; +Cc: Xin Wang, Shuicheng Lin, Matt Roper, Matthew Brost
Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
VIDEO_ENHANCE engines only. This check should have been in place from the
start, as the driver typically avoids allowing uapi cases that we have
no userspace consumer for.
Additionally, the GuC firmware on ModSched platforms no longer supports
multi-lrc on non-media engines.
V3:
- store a multi-lrc enable class mask in xe->info and populate from
xe_device_desc in xe_pci.c (Matthew Brost)
V2:
- correct the typo (Shuicheng)
- move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
- remove the graphics version check (Matt Roper)
- input more details in the commit info (Matt Roper)
Cc: Shuicheng Lin <shuicheng.lin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Xin Wang <x.wang@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 ++
drivers/gpu/drm/xe/xe_exec_queue.c | 5 +++++
drivers/gpu/drm/xe/xe_pci.c | 17 +++++++++++++++++
drivers/gpu/drm/xe/xe_pci_types.h | 1 +
4 files changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 8f3ef836541e..caa8f34a6744 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -138,6 +138,8 @@ struct xe_device {
u8 tile_count;
/** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
u8 max_gt_per_tile;
+ /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */
+ u8 multi_lrc_mask;
/** @info.gt_count: Total number of GTs for entire device */
u8 gt_count;
/** @info.vm_max_level: Max VM level */
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 66d0e10ee2c4..5abb29454d1f 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
if (XE_IOCTL_DBG(xe, !hwe))
return -EINVAL;
+ /* multi-lrc is only supported on select engine classes */
+ if (XE_IOCTL_DBG(xe, args->width > 1 &&
+ !(xe->info.multi_lrc_mask & BIT(hwe->class))))
+ return -EOPNOTSUPP;
+
vm = xe_vm_lookup(xef, args->vm_id);
if (XE_IOCTL_DBG(xe, !vm))
return -ENOENT;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index e1f569235d8a..fe63387d4077 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -194,6 +194,7 @@ static const struct xe_device_desc tgl_desc = {
.has_llc = true,
.has_sriov = true,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
.require_force_probe = true,
.va_bits = 48,
.vm_max_level = 3,
@@ -208,6 +209,7 @@ static const struct xe_device_desc rkl_desc = {
.has_display = true,
.has_llc = true,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
.require_force_probe = true,
.va_bits = 48,
.vm_max_level = 3,
@@ -225,6 +227,7 @@ static const struct xe_device_desc adl_s_desc = {
.has_llc = true,
.has_sriov = true,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
.require_force_probe = true,
.subplatforms = (const struct xe_subplatform_desc[]) {
{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
@@ -246,6 +249,7 @@ static const struct xe_device_desc adl_p_desc = {
.has_llc = true,
.has_sriov = true,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
.require_force_probe = true,
.subplatforms = (const struct xe_subplatform_desc[]) {
{ XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
@@ -283,6 +287,7 @@ static const struct xe_device_desc dg1_desc = {
.has_gsc_nvm = 1,
.has_heci_gscfi = 1,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
.require_force_probe = true,
.va_bits = 48,
.vm_max_level = 3,
@@ -313,6 +318,8 @@ static const struct xe_device_desc ats_m_desc = {
.pre_gmdid_media_ip = &media_ip_xehpm,
.dma_mask_size = 46,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
+ BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
.require_force_probe = true,
DG2_FEATURES,
@@ -325,6 +332,8 @@ static const struct xe_device_desc dg2_desc = {
.pre_gmdid_media_ip = &media_ip_xehpm,
.dma_mask_size = 46,
.max_gt_per_tile = 1,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
+ BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
.require_force_probe = true,
DG2_FEATURES,
@@ -358,6 +367,7 @@ static const struct xe_device_desc mtl_desc = {
.has_display = true,
.has_pxp = true,
.max_gt_per_tile = 2,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
.va_bits = 48,
.vm_max_level = 3,
};
@@ -393,6 +403,8 @@ static const struct xe_device_desc bmg_desc = {
.has_soc_remapper_telem = true,
.has_sriov = true,
.max_gt_per_tile = 2,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
+ BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
.needs_scratch = true,
.subplatforms = (const struct xe_subplatform_desc[]) {
{ XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
@@ -445,6 +457,8 @@ static const struct xe_device_desc cri_desc = {
.has_soc_remapper_telem = true,
.has_sriov = true,
.max_gt_per_tile = 2,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
+ BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
.require_force_probe = true,
.va_bits = 57,
.vm_max_level = 4,
@@ -459,6 +473,8 @@ static const struct xe_device_desc nvlp_desc = {
.has_page_reclaim_hw_assist = true,
.has_pre_prod_wa = true,
.max_gt_per_tile = 2,
+ .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
+ BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
.require_force_probe = true,
.va_bits = 48,
.vm_max_level = 4,
@@ -746,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
xe->info.skip_pcode = desc->skip_pcode;
xe->info.needs_scratch = desc->needs_scratch;
xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
+ xe->info.multi_lrc_mask = desc->multi_lrc_mask;
xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
xe_modparam.probe_display &&
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 470d31a1f0d6..47e8a1552c2b 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -30,6 +30,7 @@ struct xe_device_desc {
u8 dma_mask_size;
u8 max_remote_tiles:2;
u8 max_gt_per_tile:2;
+ u8 multi_lrc_mask;
u8 va_bits;
u8 vm_max_level;
u8 vram_flags;
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ CI.KUnit: success for drm/xe: restrict multi-lrc to VCS/VECS engines (rev2)
2026-02-24 2:33 [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Xin Wang
@ 2026-02-24 2:40 ` Patchwork
2026-02-24 22:05 ` [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Matt Roper
1 sibling, 0 replies; 7+ messages in thread
From: Patchwork @ 2026-02-24 2:40 UTC (permalink / raw)
To: Xin Wang; +Cc: intel-xe
== Series Details ==
Series: drm/xe: restrict multi-lrc to VCS/VECS engines (rev2)
URL : https://patchwork.freedesktop.org/series/161799/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[02:39:11] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:39:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:39:46] Starting KUnit Kernel (1/1)...
[02:39:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:39:46] ================== guc_buf (11 subtests) ===================
[02:39:46] [PASSED] test_smallest
[02:39:46] [PASSED] test_largest
[02:39:46] [PASSED] test_granular
[02:39:46] [PASSED] test_unique
[02:39:46] [PASSED] test_overlap
[02:39:46] [PASSED] test_reusable
[02:39:46] [PASSED] test_too_big
[02:39:46] [PASSED] test_flush
[02:39:46] [PASSED] test_lookup
[02:39:46] [PASSED] test_data
[02:39:46] [PASSED] test_class
[02:39:46] ===================== [PASSED] guc_buf =====================
[02:39:46] =================== guc_dbm (7 subtests) ===================
[02:39:46] [PASSED] test_empty
[02:39:46] [PASSED] test_default
[02:39:46] ======================== test_size ========================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] ==================== [PASSED] test_size ====================
[02:39:46] ======================= test_reuse ========================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] =================== [PASSED] test_reuse ====================
[02:39:46] =================== test_range_overlap ====================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] =============== [PASSED] test_range_overlap ================
[02:39:46] =================== test_range_compact ====================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] =============== [PASSED] test_range_compact ================
[02:39:46] ==================== test_range_spare =====================
[02:39:46] [PASSED] 4
[02:39:46] [PASSED] 8
[02:39:46] [PASSED] 32
[02:39:46] [PASSED] 256
[02:39:46] ================ [PASSED] test_range_spare =================
[02:39:46] ===================== [PASSED] guc_dbm =====================
[02:39:46] =================== guc_idm (6 subtests) ===================
[02:39:46] [PASSED] bad_init
[02:39:46] [PASSED] no_init
[02:39:46] [PASSED] init_fini
[02:39:46] [PASSED] check_used
[02:39:46] [PASSED] check_quota
[02:39:46] [PASSED] check_all
[02:39:46] ===================== [PASSED] guc_idm =====================
[02:39:46] ================== no_relay (3 subtests) ===================
[02:39:46] [PASSED] xe_drops_guc2pf_if_not_ready
[02:39:46] [PASSED] xe_drops_guc2vf_if_not_ready
[02:39:46] [PASSED] xe_rejects_send_if_not_ready
[02:39:46] ==================== [PASSED] no_relay =====================
[02:39:46] ================== pf_relay (14 subtests) ==================
[02:39:46] [PASSED] pf_rejects_guc2pf_too_short
[02:39:46] [PASSED] pf_rejects_guc2pf_too_long
[02:39:46] [PASSED] pf_rejects_guc2pf_no_payload
[02:39:46] [PASSED] pf_fails_no_payload
[02:39:46] [PASSED] pf_fails_bad_origin
[02:39:46] [PASSED] pf_fails_bad_type
[02:39:46] [PASSED] pf_txn_reports_error
[02:39:46] [PASSED] pf_txn_sends_pf2guc
[02:39:46] [PASSED] pf_sends_pf2guc
[02:39:46] [SKIPPED] pf_loopback_nop
[02:39:46] [SKIPPED] pf_loopback_echo
[02:39:46] [SKIPPED] pf_loopback_fail
[02:39:46] [SKIPPED] pf_loopback_busy
[02:39:46] [SKIPPED] pf_loopback_retry
[02:39:46] ==================== [PASSED] pf_relay =====================
[02:39:46] ================== vf_relay (3 subtests) ===================
[02:39:46] [PASSED] vf_rejects_guc2vf_too_short
[02:39:46] [PASSED] vf_rejects_guc2vf_too_long
[02:39:46] [PASSED] vf_rejects_guc2vf_no_payload
[02:39:46] ==================== [PASSED] vf_relay =====================
[02:39:46] ================ pf_gt_config (9 subtests) =================
[02:39:46] [PASSED] fair_contexts_1vf
[02:39:46] [PASSED] fair_doorbells_1vf
[02:39:46] [PASSED] fair_ggtt_1vf
[02:39:46] ====================== fair_vram_1vf ======================
[02:39:46] [PASSED] 3.50 GiB
[02:39:46] [PASSED] 11.5 GiB
[02:39:46] [PASSED] 15.5 GiB
[02:39:46] [PASSED] 31.5 GiB
[02:39:46] [PASSED] 63.5 GiB
[02:39:46] [PASSED] 13.9 GiB
[02:39:46] ================== [PASSED] fair_vram_1vf ==================
[02:39:46] ================ fair_vram_1vf_admin_only =================
[02:39:46] [PASSED] 3.50 GiB
[02:39:46] [PASSED] 11.5 GiB
[02:39:46] [PASSED] 15.5 GiB
[02:39:46] [PASSED] 31.5 GiB
[02:39:46] [PASSED] 63.5 GiB
[02:39:46] [PASSED] 13.9 GiB
[02:39:46] ============ [PASSED] fair_vram_1vf_admin_only =============
[02:39:46] ====================== fair_contexts ======================
[02:39:46] [PASSED] 1 VF
[02:39:46] [PASSED] 2 VFs
[02:39:46] [PASSED] 3 VFs
[02:39:46] [PASSED] 4 VFs
[02:39:46] [PASSED] 5 VFs
[02:39:46] [PASSED] 6 VFs
[02:39:46] [PASSED] 7 VFs
[02:39:46] [PASSED] 8 VFs
[02:39:46] [PASSED] 9 VFs
[02:39:46] [PASSED] 10 VFs
[02:39:46] [PASSED] 11 VFs
[02:39:46] [PASSED] 12 VFs
[02:39:46] [PASSED] 13 VFs
[02:39:46] [PASSED] 14 VFs
[02:39:46] [PASSED] 15 VFs
[02:39:46] [PASSED] 16 VFs
[02:39:46] [PASSED] 17 VFs
[02:39:46] [PASSED] 18 VFs
[02:39:46] [PASSED] 19 VFs
[02:39:46] [PASSED] 20 VFs
[02:39:46] [PASSED] 21 VFs
[02:39:46] [PASSED] 22 VFs
[02:39:46] [PASSED] 23 VFs
[02:39:46] [PASSED] 24 VFs
[02:39:46] [PASSED] 25 VFs
[02:39:46] [PASSED] 26 VFs
[02:39:46] [PASSED] 27 VFs
[02:39:46] [PASSED] 28 VFs
[02:39:46] [PASSED] 29 VFs
[02:39:46] [PASSED] 30 VFs
[02:39:46] [PASSED] 31 VFs
[02:39:46] [PASSED] 32 VFs
[02:39:46] [PASSED] 33 VFs
[02:39:46] [PASSED] 34 VFs
[02:39:46] [PASSED] 35 VFs
[02:39:46] [PASSED] 36 VFs
[02:39:46] [PASSED] 37 VFs
[02:39:46] [PASSED] 38 VFs
[02:39:46] [PASSED] 39 VFs
[02:39:46] [PASSED] 40 VFs
[02:39:46] [PASSED] 41 VFs
[02:39:46] [PASSED] 42 VFs
[02:39:46] [PASSED] 43 VFs
[02:39:46] [PASSED] 44 VFs
[02:39:46] [PASSED] 45 VFs
[02:39:46] [PASSED] 46 VFs
[02:39:46] [PASSED] 47 VFs
[02:39:46] [PASSED] 48 VFs
[02:39:46] [PASSED] 49 VFs
[02:39:46] [PASSED] 50 VFs
[02:39:46] [PASSED] 51 VFs
[02:39:46] [PASSED] 52 VFs
[02:39:46] [PASSED] 53 VFs
[02:39:46] [PASSED] 54 VFs
[02:39:46] [PASSED] 55 VFs
[02:39:46] [PASSED] 56 VFs
[02:39:46] [PASSED] 57 VFs
[02:39:46] [PASSED] 58 VFs
[02:39:46] [PASSED] 59 VFs
[02:39:46] [PASSED] 60 VFs
[02:39:46] [PASSED] 61 VFs
[02:39:46] [PASSED] 62 VFs
[02:39:46] [PASSED] 63 VFs
[02:39:46] ================== [PASSED] fair_contexts ==================
[02:39:46] ===================== fair_doorbells ======================
[02:39:46] [PASSED] 1 VF
[02:39:46] [PASSED] 2 VFs
[02:39:46] [PASSED] 3 VFs
[02:39:46] [PASSED] 4 VFs
[02:39:46] [PASSED] 5 VFs
[02:39:46] [PASSED] 6 VFs
[02:39:46] [PASSED] 7 VFs
[02:39:46] [PASSED] 8 VFs
[02:39:46] [PASSED] 9 VFs
[02:39:46] [PASSED] 10 VFs
[02:39:46] [PASSED] 11 VFs
[02:39:46] [PASSED] 12 VFs
[02:39:46] [PASSED] 13 VFs
[02:39:46] [PASSED] 14 VFs
[02:39:46] [PASSED] 15 VFs
[02:39:46] [PASSED] 16 VFs
[02:39:46] [PASSED] 17 VFs
[02:39:46] [PASSED] 18 VFs
[02:39:46] [PASSED] 19 VFs
[02:39:46] [PASSED] 20 VFs
[02:39:46] [PASSED] 21 VFs
[02:39:46] [PASSED] 22 VFs
[02:39:46] [PASSED] 23 VFs
[02:39:46] [PASSED] 24 VFs
[02:39:46] [PASSED] 25 VFs
[02:39:46] [PASSED] 26 VFs
[02:39:46] [PASSED] 27 VFs
[02:39:46] [PASSED] 28 VFs
[02:39:46] [PASSED] 29 VFs
[02:39:46] [PASSED] 30 VFs
[02:39:46] [PASSED] 31 VFs
[02:39:46] [PASSED] 32 VFs
[02:39:46] [PASSED] 33 VFs
[02:39:46] [PASSED] 34 VFs
[02:39:46] [PASSED] 35 VFs
[02:39:46] [PASSED] 36 VFs
[02:39:46] [PASSED] 37 VFs
[02:39:46] [PASSED] 38 VFs
[02:39:46] [PASSED] 39 VFs
[02:39:46] [PASSED] 40 VFs
[02:39:46] [PASSED] 41 VFs
[02:39:46] [PASSED] 42 VFs
[02:39:46] [PASSED] 43 VFs
[02:39:46] [PASSED] 44 VFs
[02:39:46] [PASSED] 45 VFs
[02:39:46] [PASSED] 46 VFs
[02:39:46] [PASSED] 47 VFs
[02:39:46] [PASSED] 48 VFs
[02:39:46] [PASSED] 49 VFs
[02:39:46] [PASSED] 50 VFs
[02:39:46] [PASSED] 51 VFs
[02:39:46] [PASSED] 52 VFs
[02:39:46] [PASSED] 53 VFs
[02:39:46] [PASSED] 54 VFs
[02:39:46] [PASSED] 55 VFs
[02:39:46] [PASSED] 56 VFs
[02:39:46] [PASSED] 57 VFs
[02:39:46] [PASSED] 58 VFs
[02:39:46] [PASSED] 59 VFs
[02:39:46] [PASSED] 60 VFs
[02:39:46] [PASSED] 61 VFs
[02:39:46] [PASSED] 62 VFs
[02:39:46] [PASSED] 63 VFs
[02:39:46] ================= [PASSED] fair_doorbells ==================
[02:39:46] ======================== fair_ggtt ========================
[02:39:46] [PASSED] 1 VF
[02:39:46] [PASSED] 2 VFs
[02:39:46] [PASSED] 3 VFs
[02:39:46] [PASSED] 4 VFs
[02:39:46] [PASSED] 5 VFs
[02:39:46] [PASSED] 6 VFs
[02:39:46] [PASSED] 7 VFs
[02:39:46] [PASSED] 8 VFs
[02:39:46] [PASSED] 9 VFs
[02:39:46] [PASSED] 10 VFs
[02:39:46] [PASSED] 11 VFs
[02:39:46] [PASSED] 12 VFs
[02:39:46] [PASSED] 13 VFs
[02:39:46] [PASSED] 14 VFs
[02:39:46] [PASSED] 15 VFs
[02:39:46] [PASSED] 16 VFs
[02:39:46] [PASSED] 17 VFs
[02:39:46] [PASSED] 18 VFs
[02:39:46] [PASSED] 19 VFs
[02:39:46] [PASSED] 20 VFs
[02:39:46] [PASSED] 21 VFs
[02:39:46] [PASSED] 22 VFs
[02:39:46] [PASSED] 23 VFs
[02:39:46] [PASSED] 24 VFs
[02:39:46] [PASSED] 25 VFs
[02:39:46] [PASSED] 26 VFs
[02:39:46] [PASSED] 27 VFs
[02:39:46] [PASSED] 28 VFs
[02:39:46] [PASSED] 29 VFs
[02:39:46] [PASSED] 30 VFs
[02:39:46] [PASSED] 31 VFs
[02:39:46] [PASSED] 32 VFs
[02:39:46] [PASSED] 33 VFs
[02:39:46] [PASSED] 34 VFs
[02:39:46] [PASSED] 35 VFs
[02:39:46] [PASSED] 36 VFs
[02:39:46] [PASSED] 37 VFs
[02:39:46] [PASSED] 38 VFs
[02:39:46] [PASSED] 39 VFs
[02:39:46] [PASSED] 40 VFs
[02:39:46] [PASSED] 41 VFs
[02:39:46] [PASSED] 42 VFs
[02:39:46] [PASSED] 43 VFs
[02:39:46] [PASSED] 44 VFs
[02:39:46] [PASSED] 45 VFs
[02:39:46] [PASSED] 46 VFs
[02:39:46] [PASSED] 47 VFs
[02:39:46] [PASSED] 48 VFs
[02:39:46] [PASSED] 49 VFs
[02:39:46] [PASSED] 50 VFs
[02:39:46] [PASSED] 51 VFs
[02:39:46] [PASSED] 52 VFs
[02:39:46] [PASSED] 53 VFs
[02:39:46] [PASSED] 54 VFs
[02:39:46] [PASSED] 55 VFs
[02:39:46] [PASSED] 56 VFs
[02:39:46] [PASSED] 57 VFs
[02:39:46] [PASSED] 58 VFs
[02:39:46] [PASSED] 59 VFs
[02:39:46] [PASSED] 60 VFs
[02:39:46] [PASSED] 61 VFs
[02:39:46] [PASSED] 62 VFs
[02:39:46] [PASSED] 63 VFs
[02:39:46] ==================== [PASSED] fair_ggtt ====================
[02:39:46] ======================== fair_vram ========================
[02:39:46] [PASSED] 1 VF
[02:39:46] [PASSED] 2 VFs
[02:39:46] [PASSED] 3 VFs
[02:39:46] [PASSED] 4 VFs
[02:39:46] [PASSED] 5 VFs
[02:39:46] [PASSED] 6 VFs
[02:39:46] [PASSED] 7 VFs
[02:39:46] [PASSED] 8 VFs
[02:39:46] [PASSED] 9 VFs
[02:39:46] [PASSED] 10 VFs
[02:39:46] [PASSED] 11 VFs
[02:39:46] [PASSED] 12 VFs
[02:39:46] [PASSED] 13 VFs
[02:39:46] [PASSED] 14 VFs
[02:39:46] [PASSED] 15 VFs
[02:39:46] [PASSED] 16 VFs
[02:39:46] [PASSED] 17 VFs
[02:39:46] [PASSED] 18 VFs
[02:39:46] [PASSED] 19 VFs
[02:39:46] [PASSED] 20 VFs
[02:39:46] [PASSED] 21 VFs
[02:39:46] [PASSED] 22 VFs
[02:39:46] [PASSED] 23 VFs
[02:39:46] [PASSED] 24 VFs
[02:39:46] [PASSED] 25 VFs
[02:39:46] [PASSED] 26 VFs
[02:39:46] [PASSED] 27 VFs
[02:39:46] [PASSED] 28 VFs
[02:39:46] [PASSED] 29 VFs
[02:39:46] [PASSED] 30 VFs
[02:39:46] [PASSED] 31 VFs
[02:39:46] [PASSED] 32 VFs
[02:39:46] [PASSED] 33 VFs
[02:39:46] [PASSED] 34 VFs
[02:39:46] [PASSED] 35 VFs
[02:39:46] [PASSED] 36 VFs
[02:39:46] [PASSED] 37 VFs
[02:39:46] [PASSED] 38 VFs
[02:39:46] [PASSED] 39 VFs
[02:39:46] [PASSED] 40 VFs
[02:39:46] [PASSED] 41 VFs
[02:39:46] [PASSED] 42 VFs
[02:39:46] [PASSED] 43 VFs
[02:39:46] [PASSED] 44 VFs
[02:39:46] [PASSED] 45 VFs
[02:39:46] [PASSED] 46 VFs
[02:39:46] [PASSED] 47 VFs
[02:39:46] [PASSED] 48 VFs
[02:39:46] [PASSED] 49 VFs
[02:39:46] [PASSED] 50 VFs
[02:39:46] [PASSED] 51 VFs
[02:39:46] [PASSED] 52 VFs
[02:39:46] [PASSED] 53 VFs
[02:39:46] [PASSED] 54 VFs
[02:39:46] [PASSED] 55 VFs
[02:39:46] [PASSED] 56 VFs
[02:39:46] [PASSED] 57 VFs
[02:39:46] [PASSED] 58 VFs
[02:39:46] [PASSED] 59 VFs
[02:39:46] [PASSED] 60 VFs
[02:39:46] [PASSED] 61 VFs
[02:39:46] [PASSED] 62 VFs
[02:39:46] [PASSED] 63 VFs
[02:39:46] ==================== [PASSED] fair_vram ====================
[02:39:46] ================== [PASSED] pf_gt_config ===================
[02:39:46] ===================== lmtt (1 subtest) =====================
[02:39:46] ======================== test_ops =========================
[02:39:46] [PASSED] 2-level
[02:39:46] [PASSED] multi-level
[02:39:46] ==================== [PASSED] test_ops =====================
[02:39:46] ====================== [PASSED] lmtt =======================
[02:39:46] ================= pf_service (11 subtests) =================
[02:39:46] [PASSED] pf_negotiate_any
[02:39:46] [PASSED] pf_negotiate_base_match
[02:39:46] [PASSED] pf_negotiate_base_newer
[02:39:46] [PASSED] pf_negotiate_base_next
[02:39:46] [SKIPPED] pf_negotiate_base_older
[02:39:46] [PASSED] pf_negotiate_base_prev
[02:39:46] [PASSED] pf_negotiate_latest_match
[02:39:46] [PASSED] pf_negotiate_latest_newer
[02:39:46] [PASSED] pf_negotiate_latest_next
[02:39:46] [SKIPPED] pf_negotiate_latest_older
[02:39:46] [SKIPPED] pf_negotiate_latest_prev
[02:39:46] =================== [PASSED] pf_service ====================
[02:39:46] ================= xe_guc_g2g (2 subtests) ==================
[02:39:46] ============== xe_live_guc_g2g_kunit_default ==============
[02:39:46] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[02:39:46] ============== xe_live_guc_g2g_kunit_allmem ===============
[02:39:46] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[02:39:46] =================== [SKIPPED] xe_guc_g2g ===================
[02:39:46] =================== xe_mocs (2 subtests) ===================
[02:39:46] ================ xe_live_mocs_kernel_kunit ================
[02:39:46] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[02:39:46] ================ xe_live_mocs_reset_kunit =================
[02:39:46] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[02:39:46] ==================== [SKIPPED] xe_mocs =====================
[02:39:46] ================= xe_migrate (2 subtests) ==================
[02:39:46] ================= xe_migrate_sanity_kunit =================
[02:39:46] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[02:39:46] ================== xe_validate_ccs_kunit ==================
[02:39:46] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[02:39:46] =================== [SKIPPED] xe_migrate ===================
[02:39:46] ================== xe_dma_buf (1 subtest) ==================
[02:39:46] ==================== xe_dma_buf_kunit =====================
[02:39:46] ================ [SKIPPED] xe_dma_buf_kunit ================
[02:39:46] =================== [SKIPPED] xe_dma_buf ===================
[02:39:46] ================= xe_bo_shrink (1 subtest) =================
[02:39:46] =================== xe_bo_shrink_kunit ====================
[02:39:46] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[02:39:46] ================== [SKIPPED] xe_bo_shrink ==================
[02:39:46] ==================== xe_bo (2 subtests) ====================
[02:39:46] ================== xe_ccs_migrate_kunit ===================
[02:39:46] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[02:39:46] ==================== xe_bo_evict_kunit ====================
[02:39:46] =============== [SKIPPED] xe_bo_evict_kunit ================
[02:39:46] ===================== [SKIPPED] xe_bo ======================
[02:39:46] ==================== args (13 subtests) ====================
[02:39:46] [PASSED] count_args_test
[02:39:46] [PASSED] call_args_example
[02:39:46] [PASSED] call_args_test
[02:39:46] [PASSED] drop_first_arg_example
[02:39:46] [PASSED] drop_first_arg_test
[02:39:46] [PASSED] first_arg_example
[02:39:46] [PASSED] first_arg_test
[02:39:46] [PASSED] last_arg_example
[02:39:46] [PASSED] last_arg_test
[02:39:46] [PASSED] pick_arg_example
[02:39:46] [PASSED] if_args_example
[02:39:46] [PASSED] if_args_test
[02:39:46] [PASSED] sep_comma_example
[02:39:46] ====================== [PASSED] args =======================
[02:39:46] =================== xe_pci (3 subtests) ====================
[02:39:46] ==================== check_graphics_ip ====================
[02:39:46] [PASSED] 12.00 Xe_LP
[02:39:46] [PASSED] 12.10 Xe_LP+
[02:39:46] [PASSED] 12.55 Xe_HPG
[02:39:46] [PASSED] 12.60 Xe_HPC
[02:39:46] [PASSED] 12.70 Xe_LPG
[02:39:46] [PASSED] 12.71 Xe_LPG
[02:39:46] [PASSED] 12.74 Xe_LPG+
[02:39:46] [PASSED] 20.01 Xe2_HPG
[02:39:46] [PASSED] 20.02 Xe2_HPG
[02:39:46] [PASSED] 20.04 Xe2_LPG
[02:39:46] [PASSED] 30.00 Xe3_LPG
[02:39:46] [PASSED] 30.01 Xe3_LPG
[02:39:46] [PASSED] 30.03 Xe3_LPG
[02:39:46] [PASSED] 30.04 Xe3_LPG
[02:39:46] [PASSED] 30.05 Xe3_LPG
[02:39:46] [PASSED] 35.10 Xe3p_LPG
[02:39:46] [PASSED] 35.11 Xe3p_XPC
[02:39:46] ================ [PASSED] check_graphics_ip ================
[02:39:46] ===================== check_media_ip ======================
[02:39:46] [PASSED] 12.00 Xe_M
[02:39:46] [PASSED] 12.55 Xe_HPM
[02:39:46] [PASSED] 13.00 Xe_LPM+
[02:39:46] [PASSED] 13.01 Xe2_HPM
[02:39:46] [PASSED] 20.00 Xe2_LPM
[02:39:46] [PASSED] 30.00 Xe3_LPM
[02:39:46] [PASSED] 30.02 Xe3_LPM
[02:39:46] [PASSED] 35.00 Xe3p_LPM
[02:39:46] [PASSED] 35.03 Xe3p_HPM
[02:39:46] ================= [PASSED] check_media_ip ==================
[02:39:46] =================== check_platform_desc ===================
[02:39:46] [PASSED] 0x9A60 (TIGERLAKE)
[02:39:46] [PASSED] 0x9A68 (TIGERLAKE)
[02:39:46] [PASSED] 0x9A70 (TIGERLAKE)
[02:39:46] [PASSED] 0x9A40 (TIGERLAKE)
[02:39:46] [PASSED] 0x9A49 (TIGERLAKE)
[02:39:46] [PASSED] 0x9A59 (TIGERLAKE)
[02:39:46] [PASSED] 0x9A78 (TIGERLAKE)
[02:39:46] [PASSED] 0x9AC0 (TIGERLAKE)
[02:39:46] [PASSED] 0x9AC9 (TIGERLAKE)
[02:39:46] [PASSED] 0x9AD9 (TIGERLAKE)
[02:39:46] [PASSED] 0x9AF8 (TIGERLAKE)
[02:39:46] [PASSED] 0x4C80 (ROCKETLAKE)
[02:39:46] [PASSED] 0x4C8A (ROCKETLAKE)
[02:39:46] [PASSED] 0x4C8B (ROCKETLAKE)
[02:39:46] [PASSED] 0x4C8C (ROCKETLAKE)
[02:39:46] [PASSED] 0x4C90 (ROCKETLAKE)
[02:39:46] [PASSED] 0x4C9A (ROCKETLAKE)
[02:39:46] [PASSED] 0x4680 (ALDERLAKE_S)
[02:39:46] [PASSED] 0x4682 (ALDERLAKE_S)
[02:39:46] [PASSED] 0x4688 (ALDERLAKE_S)
[02:39:46] [PASSED] 0x468A (ALDERLAKE_S)
[02:39:46] [PASSED] 0x468B (ALDERLAKE_S)
[02:39:46] [PASSED] 0x4690 (ALDERLAKE_S)
[02:39:46] [PASSED] 0x4692 (ALDERLAKE_S)
[02:39:46] [PASSED] 0x4693 (ALDERLAKE_S)
[02:39:46] [PASSED] 0x46A0 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46A1 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46A2 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46A3 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46A6 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46A8 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46AA (ALDERLAKE_P)
[02:39:46] [PASSED] 0x462A (ALDERLAKE_P)
[02:39:46] [PASSED] 0x4626 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x4628 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46B0 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46B1 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46B2 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46B3 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46C0 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46C1 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46C2 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46C3 (ALDERLAKE_P)
[02:39:46] [PASSED] 0x46D0 (ALDERLAKE_N)
[02:39:46] [PASSED] 0x46D1 (ALDERLAKE_N)
[02:39:46] [PASSED] 0x46D2 (ALDERLAKE_N)
[02:39:46] [PASSED] 0x46D3 (ALDERLAKE_N)
[02:39:46] [PASSED] 0x46D4 (ALDERLAKE_N)
[02:39:46] [PASSED] 0xA721 (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7A1 (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7A9 (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7AC (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7AD (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA720 (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7A0 (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7A8 (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7AA (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA7AB (ALDERLAKE_P)
[02:39:46] [PASSED] 0xA780 (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA781 (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA782 (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA783 (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA788 (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA789 (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA78A (ALDERLAKE_S)
[02:39:46] [PASSED] 0xA78B (ALDERLAKE_S)
[02:39:46] [PASSED] 0x4905 (DG1)
[02:39:46] [PASSED] 0x4906 (DG1)
[02:39:46] [PASSED] 0x4907 (DG1)
[02:39:46] [PASSED] 0x4908 (DG1)
[02:39:46] [PASSED] 0x4909 (DG1)
[02:39:46] [PASSED] 0x56C0 (DG2)
[02:39:46] [PASSED] 0x56C2 (DG2)
[02:39:46] [PASSED] 0x56C1 (DG2)
[02:39:46] [PASSED] 0x7D51 (METEORLAKE)
[02:39:46] [PASSED] 0x7DD1 (METEORLAKE)
[02:39:46] [PASSED] 0x7D41 (METEORLAKE)
[02:39:46] [PASSED] 0x7D67 (METEORLAKE)
[02:39:46] [PASSED] 0xB640 (METEORLAKE)
[02:39:46] [PASSED] 0x56A0 (DG2)
[02:39:46] [PASSED] 0x56A1 (DG2)
[02:39:46] [PASSED] 0x56A2 (DG2)
[02:39:46] [PASSED] 0x56BE (DG2)
[02:39:46] [PASSED] 0x56BF (DG2)
[02:39:46] [PASSED] 0x5690 (DG2)
[02:39:46] [PASSED] 0x5691 (DG2)
[02:39:46] [PASSED] 0x5692 (DG2)
[02:39:46] [PASSED] 0x56A5 (DG2)
[02:39:46] [PASSED] 0x56A6 (DG2)
[02:39:46] [PASSED] 0x56B0 (DG2)
[02:39:46] [PASSED] 0x56B1 (DG2)
[02:39:46] [PASSED] 0x56BA (DG2)
[02:39:46] [PASSED] 0x56BB (DG2)
[02:39:46] [PASSED] 0x56BC (DG2)
[02:39:46] [PASSED] 0x56BD (DG2)
[02:39:46] [PASSED] 0x5693 (DG2)
[02:39:46] [PASSED] 0x5694 (DG2)
[02:39:46] [PASSED] 0x5695 (DG2)
[02:39:46] [PASSED] 0x56A3 (DG2)
[02:39:46] [PASSED] 0x56A4 (DG2)
[02:39:46] [PASSED] 0x56B2 (DG2)
[02:39:46] [PASSED] 0x56B3 (DG2)
[02:39:46] [PASSED] 0x5696 (DG2)
[02:39:46] [PASSED] 0x5697 (DG2)
[02:39:46] [PASSED] 0xB69 (PVC)
[02:39:46] [PASSED] 0xB6E (PVC)
[02:39:46] [PASSED] 0xBD4 (PVC)
[02:39:46] [PASSED] 0xBD5 (PVC)
[02:39:46] [PASSED] 0xBD6 (PVC)
[02:39:46] [PASSED] 0xBD7 (PVC)
[02:39:46] [PASSED] 0xBD8 (PVC)
[02:39:46] [PASSED] 0xBD9 (PVC)
[02:39:46] [PASSED] 0xBDA (PVC)
[02:39:46] [PASSED] 0xBDB (PVC)
[02:39:46] [PASSED] 0xBE0 (PVC)
[02:39:46] [PASSED] 0xBE1 (PVC)
[02:39:46] [PASSED] 0xBE5 (PVC)
[02:39:46] [PASSED] 0x7D40 (METEORLAKE)
[02:39:46] [PASSED] 0x7D45 (METEORLAKE)
[02:39:46] [PASSED] 0x7D55 (METEORLAKE)
[02:39:46] [PASSED] 0x7D60 (METEORLAKE)
[02:39:46] [PASSED] 0x7DD5 (METEORLAKE)
[02:39:46] [PASSED] 0x6420 (LUNARLAKE)
[02:39:46] [PASSED] 0x64A0 (LUNARLAKE)
[02:39:46] [PASSED] 0x64B0 (LUNARLAKE)
[02:39:46] [PASSED] 0xE202 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE209 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE20B (BATTLEMAGE)
[02:39:46] [PASSED] 0xE20C (BATTLEMAGE)
[02:39:46] [PASSED] 0xE20D (BATTLEMAGE)
[02:39:46] [PASSED] 0xE210 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE211 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE212 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE216 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE220 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE221 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE222 (BATTLEMAGE)
[02:39:46] [PASSED] 0xE223 (BATTLEMAGE)
[02:39:46] [PASSED] 0xB080 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB081 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB082 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB083 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB084 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB085 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB086 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB087 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB08F (PANTHERLAKE)
[02:39:46] [PASSED] 0xB090 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB0A0 (PANTHERLAKE)
[02:39:46] [PASSED] 0xB0B0 (PANTHERLAKE)
[02:39:46] [PASSED] 0xFD80 (PANTHERLAKE)
[02:39:46] [PASSED] 0xFD81 (PANTHERLAKE)
[02:39:46] [PASSED] 0xD740 (NOVALAKE_S)
[02:39:46] [PASSED] 0xD741 (NOVALAKE_S)
[02:39:46] [PASSED] 0xD742 (NOVALAKE_S)
[02:39:46] [PASSED] 0xD743 (NOVALAKE_S)
[02:39:46] [PASSED] 0xD744 (NOVALAKE_S)
[02:39:46] [PASSED] 0xD745 (NOVALAKE_S)
[02:39:46] [PASSED] 0x674C (CRESCENTISLAND)
[02:39:46] [PASSED] 0xD750 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD751 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD752 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD753 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD754 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD755 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD756 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD757 (NOVALAKE_P)
[02:39:46] [PASSED] 0xD75F (NOVALAKE_P)
[02:39:46] =============== [PASSED] check_platform_desc ===============
[02:39:46] ===================== [PASSED] xe_pci ======================
[02:39:46] =================== xe_rtp (2 subtests) ====================
[02:39:46] =============== xe_rtp_process_to_sr_tests ================
[02:39:46] [PASSED] coalesce-same-reg
[02:39:46] [PASSED] no-match-no-add
[02:39:46] [PASSED] match-or
[02:39:46] [PASSED] match-or-xfail
[02:39:46] [PASSED] no-match-no-add-multiple-rules
[02:39:46] [PASSED] two-regs-two-entries
[02:39:46] [PASSED] clr-one-set-other
[02:39:46] [PASSED] set-field
[02:39:46] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[02:39:46] [PASSED] conflict-not-disjoint
[02:39:46] [PASSED] conflict-reg-type
[02:39:46] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[02:39:46] ================== xe_rtp_process_tests ===================
[02:39:46] [PASSED] active1
[02:39:46] [PASSED] active2
[02:39:46] [PASSED] active-inactive
[02:39:46] [PASSED] inactive-active
[02:39:46] [PASSED] inactive-1st_or_active-inactive
[02:39:46] [PASSED] inactive-2nd_or_active-inactive
[02:39:46] [PASSED] inactive-last_or_active-inactive
[02:39:46] [PASSED] inactive-no_or_active-inactive
[02:39:46] ============== [PASSED] xe_rtp_process_tests ===============
[02:39:46] ===================== [PASSED] xe_rtp ======================
[02:39:46] ==================== xe_wa (1 subtest) =====================
[02:39:46] ======================== xe_wa_gt =========================
[02:39:46] [PASSED] TIGERLAKE B0
[02:39:46] [PASSED] DG1 A0
[02:39:46] [PASSED] DG1 B0
[02:39:46] [PASSED] ALDERLAKE_S A0
[02:39:46] [PASSED] ALDERLAKE_S B0
[02:39:46] [PASSED] ALDERLAKE_S C0
[02:39:46] [PASSED] ALDERLAKE_S D0
[02:39:46] [PASSED] ALDERLAKE_P A0
[02:39:46] [PASSED] ALDERLAKE_P B0
[02:39:46] [PASSED] ALDERLAKE_P C0
[02:39:46] [PASSED] ALDERLAKE_S RPLS D0
[02:39:46] [PASSED] ALDERLAKE_P RPLU E0
[02:39:46] [PASSED] DG2 G10 C0
[02:39:46] [PASSED] DG2 G11 B1
[02:39:46] [PASSED] DG2 G12 A1
[02:39:46] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:39:46] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[02:39:46] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[02:39:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[02:39:46] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[02:39:46] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[02:39:46] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[02:39:46] ==================== [PASSED] xe_wa_gt =====================
[02:39:46] ====================== [PASSED] xe_wa ======================
[02:39:46] ============================================================
[02:39:46] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[02:39:46] Elapsed time: 35.297s total, 4.206s configuring, 30.424s building, 0.614s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[02:39:46] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:39:48] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:40:12] Starting KUnit Kernel (1/1)...
[02:40:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:40:12] ============ drm_test_pick_cmdline (2 subtests) ============
[02:40:12] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[02:40:12] =============== drm_test_pick_cmdline_named ===============
[02:40:12] [PASSED] NTSC
[02:40:12] [PASSED] NTSC-J
[02:40:12] [PASSED] PAL
[02:40:12] [PASSED] PAL-M
[02:40:12] =========== [PASSED] drm_test_pick_cmdline_named ===========
[02:40:12] ============== [PASSED] drm_test_pick_cmdline ==============
[02:40:12] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[02:40:12] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[02:40:12] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[02:40:12] =========== drm_validate_clone_mode (2 subtests) ===========
[02:40:12] ============== drm_test_check_in_clone_mode ===============
[02:40:12] [PASSED] in_clone_mode
[02:40:12] [PASSED] not_in_clone_mode
[02:40:12] ========== [PASSED] drm_test_check_in_clone_mode ===========
[02:40:12] =============== drm_test_check_valid_clones ===============
[02:40:12] [PASSED] not_in_clone_mode
[02:40:12] [PASSED] valid_clone
[02:40:12] [PASSED] invalid_clone
[02:40:12] =========== [PASSED] drm_test_check_valid_clones ===========
[02:40:12] ============= [PASSED] drm_validate_clone_mode =============
[02:40:12] ============= drm_validate_modeset (1 subtest) =============
[02:40:12] [PASSED] drm_test_check_connector_changed_modeset
[02:40:12] ============== [PASSED] drm_validate_modeset ===============
[02:40:12] ====== drm_test_bridge_get_current_state (2 subtests) ======
[02:40:12] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[02:40:12] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[02:40:12] ======== [PASSED] drm_test_bridge_get_current_state ========
[02:40:12] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[02:40:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[02:40:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[02:40:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[02:40:12] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[02:40:12] ============== drm_bridge_alloc (2 subtests) ===============
[02:40:12] [PASSED] drm_test_drm_bridge_alloc_basic
[02:40:12] [PASSED] drm_test_drm_bridge_alloc_get_put
[02:40:12] ================ [PASSED] drm_bridge_alloc =================
[02:40:12] ============= drm_cmdline_parser (40 subtests) =============
[02:40:12] [PASSED] drm_test_cmdline_force_d_only
[02:40:12] [PASSED] drm_test_cmdline_force_D_only_dvi
[02:40:12] [PASSED] drm_test_cmdline_force_D_only_hdmi
[02:40:12] [PASSED] drm_test_cmdline_force_D_only_not_digital
[02:40:12] [PASSED] drm_test_cmdline_force_e_only
[02:40:12] [PASSED] drm_test_cmdline_res
[02:40:12] [PASSED] drm_test_cmdline_res_vesa
[02:40:12] [PASSED] drm_test_cmdline_res_vesa_rblank
[02:40:12] [PASSED] drm_test_cmdline_res_rblank
[02:40:12] [PASSED] drm_test_cmdline_res_bpp
[02:40:12] [PASSED] drm_test_cmdline_res_refresh
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[02:40:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[02:40:12] [PASSED] drm_test_cmdline_res_margins_force_on
[02:40:12] [PASSED] drm_test_cmdline_res_vesa_margins
[02:40:12] [PASSED] drm_test_cmdline_name
[02:40:12] [PASSED] drm_test_cmdline_name_bpp
[02:40:12] [PASSED] drm_test_cmdline_name_option
[02:40:12] [PASSED] drm_test_cmdline_name_bpp_option
[02:40:12] [PASSED] drm_test_cmdline_rotate_0
[02:40:12] [PASSED] drm_test_cmdline_rotate_90
[02:40:12] [PASSED] drm_test_cmdline_rotate_180
[02:40:12] [PASSED] drm_test_cmdline_rotate_270
[02:40:12] [PASSED] drm_test_cmdline_hmirror
[02:40:12] [PASSED] drm_test_cmdline_vmirror
[02:40:12] [PASSED] drm_test_cmdline_margin_options
[02:40:12] [PASSED] drm_test_cmdline_multiple_options
[02:40:12] [PASSED] drm_test_cmdline_bpp_extra_and_option
[02:40:12] [PASSED] drm_test_cmdline_extra_and_option
[02:40:12] [PASSED] drm_test_cmdline_freestanding_options
[02:40:12] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[02:40:12] [PASSED] drm_test_cmdline_panel_orientation
[02:40:12] ================ drm_test_cmdline_invalid =================
[02:40:12] [PASSED] margin_only
[02:40:12] [PASSED] interlace_only
[02:40:12] [PASSED] res_missing_x
[02:40:12] [PASSED] res_missing_y
[02:40:12] [PASSED] res_bad_y
[02:40:12] [PASSED] res_missing_y_bpp
[02:40:12] [PASSED] res_bad_bpp
[02:40:12] [PASSED] res_bad_refresh
[02:40:12] [PASSED] res_bpp_refresh_force_on_off
[02:40:12] [PASSED] res_invalid_mode
[02:40:12] [PASSED] res_bpp_wrong_place_mode
[02:40:12] [PASSED] name_bpp_refresh
[02:40:12] [PASSED] name_refresh
[02:40:12] [PASSED] name_refresh_wrong_mode
[02:40:12] [PASSED] name_refresh_invalid_mode
[02:40:12] [PASSED] rotate_multiple
[02:40:12] [PASSED] rotate_invalid_val
[02:40:12] [PASSED] rotate_truncated
[02:40:12] [PASSED] invalid_option
[02:40:12] [PASSED] invalid_tv_option
[02:40:12] [PASSED] truncated_tv_option
[02:40:12] ============ [PASSED] drm_test_cmdline_invalid =============
[02:40:12] =============== drm_test_cmdline_tv_options ===============
[02:40:12] [PASSED] NTSC
[02:40:12] [PASSED] NTSC_443
[02:40:12] [PASSED] NTSC_J
[02:40:12] [PASSED] PAL
[02:40:12] [PASSED] PAL_M
[02:40:12] [PASSED] PAL_N
[02:40:12] [PASSED] SECAM
[02:40:12] [PASSED] MONO_525
[02:40:12] [PASSED] MONO_625
[02:40:12] =========== [PASSED] drm_test_cmdline_tv_options ===========
[02:40:12] =============== [PASSED] drm_cmdline_parser ================
[02:40:12] ========== drmm_connector_hdmi_init (20 subtests) ==========
[02:40:12] [PASSED] drm_test_connector_hdmi_init_valid
[02:40:12] [PASSED] drm_test_connector_hdmi_init_bpc_8
[02:40:12] [PASSED] drm_test_connector_hdmi_init_bpc_10
[02:40:12] [PASSED] drm_test_connector_hdmi_init_bpc_12
[02:40:12] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[02:40:12] [PASSED] drm_test_connector_hdmi_init_bpc_null
[02:40:12] [PASSED] drm_test_connector_hdmi_init_formats_empty
[02:40:12] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[02:40:12] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[02:40:12] [PASSED] supported_formats=0x9 yuv420_allowed=1
[02:40:12] [PASSED] supported_formats=0x9 yuv420_allowed=0
[02:40:12] [PASSED] supported_formats=0x3 yuv420_allowed=1
[02:40:12] [PASSED] supported_formats=0x3 yuv420_allowed=0
[02:40:12] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[02:40:12] [PASSED] drm_test_connector_hdmi_init_null_ddc
[02:40:12] [PASSED] drm_test_connector_hdmi_init_null_product
[02:40:12] [PASSED] drm_test_connector_hdmi_init_null_vendor
[02:40:12] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[02:40:12] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[02:40:12] [PASSED] drm_test_connector_hdmi_init_product_valid
[02:40:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[02:40:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[02:40:12] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[02:40:12] ========= drm_test_connector_hdmi_init_type_valid =========
[02:40:12] [PASSED] HDMI-A
[02:40:12] [PASSED] HDMI-B
[02:40:12] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[02:40:12] ======== drm_test_connector_hdmi_init_type_invalid ========
[02:40:12] [PASSED] Unknown
[02:40:12] [PASSED] VGA
[02:40:12] [PASSED] DVI-I
[02:40:12] [PASSED] DVI-D
[02:40:12] [PASSED] DVI-A
[02:40:12] [PASSED] Composite
[02:40:12] [PASSED] SVIDEO
[02:40:12] [PASSED] LVDS
[02:40:12] [PASSED] Component
[02:40:12] [PASSED] DIN
[02:40:12] [PASSED] DP
[02:40:12] [PASSED] TV
[02:40:12] [PASSED] eDP
[02:40:12] [PASSED] Virtual
[02:40:12] [PASSED] DSI
[02:40:12] [PASSED] DPI
[02:40:12] [PASSED] Writeback
[02:40:12] [PASSED] SPI
[02:40:12] [PASSED] USB
[02:40:12] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[02:40:12] ============ [PASSED] drmm_connector_hdmi_init =============
[02:40:12] ============= drmm_connector_init (3 subtests) =============
[02:40:12] [PASSED] drm_test_drmm_connector_init
[02:40:12] [PASSED] drm_test_drmm_connector_init_null_ddc
[02:40:12] ========= drm_test_drmm_connector_init_type_valid =========
[02:40:12] [PASSED] Unknown
[02:40:12] [PASSED] VGA
[02:40:12] [PASSED] DVI-I
[02:40:12] [PASSED] DVI-D
[02:40:12] [PASSED] DVI-A
[02:40:12] [PASSED] Composite
[02:40:12] [PASSED] SVIDEO
[02:40:12] [PASSED] LVDS
[02:40:12] [PASSED] Component
[02:40:12] [PASSED] DIN
[02:40:12] [PASSED] DP
[02:40:12] [PASSED] HDMI-A
[02:40:12] [PASSED] HDMI-B
[02:40:12] [PASSED] TV
[02:40:12] [PASSED] eDP
[02:40:12] [PASSED] Virtual
[02:40:12] [PASSED] DSI
[02:40:12] [PASSED] DPI
[02:40:12] [PASSED] Writeback
[02:40:12] [PASSED] SPI
[02:40:12] [PASSED] USB
[02:40:12] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[02:40:12] =============== [PASSED] drmm_connector_init ===============
[02:40:12] ========= drm_connector_dynamic_init (6 subtests) ==========
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_init
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_init_properties
[02:40:12] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[02:40:12] [PASSED] Unknown
[02:40:12] [PASSED] VGA
[02:40:12] [PASSED] DVI-I
[02:40:12] [PASSED] DVI-D
[02:40:12] [PASSED] DVI-A
[02:40:12] [PASSED] Composite
[02:40:12] [PASSED] SVIDEO
[02:40:12] [PASSED] LVDS
[02:40:12] [PASSED] Component
[02:40:12] [PASSED] DIN
[02:40:12] [PASSED] DP
[02:40:12] [PASSED] HDMI-A
[02:40:12] [PASSED] HDMI-B
[02:40:12] [PASSED] TV
[02:40:12] [PASSED] eDP
[02:40:12] [PASSED] Virtual
[02:40:12] [PASSED] DSI
[02:40:12] [PASSED] DPI
[02:40:12] [PASSED] Writeback
[02:40:12] [PASSED] SPI
[02:40:12] [PASSED] USB
[02:40:12] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[02:40:12] ======== drm_test_drm_connector_dynamic_init_name =========
[02:40:12] [PASSED] Unknown
[02:40:12] [PASSED] VGA
[02:40:12] [PASSED] DVI-I
[02:40:12] [PASSED] DVI-D
[02:40:12] [PASSED] DVI-A
[02:40:12] [PASSED] Composite
[02:40:12] [PASSED] SVIDEO
[02:40:12] [PASSED] LVDS
[02:40:12] [PASSED] Component
[02:40:12] [PASSED] DIN
[02:40:12] [PASSED] DP
[02:40:12] [PASSED] HDMI-A
[02:40:12] [PASSED] HDMI-B
[02:40:12] [PASSED] TV
[02:40:12] [PASSED] eDP
[02:40:12] [PASSED] Virtual
[02:40:12] [PASSED] DSI
[02:40:12] [PASSED] DPI
[02:40:12] [PASSED] Writeback
[02:40:12] [PASSED] SPI
[02:40:12] [PASSED] USB
[02:40:12] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[02:40:12] =========== [PASSED] drm_connector_dynamic_init ============
[02:40:12] ==== drm_connector_dynamic_register_early (4 subtests) =====
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[02:40:12] ====== [PASSED] drm_connector_dynamic_register_early =======
[02:40:12] ======= drm_connector_dynamic_register (7 subtests) ========
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[02:40:12] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[02:40:12] ========= [PASSED] drm_connector_dynamic_register ==========
[02:40:12] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[02:40:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[02:40:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[02:40:12] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[02:40:12] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[02:40:12] ========== drm_test_get_tv_mode_from_name_valid ===========
[02:40:12] [PASSED] NTSC
[02:40:12] [PASSED] NTSC-443
[02:40:12] [PASSED] NTSC-J
[02:40:12] [PASSED] PAL
[02:40:12] [PASSED] PAL-M
[02:40:12] [PASSED] PAL-N
[02:40:12] [PASSED] SECAM
[02:40:12] [PASSED] Mono
[02:40:12] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[02:40:12] [PASSED] drm_test_get_tv_mode_from_name_truncated
[02:40:12] ============ [PASSED] drm_get_tv_mode_from_name ============
[02:40:12] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[02:40:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[02:40:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[02:40:13] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[02:40:13] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[02:40:13] [PASSED] VIC 96
[02:40:13] [PASSED] VIC 97
[02:40:13] [PASSED] VIC 101
[02:40:13] [PASSED] VIC 102
[02:40:13] [PASSED] VIC 106
[02:40:13] [PASSED] VIC 107
[02:40:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[02:40:13] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[02:40:13] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[02:40:13] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[02:40:13] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[02:40:13] [PASSED] Automatic
[02:40:13] [PASSED] Full
[02:40:13] [PASSED] Limited 16:235
[02:40:13] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[02:40:13] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[02:40:13] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[02:40:13] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[02:40:13] === drm_test_drm_hdmi_connector_get_output_format_name ====
[02:40:13] [PASSED] RGB
[02:40:13] [PASSED] YUV 4:2:0
[02:40:13] [PASSED] YUV 4:2:2
[02:40:13] [PASSED] YUV 4:4:4
[02:40:13] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[02:40:13] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[02:40:13] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[02:40:13] ============= drm_damage_helper (21 subtests) ==============
[02:40:13] [PASSED] drm_test_damage_iter_no_damage
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_not_visible
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[02:40:13] [PASSED] drm_test_damage_iter_no_damage_no_fb
[02:40:13] [PASSED] drm_test_damage_iter_simple_damage
[02:40:13] [PASSED] drm_test_damage_iter_single_damage
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_outside_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_damage
[02:40:13] [PASSED] drm_test_damage_iter_damage_one_intersect
[02:40:13] [PASSED] drm_test_damage_iter_damage_one_outside
[02:40:13] [PASSED] drm_test_damage_iter_damage_src_moved
[02:40:13] [PASSED] drm_test_damage_iter_damage_not_visible
[02:40:13] ================ [PASSED] drm_damage_helper ================
[02:40:13] ============== drm_dp_mst_helper (3 subtests) ==============
[02:40:13] ============== drm_test_dp_mst_calc_pbn_mode ==============
[02:40:13] [PASSED] Clock 154000 BPP 30 DSC disabled
[02:40:13] [PASSED] Clock 234000 BPP 30 DSC disabled
[02:40:13] [PASSED] Clock 297000 BPP 24 DSC disabled
[02:40:13] [PASSED] Clock 332880 BPP 24 DSC enabled
[02:40:13] [PASSED] Clock 324540 BPP 24 DSC enabled
[02:40:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[02:40:13] ============== drm_test_dp_mst_calc_pbn_div ===============
[02:40:13] [PASSED] Link rate 2000000 lane count 4
[02:40:13] [PASSED] Link rate 2000000 lane count 2
[02:40:13] [PASSED] Link rate 2000000 lane count 1
[02:40:13] [PASSED] Link rate 1350000 lane count 4
[02:40:13] [PASSED] Link rate 1350000 lane count 2
[02:40:13] [PASSED] Link rate 1350000 lane count 1
[02:40:13] [PASSED] Link rate 1000000 lane count 4
[02:40:13] [PASSED] Link rate 1000000 lane count 2
[02:40:13] [PASSED] Link rate 1000000 lane count 1
[02:40:13] [PASSED] Link rate 810000 lane count 4
[02:40:13] [PASSED] Link rate 810000 lane count 2
[02:40:13] [PASSED] Link rate 810000 lane count 1
[02:40:13] [PASSED] Link rate 540000 lane count 4
[02:40:13] [PASSED] Link rate 540000 lane count 2
[02:40:13] [PASSED] Link rate 540000 lane count 1
[02:40:13] [PASSED] Link rate 270000 lane count 4
[02:40:13] [PASSED] Link rate 270000 lane count 2
[02:40:13] [PASSED] Link rate 270000 lane count 1
[02:40:13] [PASSED] Link rate 162000 lane count 4
[02:40:13] [PASSED] Link rate 162000 lane count 2
[02:40:13] [PASSED] Link rate 162000 lane count 1
[02:40:13] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[02:40:13] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[02:40:13] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[02:40:13] [PASSED] DP_POWER_UP_PHY with port number
[02:40:13] [PASSED] DP_POWER_DOWN_PHY with port number
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[02:40:13] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[02:40:13] [PASSED] DP_QUERY_PAYLOAD with port number
[02:40:13] [PASSED] DP_QUERY_PAYLOAD with VCPI
[02:40:13] [PASSED] DP_REMOTE_DPCD_READ with port number
[02:40:13] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[02:40:13] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[02:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[02:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[02:40:13] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[02:40:13] [PASSED] DP_REMOTE_I2C_READ with port number
[02:40:13] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[02:40:13] [PASSED] DP_REMOTE_I2C_READ with transactions array
[02:40:13] [PASSED] DP_REMOTE_I2C_WRITE with port number
[02:40:13] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[02:40:13] [PASSED] DP_REMOTE_I2C_WRITE with data array
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[02:40:13] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[02:40:13] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[02:40:13] ================ [PASSED] drm_dp_mst_helper ================
[02:40:13] ================== drm_exec (7 subtests) ===================
[02:40:13] [PASSED] sanitycheck
[02:40:13] [PASSED] test_lock
[02:40:13] [PASSED] test_lock_unlock
[02:40:13] [PASSED] test_duplicates
[02:40:13] [PASSED] test_prepare
[02:40:13] [PASSED] test_prepare_array
[02:40:13] [PASSED] test_multiple_loops
[02:40:13] ==================== [PASSED] drm_exec =====================
[02:40:13] =========== drm_format_helper_test (17 subtests) ===========
[02:40:13] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[02:40:13] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[02:40:13] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[02:40:13] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[02:40:13] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[02:40:13] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[02:40:13] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[02:40:13] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[02:40:13] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[02:40:13] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[02:40:13] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[02:40:13] ============== drm_test_fb_xrgb8888_to_mono ===============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[02:40:13] ==================== drm_test_fb_swab =====================
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ================ [PASSED] drm_test_fb_swab =================
[02:40:13] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[02:40:13] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[02:40:13] [PASSED] single_pixel_source_buffer
[02:40:13] [PASSED] single_pixel_clip_rectangle
[02:40:13] [PASSED] well_known_colors
[02:40:13] [PASSED] destination_pitch
[02:40:13] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[02:40:13] ================= drm_test_fb_clip_offset =================
[02:40:13] [PASSED] pass through
[02:40:13] [PASSED] horizontal offset
[02:40:13] [PASSED] vertical offset
[02:40:13] [PASSED] horizontal and vertical offset
[02:40:13] [PASSED] horizontal offset (custom pitch)
[02:40:13] [PASSED] vertical offset (custom pitch)
[02:40:13] [PASSED] horizontal and vertical offset (custom pitch)
[02:40:13] ============= [PASSED] drm_test_fb_clip_offset =============
[02:40:13] =================== drm_test_fb_memcpy ====================
[02:40:13] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[02:40:13] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[02:40:13] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[02:40:13] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[02:40:13] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[02:40:13] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[02:40:13] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[02:40:13] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[02:40:13] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[02:40:13] =============== [PASSED] drm_test_fb_memcpy ================
[02:40:13] ============= [PASSED] drm_format_helper_test ==============
[02:40:13] ================= drm_format (18 subtests) =================
[02:40:13] [PASSED] drm_test_format_block_width_invalid
[02:40:13] [PASSED] drm_test_format_block_width_one_plane
[02:40:13] [PASSED] drm_test_format_block_width_two_plane
[02:40:13] [PASSED] drm_test_format_block_width_three_plane
[02:40:13] [PASSED] drm_test_format_block_width_tiled
[02:40:13] [PASSED] drm_test_format_block_height_invalid
[02:40:13] [PASSED] drm_test_format_block_height_one_plane
[02:40:13] [PASSED] drm_test_format_block_height_two_plane
[02:40:13] [PASSED] drm_test_format_block_height_three_plane
[02:40:13] [PASSED] drm_test_format_block_height_tiled
[02:40:13] [PASSED] drm_test_format_min_pitch_invalid
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_two_plane
[02:40:13] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[02:40:13] [PASSED] drm_test_format_min_pitch_tiled
[02:40:13] =================== [PASSED] drm_format ====================
[02:40:13] ============== drm_framebuffer (10 subtests) ===============
[02:40:13] ========== drm_test_framebuffer_check_src_coords ==========
[02:40:13] [PASSED] Success: source fits into fb
[02:40:13] [PASSED] Fail: overflowing fb with x-axis coordinate
[02:40:13] [PASSED] Fail: overflowing fb with y-axis coordinate
[02:40:13] [PASSED] Fail: overflowing fb with source width
[02:40:13] [PASSED] Fail: overflowing fb with source height
[02:40:13] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[02:40:13] [PASSED] drm_test_framebuffer_cleanup
[02:40:13] =============== drm_test_framebuffer_create ===============
[02:40:13] [PASSED] ABGR8888 normal sizes
[02:40:13] [PASSED] ABGR8888 max sizes
[02:40:13] [PASSED] ABGR8888 pitch greater than min required
[02:40:13] [PASSED] ABGR8888 pitch less than min required
[02:40:13] [PASSED] ABGR8888 Invalid width
[02:40:13] [PASSED] ABGR8888 Invalid buffer handle
[02:40:13] [PASSED] No pixel format
[02:40:13] [PASSED] ABGR8888 Width 0
[02:40:13] [PASSED] ABGR8888 Height 0
[02:40:13] [PASSED] ABGR8888 Out of bound height * pitch combination
[02:40:13] [PASSED] ABGR8888 Large buffer offset
[02:40:13] [PASSED] ABGR8888 Buffer offset for inexistent plane
[02:40:13] [PASSED] ABGR8888 Invalid flag
[02:40:13] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[02:40:13] [PASSED] ABGR8888 Valid buffer modifier
[02:40:13] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[02:40:13] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] NV12 Normal sizes
[02:40:13] [PASSED] NV12 Max sizes
[02:40:13] [PASSED] NV12 Invalid pitch
[02:40:13] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[02:40:13] [PASSED] NV12 different modifier per-plane
[02:40:13] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[02:40:13] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] NV12 Modifier for inexistent plane
[02:40:13] [PASSED] NV12 Handle for inexistent plane
[02:40:13] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[02:40:13] [PASSED] YVU420 Normal sizes
[02:40:13] [PASSED] YVU420 Max sizes
[02:40:13] [PASSED] YVU420 Invalid pitch
[02:40:13] [PASSED] YVU420 Different pitches
[02:40:13] [PASSED] YVU420 Different buffer offsets/pitches
[02:40:13] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[02:40:13] [PASSED] YVU420 Valid modifier
[02:40:13] [PASSED] YVU420 Different modifiers per plane
[02:40:13] [PASSED] YVU420 Modifier for inexistent plane
[02:40:13] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[02:40:13] [PASSED] X0L2 Normal sizes
[02:40:13] [PASSED] X0L2 Max sizes
[02:40:13] [PASSED] X0L2 Invalid pitch
[02:40:13] [PASSED] X0L2 Pitch greater than minimum required
[02:40:13] [PASSED] X0L2 Handle for inexistent plane
[02:40:13] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[02:40:13] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[02:40:13] [PASSED] X0L2 Valid modifier
[02:40:13] [PASSED] X0L2 Modifier for inexistent plane
[02:40:13] =========== [PASSED] drm_test_framebuffer_create ===========
[02:40:13] [PASSED] drm_test_framebuffer_free
[02:40:13] [PASSED] drm_test_framebuffer_init
[02:40:13] [PASSED] drm_test_framebuffer_init_bad_format
[02:40:13] [PASSED] drm_test_framebuffer_init_dev_mismatch
[02:40:13] [PASSED] drm_test_framebuffer_lookup
[02:40:13] [PASSED] drm_test_framebuffer_lookup_inexistent
[02:40:13] [PASSED] drm_test_framebuffer_modifiers_not_supported
[02:40:13] ================= [PASSED] drm_framebuffer =================
[02:40:13] ================ drm_gem_shmem (8 subtests) ================
[02:40:13] [PASSED] drm_gem_shmem_test_obj_create
[02:40:13] [PASSED] drm_gem_shmem_test_obj_create_private
[02:40:13] [PASSED] drm_gem_shmem_test_pin_pages
[02:40:13] [PASSED] drm_gem_shmem_test_vmap
[02:40:13] [PASSED] drm_gem_shmem_test_get_sg_table
[02:40:13] [PASSED] drm_gem_shmem_test_get_pages_sgt
[02:40:13] [PASSED] drm_gem_shmem_test_madvise
[02:40:13] [PASSED] drm_gem_shmem_test_purge
[02:40:13] ================== [PASSED] drm_gem_shmem ==================
[02:40:13] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[02:40:13] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[02:40:13] [PASSED] Automatic
[02:40:13] [PASSED] Full
[02:40:13] [PASSED] Limited 16:235
[02:40:13] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[02:40:13] [PASSED] drm_test_check_disable_connector
[02:40:13] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[02:40:13] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[02:40:13] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[02:40:13] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[02:40:13] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[02:40:13] [PASSED] drm_test_check_output_bpc_dvi
[02:40:13] [PASSED] drm_test_check_output_bpc_format_vic_1
[02:40:13] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[02:40:13] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[02:40:13] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[02:40:13] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[02:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[02:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[02:40:13] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[02:40:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[02:40:13] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[02:40:13] [PASSED] drm_test_check_broadcast_rgb_value
[02:40:13] [PASSED] drm_test_check_bpc_8_value
[02:40:13] [PASSED] drm_test_check_bpc_10_value
[02:40:13] [PASSED] drm_test_check_bpc_12_value
[02:40:13] [PASSED] drm_test_check_format_value
[02:40:13] [PASSED] drm_test_check_tmds_char_value
[02:40:13] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[02:40:13] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[02:40:13] [PASSED] drm_test_check_mode_valid
[02:40:13] [PASSED] drm_test_check_mode_valid_reject
[02:40:13] [PASSED] drm_test_check_mode_valid_reject_rate
[02:40:13] [PASSED] drm_test_check_mode_valid_reject_max_clock
[02:40:13] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[02:40:13] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[02:40:13] [PASSED] drm_test_check_infoframes
[02:40:13] [PASSED] drm_test_check_reject_avi_infoframe
[02:40:13] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[02:40:13] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[02:40:13] [PASSED] drm_test_check_reject_audio_infoframe
[02:40:13] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[02:40:13] ================= drm_managed (2 subtests) =================
[02:40:13] [PASSED] drm_test_managed_release_action
[02:40:13] [PASSED] drm_test_managed_run_action
[02:40:13] =================== [PASSED] drm_managed ===================
[02:40:13] =================== drm_mm (6 subtests) ====================
[02:40:13] [PASSED] drm_test_mm_init
[02:40:13] [PASSED] drm_test_mm_debug
[02:40:13] [PASSED] drm_test_mm_align32
[02:40:13] [PASSED] drm_test_mm_align64
[02:40:13] [PASSED] drm_test_mm_lowest
[02:40:13] [PASSED] drm_test_mm_highest
[02:40:13] ===================== [PASSED] drm_mm ======================
[02:40:13] ============= drm_modes_analog_tv (5 subtests) =============
[02:40:13] [PASSED] drm_test_modes_analog_tv_mono_576i
[02:40:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[02:40:13] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[02:40:13] [PASSED] drm_test_modes_analog_tv_pal_576i
[02:40:13] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[02:40:13] =============== [PASSED] drm_modes_analog_tv ===============
[02:40:13] ============== drm_plane_helper (2 subtests) ===============
[02:40:13] =============== drm_test_check_plane_state ================
[02:40:13] [PASSED] clipping_simple
[02:40:13] [PASSED] clipping_rotate_reflect
[02:40:13] [PASSED] positioning_simple
[02:40:13] [PASSED] upscaling
[02:40:13] [PASSED] downscaling
[02:40:13] [PASSED] rounding1
[02:40:13] [PASSED] rounding2
[02:40:13] [PASSED] rounding3
[02:40:13] [PASSED] rounding4
[02:40:13] =========== [PASSED] drm_test_check_plane_state ============
[02:40:13] =========== drm_test_check_invalid_plane_state ============
[02:40:13] [PASSED] positioning_invalid
[02:40:13] [PASSED] upscaling_invalid
[02:40:13] [PASSED] downscaling_invalid
[02:40:13] ======= [PASSED] drm_test_check_invalid_plane_state ========
[02:40:13] ================ [PASSED] drm_plane_helper =================
[02:40:13] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[02:40:13] ====== drm_test_connector_helper_tv_get_modes_check =======
[02:40:13] [PASSED] None
[02:40:13] [PASSED] PAL
[02:40:13] [PASSED] NTSC
[02:40:13] [PASSED] Both, NTSC Default
[02:40:13] [PASSED] Both, PAL Default
[02:40:13] [PASSED] Both, NTSC Default, with PAL on command-line
[02:40:13] [PASSED] Both, PAL Default, with NTSC on command-line
[02:40:13] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[02:40:13] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[02:40:13] ================== drm_rect (9 subtests) ===================
[02:40:13] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[02:40:13] [PASSED] drm_test_rect_clip_scaled_not_clipped
[02:40:13] [PASSED] drm_test_rect_clip_scaled_clipped
[02:40:13] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[02:40:13] ================= drm_test_rect_intersect =================
[02:40:13] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[02:40:13] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[02:40:13] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[02:40:13] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[02:40:13] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[02:40:13] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[02:40:13] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[02:40:13] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[02:40:13] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[02:40:13] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[02:40:13] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[02:40:13] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[02:40:13] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[02:40:13] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[02:40:13] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[02:40:13] ============= [PASSED] drm_test_rect_intersect =============
[02:40:13] ================ drm_test_rect_calc_hscale ================
[02:40:13] [PASSED] normal use
[02:40:13] [PASSED] out of max range
[02:40:13] [PASSED] out of min range
[02:40:13] [PASSED] zero dst
[02:40:13] [PASSED] negative src
[02:40:13] [PASSED] negative dst
[02:40:13] ============ [PASSED] drm_test_rect_calc_hscale ============
[02:40:13] ================ drm_test_rect_calc_vscale ================
[02:40:13] [PASSED] normal use
[02:40:13] [PASSED] out of max range
[02:40:13] [PASSED] out of min range
[02:40:13] [PASSED] zero dst
[02:40:13] [PASSED] negative src
[02:40:13] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[02:40:13] ============ [PASSED] drm_test_rect_calc_vscale ============
[02:40:13] ================== drm_test_rect_rotate ===================
[02:40:13] [PASSED] reflect-x
[02:40:13] [PASSED] reflect-y
[02:40:13] [PASSED] rotate-0
[02:40:13] [PASSED] rotate-90
[02:40:13] [PASSED] rotate-180
[02:40:13] [PASSED] rotate-270
[02:40:13] ============== [PASSED] drm_test_rect_rotate ===============
[02:40:13] ================ drm_test_rect_rotate_inv =================
[02:40:13] [PASSED] reflect-x
[02:40:13] [PASSED] reflect-y
[02:40:13] [PASSED] rotate-0
[02:40:13] [PASSED] rotate-90
[02:40:13] [PASSED] rotate-180
[02:40:13] [PASSED] rotate-270
[02:40:13] ============ [PASSED] drm_test_rect_rotate_inv =============
[02:40:13] ==================== [PASSED] drm_rect =====================
[02:40:13] ============ drm_sysfb_modeset_test (1 subtest) ============
[02:40:13] ============ drm_test_sysfb_build_fourcc_list =============
[02:40:13] [PASSED] no native formats
[02:40:13] [PASSED] XRGB8888 as native format
[02:40:13] [PASSED] remove duplicates
[02:40:13] [PASSED] convert alpha formats
[02:40:13] [PASSED] random formats
[02:40:13] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[02:40:13] ============= [PASSED] drm_sysfb_modeset_test ==============
[02:40:13] ================== drm_fixp (2 subtests) ===================
[02:40:13] [PASSED] drm_test_int2fixp
[02:40:13] [PASSED] drm_test_sm2fixp
[02:40:13] ==================== [PASSED] drm_fixp =====================
[02:40:13] ============================================================
[02:40:13] Testing complete. Ran 621 tests: passed: 621
[02:40:13] Elapsed time: 26.091s total, 1.711s configuring, 24.209s building, 0.140s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[02:40:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[02:40:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[02:40:24] Starting KUnit Kernel (1/1)...
[02:40:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[02:40:24] ================= ttm_device (5 subtests) ==================
[02:40:24] [PASSED] ttm_device_init_basic
[02:40:24] [PASSED] ttm_device_init_multiple
[02:40:24] [PASSED] ttm_device_fini_basic
[02:40:24] [PASSED] ttm_device_init_no_vma_man
[02:40:24] ================== ttm_device_init_pools ==================
[02:40:24] [PASSED] No DMA allocations, no DMA32 required
[02:40:24] [PASSED] DMA allocations, DMA32 required
[02:40:24] [PASSED] No DMA allocations, DMA32 required
[02:40:24] [PASSED] DMA allocations, no DMA32 required
[02:40:24] ============== [PASSED] ttm_device_init_pools ==============
[02:40:24] =================== [PASSED] ttm_device ====================
[02:40:24] ================== ttm_pool (8 subtests) ===================
[02:40:24] ================== ttm_pool_alloc_basic ===================
[02:40:24] [PASSED] One page
[02:40:24] [PASSED] More than one page
[02:40:24] [PASSED] Above the allocation limit
[02:40:24] [PASSED] One page, with coherent DMA mappings enabled
[02:40:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:40:24] ============== [PASSED] ttm_pool_alloc_basic ===============
[02:40:24] ============== ttm_pool_alloc_basic_dma_addr ==============
[02:40:24] [PASSED] One page
[02:40:24] [PASSED] More than one page
[02:40:24] [PASSED] Above the allocation limit
[02:40:24] [PASSED] One page, with coherent DMA mappings enabled
[02:40:24] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[02:40:24] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[02:40:24] [PASSED] ttm_pool_alloc_order_caching_match
[02:40:24] [PASSED] ttm_pool_alloc_caching_mismatch
[02:40:24] [PASSED] ttm_pool_alloc_order_mismatch
[02:40:24] [PASSED] ttm_pool_free_dma_alloc
[02:40:24] [PASSED] ttm_pool_free_no_dma_alloc
[02:40:24] [PASSED] ttm_pool_fini_basic
[02:40:24] ==================== [PASSED] ttm_pool =====================
[02:40:24] ================ ttm_resource (8 subtests) =================
[02:40:24] ================= ttm_resource_init_basic =================
[02:40:24] [PASSED] Init resource in TTM_PL_SYSTEM
[02:40:24] [PASSED] Init resource in TTM_PL_VRAM
[02:40:24] [PASSED] Init resource in a private placement
[02:40:24] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[02:40:24] ============= [PASSED] ttm_resource_init_basic =============
[02:40:24] [PASSED] ttm_resource_init_pinned
[02:40:24] [PASSED] ttm_resource_fini_basic
[02:40:24] [PASSED] ttm_resource_manager_init_basic
[02:40:24] [PASSED] ttm_resource_manager_usage_basic
[02:40:24] [PASSED] ttm_resource_manager_set_used_basic
[02:40:24] [PASSED] ttm_sys_man_alloc_basic
[02:40:24] [PASSED] ttm_sys_man_free_basic
[02:40:24] ================== [PASSED] ttm_resource ===================
[02:40:24] =================== ttm_tt (15 subtests) ===================
[02:40:24] ==================== ttm_tt_init_basic ====================
[02:40:24] [PASSED] Page-aligned size
[02:40:24] [PASSED] Extra pages requested
[02:40:24] ================ [PASSED] ttm_tt_init_basic ================
[02:40:24] [PASSED] ttm_tt_init_misaligned
[02:40:24] [PASSED] ttm_tt_fini_basic
[02:40:24] [PASSED] ttm_tt_fini_sg
[02:40:24] [PASSED] ttm_tt_fini_shmem
[02:40:24] [PASSED] ttm_tt_create_basic
[02:40:24] [PASSED] ttm_tt_create_invalid_bo_type
[02:40:24] [PASSED] ttm_tt_create_ttm_exists
[02:40:24] [PASSED] ttm_tt_create_failed
[02:40:24] [PASSED] ttm_tt_destroy_basic
[02:40:24] [PASSED] ttm_tt_populate_null_ttm
[02:40:24] [PASSED] ttm_tt_populate_populated_ttm
[02:40:24] [PASSED] ttm_tt_unpopulate_basic
[02:40:24] [PASSED] ttm_tt_unpopulate_empty_ttm
[02:40:24] [PASSED] ttm_tt_swapin_basic
[02:40:24] ===================== [PASSED] ttm_tt ======================
[02:40:24] =================== ttm_bo (14 subtests) ===================
[02:40:24] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[02:40:24] [PASSED] Cannot be interrupted and sleeps
[02:40:24] [PASSED] Cannot be interrupted, locks straight away
[02:40:24] [PASSED] Can be interrupted, sleeps
[02:40:24] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[02:40:24] [PASSED] ttm_bo_reserve_locked_no_sleep
[02:40:24] [PASSED] ttm_bo_reserve_no_wait_ticket
[02:40:24] [PASSED] ttm_bo_reserve_double_resv
[02:40:24] [PASSED] ttm_bo_reserve_interrupted
[02:40:24] [PASSED] ttm_bo_reserve_deadlock
[02:40:24] [PASSED] ttm_bo_unreserve_basic
[02:40:24] [PASSED] ttm_bo_unreserve_pinned
[02:40:24] [PASSED] ttm_bo_unreserve_bulk
[02:40:24] [PASSED] ttm_bo_fini_basic
[02:40:24] [PASSED] ttm_bo_fini_shared_resv
[02:40:24] [PASSED] ttm_bo_pin_basic
[02:40:24] [PASSED] ttm_bo_pin_unpin_resource
[02:40:24] [PASSED] ttm_bo_multiple_pin_one_unpin
[02:40:24] ===================== [PASSED] ttm_bo ======================
[02:40:24] ============== ttm_bo_validate (21 subtests) ===============
[02:40:24] ============== ttm_bo_init_reserved_sys_man ===============
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[02:40:24] ============== ttm_bo_init_reserved_mock_man ==============
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[02:40:24] [PASSED] ttm_bo_init_reserved_resv
[02:40:24] ================== ttm_bo_validate_basic ==================
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ============== [PASSED] ttm_bo_validate_basic ==============
[02:40:24] [PASSED] ttm_bo_validate_invalid_placement
[02:40:24] ============= ttm_bo_validate_same_placement ==============
[02:40:24] [PASSED] System manager
[02:40:24] [PASSED] VRAM manager
[02:40:24] ========= [PASSED] ttm_bo_validate_same_placement ==========
[02:40:24] [PASSED] ttm_bo_validate_failed_alloc
[02:40:24] [PASSED] ttm_bo_validate_pinned
[02:40:24] [PASSED] ttm_bo_validate_busy_placement
[02:40:24] ================ ttm_bo_validate_multihop =================
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ============ [PASSED] ttm_bo_validate_multihop =============
[02:40:24] ========== ttm_bo_validate_no_placement_signaled ==========
[02:40:24] [PASSED] Buffer object in system domain, no page vector
[02:40:24] [PASSED] Buffer object in system domain with an existing page vector
[02:40:24] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[02:40:24] ======== ttm_bo_validate_no_placement_not_signaled ========
[02:40:24] [PASSED] Buffer object for userspace
[02:40:24] [PASSED] Kernel buffer object
[02:40:24] [PASSED] Shared buffer object
[02:40:24] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[02:40:24] [PASSED] ttm_bo_validate_move_fence_signaled
[02:40:24] ========= ttm_bo_validate_move_fence_not_signaled =========
[02:40:24] [PASSED] Waits for GPU
[02:40:24] [PASSED] Tries to lock straight away
[02:40:24] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[02:40:24] [PASSED] ttm_bo_validate_happy_evict
[02:40:24] [PASSED] ttm_bo_validate_all_pinned_evict
[02:40:24] [PASSED] ttm_bo_validate_allowed_only_evict
[02:40:24] [PASSED] ttm_bo_validate_deleted_evict
[02:40:24] [PASSED] ttm_bo_validate_busy_domain_evict
[02:40:24] [PASSED] ttm_bo_validate_evict_gutting
[02:40:24] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[02:40:24] ================= [PASSED] ttm_bo_validate =================
[02:40:24] ============================================================
[02:40:24] Testing complete. Ran 101 tests: passed: 101
[02:40:24] Elapsed time: 11.396s total, 1.676s configuring, 9.453s building, 0.225s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines
2026-02-24 2:33 [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Xin Wang
2026-02-24 2:40 ` ✓ CI.KUnit: success for drm/xe: restrict multi-lrc to VCS/VECS engines (rev2) Patchwork
@ 2026-02-24 22:05 ` Matt Roper
2026-02-24 22:20 ` Wang, X
1 sibling, 1 reply; 7+ messages in thread
From: Matt Roper @ 2026-02-24 22:05 UTC (permalink / raw)
To: Xin Wang; +Cc: intel-xe, Shuicheng Lin, Matthew Brost
On Mon, Feb 23, 2026 at 06:33:54PM -0800, Xin Wang wrote:
> Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
> VIDEO_ENHANCE engines only. This check should have been in place from the
> start, as the driver typically avoids allowing uapi cases that we have
> no userspace consumer for.
>
> Additionally, the GuC firmware on ModSched platforms no longer supports
> multi-lrc on non-media engines.
>
> V3:
> - store a multi-lrc enable class mask in xe->info and populate from
> xe_device_desc in xe_pci.c (Matthew Brost)
>
> V2:
> - correct the typo (Shuicheng)
> - move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
> - remove the graphics version check (Matt Roper)
> - input more details in the commit info (Matt Roper)
>
> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Xin Wang <x.wang@intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 2 ++
> drivers/gpu/drm/xe/xe_exec_queue.c | 5 +++++
> drivers/gpu/drm/xe/xe_pci.c | 17 +++++++++++++++++
> drivers/gpu/drm/xe/xe_pci_types.h | 1 +
> 4 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 8f3ef836541e..caa8f34a6744 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -138,6 +138,8 @@ struct xe_device {
> u8 tile_count;
> /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
> u8 max_gt_per_tile;
> + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */
> + u8 multi_lrc_mask;
> /** @info.gt_count: Total number of GTs for entire device */
> u8 gt_count;
> /** @info.vm_max_level: Max VM level */
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index 66d0e10ee2c4..5abb29454d1f 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
> if (XE_IOCTL_DBG(xe, !hwe))
> return -EINVAL;
>
> + /* multi-lrc is only supported on select engine classes */
> + if (XE_IOCTL_DBG(xe, args->width > 1 &&
> + !(xe->info.multi_lrc_mask & BIT(hwe->class))))
> + return -EOPNOTSUPP;
> +
> vm = xe_vm_lookup(xef, args->vm_id);
> if (XE_IOCTL_DBG(xe, !vm))
> return -ENOENT;
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index e1f569235d8a..fe63387d4077 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -194,6 +194,7 @@ static const struct xe_device_desc tgl_desc = {
> .has_llc = true,
> .has_sriov = true,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
Is there a reason why some platforms list both VCS + VECS but others
only list VCS? The new .multi_lrc_mask is intended to restrict usage to
just the engine type(s) where we have a real userspace consumer, and for
now I'd expect that to be the same across all current platforms. We
should double check whether the media driver is actively using this on
both media engine types or just one of them (I don't know off the top of
my head), and then set the mask accordingly.
An ioctl request for multi-LRC might also get rejected on a platform if
the engine fusing indicates that there aren't 2+ engines of the given
type, but that's an orthogonal check that's independent of the
multi_lrc_mask we're defining here. Finding out how many engines
actually exist on a device is something that we can only find out at
runtime after reading the fuse registers for a specific device.
Matt
> .require_force_probe = true,
> .va_bits = 48,
> .vm_max_level = 3,
> @@ -208,6 +209,7 @@ static const struct xe_device_desc rkl_desc = {
> .has_display = true,
> .has_llc = true,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> .require_force_probe = true,
> .va_bits = 48,
> .vm_max_level = 3,
> @@ -225,6 +227,7 @@ static const struct xe_device_desc adl_s_desc = {
> .has_llc = true,
> .has_sriov = true,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> .require_force_probe = true,
> .subplatforms = (const struct xe_subplatform_desc[]) {
> { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
> @@ -246,6 +249,7 @@ static const struct xe_device_desc adl_p_desc = {
> .has_llc = true,
> .has_sriov = true,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> .require_force_probe = true,
> .subplatforms = (const struct xe_subplatform_desc[]) {
> { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
> @@ -283,6 +287,7 @@ static const struct xe_device_desc dg1_desc = {
> .has_gsc_nvm = 1,
> .has_heci_gscfi = 1,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> .require_force_probe = true,
> .va_bits = 48,
> .vm_max_level = 3,
> @@ -313,6 +318,8 @@ static const struct xe_device_desc ats_m_desc = {
> .pre_gmdid_media_ip = &media_ip_xehpm,
> .dma_mask_size = 46,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> .require_force_probe = true,
>
> DG2_FEATURES,
> @@ -325,6 +332,8 @@ static const struct xe_device_desc dg2_desc = {
> .pre_gmdid_media_ip = &media_ip_xehpm,
> .dma_mask_size = 46,
> .max_gt_per_tile = 1,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> .require_force_probe = true,
>
> DG2_FEATURES,
> @@ -358,6 +367,7 @@ static const struct xe_device_desc mtl_desc = {
> .has_display = true,
> .has_pxp = true,
> .max_gt_per_tile = 2,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> .va_bits = 48,
> .vm_max_level = 3,
> };
> @@ -393,6 +403,8 @@ static const struct xe_device_desc bmg_desc = {
> .has_soc_remapper_telem = true,
> .has_sriov = true,
> .max_gt_per_tile = 2,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> .needs_scratch = true,
> .subplatforms = (const struct xe_subplatform_desc[]) {
> { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
> @@ -445,6 +457,8 @@ static const struct xe_device_desc cri_desc = {
> .has_soc_remapper_telem = true,
> .has_sriov = true,
> .max_gt_per_tile = 2,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> .require_force_probe = true,
> .va_bits = 57,
> .vm_max_level = 4,
> @@ -459,6 +473,8 @@ static const struct xe_device_desc nvlp_desc = {
> .has_page_reclaim_hw_assist = true,
> .has_pre_prod_wa = true,
> .max_gt_per_tile = 2,
> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> .require_force_probe = true,
> .va_bits = 48,
> .vm_max_level = 4,
> @@ -746,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
> xe->info.skip_pcode = desc->skip_pcode;
> xe->info.needs_scratch = desc->needs_scratch;
> xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
> + xe->info.multi_lrc_mask = desc->multi_lrc_mask;
>
> xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
> xe_modparam.probe_display &&
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index 470d31a1f0d6..47e8a1552c2b 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -30,6 +30,7 @@ struct xe_device_desc {
> u8 dma_mask_size;
> u8 max_remote_tiles:2;
> u8 max_gt_per_tile:2;
> + u8 multi_lrc_mask;
> u8 va_bits;
> u8 vm_max_level;
> u8 vram_flags;
> --
> 2.43.0
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines
2026-02-24 22:05 ` [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Matt Roper
@ 2026-02-24 22:20 ` Wang, X
2026-02-24 22:40 ` Matthew Brost
0 siblings, 1 reply; 7+ messages in thread
From: Wang, X @ 2026-02-24 22:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-xe, Shuicheng Lin, Matthew Brost
On 2/24/2026 14:05, Matt Roper wrote:
> On Mon, Feb 23, 2026 at 06:33:54PM -0800, Xin Wang wrote:
>> Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
>> VIDEO_ENHANCE engines only. This check should have been in place from the
>> start, as the driver typically avoids allowing uapi cases that we have
>> no userspace consumer for.
>>
>> Additionally, the GuC firmware on ModSched platforms no longer supports
>> multi-lrc on non-media engines.
>>
>> V3:
>> - store a multi-lrc enable class mask in xe->info and populate from
>> xe_device_desc in xe_pci.c (Matthew Brost)
>>
>> V2:
>> - correct the typo (Shuicheng)
>> - move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
>> - remove the graphics version check (Matt Roper)
>> - input more details in the commit info (Matt Roper)
>>
>> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Signed-off-by: Xin Wang <x.wang@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>> drivers/gpu/drm/xe/xe_exec_queue.c | 5 +++++
>> drivers/gpu/drm/xe/xe_pci.c | 17 +++++++++++++++++
>> drivers/gpu/drm/xe/xe_pci_types.h | 1 +
>> 4 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index 8f3ef836541e..caa8f34a6744 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -138,6 +138,8 @@ struct xe_device {
>> u8 tile_count;
>> /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
>> u8 max_gt_per_tile;
>> + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */
>> + u8 multi_lrc_mask;
>> /** @info.gt_count: Total number of GTs for entire device */
>> u8 gt_count;
>> /** @info.vm_max_level: Max VM level */
>> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
>> index 66d0e10ee2c4..5abb29454d1f 100644
>> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
>> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
>> @@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
>> if (XE_IOCTL_DBG(xe, !hwe))
>> return -EINVAL;
>>
>> + /* multi-lrc is only supported on select engine classes */
>> + if (XE_IOCTL_DBG(xe, args->width > 1 &&
>> + !(xe->info.multi_lrc_mask & BIT(hwe->class))))
>> + return -EOPNOTSUPP;
>> +
>> vm = xe_vm_lookup(xef, args->vm_id);
>> if (XE_IOCTL_DBG(xe, !vm))
>> return -ENOENT;
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index e1f569235d8a..fe63387d4077 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -194,6 +194,7 @@ static const struct xe_device_desc tgl_desc = {
>> .has_llc = true,
>> .has_sriov = true,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> Is there a reason why some platforms list both VCS + VECS but others
> only list VCS? The new .multi_lrc_mask is intended to restrict usage to
> just the engine type(s) where we have a real userspace consumer, and for
> now I'd expect that to be the same across all current platforms. We
> should double check whether the media driver is actively using this on
> both media engine types or just one of them (I don't know off the top of
> my head), and then set the mask accordingly.
>
> An ioctl request for multi-LRC might also get rejected on a platform if
> the engine fusing indicates that there aren't 2+ engines of the given
> type, but that's an orthogonal check that's independent of the
> multi_lrc_mask we're defining here. Finding out how many engines
> actually exist on a device is something that we can only find out at
> runtime after reading the fuse registers for a specific device.
>
>
> Matt
I checked the specs and found that some devices have fewer than two VCS
or VCES
instances. In these cases, I don't think it's necessary to allow
multi-LRC to
those engines. This would prevent the injection of some illegal ioctl
parameters.
Xin
>> .require_force_probe = true,
>> .va_bits = 48,
>> .vm_max_level = 3,
>> @@ -208,6 +209,7 @@ static const struct xe_device_desc rkl_desc = {
>> .has_display = true,
>> .has_llc = true,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>> .require_force_probe = true,
>> .va_bits = 48,
>> .vm_max_level = 3,
>> @@ -225,6 +227,7 @@ static const struct xe_device_desc adl_s_desc = {
>> .has_llc = true,
>> .has_sriov = true,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>> .require_force_probe = true,
>> .subplatforms = (const struct xe_subplatform_desc[]) {
>> { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
>> @@ -246,6 +249,7 @@ static const struct xe_device_desc adl_p_desc = {
>> .has_llc = true,
>> .has_sriov = true,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>> .require_force_probe = true,
>> .subplatforms = (const struct xe_subplatform_desc[]) {
>> { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
>> @@ -283,6 +287,7 @@ static const struct xe_device_desc dg1_desc = {
>> .has_gsc_nvm = 1,
>> .has_heci_gscfi = 1,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>> .require_force_probe = true,
>> .va_bits = 48,
>> .vm_max_level = 3,
>> @@ -313,6 +318,8 @@ static const struct xe_device_desc ats_m_desc = {
>> .pre_gmdid_media_ip = &media_ip_xehpm,
>> .dma_mask_size = 46,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>> .require_force_probe = true,
>>
>> DG2_FEATURES,
>> @@ -325,6 +332,8 @@ static const struct xe_device_desc dg2_desc = {
>> .pre_gmdid_media_ip = &media_ip_xehpm,
>> .dma_mask_size = 46,
>> .max_gt_per_tile = 1,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>> .require_force_probe = true,
>>
>> DG2_FEATURES,
>> @@ -358,6 +367,7 @@ static const struct xe_device_desc mtl_desc = {
>> .has_display = true,
>> .has_pxp = true,
>> .max_gt_per_tile = 2,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>> .va_bits = 48,
>> .vm_max_level = 3,
>> };
>> @@ -393,6 +403,8 @@ static const struct xe_device_desc bmg_desc = {
>> .has_soc_remapper_telem = true,
>> .has_sriov = true,
>> .max_gt_per_tile = 2,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>> .needs_scratch = true,
>> .subplatforms = (const struct xe_subplatform_desc[]) {
>> { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
>> @@ -445,6 +457,8 @@ static const struct xe_device_desc cri_desc = {
>> .has_soc_remapper_telem = true,
>> .has_sriov = true,
>> .max_gt_per_tile = 2,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>> .require_force_probe = true,
>> .va_bits = 57,
>> .vm_max_level = 4,
>> @@ -459,6 +473,8 @@ static const struct xe_device_desc nvlp_desc = {
>> .has_page_reclaim_hw_assist = true,
>> .has_pre_prod_wa = true,
>> .max_gt_per_tile = 2,
>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>> .require_force_probe = true,
>> .va_bits = 48,
>> .vm_max_level = 4,
>> @@ -746,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
>> xe->info.skip_pcode = desc->skip_pcode;
>> xe->info.needs_scratch = desc->needs_scratch;
>> xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
>> + xe->info.multi_lrc_mask = desc->multi_lrc_mask;
>>
>> xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
>> xe_modparam.probe_display &&
>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>> index 470d31a1f0d6..47e8a1552c2b 100644
>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>> @@ -30,6 +30,7 @@ struct xe_device_desc {
>> u8 dma_mask_size;
>> u8 max_remote_tiles:2;
>> u8 max_gt_per_tile:2;
>> + u8 multi_lrc_mask;
>> u8 va_bits;
>> u8 vm_max_level;
>> u8 vram_flags;
>> --
>> 2.43.0
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines
2026-02-24 22:20 ` Wang, X
@ 2026-02-24 22:40 ` Matthew Brost
2026-02-24 22:57 ` Wang, X
0 siblings, 1 reply; 7+ messages in thread
From: Matthew Brost @ 2026-02-24 22:40 UTC (permalink / raw)
To: Wang, X; +Cc: Matt Roper, intel-xe, Shuicheng Lin
On Tue, Feb 24, 2026 at 02:20:33PM -0800, Wang, X wrote:
>
> On 2/24/2026 14:05, Matt Roper wrote:
> > On Mon, Feb 23, 2026 at 06:33:54PM -0800, Xin Wang wrote:
> > > Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
> > > VIDEO_ENHANCE engines only. This check should have been in place from the
> > > start, as the driver typically avoids allowing uapi cases that we have
> > > no userspace consumer for.
> > >
> > > Additionally, the GuC firmware on ModSched platforms no longer supports
> > > multi-lrc on non-media engines.
> > >
> > > V3:
> > > - store a multi-lrc enable class mask in xe->info and populate from
> > > xe_device_desc in xe_pci.c (Matthew Brost)
> > >
> > > V2:
> > > - correct the typo (Shuicheng)
> > > - move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
> > > - remove the graphics version check (Matt Roper)
> > > - input more details in the commit info (Matt Roper)
> > >
> > > Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > Signed-off-by: Xin Wang <x.wang@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_device_types.h | 2 ++
> > > drivers/gpu/drm/xe/xe_exec_queue.c | 5 +++++
> > > drivers/gpu/drm/xe/xe_pci.c | 17 +++++++++++++++++
> > > drivers/gpu/drm/xe/xe_pci_types.h | 1 +
> > > 4 files changed, 25 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > > index 8f3ef836541e..caa8f34a6744 100644
> > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > @@ -138,6 +138,8 @@ struct xe_device {
> > > u8 tile_count;
> > > /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
> > > u8 max_gt_per_tile;
> > > + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */
> > > + u8 multi_lrc_mask;
> > > /** @info.gt_count: Total number of GTs for entire device */
> > > u8 gt_count;
> > > /** @info.vm_max_level: Max VM level */
> > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > index 66d0e10ee2c4..5abb29454d1f 100644
> > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > @@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
> > > if (XE_IOCTL_DBG(xe, !hwe))
> > > return -EINVAL;
> > > + /* multi-lrc is only supported on select engine classes */
> > > + if (XE_IOCTL_DBG(xe, args->width > 1 &&
> > > + !(xe->info.multi_lrc_mask & BIT(hwe->class))))
> > > + return -EOPNOTSUPP;
> > > +
> > > vm = xe_vm_lookup(xef, args->vm_id);
> > > if (XE_IOCTL_DBG(xe, !vm))
> > > return -ENOENT;
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > index e1f569235d8a..fe63387d4077 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -194,6 +194,7 @@ static const struct xe_device_desc tgl_desc = {
> > > .has_llc = true,
> > > .has_sriov = true,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > Is there a reason why some platforms list both VCS + VECS but others
> > only list VCS? The new .multi_lrc_mask is intended to restrict usage to
> > just the engine type(s) where we have a real userspace consumer, and for
> > now I'd expect that to be the same across all current platforms. We
Matt R beat me to this suggestion too, +1.
> > should double check whether the media driver is actively using this on
> > both media engine types or just one of them (I don't know off the top of
> > my head), and then set the mask accordingly.
> >
> > An ioctl request for multi-LRC might also get rejected on a platform if
> > the engine fusing indicates that there aren't 2+ engines of the given
> > type, but that's an orthogonal check that's independent of the
> > multi_lrc_mask we're defining here. Finding out how many engines
> > actually exist on a device is something that we can only find out at
> > runtime after reading the fuse registers for a specific device.
> >
> >
> > Matt
> I checked the specs and found that some devices have fewer than two VCS or
> VCES
> instances. In these cases, I don't think it's necessary to allow multi-LRC
> to
> those engines. This would prevent the injection of some illegal ioctl
> parameters.
See Matt's response above, we check in the IOCTL how many engines the
platform has, if it only has 1 the IOCTL will prevent multi-LRC queue
from being created.
So again, I'd just enable XE_ENGINE_CLASS_VIDEO_DECODE |
XE_ENGINE_CLASS_VIDEO_ENHANCE on platforms.
Matt
>
> Xin
> > > .require_force_probe = true,
> > > .va_bits = 48,
> > > .vm_max_level = 3,
> > > @@ -208,6 +209,7 @@ static const struct xe_device_desc rkl_desc = {
> > > .has_display = true,
> > > .has_llc = true,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > .require_force_probe = true,
> > > .va_bits = 48,
> > > .vm_max_level = 3,
> > > @@ -225,6 +227,7 @@ static const struct xe_device_desc adl_s_desc = {
> > > .has_llc = true,
> > > .has_sriov = true,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > .require_force_probe = true,
> > > .subplatforms = (const struct xe_subplatform_desc[]) {
> > > { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
> > > @@ -246,6 +249,7 @@ static const struct xe_device_desc adl_p_desc = {
> > > .has_llc = true,
> > > .has_sriov = true,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > .require_force_probe = true,
> > > .subplatforms = (const struct xe_subplatform_desc[]) {
> > > { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
> > > @@ -283,6 +287,7 @@ static const struct xe_device_desc dg1_desc = {
> > > .has_gsc_nvm = 1,
> > > .has_heci_gscfi = 1,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > .require_force_probe = true,
> > > .va_bits = 48,
> > > .vm_max_level = 3,
> > > @@ -313,6 +318,8 @@ static const struct xe_device_desc ats_m_desc = {
> > > .pre_gmdid_media_ip = &media_ip_xehpm,
> > > .dma_mask_size = 46,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > .require_force_probe = true,
> > > DG2_FEATURES,
> > > @@ -325,6 +332,8 @@ static const struct xe_device_desc dg2_desc = {
> > > .pre_gmdid_media_ip = &media_ip_xehpm,
> > > .dma_mask_size = 46,
> > > .max_gt_per_tile = 1,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > .require_force_probe = true,
> > > DG2_FEATURES,
> > > @@ -358,6 +367,7 @@ static const struct xe_device_desc mtl_desc = {
> > > .has_display = true,
> > > .has_pxp = true,
> > > .max_gt_per_tile = 2,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > .va_bits = 48,
> > > .vm_max_level = 3,
> > > };
> > > @@ -393,6 +403,8 @@ static const struct xe_device_desc bmg_desc = {
> > > .has_soc_remapper_telem = true,
> > > .has_sriov = true,
> > > .max_gt_per_tile = 2,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > .needs_scratch = true,
> > > .subplatforms = (const struct xe_subplatform_desc[]) {
> > > { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
> > > @@ -445,6 +457,8 @@ static const struct xe_device_desc cri_desc = {
> > > .has_soc_remapper_telem = true,
> > > .has_sriov = true,
> > > .max_gt_per_tile = 2,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > .require_force_probe = true,
> > > .va_bits = 57,
> > > .vm_max_level = 4,
> > > @@ -459,6 +473,8 @@ static const struct xe_device_desc nvlp_desc = {
> > > .has_page_reclaim_hw_assist = true,
> > > .has_pre_prod_wa = true,
> > > .max_gt_per_tile = 2,
> > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > .require_force_probe = true,
> > > .va_bits = 48,
> > > .vm_max_level = 4,
> > > @@ -746,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
> > > xe->info.skip_pcode = desc->skip_pcode;
> > > xe->info.needs_scratch = desc->needs_scratch;
> > > xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
> > > + xe->info.multi_lrc_mask = desc->multi_lrc_mask;
> > > xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
> > > xe_modparam.probe_display &&
> > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > > index 470d31a1f0d6..47e8a1552c2b 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > @@ -30,6 +30,7 @@ struct xe_device_desc {
> > > u8 dma_mask_size;
> > > u8 max_remote_tiles:2;
> > > u8 max_gt_per_tile:2;
> > > + u8 multi_lrc_mask;
> > > u8 va_bits;
> > > u8 vm_max_level;
> > > u8 vram_flags;
> > > --
> > > 2.43.0
> > >
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines
2026-02-24 22:40 ` Matthew Brost
@ 2026-02-24 22:57 ` Wang, X
2026-02-24 23:03 ` Matthew Brost
0 siblings, 1 reply; 7+ messages in thread
From: Wang, X @ 2026-02-24 22:57 UTC (permalink / raw)
To: Matthew Brost; +Cc: Matt Roper, intel-xe, Shuicheng Lin
On 2/24/2026 14:40, Matthew Brost wrote:
> On Tue, Feb 24, 2026 at 02:20:33PM -0800, Wang, X wrote:
>> On 2/24/2026 14:05, Matt Roper wrote:
>>> On Mon, Feb 23, 2026 at 06:33:54PM -0800, Xin Wang wrote:
>>>> Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
>>>> VIDEO_ENHANCE engines only. This check should have been in place from the
>>>> start, as the driver typically avoids allowing uapi cases that we have
>>>> no userspace consumer for.
>>>>
>>>> Additionally, the GuC firmware on ModSched platforms no longer supports
>>>> multi-lrc on non-media engines.
>>>>
>>>> V3:
>>>> - store a multi-lrc enable class mask in xe->info and populate from
>>>> xe_device_desc in xe_pci.c (Matthew Brost)
>>>>
>>>> V2:
>>>> - correct the typo (Shuicheng)
>>>> - move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
>>>> - remove the graphics version check (Matt Roper)
>>>> - input more details in the commit info (Matt Roper)
>>>>
>>>> Cc: Shuicheng Lin <shuicheng.lin@intel.com>
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> Cc: Matthew Brost <matthew.brost@intel.com>
>>>> Signed-off-by: Xin Wang <x.wang@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>>>> drivers/gpu/drm/xe/xe_exec_queue.c | 5 +++++
>>>> drivers/gpu/drm/xe/xe_pci.c | 17 +++++++++++++++++
>>>> drivers/gpu/drm/xe/xe_pci_types.h | 1 +
>>>> 4 files changed, 25 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>>>> index 8f3ef836541e..caa8f34a6744 100644
>>>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>>>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>>>> @@ -138,6 +138,8 @@ struct xe_device {
>>>> u8 tile_count;
>>>> /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
>>>> u8 max_gt_per_tile;
>>>> + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */
>>>> + u8 multi_lrc_mask;
>>>> /** @info.gt_count: Total number of GTs for entire device */
>>>> u8 gt_count;
>>>> /** @info.vm_max_level: Max VM level */
>>>> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
>>>> index 66d0e10ee2c4..5abb29454d1f 100644
>>>> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
>>>> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
>>>> @@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
>>>> if (XE_IOCTL_DBG(xe, !hwe))
>>>> return -EINVAL;
>>>> + /* multi-lrc is only supported on select engine classes */
>>>> + if (XE_IOCTL_DBG(xe, args->width > 1 &&
>>>> + !(xe->info.multi_lrc_mask & BIT(hwe->class))))
>>>> + return -EOPNOTSUPP;
>>>> +
>>>> vm = xe_vm_lookup(xef, args->vm_id);
>>>> if (XE_IOCTL_DBG(xe, !vm))
>>>> return -ENOENT;
>>>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>>>> index e1f569235d8a..fe63387d4077 100644
>>>> --- a/drivers/gpu/drm/xe/xe_pci.c
>>>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>>>> @@ -194,6 +194,7 @@ static const struct xe_device_desc tgl_desc = {
>>>> .has_llc = true,
>>>> .has_sriov = true,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>>> Is there a reason why some platforms list both VCS + VECS but others
>>> only list VCS? The new .multi_lrc_mask is intended to restrict usage to
>>> just the engine type(s) where we have a real userspace consumer, and for
>>> now I'd expect that to be the same across all current platforms. We
> Matt R beat me to this suggestion too, +1.
>
>>> should double check whether the media driver is actively using this on
>>> both media engine types or just one of them (I don't know off the top of
>>> my head), and then set the mask accordingly.
>>>
>>> An ioctl request for multi-LRC might also get rejected on a platform if
>>> the engine fusing indicates that there aren't 2+ engines of the given
>>> type, but that's an orthogonal check that's independent of the
>>> multi_lrc_mask we're defining here. Finding out how many engines
>>> actually exist on a device is something that we can only find out at
>>> runtime after reading the fuse registers for a specific device.
>>>
>>>
>>> Matt
>> I checked the specs and found that some devices have fewer than two VCS or
>> VCES
>> instances. In these cases, I don't think it's necessary to allow multi-LRC
>> to
>> those engines. This would prevent the injection of some illegal ioctl
>> parameters.
> See Matt's response above, we check in the IOCTL how many engines the
> platform has, if it only has 1 the IOCTL will prevent multi-LRC queue
> from being created.
>
> So again, I'd just enable XE_ENGINE_CLASS_VIDEO_DECODE |
> XE_ENGINE_CLASS_VIDEO_ENHANCE on platforms.
>
> Matt
This means we can enable the VCS/VECS multi-lrc on all platforms without
considering the number of engines. I can create a macro definition and add
it to all current platforms.
#define MULTI_LRC_MASK \
.multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \
BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE)
My understanding is that the advantage of adding a mask for each platform
is that if we need to support multi-LRC for more engines in the future,
we can simply modify the platform's xe_device_desc without changing the
code logic.
Xin
>> Xin
>>>> .require_force_probe = true,
>>>> .va_bits = 48,
>>>> .vm_max_level = 3,
>>>> @@ -208,6 +209,7 @@ static const struct xe_device_desc rkl_desc = {
>>>> .has_display = true,
>>>> .has_llc = true,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>>>> .require_force_probe = true,
>>>> .va_bits = 48,
>>>> .vm_max_level = 3,
>>>> @@ -225,6 +227,7 @@ static const struct xe_device_desc adl_s_desc = {
>>>> .has_llc = true,
>>>> .has_sriov = true,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>>>> .require_force_probe = true,
>>>> .subplatforms = (const struct xe_subplatform_desc[]) {
>>>> { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
>>>> @@ -246,6 +249,7 @@ static const struct xe_device_desc adl_p_desc = {
>>>> .has_llc = true,
>>>> .has_sriov = true,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>>>> .require_force_probe = true,
>>>> .subplatforms = (const struct xe_subplatform_desc[]) {
>>>> { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
>>>> @@ -283,6 +287,7 @@ static const struct xe_device_desc dg1_desc = {
>>>> .has_gsc_nvm = 1,
>>>> .has_heci_gscfi = 1,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>>>> .require_force_probe = true,
>>>> .va_bits = 48,
>>>> .vm_max_level = 3,
>>>> @@ -313,6 +318,8 @@ static const struct xe_device_desc ats_m_desc = {
>>>> .pre_gmdid_media_ip = &media_ip_xehpm,
>>>> .dma_mask_size = 46,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>>>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>>>> .require_force_probe = true,
>>>> DG2_FEATURES,
>>>> @@ -325,6 +332,8 @@ static const struct xe_device_desc dg2_desc = {
>>>> .pre_gmdid_media_ip = &media_ip_xehpm,
>>>> .dma_mask_size = 46,
>>>> .max_gt_per_tile = 1,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>>>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>>>> .require_force_probe = true,
>>>> DG2_FEATURES,
>>>> @@ -358,6 +367,7 @@ static const struct xe_device_desc mtl_desc = {
>>>> .has_display = true,
>>>> .has_pxp = true,
>>>> .max_gt_per_tile = 2,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
>>>> .va_bits = 48,
>>>> .vm_max_level = 3,
>>>> };
>>>> @@ -393,6 +403,8 @@ static const struct xe_device_desc bmg_desc = {
>>>> .has_soc_remapper_telem = true,
>>>> .has_sriov = true,
>>>> .max_gt_per_tile = 2,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>>>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>>>> .needs_scratch = true,
>>>> .subplatforms = (const struct xe_subplatform_desc[]) {
>>>> { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
>>>> @@ -445,6 +457,8 @@ static const struct xe_device_desc cri_desc = {
>>>> .has_soc_remapper_telem = true,
>>>> .has_sriov = true,
>>>> .max_gt_per_tile = 2,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>>>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>>>> .require_force_probe = true,
>>>> .va_bits = 57,
>>>> .vm_max_level = 4,
>>>> @@ -459,6 +473,8 @@ static const struct xe_device_desc nvlp_desc = {
>>>> .has_page_reclaim_hw_assist = true,
>>>> .has_pre_prod_wa = true,
>>>> .max_gt_per_tile = 2,
>>>> + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
>>>> + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
>>>> .require_force_probe = true,
>>>> .va_bits = 48,
>>>> .vm_max_level = 4,
>>>> @@ -746,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
>>>> xe->info.skip_pcode = desc->skip_pcode;
>>>> xe->info.needs_scratch = desc->needs_scratch;
>>>> xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
>>>> + xe->info.multi_lrc_mask = desc->multi_lrc_mask;
>>>> xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
>>>> xe_modparam.probe_display &&
>>>> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
>>>> index 470d31a1f0d6..47e8a1552c2b 100644
>>>> --- a/drivers/gpu/drm/xe/xe_pci_types.h
>>>> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
>>>> @@ -30,6 +30,7 @@ struct xe_device_desc {
>>>> u8 dma_mask_size;
>>>> u8 max_remote_tiles:2;
>>>> u8 max_gt_per_tile:2;
>>>> + u8 multi_lrc_mask;
>>>> u8 va_bits;
>>>> u8 vm_max_level;
>>>> u8 vram_flags;
>>>> --
>>>> 2.43.0
>>>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines
2026-02-24 22:57 ` Wang, X
@ 2026-02-24 23:03 ` Matthew Brost
0 siblings, 0 replies; 7+ messages in thread
From: Matthew Brost @ 2026-02-24 23:03 UTC (permalink / raw)
To: Wang, X; +Cc: Matt Roper, intel-xe, Shuicheng Lin
On Tue, Feb 24, 2026 at 02:57:48PM -0800, Wang, X wrote:
>
> On 2/24/2026 14:40, Matthew Brost wrote:
> > On Tue, Feb 24, 2026 at 02:20:33PM -0800, Wang, X wrote:
> > > On 2/24/2026 14:05, Matt Roper wrote:
> > > > On Mon, Feb 23, 2026 at 06:33:54PM -0800, Xin Wang wrote:
> > > > > Tighten uapi validation to restrict multi-lrc support to VIDEO_DECODE and
> > > > > VIDEO_ENHANCE engines only. This check should have been in place from the
> > > > > start, as the driver typically avoids allowing uapi cases that we have
> > > > > no userspace consumer for.
> > > > >
> > > > > Additionally, the GuC firmware on ModSched platforms no longer supports
> > > > > multi-lrc on non-media engines.
> > > > >
> > > > > V3:
> > > > > - store a multi-lrc enable class mask in xe->info and populate from
> > > > > xe_device_desc in xe_pci.c (Matthew Brost)
> > > > >
> > > > > V2:
> > > > > - correct the typo (Shuicheng)
> > > > > - move the check earlier to avoid VM lookup (Shuicheng, Matt Roper)
> > > > > - remove the graphics version check (Matt Roper)
> > > > > - input more details in the commit info (Matt Roper)
> > > > >
> > > > > Cc: Shuicheng Lin <shuicheng.lin@intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Matthew Brost <matthew.brost@intel.com>
> > > > > Signed-off-by: Xin Wang <x.wang@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/xe/xe_device_types.h | 2 ++
> > > > > drivers/gpu/drm/xe/xe_exec_queue.c | 5 +++++
> > > > > drivers/gpu/drm/xe/xe_pci.c | 17 +++++++++++++++++
> > > > > drivers/gpu/drm/xe/xe_pci_types.h | 1 +
> > > > > 4 files changed, 25 insertions(+)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > > > > index 8f3ef836541e..caa8f34a6744 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > > > @@ -138,6 +138,8 @@ struct xe_device {
> > > > > u8 tile_count;
> > > > > /** @info.max_gt_per_tile: Number of GT IDs allocated to each tile */
> > > > > u8 max_gt_per_tile;
> > > > > + /** @info.multi_lrc_mask: bitmask of engine classes which support multi-lrc */
> > > > > + u8 multi_lrc_mask;
> > > > > /** @info.gt_count: Total number of GTs for entire device */
> > > > > u8 gt_count;
> > > > > /** @info.vm_max_level: Max VM level */
> > > > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > index 66d0e10ee2c4..5abb29454d1f 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > > > > @@ -1184,6 +1184,11 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
> > > > > if (XE_IOCTL_DBG(xe, !hwe))
> > > > > return -EINVAL;
> > > > > + /* multi-lrc is only supported on select engine classes */
> > > > > + if (XE_IOCTL_DBG(xe, args->width > 1 &&
> > > > > + !(xe->info.multi_lrc_mask & BIT(hwe->class))))
> > > > > + return -EOPNOTSUPP;
> > > > > +
> > > > > vm = xe_vm_lookup(xef, args->vm_id);
> > > > > if (XE_IOCTL_DBG(xe, !vm))
> > > > > return -ENOENT;
> > > > > diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> > > > > index e1f569235d8a..fe63387d4077 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > > > @@ -194,6 +194,7 @@ static const struct xe_device_desc tgl_desc = {
> > > > > .has_llc = true,
> > > > > .has_sriov = true,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > > Is there a reason why some platforms list both VCS + VECS but others
> > > > only list VCS? The new .multi_lrc_mask is intended to restrict usage to
> > > > just the engine type(s) where we have a real userspace consumer, and for
> > > > now I'd expect that to be the same across all current platforms. We
> > Matt R beat me to this suggestion too, +1.
> >
> > > > should double check whether the media driver is actively using this on
> > > > both media engine types or just one of them (I don't know off the top of
> > > > my head), and then set the mask accordingly.
> > > >
> > > > An ioctl request for multi-LRC might also get rejected on a platform if
> > > > the engine fusing indicates that there aren't 2+ engines of the given
> > > > type, but that's an orthogonal check that's independent of the
> > > > multi_lrc_mask we're defining here. Finding out how many engines
> > > > actually exist on a device is something that we can only find out at
> > > > runtime after reading the fuse registers for a specific device.
> > > >
> > > >
> > > > Matt
> > > I checked the specs and found that some devices have fewer than two VCS or
> > > VCES
> > > instances. In these cases, I don't think it's necessary to allow multi-LRC
> > > to
> > > those engines. This would prevent the injection of some illegal ioctl
> > > parameters.
> > See Matt's response above, we check in the IOCTL how many engines the
> > platform has, if it only has 1 the IOCTL will prevent multi-LRC queue
> > from being created.
> >
> > So again, I'd just enable XE_ENGINE_CLASS_VIDEO_DECODE |
> > XE_ENGINE_CLASS_VIDEO_ENHANCE on platforms.
> >
> > Matt
> This means we can enable the VCS/VECS multi-lrc on all platforms without
> considering the number of engines. I can create a macro definition and add
> it to all current platforms.
>
> #define MULTI_LRC_MASK \
> .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) | \
> BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE)
>
> My understanding is that the advantage of adding a mask for each platform
> is that if we need to support multi-LRC for more engines in the future,
> we can simply modify the platform's xe_device_desc without changing the
> code logic.
Correct. Most behavioral choices in our driver should be encoded in the
xe_pci.c descriptors, which propagate into xe->info, and then the core
driver logic operates on xe->info to decide the appropriate behavior as
needed.
Matt
> Xin
> > > Xin
> > > > > .require_force_probe = true,
> > > > > .va_bits = 48,
> > > > > .vm_max_level = 3,
> > > > > @@ -208,6 +209,7 @@ static const struct xe_device_desc rkl_desc = {
> > > > > .has_display = true,
> > > > > .has_llc = true,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > > > .require_force_probe = true,
> > > > > .va_bits = 48,
> > > > > .vm_max_level = 3,
> > > > > @@ -225,6 +227,7 @@ static const struct xe_device_desc adl_s_desc = {
> > > > > .has_llc = true,
> > > > > .has_sriov = true,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > > > .require_force_probe = true,
> > > > > .subplatforms = (const struct xe_subplatform_desc[]) {
> > > > > { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
> > > > > @@ -246,6 +249,7 @@ static const struct xe_device_desc adl_p_desc = {
> > > > > .has_llc = true,
> > > > > .has_sriov = true,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > > > .require_force_probe = true,
> > > > > .subplatforms = (const struct xe_subplatform_desc[]) {
> > > > > { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
> > > > > @@ -283,6 +287,7 @@ static const struct xe_device_desc dg1_desc = {
> > > > > .has_gsc_nvm = 1,
> > > > > .has_heci_gscfi = 1,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > > > .require_force_probe = true,
> > > > > .va_bits = 48,
> > > > > .vm_max_level = 3,
> > > > > @@ -313,6 +318,8 @@ static const struct xe_device_desc ats_m_desc = {
> > > > > .pre_gmdid_media_ip = &media_ip_xehpm,
> > > > > .dma_mask_size = 46,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > > > .require_force_probe = true,
> > > > > DG2_FEATURES,
> > > > > @@ -325,6 +332,8 @@ static const struct xe_device_desc dg2_desc = {
> > > > > .pre_gmdid_media_ip = &media_ip_xehpm,
> > > > > .dma_mask_size = 46,
> > > > > .max_gt_per_tile = 1,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > > > .require_force_probe = true,
> > > > > DG2_FEATURES,
> > > > > @@ -358,6 +367,7 @@ static const struct xe_device_desc mtl_desc = {
> > > > > .has_display = true,
> > > > > .has_pxp = true,
> > > > > .max_gt_per_tile = 2,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE),
> > > > > .va_bits = 48,
> > > > > .vm_max_level = 3,
> > > > > };
> > > > > @@ -393,6 +403,8 @@ static const struct xe_device_desc bmg_desc = {
> > > > > .has_soc_remapper_telem = true,
> > > > > .has_sriov = true,
> > > > > .max_gt_per_tile = 2,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > > > .needs_scratch = true,
> > > > > .subplatforms = (const struct xe_subplatform_desc[]) {
> > > > > { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
> > > > > @@ -445,6 +457,8 @@ static const struct xe_device_desc cri_desc = {
> > > > > .has_soc_remapper_telem = true,
> > > > > .has_sriov = true,
> > > > > .max_gt_per_tile = 2,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > > > .require_force_probe = true,
> > > > > .va_bits = 57,
> > > > > .vm_max_level = 4,
> > > > > @@ -459,6 +473,8 @@ static const struct xe_device_desc nvlp_desc = {
> > > > > .has_page_reclaim_hw_assist = true,
> > > > > .has_pre_prod_wa = true,
> > > > > .max_gt_per_tile = 2,
> > > > > + .multi_lrc_mask = BIT(XE_ENGINE_CLASS_VIDEO_DECODE) |
> > > > > + BIT(XE_ENGINE_CLASS_VIDEO_ENHANCE),
> > > > > .require_force_probe = true,
> > > > > .va_bits = 48,
> > > > > .vm_max_level = 4,
> > > > > @@ -746,6 +762,7 @@ static int xe_info_init_early(struct xe_device *xe,
> > > > > xe->info.skip_pcode = desc->skip_pcode;
> > > > > xe->info.needs_scratch = desc->needs_scratch;
> > > > > xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
> > > > > + xe->info.multi_lrc_mask = desc->multi_lrc_mask;
> > > > > xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
> > > > > xe_modparam.probe_display &&
> > > > > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> > > > > index 470d31a1f0d6..47e8a1552c2b 100644
> > > > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > > > @@ -30,6 +30,7 @@ struct xe_device_desc {
> > > > > u8 dma_mask_size;
> > > > > u8 max_remote_tiles:2;
> > > > > u8 max_gt_per_tile:2;
> > > > > + u8 multi_lrc_mask;
> > > > > u8 va_bits;
> > > > > u8 vm_max_level;
> > > > > u8 vram_flags;
> > > > > --
> > > > > 2.43.0
> > > > >
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2026-02-24 23:03 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-24 2:33 [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Xin Wang
2026-02-24 2:40 ` ✓ CI.KUnit: success for drm/xe: restrict multi-lrc to VCS/VECS engines (rev2) Patchwork
2026-02-24 22:05 ` [PATCH v3] drm/xe: restrict multi-lrc to VCS/VECS engines Matt Roper
2026-02-24 22:20 ` Wang, X
2026-02-24 22:40 ` Matthew Brost
2026-02-24 22:57 ` Wang, X
2026-02-24 23:03 ` Matthew Brost
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