[PATCH v2 0/4] Introduce Xe Correctable Error Handling

[PATCH v2 0/4] Introduce Xe Correctable Error Handling

[Raag Jadav]

This series builds on top of system controller series[1] and adds initial
support for correctable error handling in xe. This serves as a foundation
for RAS infrastructure and will be further extended to facilitate other
RAS features.

Detailed description in commit message.

[1] https://patchwork.freedesktop.org/series/159554/

v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
    Handle unexpected response length (Mallesh)

Anoop Vijay (1):
  drm/xe/sysctrl: Add System Controller

Raag Jadav (3):
  drm/xe/sysctrl: Add system controller interrupt handler
  drm/xe/sysctrl: Add system controller event support
  drm/xe/ras: Introduce correctable error handling

 drivers/gpu/drm/xe/Makefile                   |   4 +
 drivers/gpu/drm/xe/regs/xe_irq_regs.h         |   1 +
 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h     |  36 ++
 drivers/gpu/drm/xe/xe_device.c                |   5 +
 drivers/gpu/drm/xe/xe_device_types.h          |   6 +
 drivers/gpu/drm/xe/xe_irq.c                   |   2 +
 drivers/gpu/drm/xe/xe_pci.c                   |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
 drivers/gpu/drm/xe/xe_ras.c                   |  87 ++++
 drivers/gpu/drm/xe/xe_ras.h                   |  14 +
 drivers/gpu/drm/xe/xe_ras_types.h             |  79 ++++
 drivers/gpu/drm/xe/xe_sysctrl.c               | 110 +++++
 drivers/gpu/drm/xe/xe_sysctrl.h               |  17 +
 drivers/gpu/drm/xe/xe_sysctrl_event.c         |  77 ++++
 drivers/gpu/drm/xe/xe_sysctrl_event_types.h   |  49 +++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c       | 390 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h       |  45 ++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  42 ++
 drivers/gpu/drm/xe/xe_sysctrl_types.h         |  40 ++
 19 files changed, 1007 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_ras.c
 create mode 100644 drivers/gpu/drm/xe/xe_ras.h
 create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h

-- 
2.43.0

[PATCH v2 1/4] drm/xe/sysctrl: Add System Controller

[Raag Jadav]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Do not review, CI only.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
 drivers/gpu/drm/xe/Makefile                   |   2 +
 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h     |  36 ++
 drivers/gpu/drm/xe/xe_device.c                |   5 +
 drivers/gpu/drm/xe/xe_device_types.h          |   6 +
 drivers/gpu/drm/xe/xe_pci.c                   |   2 +
 drivers/gpu/drm/xe/xe_pci_types.h             |   1 +
 drivers/gpu/drm/xe/xe_sysctrl.c               |  80 ++++
 drivers/gpu/drm/xe/xe_sysctrl.h               |  13 +
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c       | 390 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h       |  35 ++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  42 ++
 drivers/gpu/drm/xe/xe_sysctrl_types.h         |  33 ++
 12 files changed, 645 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 4a7eaeeca293..8005293dc30f 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -122,6 +122,8 @@ xe-y += xe_bb.o \
 	xe_step.o \
 	xe_survivability_mode.o \
 	xe_sync.o \
+	xe_sysctrl.o \
+	xe_sysctrl_mailbox.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
 	xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
new file mode 100644
index 000000000000..2e91febfa9a2
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_REGS_H_
+#define _XE_SYSCTRL_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET			0xdb000
+#define SYSCTRL_BASE				(SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX			0x03
+#define SYSCTRL_BAR_LENGTH			0x1000
+
+#define SYSCTRL_MB_CTRL				XE_REG(0x10)
+#define   SYSCTRL_MB_CTRL_RUN_BUSY		REG_BIT(31)
+#define   SYSCTRL_MB_CTRL_IRQ			REG_BIT(30)
+#define   SYSCTRL_MB_CTRL_RUN_BUSY_OUT		REG_BIT(29)
+#define   SYSCTRL_MB_CTRL_PARAM3_MASK		REG_GENMASK(28, 24)
+#define   SYSCTRL_MB_CTRL_PARAM2_MASK		REG_GENMASK(23, 16)
+#define   SYSCTRL_MB_CTRL_PARAM1_MASK		REG_GENMASK(15, 8)
+#define   SYSCTRL_MB_CTRL_COMMAND_MASK		REG_GENMASK(7, 0)
+#define   SYSCTRL_MB_CTRL_MKHI_CMD		REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5)
+
+#define SYSCTRL_MB_DATA0			XE_REG(0x14)
+#define SYSCTRL_MB_DATA1			XE_REG(0x18)
+#define SYSCTRL_MB_DATA2			XE_REG(0x1C)
+#define SYSCTRL_MB_DATA3			XE_REG(0x20)
+
+#define MKHI_FRAME_PHASE			REG_BIT(24)
+#define MKHI_FRAME_CURRENT_MASK			REG_GENMASK(21, 16)
+#define MKHI_FRAME_TOTAL_MASK			REG_GENMASK(13, 8)
+#define MKHI_FRAME_COMMAND_MASK			REG_GENMASK(7, 0)
+
+#endif /* _XE_SYSCTRL_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 4b68a2d55651..4a5922b25ca3 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -65,6 +65,7 @@
 #include "xe_survivability_mode.h"
 #include "xe_sriov.h"
 #include "xe_svm.h"
+#include "xe_sysctrl.h"
 #include "xe_tile.h"
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_ttm_sys_mgr.h"
@@ -985,6 +986,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err_unregister_display;
 
+	err = xe_sysctrl_init(xe);
+	if (err)
+		goto err_unregister_display;
+
 	err = xe_device_sysfs_init(xe);
 	if (err)
 		goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 059f026e80d5..eb337fc65dd6 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -26,6 +26,7 @@
 #include "xe_sriov_vf_ccs_types.h"
 #include "xe_step_types.h"
 #include "xe_survivability_mode_types.h"
+#include "xe_sysctrl_types.h"
 #include "xe_tile_types.h"
 #include "xe_validation.h"
 
@@ -202,6 +203,8 @@ struct xe_device {
 		u8 has_soc_remapper_telem:1;
 		/** @info.has_sriov: Supports SR-IOV */
 		u8 has_sriov:1;
+		/** @info.has_sysctrl: Supports System Controller */
+		u8 has_sysctrl:1;
 		/** @info.has_usm: Device has unified shared memory support */
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -470,6 +473,9 @@ struct xe_device {
 	/** @heci_gsc: graphics security controller */
 	struct xe_heci_gsc heci_gsc;
 
+	/** @sc: System Controller */
+	struct xe_sysctrl sc;
+
 	/** @nvm: discrete graphics non-volatile memory */
 	struct intel_dg_nvm_dev *nvm;
 
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 56a768f2cfca..0a3bc5067a76 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -444,6 +444,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_soc_remapper_sysctrl = true,
 	.has_soc_remapper_telem = true,
 	.has_sriov = true,
+	.has_sysctrl = true,
 	.max_gt_per_tile = 2,
 	.require_force_probe = true,
 	.va_bits = 57,
@@ -740,6 +741,7 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 		desc->has_sriov;
+	xe->info.has_sysctrl = desc->has_sysctrl;
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
 	xe->info.skip_mtcfg = desc->skip_mtcfg;
 	xe->info.skip_pcode = desc->skip_pcode;
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 470d31a1f0d6..00dbe98653ba 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -56,6 +56,7 @@ struct xe_device_desc {
 	u8 has_soc_remapper_sysctrl:1;
 	u8 has_soc_remapper_telem:1;
 	u8 has_sriov:1;
+	u8 has_sysctrl:1;
 	u8 needs_scratch:1;
 	u8 skip_guc_pc:1;
 	u8 skip_mtcfg:1;
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
new file mode 100644
index 000000000000..430bccbdc3b9
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <drm/drm_managed.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_printk.h"
+#include "xe_soc_remapper.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+
+/**
+ * DOC: System Controller (sysctrl)
+ *
+ * The System Controller (sysctrl) is an embedded microcontroller in Intel GPUs
+ * responsible for managing various low-level platform functions. Communication
+ * between the driver and the System Controller occurs via a mailbox interface,
+ * enabling the exchange of commands and responses.
+ *
+ * This module provides initialization routines and helper functions to interact
+ * with the System Controller through the mailbox.
+ */
+
+static void xe_sysctrl_fini(void *arg)
+{
+	struct xe_device *xe = arg;
+
+	xe->soc_remapper.set_sysctrl_region(xe, 0);
+}
+
+/**
+ * xe_sysctrl_init - Initialize System Controller subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for System Controller initialization, called from xe_device_probe.
+ * This function checks platform support and initializes the system controller.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_init(struct xe_device *xe)
+{
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+	struct xe_sysctrl *sc = &xe->sc;
+	int ret;
+
+	if (!xe->info.has_sysctrl)
+		return 0;
+
+	if (!xe->soc_remapper.set_sysctrl_region)
+		return -ENODEV;
+
+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+	ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
+	if (ret)
+		return ret;
+
+	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
+	if (!sc->mmio)
+		return -ENOMEM;
+
+	xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
+	sc->mmio->adj_offset = SYSCTRL_BASE;
+	sc->mmio->adj_limit = U32_MAX;
+
+	ret = drmm_mutex_init(&xe->drm, &sc->cmd_lock);
+	if (ret)
+		return ret;
+
+	xe_sysctrl_mailbox_init(sc);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
new file mode 100644
index 000000000000..ee7826fe4c98
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_H_
+#define _XE_SYSCTRL_H_
+
+struct xe_device;
+
+int xe_sysctrl_init(struct xe_device *xe);
+
+#endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
new file mode 100644
index 000000000000..15a186a6f057
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/container_of.h>
+#include <linux/errno.h>
+#include <linux/minmax.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_device_types.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+#include "xe_sysctrl_types.h"
+
+#define MKHI_HDR_GROUP_ID_MASK		GENMASK(7, 0)
+#define MKHI_HDR_COMMAND_MASK		GENMASK(14, 8)
+#define MKHI_HDR_IS_RESPONSE		BIT(15)
+#define MKHI_HDR_RESERVED_MASK		GENMASK(23, 16)
+#define MKHI_HDR_RESULT_MASK		GENMASK(31, 24)
+
+#define XE_SYSCTRL_MKHI_HDR_GROUP_ID(hdr) \
+	FIELD_GET(MKHI_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_COMMAND(hdr) \
+	FIELD_GET(MKHI_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(hdr) \
+	FIELD_GET(MKHI_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_MKHI_HDR_RESULT(hdr) \
+	FIELD_GET(MKHI_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
+
+static struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
+{
+	return container_of(sc, struct xe_device, sc);
+}
+
+static bool xe_sysctrl_mailbox_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
+					      unsigned int timeout_ms)
+{
+	int ret;
+
+	ret = xe_mmio_wait32_not(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+				 timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static bool xe_sysctrl_mailbox_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
+					    unsigned int timeout_ms)
+{
+	int ret;
+
+	ret = xe_mmio_wait32(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+			     timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static int xe_sysctrl_mailbox_write_frame(struct xe_sysctrl *sc, const void *frame,
+					  size_t len)
+{
+	static const struct xe_reg regs[] = {
+		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+	};
+	u32 val[SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+	u32 i;
+
+	memcpy(val, frame, len);
+
+	for (i = 0; i < dw; i++)
+		xe_mmio_write32(sc->mmio, regs[i], val[i]);
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_read_frame(struct xe_sysctrl *sc, void *frame,
+					 size_t len)
+{
+	static const struct xe_reg regs[] = {
+		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+	};
+	u32 val[SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+	u32 i;
+
+	for (i = 0; i < dw; i++)
+		val[i] = xe_mmio_read32(sc->mmio, regs[i]);
+
+	memcpy(frame, val, len);
+
+	return 0;
+}
+
+static void xe_sysctrl_mailbox_clear_response(struct xe_sysctrl *sc)
+{
+	xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);
+}
+
+static int xe_sysctrl_mailbox_prepare_command(struct xe_device *xe,
+					      u8 group_id, u8 command,
+					      const void *data_in, size_t data_in_len,
+					      u8 **mbox_cmd, size_t *cmd_size)
+{
+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+	size_t size;
+	u8 *buffer;
+
+	if (data_in_len > SYSCTRL_MB_MAX_MESSAGE_SIZE - sizeof(*mkhi_hdr)) {
+		xe_err(xe, "sysctrl: Input data too large: %zu bytes\n", data_in_len);
+		return -EINVAL;
+	}
+
+	size = sizeof(*mkhi_hdr) + data_in_len;
+
+	buffer = kmalloc(size, GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	mkhi_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)buffer;
+	mkhi_hdr->data = cpu_to_le32(FIELD_PREP(MKHI_HDR_GROUP_ID_MASK, group_id) |
+				     FIELD_PREP(MKHI_HDR_COMMAND_MASK, command & 0x7F) |
+				     FIELD_PREP(MKHI_HDR_IS_RESPONSE, 0) |
+				     FIELD_PREP(MKHI_HDR_RESERVED_MASK, 0) |
+				     FIELD_PREP(MKHI_HDR_RESULT_MASK, 0));
+
+	if (data_in && data_in_len)
+		memcpy(buffer + sizeof(*mkhi_hdr), data_in, data_in_len);
+
+	*mbox_cmd = buffer;
+	*cmd_size = size;
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_send_frames(struct xe_sysctrl *sc,
+					  const u8 *mbox_cmd,
+					  size_t cmd_size, unsigned int timeout_ms)
+{
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 ctrl_reg, total_frames, frame;
+	size_t bytes_sent, frame_size;
+
+	total_frames = DIV_ROUND_UP(cmd_size, SYSCTRL_MB_FRAME_SIZE);
+
+	if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+		xe_err(xe, "sysctrl: Mailbox busy\n");
+		return -EBUSY;
+	}
+
+	sc->phase_bit ^= 1;
+	bytes_sent = 0;
+
+	for (frame = 0; frame < total_frames; frame++) {
+		frame_size = min_t(size_t, cmd_size - bytes_sent, SYSCTRL_MB_FRAME_SIZE);
+
+		if (xe_sysctrl_mailbox_write_frame(sc, mbox_cmd + bytes_sent, frame_size)) {
+			xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
+			sc->phase_bit = 0;
+			return -EIO;
+		}
+
+		ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY |
+			   FIELD_PREP(MKHI_FRAME_CURRENT_MASK, frame) |
+			   FIELD_PREP(MKHI_FRAME_TOTAL_MASK, total_frames - 1) |
+			   SYSCTRL_MB_CTRL_MKHI_CMD |
+			   (sc->phase_bit ? MKHI_FRAME_PHASE : 0);
+
+		xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg);
+
+		if (!xe_sysctrl_mailbox_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+			xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
+			sc->phase_bit = 0;
+			return -ETIMEDOUT;
+		}
+
+		bytes_sent += frame_size;
+	}
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_process_frame(struct xe_sysctrl *sc, void *out,
+					    size_t frame_size, unsigned int timeout_ms,
+					    bool *done)
+{
+	u32 curr_frame, total_frames, ctrl_reg;
+	struct xe_device *xe = sc_to_xe(sc);
+	int ret;
+
+	if (!xe_sysctrl_mailbox_wait_bit_set(sc, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+		xe_err(xe, "sysctrl: Response frame timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+	total_frames = FIELD_GET(MKHI_FRAME_TOTAL_MASK, ctrl_reg);
+	curr_frame = FIELD_GET(MKHI_FRAME_CURRENT_MASK, ctrl_reg);
+
+	ret = xe_sysctrl_mailbox_read_frame(sc, out, frame_size);
+	if (ret)
+		return ret;
+
+	xe_sysctrl_mailbox_clear_response(sc);
+
+	if (curr_frame == total_frames)
+		*done = true;
+
+	return 0;
+}
+
+static int xe_sysctrl_mailbox_receive_frames(struct xe_sysctrl *sc,
+					     const struct xe_sysctrl_mailbox_mkhi_msg_hdr *req,
+					     void *data_out, size_t data_out_len,
+					     size_t *rdata_len, unsigned int timeout_ms)
+{
+	struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+	struct xe_device *xe = sc_to_xe(sc);
+	size_t frame_size, remain;
+	bool done = false;
+	u8 *out;
+	int ret = 0;
+
+	remain = sizeof(*mkhi_hdr) + data_out_len;
+	u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	out = buffer;
+	while (!done && remain) {
+		frame_size = min_t(size_t, remain, SYSCTRL_MB_FRAME_SIZE);
+
+		ret = xe_sysctrl_mailbox_process_frame(sc, out, frame_size, timeout_ms,
+						       &done);
+		if (ret)
+			return ret;
+
+		remain -= frame_size;
+		out += frame_size;
+	}
+
+	mkhi_hdr = (struct xe_sysctrl_mailbox_mkhi_msg_hdr *)buffer;
+
+	if (!XE_SYSCTRL_MKHI_HDR_IS_RESPONSE(mkhi_hdr) ||
+	    XE_SYSCTRL_MKHI_HDR_GROUP_ID(mkhi_hdr) != XE_SYSCTRL_MKHI_HDR_GROUP_ID(req) ||
+	    XE_SYSCTRL_MKHI_HDR_COMMAND(mkhi_hdr) != XE_SYSCTRL_MKHI_HDR_COMMAND(req)) {
+		xe_err(xe, "sysctrl: Response header mismatch\n");
+		return -EPROTO;
+	}
+
+	if (XE_SYSCTRL_MKHI_HDR_RESULT(mkhi_hdr) != 0) {
+		xe_err(xe, "sysctrl: Firmware error: 0x%02lx\n",
+		       XE_SYSCTRL_MKHI_HDR_RESULT(mkhi_hdr));
+		return -EIO;
+	}
+
+	memcpy(data_out, mkhi_hdr + 1, data_out_len);
+	*rdata_len = out - buffer - sizeof(*mkhi_hdr);
+
+	return ret;
+}
+
+static int xe_sysctrl_mailbox_send_command(struct xe_sysctrl *sc,
+					   const u8 *mbox_cmd, size_t cmd_size,
+					   void *data_out, size_t data_out_len,
+					   size_t *rdata_len, unsigned int timeout_ms)
+{
+	const struct xe_sysctrl_mailbox_mkhi_msg_hdr *mkhi_hdr;
+	size_t received;
+	int ret;
+
+	ret = xe_sysctrl_mailbox_send_frames(sc, mbox_cmd, cmd_size, timeout_ms);
+	if (ret)
+		return ret;
+
+	if (!data_out || !rdata_len)
+		return 0;
+
+	mkhi_hdr = (const struct xe_sysctrl_mailbox_mkhi_msg_hdr *)mbox_cmd;
+
+	ret = xe_sysctrl_mailbox_receive_frames(sc, mkhi_hdr, data_out, data_out_len,
+						&received, timeout_ms);
+	if (ret)
+		return ret;
+
+	*rdata_len = received;
+
+	return 0;
+}
+
+/**
+ * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface
+ * @sc: System controller structure
+ *
+ * Initialize system controller mailbox interface for communication.
+ */
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
+{
+	u32 ctrl_reg;
+
+	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+	sc->phase_bit = (ctrl_reg & MKHI_FRAME_PHASE) ? 1 : 0;
+}
+
+/**
+ * xe_sysctrl_send_command - Send command to System Controller via mailbox
+ * @xe: XE device instance
+ * @cmd: Pointer to xe_sysctrl_mailbox_command structure
+ * @rdata_len: Pointer to store actual response data size (can be NULL)
+ *
+ * Send a command to the System Controller using MKHI protocol. Handles
+ * command preparation, fragmentation, transmission, and response reception.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_sysctrl_send_command(struct xe_device *xe,
+			    struct xe_sysctrl_mailbox_command *cmd,
+			    size_t *rdata_len)
+{
+	struct xe_sysctrl *sc;
+	u8 group_id, command_code;
+	u8 *mbox_cmd = NULL;
+	size_t cmd_size = 0;
+	int ret = 0;
+
+	if (!xe) {
+		pr_err("sysctrl: Invalid device handle\n");
+		return -EINVAL;
+	}
+
+	if (!xe->info.has_sysctrl)
+		return -ENODEV;
+
+	sc = &xe->sc;
+
+	if (!cmd) {
+		xe_err(xe, "sysctrl: Invalid command buffer\n");
+		return -EINVAL;
+	}
+
+	group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
+	command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
+
+	if (!cmd->data_in && cmd->data_in_len) {
+		xe_err(xe, "sysctrl: Invalid input parameters\n");
+		return -EINVAL;
+	}
+
+	if (!cmd->data_out && cmd->data_out_len) {
+		xe_err(xe, "sysctrl: Invalid output parameters\n");
+		return -EINVAL;
+	}
+
+	might_sleep();
+
+	ret = xe_sysctrl_mailbox_prepare_command(xe, group_id, command_code,
+						 cmd->data_in, cmd->data_in_len,
+						 &mbox_cmd, &cmd_size);
+	if (ret) {
+		xe_err(xe, "sysctrl: Failed to prepare command: %d\n", ret);
+		return ret;
+	}
+
+	guard(xe_pm_runtime)(xe);
+
+	guard(mutex)(&sc->cmd_lock);
+
+	ret = xe_sysctrl_mailbox_send_command(sc, mbox_cmd, cmd_size,
+					      cmd->data_out, cmd->data_out_len, rdata_len,
+					      SYSCTRL_MB_DEFAULT_TIMEOUT_MS);
+	if (ret)
+		xe_err(xe, "sysctrl: Mailbox command failed: %d\n", ret);
+
+	kfree(mbox_cmd);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
new file mode 100644
index 000000000000..2b64165c8e76
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __XE_SYSCTRL_MAILBOX_H__
+#define __XE_SYSCTRL_MAILBOX_H__
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+struct xe_sysctrl;
+struct xe_device;
+struct xe_sysctrl_mailbox_command;
+
+#define APP_HDR_GROUP_ID_MASK			GENMASK(7, 0)
+#define APP_HDR_COMMAND_MASK			GENMASK(15, 8)
+#define APP_HDR_VERSION_MASK			GENMASK(23, 16)
+#define APP_HDR_RESERVED_MASK			GENMASK(31, 24)
+
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
+	FIELD_GET(APP_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
+	FIELD_GET(APP_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
+	FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
+int xe_sysctrl_send_command(struct xe_device *xe,
+			    struct xe_sysctrl_mailbox_command *cmd,
+			    size_t *rdata_len);
+
+#endif /* __XE_SYSCTRL_MAILBOX_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
new file mode 100644
index 000000000000..ce10924c5881
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __XE_SYSCTRL_MAILBOX_TYPES_H__
+#define __XE_SYSCTRL_MAILBOX_TYPES_H__
+
+#include <linux/types.h>
+
+struct xe_sysctrl_mailbox_mkhi_msg_hdr {
+	__le32 data;
+} __packed;
+
+struct xe_sysctrl_mailbox_app_msg_hdr {
+	__le32 data;
+} __packed;
+
+struct xe_sysctrl_mailbox_command {
+	/** @header: Application message header containing command information */
+	struct xe_sysctrl_mailbox_app_msg_hdr header;
+
+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
+	void *data_in;
+
+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
+	size_t data_in_len;
+
+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+	void *data_out;
+
+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+	size_t data_out_len;
+};
+
+#define SYSCTRL_MB_FRAME_SIZE			16
+#define SYSCTRL_MB_MAX_FRAMES			64
+#define SYSCTRL_MB_MAX_MESSAGE_SIZE		(SYSCTRL_MB_FRAME_SIZE * SYSCTRL_MB_MAX_FRAMES)
+
+#define SYSCTRL_MB_DEFAULT_TIMEOUT_MS		500
+
+#endif /* __XE_SYSCTRL_MAILBOX_TYPES_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
new file mode 100644
index 000000000000..d4a362564925
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_TYPES_H_
+#define _XE_SYSCTRL_TYPES_H_
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+
+struct xe_mmio;
+
+/**
+ * struct xe_sysctrl - System Controller driver context
+ */
+struct xe_sysctrl {
+	/** @mmio: MMIO region for system control registers */
+	struct xe_mmio *mmio;
+
+	/** @cmd_lock: Mutex protecting mailbox command operations */
+	struct mutex cmd_lock;
+
+	/**
+	 * @phase_bit: MKHI message boundary phase toggle bit
+	 *
+	 * Phase bit alternates between 0 and 1 for consecutive
+	 * messages to help distinguish message boundaries.
+	 */
+	bool phase_bit;
+};
+
+#endif /* _XE_SYSCTRL_TYPES_H_ */
-- 
2.43.0

[PATCH v2 2/4] drm/xe/sysctrl: Add system controller interrupt handler

[Raag Jadav]

Add system controller interrupt handler which is denoted by 11th bit in
GFX master interrupt register. While at it, add worker for scheduling
system controller work.

v2: Use system_percpu_wq instead of dedicated (Matthew Brost)

Co-developed-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_irq_regs.h |  1 +
 drivers/gpu/drm/xe/xe_irq.c           |  2 ++
 drivers/gpu/drm/xe/xe_sysctrl.c       | 39 ++++++++++++++++++++++-----
 drivers/gpu/drm/xe/xe_sysctrl.h       |  3 +++
 drivers/gpu/drm/xe/xe_sysctrl_types.h |  7 +++++
 5 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 9d74f454d3ff..1d6b976c4de0 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -22,6 +22,7 @@
 #define   DISPLAY_IRQ				REG_BIT(16)
 #define   SOC_H2DMEMINT_IRQ			REG_BIT(13)
 #define   I2C_IRQ				REG_BIT(12)
+#define   SYSCTRL_IRQ				REG_BIT(11)
 #define   GT_DW_IRQ(x)				REG_BIT(x)
 
 /*
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 7560a45f7f64..9e49e2241da4 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -24,6 +24,7 @@
 #include "xe_mmio.h"
 #include "xe_pxp.h"
 #include "xe_sriov.h"
+#include "xe_sysctrl.h"
 #include "xe_tile.h"
 
 /*
@@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
 				xe_heci_csc_irq_handler(xe, master_ctl);
 			xe_display_irq_handler(xe, master_ctl);
 			xe_i2c_irq_handler(xe, master_ctl);
+			xe_sysctrl_irq_handler(xe, master_ctl);
 			xe_mert_irq_handler(xe, master_ctl);
 			gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
 		}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 430bccbdc3b9..aba2166650aa 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -7,6 +7,7 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 
+#include "regs/xe_irq_regs.h"
 #include "regs/xe_sysctrl_regs.h"
 #include "xe_device.h"
 #include "xe_mmio.h"
@@ -28,10 +29,16 @@
  * with the System Controller through the mailbox.
  */
 
+static void xe_sysctrl_work(struct work_struct *work)
+{
+}
+
 static void xe_sysctrl_fini(void *arg)
 {
 	struct xe_device *xe = arg;
+	struct xe_sysctrl *sc = &xe->sc;
 
+	cancel_work_sync(&sc->work);
 	xe->soc_remapper.set_sysctrl_region(xe, 0);
 }
 
@@ -56,12 +63,6 @@ int xe_sysctrl_init(struct xe_device *xe)
 	if (!xe->soc_remapper.set_sysctrl_region)
 		return -ENODEV;
 
-	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
-
-	ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
-	if (ret)
-		return ret;
-
 	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
 	if (!sc->mmio)
 		return -ENOMEM;
@@ -74,7 +75,31 @@ int xe_sysctrl_init(struct xe_device *xe)
 	if (ret)
 		return ret;
 
+	ret = drmm_mutex_init(&xe->drm, &sc->work_lock);
+	if (ret)
+		return ret;
+
+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
 	xe_sysctrl_mailbox_init(sc);
+	INIT_WORK(&sc->work, xe_sysctrl_work);
 
-	return 0;
+	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
+}
+
+/**
+ * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
+ * @xe: xe device instance
+ * @master_ctl: interrupt register
+ *
+ * Handle interrupts generated by System Controller.
+ */
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
+{
+	struct xe_sysctrl *sc = &xe->sc;
+
+	if (!xe->info.has_sysctrl)
+		return;
+
+	if (master_ctl & SYSCTRL_IRQ)
+		schedule_work(&sc->work);
 }
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index ee7826fe4c98..5919310b9db9 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -6,8 +6,11 @@
 #ifndef _XE_SYSCTRL_H_
 #define _XE_SYSCTRL_H_
 
+#include <linux/types.h>
+
 struct xe_device;
 
 int xe_sysctrl_init(struct xe_device *xe);
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
 
 #endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
index d4a362564925..bfaa9ad085ce 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -8,6 +8,7 @@
 
 #include <linux/mutex.h>
 #include <linux/types.h>
+#include <linux/workqueue_types.h>
 
 struct xe_mmio;
 
@@ -28,6 +29,12 @@ struct xe_sysctrl {
 	 * messages to help distinguish message boundaries.
 	 */
 	bool phase_bit;
+
+	/** @work: Pending events work */
+	struct work_struct work;
+
+	/** @work_lock: Mutex protecting pending events */
+	struct mutex work_lock;
 };
 
 #endif /* _XE_SYSCTRL_TYPES_H_ */
-- 
2.43.0

Re: [PATCH v2 2/4] drm/xe/sysctrl: Add system controller interrupt handler

[Mallesh, Koujalagi]

Hi Raag,

On 13-02-2026 01:46 pm, Raag Jadav wrote:
> Add system controller interrupt handler which is denoted by 11th bit in
> GFX master interrupt register. While at it, add worker for scheduling
> system controller work.
>
> v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
>
> Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_irq_regs.h |  1 +
>   drivers/gpu/drm/xe/xe_irq.c           |  2 ++
>   drivers/gpu/drm/xe/xe_sysctrl.c       | 39 ++++++++++++++++++++++-----
>   drivers/gpu/drm/xe/xe_sysctrl.h       |  3 +++
>   drivers/gpu/drm/xe/xe_sysctrl_types.h |  7 +++++
>   5 files changed, 45 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 9d74f454d3ff..1d6b976c4de0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -22,6 +22,7 @@
>   #define   DISPLAY_IRQ				REG_BIT(16)
>   #define   SOC_H2DMEMINT_IRQ			REG_BIT(13)
>   #define   I2C_IRQ				REG_BIT(12)
> +#define   SYSCTRL_IRQ				REG_BIT(11)
>   #define   GT_DW_IRQ(x)				REG_BIT(x)
>   
>   /*
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 7560a45f7f64..9e49e2241da4 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -24,6 +24,7 @@
>   #include "xe_mmio.h"
>   #include "xe_pxp.h"
>   #include "xe_sriov.h"
> +#include "xe_sysctrl.h"
>   #include "xe_tile.h"
>   
>   /*
> @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>   				xe_heci_csc_irq_handler(xe, master_ctl);
>   			xe_display_irq_handler(xe, master_ctl);
>   			xe_i2c_irq_handler(xe, master_ctl);
> +			xe_sysctrl_irq_handler(xe, master_ctl);
>   			xe_mert_irq_handler(xe, master_ctl);
>   			gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
>   		}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 430bccbdc3b9..aba2166650aa 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -7,6 +7,7 @@
>   #include <linux/device.h>
>   #include <linux/mutex.h>
>   
> +#include "regs/xe_irq_regs.h"
>   #include "regs/xe_sysctrl_regs.h"
>   #include "xe_device.h"
>   #include "xe_mmio.h"
> @@ -28,10 +29,16 @@
>    * with the System Controller through the mailbox.
>    */
>   
> +static void xe_sysctrl_work(struct work_struct *work)
> +{
> +}
> +
>   static void xe_sysctrl_fini(void *arg)
>   {
>   	struct xe_device *xe = arg;
> +	struct xe_sysctrl *sc = &xe->sc;
>   
> +	cancel_work_sync(&sc->work);
>   	xe->soc_remapper.set_sysctrl_region(xe, 0);
>   }
>   
> @@ -56,12 +63,6 @@ int xe_sysctrl_init(struct xe_device *xe)
>   	if (!xe->soc_remapper.set_sysctrl_region)
>   		return -ENODEV;
>   
> -	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> -
> -	ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> -	if (ret)
> -		return ret;
> -
>   	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
>   	if (!sc->mmio)
>   		return -ENOMEM;
> @@ -74,7 +75,31 @@ int xe_sysctrl_init(struct xe_device *xe)
>   	if (ret)
>   		return ret;
>   
> +	ret = drmm_mutex_init(&xe->drm, &sc->work_lock);
> +	if (ret)
> +		return ret;
> +
> +	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>   	xe_sysctrl_mailbox_init(sc);
> +	INIT_WORK(&sc->work, xe_sysctrl_work);
>   
> -	return 0;
> +	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> +}
> +
> +/**
> + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
> + * @xe: xe device instance
> + * @master_ctl: interrupt register
> + *
> + * Handle interrupts generated by System Controller.
> + */
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> +{
> +	struct xe_sysctrl *sc = &xe->sc;
> +
> +	if (!xe->info.has_sysctrl)
> +		return;
> +
What will be happen when multiple interrupts arriving before the work 
execution?
> +	if (master_ctl & SYSCTRL_IRQ)
> +		schedule_work(&sc->work);

Please use system_percpu_wq instead of global system_wq in order to 
reduce contention and improve cache locality.

Thanks,

-/Mallesh

>   }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index ee7826fe4c98..5919310b9db9 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -6,8 +6,11 @@
>   #ifndef _XE_SYSCTRL_H_
>   #define _XE_SYSCTRL_H_
>   
> +#include <linux/types.h>
> +
>   struct xe_device;
>   
>   int xe_sysctrl_init(struct xe_device *xe);
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
>   
>   #endif /* _XE_SYSCTRL_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> index d4a362564925..bfaa9ad085ce 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> @@ -8,6 +8,7 @@
>   
>   #include <linux/mutex.h>
>   #include <linux/types.h>
> +#include <linux/workqueue_types.h>
>   
>   struct xe_mmio;
>   
> @@ -28,6 +29,12 @@ struct xe_sysctrl {
>   	 * messages to help distinguish message boundaries.
>   	 */
>   	bool phase_bit;
> +
> +	/** @work: Pending events work */
> +	struct work_struct work;
> +
> +	/** @work_lock: Mutex protecting pending events */
> +	struct mutex work_lock;
>   };
>   
>   #endif /* _XE_SYSCTRL_TYPES_H_ */

Re: [PATCH v2 2/4] drm/xe/sysctrl: Add system controller interrupt handler

[Raag Jadav]

On Wed, Feb 25, 2026 at 03:40:12PM +0530, Mallesh, Koujalagi wrote:
> On 13-02-2026 01:46 pm, Raag Jadav wrote:
> > Add system controller interrupt handler which is denoted by 11th bit in
> > GFX master interrupt register. While at it, add worker for scheduling
> > system controller work.
> > 
> > v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
> > 
> > Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> >   drivers/gpu/drm/xe/regs/xe_irq_regs.h |  1 +
> >   drivers/gpu/drm/xe/xe_irq.c           |  2 ++
> >   drivers/gpu/drm/xe/xe_sysctrl.c       | 39 ++++++++++++++++++++++-----
> >   drivers/gpu/drm/xe/xe_sysctrl.h       |  3 +++
> >   drivers/gpu/drm/xe/xe_sysctrl_types.h |  7 +++++
> >   5 files changed, 45 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > index 9d74f454d3ff..1d6b976c4de0 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > @@ -22,6 +22,7 @@
> >   #define   DISPLAY_IRQ				REG_BIT(16)
> >   #define   SOC_H2DMEMINT_IRQ			REG_BIT(13)
> >   #define   I2C_IRQ				REG_BIT(12)
> > +#define   SYSCTRL_IRQ				REG_BIT(11)
> >   #define   GT_DW_IRQ(x)				REG_BIT(x)
> >   /*
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 7560a45f7f64..9e49e2241da4 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -24,6 +24,7 @@
> >   #include "xe_mmio.h"
> >   #include "xe_pxp.h"
> >   #include "xe_sriov.h"
> > +#include "xe_sysctrl.h"
> >   #include "xe_tile.h"
> >   /*
> > @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> >   				xe_heci_csc_irq_handler(xe, master_ctl);
> >   			xe_display_irq_handler(xe, master_ctl);
> >   			xe_i2c_irq_handler(xe, master_ctl);
> > +			xe_sysctrl_irq_handler(xe, master_ctl);
> >   			xe_mert_irq_handler(xe, master_ctl);
> >   			gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> >   		}
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 430bccbdc3b9..aba2166650aa 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -7,6 +7,7 @@
> >   #include <linux/device.h>
> >   #include <linux/mutex.h>
> > +#include "regs/xe_irq_regs.h"
> >   #include "regs/xe_sysctrl_regs.h"
> >   #include "xe_device.h"
> >   #include "xe_mmio.h"
> > @@ -28,10 +29,16 @@
> >    * with the System Controller through the mailbox.
> >    */
> > +static void xe_sysctrl_work(struct work_struct *work)
> > +{
> > +}
> > +
> >   static void xe_sysctrl_fini(void *arg)
> >   {
> >   	struct xe_device *xe = arg;
> > +	struct xe_sysctrl *sc = &xe->sc;
> > +	cancel_work_sync(&sc->work);
> >   	xe->soc_remapper.set_sysctrl_region(xe, 0);
> >   }
> > @@ -56,12 +63,6 @@ int xe_sysctrl_init(struct xe_device *xe)
> >   	if (!xe->soc_remapper.set_sysctrl_region)
> >   		return -ENODEV;
> > -	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > -
> > -	ret = devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> > -	if (ret)
> > -		return ret;
> > -
> >   	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
> >   	if (!sc->mmio)
> >   		return -ENOMEM;
> > @@ -74,7 +75,31 @@ int xe_sysctrl_init(struct xe_device *xe)
> >   	if (ret)
> >   		return ret;
> > +	ret = drmm_mutex_init(&xe->drm, &sc->work_lock);
> > +	if (ret)
> > +		return ret;
> > +
> > +	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> >   	xe_sysctrl_mailbox_init(sc);
> > +	INIT_WORK(&sc->work, xe_sysctrl_work);
> > -	return 0;
> > +	return devm_add_action_or_reset(xe->drm.dev, xe_sysctrl_fini, xe);
> > +}
> > +
> > +/**
> > + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
> > + * @xe: xe device instance
> > + * @master_ctl: interrupt register
> > + *
> > + * Handle interrupts generated by System Controller.
> > + */
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> > +{
> > +	struct xe_sysctrl *sc = &xe->sc;
> > +
> > +	if (!xe->info.has_sysctrl)
> > +		return;
> > +
> What will be happen when multiple interrupts arriving before the work
> execution?

This is why we have work_lock in patch 3.

> > +	if (master_ctl & SYSCTRL_IRQ)
> > +		schedule_work(&sc->work);
> 
> Please use system_percpu_wq instead of global system_wq in order to reduce
> contention and improve cache locality.

We already do. Perhaps the documentation is what needs to be updated.

Raag

> >   }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index ee7826fe4c98..5919310b9db9 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -6,8 +6,11 @@
> >   #ifndef _XE_SYSCTRL_H_
> >   #define _XE_SYSCTRL_H_
> > +#include <linux/types.h>
> > +
> >   struct xe_device;
> >   int xe_sysctrl_init(struct xe_device *xe);
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> >   #endif /* _XE_SYSCTRL_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > index d4a362564925..bfaa9ad085ce 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > @@ -8,6 +8,7 @@
> >   #include <linux/mutex.h>
> >   #include <linux/types.h>
> > +#include <linux/workqueue_types.h>
> >   struct xe_mmio;
> > @@ -28,6 +29,12 @@ struct xe_sysctrl {
> >   	 * messages to help distinguish message boundaries.
> >   	 */
> >   	bool phase_bit;
> > +
> > +	/** @work: Pending events work */
> > +	struct work_struct work;
> > +
> > +	/** @work_lock: Mutex protecting pending events */
> > +	struct mutex work_lock;
> >   };
> >   #endif /* _XE_SYSCTRL_TYPES_H_ */

[PATCH v2 3/4] drm/xe/sysctrl: Add system controller event support

[Raag Jadav]

System controller reports different types of events to GFX endpoint for
different usecases, add initial support for them. This will be further
extended to service those usecases.

v2: Handle unexpected response length (Mallesh)

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
 drivers/gpu/drm/xe/Makefile                 |  1 +
 drivers/gpu/drm/xe/xe_sysctrl.c             |  5 ++
 drivers/gpu/drm/xe/xe_sysctrl.h             |  1 +
 drivers/gpu/drm/xe/xe_sysctrl_event.c       | 76 +++++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h     | 10 +++
 6 files changed, 142 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
 create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 8005293dc30f..59e083f90d7e 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -123,6 +123,7 @@ xe-y += xe_bb.o \
 	xe_survivability_mode.o \
 	xe_sync.o \
 	xe_sysctrl.o \
+	xe_sysctrl_event.o \
 	xe_sysctrl_mailbox.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index aba2166650aa..bbfb737efc88 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -31,6 +31,11 @@
 
 static void xe_sysctrl_work(struct work_struct *work)
 {
+	struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
+	struct xe_device *xe = container_of(sc, struct xe_device, sc);
+
+	guard(mutex)(&sc->work_lock);
+	xe_sysctrl_event(xe);
 }
 
 static void xe_sysctrl_fini(void *arg)
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index 5919310b9db9..bd9acf575d14 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -12,5 +12,6 @@ struct xe_device;
 
 int xe_sysctrl_init(struct xe_device *xe);
 void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
+void xe_sysctrl_event(struct xe_device *xe);
 
 #endif /* _XE_SYSCTRL_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
new file mode 100644
index 000000000000..7c3041f4196a
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_assert.h"
+#include "xe_device.h"
+#include "xe_irq.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+static void xe_sysctrl_get_pending_event(struct xe_device *xe,
+					 struct xe_sysctrl_mailbox_command *command)
+{
+	struct xe_sysctrl_event_response response;
+	size_t len;
+	int ret;
+
+	command->data_out = &response;
+	command->data_out_len = sizeof(response);
+
+	do {
+		memset(&response, 0, sizeof(response));
+
+		ret = xe_sysctrl_send_command(xe, command, &len);
+		if (ret) {
+			xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
+			return;
+		}
+
+		if (len != sizeof(response)) {
+			xe_err(xe, "sysctrl: unexpected response length %ld\n", len);
+			return;
+		}
+
+		if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
+			xe_warn(xe, "[RAS]: error counter threshold crossed\n");
+		} else {
+			xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
+			return;
+		}
+
+		xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
+	} while (response.count);
+}
+
+static void xe_sysctrl_event_request_prep(struct xe_device *xe,
+					  struct xe_sysctrl_mailbox_app_msg_hdr *header,
+					  struct xe_sysctrl_event_request *request)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+	header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
+		       REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
+
+	request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
+	request->fn = PCI_FUNC(pdev->devfn);
+}
+
+void xe_sysctrl_event(struct xe_device *xe)
+{
+	struct xe_sysctrl_mailbox_app_msg_hdr header = {};
+	struct xe_sysctrl_mailbox_command command = {};
+	struct xe_sysctrl_event_request request = {};
+
+	xe_sysctrl_event_request_prep(xe, &header, &request);
+
+	command.header = header;
+	command.data_in = &request;
+	command.data_in_len = sizeof(request);
+
+	xe_sysctrl_get_pending_event(xe, &command);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
new file mode 100644
index 000000000000..9c5fb95c58f7
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
+#define _XE_SYSCTRL_EVENT_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_SYSCTRL_EVENT_DATA_LEN		68
+
+enum xe_sysctrl_event {
+	XE_SYSCTRL_EVENT_THRESHOLD_CROSSED	= 0x01,
+};
+
+/**
+ * struct xe_sysctrl_event_request - Request structure for pending event
+ */
+struct xe_sysctrl_event_request {
+	/** @vector: MSI-X vector that was triggered */
+	u32 vector;
+	/** @fn: Function index (0-7) of PCIe device */
+	u8 fn;
+	/** @reserved: Reserved for future use */
+	u16 reserved;
+	/** @reserved2: Reserved for future use */
+	u32 reserved2[2];
+} __packed;
+
+/**
+ * struct xe_sysctrl_event_response - Response structure for pending event
+ */
+struct xe_sysctrl_event_response {
+	/** @count: Number of pending events */
+	u32 count;
+	/** @event: Pending event */
+	enum xe_sysctrl_event event;
+	/** @timestamp: Timestamp of most recent event */
+	u64 timestamp;
+	/** @extended: Event has extended payload */
+	u8 extended:1;
+	/** @reserved: Reserved for future use */
+	u32 reserved:23;
+	/** @data: Generic event data */
+	u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
+} __packed;
+
+#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
index 2b64165c8e76..f060be5124f2 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
 #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
 	FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
 
+/* Command groups */
+enum xe_sysctrl_group {
+	XE_SYSCTRL_GROUP_GFSP			= 0x01,
+};
+
+/* Commands supported by GFSP group */
+enum xe_sysctrl_gfsp_cmd {
+	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
+};
+
 void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
 int xe_sysctrl_send_command(struct xe_device *xe,
 			    struct xe_sysctrl_mailbox_command *cmd,
-- 
2.43.0

Re: [PATCH v2 3/4] drm/xe/sysctrl: Add system controller event support

[Mallesh, Koujalagi]

On 13-02-2026 01:46 pm, Raag Jadav wrote:
> System controller reports different types of events to GFX endpoint for
> different usecases, add initial support for them. This will be further
> extended to service those usecases.
>
> v2: Handle unexpected response length (Mallesh)
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
>   drivers/gpu/drm/xe/Makefile                 |  1 +
>   drivers/gpu/drm/xe/xe_sysctrl.c             |  5 ++
>   drivers/gpu/drm/xe/xe_sysctrl.h             |  1 +
>   drivers/gpu/drm/xe/xe_sysctrl_event.c       | 76 +++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl_mailbox.h     | 10 +++
>   6 files changed, 142 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
>   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 8005293dc30f..59e083f90d7e 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -123,6 +123,7 @@ xe-y += xe_bb.o \
>   	xe_survivability_mode.o \
>   	xe_sync.o \
>   	xe_sysctrl.o \
> +	xe_sysctrl_event.o \
>   	xe_sysctrl_mailbox.o \
>   	xe_tile.o \
>   	xe_tile_sysfs.o \
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index aba2166650aa..bbfb737efc88 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -31,6 +31,11 @@
>   
>   static void xe_sysctrl_work(struct work_struct *work)
>   {
> +	struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> +	struct xe_device *xe = container_of(sc, struct xe_device, sc);
> +
> +	guard(mutex)(&sc->work_lock);
> +	xe_sysctrl_event(xe);
>   }
>   
>   static void xe_sysctrl_fini(void *arg)
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index 5919310b9db9..bd9acf575d14 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -12,5 +12,6 @@ struct xe_device;
>   
>   int xe_sysctrl_init(struct xe_device *xe);
>   void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> +void xe_sysctrl_event(struct xe_device *xe);
>   
>   #endif /* _XE_SYSCTRL_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> new file mode 100644
> index 000000000000..7c3041f4196a
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -0,0 +1,76 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_assert.h"
> +#include "xe_device.h"
> +#include "xe_irq.h"
> +#include "xe_printk.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_mailbox_types.h"
> +
> +static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> +					 struct xe_sysctrl_mailbox_command *command)
> +{
> +	struct xe_sysctrl_event_response response;
> +	size_t len;
> +	int ret;
> +
> +	command->data_out = &response;
> +	command->data_out_len = sizeof(response);
> +
> +	do {
> +		memset(&response, 0, sizeof(response));
> +
> +		ret = xe_sysctrl_send_command(xe, command, &len);
> +		if (ret) {
> +			xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> +			return;
> +		}
> +
> +		if (len != sizeof(response)) {
> +			xe_err(xe, "sysctrl: unexpected response length %ld\n", len);
> +			return;
> +		}
> +
> +		if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> +			xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> +		} else {
> +			xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
What about remaining events in response.count?
> +			return;
> +		}
> +
> +		xe_dbg(xe, "sysctrl: %u events pending\n", response.count);

What happen when sysctrl continuously reports pending events, this could 
loop forever by monopolizing the work queue thread?

Thanks

-/Mallesh

> +	} while (response.count);
> +}
> +
> +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> +					  struct xe_sysctrl_mailbox_app_msg_hdr *header,
> +					  struct xe_sysctrl_event_request *request)
> +{
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> +	header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> +		       REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> +
> +	request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> +	request->fn = PCI_FUNC(pdev->devfn);
> +}
> +
> +void xe_sysctrl_event(struct xe_device *xe)
> +{
> +	struct xe_sysctrl_mailbox_app_msg_hdr header = {};
> +	struct xe_sysctrl_mailbox_command command = {};
> +	struct xe_sysctrl_event_request request = {};
> +
> +	xe_sysctrl_event_request_prep(xe, &header, &request);
> +
> +	command.header = header;
> +	command.data_in = &request;
> +	command.data_in_len = sizeof(request);
> +
> +	xe_sysctrl_get_pending_event(xe, &command);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> new file mode 100644
> index 000000000000..9c5fb95c58f7
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> +#define _XE_SYSCTRL_EVENT_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_SYSCTRL_EVENT_DATA_LEN		68
> +
> +enum xe_sysctrl_event {
> +	XE_SYSCTRL_EVENT_THRESHOLD_CROSSED	= 0x01,
> +};
> +
> +/**
> + * struct xe_sysctrl_event_request - Request structure for pending event
> + */
> +struct xe_sysctrl_event_request {
> +	/** @vector: MSI-X vector that was triggered */
> +	u32 vector;
> +	/** @fn: Function index (0-7) of PCIe device */
> +	u8 fn;
> +	/** @reserved: Reserved for future use */
> +	u16 reserved;
> +	/** @reserved2: Reserved for future use */
> +	u32 reserved2[2];
> +} __packed;
> +
> +/**
> + * struct xe_sysctrl_event_response - Response structure for pending event
> + */
> +struct xe_sysctrl_event_response {
> +	/** @count: Number of pending events */
> +	u32 count;
> +	/** @event: Pending event */
> +	enum xe_sysctrl_event event;
> +	/** @timestamp: Timestamp of most recent event */
> +	u64 timestamp;
> +	/** @extended: Event has extended payload */
> +	u8 extended:1;
> +	/** @reserved: Reserved for future use */
> +	u32 reserved:23;
> +	/** @data: Generic event data */
> +	u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> +} __packed;
> +
> +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> index 2b64165c8e76..f060be5124f2 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> @@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
>   #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
>   	FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>   
> +/* Command groups */
> +enum xe_sysctrl_group {
> +	XE_SYSCTRL_GROUP_GFSP			= 0x01,
> +};
> +
> +/* Commands supported by GFSP group */
> +enum xe_sysctrl_gfsp_cmd {
> +	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
> +};
> +
>   void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
>   int xe_sysctrl_send_command(struct xe_device *xe,
>   			    struct xe_sysctrl_mailbox_command *cmd,

Re: [PATCH v2 3/4] drm/xe/sysctrl: Add system controller event support

[Raag Jadav]

On Tue, Mar 10, 2026 at 11:51:56AM +0530, Mallesh, Koujalagi wrote:
> On 13-02-2026 01:46 pm, Raag Jadav wrote:
> > System controller reports different types of events to GFX endpoint for
> > different usecases, add initial support for them. This will be further
> > extended to service those usecases.
> > 
> > v2: Handle unexpected response length (Mallesh)
> > 
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> >   drivers/gpu/drm/xe/Makefile                 |  1 +
> >   drivers/gpu/drm/xe/xe_sysctrl.c             |  5 ++
> >   drivers/gpu/drm/xe/xe_sysctrl.h             |  1 +
> >   drivers/gpu/drm/xe/xe_sysctrl_event.c       | 76 +++++++++++++++++++++
> >   drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 49 +++++++++++++
> >   drivers/gpu/drm/xe/xe_sysctrl_mailbox.h     | 10 +++
> >   6 files changed, 142 insertions(+)
> >   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> >   create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > 
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 8005293dc30f..59e083f90d7e 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -123,6 +123,7 @@ xe-y += xe_bb.o \
> >   	xe_survivability_mode.o \
> >   	xe_sync.o \
> >   	xe_sysctrl.o \
> > +	xe_sysctrl_event.o \
> >   	xe_sysctrl_mailbox.o \
> >   	xe_tile.o \
> >   	xe_tile_sysfs.o \
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index aba2166650aa..bbfb737efc88 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -31,6 +31,11 @@
> >   static void xe_sysctrl_work(struct work_struct *work)
> >   {
> > +	struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> > +	struct xe_device *xe = container_of(sc, struct xe_device, sc);
> > +
> > +	guard(mutex)(&sc->work_lock);
> > +	xe_sysctrl_event(xe);
> >   }
> >   static void xe_sysctrl_fini(void *arg)
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index 5919310b9db9..bd9acf575d14 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -12,5 +12,6 @@ struct xe_device;
> >   int xe_sysctrl_init(struct xe_device *xe);
> >   void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > +void xe_sysctrl_event(struct xe_device *xe);
> >   #endif /* _XE_SYSCTRL_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > new file mode 100644
> > index 000000000000..7c3041f4196a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -0,0 +1,76 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_assert.h"
> > +#include "xe_device.h"
> > +#include "xe_irq.h"
> > +#include "xe_printk.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +#include "xe_sysctrl_mailbox.h"
> > +#include "xe_sysctrl_mailbox_types.h"
> > +
> > +static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> > +					 struct xe_sysctrl_mailbox_command *command)
> > +{
> > +	struct xe_sysctrl_event_response response;
> > +	size_t len;
> > +	int ret;
> > +
> > +	command->data_out = &response;
> > +	command->data_out_len = sizeof(response);
> > +
> > +	do {
> > +		memset(&response, 0, sizeof(response));
> > +
> > +		ret = xe_sysctrl_send_command(xe, command, &len);
> > +		if (ret) {
> > +			xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> > +			return;
> > +		}
> > +
> > +		if (len != sizeof(response)) {
> > +			xe_err(xe, "sysctrl: unexpected response length %ld\n", len);
> > +			return;
> > +		}
> > +
> > +		if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > +			xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > +		} else {
> > +			xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> What about remaining events in response.count?

We tream them as firmware bugs, similar to above cases.

> > +			return;
> > +		}
> > +
> > +		xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
> 
> What happen when sysctrl continuously reports pending events, this could
> loop forever by monopolizing the work queue thread?

I already have it locally but thanks for pointing it out.

Raag

> > +	} while (response.count);
> > +}
> > +
> > +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> > +					  struct xe_sysctrl_mailbox_app_msg_hdr *header,
> > +					  struct xe_sysctrl_event_request *request)
> > +{
> > +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> > +
> > +	header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> > +		       REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> > +
> > +	request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> > +	request->fn = PCI_FUNC(pdev->devfn);
> > +}
> > +
> > +void xe_sysctrl_event(struct xe_device *xe)
> > +{
> > +	struct xe_sysctrl_mailbox_app_msg_hdr header = {};
> > +	struct xe_sysctrl_mailbox_command command = {};
> > +	struct xe_sysctrl_event_request request = {};
> > +
> > +	xe_sysctrl_event_request_prep(xe, &header, &request);
> > +
> > +	command.header = header;
> > +	command.data_in = &request;
> > +	command.data_in_len = sizeof(request);
> > +
> > +	xe_sysctrl_get_pending_event(xe, &command);
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > new file mode 100644
> > index 000000000000..9c5fb95c58f7
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> > @@ -0,0 +1,49 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> > +#define _XE_SYSCTRL_EVENT_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_SYSCTRL_EVENT_DATA_LEN		68
> > +
> > +enum xe_sysctrl_event {
> > +	XE_SYSCTRL_EVENT_THRESHOLD_CROSSED	= 0x01,
> > +};
> > +
> > +/**
> > + * struct xe_sysctrl_event_request - Request structure for pending event
> > + */
> > +struct xe_sysctrl_event_request {
> > +	/** @vector: MSI-X vector that was triggered */
> > +	u32 vector;
> > +	/** @fn: Function index (0-7) of PCIe device */
> > +	u8 fn;
> > +	/** @reserved: Reserved for future use */
> > +	u16 reserved;
> > +	/** @reserved2: Reserved for future use */
> > +	u32 reserved2[2];
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sysctrl_event_response - Response structure for pending event
> > + */
> > +struct xe_sysctrl_event_response {
> > +	/** @count: Number of pending events */
> > +	u32 count;
> > +	/** @event: Pending event */
> > +	enum xe_sysctrl_event event;
> > +	/** @timestamp: Timestamp of most recent event */
> > +	u64 timestamp;
> > +	/** @extended: Event has extended payload */
> > +	u8 extended:1;
> > +	/** @reserved: Reserved for future use */
> > +	u32 reserved:23;
> > +	/** @data: Generic event data */
> > +	u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> > +} __packed;
> > +
> > +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > index 2b64165c8e76..f060be5124f2 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> > @@ -27,6 +27,16 @@ struct xe_sysctrl_mailbox_command;
> >   #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> >   	FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
> > +/* Command groups */
> > +enum xe_sysctrl_group {
> > +	XE_SYSCTRL_GROUP_GFSP			= 0x01,
> > +};
> > +
> > +/* Commands supported by GFSP group */
> > +enum xe_sysctrl_gfsp_cmd {
> > +	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
> > +};
> > +
> >   void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> >   int xe_sysctrl_send_command(struct xe_device *xe,
> >   			    struct xe_sysctrl_mailbox_command *cmd,

[PATCH v2 4/4] drm/xe/ras: Introduce correctable error handling

[Raag Jadav]

Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.

Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
 drivers/gpu/drm/xe/Makefile           |  1 +
 drivers/gpu/drm/xe/xe_ras.c           | 87 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_ras.h           | 14 +++++
 drivers/gpu/drm/xe/xe_ras_types.h     | 79 ++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_sysctrl_event.c |  3 +-
 5 files changed, 183 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/xe/xe_ras.c
 create mode 100644 drivers/gpu/drm/xe/xe_ras.h
 create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 59e083f90d7e..7fc67c320086 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -111,6 +111,7 @@ xe-y += xe_bb.o \
 	xe_pxp_submit.o \
 	xe_query.o \
 	xe_range_fence.o \
+	xe_ras.o \
 	xe_reg_sr.o \
 	xe_reg_whitelist.o \
 	xe_ring_ops.o \
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
new file mode 100644
index 000000000000..413c6e62cd50
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_assert.h"
+#include "xe_printk.h"
+#include "xe_ras.h"
+#include "xe_ras_types.h"
+#include "xe_sysctrl_event_types.h"
+
+/* Severity of detected errors  */
+enum xe_ras_severity {
+	XE_RAS_SEV_NOT_SUPPORTED		= 0x00,
+	XE_RAS_SEV_CORRECTABLE			= 0x01,
+	XE_RAS_SEV_UNCORRECTABLE		= 0x02,
+	XE_RAS_SEV_INFORMATIONAL		= 0x03,
+	XE_RAS_SEV_MAX
+};
+
+/* Major IP blocks/components where errors can originate */
+enum xe_ras_component {
+	XE_RAS_COMP_NOT_SUPPORTED		= 0x00,
+	XE_RAS_COMP_DEVICE_MEMORY		= 0x01,
+	XE_RAS_COMP_CORE_COMPUTE		= 0x02,
+	XE_RAS_COMP_RESERVED			= 0x03,
+	XE_RAS_COMP_PCIE			= 0x04,
+	XE_RAS_COMP_FABRIC			= 0x05,
+	XE_RAS_COMP_SOC_INTERNAL		= 0x06,
+	XE_RAS_COMP_MAX
+};
+
+static const char *const xe_ras_severities[] = {
+	[XE_RAS_SEV_NOT_SUPPORTED]		= "Not Supported",
+	[XE_RAS_SEV_CORRECTABLE]		= "Correctable",
+	[XE_RAS_SEV_UNCORRECTABLE]		= "Uncorrectable",
+	[XE_RAS_SEV_INFORMATIONAL]		= "Informational",
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
+
+static const char *const xe_ras_components[] = {
+	[XE_RAS_COMP_NOT_SUPPORTED]		= "Not Supported",
+	[XE_RAS_COMP_DEVICE_MEMORY]		= "Device Memory",
+	[XE_RAS_COMP_CORE_COMPUTE]		= "Core Compute",
+	[XE_RAS_COMP_RESERVED]			= "Reserved",
+	[XE_RAS_COMP_PCIE]			= "PCIe",
+	[XE_RAS_COMP_FABRIC]			= "Fabric",
+	[XE_RAS_COMP_SOC_INTERNAL]		= "SoC Internal",
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
+
+static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
+{
+	xe_assert(xe, sev < XE_RAS_SEV_MAX);
+
+	return xe_ras_severities[sev];
+}
+
+static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
+{
+	xe_assert(xe, comp < XE_RAS_COMP_MAX);
+
+	return xe_ras_components[comp];
+}
+
+void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response)
+{
+	struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
+	struct xe_ras_error *errors = pending->counters;
+	u32 cid, sev, comp, inst, cause;
+	u8 tile;
+
+	xe_warn(xe, "[RAS]: error counter threshold crossed\n");
+	xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
+
+	for (cid = 0; cid < pending->ncounters; cid++) {
+		sev = errors[cid].common.severity;
+		comp = errors[cid].common.component;
+
+		tile = errors[cid].product.unit.tile;
+		inst = errors[cid].product.unit.instance;
+		cause = errors[cid].product.cause.cause;
+
+		xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n",
+			sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause);
+	}
+}
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
new file mode 100644
index 000000000000..fdefe0e2fe98
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_H_
+#define _XE_RAS_H_
+
+struct xe_device;
+struct xe_sysctrl_event_response;
+
+void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
new file mode 100644
index 000000000000..0afcf8bf982d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_TYPES_H_
+#define _XE_RAS_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_RAS_NUM_COUNTERS			21
+
+/**
+ * struct xe_ras_error_common - Error fields that are common across all products
+ */
+struct xe_ras_error_common {
+	/** @severity: Error severity */
+	u8 severity;
+	/** @component: IP block where error originated */
+	u8 component;
+} __packed;
+
+/**
+ * struct xe_ras_error_unit - Error unit information
+ */
+struct xe_ras_error_unit {
+	/** @tile: Tile identifier */
+	u8 tile;
+	/** @instance: Instance identifier specific to IP */
+	u32 instance;
+} __packed;
+
+/**
+ * struct xe_ras_error_cause - Error cause information
+ */
+struct xe_ras_error_cause {
+	/** @cause: Cause/checker */
+	u32 cause;
+	/** @reserved: For future use */
+	u8 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_error_product - Error fields that are specific to the product
+ */
+struct xe_ras_error_product {
+	/** @unit: Unit within IP block */
+	struct xe_ras_error_unit unit;
+	/** @cause: Cause/checker */
+	struct xe_ras_error_cause cause;
+} __packed;
+
+/**
+ * struct xe_ras_error - Combines common and product-specific parts
+ */
+struct xe_ras_error {
+	/** @common: Common error type and component */
+	struct xe_ras_error_common common;
+	/** @product: Product-specific unit and cause */
+	struct xe_ras_error_product product;
+} __packed;
+
+/**
+ * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event
+ */
+struct xe_ras_event_threshold_crossed {
+	/** @ncounters: Number of counters that crossed thresholds */
+	u32 ncounters;
+	/** @ts_high: Higher 32 bits of event timestamp */
+	u32 ts_high;
+	/** @ts_low: Lower 32 bits of event timestamp */
+	u32 ts_low;
+	/** @reason: Threshold cross reason */
+	u32 reason;
+	/** @counters: Array of error counters that crossed threshold */
+	struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
index 7c3041f4196a..876754f9fe35 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -7,6 +7,7 @@
 #include "xe_device.h"
 #include "xe_irq.h"
 #include "xe_printk.h"
+#include "xe_ras.h"
 #include "xe_sysctrl.h"
 #include "xe_sysctrl_event_types.h"
 #include "xe_sysctrl_mailbox.h"
@@ -37,7 +38,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe,
 		}
 
 		if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
-			xe_warn(xe, "[RAS]: error counter threshold crossed\n");
+			xe_ras_event_log(xe, &response);
 		} else {
 			xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
 			return;
-- 
2.43.0

Re: [PATCH v2 4/4] drm/xe/ras: Introduce correctable error handling

[Mallesh, Koujalagi]

On 13-02-2026 01:46 pm, Raag Jadav wrote:
> Add initial support for correctable error handling which is serviced
> using system controller event. Currently we only log the errors in
> dmesg but this serves as a foundation for RAS infrastructure and will
> be further extended to facilitate other RAS features.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
>   drivers/gpu/drm/xe/Makefile           |  1 +
>   drivers/gpu/drm/xe/xe_ras.c           | 87 +++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_ras.h           | 14 +++++
>   drivers/gpu/drm/xe/xe_ras_types.h     | 79 ++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_sysctrl_event.c |  3 +-
>   5 files changed, 183 insertions(+), 1 deletion(-)
>   create mode 100644 drivers/gpu/drm/xe/xe_ras.c
>   create mode 100644 drivers/gpu/drm/xe/xe_ras.h
>   create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 59e083f90d7e..7fc67c320086 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -111,6 +111,7 @@ xe-y += xe_bb.o \
>   	xe_pxp_submit.o \
>   	xe_query.o \
>   	xe_range_fence.o \
> +	xe_ras.o \
>   	xe_reg_sr.o \
>   	xe_reg_whitelist.o \
>   	xe_ring_ops.o \
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> new file mode 100644
> index 000000000000..413c6e62cd50
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -0,0 +1,87 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_assert.h"
> +#include "xe_printk.h"
> +#include "xe_ras.h"
> +#include "xe_ras_types.h"
> +#include "xe_sysctrl_event_types.h"
> +
> +/* Severity of detected errors  */
> +enum xe_ras_severity {
> +	XE_RAS_SEV_NOT_SUPPORTED		= 0x00,
> +	XE_RAS_SEV_CORRECTABLE			= 0x01,
> +	XE_RAS_SEV_UNCORRECTABLE		= 0x02,
> +	XE_RAS_SEV_INFORMATIONAL		= 0x03,
> +	XE_RAS_SEV_MAX
> +};
> +
> +/* Major IP blocks/components where errors can originate */
> +enum xe_ras_component {
> +	XE_RAS_COMP_NOT_SUPPORTED		= 0x00,
> +	XE_RAS_COMP_DEVICE_MEMORY		= 0x01,
> +	XE_RAS_COMP_CORE_COMPUTE		= 0x02,
> +	XE_RAS_COMP_RESERVED			= 0x03,
> +	XE_RAS_COMP_PCIE			= 0x04,
> +	XE_RAS_COMP_FABRIC			= 0x05,
> +	XE_RAS_COMP_SOC_INTERNAL		= 0x06,
> +	XE_RAS_COMP_MAX
> +};
> +
> +static const char *const xe_ras_severities[] = {
> +	[XE_RAS_SEV_NOT_SUPPORTED]		= "Not Supported",
> +	[XE_RAS_SEV_CORRECTABLE]		= "Correctable",
> +	[XE_RAS_SEV_UNCORRECTABLE]		= "Uncorrectable",
> +	[XE_RAS_SEV_INFORMATIONAL]		= "Informational",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> +
> +static const char *const xe_ras_components[] = {
> +	[XE_RAS_COMP_NOT_SUPPORTED]		= "Not Supported",
> +	[XE_RAS_COMP_DEVICE_MEMORY]		= "Device Memory",
> +	[XE_RAS_COMP_CORE_COMPUTE]		= "Core Compute",
> +	[XE_RAS_COMP_RESERVED]			= "Reserved",
> +	[XE_RAS_COMP_PCIE]			= "PCIe",
> +	[XE_RAS_COMP_FABRIC]			= "Fabric",
> +	[XE_RAS_COMP_SOC_INTERNAL]		= "SoC Internal",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> +
> +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> +{
> +	xe_assert(xe, sev < XE_RAS_SEV_MAX);
> +
> +	return xe_ras_severities[sev];
> +}
> +
> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> +{
> +	xe_assert(xe, comp < XE_RAS_COMP_MAX);
> +
> +	return xe_ras_components[comp];
> +}
> +
> +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response)
> +{
> +	struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> +	struct xe_ras_error *errors = pending->counters;
> +	u32 cid, sev, comp, inst, cause;
> +	u8 tile;
> +
> +	xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> +	xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> +
> +	for (cid = 0; cid < pending->ncounters; cid++) {
> +		sev = errors[cid].common.severity;
> +		comp = errors[cid].common.component;
> +
> +		tile = errors[cid].product.unit.tile;
> +		inst = errors[cid].product.unit.instance;
> +		cause = errors[cid].product.cause.cause;
> +
Unaligned access of member cause penalty, we need to check.
> +		xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n",
> +			sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause);

Spam kernel Log, we can use rate limit right?

Thanks

-/Mallesh

> +	}
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> new file mode 100644
> index 000000000000..fdefe0e2fe98
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_H_
> +#define _XE_RAS_H_
> +
> +struct xe_device;
> +struct xe_sysctrl_event_response;
> +
> +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> new file mode 100644
> index 000000000000..0afcf8bf982d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -0,0 +1,79 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_TYPES_H_
> +#define _XE_RAS_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_RAS_NUM_COUNTERS			21
> +
> +/**
> + * struct xe_ras_error_common - Error fields that are common across all products
> + */
> +struct xe_ras_error_common {
> +	/** @severity: Error severity */
> +	u8 severity;
> +	/** @component: IP block where error originated */
> +	u8 component;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_unit - Error unit information
> + */
> +struct xe_ras_error_unit {
> +	/** @tile: Tile identifier */
> +	u8 tile;
> +	/** @instance: Instance identifier specific to IP */
> +	u32 instance;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_cause - Error cause information
> + */
> +struct xe_ras_error_cause {
> +	/** @cause: Cause/checker */
> +	u32 cause;
> +	/** @reserved: For future use */
> +	u8 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_product - Error fields that are specific to the product
> + */
> +struct xe_ras_error_product {
> +	/** @unit: Unit within IP block */
> +	struct xe_ras_error_unit unit;
> +	/** @cause: Cause/checker */
> +	struct xe_ras_error_cause cause;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error - Combines common and product-specific parts
> + */
> +struct xe_ras_error {
> +	/** @common: Common error type and component */
> +	struct xe_ras_error_common common;
> +	/** @product: Product-specific unit and cause */
> +	struct xe_ras_error_product product;
> +} __packed;
> +
> +/**
> + * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event
> + */
> +struct xe_ras_event_threshold_crossed {
> +	/** @ncounters: Number of counters that crossed thresholds */
> +	u32 ncounters;
> +	/** @ts_high: Higher 32 bits of event timestamp */
> +	u32 ts_high;
> +	/** @ts_low: Lower 32 bits of event timestamp */
> +	u32 ts_low;
> +	/** @reason: Threshold cross reason */
> +	u32 reason;
> +	/** @counters: Array of error counters that crossed threshold */
> +	struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> +} __packed;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> index 7c3041f4196a..876754f9fe35 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -7,6 +7,7 @@
>   #include "xe_device.h"
>   #include "xe_irq.h"
>   #include "xe_printk.h"
> +#include "xe_ras.h"
>   #include "xe_sysctrl.h"
>   #include "xe_sysctrl_event_types.h"
>   #include "xe_sysctrl_mailbox.h"
> @@ -37,7 +38,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe,
>   		}
>   
>   		if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> -			xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> +			xe_ras_event_log(xe, &response);
>   		} else {
>   			xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
>   			return;

Re: [PATCH v2 4/4] drm/xe/ras: Introduce correctable error handling

[Raag Jadav]

On Tue, Mar 10, 2026 at 03:48:35PM +0530, Mallesh, Koujalagi wrote:
> On 13-02-2026 01:46 pm, Raag Jadav wrote:
> > Add initial support for correctable error handling which is serviced
> > using system controller event. Currently we only log the errors in
> > dmesg but this serves as a foundation for RAS infrastructure and will
> > be further extended to facilitate other RAS features.
> > 
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> >   drivers/gpu/drm/xe/Makefile           |  1 +
> >   drivers/gpu/drm/xe/xe_ras.c           | 87 +++++++++++++++++++++++++++
> >   drivers/gpu/drm/xe/xe_ras.h           | 14 +++++
> >   drivers/gpu/drm/xe/xe_ras_types.h     | 79 ++++++++++++++++++++++++
> >   drivers/gpu/drm/xe/xe_sysctrl_event.c |  3 +-
> >   5 files changed, 183 insertions(+), 1 deletion(-)
> >   create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> >   create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> >   create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
> > 
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 59e083f90d7e..7fc67c320086 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -111,6 +111,7 @@ xe-y += xe_bb.o \
> >   	xe_pxp_submit.o \
> >   	xe_query.o \
> >   	xe_range_fence.o \
> > +	xe_ras.o \
> >   	xe_reg_sr.o \
> >   	xe_reg_whitelist.o \
> >   	xe_ring_ops.o \
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > new file mode 100644
> > index 000000000000..413c6e62cd50
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > @@ -0,0 +1,87 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_assert.h"
> > +#include "xe_printk.h"
> > +#include "xe_ras.h"
> > +#include "xe_ras_types.h"
> > +#include "xe_sysctrl_event_types.h"
> > +
> > +/* Severity of detected errors  */
> > +enum xe_ras_severity {
> > +	XE_RAS_SEV_NOT_SUPPORTED		= 0x00,
> > +	XE_RAS_SEV_CORRECTABLE			= 0x01,
> > +	XE_RAS_SEV_UNCORRECTABLE		= 0x02,
> > +	XE_RAS_SEV_INFORMATIONAL		= 0x03,
> > +	XE_RAS_SEV_MAX
> > +};
> > +
> > +/* Major IP blocks/components where errors can originate */
> > +enum xe_ras_component {
> > +	XE_RAS_COMP_NOT_SUPPORTED		= 0x00,
> > +	XE_RAS_COMP_DEVICE_MEMORY		= 0x01,
> > +	XE_RAS_COMP_CORE_COMPUTE		= 0x02,
> > +	XE_RAS_COMP_RESERVED			= 0x03,
> > +	XE_RAS_COMP_PCIE			= 0x04,
> > +	XE_RAS_COMP_FABRIC			= 0x05,
> > +	XE_RAS_COMP_SOC_INTERNAL		= 0x06,
> > +	XE_RAS_COMP_MAX
> > +};
> > +
> > +static const char *const xe_ras_severities[] = {
> > +	[XE_RAS_SEV_NOT_SUPPORTED]		= "Not Supported",
> > +	[XE_RAS_SEV_CORRECTABLE]		= "Correctable",
> > +	[XE_RAS_SEV_UNCORRECTABLE]		= "Uncorrectable",
> > +	[XE_RAS_SEV_INFORMATIONAL]		= "Informational",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> > +
> > +static const char *const xe_ras_components[] = {
> > +	[XE_RAS_COMP_NOT_SUPPORTED]		= "Not Supported",
> > +	[XE_RAS_COMP_DEVICE_MEMORY]		= "Device Memory",
> > +	[XE_RAS_COMP_CORE_COMPUTE]		= "Core Compute",
> > +	[XE_RAS_COMP_RESERVED]			= "Reserved",
> > +	[XE_RAS_COMP_PCIE]			= "PCIe",
> > +	[XE_RAS_COMP_FABRIC]			= "Fabric",
> > +	[XE_RAS_COMP_SOC_INTERNAL]		= "SoC Internal",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> > +
> > +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> > +{
> > +	xe_assert(xe, sev < XE_RAS_SEV_MAX);
> > +
> > +	return xe_ras_severities[sev];
> > +}
> > +
> > +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> > +{
> > +	xe_assert(xe, comp < XE_RAS_COMP_MAX);
> > +
> > +	return xe_ras_components[comp];
> > +}
> > +
> > +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response)
> > +{
> > +	struct xe_ras_event_threshold_crossed *pending = (void *)&response->data;
> > +	struct xe_ras_error *errors = pending->counters;
> > +	u32 cid, sev, comp, inst, cause;
> > +	u8 tile;
> > +
> > +	xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > +	xe_assert(xe, pending->ncounters < XE_RAS_NUM_COUNTERS);
> > +
> > +	for (cid = 0; cid < pending->ncounters; cid++) {
> > +		sev = errors[cid].common.severity;
> > +		comp = errors[cid].common.component;
> > +
> > +		tile = errors[cid].product.unit.tile;
> > +		inst = errors[cid].product.unit.instance;
> > +		cause = errors[cid].product.cause.cause;
> > +
> Unaligned access of member cause penalty, we need to check.

I'm okay with aligning but not sure if the firmware will accept it.
Let's check with arch.

> > +		xe_warn(xe, "[RAS]: Error:%s Tile:%u Component:%s Instance:%u Cause:%#x\n",
> > +			sev_to_str(xe, sev), tile, comp_to_str(xe, comp), inst, cause);
> 
> Spam kernel Log, we can use rate limit right?

Yep.

Raag

> > +	}
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> > new file mode 100644
> > index 000000000000..fdefe0e2fe98
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_H_
> > +#define _XE_RAS_H_
> > +
> > +struct xe_device;
> > +struct xe_sysctrl_event_response;
> > +
> > +void xe_ras_event_log(struct xe_device *xe, struct xe_sysctrl_event_response *response);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> > new file mode 100644
> > index 000000000000..0afcf8bf982d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> > @@ -0,0 +1,79 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_TYPES_H_
> > +#define _XE_RAS_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_RAS_NUM_COUNTERS			21
> > +
> > +/**
> > + * struct xe_ras_error_common - Error fields that are common across all products
> > + */
> > +struct xe_ras_error_common {
> > +	/** @severity: Error severity */
> > +	u8 severity;
> > +	/** @component: IP block where error originated */
> > +	u8 component;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_unit - Error unit information
> > + */
> > +struct xe_ras_error_unit {
> > +	/** @tile: Tile identifier */
> > +	u8 tile;
> > +	/** @instance: Instance identifier specific to IP */
> > +	u32 instance;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_cause - Error cause information
> > + */
> > +struct xe_ras_error_cause {
> > +	/** @cause: Cause/checker */
> > +	u32 cause;
> > +	/** @reserved: For future use */
> > +	u8 reserved;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_product - Error fields that are specific to the product
> > + */
> > +struct xe_ras_error_product {
> > +	/** @unit: Unit within IP block */
> > +	struct xe_ras_error_unit unit;
> > +	/** @cause: Cause/checker */
> > +	struct xe_ras_error_cause cause;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error - Combines common and product-specific parts
> > + */
> > +struct xe_ras_error {
> > +	/** @common: Common error type and component */
> > +	struct xe_ras_error_common common;
> > +	/** @product: Product-specific unit and cause */
> > +	struct xe_ras_error_product product;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_event_threshold_crossed - Event data for counter threshold crossed event
> > + */
> > +struct xe_ras_event_threshold_crossed {
> > +	/** @ncounters: Number of counters that crossed thresholds */
> > +	u32 ncounters;
> > +	/** @ts_high: Higher 32 bits of event timestamp */
> > +	u32 ts_high;
> > +	/** @ts_low: Lower 32 bits of event timestamp */
> > +	u32 ts_low;
> > +	/** @reason: Threshold cross reason */
> > +	u32 reason;
> > +	/** @counters: Array of error counters that crossed threshold */
> > +	struct xe_ras_error counters[XE_RAS_NUM_COUNTERS];
> > +} __packed;
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > index 7c3041f4196a..876754f9fe35 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -7,6 +7,7 @@
> >   #include "xe_device.h"
> >   #include "xe_irq.h"
> >   #include "xe_printk.h"
> > +#include "xe_ras.h"
> >   #include "xe_sysctrl.h"
> >   #include "xe_sysctrl_event_types.h"
> >   #include "xe_sysctrl_mailbox.h"
> > @@ -37,7 +38,7 @@ static void xe_sysctrl_get_pending_event(struct xe_device *xe,
> >   		}
> >   		if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> > -			xe_warn(xe, "[RAS]: error counter threshold crossed\n");
> > +			xe_ras_event_log(xe, &response);
> >   		} else {
> >   			xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> >   			return;

✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev2)

[Patchwork]

== Series Details ==

Series: Introduce Xe Correctable Error Handling (rev2)
URL   : https://patchwork.freedesktop.org/series/160184/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 95b4bc3a4cca88a7be14b8603996b8385e758c67
Author: Raag Jadav <raag.jadav@intel.com>
Date:   Fri Feb 13 13:46:02 2026 +0530

    drm/xe/ras: Introduce correctable error handling
    
    Add initial support for correctable error handling which is serviced
    using system controller event. Currently we only log the errors in
    dmesg but this serves as a foundation for RAS infrastructure and will
    be further extended to facilitate other RAS features.
    
    Signed-off-by: Raag Jadav <raag.jadav@intel.com>
+ /mt/dim checkpatch cd76e45b9a192aa3d4f7a2efb8ee46767f098e07 drm-intel
636520e8a067 drm/xe/sysctrl: Add System Controller
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

-:779: ERROR:NO_AUTHOR_SIGN_OFF: Missing Signed-off-by: line by nominal patch author 'Anoop Vijay <anoop.c.vijay@intel.com>'

total: 1 errors, 1 warnings, 0 checks, 699 lines checked
d065f825ea0c drm/xe/sysctrl: Add system controller interrupt handler
264bd343f32b drm/xe/sysctrl: Add system controller event support
-:54: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 165 lines checked
95b4bc3a4cca drm/xe/ras: Introduce correctable error handling
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26: 
new file mode 100644

-:69: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#69: FILE: drivers/gpu/drm/xe/xe_ras.c:39:
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);

-:80: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#80: FILE: drivers/gpu/drm/xe/xe_ras.c:50:
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);

total: 0 errors, 1 warnings, 2 checks, 202 lines checked

✓ CI.KUnit: success for Introduce Xe Correctable Error Handling (rev2)

[Patchwork]

== Series Details ==

Series: Introduce Xe Correctable Error Handling (rev2)
URL   : https://patchwork.freedesktop.org/series/160184/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[08:23:48] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:23:53] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:24:24] Starting KUnit Kernel (1/1)...
[08:24:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:24:24] ================== guc_buf (11 subtests) ===================
[08:24:24] [PASSED] test_smallest
[08:24:24] [PASSED] test_largest
[08:24:24] [PASSED] test_granular
[08:24:24] [PASSED] test_unique
[08:24:24] [PASSED] test_overlap
[08:24:24] [PASSED] test_reusable
[08:24:24] [PASSED] test_too_big
[08:24:24] [PASSED] test_flush
[08:24:24] [PASSED] test_lookup
[08:24:24] [PASSED] test_data
[08:24:24] [PASSED] test_class
[08:24:24] ===================== [PASSED] guc_buf =====================
[08:24:24] =================== guc_dbm (7 subtests) ===================
[08:24:24] [PASSED] test_empty
[08:24:24] [PASSED] test_default
[08:24:24] ======================== test_size  ========================
[08:24:24] [PASSED] 4
[08:24:24] [PASSED] 8
[08:24:24] [PASSED] 32
[08:24:24] [PASSED] 256
[08:24:24] ==================== [PASSED] test_size ====================
[08:24:24] ======================= test_reuse  ========================
[08:24:24] [PASSED] 4
[08:24:24] [PASSED] 8
[08:24:24] [PASSED] 32
[08:24:24] [PASSED] 256
[08:24:24] =================== [PASSED] test_reuse ====================
[08:24:24] =================== test_range_overlap  ====================
[08:24:24] [PASSED] 4
[08:24:24] [PASSED] 8
[08:24:24] [PASSED] 32
[08:24:24] [PASSED] 256
[08:24:24] =============== [PASSED] test_range_overlap ================
[08:24:24] =================== test_range_compact  ====================
[08:24:24] [PASSED] 4
[08:24:24] [PASSED] 8
[08:24:24] [PASSED] 32
[08:24:24] [PASSED] 256
[08:24:24] =============== [PASSED] test_range_compact ================
[08:24:24] ==================== test_range_spare  =====================
[08:24:24] [PASSED] 4
[08:24:24] [PASSED] 8
[08:24:24] [PASSED] 32
[08:24:24] [PASSED] 256
[08:24:24] ================ [PASSED] test_range_spare =================
[08:24:24] ===================== [PASSED] guc_dbm =====================
[08:24:24] =================== guc_idm (6 subtests) ===================
[08:24:24] [PASSED] bad_init
[08:24:24] [PASSED] no_init
[08:24:24] [PASSED] init_fini
[08:24:24] [PASSED] check_used
[08:24:24] [PASSED] check_quota
[08:24:24] [PASSED] check_all
[08:24:24] ===================== [PASSED] guc_idm =====================
[08:24:24] ================== no_relay (3 subtests) ===================
[08:24:24] [PASSED] xe_drops_guc2pf_if_not_ready
[08:24:24] [PASSED] xe_drops_guc2vf_if_not_ready
[08:24:24] [PASSED] xe_rejects_send_if_not_ready
[08:24:24] ==================== [PASSED] no_relay =====================
[08:24:24] ================== pf_relay (14 subtests) ==================
[08:24:24] [PASSED] pf_rejects_guc2pf_too_short
[08:24:24] [PASSED] pf_rejects_guc2pf_too_long
[08:24:24] [PASSED] pf_rejects_guc2pf_no_payload
[08:24:24] [PASSED] pf_fails_no_payload
[08:24:24] [PASSED] pf_fails_bad_origin
[08:24:24] [PASSED] pf_fails_bad_type
[08:24:24] [PASSED] pf_txn_reports_error
[08:24:24] [PASSED] pf_txn_sends_pf2guc
[08:24:24] [PASSED] pf_sends_pf2guc
[08:24:24] [SKIPPED] pf_loopback_nop
[08:24:24] [SKIPPED] pf_loopback_echo
[08:24:24] [SKIPPED] pf_loopback_fail
[08:24:24] [SKIPPED] pf_loopback_busy
[08:24:24] [SKIPPED] pf_loopback_retry
[08:24:25] ==================== [PASSED] pf_relay =====================
[08:24:25] ================== vf_relay (3 subtests) ===================
[08:24:25] [PASSED] vf_rejects_guc2vf_too_short
[08:24:25] [PASSED] vf_rejects_guc2vf_too_long
[08:24:25] [PASSED] vf_rejects_guc2vf_no_payload
[08:24:25] ==================== [PASSED] vf_relay =====================
[08:24:25] ================ pf_gt_config (6 subtests) =================
[08:24:25] [PASSED] fair_contexts_1vf
[08:24:25] [PASSED] fair_doorbells_1vf
[08:24:25] [PASSED] fair_ggtt_1vf
[08:24:25] ====================== fair_contexts  ======================
[08:24:25] [PASSED] 1 VF
[08:24:25] [PASSED] 2 VFs
[08:24:25] [PASSED] 3 VFs
[08:24:25] [PASSED] 4 VFs
[08:24:25] [PASSED] 5 VFs
[08:24:25] [PASSED] 6 VFs
[08:24:25] [PASSED] 7 VFs
[08:24:25] [PASSED] 8 VFs
[08:24:25] [PASSED] 9 VFs
[08:24:25] [PASSED] 10 VFs
[08:24:25] [PASSED] 11 VFs
[08:24:25] [PASSED] 12 VFs
[08:24:25] [PASSED] 13 VFs
[08:24:25] [PASSED] 14 VFs
[08:24:25] [PASSED] 15 VFs
[08:24:25] [PASSED] 16 VFs
[08:24:25] [PASSED] 17 VFs
[08:24:25] [PASSED] 18 VFs
[08:24:25] [PASSED] 19 VFs
[08:24:25] [PASSED] 20 VFs
[08:24:25] [PASSED] 21 VFs
[08:24:25] [PASSED] 22 VFs
[08:24:25] [PASSED] 23 VFs
[08:24:25] [PASSED] 24 VFs
[08:24:25] [PASSED] 25 VFs
[08:24:25] [PASSED] 26 VFs
[08:24:25] [PASSED] 27 VFs
[08:24:25] [PASSED] 28 VFs
[08:24:25] [PASSED] 29 VFs
[08:24:25] [PASSED] 30 VFs
[08:24:25] [PASSED] 31 VFs
[08:24:25] [PASSED] 32 VFs
[08:24:25] [PASSED] 33 VFs
[08:24:25] [PASSED] 34 VFs
[08:24:25] [PASSED] 35 VFs
[08:24:25] [PASSED] 36 VFs
[08:24:25] [PASSED] 37 VFs
[08:24:25] [PASSED] 38 VFs
[08:24:25] [PASSED] 39 VFs
[08:24:25] [PASSED] 40 VFs
[08:24:25] [PASSED] 41 VFs
[08:24:25] [PASSED] 42 VFs
[08:24:25] [PASSED] 43 VFs
[08:24:25] [PASSED] 44 VFs
[08:24:25] [PASSED] 45 VFs
[08:24:25] [PASSED] 46 VFs
[08:24:25] [PASSED] 47 VFs
[08:24:25] [PASSED] 48 VFs
[08:24:25] [PASSED] 49 VFs
[08:24:25] [PASSED] 50 VFs
[08:24:25] [PASSED] 51 VFs
[08:24:25] [PASSED] 52 VFs
[08:24:25] [PASSED] 53 VFs
[08:24:25] [PASSED] 54 VFs
[08:24:25] [PASSED] 55 VFs
[08:24:25] [PASSED] 56 VFs
[08:24:25] [PASSED] 57 VFs
[08:24:25] [PASSED] 58 VFs
[08:24:25] [PASSED] 59 VFs
[08:24:25] [PASSED] 60 VFs
[08:24:25] [PASSED] 61 VFs
[08:24:25] [PASSED] 62 VFs
[08:24:25] [PASSED] 63 VFs
[08:24:25] ================== [PASSED] fair_contexts ==================
[08:24:25] ===================== fair_doorbells  ======================
[08:24:25] [PASSED] 1 VF
[08:24:25] [PASSED] 2 VFs
[08:24:25] [PASSED] 3 VFs
[08:24:25] [PASSED] 4 VFs
[08:24:25] [PASSED] 5 VFs
[08:24:25] [PASSED] 6 VFs
[08:24:25] [PASSED] 7 VFs
[08:24:25] [PASSED] 8 VFs
[08:24:25] [PASSED] 9 VFs
[08:24:25] [PASSED] 10 VFs
[08:24:25] [PASSED] 11 VFs
[08:24:25] [PASSED] 12 VFs
[08:24:25] [PASSED] 13 VFs
[08:24:25] [PASSED] 14 VFs
[08:24:25] [PASSED] 15 VFs
[08:24:25] [PASSED] 16 VFs
[08:24:25] [PASSED] 17 VFs
[08:24:25] [PASSED] 18 VFs
[08:24:25] [PASSED] 19 VFs
[08:24:25] [PASSED] 20 VFs
[08:24:25] [PASSED] 21 VFs
[08:24:25] [PASSED] 22 VFs
[08:24:25] [PASSED] 23 VFs
[08:24:25] [PASSED] 24 VFs
[08:24:25] [PASSED] 25 VFs
[08:24:25] [PASSED] 26 VFs
[08:24:25] [PASSED] 27 VFs
[08:24:25] [PASSED] 28 VFs
[08:24:25] [PASSED] 29 VFs
[08:24:25] [PASSED] 30 VFs
[08:24:25] [PASSED] 31 VFs
[08:24:25] [PASSED] 32 VFs
[08:24:25] [PASSED] 33 VFs
[08:24:25] [PASSED] 34 VFs
[08:24:25] [PASSED] 35 VFs
[08:24:25] [PASSED] 36 VFs
[08:24:25] [PASSED] 37 VFs
[08:24:25] [PASSED] 38 VFs
[08:24:25] [PASSED] 39 VFs
[08:24:25] [PASSED] 40 VFs
[08:24:25] [PASSED] 41 VFs
[08:24:25] [PASSED] 42 VFs
[08:24:25] [PASSED] 43 VFs
[08:24:25] [PASSED] 44 VFs
[08:24:25] [PASSED] 45 VFs
[08:24:25] [PASSED] 46 VFs
[08:24:25] [PASSED] 47 VFs
[08:24:25] [PASSED] 48 VFs
[08:24:25] [PASSED] 49 VFs
[08:24:25] [PASSED] 50 VFs
[08:24:25] [PASSED] 51 VFs
[08:24:25] [PASSED] 52 VFs
[08:24:25] [PASSED] 53 VFs
[08:24:25] [PASSED] 54 VFs
[08:24:25] [PASSED] 55 VFs
[08:24:25] [PASSED] 56 VFs
[08:24:25] [PASSED] 57 VFs
[08:24:25] [PASSED] 58 VFs
[08:24:25] [PASSED] 59 VFs
[08:24:25] [PASSED] 60 VFs
[08:24:25] [PASSED] 61 VFs
[08:24:25] [PASSED] 62 VFs
[08:24:25] [PASSED] 63 VFs
[08:24:25] ================= [PASSED] fair_doorbells ==================
[08:24:25] ======================== fair_ggtt  ========================
[08:24:25] [PASSED] 1 VF
[08:24:25] [PASSED] 2 VFs
[08:24:25] [PASSED] 3 VFs
[08:24:25] [PASSED] 4 VFs
[08:24:25] [PASSED] 5 VFs
[08:24:25] [PASSED] 6 VFs
[08:24:25] [PASSED] 7 VFs
[08:24:25] [PASSED] 8 VFs
[08:24:25] [PASSED] 9 VFs
[08:24:25] [PASSED] 10 VFs
[08:24:25] [PASSED] 11 VFs
[08:24:25] [PASSED] 12 VFs
[08:24:25] [PASSED] 13 VFs
[08:24:25] [PASSED] 14 VFs
[08:24:25] [PASSED] 15 VFs
[08:24:25] [PASSED] 16 VFs
[08:24:25] [PASSED] 17 VFs
[08:24:25] [PASSED] 18 VFs
[08:24:25] [PASSED] 19 VFs
[08:24:25] [PASSED] 20 VFs
[08:24:25] [PASSED] 21 VFs
[08:24:25] [PASSED] 22 VFs
[08:24:25] [PASSED] 23 VFs
[08:24:25] [PASSED] 24 VFs
[08:24:25] [PASSED] 25 VFs
[08:24:25] [PASSED] 26 VFs
[08:24:25] [PASSED] 27 VFs
[08:24:25] [PASSED] 28 VFs
[08:24:25] [PASSED] 29 VFs
[08:24:25] [PASSED] 30 VFs
[08:24:25] [PASSED] 31 VFs
[08:24:25] [PASSED] 32 VFs
[08:24:25] [PASSED] 33 VFs
[08:24:25] [PASSED] 34 VFs
[08:24:25] [PASSED] 35 VFs
[08:24:25] [PASSED] 36 VFs
[08:24:25] [PASSED] 37 VFs
[08:24:25] [PASSED] 38 VFs
[08:24:25] [PASSED] 39 VFs
[08:24:25] [PASSED] 40 VFs
[08:24:25] [PASSED] 41 VFs
[08:24:25] [PASSED] 42 VFs
[08:24:25] [PASSED] 43 VFs
[08:24:25] [PASSED] 44 VFs
[08:24:25] [PASSED] 45 VFs
[08:24:25] [PASSED] 46 VFs
[08:24:25] [PASSED] 47 VFs
[08:24:25] [PASSED] 48 VFs
[08:24:25] [PASSED] 49 VFs
[08:24:25] [PASSED] 50 VFs
[08:24:25] [PASSED] 51 VFs
[08:24:25] [PASSED] 52 VFs
[08:24:25] [PASSED] 53 VFs
[08:24:25] [PASSED] 54 VFs
[08:24:25] [PASSED] 55 VFs
[08:24:25] [PASSED] 56 VFs
[08:24:25] [PASSED] 57 VFs
[08:24:25] [PASSED] 58 VFs
[08:24:25] [PASSED] 59 VFs
[08:24:25] [PASSED] 60 VFs
[08:24:25] [PASSED] 61 VFs
[08:24:25] [PASSED] 62 VFs
[08:24:25] [PASSED] 63 VFs
[08:24:25] ==================== [PASSED] fair_ggtt ====================
[08:24:25] ================== [PASSED] pf_gt_config ===================
[08:24:25] ===================== lmtt (1 subtest) =====================
[08:24:25] ======================== test_ops  =========================
[08:24:25] [PASSED] 2-level
[08:24:25] [PASSED] multi-level
[08:24:25] ==================== [PASSED] test_ops =====================
[08:24:25] ====================== [PASSED] lmtt =======================
[08:24:25] ================= pf_service (11 subtests) =================
[08:24:25] [PASSED] pf_negotiate_any
[08:24:25] [PASSED] pf_negotiate_base_match
[08:24:25] [PASSED] pf_negotiate_base_newer
[08:24:25] [PASSED] pf_negotiate_base_next
[08:24:25] [SKIPPED] pf_negotiate_base_older
[08:24:25] [PASSED] pf_negotiate_base_prev
[08:24:25] [PASSED] pf_negotiate_latest_match
[08:24:25] [PASSED] pf_negotiate_latest_newer
[08:24:25] [PASSED] pf_negotiate_latest_next
[08:24:25] [SKIPPED] pf_negotiate_latest_older
[08:24:25] [SKIPPED] pf_negotiate_latest_prev
[08:24:25] =================== [PASSED] pf_service ====================
[08:24:25] ================= xe_guc_g2g (2 subtests) ==================
[08:24:25] ============== xe_live_guc_g2g_kunit_default  ==============
[08:24:25] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[08:24:25] ============== xe_live_guc_g2g_kunit_allmem  ===============
[08:24:25] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[08:24:25] =================== [SKIPPED] xe_guc_g2g ===================
[08:24:25] =================== xe_mocs (2 subtests) ===================
[08:24:25] ================ xe_live_mocs_kernel_kunit  ================
[08:24:25] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[08:24:25] ================ xe_live_mocs_reset_kunit  =================
[08:24:25] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[08:24:25] ==================== [SKIPPED] xe_mocs =====================
[08:24:25] ================= xe_migrate (2 subtests) ==================
[08:24:25] ================= xe_migrate_sanity_kunit  =================
[08:24:25] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[08:24:25] ================== xe_validate_ccs_kunit  ==================
[08:24:25] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[08:24:25] =================== [SKIPPED] xe_migrate ===================
[08:24:25] ================== xe_dma_buf (1 subtest) ==================
[08:24:25] ==================== xe_dma_buf_kunit  =====================
[08:24:25] ================ [SKIPPED] xe_dma_buf_kunit ================
[08:24:25] =================== [SKIPPED] xe_dma_buf ===================
[08:24:25] ================= xe_bo_shrink (1 subtest) =================
[08:24:25] =================== xe_bo_shrink_kunit  ====================
[08:24:25] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[08:24:25] ================== [SKIPPED] xe_bo_shrink ==================
[08:24:25] ==================== xe_bo (2 subtests) ====================
[08:24:25] ================== xe_ccs_migrate_kunit  ===================
[08:24:25] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[08:24:25] ==================== xe_bo_evict_kunit  ====================
[08:24:25] =============== [SKIPPED] xe_bo_evict_kunit ================
[08:24:25] ===================== [SKIPPED] xe_bo ======================
[08:24:25] ==================== args (13 subtests) ====================
[08:24:25] [PASSED] count_args_test
[08:24:25] [PASSED] call_args_example
[08:24:25] [PASSED] call_args_test
[08:24:25] [PASSED] drop_first_arg_example
[08:24:25] [PASSED] drop_first_arg_test
[08:24:25] [PASSED] first_arg_example
[08:24:25] [PASSED] first_arg_test
[08:24:25] [PASSED] last_arg_example
[08:24:25] [PASSED] last_arg_test
[08:24:25] [PASSED] pick_arg_example
[08:24:25] [PASSED] if_args_example
[08:24:25] [PASSED] if_args_test
[08:24:25] [PASSED] sep_comma_example
[08:24:25] ====================== [PASSED] args =======================
[08:24:25] =================== xe_pci (3 subtests) ====================
[08:24:25] ==================== check_graphics_ip  ====================
[08:24:25] [PASSED] 12.00 Xe_LP
[08:24:25] [PASSED] 12.10 Xe_LP+
[08:24:25] [PASSED] 12.55 Xe_HPG
[08:24:25] [PASSED] 12.60 Xe_HPC
[08:24:25] [PASSED] 12.70 Xe_LPG
[08:24:25] [PASSED] 12.71 Xe_LPG
[08:24:25] [PASSED] 12.74 Xe_LPG+
[08:24:25] [PASSED] 20.01 Xe2_HPG
[08:24:25] [PASSED] 20.02 Xe2_HPG
[08:24:25] [PASSED] 20.04 Xe2_LPG
[08:24:25] [PASSED] 30.00 Xe3_LPG
[08:24:25] [PASSED] 30.01 Xe3_LPG
[08:24:25] [PASSED] 30.03 Xe3_LPG
[08:24:25] [PASSED] 30.04 Xe3_LPG
[08:24:25] [PASSED] 30.05 Xe3_LPG
[08:24:25] [PASSED] 35.10 Xe3p_LPG
[08:24:25] [PASSED] 35.11 Xe3p_XPC
[08:24:25] ================ [PASSED] check_graphics_ip ================
[08:24:25] ===================== check_media_ip  ======================
[08:24:25] [PASSED] 12.00 Xe_M
[08:24:25] [PASSED] 12.55 Xe_HPM
[08:24:25] [PASSED] 13.00 Xe_LPM+
[08:24:25] [PASSED] 13.01 Xe2_HPM
[08:24:25] [PASSED] 20.00 Xe2_LPM
[08:24:25] [PASSED] 30.00 Xe3_LPM
[08:24:25] [PASSED] 30.02 Xe3_LPM
[08:24:25] [PASSED] 35.00 Xe3p_LPM
[08:24:25] [PASSED] 35.03 Xe3p_HPM
[08:24:25] ================= [PASSED] check_media_ip ==================
[08:24:25] =================== check_platform_desc  ===================
[08:24:25] [PASSED] 0x9A60 (TIGERLAKE)
[08:24:25] [PASSED] 0x9A68 (TIGERLAKE)
[08:24:25] [PASSED] 0x9A70 (TIGERLAKE)
[08:24:25] [PASSED] 0x9A40 (TIGERLAKE)
[08:24:25] [PASSED] 0x9A49 (TIGERLAKE)
[08:24:25] [PASSED] 0x9A59 (TIGERLAKE)
[08:24:25] [PASSED] 0x9A78 (TIGERLAKE)
[08:24:25] [PASSED] 0x9AC0 (TIGERLAKE)
[08:24:25] [PASSED] 0x9AC9 (TIGERLAKE)
[08:24:25] [PASSED] 0x9AD9 (TIGERLAKE)
[08:24:25] [PASSED] 0x9AF8 (TIGERLAKE)
[08:24:25] [PASSED] 0x4C80 (ROCKETLAKE)
[08:24:25] [PASSED] 0x4C8A (ROCKETLAKE)
[08:24:25] [PASSED] 0x4C8B (ROCKETLAKE)
[08:24:25] [PASSED] 0x4C8C (ROCKETLAKE)
[08:24:25] [PASSED] 0x4C90 (ROCKETLAKE)
[08:24:25] [PASSED] 0x4C9A (ROCKETLAKE)
[08:24:25] [PASSED] 0x4680 (ALDERLAKE_S)
[08:24:25] [PASSED] 0x4682 (ALDERLAKE_S)
[08:24:25] [PASSED] 0x4688 (ALDERLAKE_S)
[08:24:25] [PASSED] 0x468A (ALDERLAKE_S)
[08:24:25] [PASSED] 0x468B (ALDERLAKE_S)
[08:24:25] [PASSED] 0x4690 (ALDERLAKE_S)
[08:24:25] [PASSED] 0x4692 (ALDERLAKE_S)
[08:24:25] [PASSED] 0x4693 (ALDERLAKE_S)
[08:24:25] [PASSED] 0x46A0 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46A1 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46A2 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46A3 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46A6 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46A8 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46AA (ALDERLAKE_P)
[08:24:25] [PASSED] 0x462A (ALDERLAKE_P)
[08:24:25] [PASSED] 0x4626 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[08:24:25] [PASSED] 0x4628 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46B0 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46B1 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46B2 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46B3 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46C0 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46C1 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46C2 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46C3 (ALDERLAKE_P)
[08:24:25] [PASSED] 0x46D0 (ALDERLAKE_N)
[08:24:25] [PASSED] 0x46D1 (ALDERLAKE_N)
[08:24:25] [PASSED] 0x46D2 (ALDERLAKE_N)
[08:24:25] [PASSED] 0x46D3 (ALDERLAKE_N)
[08:24:25] [PASSED] 0x46D4 (ALDERLAKE_N)
[08:24:25] [PASSED] 0xA721 (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7A1 (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7A9 (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7AC (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7AD (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA720 (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7A0 (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7A8 (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7AA (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA7AB (ALDERLAKE_P)
[08:24:25] [PASSED] 0xA780 (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA781 (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA782 (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA783 (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA788 (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA789 (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA78A (ALDERLAKE_S)
[08:24:25] [PASSED] 0xA78B (ALDERLAKE_S)
[08:24:25] [PASSED] 0x4905 (DG1)
[08:24:25] [PASSED] 0x4906 (DG1)
[08:24:25] [PASSED] 0x4907 (DG1)
[08:24:25] [PASSED] 0x4908 (DG1)
[08:24:25] [PASSED] 0x4909 (DG1)
[08:24:25] [PASSED] 0x56C0 (DG2)
[08:24:25] [PASSED] 0x56C2 (DG2)
[08:24:25] [PASSED] 0x56C1 (DG2)
[08:24:25] [PASSED] 0x7D51 (METEORLAKE)
[08:24:25] [PASSED] 0x7DD1 (METEORLAKE)
[08:24:25] [PASSED] 0x7D41 (METEORLAKE)
[08:24:25] [PASSED] 0x7D67 (METEORLAKE)
[08:24:25] [PASSED] 0xB640 (METEORLAKE)
[08:24:25] [PASSED] 0x56A0 (DG2)
[08:24:25] [PASSED] 0x56A1 (DG2)
[08:24:25] [PASSED] 0x56A2 (DG2)
[08:24:25] [PASSED] 0x56BE (DG2)
[08:24:25] [PASSED] 0x56BF (DG2)
[08:24:25] [PASSED] 0x5690 (DG2)
[08:24:25] [PASSED] 0x5691 (DG2)
[08:24:25] [PASSED] 0x5692 (DG2)
[08:24:25] [PASSED] 0x56A5 (DG2)
[08:24:25] [PASSED] 0x56A6 (DG2)
[08:24:25] [PASSED] 0x56B0 (DG2)
[08:24:25] [PASSED] 0x56B1 (DG2)
[08:24:25] [PASSED] 0x56BA (DG2)
[08:24:25] [PASSED] 0x56BB (DG2)
[08:24:25] [PASSED] 0x56BC (DG2)
[08:24:25] [PASSED] 0x56BD (DG2)
[08:24:25] [PASSED] 0x5693 (DG2)
[08:24:25] [PASSED] 0x5694 (DG2)
[08:24:25] [PASSED] 0x5695 (DG2)
[08:24:25] [PASSED] 0x56A3 (DG2)
[08:24:25] [PASSED] 0x56A4 (DG2)
[08:24:25] [PASSED] 0x56B2 (DG2)
[08:24:25] [PASSED] 0x56B3 (DG2)
[08:24:25] [PASSED] 0x5696 (DG2)
[08:24:25] [PASSED] 0x5697 (DG2)
[08:24:25] [PASSED] 0xB69 (PVC)
[08:24:25] [PASSED] 0xB6E (PVC)
[08:24:25] [PASSED] 0xBD4 (PVC)
[08:24:25] [PASSED] 0xBD5 (PVC)
[08:24:25] [PASSED] 0xBD6 (PVC)
[08:24:25] [PASSED] 0xBD7 (PVC)
[08:24:25] [PASSED] 0xBD8 (PVC)
[08:24:25] [PASSED] 0xBD9 (PVC)
[08:24:25] [PASSED] 0xBDA (PVC)
[08:24:25] [PASSED] 0xBDB (PVC)
[08:24:25] [PASSED] 0xBE0 (PVC)
[08:24:25] [PASSED] 0xBE1 (PVC)
[08:24:25] [PASSED] 0xBE5 (PVC)
[08:24:25] [PASSED] 0x7D40 (METEORLAKE)
[08:24:25] [PASSED] 0x7D45 (METEORLAKE)
[08:24:25] [PASSED] 0x7D55 (METEORLAKE)
[08:24:25] [PASSED] 0x7D60 (METEORLAKE)
[08:24:25] [PASSED] 0x7DD5 (METEORLAKE)
[08:24:25] [PASSED] 0x6420 (LUNARLAKE)
[08:24:25] [PASSED] 0x64A0 (LUNARLAKE)
[08:24:25] [PASSED] 0x64B0 (LUNARLAKE)
[08:24:25] [PASSED] 0xE202 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE209 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE20B (BATTLEMAGE)
[08:24:25] [PASSED] 0xE20C (BATTLEMAGE)
[08:24:25] [PASSED] 0xE20D (BATTLEMAGE)
[08:24:25] [PASSED] 0xE210 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE211 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE212 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE216 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE220 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE221 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE222 (BATTLEMAGE)
[08:24:25] [PASSED] 0xE223 (BATTLEMAGE)
[08:24:25] [PASSED] 0xB080 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB081 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB082 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB083 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB084 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB085 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB086 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB087 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB08F (PANTHERLAKE)
[08:24:25] [PASSED] 0xB090 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB0A0 (PANTHERLAKE)
[08:24:25] [PASSED] 0xB0B0 (PANTHERLAKE)
[08:24:25] [PASSED] 0xFD80 (PANTHERLAKE)
[08:24:25] [PASSED] 0xFD81 (PANTHERLAKE)
[08:24:25] [PASSED] 0xD740 (NOVALAKE_S)
[08:24:25] [PASSED] 0xD741 (NOVALAKE_S)
[08:24:25] [PASSED] 0xD742 (NOVALAKE_S)
[08:24:25] [PASSED] 0xD743 (NOVALAKE_S)
[08:24:25] [PASSED] 0xD744 (NOVALAKE_S)
[08:24:25] [PASSED] 0xD745 (NOVALAKE_S)
[08:24:25] [PASSED] 0x674C (CRESCENTISLAND)
[08:24:25] [PASSED] 0xD750 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD751 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD752 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD753 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD754 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD755 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD756 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD757 (NOVALAKE_P)
[08:24:25] [PASSED] 0xD75F (NOVALAKE_P)
[08:24:25] =============== [PASSED] check_platform_desc ===============
[08:24:25] ===================== [PASSED] xe_pci ======================
[08:24:25] =================== xe_rtp (2 subtests) ====================
[08:24:25] =============== xe_rtp_process_to_sr_tests  ================
[08:24:25] [PASSED] coalesce-same-reg
[08:24:25] [PASSED] no-match-no-add
[08:24:25] [PASSED] match-or
[08:24:25] [PASSED] match-or-xfail
[08:24:25] [PASSED] no-match-no-add-multiple-rules
[08:24:25] [PASSED] two-regs-two-entries
[08:24:25] [PASSED] clr-one-set-other
[08:24:25] [PASSED] set-field
[08:24:25] [PASSED] conflict-duplicate
[08:24:25] [PASSED] conflict-not-disjoint
[08:24:25] [PASSED] conflict-reg-type
[08:24:25] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[08:24:25] ================== xe_rtp_process_tests  ===================
[08:24:25] [PASSED] active1
[08:24:25] [PASSED] active2
[08:24:25] [PASSED] active-inactive
[08:24:25] [PASSED] inactive-active
[08:24:25] [PASSED] inactive-1st_or_active-inactive
[08:24:25] [PASSED] inactive-2nd_or_active-inactive
[08:24:25] [PASSED] inactive-last_or_active-inactive
[08:24:25] [PASSED] inactive-no_or_active-inactive
[08:24:25] ============== [PASSED] xe_rtp_process_tests ===============
[08:24:25] ===================== [PASSED] xe_rtp ======================
[08:24:25] ==================== xe_wa (1 subtest) =====================
[08:24:25] ======================== xe_wa_gt  =========================
[08:24:25] [PASSED] TIGERLAKE B0
[08:24:25] [PASSED] DG1 A0
[08:24:25] [PASSED] DG1 B0
[08:24:25] [PASSED] ALDERLAKE_S A0
[08:24:25] [PASSED] ALDERLAKE_S B0
[08:24:25] [PASSED] ALDERLAKE_S C0
[08:24:25] [PASSED] ALDERLAKE_S D0
[08:24:25] [PASSED] ALDERLAKE_P A0
[08:24:25] [PASSED] ALDERLAKE_P B0
[08:24:25] [PASSED] ALDERLAKE_P C0
[08:24:25] [PASSED] ALDERLAKE_S RPLS D0
[08:24:25] [PASSED] ALDERLAKE_P RPLU E0
[08:24:25] [PASSED] DG2 G10 C0
[08:24:25] [PASSED] DG2 G11 B1
[08:24:25] [PASSED] DG2 G12 A1
[08:24:25] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[08:24:25] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[08:24:25] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[08:24:25] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[08:24:25] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[08:24:25] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[08:24:25] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[08:24:25] ==================== [PASSED] xe_wa_gt =====================
[08:24:25] ====================== [PASSED] xe_wa ======================
[08:24:25] ============================================================
[08:24:25] Testing complete. Ran 522 tests: passed: 504, skipped: 18
[08:24:25] Elapsed time: 36.491s total, 4.250s configuring, 31.723s building, 0.463s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[08:24:25] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:24:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:24:52] Starting KUnit Kernel (1/1)...
[08:24:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:24:52] ============ drm_test_pick_cmdline (2 subtests) ============
[08:24:52] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[08:24:52] =============== drm_test_pick_cmdline_named  ===============
[08:24:52] [PASSED] NTSC
[08:24:52] [PASSED] NTSC-J
[08:24:52] [PASSED] PAL
[08:24:52] [PASSED] PAL-M
[08:24:52] =========== [PASSED] drm_test_pick_cmdline_named ===========
[08:24:52] ============== [PASSED] drm_test_pick_cmdline ==============
[08:24:52] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[08:24:52] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[08:24:52] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[08:24:52] =========== drm_validate_clone_mode (2 subtests) ===========
[08:24:52] ============== drm_test_check_in_clone_mode  ===============
[08:24:52] [PASSED] in_clone_mode
[08:24:52] [PASSED] not_in_clone_mode
[08:24:52] ========== [PASSED] drm_test_check_in_clone_mode ===========
[08:24:52] =============== drm_test_check_valid_clones  ===============
[08:24:52] [PASSED] not_in_clone_mode
[08:24:52] [PASSED] valid_clone
[08:24:52] [PASSED] invalid_clone
[08:24:52] =========== [PASSED] drm_test_check_valid_clones ===========
[08:24:52] ============= [PASSED] drm_validate_clone_mode =============
[08:24:52] ============= drm_validate_modeset (1 subtest) =============
[08:24:52] [PASSED] drm_test_check_connector_changed_modeset
[08:24:52] ============== [PASSED] drm_validate_modeset ===============
[08:24:52] ====== drm_test_bridge_get_current_state (2 subtests) ======
[08:24:52] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[08:24:52] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[08:24:52] ======== [PASSED] drm_test_bridge_get_current_state ========
[08:24:52] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[08:24:52] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[08:24:52] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[08:24:52] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[08:24:52] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[08:24:52] ============== drm_bridge_alloc (2 subtests) ===============
[08:24:52] [PASSED] drm_test_drm_bridge_alloc_basic
[08:24:52] [PASSED] drm_test_drm_bridge_alloc_get_put
[08:24:52] ================ [PASSED] drm_bridge_alloc =================
[08:24:52] ============= drm_cmdline_parser (40 subtests) =============
[08:24:52] [PASSED] drm_test_cmdline_force_d_only
[08:24:52] [PASSED] drm_test_cmdline_force_D_only_dvi
[08:24:52] [PASSED] drm_test_cmdline_force_D_only_hdmi
[08:24:52] [PASSED] drm_test_cmdline_force_D_only_not_digital
[08:24:52] [PASSED] drm_test_cmdline_force_e_only
[08:24:52] [PASSED] drm_test_cmdline_res
[08:24:52] [PASSED] drm_test_cmdline_res_vesa
[08:24:52] [PASSED] drm_test_cmdline_res_vesa_rblank
[08:24:52] [PASSED] drm_test_cmdline_res_rblank
[08:24:52] [PASSED] drm_test_cmdline_res_bpp
[08:24:52] [PASSED] drm_test_cmdline_res_refresh
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[08:24:52] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[08:24:52] [PASSED] drm_test_cmdline_res_margins_force_on
[08:24:52] [PASSED] drm_test_cmdline_res_vesa_margins
[08:24:52] [PASSED] drm_test_cmdline_name
[08:24:52] [PASSED] drm_test_cmdline_name_bpp
[08:24:52] [PASSED] drm_test_cmdline_name_option
[08:24:52] [PASSED] drm_test_cmdline_name_bpp_option
[08:24:52] [PASSED] drm_test_cmdline_rotate_0
[08:24:52] [PASSED] drm_test_cmdline_rotate_90
[08:24:52] [PASSED] drm_test_cmdline_rotate_180
[08:24:52] [PASSED] drm_test_cmdline_rotate_270
[08:24:52] [PASSED] drm_test_cmdline_hmirror
[08:24:52] [PASSED] drm_test_cmdline_vmirror
[08:24:52] [PASSED] drm_test_cmdline_margin_options
[08:24:52] [PASSED] drm_test_cmdline_multiple_options
[08:24:52] [PASSED] drm_test_cmdline_bpp_extra_and_option
[08:24:52] [PASSED] drm_test_cmdline_extra_and_option
[08:24:52] [PASSED] drm_test_cmdline_freestanding_options
[08:24:52] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[08:24:52] [PASSED] drm_test_cmdline_panel_orientation
[08:24:52] ================ drm_test_cmdline_invalid  =================
[08:24:52] [PASSED] margin_only
[08:24:52] [PASSED] interlace_only
[08:24:52] [PASSED] res_missing_x
[08:24:52] [PASSED] res_missing_y
[08:24:52] [PASSED] res_bad_y
[08:24:52] [PASSED] res_missing_y_bpp
[08:24:52] [PASSED] res_bad_bpp
[08:24:52] [PASSED] res_bad_refresh
[08:24:52] [PASSED] res_bpp_refresh_force_on_off
[08:24:52] [PASSED] res_invalid_mode
[08:24:52] [PASSED] res_bpp_wrong_place_mode
[08:24:52] [PASSED] name_bpp_refresh
[08:24:52] [PASSED] name_refresh
[08:24:52] [PASSED] name_refresh_wrong_mode
[08:24:52] [PASSED] name_refresh_invalid_mode
[08:24:52] [PASSED] rotate_multiple
[08:24:52] [PASSED] rotate_invalid_val
[08:24:52] [PASSED] rotate_truncated
[08:24:52] [PASSED] invalid_option
[08:24:52] [PASSED] invalid_tv_option
[08:24:52] [PASSED] truncated_tv_option
[08:24:52] ============ [PASSED] drm_test_cmdline_invalid =============
[08:24:52] =============== drm_test_cmdline_tv_options  ===============
[08:24:52] [PASSED] NTSC
[08:24:52] [PASSED] NTSC_443
[08:24:52] [PASSED] NTSC_J
[08:24:52] [PASSED] PAL
[08:24:52] [PASSED] PAL_M
[08:24:52] [PASSED] PAL_N
[08:24:52] [PASSED] SECAM
[08:24:52] [PASSED] MONO_525
[08:24:52] [PASSED] MONO_625
[08:24:52] =========== [PASSED] drm_test_cmdline_tv_options ===========
[08:24:52] =============== [PASSED] drm_cmdline_parser ================
[08:24:52] ========== drmm_connector_hdmi_init (20 subtests) ==========
[08:24:52] [PASSED] drm_test_connector_hdmi_init_valid
[08:24:52] [PASSED] drm_test_connector_hdmi_init_bpc_8
[08:24:52] [PASSED] drm_test_connector_hdmi_init_bpc_10
[08:24:52] [PASSED] drm_test_connector_hdmi_init_bpc_12
[08:24:52] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[08:24:52] [PASSED] drm_test_connector_hdmi_init_bpc_null
[08:24:52] [PASSED] drm_test_connector_hdmi_init_formats_empty
[08:24:52] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[08:24:52] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[08:24:52] [PASSED] supported_formats=0x9 yuv420_allowed=1
[08:24:52] [PASSED] supported_formats=0x9 yuv420_allowed=0
[08:24:52] [PASSED] supported_formats=0x3 yuv420_allowed=1
[08:24:52] [PASSED] supported_formats=0x3 yuv420_allowed=0
[08:24:52] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[08:24:52] [PASSED] drm_test_connector_hdmi_init_null_ddc
[08:24:52] [PASSED] drm_test_connector_hdmi_init_null_product
[08:24:52] [PASSED] drm_test_connector_hdmi_init_null_vendor
[08:24:52] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[08:24:52] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[08:24:52] [PASSED] drm_test_connector_hdmi_init_product_valid
[08:24:52] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[08:24:52] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[08:24:52] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[08:24:52] ========= drm_test_connector_hdmi_init_type_valid  =========
[08:24:52] [PASSED] HDMI-A
[08:24:52] [PASSED] HDMI-B
[08:24:52] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[08:24:52] ======== drm_test_connector_hdmi_init_type_invalid  ========
[08:24:52] [PASSED] Unknown
[08:24:52] [PASSED] VGA
[08:24:52] [PASSED] DVI-I
[08:24:52] [PASSED] DVI-D
[08:24:52] [PASSED] DVI-A
[08:24:52] [PASSED] Composite
[08:24:52] [PASSED] SVIDEO
[08:24:52] [PASSED] LVDS
[08:24:52] [PASSED] Component
[08:24:52] [PASSED] DIN
[08:24:52] [PASSED] DP
[08:24:52] [PASSED] TV
[08:24:52] [PASSED] eDP
[08:24:52] [PASSED] Virtual
[08:24:52] [PASSED] DSI
[08:24:52] [PASSED] DPI
[08:24:52] [PASSED] Writeback
[08:24:52] [PASSED] SPI
[08:24:52] [PASSED] USB
[08:24:52] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[08:24:52] ============ [PASSED] drmm_connector_hdmi_init =============
[08:24:52] ============= drmm_connector_init (3 subtests) =============
[08:24:52] [PASSED] drm_test_drmm_connector_init
[08:24:52] [PASSED] drm_test_drmm_connector_init_null_ddc
[08:24:52] ========= drm_test_drmm_connector_init_type_valid  =========
[08:24:52] [PASSED] Unknown
[08:24:52] [PASSED] VGA
[08:24:52] [PASSED] DVI-I
[08:24:52] [PASSED] DVI-D
[08:24:52] [PASSED] DVI-A
[08:24:52] [PASSED] Composite
[08:24:52] [PASSED] SVIDEO
[08:24:52] [PASSED] LVDS
[08:24:52] [PASSED] Component
[08:24:52] [PASSED] DIN
[08:24:52] [PASSED] DP
[08:24:52] [PASSED] HDMI-A
[08:24:52] [PASSED] HDMI-B
[08:24:52] [PASSED] TV
[08:24:52] [PASSED] eDP
[08:24:52] [PASSED] Virtual
[08:24:52] [PASSED] DSI
[08:24:52] [PASSED] DPI
[08:24:52] [PASSED] Writeback
[08:24:52] [PASSED] SPI
[08:24:52] [PASSED] USB
[08:24:52] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[08:24:52] =============== [PASSED] drmm_connector_init ===============
[08:24:52] ========= drm_connector_dynamic_init (6 subtests) ==========
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_init
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_init_properties
[08:24:52] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[08:24:52] [PASSED] Unknown
[08:24:52] [PASSED] VGA
[08:24:52] [PASSED] DVI-I
[08:24:52] [PASSED] DVI-D
[08:24:52] [PASSED] DVI-A
[08:24:52] [PASSED] Composite
[08:24:52] [PASSED] SVIDEO
[08:24:52] [PASSED] LVDS
[08:24:52] [PASSED] Component
[08:24:52] [PASSED] DIN
[08:24:52] [PASSED] DP
[08:24:52] [PASSED] HDMI-A
[08:24:52] [PASSED] HDMI-B
[08:24:52] [PASSED] TV
[08:24:52] [PASSED] eDP
[08:24:52] [PASSED] Virtual
[08:24:52] [PASSED] DSI
[08:24:52] [PASSED] DPI
[08:24:52] [PASSED] Writeback
[08:24:52] [PASSED] SPI
[08:24:52] [PASSED] USB
[08:24:52] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[08:24:52] ======== drm_test_drm_connector_dynamic_init_name  =========
[08:24:52] [PASSED] Unknown
[08:24:52] [PASSED] VGA
[08:24:52] [PASSED] DVI-I
[08:24:52] [PASSED] DVI-D
[08:24:52] [PASSED] DVI-A
[08:24:52] [PASSED] Composite
[08:24:52] [PASSED] SVIDEO
[08:24:52] [PASSED] LVDS
[08:24:52] [PASSED] Component
[08:24:52] [PASSED] DIN
[08:24:52] [PASSED] DP
[08:24:52] [PASSED] HDMI-A
[08:24:52] [PASSED] HDMI-B
[08:24:52] [PASSED] TV
[08:24:52] [PASSED] eDP
[08:24:52] [PASSED] Virtual
[08:24:52] [PASSED] DSI
[08:24:52] [PASSED] DPI
[08:24:52] [PASSED] Writeback
[08:24:52] [PASSED] SPI
[08:24:52] [PASSED] USB
[08:24:52] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[08:24:52] =========== [PASSED] drm_connector_dynamic_init ============
[08:24:52] ==== drm_connector_dynamic_register_early (4 subtests) =====
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[08:24:52] ====== [PASSED] drm_connector_dynamic_register_early =======
[08:24:52] ======= drm_connector_dynamic_register (7 subtests) ========
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[08:24:52] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[08:24:52] ========= [PASSED] drm_connector_dynamic_register ==========
[08:24:52] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[08:24:52] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[08:24:52] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[08:24:52] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[08:24:52] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[08:24:52] ========== drm_test_get_tv_mode_from_name_valid  ===========
[08:24:52] [PASSED] NTSC
[08:24:52] [PASSED] NTSC-443
[08:24:52] [PASSED] NTSC-J
[08:24:52] [PASSED] PAL
[08:24:52] [PASSED] PAL-M
[08:24:52] [PASSED] PAL-N
[08:24:52] [PASSED] SECAM
[08:24:52] [PASSED] Mono
[08:24:52] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[08:24:52] [PASSED] drm_test_get_tv_mode_from_name_truncated
[08:24:52] ============ [PASSED] drm_get_tv_mode_from_name ============
[08:24:52] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[08:24:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[08:24:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[08:24:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[08:24:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[08:24:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[08:24:52] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[08:24:52] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[08:24:52] [PASSED] VIC 96
[08:24:52] [PASSED] VIC 97
[08:24:52] [PASSED] VIC 101
[08:24:52] [PASSED] VIC 102
[08:24:52] [PASSED] VIC 106
[08:24:52] [PASSED] VIC 107
[08:24:52] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[08:24:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[08:24:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[08:24:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[08:24:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[08:24:52] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[08:24:52] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[08:24:52] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[08:24:52] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[08:24:52] [PASSED] Automatic
[08:24:52] [PASSED] Full
[08:24:52] [PASSED] Limited 16:235
[08:24:52] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[08:24:52] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[08:24:52] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[08:24:52] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[08:24:52] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[08:24:52] [PASSED] RGB
[08:24:52] [PASSED] YUV 4:2:0
[08:24:52] [PASSED] YUV 4:2:2
[08:24:52] [PASSED] YUV 4:4:4
[08:24:52] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[08:24:52] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[08:24:52] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[08:24:52] ============= drm_damage_helper (21 subtests) ==============
[08:24:52] [PASSED] drm_test_damage_iter_no_damage
[08:24:52] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[08:24:52] [PASSED] drm_test_damage_iter_no_damage_src_moved
[08:24:52] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[08:24:52] [PASSED] drm_test_damage_iter_no_damage_not_visible
[08:24:52] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[08:24:52] [PASSED] drm_test_damage_iter_no_damage_no_fb
[08:24:52] [PASSED] drm_test_damage_iter_simple_damage
[08:24:52] [PASSED] drm_test_damage_iter_single_damage
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_outside_src
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_src_moved
[08:24:52] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[08:24:52] [PASSED] drm_test_damage_iter_damage
[08:24:52] [PASSED] drm_test_damage_iter_damage_one_intersect
[08:24:52] [PASSED] drm_test_damage_iter_damage_one_outside
[08:24:52] [PASSED] drm_test_damage_iter_damage_src_moved
[08:24:52] [PASSED] drm_test_damage_iter_damage_not_visible
[08:24:52] ================ [PASSED] drm_damage_helper ================
[08:24:52] ============== drm_dp_mst_helper (3 subtests) ==============
[08:24:52] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[08:24:52] [PASSED] Clock 154000 BPP 30 DSC disabled
[08:24:52] [PASSED] Clock 234000 BPP 30 DSC disabled
[08:24:52] [PASSED] Clock 297000 BPP 24 DSC disabled
[08:24:52] [PASSED] Clock 332880 BPP 24 DSC enabled
[08:24:52] [PASSED] Clock 324540 BPP 24 DSC enabled
[08:24:52] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[08:24:52] ============== drm_test_dp_mst_calc_pbn_div  ===============
[08:24:52] [PASSED] Link rate 2000000 lane count 4
[08:24:52] [PASSED] Link rate 2000000 lane count 2
[08:24:52] [PASSED] Link rate 2000000 lane count 1
[08:24:52] [PASSED] Link rate 1350000 lane count 4
[08:24:52] [PASSED] Link rate 1350000 lane count 2
[08:24:52] [PASSED] Link rate 1350000 lane count 1
[08:24:52] [PASSED] Link rate 1000000 lane count 4
[08:24:52] [PASSED] Link rate 1000000 lane count 2
[08:24:52] [PASSED] Link rate 1000000 lane count 1
[08:24:52] [PASSED] Link rate 810000 lane count 4
[08:24:52] [PASSED] Link rate 810000 lane count 2
[08:24:52] [PASSED] Link rate 810000 lane count 1
[08:24:52] [PASSED] Link rate 540000 lane count 4
[08:24:52] [PASSED] Link rate 540000 lane count 2
[08:24:52] [PASSED] Link rate 540000 lane count 1
[08:24:52] [PASSED] Link rate 270000 lane count 4
[08:24:52] [PASSED] Link rate 270000 lane count 2
[08:24:52] [PASSED] Link rate 270000 lane count 1
[08:24:52] [PASSED] Link rate 162000 lane count 4
[08:24:52] [PASSED] Link rate 162000 lane count 2
[08:24:52] [PASSED] Link rate 162000 lane count 1
[08:24:52] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[08:24:52] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[08:24:52] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[08:24:52] [PASSED] DP_POWER_UP_PHY with port number
[08:24:52] [PASSED] DP_POWER_DOWN_PHY with port number
[08:24:52] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[08:24:52] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[08:24:52] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[08:24:52] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[08:24:52] [PASSED] DP_QUERY_PAYLOAD with port number
[08:24:52] [PASSED] DP_QUERY_PAYLOAD with VCPI
[08:24:52] [PASSED] DP_REMOTE_DPCD_READ with port number
[08:24:52] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[08:24:52] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[08:24:52] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[08:24:52] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[08:24:52] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[08:24:52] [PASSED] DP_REMOTE_I2C_READ with port number
[08:24:52] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[08:24:52] [PASSED] DP_REMOTE_I2C_READ with transactions array
[08:24:52] [PASSED] DP_REMOTE_I2C_WRITE with port number
[08:24:52] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[08:24:52] [PASSED] DP_REMOTE_I2C_WRITE with data array
[08:24:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[08:24:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[08:24:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[08:24:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[08:24:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[08:24:52] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[08:24:52] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[08:24:52] ================ [PASSED] drm_dp_mst_helper ================
[08:24:52] ================== drm_exec (7 subtests) ===================
[08:24:52] [PASSED] sanitycheck
[08:24:52] [PASSED] test_lock
[08:24:52] [PASSED] test_lock_unlock
[08:24:52] [PASSED] test_duplicates
[08:24:52] [PASSED] test_prepare
[08:24:52] [PASSED] test_prepare_array
[08:24:52] [PASSED] test_multiple_loops
[08:24:52] ==================== [PASSED] drm_exec =====================
[08:24:52] =========== drm_format_helper_test (17 subtests) ===========
[08:24:52] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[08:24:52] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[08:24:52] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[08:24:52] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[08:24:52] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[08:24:52] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[08:24:52] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[08:24:52] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[08:24:52] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[08:24:52] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[08:24:52] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[08:24:52] ============== drm_test_fb_xrgb8888_to_mono  ===============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[08:24:52] ==================== drm_test_fb_swab  =====================
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ================ [PASSED] drm_test_fb_swab =================
[08:24:52] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[08:24:52] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[08:24:52] [PASSED] single_pixel_source_buffer
[08:24:52] [PASSED] single_pixel_clip_rectangle
[08:24:52] [PASSED] well_known_colors
[08:24:52] [PASSED] destination_pitch
[08:24:52] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[08:24:52] ================= drm_test_fb_clip_offset  =================
[08:24:52] [PASSED] pass through
[08:24:52] [PASSED] horizontal offset
[08:24:52] [PASSED] vertical offset
[08:24:52] [PASSED] horizontal and vertical offset
[08:24:52] [PASSED] horizontal offset (custom pitch)
[08:24:52] [PASSED] vertical offset (custom pitch)
[08:24:52] [PASSED] horizontal and vertical offset (custom pitch)
[08:24:52] ============= [PASSED] drm_test_fb_clip_offset =============
[08:24:52] =================== drm_test_fb_memcpy  ====================
[08:24:52] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[08:24:52] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[08:24:52] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[08:24:52] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[08:24:52] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[08:24:52] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[08:24:52] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[08:24:52] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[08:24:52] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[08:24:52] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[08:24:52] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[08:24:52] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[08:24:52] =============== [PASSED] drm_test_fb_memcpy ================
[08:24:52] ============= [PASSED] drm_format_helper_test ==============
[08:24:52] ================= drm_format (18 subtests) =================
[08:24:52] [PASSED] drm_test_format_block_width_invalid
[08:24:52] [PASSED] drm_test_format_block_width_one_plane
[08:24:52] [PASSED] drm_test_format_block_width_two_plane
[08:24:52] [PASSED] drm_test_format_block_width_three_plane
[08:24:52] [PASSED] drm_test_format_block_width_tiled
[08:24:52] [PASSED] drm_test_format_block_height_invalid
[08:24:52] [PASSED] drm_test_format_block_height_one_plane
[08:24:52] [PASSED] drm_test_format_block_height_two_plane
[08:24:52] [PASSED] drm_test_format_block_height_three_plane
[08:24:52] [PASSED] drm_test_format_block_height_tiled
[08:24:52] [PASSED] drm_test_format_min_pitch_invalid
[08:24:52] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[08:24:52] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[08:24:52] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[08:24:52] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[08:24:52] [PASSED] drm_test_format_min_pitch_two_plane
[08:24:52] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[08:24:52] [PASSED] drm_test_format_min_pitch_tiled
[08:24:52] =================== [PASSED] drm_format ====================
[08:24:52] ============== drm_framebuffer (10 subtests) ===============
[08:24:52] ========== drm_test_framebuffer_check_src_coords  ==========
[08:24:52] [PASSED] Success: source fits into fb
[08:24:52] [PASSED] Fail: overflowing fb with x-axis coordinate
[08:24:52] [PASSED] Fail: overflowing fb with y-axis coordinate
[08:24:52] [PASSED] Fail: overflowing fb with source width
[08:24:52] [PASSED] Fail: overflowing fb with source height
[08:24:52] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[08:24:52] [PASSED] drm_test_framebuffer_cleanup
[08:24:52] =============== drm_test_framebuffer_create  ===============
[08:24:52] [PASSED] ABGR8888 normal sizes
[08:24:52] [PASSED] ABGR8888 max sizes
[08:24:52] [PASSED] ABGR8888 pitch greater than min required
[08:24:52] [PASSED] ABGR8888 pitch less than min required
[08:24:52] [PASSED] ABGR8888 Invalid width
[08:24:52] [PASSED] ABGR8888 Invalid buffer handle
[08:24:52] [PASSED] No pixel format
[08:24:52] [PASSED] ABGR8888 Width 0
[08:24:52] [PASSED] ABGR8888 Height 0
[08:24:52] [PASSED] ABGR8888 Out of bound height * pitch combination
[08:24:52] [PASSED] ABGR8888 Large buffer offset
[08:24:52] [PASSED] ABGR8888 Buffer offset for inexistent plane
[08:24:52] [PASSED] ABGR8888 Invalid flag
[08:24:52] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[08:24:52] [PASSED] ABGR8888 Valid buffer modifier
[08:24:52] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[08:24:52] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] NV12 Normal sizes
[08:24:52] [PASSED] NV12 Max sizes
[08:24:52] [PASSED] NV12 Invalid pitch
[08:24:52] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[08:24:52] [PASSED] NV12 different  modifier per-plane
[08:24:52] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[08:24:52] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] NV12 Modifier for inexistent plane
[08:24:52] [PASSED] NV12 Handle for inexistent plane
[08:24:52] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[08:24:52] [PASSED] YVU420 Normal sizes
[08:24:52] [PASSED] YVU420 Max sizes
[08:24:52] [PASSED] YVU420 Invalid pitch
[08:24:52] [PASSED] YVU420 Different pitches
[08:24:52] [PASSED] YVU420 Different buffer offsets/pitches
[08:24:52] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[08:24:52] [PASSED] YVU420 Valid modifier
[08:24:52] [PASSED] YVU420 Different modifiers per plane
[08:24:52] [PASSED] YVU420 Modifier for inexistent plane
[08:24:52] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[08:24:52] [PASSED] X0L2 Normal sizes
[08:24:52] [PASSED] X0L2 Max sizes
[08:24:52] [PASSED] X0L2 Invalid pitch
[08:24:52] [PASSED] X0L2 Pitch greater than minimum required
[08:24:52] [PASSED] X0L2 Handle for inexistent plane
[08:24:52] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[08:24:52] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[08:24:52] [PASSED] X0L2 Valid modifier
[08:24:52] [PASSED] X0L2 Modifier for inexistent plane
[08:24:52] =========== [PASSED] drm_test_framebuffer_create ===========
[08:24:52] [PASSED] drm_test_framebuffer_free
[08:24:52] [PASSED] drm_test_framebuffer_init
[08:24:52] [PASSED] drm_test_framebuffer_init_bad_format
[08:24:52] [PASSED] drm_test_framebuffer_init_dev_mismatch
[08:24:52] [PASSED] drm_test_framebuffer_lookup
[08:24:52] [PASSED] drm_test_framebuffer_lookup_inexistent
[08:24:52] [PASSED] drm_test_framebuffer_modifiers_not_supported
[08:24:52] ================= [PASSED] drm_framebuffer =================
[08:24:52] ================ drm_gem_shmem (8 subtests) ================
[08:24:52] [PASSED] drm_gem_shmem_test_obj_create
[08:24:52] [PASSED] drm_gem_shmem_test_obj_create_private
[08:24:52] [PASSED] drm_gem_shmem_test_pin_pages
[08:24:52] [PASSED] drm_gem_shmem_test_vmap
[08:24:52] [PASSED] drm_gem_shmem_test_get_sg_table
[08:24:52] [PASSED] drm_gem_shmem_test_get_pages_sgt
[08:24:52] [PASSED] drm_gem_shmem_test_madvise
[08:24:52] [PASSED] drm_gem_shmem_test_purge
[08:24:52] ================== [PASSED] drm_gem_shmem ==================
[08:24:52] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[08:24:52] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[08:24:52] [PASSED] Automatic
[08:24:52] [PASSED] Full
[08:24:52] [PASSED] Limited 16:235
[08:24:52] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[08:24:52] [PASSED] drm_test_check_disable_connector
[08:24:52] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[08:24:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[08:24:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[08:24:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[08:24:52] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[08:24:52] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[08:24:52] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[08:24:52] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[08:24:52] [PASSED] drm_test_check_output_bpc_dvi
[08:24:52] [PASSED] drm_test_check_output_bpc_format_vic_1
[08:24:52] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[08:24:52] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[08:24:52] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[08:24:52] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[08:24:52] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[08:24:52] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[08:24:52] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[08:24:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[08:24:52] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[08:24:52] [PASSED] drm_test_check_broadcast_rgb_value
[08:24:52] [PASSED] drm_test_check_bpc_8_value
[08:24:52] [PASSED] drm_test_check_bpc_10_value
[08:24:52] [PASSED] drm_test_check_bpc_12_value
[08:24:52] [PASSED] drm_test_check_format_value
[08:24:52] [PASSED] drm_test_check_tmds_char_value
[08:24:52] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[08:24:52] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[08:24:52] [PASSED] drm_test_check_mode_valid
[08:24:52] [PASSED] drm_test_check_mode_valid_reject
[08:24:52] [PASSED] drm_test_check_mode_valid_reject_rate
[08:24:52] [PASSED] drm_test_check_mode_valid_reject_max_clock
[08:24:52] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[08:24:52] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[08:24:52] [PASSED] drm_test_check_infoframes
[08:24:52] [PASSED] drm_test_check_reject_avi_infoframe
[08:24:52] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[08:24:52] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[08:24:52] [PASSED] drm_test_check_reject_audio_infoframe
[08:24:52] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[08:24:52] ================= drm_managed (2 subtests) =================
[08:24:52] [PASSED] drm_test_managed_release_action
[08:24:52] [PASSED] drm_test_managed_run_action
[08:24:52] =================== [PASSED] drm_managed ===================
[08:24:52] =================== drm_mm (6 subtests) ====================
[08:24:52] [PASSED] drm_test_mm_init
[08:24:52] [PASSED] drm_test_mm_debug
[08:24:52] [PASSED] drm_test_mm_align32
[08:24:52] [PASSED] drm_test_mm_align64
[08:24:52] [PASSED] drm_test_mm_lowest
[08:24:52] [PASSED] drm_test_mm_highest
[08:24:52] ===================== [PASSED] drm_mm ======================
[08:24:52] ============= drm_modes_analog_tv (5 subtests) =============
[08:24:52] [PASSED] drm_test_modes_analog_tv_mono_576i
[08:24:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[08:24:52] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[08:24:52] [PASSED] drm_test_modes_analog_tv_pal_576i
[08:24:52] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[08:24:52] =============== [PASSED] drm_modes_analog_tv ===============
[08:24:52] ============== drm_plane_helper (2 subtests) ===============
[08:24:52] =============== drm_test_check_plane_state  ================
[08:24:52] [PASSED] clipping_simple
[08:24:52] [PASSED] clipping_rotate_reflect
[08:24:52] [PASSED] positioning_simple
[08:24:52] [PASSED] upscaling
[08:24:52] [PASSED] downscaling
[08:24:52] [PASSED] rounding1
[08:24:52] [PASSED] rounding2
[08:24:52] [PASSED] rounding3
[08:24:52] [PASSED] rounding4
[08:24:52] =========== [PASSED] drm_test_check_plane_state ============
[08:24:52] =========== drm_test_check_invalid_plane_state  ============
[08:24:52] [PASSED] positioning_invalid
[08:24:52] [PASSED] upscaling_invalid
[08:24:52] [PASSED] downscaling_invalid
[08:24:52] ======= [PASSED] drm_test_check_invalid_plane_state ========
[08:24:52] ================ [PASSED] drm_plane_helper =================
[08:24:52] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[08:24:52] ====== drm_test_connector_helper_tv_get_modes_check  =======
[08:24:52] [PASSED] None
[08:24:52] [PASSED] PAL
[08:24:52] [PASSED] NTSC
[08:24:52] [PASSED] Both, NTSC Default
[08:24:52] [PASSED] Both, PAL Default
[08:24:52] [PASSED] Both, NTSC Default, with PAL on command-line
[08:24:52] [PASSED] Both, PAL Default, with NTSC on command-line
[08:24:52] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[08:24:52] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[08:24:52] ================== drm_rect (9 subtests) ===================
[08:24:52] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[08:24:52] [PASSED] drm_test_rect_clip_scaled_not_clipped
[08:24:52] [PASSED] drm_test_rect_clip_scaled_clipped
[08:24:52] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[08:24:52] ================= drm_test_rect_intersect  =================
[08:24:52] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[08:24:52] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[08:24:52] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[08:24:52] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[08:24:52] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[08:24:52] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[08:24:52] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[08:24:52] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[08:24:52] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[08:24:52] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[08:24:52] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[08:24:52] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[08:24:52] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[08:24:52] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[08:24:52] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[08:24:52] ============= [PASSED] drm_test_rect_intersect =============
[08:24:52] ================ drm_test_rect_calc_hscale  ================
[08:24:52] [PASSED] normal use
[08:24:52] [PASSED] out of max range
[08:24:52] [PASSED] out of min range
[08:24:52] [PASSED] zero dst
[08:24:52] [PASSED] negative src
[08:24:52] [PASSED] negative dst
[08:24:52] ============ [PASSED] drm_test_rect_calc_hscale ============
[08:24:52] ================ drm_test_rect_calc_vscale  ================
[08:24:52] [PASSED] normal use
[08:24:52] [PASSED] out of max range
[08:24:52] [PASSED] out of min range
[08:24:52] [PASSED] zero dst
[08:24:52] [PASSED] negative src
[08:24:52] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[08:24:52] ============ [PASSED] drm_test_rect_calc_vscale ============
[08:24:52] ================== drm_test_rect_rotate  ===================
[08:24:52] [PASSED] reflect-x
[08:24:52] [PASSED] reflect-y
[08:24:52] [PASSED] rotate-0
[08:24:52] [PASSED] rotate-90
[08:24:52] [PASSED] rotate-180
[08:24:52] [PASSED] rotate-270
[08:24:52] ============== [PASSED] drm_test_rect_rotate ===============
[08:24:52] ================ drm_test_rect_rotate_inv  =================
[08:24:52] [PASSED] reflect-x
[08:24:52] [PASSED] reflect-y
[08:24:52] [PASSED] rotate-0
[08:24:52] [PASSED] rotate-90
[08:24:52] [PASSED] rotate-180
[08:24:52] [PASSED] rotate-270
[08:24:52] ============ [PASSED] drm_test_rect_rotate_inv =============
[08:24:52] ==================== [PASSED] drm_rect =====================
[08:24:52] ============ drm_sysfb_modeset_test (1 subtest) ============
[08:24:52] ============ drm_test_sysfb_build_fourcc_list  =============
[08:24:52] [PASSED] no native formats
[08:24:52] [PASSED] XRGB8888 as native format
[08:24:52] [PASSED] remove duplicates
[08:24:52] [PASSED] convert alpha formats
[08:24:52] [PASSED] random formats
[08:24:52] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[08:24:52] ============= [PASSED] drm_sysfb_modeset_test ==============
[08:24:52] ================== drm_fixp (2 subtests) ===================
[08:24:52] [PASSED] drm_test_int2fixp
[08:24:52] [PASSED] drm_test_sm2fixp
[08:24:52] ==================== [PASSED] drm_fixp =====================
[08:24:52] ============================================================
[08:24:52] Testing complete. Ran 621 tests: passed: 621
[08:24:52] Elapsed time: 27.144s total, 1.626s configuring, 25.396s building, 0.120s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[08:24:52] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[08:24:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[08:25:03] Starting KUnit Kernel (1/1)...
[08:25:03] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[08:25:03] ================= ttm_device (5 subtests) ==================
[08:25:03] [PASSED] ttm_device_init_basic
[08:25:03] [PASSED] ttm_device_init_multiple
[08:25:03] [PASSED] ttm_device_fini_basic
[08:25:03] [PASSED] ttm_device_init_no_vma_man
[08:25:03] ================== ttm_device_init_pools  ==================
[08:25:03] [PASSED] No DMA allocations, no DMA32 required
[08:25:03] [PASSED] DMA allocations, DMA32 required
[08:25:03] [PASSED] No DMA allocations, DMA32 required
[08:25:03] [PASSED] DMA allocations, no DMA32 required
[08:25:03] ============== [PASSED] ttm_device_init_pools ==============
[08:25:03] =================== [PASSED] ttm_device ====================
[08:25:03] ================== ttm_pool (8 subtests) ===================
[08:25:03] ================== ttm_pool_alloc_basic  ===================
[08:25:03] [PASSED] One page
[08:25:03] [PASSED] More than one page
[08:25:03] [PASSED] Above the allocation limit
[08:25:03] [PASSED] One page, with coherent DMA mappings enabled
[08:25:03] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:25:03] ============== [PASSED] ttm_pool_alloc_basic ===============
[08:25:03] ============== ttm_pool_alloc_basic_dma_addr  ==============
[08:25:03] [PASSED] One page
[08:25:03] [PASSED] More than one page
[08:25:03] [PASSED] Above the allocation limit
[08:25:03] [PASSED] One page, with coherent DMA mappings enabled
[08:25:03] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[08:25:03] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[08:25:03] [PASSED] ttm_pool_alloc_order_caching_match
[08:25:03] [PASSED] ttm_pool_alloc_caching_mismatch
[08:25:03] [PASSED] ttm_pool_alloc_order_mismatch
[08:25:03] [PASSED] ttm_pool_free_dma_alloc
[08:25:03] [PASSED] ttm_pool_free_no_dma_alloc
[08:25:03] [PASSED] ttm_pool_fini_basic
[08:25:03] ==================== [PASSED] ttm_pool =====================
[08:25:03] ================ ttm_resource (8 subtests) =================
[08:25:03] ================= ttm_resource_init_basic  =================
[08:25:03] [PASSED] Init resource in TTM_PL_SYSTEM
[08:25:03] [PASSED] Init resource in TTM_PL_VRAM
[08:25:03] [PASSED] Init resource in a private placement
[08:25:03] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[08:25:03] ============= [PASSED] ttm_resource_init_basic =============
[08:25:03] [PASSED] ttm_resource_init_pinned
[08:25:03] [PASSED] ttm_resource_fini_basic
[08:25:03] [PASSED] ttm_resource_manager_init_basic
[08:25:03] [PASSED] ttm_resource_manager_usage_basic
[08:25:03] [PASSED] ttm_resource_manager_set_used_basic
[08:25:03] [PASSED] ttm_sys_man_alloc_basic
[08:25:03] [PASSED] ttm_sys_man_free_basic
[08:25:03] ================== [PASSED] ttm_resource ===================
[08:25:03] =================== ttm_tt (15 subtests) ===================
[08:25:03] ==================== ttm_tt_init_basic  ====================
[08:25:03] [PASSED] Page-aligned size
[08:25:03] [PASSED] Extra pages requested
[08:25:03] ================ [PASSED] ttm_tt_init_basic ================
[08:25:03] [PASSED] ttm_tt_init_misaligned
[08:25:03] [PASSED] ttm_tt_fini_basic
[08:25:03] [PASSED] ttm_tt_fini_sg
[08:25:03] [PASSED] ttm_tt_fini_shmem
[08:25:03] [PASSED] ttm_tt_create_basic
[08:25:03] [PASSED] ttm_tt_create_invalid_bo_type
[08:25:03] [PASSED] ttm_tt_create_ttm_exists
[08:25:03] [PASSED] ttm_tt_create_failed
[08:25:03] [PASSED] ttm_tt_destroy_basic
[08:25:03] [PASSED] ttm_tt_populate_null_ttm
[08:25:03] [PASSED] ttm_tt_populate_populated_ttm
[08:25:03] [PASSED] ttm_tt_unpopulate_basic
[08:25:03] [PASSED] ttm_tt_unpopulate_empty_ttm
[08:25:03] [PASSED] ttm_tt_swapin_basic
[08:25:03] ===================== [PASSED] ttm_tt ======================
[08:25:03] =================== ttm_bo (14 subtests) ===================
[08:25:03] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[08:25:03] [PASSED] Cannot be interrupted and sleeps
[08:25:03] [PASSED] Cannot be interrupted, locks straight away
[08:25:03] [PASSED] Can be interrupted, sleeps
[08:25:03] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[08:25:03] [PASSED] ttm_bo_reserve_locked_no_sleep
[08:25:03] [PASSED] ttm_bo_reserve_no_wait_ticket
[08:25:04] [PASSED] ttm_bo_reserve_double_resv
[08:25:04] [PASSED] ttm_bo_reserve_interrupted
[08:25:04] [PASSED] ttm_bo_reserve_deadlock
[08:25:04] [PASSED] ttm_bo_unreserve_basic
[08:25:04] [PASSED] ttm_bo_unreserve_pinned
[08:25:04] [PASSED] ttm_bo_unreserve_bulk
[08:25:04] [PASSED] ttm_bo_fini_basic
[08:25:04] [PASSED] ttm_bo_fini_shared_resv
[08:25:04] [PASSED] ttm_bo_pin_basic
[08:25:04] [PASSED] ttm_bo_pin_unpin_resource
[08:25:04] [PASSED] ttm_bo_multiple_pin_one_unpin
[08:25:04] ===================== [PASSED] ttm_bo ======================
[08:25:04] ============== ttm_bo_validate (21 subtests) ===============
[08:25:04] ============== ttm_bo_init_reserved_sys_man  ===============
[08:25:04] [PASSED] Buffer object for userspace
[08:25:04] [PASSED] Kernel buffer object
[08:25:04] [PASSED] Shared buffer object
[08:25:04] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[08:25:04] ============== ttm_bo_init_reserved_mock_man  ==============
[08:25:04] [PASSED] Buffer object for userspace
[08:25:04] [PASSED] Kernel buffer object
[08:25:04] [PASSED] Shared buffer object
[08:25:04] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[08:25:04] [PASSED] ttm_bo_init_reserved_resv
[08:25:04] ================== ttm_bo_validate_basic  ==================
[08:25:04] [PASSED] Buffer object for userspace
[08:25:04] [PASSED] Kernel buffer object
[08:25:04] [PASSED] Shared buffer object
[08:25:04] ============== [PASSED] ttm_bo_validate_basic ==============
[08:25:04] [PASSED] ttm_bo_validate_invalid_placement
[08:25:04] ============= ttm_bo_validate_same_placement  ==============
[08:25:04] [PASSED] System manager
[08:25:04] [PASSED] VRAM manager
[08:25:04] ========= [PASSED] ttm_bo_validate_same_placement ==========
[08:25:04] [PASSED] ttm_bo_validate_failed_alloc
[08:25:04] [PASSED] ttm_bo_validate_pinned
[08:25:04] [PASSED] ttm_bo_validate_busy_placement
[08:25:04] ================ ttm_bo_validate_multihop  =================
[08:25:04] [PASSED] Buffer object for userspace
[08:25:04] [PASSED] Kernel buffer object
[08:25:04] [PASSED] Shared buffer object
[08:25:04] ============ [PASSED] ttm_bo_validate_multihop =============
[08:25:04] ========== ttm_bo_validate_no_placement_signaled  ==========
[08:25:04] [PASSED] Buffer object in system domain, no page vector
[08:25:04] [PASSED] Buffer object in system domain with an existing page vector
[08:25:04] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[08:25:04] ======== ttm_bo_validate_no_placement_not_signaled  ========
[08:25:04] [PASSED] Buffer object for userspace
[08:25:04] [PASSED] Kernel buffer object
[08:25:04] [PASSED] Shared buffer object
[08:25:04] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[08:25:04] [PASSED] ttm_bo_validate_move_fence_signaled
[08:25:04] ========= ttm_bo_validate_move_fence_not_signaled  =========
[08:25:04] [PASSED] Waits for GPU
[08:25:04] [PASSED] Tries to lock straight away
[08:25:04] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[08:25:04] [PASSED] ttm_bo_validate_happy_evict
[08:25:04] [PASSED] ttm_bo_validate_all_pinned_evict
[08:25:04] [PASSED] ttm_bo_validate_allowed_only_evict
[08:25:04] [PASSED] ttm_bo_validate_deleted_evict
[08:25:04] [PASSED] ttm_bo_validate_busy_domain_evict
[08:25:04] [PASSED] ttm_bo_validate_evict_gutting
[08:25:04] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[08:25:04] ================= [PASSED] ttm_bo_validate =================
[08:25:04] ============================================================
[08:25:04] Testing complete. Ran 101 tests: passed: 101
[08:25:04] Elapsed time: 11.535s total, 1.724s configuring, 9.545s building, 0.224s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Introduce Xe Correctable Error Handling (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1872 bytes --]

== Series Details ==

Series: Introduce Xe Correctable Error Handling (rev2)
URL   : https://patchwork.freedesktop.org/series/160184/
State : success

== Summary ==

CI Bug Log - changes from xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07_BAT -> xe-pw-160184v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 11)
------------------------------

  Missing    (3): bat-adlp-vm bat-ptl-vm bat-bmg-3 

Known issues
------------

  Here are the changes found in xe-pw-160184v2_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#7249])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  * igt@xe_waitfence@abstime:
    - bat-dg2-oem2:       [PASS][3] -> [TIMEOUT][4] ([Intel XE#6506])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/bat-dg2-oem2/igt@xe_waitfence@abstime.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/bat-dg2-oem2/igt@xe_waitfence@abstime.html

  
  [Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
  [Intel XE#7249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7249


Build changes
-------------

  * Linux: xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07 -> xe-pw-160184v2

  IGT_8753: 8753
  xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07: cd76e45b9a192aa3d4f7a2efb8ee46767f098e07
  xe-pw-160184v2: 160184v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/index.html

[-- Attachment #2: Type: text/html, Size: 2471 bytes --]

✓ Xe.CI.FULL: success for Introduce Xe Correctable Error Handling (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 20455 bytes --]

== Series Details ==

Series: Introduce Xe Correctable Error Handling (rev2)
URL   : https://patchwork.freedesktop.org/series/160184/
State : success

== Summary ==

CI Bug Log - changes from xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07_FULL -> xe-pw-160184v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-160184v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2327])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-4/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#1124]) +4 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_bw@linear-tiling-4-displays-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#367]) +3 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#2887]) +5 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#3432])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2252]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2325])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-4/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_content_protection@mei-interface:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2341])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][10] ([Intel XE#1178] / [Intel XE#3304]) +2 other tests fail
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-1/igt@kms_content_protection@srm@pipe-a-dp-2.html

  * igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][11] ([Intel XE#6707])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_content_protection@uevent-hdcp14@pipe-a-dp-1.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-bmg:          NOTRUN -> [SKIP][12] ([Intel XE#2320]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][13] -> [FAIL][14] ([Intel XE#6715])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#2244])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [PASS][16] -> [FAIL][17] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#7178]) +2 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][19] ([Intel XE#4141]) +6 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#7061])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2311]) +14 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#2313]) +11 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#4298])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-6/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#7111]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2393])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2505])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-bmg:          NOTRUN -> [SKIP][27] ([Intel XE#2499])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-6/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#3414] / [Intel XE#3904])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_sharpness_filter@filter-basic:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6503])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_sharpness_filter@filter-basic.html

  * igt@kms_vrr@cmrr:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#2168])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_vrr@cmrr.html

  * igt@kms_vrr@flip-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][33] ([Intel XE#1499])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@kms_vrr@flip-suspend.html

  * igt@xe_eudebug@vma-ufence:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#4837]) +4 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@xe_eudebug@vma-ufence.html

  * igt@xe_eudebug_online@breakpoint-many-sessions-single-tile:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#4837] / [Intel XE#6665]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@xe_eudebug_online@breakpoint-many-sessions-single-tile.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2322]) +4 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-6/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#7136]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@xe_exec_fault_mode@many-execqueues-multi-queue-userptr.html

  * igt@xe_exec_multi_queue@two-queues-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#6874]) +14 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-6/igt@xe_exec_multi_queue@two-queues-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-cm-fd-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#7138]) +3 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@xe_exec_threads@threads-multi-queue-cm-fd-rebind.html

  * igt@xe_multigpu_svm@mgpu-migration-basic:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#6964]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@xe_multigpu_svm@mgpu-migration-basic.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2236])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-2/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#4733]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@xe_pxp@display-pxp-fb.html

  
#### Possible fixes ####

  * igt@kms_addfb_basic@unused-handle:
    - shard-bmg:          [DMESG-WARN][43] ([Intel XE#1727] / [Intel XE#6819]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-3/igt@kms_addfb_basic@unused-handle.html
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_addfb_basic@unused-handle.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3:
    - shard-bmg:          [DMESG-WARN][45] ([Intel XE#3428]) -> [PASS][46] +1 other test pass
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-3/igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-5/igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [FAIL][47] ([Intel XE#5299]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-bmg:          [FAIL][49] ([Intel XE#3098]) -> [PASS][50] +1 other test pass
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-8/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-4/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][51] ([Intel XE#1503]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-3/igt@kms_hdr@invalid-hdr.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [FAIL][53] ([Intel XE#2142]) -> [PASS][54] +1 other test pass
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-lnl-4/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-lnl-6/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][55] ([Intel XE#6321]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-9/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_oa@non-zero-reason-all:
    - shard-lnl:          [FAIL][57] -> [PASS][58] +1 other test pass
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-lnl-6/igt@xe_oa@non-zero-reason-all.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-lnl-2/igt@xe_oa@non-zero-reason-all.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@short-flip-before-cursor-toggle:
    - shard-bmg:          [ABORT][59] ([Intel XE#1727] / [Intel XE#2705] / [Intel XE#4760] / [Intel XE#7169]) -> [ABORT][60] ([Intel XE#2705] / [Intel XE#4760] / [Intel XE#7169])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-2/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-1/igt@kms_cursor_legacy@short-flip-before-cursor-toggle.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [FAIL][61] ([Intel XE#1729]) -> [SKIP][62] ([Intel XE#2426])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2168
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2236]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2236
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2499
  [Intel XE#2505]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2505
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4760
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
  [Intel XE#6707]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6707
  [Intel XE#6715]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6715
  [Intel XE#6819]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6819
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7111]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7111
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7169]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7169
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787


Build changes
-------------

  * Linux: xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07 -> xe-pw-160184v2

  IGT_8753: 8753
  xe-4552-cd76e45b9a192aa3d4f7a2efb8ee46767f098e07: cd76e45b9a192aa3d4f7a2efb8ee46767f098e07
  xe-pw-160184v2: 160184v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v2/index.html

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