* [PATCH v5 0/2] Different page size handle in migrate layer
@ 2025-10-13 3:45 Matthew Brost
2025-10-13 3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost
` (4 more replies)
0 siblings, 5 replies; 17+ messages in thread
From: Matthew Brost @ 2025-10-13 3:45 UTC (permalink / raw)
To: intel-xe; +Cc: stuart.summers, matthew.auld, simon.richter
Handle non-4K PAGE_SIZE and use 2M GPU pages when possible.
Matt
Matthew Brost (2):
drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE
drm/xe: Enable 2M pages in xe_migrate_vram
drivers/gpu/drm/xe/xe_migrate.c | 79 +++++++++++++++++++++++++++------
1 file changed, 65 insertions(+), 14 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 17+ messages in thread* [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE 2025-10-13 3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost @ 2025-10-13 3:45 ` Matthew Brost 2025-10-13 16:38 ` [v5,1/2] " Simon Richter 2025-10-13 16:53 ` [PATCH v5 1/2] " Summers, Stuart 2025-10-13 3:45 ` [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram Matthew Brost ` (3 subsequent siblings) 4 siblings, 2 replies; 17+ messages in thread From: Matthew Brost @ 2025-10-13 3:45 UTC (permalink / raw) To: intel-xe; +Cc: stuart.summers, matthew.auld, simon.richter The build_pt_update_batch_sram function in the Xe migrate layer assumes PAGE_SIZE == XE_PAGE_SIZE (4K), which is not a valid assumption on non-x86 platforms. This patch updates build_pt_update_batch_sram to correctly handle PAGE_SIZE > 4K by programming multiple 4K GPU pages per CPU page. v5: - Mask off non-address bits during compare Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/xe/xe_migrate.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c index 7345a5b65169..216fc0ec2bb7 100644 --- a/drivers/gpu/drm/xe/xe_migrate.c +++ b/drivers/gpu/drm/xe/xe_migrate.c @@ -1781,13 +1781,15 @@ static void build_pt_update_batch_sram(struct xe_migrate *m, u32 size) { u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB]; + u64 gpu_page_size = 0x1ull << xe_pt_shift(0); u32 ptes; int i = 0; - ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE); + ptes = DIV_ROUND_UP(size, gpu_page_size); while (ptes) { u32 chunk = min(MAX_PTE_PER_SDI, ptes); + chunk = ALIGN_DOWN(chunk, PAGE_SIZE / XE_PAGE_SIZE); bb->cs[bb->len++] = MI_STORE_DATA_IMM | MI_SDI_NUM_QW(chunk); bb->cs[bb->len++] = pt_offset; bb->cs[bb->len++] = 0; @@ -1796,18 +1798,30 @@ static void build_pt_update_batch_sram(struct xe_migrate *m, ptes -= chunk; while (chunk--) { - u64 addr = sram_addr[i].addr & PAGE_MASK; + u64 addr = sram_addr[i].addr & ~(gpu_page_size - 1); + u64 pte, orig_addr = addr; xe_tile_assert(m->tile, sram_addr[i].proto == DRM_INTERCONNECT_SYSTEM); xe_tile_assert(m->tile, addr); - addr = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe, - addr, pat_index, - 0, false, 0); - bb->cs[bb->len++] = lower_32_bits(addr); - bb->cs[bb->len++] = upper_32_bits(addr); - i++; +again: + pte = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe, + addr, pat_index, + 0, false, 0); + bb->cs[bb->len++] = lower_32_bits(pte); + bb->cs[bb->len++] = upper_32_bits(pte); + + if (gpu_page_size < PAGE_SIZE) { + addr += XE_PAGE_SIZE; + if (orig_addr + PAGE_SIZE != addr) { + chunk--; + goto again; + } + i++; + } else { + i += gpu_page_size / PAGE_SIZE; + } } } } -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [v5,1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE 2025-10-13 3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost @ 2025-10-13 16:38 ` Simon Richter 2025-10-13 16:53 ` [PATCH v5 1/2] " Summers, Stuart 1 sibling, 0 replies; 17+ messages in thread From: Simon Richter @ 2025-10-13 16:38 UTC (permalink / raw) To: Matthew Brost, intel-xe; +Cc: stuart.summers, matthew.auld [-- Attachment #1.1: Type: text/plain, Size: 482 bytes --] Hi, On 10/13/25 12:45, Matthew Brost wrote: > The build_pt_update_batch_sram function in the Xe migrate layer assumes > PAGE_SIZE == XE_PAGE_SIZE (4K), which is not a valid assumption on > non-x86 platforms. This patch updates build_pt_update_batch_sram to > correctly handle PAGE_SIZE > 4K by programming multiple 4K GPU pages per > CPU page. > > v5: > - Mask off non-address bits during compare Tested-by: Simon Richter <Simon.Richter@hogyros.de> Simon [-- Attachment #2: OpenPGP digital signature --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE 2025-10-13 3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost 2025-10-13 16:38 ` [v5,1/2] " Simon Richter @ 2025-10-13 16:53 ` Summers, Stuart 1 sibling, 0 replies; 17+ messages in thread From: Summers, Stuart @ 2025-10-13 16:53 UTC (permalink / raw) To: intel-xe@lists.freedesktop.org, Brost, Matthew Cc: simon.richter@hogyros.de, Auld, Matthew On Sun, 2025-10-12 at 20:45 -0700, Matthew Brost wrote: > The build_pt_update_batch_sram function in the Xe migrate layer > assumes > PAGE_SIZE == XE_PAGE_SIZE (4K), which is not a valid assumption on > non-x86 platforms. This patch updates build_pt_update_batch_sram to > correctly handle PAGE_SIZE > 4K by programming multiple 4K GPU pages > per > CPU page. > > v5: > - Mask off non-address bits during compare > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> Reviewed-by: Stuart Summers <stuart.summers@intel.com> > --- > drivers/gpu/drm/xe/xe_migrate.c | 30 ++++++++++++++++++++++-------- > 1 file changed, 22 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > b/drivers/gpu/drm/xe/xe_migrate.c > index 7345a5b65169..216fc0ec2bb7 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.c > +++ b/drivers/gpu/drm/xe/xe_migrate.c > @@ -1781,13 +1781,15 @@ static void build_pt_update_batch_sram(struct > xe_migrate *m, > u32 size) > { > u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB]; > + u64 gpu_page_size = 0x1ull << xe_pt_shift(0); > u32 ptes; > int i = 0; > > - ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE); > + ptes = DIV_ROUND_UP(size, gpu_page_size); > while (ptes) { > u32 chunk = min(MAX_PTE_PER_SDI, ptes); > > + chunk = ALIGN_DOWN(chunk, PAGE_SIZE / XE_PAGE_SIZE); > bb->cs[bb->len++] = MI_STORE_DATA_IMM | > MI_SDI_NUM_QW(chunk); > bb->cs[bb->len++] = pt_offset; > bb->cs[bb->len++] = 0; > @@ -1796,18 +1798,30 @@ static void build_pt_update_batch_sram(struct > xe_migrate *m, > ptes -= chunk; > > while (chunk--) { > - u64 addr = sram_addr[i].addr & PAGE_MASK; > + u64 addr = sram_addr[i].addr & > ~(gpu_page_size - 1); > + u64 pte, orig_addr = addr; > > xe_tile_assert(m->tile, sram_addr[i].proto == > DRM_INTERCONNECT_SYSTEM); > xe_tile_assert(m->tile, addr); > - addr = m->q->vm->pt_ops->pte_encode_addr(m- > >tile->xe, > - > addr, pat_index, > - 0, > false, 0); > - bb->cs[bb->len++] = lower_32_bits(addr); > - bb->cs[bb->len++] = upper_32_bits(addr); > > - i++; > +again: > + pte = m->q->vm->pt_ops->pte_encode_addr(m- > >tile->xe, > + addr, > pat_index, > + 0, > false, 0); > + bb->cs[bb->len++] = lower_32_bits(pte); > + bb->cs[bb->len++] = upper_32_bits(pte); > + > + if (gpu_page_size < PAGE_SIZE) { > + addr += XE_PAGE_SIZE; > + if (orig_addr + PAGE_SIZE != addr) { > + chunk--; > + goto again; > + } > + i++; > + } else { > + i += gpu_page_size / PAGE_SIZE; > + } > } > } > } ^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost 2025-10-13 3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost @ 2025-10-13 3:45 ` Matthew Brost 2025-10-13 17:08 ` Summers, Stuart 2025-10-13 5:38 ` ✓ CI.KUnit: success for Different page size handle in migrate layer (rev2) Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 17+ messages in thread From: Matthew Brost @ 2025-10-13 3:45 UTC (permalink / raw) To: intel-xe; +Cc: stuart.summers, matthew.auld, simon.richter Using 2M pages in xe_migrate_vram has two benefits: we issue fewer instructions per 2M copy (1 vs. 512), and the cache hit rate should be higher. This results in increased copy engine bandwidth, as shown by benchmark IGTs. Enable 2M pages by reserving PDEs in the migrate VM and using 2M pages in xe_migrate_vram if the DMA address order matches 2M. v2: - Reuse build_pt_update_batch_sram (Stuart) - Fix build_pt_update_batch_sram for PAGE_SIZE > 4K v3: - More fixes for PAGE_SIZE > 4K, align chunk, decrement chunk as needed - Use stack incr var in xe_migrate_vram_use_pde (Stuart) v4: - Split PAGE_SIZE > 4K fix out in different patch (Stuart) Signed-off-by: Matthew Brost <matthew.brost@intel.com> --- drivers/gpu/drm/xe/xe_migrate.c | 53 ++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c index 216fc0ec2bb7..4ca48dd1cfd8 100644 --- a/drivers/gpu/drm/xe/xe_migrate.c +++ b/drivers/gpu/drm/xe/xe_migrate.c @@ -57,6 +57,13 @@ struct xe_migrate { u64 usm_batch_base_ofs; /** @cleared_mem_ofs: VM offset of @cleared_bo. */ u64 cleared_mem_ofs; + /** @large_page_copy_ofs: VM offset of 2M pages used for large copies */ + u64 large_page_copy_ofs; + /** + * @large_page_copy_pdes: BO offset to writeout 2M pages (PDEs) used for + * large copies + */ + u64 large_page_copy_pdes; /** * @fence: dma-fence representing the last migration job batch. * Protected by @job_mutex. @@ -288,6 +295,12 @@ static int xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m, (i + 1) * 8, u64, entry); } + /* Reserve 2M PDEs */ + level = 1; + m->large_page_copy_ofs = NUM_PT_SLOTS << xe_pt_shift(level); + m->large_page_copy_pdes = map_ofs + XE_PAGE_SIZE * level + + NUM_PT_SLOTS * 8; + /* Set up a 1GiB NULL mapping at 255GiB offset. */ level = 2; xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level + 255 * 8, u64, @@ -1778,10 +1791,10 @@ static u32 pte_update_cmd_size(u64 size) static void build_pt_update_batch_sram(struct xe_migrate *m, struct xe_bb *bb, u32 pt_offset, struct drm_pagemap_addr *sram_addr, - u32 size) + u32 size, int level) { u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB]; - u64 gpu_page_size = 0x1ull << xe_pt_shift(0); + u64 gpu_page_size = 0x1ull << xe_pt_shift(level); u32 ptes; int i = 0; @@ -1808,7 +1821,7 @@ static void build_pt_update_batch_sram(struct xe_migrate *m, again: pte = m->q->vm->pt_ops->pte_encode_addr(m->tile->xe, addr, pat_index, - 0, false, 0); + level, false, 0); bb->cs[bb->len++] = lower_32_bits(pte); bb->cs[bb->len++] = upper_32_bits(pte); @@ -1826,6 +1839,19 @@ static void build_pt_update_batch_sram(struct xe_migrate *m, } } +static bool xe_migrate_vram_use_pde(struct drm_pagemap_addr *sram_addr, + unsigned long size) +{ + u32 large_size = (0x1 << xe_pt_shift(1)); + unsigned long i, incr = large_size / PAGE_SIZE; + + for (i = 0; i < DIV_ROUND_UP(size, PAGE_SIZE); i += incr) + if (PAGE_SIZE << sram_addr[i].order != large_size) + return false; + + return true; +} + enum xe_migrate_copy_dir { XE_MIGRATE_COPY_TO_VRAM, XE_MIGRATE_COPY_TO_SRAM, @@ -1855,6 +1881,7 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m, PAGE_SIZE : 4; int err; unsigned long i, j; + bool use_pde = xe_migrate_vram_use_pde(sram_addr, len + sram_offset); if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) || (sram_offset | vram_addr) & XE_CACHELINE_MASK)) @@ -1879,7 +1906,7 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m, * struct drm_pagemap_addr. Ensure this is the case even with higher * orders. */ - for (i = 0; i < npages;) { + for (i = 0; !use_pde && i < npages;) { unsigned int order = sram_addr[i].order; for (j = 1; j < NR_PAGES(order) && i + j < npages; j++) @@ -1889,16 +1916,26 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m, i += NR_PAGES(order); } - build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE, - sram_addr, len + sram_offset); + if (use_pde) + build_pt_update_batch_sram(m, bb, m->large_page_copy_pdes, + sram_addr, len + sram_offset, 1); + else + build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE, + sram_addr, len + sram_offset, 0); if (dir == XE_MIGRATE_COPY_TO_VRAM) { - src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + sram_offset; + if (use_pde) + src_L0_ofs = m->large_page_copy_ofs + sram_offset; + else + src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + sram_offset; dst_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, false); } else { src_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, false); - dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + sram_offset; + if (use_pde) + dst_L0_ofs = m->large_page_copy_ofs + sram_offset; + else + dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + sram_offset; } bb->cs[bb->len++] = MI_BATCH_BUFFER_END; -- 2.34.1 ^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 3:45 ` [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram Matthew Brost @ 2025-10-13 17:08 ` Summers, Stuart 2025-10-13 17:14 ` Matthew Brost 0 siblings, 1 reply; 17+ messages in thread From: Summers, Stuart @ 2025-10-13 17:08 UTC (permalink / raw) To: intel-xe@lists.freedesktop.org, Brost, Matthew Cc: simon.richter@hogyros.de, Auld, Matthew On Sun, 2025-10-12 at 20:45 -0700, Matthew Brost wrote: > Using 2M pages in xe_migrate_vram has two benefits: we issue fewer > instructions per 2M copy (1 vs. 512), and the cache hit rate should > be > higher. This results in increased copy engine bandwidth, as shown by > benchmark IGTs. > > Enable 2M pages by reserving PDEs in the migrate VM and using 2M > pages > in xe_migrate_vram if the DMA address order matches 2M. > > v2: > - Reuse build_pt_update_batch_sram (Stuart) > - Fix build_pt_update_batch_sram for PAGE_SIZE > 4K > v3: > - More fixes for PAGE_SIZE > 4K, align chunk, decrement chunk as > needed > - Use stack incr var in xe_migrate_vram_use_pde (Stuart) > v4: > - Split PAGE_SIZE > 4K fix out in different patch (Stuart) > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > --- > drivers/gpu/drm/xe/xe_migrate.c | 53 ++++++++++++++++++++++++++++--- > -- > 1 file changed, 45 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > b/drivers/gpu/drm/xe/xe_migrate.c > index 216fc0ec2bb7..4ca48dd1cfd8 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.c > +++ b/drivers/gpu/drm/xe/xe_migrate.c > @@ -57,6 +57,13 @@ struct xe_migrate { > u64 usm_batch_base_ofs; > /** @cleared_mem_ofs: VM offset of @cleared_bo. */ > u64 cleared_mem_ofs; > + /** @large_page_copy_ofs: VM offset of 2M pages used for > large copies */ > + u64 large_page_copy_ofs; > + /** > + * @large_page_copy_pdes: BO offset to writeout 2M pages > (PDEs) used for > + * large copies > + */ > + u64 large_page_copy_pdes; > /** > * @fence: dma-fence representing the last migration job > batch. > * Protected by @job_mutex. > @@ -288,6 +295,12 @@ static int xe_migrate_prepare_vm(struct xe_tile > *tile, struct xe_migrate *m, > (i + 1) * 8, u64, entry); > } > > + /* Reserve 2M PDEs */ > + level = 1; > + m->large_page_copy_ofs = NUM_PT_SLOTS << xe_pt_shift(level); > + m->large_page_copy_pdes = map_ofs + XE_PAGE_SIZE * level + > + NUM_PT_SLOTS * 8; > + > /* Set up a 1GiB NULL mapping at 255GiB offset. */ > level = 2; > xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level + 255 > * 8, u64, > @@ -1778,10 +1791,10 @@ static u32 pte_update_cmd_size(u64 size) > static void build_pt_update_batch_sram(struct xe_migrate *m, > struct xe_bb *bb, u32 > pt_offset, > struct drm_pagemap_addr > *sram_addr, > - u32 size) > + u32 size, int level) > { > u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB]; > - u64 gpu_page_size = 0x1ull << xe_pt_shift(0); > + u64 gpu_page_size = 0x1ull << xe_pt_shift(level); > u32 ptes; > int i = 0; > > @@ -1808,7 +1821,7 @@ static void build_pt_update_batch_sram(struct > xe_migrate *m, > again: > pte = m->q->vm->pt_ops->pte_encode_addr(m- > >tile->xe, > addr, > pat_index, > - 0, > false, 0); > + level > , false, 0); > bb->cs[bb->len++] = lower_32_bits(pte); > bb->cs[bb->len++] = upper_32_bits(pte); > > @@ -1826,6 +1839,19 @@ static void build_pt_update_batch_sram(struct > xe_migrate *m, > } > } > > +static bool xe_migrate_vram_use_pde(struct drm_pagemap_addr > *sram_addr, > + unsigned long size) > +{ > + u32 large_size = (0x1 << xe_pt_shift(1)); > + unsigned long i, incr = large_size / PAGE_SIZE; > + > + for (i = 0; i < DIV_ROUND_UP(size, PAGE_SIZE); i += incr) > + if (PAGE_SIZE << sram_addr[i].order != large_size) > + return false; > + > + return true; > +} > + > enum xe_migrate_copy_dir { > XE_MIGRATE_COPY_TO_VRAM, > XE_MIGRATE_COPY_TO_SRAM, > @@ -1855,6 +1881,7 @@ static struct dma_fence *xe_migrate_vram(struct > xe_migrate *m, > PAGE_SIZE : 4; > int err; > unsigned long i, j; > + bool use_pde = xe_migrate_vram_use_pde(sram_addr, len + > sram_offset); > > if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) || > (sram_offset | vram_addr) & > XE_CACHELINE_MASK)) > @@ -1879,7 +1906,7 @@ static struct dma_fence *xe_migrate_vram(struct > xe_migrate *m, > * struct drm_pagemap_addr. Ensure this is the case even with > higher > * orders. > */ > - for (i = 0; i < npages;) { > + for (i = 0; !use_pde && i < npages;) { What if the CPU page size is larger than 2M? Don't we still want this? Thanks, Stuart > unsigned int order = sram_addr[i].order; > > for (j = 1; j < NR_PAGES(order) && i + j < npages; > j++) > @@ -1889,16 +1916,26 @@ static struct dma_fence > *xe_migrate_vram(struct xe_migrate *m, > i += NR_PAGES(order); > } > > - build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE, > - sram_addr, len + sram_offset); > + if (use_pde) > + build_pt_update_batch_sram(m, bb, m- > >large_page_copy_pdes, > + sram_addr, len + > sram_offset, 1); > + else > + build_pt_update_batch_sram(m, bb, pt_slot * > XE_PAGE_SIZE, > + sram_addr, len + > sram_offset, 0); > > if (dir == XE_MIGRATE_COPY_TO_VRAM) { > - src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > sram_offset; > + if (use_pde) > + src_L0_ofs = m->large_page_copy_ofs + > sram_offset; > + else > + src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > sram_offset; > dst_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > false); > > } else { > src_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > false); > - dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > sram_offset; > + if (use_pde) > + dst_L0_ofs = m->large_page_copy_ofs + > sram_offset; > + else > + dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > sram_offset; > } > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:08 ` Summers, Stuart @ 2025-10-13 17:14 ` Matthew Brost 2025-10-13 17:22 ` Summers, Stuart 2025-10-13 17:29 ` Simon.Richter 0 siblings, 2 replies; 17+ messages in thread From: Matthew Brost @ 2025-10-13 17:14 UTC (permalink / raw) To: Summers, Stuart Cc: intel-xe@lists.freedesktop.org, simon.richter@hogyros.de, Auld, Matthew On Mon, Oct 13, 2025 at 11:08:03AM -0600, Summers, Stuart wrote: > On Sun, 2025-10-12 at 20:45 -0700, Matthew Brost wrote: > > Using 2M pages in xe_migrate_vram has two benefits: we issue fewer > > instructions per 2M copy (1 vs. 512), and the cache hit rate should > > be > > higher. This results in increased copy engine bandwidth, as shown by > > benchmark IGTs. > > > > Enable 2M pages by reserving PDEs in the migrate VM and using 2M > > pages > > in xe_migrate_vram if the DMA address order matches 2M. > > > > v2: > > - Reuse build_pt_update_batch_sram (Stuart) > > - Fix build_pt_update_batch_sram for PAGE_SIZE > 4K > > v3: > > - More fixes for PAGE_SIZE > 4K, align chunk, decrement chunk as > > needed > > - Use stack incr var in xe_migrate_vram_use_pde (Stuart) > > v4: > > - Split PAGE_SIZE > 4K fix out in different patch (Stuart) > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > --- > > drivers/gpu/drm/xe/xe_migrate.c | 53 ++++++++++++++++++++++++++++--- > > -- > > 1 file changed, 45 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > > b/drivers/gpu/drm/xe/xe_migrate.c > > index 216fc0ec2bb7..4ca48dd1cfd8 100644 > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > @@ -57,6 +57,13 @@ struct xe_migrate { > > u64 usm_batch_base_ofs; > > /** @cleared_mem_ofs: VM offset of @cleared_bo. */ > > u64 cleared_mem_ofs; > > + /** @large_page_copy_ofs: VM offset of 2M pages used for > > large copies */ > > + u64 large_page_copy_ofs; > > + /** > > + * @large_page_copy_pdes: BO offset to writeout 2M pages > > (PDEs) used for > > + * large copies > > + */ > > + u64 large_page_copy_pdes; > > /** > > * @fence: dma-fence representing the last migration job > > batch. > > * Protected by @job_mutex. > > @@ -288,6 +295,12 @@ static int xe_migrate_prepare_vm(struct xe_tile > > *tile, struct xe_migrate *m, > > (i + 1) * 8, u64, entry); > > } > > > > + /* Reserve 2M PDEs */ > > + level = 1; > > + m->large_page_copy_ofs = NUM_PT_SLOTS << xe_pt_shift(level); > > + m->large_page_copy_pdes = map_ofs + XE_PAGE_SIZE * level + > > + NUM_PT_SLOTS * 8; > > + > > /* Set up a 1GiB NULL mapping at 255GiB offset. */ > > level = 2; > > xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level + 255 > > * 8, u64, > > @@ -1778,10 +1791,10 @@ static u32 pte_update_cmd_size(u64 size) > > static void build_pt_update_batch_sram(struct xe_migrate *m, > > struct xe_bb *bb, u32 > > pt_offset, > > struct drm_pagemap_addr > > *sram_addr, > > - u32 size) > > + u32 size, int level) > > { > > u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB]; > > - u64 gpu_page_size = 0x1ull << xe_pt_shift(0); > > + u64 gpu_page_size = 0x1ull << xe_pt_shift(level); > > u32 ptes; > > int i = 0; > > > > @@ -1808,7 +1821,7 @@ static void build_pt_update_batch_sram(struct > > xe_migrate *m, > > again: > > pte = m->q->vm->pt_ops->pte_encode_addr(m- > > >tile->xe, > > addr, > > pat_index, > > - 0, > > false, 0); > > + level > > , false, 0); > > bb->cs[bb->len++] = lower_32_bits(pte); > > bb->cs[bb->len++] = upper_32_bits(pte); > > > > @@ -1826,6 +1839,19 @@ static void build_pt_update_batch_sram(struct > > xe_migrate *m, > > } > > } > > > > +static bool xe_migrate_vram_use_pde(struct drm_pagemap_addr > > *sram_addr, > > + unsigned long size) > > +{ > > + u32 large_size = (0x1 << xe_pt_shift(1)); > > + unsigned long i, incr = large_size / PAGE_SIZE; > > + > > + for (i = 0; i < DIV_ROUND_UP(size, PAGE_SIZE); i += incr) > > + if (PAGE_SIZE << sram_addr[i].order != large_size) > > + return false; > > + > > + return true; > > +} > > + > > enum xe_migrate_copy_dir { > > XE_MIGRATE_COPY_TO_VRAM, > > XE_MIGRATE_COPY_TO_SRAM, > > @@ -1855,6 +1881,7 @@ static struct dma_fence *xe_migrate_vram(struct > > xe_migrate *m, > > PAGE_SIZE : 4; > > int err; > > unsigned long i, j; > > + bool use_pde = xe_migrate_vram_use_pde(sram_addr, len + > > sram_offset); > > > > if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) || > > (sram_offset | vram_addr) & > > XE_CACHELINE_MASK)) > > @@ -1879,7 +1906,7 @@ static struct dma_fence *xe_migrate_vram(struct > > xe_migrate *m, > > * struct drm_pagemap_addr. Ensure this is the case even with > > higher > > * orders. > > */ > > - for (i = 0; i < npages;) { > > + for (i = 0; !use_pde && i < npages;) { > > What if the CPU page size is larger than 2M? Don't we still want this? > I'm not handling this but I believe CPU pages are at most 64k on ARM, power, or longsoon. I could add an assert I suppose to make sure this unhandled case never occurs. Matt > Thanks, > Stuart > > > unsigned int order = sram_addr[i].order; > > > > for (j = 1; j < NR_PAGES(order) && i + j < npages; > > j++) > > @@ -1889,16 +1916,26 @@ static struct dma_fence > > *xe_migrate_vram(struct xe_migrate *m, > > i += NR_PAGES(order); > > } > > > > - build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE, > > - sram_addr, len + sram_offset); > > + if (use_pde) > > + build_pt_update_batch_sram(m, bb, m- > > >large_page_copy_pdes, > > + sram_addr, len + > > sram_offset, 1); > > + else > > + build_pt_update_batch_sram(m, bb, pt_slot * > > XE_PAGE_SIZE, > > + sram_addr, len + > > sram_offset, 0); > > > > if (dir == XE_MIGRATE_COPY_TO_VRAM) { > > - src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > sram_offset; > > + if (use_pde) > > + src_L0_ofs = m->large_page_copy_ofs + > > sram_offset; > > + else > > + src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > sram_offset; > > dst_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > > false); > > > > } else { > > src_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > > false); > > - dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > sram_offset; > > + if (use_pde) > > + dst_L0_ofs = m->large_page_copy_ofs + > > sram_offset; > > + else > > + dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > sram_offset; > > } > > > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:14 ` Matthew Brost @ 2025-10-13 17:22 ` Summers, Stuart 2025-10-13 17:34 ` Matthew Brost 2025-10-14 2:17 ` Simon Richter 2025-10-13 17:29 ` Simon.Richter 1 sibling, 2 replies; 17+ messages in thread From: Summers, Stuart @ 2025-10-13 17:22 UTC (permalink / raw) To: Brost, Matthew Cc: intel-xe@lists.freedesktop.org, simon.richter@hogyros.de, Auld, Matthew On Mon, 2025-10-13 at 10:14 -0700, Matthew Brost wrote: > On Mon, Oct 13, 2025 at 11:08:03AM -0600, Summers, Stuart wrote: > > On Sun, 2025-10-12 at 20:45 -0700, Matthew Brost wrote: > > > Using 2M pages in xe_migrate_vram has two benefits: we issue > > > fewer > > > instructions per 2M copy (1 vs. 512), and the cache hit rate > > > should > > > be > > > higher. This results in increased copy engine bandwidth, as shown > > > by > > > benchmark IGTs. > > > > > > Enable 2M pages by reserving PDEs in the migrate VM and using 2M > > > pages > > > in xe_migrate_vram if the DMA address order matches 2M. > > > > > > v2: > > > - Reuse build_pt_update_batch_sram (Stuart) > > > - Fix build_pt_update_batch_sram for PAGE_SIZE > 4K > > > v3: > > > - More fixes for PAGE_SIZE > 4K, align chunk, decrement chunk as > > > needed > > > - Use stack incr var in xe_migrate_vram_use_pde (Stuart) > > > v4: > > > - Split PAGE_SIZE > 4K fix out in different patch (Stuart) > > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > > --- > > > drivers/gpu/drm/xe/xe_migrate.c | 53 > > > ++++++++++++++++++++++++++++--- > > > -- > > > 1 file changed, 45 insertions(+), 8 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > > > b/drivers/gpu/drm/xe/xe_migrate.c > > > index 216fc0ec2bb7..4ca48dd1cfd8 100644 > > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > > @@ -57,6 +57,13 @@ struct xe_migrate { > > > u64 usm_batch_base_ofs; > > > /** @cleared_mem_ofs: VM offset of @cleared_bo. */ > > > u64 cleared_mem_ofs; > > > + /** @large_page_copy_ofs: VM offset of 2M pages used for > > > large copies */ > > > + u64 large_page_copy_ofs; > > > + /** > > > + * @large_page_copy_pdes: BO offset to writeout 2M pages > > > (PDEs) used for > > > + * large copies > > > + */ > > > + u64 large_page_copy_pdes; > > > /** > > > * @fence: dma-fence representing the last migration job > > > batch. > > > * Protected by @job_mutex. > > > @@ -288,6 +295,12 @@ static int xe_migrate_prepare_vm(struct > > > xe_tile > > > *tile, struct xe_migrate *m, > > > (i + 1) * 8, u64, entry); > > > } > > > > > > + /* Reserve 2M PDEs */ > > > + level = 1; > > > + m->large_page_copy_ofs = NUM_PT_SLOTS << > > > xe_pt_shift(level); > > > + m->large_page_copy_pdes = map_ofs + XE_PAGE_SIZE * level > > > + > > > + NUM_PT_SLOTS * 8; > > > + > > > /* Set up a 1GiB NULL mapping at 255GiB offset. */ > > > level = 2; > > > xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level + > > > 255 > > > * 8, u64, > > > @@ -1778,10 +1791,10 @@ static u32 pte_update_cmd_size(u64 size) > > > static void build_pt_update_batch_sram(struct xe_migrate *m, > > > struct xe_bb *bb, u32 > > > pt_offset, > > > struct drm_pagemap_addr > > > *sram_addr, > > > - u32 size) > > > + u32 size, int level) > > > { > > > u16 pat_index = tile_to_xe(m->tile)- > > > >pat.idx[XE_CACHE_WB]; > > > - u64 gpu_page_size = 0x1ull << xe_pt_shift(0); > > > + u64 gpu_page_size = 0x1ull << xe_pt_shift(level); > > > u32 ptes; > > > int i = 0; > > > > > > @@ -1808,7 +1821,7 @@ static void > > > build_pt_update_batch_sram(struct > > > xe_migrate *m, > > > again: > > > pte = m->q->vm->pt_ops- > > > >pte_encode_addr(m- > > > > tile->xe, > > > a > > > ddr, > > > pat_index, > > > - > > > 0, > > > false, 0); > > > + l > > > evel > > > , false, 0); > > > bb->cs[bb->len++] = lower_32_bits(pte); > > > bb->cs[bb->len++] = upper_32_bits(pte); > > > > > > @@ -1826,6 +1839,19 @@ static void > > > build_pt_update_batch_sram(struct > > > xe_migrate *m, > > > } > > > } > > > > > > +static bool xe_migrate_vram_use_pde(struct drm_pagemap_addr > > > *sram_addr, > > > + unsigned long size) > > > +{ > > > + u32 large_size = (0x1 << xe_pt_shift(1)); > > > + unsigned long i, incr = large_size / PAGE_SIZE; > > > + > > > + for (i = 0; i < DIV_ROUND_UP(size, PAGE_SIZE); i += incr) > > > + if (PAGE_SIZE << sram_addr[i].order != > > > large_size) > > > + return false; > > > + > > > + return true; > > > +} > > > + > > > enum xe_migrate_copy_dir { > > > XE_MIGRATE_COPY_TO_VRAM, > > > XE_MIGRATE_COPY_TO_SRAM, > > > @@ -1855,6 +1881,7 @@ static struct dma_fence > > > *xe_migrate_vram(struct > > > xe_migrate *m, > > > PAGE_SIZE : 4; > > > int err; > > > unsigned long i, j; > > > + bool use_pde = xe_migrate_vram_use_pde(sram_addr, len + > > > sram_offset); > > > > > > if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) || > > > (sram_offset | vram_addr) & > > > XE_CACHELINE_MASK)) > > > @@ -1879,7 +1906,7 @@ static struct dma_fence > > > *xe_migrate_vram(struct > > > xe_migrate *m, > > > * struct drm_pagemap_addr. Ensure this is the case even > > > with > > > higher > > > * orders. > > > */ > > > - for (i = 0; i < npages;) { > > > + for (i = 0; !use_pde && i < npages;) { > > > > What if the CPU page size is larger than 2M? Don't we still want > > this? > > > > I'm not handling this but I believe CPU pages are at most 64k on ARM, > power, or longsoon. I could add an assert I suppose to make sure this > unhandled case never occurs. So according to https://docs.kernel.org/admin-guide/mm/hugetlbpage.html we can potentially get 4M-256M pages on some architectures. Maybe we want to say we aren't supporting these? In which case, yeah I think having an assertion here would be helpful. Would it be easier just to apply this same code if sram_addr[i].order > != 2M? Thanks, Stuart > > Matt > > > Thanks, > > Stuart > > > > > unsigned int order = sram_addr[i].order; > > > > > > for (j = 1; j < NR_PAGES(order) && i + j < > > > npages; > > > j++) > > > @@ -1889,16 +1916,26 @@ static struct dma_fence > > > *xe_migrate_vram(struct xe_migrate *m, > > > i += NR_PAGES(order); > > > } > > > > > > - build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE, > > > - sram_addr, len + sram_offset); > > > + if (use_pde) > > > + build_pt_update_batch_sram(m, bb, m- > > > > large_page_copy_pdes, > > > + sram_addr, len + > > > sram_offset, 1); > > > + else > > > + build_pt_update_batch_sram(m, bb, pt_slot * > > > XE_PAGE_SIZE, > > > + sram_addr, len + > > > sram_offset, 0); > > > > > > if (dir == XE_MIGRATE_COPY_TO_VRAM) { > > > - src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > > sram_offset; > > > + if (use_pde) > > > + src_L0_ofs = m->large_page_copy_ofs + > > > sram_offset; > > > + else > > > + src_L0_ofs = xe_migrate_vm_addr(pt_slot, > > > 0) + > > > sram_offset; > > > dst_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > > > false); > > > > > > } else { > > > src_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > > > false); > > > - dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > > sram_offset; > > > + if (use_pde) > > > + dst_L0_ofs = m->large_page_copy_ofs + > > > sram_offset; > > > + else > > > + dst_L0_ofs = xe_migrate_vm_addr(pt_slot, > > > 0) + > > > sram_offset; > > > } > > > > > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:22 ` Summers, Stuart @ 2025-10-13 17:34 ` Matthew Brost 2025-10-13 18:01 ` Summers, Stuart 2025-10-14 2:17 ` Simon Richter 1 sibling, 1 reply; 17+ messages in thread From: Matthew Brost @ 2025-10-13 17:34 UTC (permalink / raw) To: Summers, Stuart Cc: intel-xe@lists.freedesktop.org, simon.richter@hogyros.de, Auld, Matthew On Mon, Oct 13, 2025 at 11:22:10AM -0600, Summers, Stuart wrote: > On Mon, 2025-10-13 at 10:14 -0700, Matthew Brost wrote: > > On Mon, Oct 13, 2025 at 11:08:03AM -0600, Summers, Stuart wrote: > > > On Sun, 2025-10-12 at 20:45 -0700, Matthew Brost wrote: > > > > Using 2M pages in xe_migrate_vram has two benefits: we issue > > > > fewer > > > > instructions per 2M copy (1 vs. 512), and the cache hit rate > > > > should > > > > be > > > > higher. This results in increased copy engine bandwidth, as shown > > > > by > > > > benchmark IGTs. > > > > > > > > Enable 2M pages by reserving PDEs in the migrate VM and using 2M > > > > pages > > > > in xe_migrate_vram if the DMA address order matches 2M. > > > > > > > > v2: > > > > - Reuse build_pt_update_batch_sram (Stuart) > > > > - Fix build_pt_update_batch_sram for PAGE_SIZE > 4K > > > > v3: > > > > - More fixes for PAGE_SIZE > 4K, align chunk, decrement chunk as > > > > needed > > > > - Use stack incr var in xe_migrate_vram_use_pde (Stuart) > > > > v4: > > > > - Split PAGE_SIZE > 4K fix out in different patch (Stuart) > > > > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > > > --- > > > > drivers/gpu/drm/xe/xe_migrate.c | 53 > > > > ++++++++++++++++++++++++++++--- > > > > -- > > > > 1 file changed, 45 insertions(+), 8 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > > > > b/drivers/gpu/drm/xe/xe_migrate.c > > > > index 216fc0ec2bb7..4ca48dd1cfd8 100644 > > > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > > > @@ -57,6 +57,13 @@ struct xe_migrate { > > > > u64 usm_batch_base_ofs; > > > > /** @cleared_mem_ofs: VM offset of @cleared_bo. */ > > > > u64 cleared_mem_ofs; > > > > + /** @large_page_copy_ofs: VM offset of 2M pages used for > > > > large copies */ > > > > + u64 large_page_copy_ofs; > > > > + /** > > > > + * @large_page_copy_pdes: BO offset to writeout 2M pages > > > > (PDEs) used for > > > > + * large copies > > > > + */ > > > > + u64 large_page_copy_pdes; > > > > /** > > > > * @fence: dma-fence representing the last migration job > > > > batch. > > > > * Protected by @job_mutex. > > > > @@ -288,6 +295,12 @@ static int xe_migrate_prepare_vm(struct > > > > xe_tile > > > > *tile, struct xe_migrate *m, > > > > (i + 1) * 8, u64, entry); > > > > } > > > > > > > > + /* Reserve 2M PDEs */ > > > > + level = 1; > > > > + m->large_page_copy_ofs = NUM_PT_SLOTS << > > > > xe_pt_shift(level); > > > > + m->large_page_copy_pdes = map_ofs + XE_PAGE_SIZE * level > > > > + > > > > + NUM_PT_SLOTS * 8; > > > > + > > > > /* Set up a 1GiB NULL mapping at 255GiB offset. */ > > > > level = 2; > > > > xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * level + > > > > 255 > > > > * 8, u64, > > > > @@ -1778,10 +1791,10 @@ static u32 pte_update_cmd_size(u64 size) > > > > static void build_pt_update_batch_sram(struct xe_migrate *m, > > > > struct xe_bb *bb, u32 > > > > pt_offset, > > > > struct drm_pagemap_addr > > > > *sram_addr, > > > > - u32 size) > > > > + u32 size, int level) > > > > { > > > > u16 pat_index = tile_to_xe(m->tile)- > > > > >pat.idx[XE_CACHE_WB]; > > > > - u64 gpu_page_size = 0x1ull << xe_pt_shift(0); > > > > + u64 gpu_page_size = 0x1ull << xe_pt_shift(level); > > > > u32 ptes; > > > > int i = 0; > > > > > > > > @@ -1808,7 +1821,7 @@ static void > > > > build_pt_update_batch_sram(struct > > > > xe_migrate *m, > > > > again: > > > > pte = m->q->vm->pt_ops- > > > > >pte_encode_addr(m- > > > > > tile->xe, > > > > a > > > > ddr, > > > > pat_index, > > > > - > > > > 0, > > > > false, 0); > > > > + l > > > > evel > > > > , false, 0); > > > > bb->cs[bb->len++] = lower_32_bits(pte); > > > > bb->cs[bb->len++] = upper_32_bits(pte); > > > > > > > > @@ -1826,6 +1839,19 @@ static void > > > > build_pt_update_batch_sram(struct > > > > xe_migrate *m, > > > > } > > > > } > > > > > > > > +static bool xe_migrate_vram_use_pde(struct drm_pagemap_addr > > > > *sram_addr, > > > > + unsigned long size) > > > > +{ > > > > + u32 large_size = (0x1 << xe_pt_shift(1)); > > > > + unsigned long i, incr = large_size / PAGE_SIZE; > > > > + > > > > + for (i = 0; i < DIV_ROUND_UP(size, PAGE_SIZE); i += incr) > > > > + if (PAGE_SIZE << sram_addr[i].order != > > > > large_size) > > > > + return false; > > > > + > > > > + return true; > > > > +} > > > > + > > > > enum xe_migrate_copy_dir { > > > > XE_MIGRATE_COPY_TO_VRAM, > > > > XE_MIGRATE_COPY_TO_SRAM, > > > > @@ -1855,6 +1881,7 @@ static struct dma_fence > > > > *xe_migrate_vram(struct > > > > xe_migrate *m, > > > > PAGE_SIZE : 4; > > > > int err; > > > > unsigned long i, j; > > > > + bool use_pde = xe_migrate_vram_use_pde(sram_addr, len + > > > > sram_offset); > > > > > > > > if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) || > > > > (sram_offset | vram_addr) & > > > > XE_CACHELINE_MASK)) > > > > @@ -1879,7 +1906,7 @@ static struct dma_fence > > > > *xe_migrate_vram(struct > > > > xe_migrate *m, > > > > * struct drm_pagemap_addr. Ensure this is the case even > > > > with > > > > higher > > > > * orders. > > > > */ > > > > - for (i = 0; i < npages;) { > > > > + for (i = 0; !use_pde && i < npages;) { > > > > > > What if the CPU page size is larger than 2M? Don't we still want > > > this? > > > > > > > I'm not handling this but I believe CPU pages are at most 64k on ARM, > > power, or longsoon. I could add an assert I suppose to make sure this > > unhandled case never occurs. > > So according to https://docs.kernel.org/admin-guide/mm/hugetlbpage.html > we can potentially get 4M-256M pages on some architectures. Maybe we > want to say we aren't supporting these? In which case, yeah I think > having an assertion here would be helpful. Would it be easier just to > apply this same code if sram_addr[i].order > != 2M? > I only enable the PDE path if order == 2M. See what xe_migrate_vram_use_pde does. Matt > Thanks, > Stuart > > > > > Matt > > > > > Thanks, > > > Stuart > > > > > > > unsigned int order = sram_addr[i].order; > > > > > > > > for (j = 1; j < NR_PAGES(order) && i + j < > > > > npages; > > > > j++) > > > > @@ -1889,16 +1916,26 @@ static struct dma_fence > > > > *xe_migrate_vram(struct xe_migrate *m, > > > > i += NR_PAGES(order); > > > > } > > > > > > > > - build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE, > > > > - sram_addr, len + sram_offset); > > > > + if (use_pde) > > > > + build_pt_update_batch_sram(m, bb, m- > > > > > large_page_copy_pdes, > > > > + sram_addr, len + > > > > sram_offset, 1); > > > > + else > > > > + build_pt_update_batch_sram(m, bb, pt_slot * > > > > XE_PAGE_SIZE, > > > > + sram_addr, len + > > > > sram_offset, 0); > > > > > > > > if (dir == XE_MIGRATE_COPY_TO_VRAM) { > > > > - src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > > > sram_offset; > > > > + if (use_pde) > > > > + src_L0_ofs = m->large_page_copy_ofs + > > > > sram_offset; > > > > + else > > > > + src_L0_ofs = xe_migrate_vm_addr(pt_slot, > > > > 0) + > > > > sram_offset; > > > > dst_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > > > > false); > > > > > > > > } else { > > > > src_L0_ofs = xe_migrate_vram_ofs(xe, vram_addr, > > > > false); > > > > - dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > > > sram_offset; > > > > + if (use_pde) > > > > + dst_L0_ofs = m->large_page_copy_ofs + > > > > sram_offset; > > > > + else > > > > + dst_L0_ofs = xe_migrate_vm_addr(pt_slot, > > > > 0) + > > > > sram_offset; > > > > } > > > > > > > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; > > > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:34 ` Matthew Brost @ 2025-10-13 18:01 ` Summers, Stuart 0 siblings, 0 replies; 17+ messages in thread From: Summers, Stuart @ 2025-10-13 18:01 UTC (permalink / raw) To: Brost, Matthew Cc: intel-xe@lists.freedesktop.org, simon.richter@hogyros.de, Auld, Matthew On Mon, 2025-10-13 at 10:34 -0700, Matthew Brost wrote: > On Mon, Oct 13, 2025 at 11:22:10AM -0600, Summers, Stuart wrote: > > On Mon, 2025-10-13 at 10:14 -0700, Matthew Brost wrote: > > > On Mon, Oct 13, 2025 at 11:08:03AM -0600, Summers, Stuart wrote: > > > > On Sun, 2025-10-12 at 20:45 -0700, Matthew Brost wrote: > > > > > Using 2M pages in xe_migrate_vram has two benefits: we issue > > > > > fewer > > > > > instructions per 2M copy (1 vs. 512), and the cache hit rate > > > > > should > > > > > be > > > > > higher. This results in increased copy engine bandwidth, as > > > > > shown > > > > > by > > > > > benchmark IGTs. > > > > > > > > > > Enable 2M pages by reserving PDEs in the migrate VM and using > > > > > 2M > > > > > pages > > > > > in xe_migrate_vram if the DMA address order matches 2M. > > > > > > > > > > v2: > > > > > - Reuse build_pt_update_batch_sram (Stuart) > > > > > - Fix build_pt_update_batch_sram for PAGE_SIZE > 4K > > > > > v3: > > > > > - More fixes for PAGE_SIZE > 4K, align chunk, decrement > > > > > chunk as > > > > > needed > > > > > - Use stack incr var in xe_migrate_vram_use_pde (Stuart) > > > > > v4: > > > > > - Split PAGE_SIZE > 4K fix out in different patch (Stuart) > > > > > > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com> > > > > > --- > > > > > drivers/gpu/drm/xe/xe_migrate.c | 53 > > > > > ++++++++++++++++++++++++++++--- > > > > > -- > > > > > 1 file changed, 45 insertions(+), 8 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c > > > > > b/drivers/gpu/drm/xe/xe_migrate.c > > > > > index 216fc0ec2bb7..4ca48dd1cfd8 100644 > > > > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > > > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > > > > @@ -57,6 +57,13 @@ struct xe_migrate { > > > > > u64 usm_batch_base_ofs; > > > > > /** @cleared_mem_ofs: VM offset of @cleared_bo. */ > > > > > u64 cleared_mem_ofs; > > > > > + /** @large_page_copy_ofs: VM offset of 2M pages used > > > > > for > > > > > large copies */ > > > > > + u64 large_page_copy_ofs; > > > > > + /** > > > > > + * @large_page_copy_pdes: BO offset to writeout 2M > > > > > pages > > > > > (PDEs) used for > > > > > + * large copies > > > > > + */ > > > > > + u64 large_page_copy_pdes; > > > > > /** > > > > > * @fence: dma-fence representing the last migration > > > > > job > > > > > batch. > > > > > * Protected by @job_mutex. > > > > > @@ -288,6 +295,12 @@ static int xe_migrate_prepare_vm(struct > > > > > xe_tile > > > > > *tile, struct xe_migrate *m, > > > > > (i + 1) * 8, u64, entry); > > > > > } > > > > > > > > > > + /* Reserve 2M PDEs */ > > > > > + level = 1; > > > > > + m->large_page_copy_ofs = NUM_PT_SLOTS << > > > > > xe_pt_shift(level); > > > > > + m->large_page_copy_pdes = map_ofs + XE_PAGE_SIZE * > > > > > level > > > > > + > > > > > + NUM_PT_SLOTS * 8; > > > > > + > > > > > /* Set up a 1GiB NULL mapping at 255GiB offset. */ > > > > > level = 2; > > > > > xe_map_wr(xe, &bo->vmap, map_ofs + XE_PAGE_SIZE * > > > > > level + > > > > > 255 > > > > > * 8, u64, > > > > > @@ -1778,10 +1791,10 @@ static u32 pte_update_cmd_size(u64 > > > > > size) > > > > > static void build_pt_update_batch_sram(struct xe_migrate *m, > > > > > struct xe_bb *bb, u32 > > > > > pt_offset, > > > > > struct > > > > > drm_pagemap_addr > > > > > *sram_addr, > > > > > - u32 size) > > > > > + u32 size, int level) > > > > > { > > > > > u16 pat_index = tile_to_xe(m->tile)- > > > > > > pat.idx[XE_CACHE_WB]; > > > > > - u64 gpu_page_size = 0x1ull << xe_pt_shift(0); > > > > > + u64 gpu_page_size = 0x1ull << xe_pt_shift(level); > > > > > u32 ptes; > > > > > int i = 0; > > > > > > > > > > @@ -1808,7 +1821,7 @@ static void > > > > > build_pt_update_batch_sram(struct > > > > > xe_migrate *m, > > > > > again: > > > > > pte = m->q->vm->pt_ops- > > > > > > pte_encode_addr(m- > > > > > > tile->xe, > > > > > > > > > > a > > > > > ddr, > > > > > pat_index, > > > > > - > > > > > > > > > > 0, > > > > > false, 0); > > > > > + > > > > > l > > > > > evel > > > > > , false, 0); > > > > > bb->cs[bb->len++] = > > > > > lower_32_bits(pte); > > > > > bb->cs[bb->len++] = > > > > > upper_32_bits(pte); > > > > > > > > > > @@ -1826,6 +1839,19 @@ static void > > > > > build_pt_update_batch_sram(struct > > > > > xe_migrate *m, > > > > > } > > > > > } > > > > > > > > > > +static bool xe_migrate_vram_use_pde(struct drm_pagemap_addr > > > > > *sram_addr, > > > > > + unsigned long size) > > > > > +{ > > > > > + u32 large_size = (0x1 << xe_pt_shift(1)); > > > > > + unsigned long i, incr = large_size / PAGE_SIZE; > > > > > + > > > > > + for (i = 0; i < DIV_ROUND_UP(size, PAGE_SIZE); i += > > > > > incr) > > > > > + if (PAGE_SIZE << sram_addr[i].order != > > > > > large_size) > > > > > + return false; > > > > > + > > > > > + return true; > > > > > +} > > > > > + > > > > > enum xe_migrate_copy_dir { > > > > > XE_MIGRATE_COPY_TO_VRAM, > > > > > XE_MIGRATE_COPY_TO_SRAM, > > > > > @@ -1855,6 +1881,7 @@ static struct dma_fence > > > > > *xe_migrate_vram(struct > > > > > xe_migrate *m, > > > > > PAGE_SIZE : 4; > > > > > int err; > > > > > unsigned long i, j; > > > > > + bool use_pde = xe_migrate_vram_use_pde(sram_addr, len > > > > > + > > > > > sram_offset); > > > > > > > > > > if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) > > > > > || > > > > > (sram_offset | vram_addr) & > > > > > XE_CACHELINE_MASK)) > > > > > @@ -1879,7 +1906,7 @@ static struct dma_fence > > > > > *xe_migrate_vram(struct > > > > > xe_migrate *m, > > > > > * struct drm_pagemap_addr. Ensure this is the case > > > > > even > > > > > with > > > > > higher > > > > > * orders. > > > > > */ > > > > > - for (i = 0; i < npages;) { > > > > > + for (i = 0; !use_pde && i < npages;) { > > > > > > > > What if the CPU page size is larger than 2M? Don't we still > > > > want > > > > this? > > > > > > > > > > I'm not handling this but I believe CPU pages are at most 64k on > > > ARM, > > > power, or longsoon. I could add an assert I suppose to make sure > > > this > > > unhandled case never occurs. > > > > So according to > > https://docs.kernel.org/admin-guide/mm/hugetlbpage.html > > we can potentially get 4M-256M pages on some architectures. Maybe > > we > > want to say we aren't supporting these? In which case, yeah I think > > having an assertion here would be helpful. Would it be easier just > > to > > apply this same code if sram_addr[i].order > != 2M? > > > > I only enable the PDE path if order == 2M. See what > xe_migrate_vram_use_pde does. Yeah you're right and I agree we shouldn't have an issue here after a closer look. Reviewed-by: Stuart Summers <stuart.summers@intel.com> Thanks, Stuart > > Matt > > > Thanks, > > Stuart > > > > > > > > Matt > > > > > > > Thanks, > > > > Stuart > > > > > > > > > unsigned int order = sram_addr[i].order; > > > > > > > > > > for (j = 1; j < NR_PAGES(order) && i + j < > > > > > npages; > > > > > j++) > > > > > @@ -1889,16 +1916,26 @@ static struct dma_fence > > > > > *xe_migrate_vram(struct xe_migrate *m, > > > > > i += NR_PAGES(order); > > > > > } > > > > > > > > > > - build_pt_update_batch_sram(m, bb, pt_slot * > > > > > XE_PAGE_SIZE, > > > > > - sram_addr, len + > > > > > sram_offset); > > > > > + if (use_pde) > > > > > + build_pt_update_batch_sram(m, bb, m- > > > > > > large_page_copy_pdes, > > > > > + sram_addr, len + > > > > > sram_offset, 1); > > > > > + else > > > > > + build_pt_update_batch_sram(m, bb, pt_slot * > > > > > XE_PAGE_SIZE, > > > > > + sram_addr, len + > > > > > sram_offset, 0); > > > > > > > > > > if (dir == XE_MIGRATE_COPY_TO_VRAM) { > > > > > - src_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > > > > sram_offset; > > > > > + if (use_pde) > > > > > + src_L0_ofs = m->large_page_copy_ofs + > > > > > sram_offset; > > > > > + else > > > > > + src_L0_ofs = > > > > > xe_migrate_vm_addr(pt_slot, > > > > > 0) + > > > > > sram_offset; > > > > > dst_L0_ofs = xe_migrate_vram_ofs(xe, > > > > > vram_addr, > > > > > false); > > > > > > > > > > } else { > > > > > src_L0_ofs = xe_migrate_vram_ofs(xe, > > > > > vram_addr, > > > > > false); > > > > > - dst_L0_ofs = xe_migrate_vm_addr(pt_slot, 0) + > > > > > sram_offset; > > > > > + if (use_pde) > > > > > + dst_L0_ofs = m->large_page_copy_ofs + > > > > > sram_offset; > > > > > + else > > > > > + dst_L0_ofs = > > > > > xe_migrate_vm_addr(pt_slot, > > > > > 0) + > > > > > sram_offset; > > > > > } > > > > > > > > > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; > > > > > > ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:22 ` Summers, Stuart 2025-10-13 17:34 ` Matthew Brost @ 2025-10-14 2:17 ` Simon Richter 2025-10-14 3:08 ` Summers, Stuart 1 sibling, 1 reply; 17+ messages in thread From: Simon Richter @ 2025-10-14 2:17 UTC (permalink / raw) To: Summers, Stuart, Brost, Matthew Cc: intel-xe@lists.freedesktop.org, Auld, Matthew Hi, On 10/14/25 2:22 AM, Summers, Stuart wrote: > So according to https://docs.kernel.org/admin-guide/mm/hugetlbpage.html > we can potentially get 4M-256M pages on some architectures. These exist but will not be the finest granularity on those architectures, so these should never appear as PAGE_SIZE. The kernel is unable to load executables that have a smaller alignment than PAGE_SIZE for their loadable segments, so that gives a nice upper bound for what we need to expect. There might be places that make the assumption that if there is a hugetlb size that the host supports, it will be 2M, but the worst thing that can happen there is a fallback to PAGE_SIZE and slightly degraded performance. Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-14 2:17 ` Simon Richter @ 2025-10-14 3:08 ` Summers, Stuart 0 siblings, 0 replies; 17+ messages in thread From: Summers, Stuart @ 2025-10-14 3:08 UTC (permalink / raw) To: Brost, Matthew, Simon.Richter@hogyros.de Cc: intel-xe@lists.freedesktop.org, Auld, Matthew On Tue, 2025-10-14 at 11:17 +0900, Simon Richter wrote: > Hi, > > On 10/14/25 2:22 AM, Summers, Stuart wrote: > > > So according to > > https://docs.kernel.org/admin-guide/mm/hugetlbpage.html > > we can potentially get 4M-256M pages on some architectures. > > These exist but will not be the finest granularity on those > architectures, so these should never appear as PAGE_SIZE. > > The kernel is unable to load executables that have a smaller > alignment > than PAGE_SIZE for their loadable segments, so that gives a nice > upper > bound for what we need to expect. > > There might be places that make the assumption that if there is a > hugetlb size that the host supports, it will be 2M, but the worst > thing > that can happen there is a fallback to PAGE_SIZE and slightly > degraded > performance. Yeah makes sense Simon and thanks for the follow-up! -Stuart > > Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:14 ` Matthew Brost 2025-10-13 17:22 ` Summers, Stuart @ 2025-10-13 17:29 ` Simon.Richter 2025-10-13 17:32 ` Matthew Brost 1 sibling, 1 reply; 17+ messages in thread From: Simon.Richter @ 2025-10-13 17:29 UTC (permalink / raw) To: Matthew Brost; +Cc: Summers, Stuart, intel-xe, Auld, Matthew 14 Oct 2025 02:14:44 Matthew Brost <matthew.brost@intel.com>: > I'm not handling this but I believe CPU pages are at most 64k on ARM, > power, or longsoon. I could add an assert I suppose to make sure this > unhandled case never occurs. Hi, POWER can also do 256kB, but that is a very uncommon configuration because it requires the complete userspace to be rebuilt with 256k segment alignment. For that reason I'd expect even larger pages to be very unlikely. Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram 2025-10-13 17:29 ` Simon.Richter @ 2025-10-13 17:32 ` Matthew Brost 0 siblings, 0 replies; 17+ messages in thread From: Matthew Brost @ 2025-10-13 17:32 UTC (permalink / raw) To: Simon.Richter; +Cc: Summers, Stuart, intel-xe, Auld, Matthew On Tue, Oct 14, 2025 at 02:29:52AM +0900, Simon.Richter@hogyros.de wrote: > 14 Oct 2025 02:14:44 Matthew Brost <matthew.brost@intel.com>: > > > I'm not handling this but I believe CPU pages are at most 64k on ARM, > > power, or longsoon. I could add an assert I suppose to make sure this > > unhandled case never occurs. > Hi, > > POWER can also do 256kB, but that is a very uncommon configuration because > it requires the complete userspace to be rebuilt with 256k segment > alignment. > > For that reason I'd expect even larger pages to be very unlikely. > That's still considerably less than 2M so we are good here. Matt > Simon ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ CI.KUnit: success for Different page size handle in migrate layer (rev2) 2025-10-13 3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost 2025-10-13 3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost 2025-10-13 3:45 ` [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram Matthew Brost @ 2025-10-13 5:38 ` Patchwork 2025-10-13 6:23 ` ✓ Xe.CI.BAT: " Patchwork 2025-10-13 6:51 ` ✓ Xe.CI.Full: " Patchwork 4 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2025-10-13 5:38 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-xe == Series Details == Series: Different page size handle in migrate layer (rev2) URL : https://patchwork.freedesktop.org/series/155794/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig [05:37:16] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [05:37:20] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [05:37:51] Starting KUnit Kernel (1/1)... [05:37:51] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [05:37:51] ================== guc_buf (11 subtests) =================== [05:37:51] [PASSED] test_smallest [05:37:51] [PASSED] test_largest [05:37:51] [PASSED] test_granular [05:37:51] [PASSED] test_unique [05:37:51] [PASSED] test_overlap [05:37:51] [PASSED] test_reusable [05:37:51] [PASSED] test_too_big [05:37:51] [PASSED] test_flush [05:37:51] [PASSED] test_lookup [05:37:51] [PASSED] test_data [05:37:51] [PASSED] test_class [05:37:51] ===================== [PASSED] guc_buf ===================== [05:37:51] =================== guc_dbm (7 subtests) =================== [05:37:51] [PASSED] test_empty [05:37:51] [PASSED] test_default [05:37:51] ======================== test_size ======================== [05:37:51] [PASSED] 4 [05:37:51] [PASSED] 8 [05:37:51] [PASSED] 32 [05:37:51] [PASSED] 256 [05:37:51] ==================== [PASSED] test_size ==================== [05:37:51] ======================= test_reuse ======================== [05:37:51] [PASSED] 4 [05:37:51] [PASSED] 8 [05:37:51] [PASSED] 32 [05:37:51] [PASSED] 256 [05:37:51] =================== [PASSED] test_reuse ==================== [05:37:51] =================== test_range_overlap ==================== [05:37:51] [PASSED] 4 [05:37:51] [PASSED] 8 [05:37:51] [PASSED] 32 [05:37:51] [PASSED] 256 [05:37:51] =============== [PASSED] test_range_overlap ================ [05:37:51] =================== test_range_compact ==================== [05:37:51] [PASSED] 4 [05:37:51] [PASSED] 8 [05:37:51] [PASSED] 32 [05:37:51] [PASSED] 256 [05:37:51] =============== [PASSED] test_range_compact ================ [05:37:51] ==================== test_range_spare ===================== [05:37:51] [PASSED] 4 [05:37:51] [PASSED] 8 [05:37:51] [PASSED] 32 [05:37:51] [PASSED] 256 [05:37:51] ================ [PASSED] test_range_spare ================= [05:37:51] ===================== [PASSED] guc_dbm ===================== [05:37:51] =================== guc_idm (6 subtests) =================== [05:37:51] [PASSED] bad_init [05:37:51] [PASSED] no_init [05:37:51] [PASSED] init_fini [05:37:51] [PASSED] check_used [05:37:51] [PASSED] check_quota [05:37:51] [PASSED] check_all [05:37:51] ===================== [PASSED] guc_idm ===================== [05:37:51] ================== no_relay (3 subtests) =================== [05:37:51] [PASSED] xe_drops_guc2pf_if_not_ready [05:37:51] [PASSED] xe_drops_guc2vf_if_not_ready [05:37:51] [PASSED] xe_rejects_send_if_not_ready [05:37:51] ==================== [PASSED] no_relay ===================== [05:37:51] ================== pf_relay (14 subtests) ================== [05:37:51] [PASSED] pf_rejects_guc2pf_too_short [05:37:51] [PASSED] pf_rejects_guc2pf_too_long [05:37:51] [PASSED] pf_rejects_guc2pf_no_payload [05:37:51] [PASSED] pf_fails_no_payload [05:37:51] [PASSED] pf_fails_bad_origin [05:37:51] [PASSED] pf_fails_bad_type [05:37:51] [PASSED] pf_txn_reports_error [05:37:51] [PASSED] pf_txn_sends_pf2guc [05:37:51] [PASSED] pf_sends_pf2guc [05:37:51] [SKIPPED] pf_loopback_nop [05:37:51] [SKIPPED] pf_loopback_echo [05:37:51] [SKIPPED] pf_loopback_fail [05:37:51] [SKIPPED] pf_loopback_busy [05:37:51] [SKIPPED] pf_loopback_retry [05:37:51] ==================== [PASSED] pf_relay ===================== [05:37:51] ================== vf_relay (3 subtests) =================== [05:37:51] [PASSED] vf_rejects_guc2vf_too_short [05:37:51] [PASSED] vf_rejects_guc2vf_too_long [05:37:51] [PASSED] vf_rejects_guc2vf_no_payload [05:37:51] ==================== [PASSED] vf_relay ===================== [05:37:51] ===================== lmtt (1 subtest) ===================== [05:37:51] ======================== test_ops ========================= [05:37:51] [PASSED] 2-level [05:37:51] [PASSED] multi-level [05:37:51] ==================== [PASSED] test_ops ===================== [05:37:51] ====================== [PASSED] lmtt ======================= [05:37:51] ================= pf_service (11 subtests) ================= [05:37:51] [PASSED] pf_negotiate_any [05:37:51] [PASSED] pf_negotiate_base_match [05:37:51] [PASSED] pf_negotiate_base_newer [05:37:51] [PASSED] pf_negotiate_base_next [05:37:51] [SKIPPED] pf_negotiate_base_older [05:37:51] [PASSED] pf_negotiate_base_prev [05:37:51] [PASSED] pf_negotiate_latest_match [05:37:51] [PASSED] pf_negotiate_latest_newer [05:37:51] [PASSED] pf_negotiate_latest_next [05:37:51] [SKIPPED] pf_negotiate_latest_older [05:37:51] [SKIPPED] pf_negotiate_latest_prev [05:37:51] =================== [PASSED] pf_service ==================== [05:37:51] ================= xe_guc_g2g (2 subtests) ================== [05:37:51] ============== xe_live_guc_g2g_kunit_default ============== [05:37:51] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ========== [05:37:51] ============== xe_live_guc_g2g_kunit_allmem =============== [05:37:51] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ========== [05:37:51] =================== [SKIPPED] xe_guc_g2g =================== [05:37:51] =================== xe_mocs (2 subtests) =================== [05:37:51] ================ xe_live_mocs_kernel_kunit ================ [05:37:51] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============ [05:37:51] ================ xe_live_mocs_reset_kunit ================= [05:37:51] ============ [SKIPPED] xe_live_mocs_reset_kunit ============ [05:37:51] ==================== [SKIPPED] xe_mocs ===================== [05:37:51] ================= xe_migrate (2 subtests) ================== [05:37:51] ================= xe_migrate_sanity_kunit ================= [05:37:51] ============ [SKIPPED] xe_migrate_sanity_kunit ============= [05:37:51] ================== xe_validate_ccs_kunit ================== [05:37:51] ============= [SKIPPED] xe_validate_ccs_kunit ============== [05:37:51] =================== [SKIPPED] xe_migrate =================== [05:37:51] ================== xe_dma_buf (1 subtest) ================== [05:37:51] ==================== xe_dma_buf_kunit ===================== [05:37:51] ================ [SKIPPED] xe_dma_buf_kunit ================ [05:37:51] =================== [SKIPPED] xe_dma_buf =================== [05:37:51] ================= xe_bo_shrink (1 subtest) ================= [05:37:51] =================== xe_bo_shrink_kunit ==================== [05:37:51] =============== [SKIPPED] xe_bo_shrink_kunit =============== [05:37:51] ================== [SKIPPED] xe_bo_shrink ================== [05:37:51] ==================== xe_bo (2 subtests) ==================== [05:37:51] ================== xe_ccs_migrate_kunit =================== [05:37:51] ============== [SKIPPED] xe_ccs_migrate_kunit ============== [05:37:51] ==================== xe_bo_evict_kunit ==================== [05:37:51] =============== [SKIPPED] xe_bo_evict_kunit ================ [05:37:51] ===================== [SKIPPED] xe_bo ====================== [05:37:51] ==================== args (11 subtests) ==================== [05:37:51] [PASSED] count_args_test [05:37:51] [PASSED] call_args_example [05:37:51] [PASSED] call_args_test [05:37:51] [PASSED] drop_first_arg_example [05:37:51] [PASSED] drop_first_arg_test [05:37:51] [PASSED] first_arg_example [05:37:51] [PASSED] first_arg_test [05:37:51] [PASSED] last_arg_example [05:37:51] [PASSED] last_arg_test [05:37:51] [PASSED] pick_arg_example [05:37:51] [PASSED] sep_comma_example [05:37:51] ====================== [PASSED] args ======================= [05:37:51] =================== xe_pci (3 subtests) ==================== [05:37:51] ==================== check_graphics_ip ==================== [05:37:51] [PASSED] 12.00 Xe_LP [05:37:51] [PASSED] 12.10 Xe_LP+ [05:37:51] [PASSED] 12.55 Xe_HPG [05:37:51] [PASSED] 12.60 Xe_HPC [05:37:51] [PASSED] 12.70 Xe_LPG [05:37:51] [PASSED] 12.71 Xe_LPG [05:37:51] [PASSED] 12.74 Xe_LPG+ [05:37:51] [PASSED] 20.01 Xe2_HPG [05:37:51] [PASSED] 20.02 Xe2_HPG [05:37:51] [PASSED] 20.04 Xe2_LPG [05:37:51] [PASSED] 30.00 Xe3_LPG [05:37:51] [PASSED] 30.01 Xe3_LPG [05:37:51] [PASSED] 30.03 Xe3_LPG [05:37:51] ================ [PASSED] check_graphics_ip ================ [05:37:51] ===================== check_media_ip ====================== [05:37:51] [PASSED] 12.00 Xe_M [05:37:51] [PASSED] 12.55 Xe_HPM [05:37:51] [PASSED] 13.00 Xe_LPM+ [05:37:51] [PASSED] 13.01 Xe2_HPM [05:37:51] [PASSED] 20.00 Xe2_LPM [05:37:51] [PASSED] 30.00 Xe3_LPM [05:37:51] [PASSED] 30.02 Xe3_LPM [05:37:51] ================= [PASSED] check_media_ip ================== [05:37:51] ================= check_platform_gt_count ================= [05:37:51] [PASSED] 0x9A60 (TIGERLAKE) [05:37:51] [PASSED] 0x9A68 (TIGERLAKE) [05:37:51] [PASSED] 0x9A70 (TIGERLAKE) [05:37:51] [PASSED] 0x9A40 (TIGERLAKE) [05:37:51] [PASSED] 0x9A49 (TIGERLAKE) [05:37:51] [PASSED] 0x9A59 (TIGERLAKE) [05:37:51] [PASSED] 0x9A78 (TIGERLAKE) [05:37:51] [PASSED] 0x9AC0 (TIGERLAKE) [05:37:51] [PASSED] 0x9AC9 (TIGERLAKE) [05:37:51] [PASSED] 0x9AD9 (TIGERLAKE) [05:37:51] [PASSED] 0x9AF8 (TIGERLAKE) [05:37:51] [PASSED] 0x4C80 (ROCKETLAKE) [05:37:51] [PASSED] 0x4C8A (ROCKETLAKE) [05:37:51] [PASSED] 0x4C8B (ROCKETLAKE) [05:37:51] [PASSED] 0x4C8C (ROCKETLAKE) [05:37:51] [PASSED] 0x4C90 (ROCKETLAKE) [05:37:51] [PASSED] 0x4C9A (ROCKETLAKE) [05:37:51] [PASSED] 0x4680 (ALDERLAKE_S) [05:37:51] [PASSED] 0x4682 (ALDERLAKE_S) [05:37:51] [PASSED] 0x4688 (ALDERLAKE_S) [05:37:51] [PASSED] 0x468A (ALDERLAKE_S) [05:37:51] [PASSED] 0x468B (ALDERLAKE_S) [05:37:51] [PASSED] 0x4690 (ALDERLAKE_S) [05:37:51] [PASSED] 0x4692 (ALDERLAKE_S) [05:37:51] [PASSED] 0x4693 (ALDERLAKE_S) [05:37:51] [PASSED] 0x46A0 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46A1 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46A2 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46A3 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46A6 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46A8 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46AA (ALDERLAKE_P) [05:37:51] [PASSED] 0x462A (ALDERLAKE_P) [05:37:51] [PASSED] 0x4626 (ALDERLAKE_P) [05:37:51] [PASSED] 0x4628 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46B0 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46B1 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46B2 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46B3 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46C0 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46C1 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46C2 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46C3 (ALDERLAKE_P) [05:37:51] [PASSED] 0x46D0 (ALDERLAKE_N) [05:37:51] [PASSED] 0x46D1 (ALDERLAKE_N) [05:37:51] [PASSED] 0x46D2 (ALDERLAKE_N) [05:37:51] [PASSED] 0x46D3 (ALDERLAKE_N) [05:37:51] [PASSED] 0x46D4 (ALDERLAKE_N) [05:37:51] [PASSED] 0xA721 (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7A1 (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7A9 (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7AC (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7AD (ALDERLAKE_P) [05:37:51] [PASSED] 0xA720 (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7A0 (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7A8 (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7AA (ALDERLAKE_P) [05:37:51] [PASSED] 0xA7AB (ALDERLAKE_P) [05:37:51] [PASSED] 0xA780 (ALDERLAKE_S) [05:37:51] [PASSED] 0xA781 (ALDERLAKE_S) [05:37:51] [PASSED] 0xA782 (ALDERLAKE_S) [05:37:51] [PASSED] 0xA783 (ALDERLAKE_S) [05:37:51] [PASSED] 0xA788 (ALDERLAKE_S) [05:37:51] [PASSED] 0xA789 (ALDERLAKE_S) [05:37:51] [PASSED] 0xA78A (ALDERLAKE_S) [05:37:51] [PASSED] 0xA78B (ALDERLAKE_S) [05:37:51] [PASSED] 0x4905 (DG1) [05:37:51] [PASSED] 0x4906 (DG1) [05:37:51] [PASSED] 0x4907 (DG1) [05:37:51] [PASSED] 0x4908 (DG1) [05:37:51] [PASSED] 0x4909 (DG1) [05:37:51] [PASSED] 0x56C0 (DG2) [05:37:51] [PASSED] 0x56C2 (DG2) [05:37:51] [PASSED] 0x56C1 (DG2) [05:37:51] [PASSED] 0x7D51 (METEORLAKE) [05:37:51] [PASSED] 0x7DD1 (METEORLAKE) [05:37:51] [PASSED] 0x7D41 (METEORLAKE) [05:37:51] [PASSED] 0x7D67 (METEORLAKE) [05:37:51] [PASSED] 0xB640 (METEORLAKE) [05:37:51] [PASSED] 0x56A0 (DG2) [05:37:51] [PASSED] 0x56A1 (DG2) [05:37:51] [PASSED] 0x56A2 (DG2) [05:37:51] [PASSED] 0x56BE (DG2) [05:37:51] [PASSED] 0x56BF (DG2) [05:37:51] [PASSED] 0x5690 (DG2) [05:37:51] [PASSED] 0x5691 (DG2) [05:37:51] [PASSED] 0x5692 (DG2) [05:37:51] [PASSED] 0x56A5 (DG2) [05:37:51] [PASSED] 0x56A6 (DG2) [05:37:51] [PASSED] 0x56B0 (DG2) [05:37:51] [PASSED] 0x56B1 (DG2) [05:37:51] [PASSED] 0x56BA (DG2) [05:37:51] [PASSED] 0x56BB (DG2) [05:37:51] [PASSED] 0x56BC (DG2) [05:37:51] [PASSED] 0x56BD (DG2) [05:37:51] [PASSED] 0x5693 (DG2) [05:37:51] [PASSED] 0x5694 (DG2) [05:37:51] [PASSED] 0x5695 (DG2) [05:37:51] [PASSED] 0x56A3 (DG2) [05:37:51] [PASSED] 0x56A4 (DG2) [05:37:51] [PASSED] 0x56B2 (DG2) [05:37:51] [PASSED] 0x56B3 (DG2) [05:37:51] [PASSED] 0x5696 (DG2) [05:37:51] [PASSED] 0x5697 (DG2) [05:37:51] [PASSED] 0xB69 (PVC) [05:37:51] [PASSED] 0xB6E (PVC) [05:37:51] [PASSED] 0xBD4 (PVC) [05:37:51] [PASSED] 0xBD5 (PVC) [05:37:51] [PASSED] 0xBD6 (PVC) [05:37:51] [PASSED] 0xBD7 (PVC) [05:37:51] [PASSED] 0xBD8 (PVC) [05:37:51] [PASSED] 0xBD9 (PVC) [05:37:51] [PASSED] 0xBDA (PVC) [05:37:51] [PASSED] 0xBDB (PVC) [05:37:51] [PASSED] 0xBE0 (PVC) [05:37:51] [PASSED] 0xBE1 (PVC) [05:37:51] [PASSED] 0xBE5 (PVC) [05:37:51] [PASSED] 0x7D40 (METEORLAKE) [05:37:51] [PASSED] 0x7D45 (METEORLAKE) [05:37:51] [PASSED] 0x7D55 (METEORLAKE) [05:37:51] [PASSED] 0x7D60 (METEORLAKE) [05:37:51] [PASSED] 0x7DD5 (METEORLAKE) [05:37:51] [PASSED] 0x6420 (LUNARLAKE) [05:37:51] [PASSED] 0x64A0 (LUNARLAKE) [05:37:51] [PASSED] 0x64B0 (LUNARLAKE) [05:37:51] [PASSED] 0xE202 (BATTLEMAGE) [05:37:51] [PASSED] 0xE209 (BATTLEMAGE) [05:37:51] [PASSED] 0xE20B (BATTLEMAGE) [05:37:51] [PASSED] 0xE20C (BATTLEMAGE) [05:37:51] [PASSED] 0xE20D (BATTLEMAGE) [05:37:51] [PASSED] 0xE210 (BATTLEMAGE) [05:37:51] [PASSED] 0xE211 (BATTLEMAGE) [05:37:51] [PASSED] 0xE212 (BATTLEMAGE) [05:37:51] [PASSED] 0xE216 (BATTLEMAGE) [05:37:51] [PASSED] 0xE220 (BATTLEMAGE) [05:37:51] [PASSED] 0xE221 (BATTLEMAGE) [05:37:51] [PASSED] 0xE222 (BATTLEMAGE) [05:37:51] [PASSED] 0xE223 (BATTLEMAGE) [05:37:51] [PASSED] 0xB080 (PANTHERLAKE) [05:37:51] [PASSED] 0xB081 (PANTHERLAKE) [05:37:51] [PASSED] 0xB082 (PANTHERLAKE) [05:37:51] [PASSED] 0xB083 (PANTHERLAKE) [05:37:51] [PASSED] 0xB084 (PANTHERLAKE) [05:37:51] [PASSED] 0xB085 (PANTHERLAKE) [05:37:51] [PASSED] 0xB086 (PANTHERLAKE) [05:37:51] [PASSED] 0xB087 (PANTHERLAKE) [05:37:51] [PASSED] 0xB08F (PANTHERLAKE) [05:37:51] [PASSED] 0xB090 (PANTHERLAKE) [05:37:51] [PASSED] 0xB0A0 (PANTHERLAKE) [05:37:51] [PASSED] 0xB0B0 (PANTHERLAKE) [05:37:51] [PASSED] 0xFD80 (PANTHERLAKE) [05:37:51] [PASSED] 0xFD81 (PANTHERLAKE) [05:37:51] ============= [PASSED] check_platform_gt_count ============= [05:37:51] ===================== [PASSED] xe_pci ====================== [05:37:51] =================== xe_rtp (2 subtests) ==================== [05:37:51] =============== xe_rtp_process_to_sr_tests ================ [05:37:51] [PASSED] coalesce-same-reg [05:37:51] [PASSED] no-match-no-add [05:37:51] [PASSED] match-or [05:37:51] [PASSED] match-or-xfail [05:37:51] [PASSED] no-match-no-add-multiple-rules [05:37:51] [PASSED] two-regs-two-entries [05:37:51] [PASSED] clr-one-set-other [05:37:51] [PASSED] set-field [05:37:51] [PASSED] conflict-duplicate [05:37:51] [PASSED] conflict-not-disjoint [05:37:51] [PASSED] conflict-reg-type [05:37:51] =========== [PASSED] xe_rtp_process_to_sr_tests ============ [05:37:51] ================== xe_rtp_process_tests =================== [05:37:51] [PASSED] active1 [05:37:51] [PASSED] active2 [05:37:51] [PASSED] active-inactive [05:37:51] [PASSED] inactive-active [05:37:51] [PASSED] inactive-1st_or_active-inactive [05:37:51] [PASSED] inactive-2nd_or_active-inactive [05:37:51] [PASSED] inactive-last_or_active-inactive [05:37:51] [PASSED] inactive-no_or_active-inactive [05:37:51] ============== [PASSED] xe_rtp_process_tests =============== [05:37:51] ===================== [PASSED] xe_rtp ====================== [05:37:51] ==================== xe_wa (1 subtest) ===================== [05:37:51] ======================== xe_wa_gt ========================= [05:37:51] [PASSED] TIGERLAKE B0 [05:37:51] [PASSED] DG1 A0 [05:37:51] [PASSED] DG1 B0 [05:37:51] [PASSED] ALDERLAKE_S A0 [05:37:51] [PASSED] ALDERLAKE_S B0 stty: 'standard input': Inappropriate ioctl for device [05:37:51] [PASSED] ALDERLAKE_S C0 [05:37:51] [PASSED] ALDERLAKE_S D0 [05:37:51] [PASSED] ALDERLAKE_P A0 [05:37:51] [PASSED] ALDERLAKE_P B0 [05:37:51] [PASSED] ALDERLAKE_P C0 [05:37:51] [PASSED] ALDERLAKE_S RPLS D0 [05:37:51] [PASSED] ALDERLAKE_P RPLU E0 [05:37:51] [PASSED] DG2 G10 C0 [05:37:51] [PASSED] DG2 G11 B1 [05:37:51] [PASSED] DG2 G12 A1 [05:37:51] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0 [05:37:51] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0 [05:37:51] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0 [05:37:51] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0 [05:37:51] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0 [05:37:51] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1 [05:37:51] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0 [05:37:51] ==================== [PASSED] xe_wa_gt ===================== [05:37:51] ====================== [PASSED] xe_wa ====================== [05:37:51] ============================================================ [05:37:51] Testing complete. Ran 306 tests: passed: 288, skipped: 18 [05:37:51] Elapsed time: 34.936s total, 4.272s configuring, 30.297s building, 0.323s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [05:37:51] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [05:37:53] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [05:38:17] Starting KUnit Kernel (1/1)... [05:38:17] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [05:38:17] ============ drm_test_pick_cmdline (2 subtests) ============ [05:38:17] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [05:38:17] =============== drm_test_pick_cmdline_named =============== [05:38:17] [PASSED] NTSC [05:38:17] [PASSED] NTSC-J [05:38:17] [PASSED] PAL [05:38:17] [PASSED] PAL-M [05:38:17] =========== [PASSED] drm_test_pick_cmdline_named =========== [05:38:17] ============== [PASSED] drm_test_pick_cmdline ============== [05:38:17] == drm_test_atomic_get_connector_for_encoder (1 subtest) === [05:38:17] [PASSED] drm_test_drm_atomic_get_connector_for_encoder [05:38:17] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ==== [05:38:17] =========== drm_validate_clone_mode (2 subtests) =========== [05:38:17] ============== drm_test_check_in_clone_mode =============== [05:38:17] [PASSED] in_clone_mode [05:38:17] [PASSED] not_in_clone_mode [05:38:17] ========== [PASSED] drm_test_check_in_clone_mode =========== [05:38:17] =============== drm_test_check_valid_clones =============== [05:38:17] [PASSED] not_in_clone_mode [05:38:17] [PASSED] valid_clone [05:38:17] [PASSED] invalid_clone [05:38:17] =========== [PASSED] drm_test_check_valid_clones =========== [05:38:17] ============= [PASSED] drm_validate_clone_mode ============= [05:38:17] ============= drm_validate_modeset (1 subtest) ============= [05:38:17] [PASSED] drm_test_check_connector_changed_modeset [05:38:17] ============== [PASSED] drm_validate_modeset =============== [05:38:17] ====== drm_test_bridge_get_current_state (2 subtests) ====== [05:38:17] [PASSED] drm_test_drm_bridge_get_current_state_atomic [05:38:17] [PASSED] drm_test_drm_bridge_get_current_state_legacy [05:38:17] ======== [PASSED] drm_test_bridge_get_current_state ======== [05:38:17] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ====== [05:38:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic [05:38:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled [05:38:17] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy [05:38:17] ======== [PASSED] drm_test_bridge_helper_reset_crtc ======== [05:38:17] ============== drm_bridge_alloc (2 subtests) =============== [05:38:17] [PASSED] drm_test_drm_bridge_alloc_basic [05:38:17] [PASSED] drm_test_drm_bridge_alloc_get_put [05:38:17] ================ [PASSED] drm_bridge_alloc ================= [05:38:17] ================== drm_buddy (8 subtests) ================== [05:38:17] [PASSED] drm_test_buddy_alloc_limit [05:38:17] [PASSED] drm_test_buddy_alloc_optimistic [05:38:17] [PASSED] drm_test_buddy_alloc_pessimistic [05:38:17] [PASSED] drm_test_buddy_alloc_pathological [05:38:17] [PASSED] drm_test_buddy_alloc_contiguous [05:38:17] [PASSED] drm_test_buddy_alloc_clear [05:38:18] [PASSED] drm_test_buddy_alloc_range_bias [05:38:18] [PASSED] drm_test_buddy_fragmentation_performance [05:38:18] ==================== [PASSED] drm_buddy ==================== [05:38:18] ============= drm_cmdline_parser (40 subtests) ============= [05:38:18] [PASSED] drm_test_cmdline_force_d_only [05:38:18] [PASSED] drm_test_cmdline_force_D_only_dvi [05:38:18] [PASSED] drm_test_cmdline_force_D_only_hdmi [05:38:18] [PASSED] drm_test_cmdline_force_D_only_not_digital [05:38:18] [PASSED] drm_test_cmdline_force_e_only [05:38:18] [PASSED] drm_test_cmdline_res [05:38:18] [PASSED] drm_test_cmdline_res_vesa [05:38:18] [PASSED] drm_test_cmdline_res_vesa_rblank [05:38:18] [PASSED] drm_test_cmdline_res_rblank [05:38:18] [PASSED] drm_test_cmdline_res_bpp [05:38:18] [PASSED] drm_test_cmdline_res_refresh [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [05:38:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [05:38:18] [PASSED] drm_test_cmdline_res_margins_force_on [05:38:18] [PASSED] drm_test_cmdline_res_vesa_margins [05:38:18] [PASSED] drm_test_cmdline_name [05:38:18] [PASSED] drm_test_cmdline_name_bpp [05:38:18] [PASSED] drm_test_cmdline_name_option [05:38:18] [PASSED] drm_test_cmdline_name_bpp_option [05:38:18] [PASSED] drm_test_cmdline_rotate_0 [05:38:18] [PASSED] drm_test_cmdline_rotate_90 [05:38:18] [PASSED] drm_test_cmdline_rotate_180 [05:38:18] [PASSED] drm_test_cmdline_rotate_270 [05:38:18] [PASSED] drm_test_cmdline_hmirror [05:38:18] [PASSED] drm_test_cmdline_vmirror [05:38:18] [PASSED] drm_test_cmdline_margin_options [05:38:18] [PASSED] drm_test_cmdline_multiple_options [05:38:18] [PASSED] drm_test_cmdline_bpp_extra_and_option [05:38:18] [PASSED] drm_test_cmdline_extra_and_option [05:38:18] [PASSED] drm_test_cmdline_freestanding_options [05:38:18] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [05:38:18] [PASSED] drm_test_cmdline_panel_orientation [05:38:18] ================ drm_test_cmdline_invalid ================= [05:38:18] [PASSED] margin_only [05:38:18] [PASSED] interlace_only [05:38:18] [PASSED] res_missing_x [05:38:18] [PASSED] res_missing_y [05:38:18] [PASSED] res_bad_y [05:38:18] [PASSED] res_missing_y_bpp [05:38:18] [PASSED] res_bad_bpp [05:38:18] [PASSED] res_bad_refresh [05:38:18] [PASSED] res_bpp_refresh_force_on_off [05:38:18] [PASSED] res_invalid_mode [05:38:18] [PASSED] res_bpp_wrong_place_mode [05:38:18] [PASSED] name_bpp_refresh [05:38:18] [PASSED] name_refresh [05:38:18] [PASSED] name_refresh_wrong_mode [05:38:18] [PASSED] name_refresh_invalid_mode [05:38:18] [PASSED] rotate_multiple [05:38:18] [PASSED] rotate_invalid_val [05:38:18] [PASSED] rotate_truncated [05:38:18] [PASSED] invalid_option [05:38:18] [PASSED] invalid_tv_option [05:38:18] [PASSED] truncated_tv_option [05:38:18] ============ [PASSED] drm_test_cmdline_invalid ============= [05:38:18] =============== drm_test_cmdline_tv_options =============== [05:38:18] [PASSED] NTSC [05:38:18] [PASSED] NTSC_443 [05:38:18] [PASSED] NTSC_J [05:38:18] [PASSED] PAL [05:38:18] [PASSED] PAL_M [05:38:18] [PASSED] PAL_N [05:38:18] [PASSED] SECAM [05:38:18] [PASSED] MONO_525 [05:38:18] [PASSED] MONO_625 [05:38:18] =========== [PASSED] drm_test_cmdline_tv_options =========== [05:38:18] =============== [PASSED] drm_cmdline_parser ================ [05:38:18] ========== drmm_connector_hdmi_init (20 subtests) ========== [05:38:18] [PASSED] drm_test_connector_hdmi_init_valid [05:38:18] [PASSED] drm_test_connector_hdmi_init_bpc_8 [05:38:18] [PASSED] drm_test_connector_hdmi_init_bpc_10 [05:38:18] [PASSED] drm_test_connector_hdmi_init_bpc_12 [05:38:18] [PASSED] drm_test_connector_hdmi_init_bpc_invalid [05:38:18] [PASSED] drm_test_connector_hdmi_init_bpc_null [05:38:18] [PASSED] drm_test_connector_hdmi_init_formats_empty [05:38:18] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb [05:38:18] === drm_test_connector_hdmi_init_formats_yuv420_allowed === [05:38:18] [PASSED] supported_formats=0x9 yuv420_allowed=1 [05:38:18] [PASSED] supported_formats=0x9 yuv420_allowed=0 [05:38:18] [PASSED] supported_formats=0x3 yuv420_allowed=1 [05:38:18] [PASSED] supported_formats=0x3 yuv420_allowed=0 [05:38:18] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed === [05:38:18] [PASSED] drm_test_connector_hdmi_init_null_ddc [05:38:18] [PASSED] drm_test_connector_hdmi_init_null_product [05:38:18] [PASSED] drm_test_connector_hdmi_init_null_vendor [05:38:18] [PASSED] drm_test_connector_hdmi_init_product_length_exact [05:38:18] [PASSED] drm_test_connector_hdmi_init_product_length_too_long [05:38:18] [PASSED] drm_test_connector_hdmi_init_product_valid [05:38:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact [05:38:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long [05:38:18] [PASSED] drm_test_connector_hdmi_init_vendor_valid [05:38:18] ========= drm_test_connector_hdmi_init_type_valid ========= [05:38:18] [PASSED] HDMI-A [05:38:18] [PASSED] HDMI-B [05:38:18] ===== [PASSED] drm_test_connector_hdmi_init_type_valid ===== [05:38:18] ======== drm_test_connector_hdmi_init_type_invalid ======== [05:38:18] [PASSED] Unknown [05:38:18] [PASSED] VGA [05:38:18] [PASSED] DVI-I [05:38:18] [PASSED] DVI-D [05:38:18] [PASSED] DVI-A [05:38:18] [PASSED] Composite [05:38:18] [PASSED] SVIDEO [05:38:18] [PASSED] LVDS [05:38:18] [PASSED] Component [05:38:18] [PASSED] DIN [05:38:18] [PASSED] DP [05:38:18] [PASSED] TV [05:38:18] [PASSED] eDP [05:38:18] [PASSED] Virtual [05:38:18] [PASSED] DSI [05:38:18] [PASSED] DPI [05:38:18] [PASSED] Writeback [05:38:18] [PASSED] SPI [05:38:18] [PASSED] USB [05:38:18] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ==== [05:38:18] ============ [PASSED] drmm_connector_hdmi_init ============= [05:38:18] ============= drmm_connector_init (3 subtests) ============= [05:38:18] [PASSED] drm_test_drmm_connector_init [05:38:18] [PASSED] drm_test_drmm_connector_init_null_ddc [05:38:18] ========= drm_test_drmm_connector_init_type_valid ========= [05:38:18] [PASSED] Unknown [05:38:18] [PASSED] VGA [05:38:18] [PASSED] DVI-I [05:38:18] [PASSED] DVI-D [05:38:18] [PASSED] DVI-A [05:38:18] [PASSED] Composite [05:38:18] [PASSED] SVIDEO [05:38:18] [PASSED] LVDS [05:38:18] [PASSED] Component [05:38:18] [PASSED] DIN [05:38:18] [PASSED] DP [05:38:18] [PASSED] HDMI-A [05:38:18] [PASSED] HDMI-B [05:38:18] [PASSED] TV [05:38:18] [PASSED] eDP [05:38:18] [PASSED] Virtual [05:38:18] [PASSED] DSI [05:38:18] [PASSED] DPI [05:38:18] [PASSED] Writeback [05:38:18] [PASSED] SPI [05:38:18] [PASSED] USB [05:38:18] ===== [PASSED] drm_test_drmm_connector_init_type_valid ===== [05:38:18] =============== [PASSED] drmm_connector_init =============== [05:38:18] ========= drm_connector_dynamic_init (6 subtests) ========== [05:38:18] [PASSED] drm_test_drm_connector_dynamic_init [05:38:18] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc [05:38:18] [PASSED] drm_test_drm_connector_dynamic_init_not_added [05:38:18] [PASSED] drm_test_drm_connector_dynamic_init_properties [05:38:18] ===== drm_test_drm_connector_dynamic_init_type_valid ====== [05:38:18] [PASSED] Unknown [05:38:18] [PASSED] VGA [05:38:18] [PASSED] DVI-I [05:38:18] [PASSED] DVI-D [05:38:18] [PASSED] DVI-A [05:38:18] [PASSED] Composite [05:38:18] [PASSED] SVIDEO [05:38:18] [PASSED] LVDS [05:38:18] [PASSED] Component [05:38:18] [PASSED] DIN [05:38:18] [PASSED] DP [05:38:18] [PASSED] HDMI-A [05:38:18] [PASSED] HDMI-B [05:38:18] [PASSED] TV [05:38:18] [PASSED] eDP [05:38:18] [PASSED] Virtual [05:38:18] [PASSED] DSI [05:38:18] [PASSED] DPI [05:38:18] [PASSED] Writeback [05:38:18] [PASSED] SPI [05:38:18] [PASSED] USB [05:38:18] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid == [05:38:18] ======== drm_test_drm_connector_dynamic_init_name ========= [05:38:18] [PASSED] Unknown [05:38:18] [PASSED] VGA [05:38:18] [PASSED] DVI-I [05:38:18] [PASSED] DVI-D [05:38:18] [PASSED] DVI-A [05:38:18] [PASSED] Composite [05:38:18] [PASSED] SVIDEO [05:38:18] [PASSED] LVDS [05:38:18] [PASSED] Component [05:38:18] [PASSED] DIN [05:38:18] [PASSED] DP [05:38:18] [PASSED] HDMI-A [05:38:18] [PASSED] HDMI-B [05:38:18] [PASSED] TV [05:38:18] [PASSED] eDP [05:38:18] [PASSED] Virtual [05:38:18] [PASSED] DSI [05:38:18] [PASSED] DPI [05:38:18] [PASSED] Writeback [05:38:18] [PASSED] SPI [05:38:18] [PASSED] USB [05:38:18] ==== [PASSED] drm_test_drm_connector_dynamic_init_name ===== [05:38:18] =========== [PASSED] drm_connector_dynamic_init ============ [05:38:18] ==== drm_connector_dynamic_register_early (4 subtests) ===== [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_early_defer [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object [05:38:18] ====== [PASSED] drm_connector_dynamic_register_early ======= [05:38:18] ======= drm_connector_dynamic_register (7 subtests) ======== [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_on_list [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_no_defer [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_no_init [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_mode_object [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name [05:38:18] [PASSED] drm_test_drm_connector_dynamic_register_debugfs [05:38:18] ========= [PASSED] drm_connector_dynamic_register ========== [05:38:18] = drm_connector_attach_broadcast_rgb_property (2 subtests) = [05:38:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property [05:38:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector [05:38:18] === [PASSED] drm_connector_attach_broadcast_rgb_property === [05:38:18] ========== drm_get_tv_mode_from_name (2 subtests) ========== [05:38:18] ========== drm_test_get_tv_mode_from_name_valid =========== [05:38:18] [PASSED] NTSC [05:38:18] [PASSED] NTSC-443 [05:38:18] [PASSED] NTSC-J [05:38:18] [PASSED] PAL [05:38:18] [PASSED] PAL-M [05:38:18] [PASSED] PAL-N [05:38:18] [PASSED] SECAM [05:38:18] [PASSED] Mono [05:38:18] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [05:38:18] [PASSED] drm_test_get_tv_mode_from_name_truncated [05:38:18] ============ [PASSED] drm_get_tv_mode_from_name ============ [05:38:18] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) = [05:38:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb [05:38:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc [05:38:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1 [05:38:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc [05:38:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1 [05:38:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double [05:38:18] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid = [05:38:18] [PASSED] VIC 96 [05:38:18] [PASSED] VIC 97 [05:38:18] [PASSED] VIC 101 [05:38:18] [PASSED] VIC 102 [05:38:18] [PASSED] VIC 106 [05:38:18] [PASSED] VIC 107 [05:38:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid === [05:38:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc [05:38:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc [05:38:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc [05:38:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc [05:38:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc [05:38:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ==== [05:38:18] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) == [05:38:18] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ==== [05:38:18] [PASSED] Automatic [05:38:18] [PASSED] Full [05:38:18] [PASSED] Limited 16:235 [05:38:18] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name === [05:38:18] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid [05:38:18] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ==== [05:38:18] == drm_hdmi_connector_get_output_format_name (2 subtests) == [05:38:18] === drm_test_drm_hdmi_connector_get_output_format_name ==== [05:38:18] [PASSED] RGB [05:38:18] [PASSED] YUV 4:2:0 [05:38:18] [PASSED] YUV 4:2:2 [05:38:18] [PASSED] YUV 4:4:4 [05:38:18] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name === [05:38:18] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid [05:38:18] ==== [PASSED] drm_hdmi_connector_get_output_format_name ==== [05:38:18] ============= drm_damage_helper (21 subtests) ============== [05:38:18] [PASSED] drm_test_damage_iter_no_damage [05:38:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src [05:38:18] [PASSED] drm_test_damage_iter_no_damage_src_moved [05:38:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [05:38:18] [PASSED] drm_test_damage_iter_no_damage_not_visible [05:38:18] [PASSED] drm_test_damage_iter_no_damage_no_crtc [05:38:18] [PASSED] drm_test_damage_iter_no_damage_no_fb [05:38:18] [PASSED] drm_test_damage_iter_simple_damage [05:38:18] [PASSED] drm_test_damage_iter_single_damage [05:38:18] [PASSED] drm_test_damage_iter_single_damage_intersect_src [05:38:18] [PASSED] drm_test_damage_iter_single_damage_outside_src [05:38:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src [05:38:18] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [05:38:18] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [05:38:18] [PASSED] drm_test_damage_iter_single_damage_src_moved [05:38:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [05:38:18] [PASSED] drm_test_damage_iter_damage [05:38:18] [PASSED] drm_test_damage_iter_damage_one_intersect [05:38:18] [PASSED] drm_test_damage_iter_damage_one_outside [05:38:18] [PASSED] drm_test_damage_iter_damage_src_moved [05:38:18] [PASSED] drm_test_damage_iter_damage_not_visible [05:38:18] ================ [PASSED] drm_damage_helper ================ [05:38:18] ============== drm_dp_mst_helper (3 subtests) ============== [05:38:18] ============== drm_test_dp_mst_calc_pbn_mode ============== [05:38:18] [PASSED] Clock 154000 BPP 30 DSC disabled [05:38:18] [PASSED] Clock 234000 BPP 30 DSC disabled [05:38:18] [PASSED] Clock 297000 BPP 24 DSC disabled [05:38:18] [PASSED] Clock 332880 BPP 24 DSC enabled [05:38:18] [PASSED] Clock 324540 BPP 24 DSC enabled [05:38:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [05:38:18] ============== drm_test_dp_mst_calc_pbn_div =============== [05:38:18] [PASSED] Link rate 2000000 lane count 4 [05:38:18] [PASSED] Link rate 2000000 lane count 2 [05:38:18] [PASSED] Link rate 2000000 lane count 1 [05:38:18] [PASSED] Link rate 1350000 lane count 4 [05:38:18] [PASSED] Link rate 1350000 lane count 2 [05:38:18] [PASSED] Link rate 1350000 lane count 1 [05:38:18] [PASSED] Link rate 1000000 lane count 4 [05:38:18] [PASSED] Link rate 1000000 lane count 2 [05:38:18] [PASSED] Link rate 1000000 lane count 1 [05:38:18] [PASSED] Link rate 810000 lane count 4 [05:38:18] [PASSED] Link rate 810000 lane count 2 [05:38:18] [PASSED] Link rate 810000 lane count 1 [05:38:18] [PASSED] Link rate 540000 lane count 4 [05:38:18] [PASSED] Link rate 540000 lane count 2 [05:38:18] [PASSED] Link rate 540000 lane count 1 [05:38:18] [PASSED] Link rate 270000 lane count 4 [05:38:18] [PASSED] Link rate 270000 lane count 2 [05:38:18] [PASSED] Link rate 270000 lane count 1 [05:38:18] [PASSED] Link rate 162000 lane count 4 [05:38:18] [PASSED] Link rate 162000 lane count 2 [05:38:18] [PASSED] Link rate 162000 lane count 1 [05:38:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_div =========== [05:38:18] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [05:38:18] [PASSED] DP_ENUM_PATH_RESOURCES with port number [05:38:18] [PASSED] DP_POWER_UP_PHY with port number [05:38:18] [PASSED] DP_POWER_DOWN_PHY with port number [05:38:18] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [05:38:18] [PASSED] DP_ALLOCATE_PAYLOAD with port number [05:38:18] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [05:38:18] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [05:38:18] [PASSED] DP_QUERY_PAYLOAD with port number [05:38:18] [PASSED] DP_QUERY_PAYLOAD with VCPI [05:38:18] [PASSED] DP_REMOTE_DPCD_READ with port number [05:38:18] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [05:38:18] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [05:38:18] [PASSED] DP_REMOTE_DPCD_WRITE with port number [05:38:18] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [05:38:18] [PASSED] DP_REMOTE_DPCD_WRITE with data array [05:38:18] [PASSED] DP_REMOTE_I2C_READ with port number [05:38:18] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [05:38:18] [PASSED] DP_REMOTE_I2C_READ with transactions array [05:38:18] [PASSED] DP_REMOTE_I2C_WRITE with port number [05:38:18] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [05:38:18] [PASSED] DP_REMOTE_I2C_WRITE with data array [05:38:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [05:38:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [05:38:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [05:38:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [05:38:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [05:38:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [05:38:18] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [05:38:18] ================ [PASSED] drm_dp_mst_helper ================ [05:38:18] ================== drm_exec (7 subtests) =================== [05:38:18] [PASSED] sanitycheck [05:38:18] [PASSED] test_lock [05:38:18] [PASSED] test_lock_unlock [05:38:18] [PASSED] test_duplicates [05:38:18] [PASSED] test_prepare [05:38:18] [PASSED] test_prepare_array [05:38:18] [PASSED] test_multiple_loops [05:38:18] ==================== [PASSED] drm_exec ===================== [05:38:18] =========== drm_format_helper_test (17 subtests) =========== [05:38:18] ============== drm_test_fb_xrgb8888_to_gray8 ============== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [05:38:18] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [05:38:18] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [05:38:18] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [05:38:18] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [05:38:18] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [05:38:18] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [05:38:18] ============= drm_test_fb_xrgb8888_to_bgr888 ============== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ========== [05:38:18] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [05:38:18] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [05:38:18] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [05:38:18] ============== drm_test_fb_xrgb8888_to_mono =============== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [05:38:18] ==================== drm_test_fb_swab ===================== [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ================ [PASSED] drm_test_fb_swab ================= [05:38:18] ============ drm_test_fb_xrgb8888_to_xbgr8888 ============= [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 ========= [05:38:18] ============ drm_test_fb_xrgb8888_to_abgr8888 ============= [05:38:18] [PASSED] single_pixel_source_buffer [05:38:18] [PASSED] single_pixel_clip_rectangle [05:38:18] [PASSED] well_known_colors [05:38:18] [PASSED] destination_pitch [05:38:18] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 ========= [05:38:18] ================= drm_test_fb_clip_offset ================= [05:38:18] [PASSED] pass through [05:38:18] [PASSED] horizontal offset [05:38:18] [PASSED] vertical offset [05:38:18] [PASSED] horizontal and vertical offset [05:38:18] [PASSED] horizontal offset (custom pitch) [05:38:18] [PASSED] vertical offset (custom pitch) [05:38:18] [PASSED] horizontal and vertical offset (custom pitch) [05:38:18] ============= [PASSED] drm_test_fb_clip_offset ============= [05:38:18] =================== drm_test_fb_memcpy ==================== [05:38:18] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258) [05:38:18] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258) [05:38:18] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559) [05:38:18] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258) [05:38:18] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258) [05:38:18] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559) [05:38:18] [PASSED] well_known_colors: XB24 little-endian (0x34324258) [05:38:18] [PASSED] well_known_colors: XRA8 little-endian (0x38415258) [05:38:18] [PASSED] well_known_colors: YU24 little-endian (0x34325559) [05:38:18] [PASSED] destination_pitch: XB24 little-endian (0x34324258) [05:38:18] [PASSED] destination_pitch: XRA8 little-endian (0x38415258) [05:38:18] [PASSED] destination_pitch: YU24 little-endian (0x34325559) [05:38:18] =============== [PASSED] drm_test_fb_memcpy ================ [05:38:18] ============= [PASSED] drm_format_helper_test ============== [05:38:18] ================= drm_format (18 subtests) ================= [05:38:18] [PASSED] drm_test_format_block_width_invalid [05:38:18] [PASSED] drm_test_format_block_width_one_plane [05:38:18] [PASSED] drm_test_format_block_width_two_plane [05:38:18] [PASSED] drm_test_format_block_width_three_plane [05:38:18] [PASSED] drm_test_format_block_width_tiled [05:38:18] [PASSED] drm_test_format_block_height_invalid [05:38:18] [PASSED] drm_test_format_block_height_one_plane [05:38:18] [PASSED] drm_test_format_block_height_two_plane [05:38:18] [PASSED] drm_test_format_block_height_three_plane [05:38:18] [PASSED] drm_test_format_block_height_tiled [05:38:18] [PASSED] drm_test_format_min_pitch_invalid [05:38:18] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [05:38:18] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [05:38:18] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [05:38:18] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [05:38:18] [PASSED] drm_test_format_min_pitch_two_plane [05:38:18] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [05:38:18] [PASSED] drm_test_format_min_pitch_tiled [05:38:18] =================== [PASSED] drm_format ==================== [05:38:18] ============== drm_framebuffer (10 subtests) =============== [05:38:18] ========== drm_test_framebuffer_check_src_coords ========== [05:38:18] [PASSED] Success: source fits into fb [05:38:18] [PASSED] Fail: overflowing fb with x-axis coordinate [05:38:18] [PASSED] Fail: overflowing fb with y-axis coordinate [05:38:18] [PASSED] Fail: overflowing fb with source width [05:38:18] [PASSED] Fail: overflowing fb with source height [05:38:18] ====== [PASSED] drm_test_framebuffer_check_src_coords ====== [05:38:18] [PASSED] drm_test_framebuffer_cleanup [05:38:18] =============== drm_test_framebuffer_create =============== [05:38:18] [PASSED] ABGR8888 normal sizes [05:38:18] [PASSED] ABGR8888 max sizes [05:38:18] [PASSED] ABGR8888 pitch greater than min required [05:38:18] [PASSED] ABGR8888 pitch less than min required [05:38:18] [PASSED] ABGR8888 Invalid width [05:38:18] [PASSED] ABGR8888 Invalid buffer handle [05:38:18] [PASSED] No pixel format [05:38:18] [PASSED] ABGR8888 Width 0 [05:38:18] [PASSED] ABGR8888 Height 0 [05:38:18] [PASSED] ABGR8888 Out of bound height * pitch combination [05:38:18] [PASSED] ABGR8888 Large buffer offset [05:38:18] [PASSED] ABGR8888 Buffer offset for inexistent plane [05:38:18] [PASSED] ABGR8888 Invalid flag [05:38:18] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [05:38:18] [PASSED] ABGR8888 Valid buffer modifier [05:38:18] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [05:38:18] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] NV12 Normal sizes [05:38:18] [PASSED] NV12 Max sizes [05:38:18] [PASSED] NV12 Invalid pitch [05:38:18] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [05:38:18] [PASSED] NV12 different modifier per-plane [05:38:18] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [05:38:18] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] NV12 Modifier for inexistent plane [05:38:18] [PASSED] NV12 Handle for inexistent plane [05:38:18] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [05:38:18] [PASSED] YVU420 Normal sizes [05:38:18] [PASSED] YVU420 Max sizes [05:38:18] [PASSED] YVU420 Invalid pitch [05:38:18] [PASSED] YVU420 Different pitches [05:38:18] [PASSED] YVU420 Different buffer offsets/pitches [05:38:18] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [05:38:18] [PASSED] YVU420 Valid modifier [05:38:18] [PASSED] YVU420 Different modifiers per plane [05:38:18] [PASSED] YVU420 Modifier for inexistent plane [05:38:18] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR) [05:38:18] [PASSED] X0L2 Normal sizes [05:38:18] [PASSED] X0L2 Max sizes [05:38:18] [PASSED] X0L2 Invalid pitch [05:38:18] [PASSED] X0L2 Pitch greater than minimum required [05:38:18] [PASSED] X0L2 Handle for inexistent plane [05:38:18] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [05:38:18] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [05:38:18] [PASSED] X0L2 Valid modifier [05:38:18] [PASSED] X0L2 Modifier for inexistent plane [05:38:18] =========== [PASSED] drm_test_framebuffer_create =========== [05:38:18] [PASSED] drm_test_framebuffer_free [05:38:18] [PASSED] drm_test_framebuffer_init [05:38:18] [PASSED] drm_test_framebuffer_init_bad_format [05:38:18] [PASSED] drm_test_framebuffer_init_dev_mismatch [05:38:18] [PASSED] drm_test_framebuffer_lookup [05:38:18] [PASSED] drm_test_framebuffer_lookup_inexistent [05:38:18] [PASSED] drm_test_framebuffer_modifiers_not_supported [05:38:18] ================= [PASSED] drm_framebuffer ================= [05:38:18] ================ drm_gem_shmem (8 subtests) ================ [05:38:18] [PASSED] drm_gem_shmem_test_obj_create [05:38:18] [PASSED] drm_gem_shmem_test_obj_create_private [05:38:18] [PASSED] drm_gem_shmem_test_pin_pages [05:38:18] [PASSED] drm_gem_shmem_test_vmap [05:38:18] [PASSED] drm_gem_shmem_test_get_pages_sgt [05:38:18] [PASSED] drm_gem_shmem_test_get_sg_table [05:38:18] [PASSED] drm_gem_shmem_test_madvise [05:38:18] [PASSED] drm_gem_shmem_test_purge [05:38:18] ================== [PASSED] drm_gem_shmem ================== [05:38:18] === drm_atomic_helper_connector_hdmi_check (27 subtests) === [05:38:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode [05:38:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1 [05:38:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode [05:38:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1 [05:38:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode [05:38:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1 [05:38:18] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 ======= [05:38:18] [PASSED] Automatic [05:38:18] [PASSED] Full [05:38:18] [PASSED] Limited 16:235 [05:38:18] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 === [05:38:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed [05:38:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed [05:38:18] [PASSED] drm_test_check_disable_connector [05:38:18] [PASSED] drm_test_check_hdmi_funcs_reject_rate [05:38:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb [05:38:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420 [05:38:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422 [05:38:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420 [05:38:18] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420 [05:38:18] [PASSED] drm_test_check_output_bpc_crtc_mode_changed [05:38:18] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed [05:38:18] [PASSED] drm_test_check_output_bpc_dvi [05:38:18] [PASSED] drm_test_check_output_bpc_format_vic_1 [05:38:18] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only [05:38:18] [PASSED] drm_test_check_output_bpc_format_display_rgb_only [05:38:18] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only [05:38:18] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only [05:38:18] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc [05:38:18] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc [05:38:18] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc [05:38:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ====== [05:38:18] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ==== [05:38:18] [PASSED] drm_test_check_broadcast_rgb_value [05:38:18] [PASSED] drm_test_check_bpc_8_value [05:38:18] [PASSED] drm_test_check_bpc_10_value [05:38:18] [PASSED] drm_test_check_bpc_12_value [05:38:18] [PASSED] drm_test_check_format_value [05:38:18] [PASSED] drm_test_check_tmds_char_value [05:38:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ====== [05:38:18] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) = [05:38:18] [PASSED] drm_test_check_mode_valid [05:38:18] [PASSED] drm_test_check_mode_valid_reject [05:38:18] [PASSED] drm_test_check_mode_valid_reject_rate [05:38:18] [PASSED] drm_test_check_mode_valid_reject_max_clock [05:38:18] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid === [05:38:18] ================= drm_managed (2 subtests) ================= [05:38:18] [PASSED] drm_test_managed_release_action [05:38:18] [PASSED] drm_test_managed_run_action [05:38:18] =================== [PASSED] drm_managed =================== [05:38:18] =================== drm_mm (6 subtests) ==================== [05:38:18] [PASSED] drm_test_mm_init [05:38:18] [PASSED] drm_test_mm_debug [05:38:18] [PASSED] drm_test_mm_align32 [05:38:18] [PASSED] drm_test_mm_align64 [05:38:18] [PASSED] drm_test_mm_lowest [05:38:18] [PASSED] drm_test_mm_highest [05:38:18] ===================== [PASSED] drm_mm ====================== [05:38:18] ============= drm_modes_analog_tv (5 subtests) ============= [05:38:18] [PASSED] drm_test_modes_analog_tv_mono_576i [05:38:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i [05:38:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [05:38:18] [PASSED] drm_test_modes_analog_tv_pal_576i [05:38:18] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [05:38:18] =============== [PASSED] drm_modes_analog_tv =============== [05:38:18] ============== drm_plane_helper (2 subtests) =============== [05:38:18] =============== drm_test_check_plane_state ================ [05:38:18] [PASSED] clipping_simple [05:38:18] [PASSED] clipping_rotate_reflect [05:38:18] [PASSED] positioning_simple [05:38:18] [PASSED] upscaling [05:38:18] [PASSED] downscaling [05:38:18] [PASSED] rounding1 [05:38:18] [PASSED] rounding2 [05:38:18] [PASSED] rounding3 [05:38:18] [PASSED] rounding4 [05:38:18] =========== [PASSED] drm_test_check_plane_state ============ [05:38:18] =========== drm_test_check_invalid_plane_state ============ [05:38:18] [PASSED] positioning_invalid [05:38:18] [PASSED] upscaling_invalid [05:38:18] [PASSED] downscaling_invalid [05:38:18] ======= [PASSED] drm_test_check_invalid_plane_state ======== [05:38:18] ================ [PASSED] drm_plane_helper ================= [05:38:18] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [05:38:18] ====== drm_test_connector_helper_tv_get_modes_check ======= [05:38:18] [PASSED] None [05:38:18] [PASSED] PAL [05:38:18] [PASSED] NTSC [05:38:18] [PASSED] Both, NTSC Default [05:38:18] [PASSED] Both, PAL Default [05:38:18] [PASSED] Both, NTSC Default, with PAL on command-line [05:38:18] [PASSED] Both, PAL Default, with NTSC on command-line [05:38:18] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [05:38:18] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [05:38:18] ================== drm_rect (9 subtests) =================== [05:38:18] [PASSED] drm_test_rect_clip_scaled_div_by_zero [05:38:18] [PASSED] drm_test_rect_clip_scaled_not_clipped [05:38:18] [PASSED] drm_test_rect_clip_scaled_clipped [05:38:18] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [05:38:18] ================= drm_test_rect_intersect ================= [05:38:18] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [05:38:18] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [05:38:18] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [05:38:18] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [05:38:18] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [05:38:18] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [05:38:18] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [05:38:18] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [05:38:18] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [05:38:18] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [05:38:18] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [05:38:18] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [05:38:18] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [05:38:18] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [05:38:18] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [05:38:18] ============= [PASSED] drm_test_rect_intersect ============= [05:38:18] ================ drm_test_rect_calc_hscale ================ [05:38:18] [PASSED] normal use [05:38:18] [PASSED] out of max range [05:38:18] [PASSED] out of min range [05:38:18] [PASSED] zero dst [05:38:18] [PASSED] negative src [05:38:18] [PASSED] negative dst [05:38:18] ============ [PASSED] drm_test_rect_calc_hscale ============ [05:38:18] ================ drm_test_rect_calc_vscale ================ [05:38:18] [PASSED] normal use stty: 'standard input': Inappropriate ioctl for device [05:38:18] [PASSED] out of max range [05:38:18] [PASSED] out of min range [05:38:18] [PASSED] zero dst [05:38:18] [PASSED] negative src [05:38:18] [PASSED] negative dst [05:38:18] ============ [PASSED] drm_test_rect_calc_vscale ============ [05:38:18] ================== drm_test_rect_rotate =================== [05:38:18] [PASSED] reflect-x [05:38:18] [PASSED] reflect-y [05:38:18] [PASSED] rotate-0 [05:38:18] [PASSED] rotate-90 [05:38:18] [PASSED] rotate-180 [05:38:18] [PASSED] rotate-270 [05:38:18] ============== [PASSED] drm_test_rect_rotate =============== [05:38:18] ================ drm_test_rect_rotate_inv ================= [05:38:18] [PASSED] reflect-x [05:38:18] [PASSED] reflect-y [05:38:18] [PASSED] rotate-0 [05:38:18] [PASSED] rotate-90 [05:38:18] [PASSED] rotate-180 [05:38:18] [PASSED] rotate-270 [05:38:18] ============ [PASSED] drm_test_rect_rotate_inv ============= [05:38:18] ==================== [PASSED] drm_rect ===================== [05:38:18] ============ drm_sysfb_modeset_test (1 subtest) ============ [05:38:18] ============ drm_test_sysfb_build_fourcc_list ============= [05:38:18] [PASSED] no native formats [05:38:18] [PASSED] XRGB8888 as native format [05:38:18] [PASSED] remove duplicates [05:38:18] [PASSED] convert alpha formats [05:38:18] [PASSED] random formats [05:38:18] ======== [PASSED] drm_test_sysfb_build_fourcc_list ========= [05:38:18] ============= [PASSED] drm_sysfb_modeset_test ============== [05:38:18] ============================================================ [05:38:18] Testing complete. Ran 622 tests: passed: 622 [05:38:18] Elapsed time: 26.788s total, 1.737s configuring, 24.634s building, 0.387s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig [05:38:18] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [05:38:20] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48 [05:38:29] Starting KUnit Kernel (1/1)... [05:38:29] ============================================================ Running tests with: $ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt [05:38:29] ================= ttm_device (5 subtests) ================== [05:38:29] [PASSED] ttm_device_init_basic [05:38:29] [PASSED] ttm_device_init_multiple [05:38:29] [PASSED] ttm_device_fini_basic [05:38:29] [PASSED] ttm_device_init_no_vma_man [05:38:29] ================== ttm_device_init_pools ================== [05:38:29] [PASSED] No DMA allocations, no DMA32 required [05:38:29] [PASSED] DMA allocations, DMA32 required [05:38:29] [PASSED] No DMA allocations, DMA32 required [05:38:29] [PASSED] DMA allocations, no DMA32 required [05:38:29] ============== [PASSED] ttm_device_init_pools ============== [05:38:29] =================== [PASSED] ttm_device ==================== [05:38:29] ================== ttm_pool (8 subtests) =================== [05:38:29] ================== ttm_pool_alloc_basic =================== [05:38:29] [PASSED] One page [05:38:29] [PASSED] More than one page [05:38:29] [PASSED] Above the allocation limit [05:38:29] [PASSED] One page, with coherent DMA mappings enabled [05:38:29] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [05:38:29] ============== [PASSED] ttm_pool_alloc_basic =============== [05:38:29] ============== ttm_pool_alloc_basic_dma_addr ============== [05:38:29] [PASSED] One page [05:38:29] [PASSED] More than one page [05:38:29] [PASSED] Above the allocation limit [05:38:29] [PASSED] One page, with coherent DMA mappings enabled [05:38:29] [PASSED] Above the allocation limit, with coherent DMA mappings enabled [05:38:29] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ========== [05:38:29] [PASSED] ttm_pool_alloc_order_caching_match [05:38:29] [PASSED] ttm_pool_alloc_caching_mismatch [05:38:29] [PASSED] ttm_pool_alloc_order_mismatch [05:38:29] [PASSED] ttm_pool_free_dma_alloc [05:38:29] [PASSED] ttm_pool_free_no_dma_alloc [05:38:29] [PASSED] ttm_pool_fini_basic [05:38:29] ==================== [PASSED] ttm_pool ===================== [05:38:29] ================ ttm_resource (8 subtests) ================= [05:38:29] ================= ttm_resource_init_basic ================= [05:38:29] [PASSED] Init resource in TTM_PL_SYSTEM [05:38:29] [PASSED] Init resource in TTM_PL_VRAM [05:38:29] [PASSED] Init resource in a private placement [05:38:29] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags [05:38:29] ============= [PASSED] ttm_resource_init_basic ============= [05:38:29] [PASSED] ttm_resource_init_pinned [05:38:29] [PASSED] ttm_resource_fini_basic [05:38:29] [PASSED] ttm_resource_manager_init_basic [05:38:29] [PASSED] ttm_resource_manager_usage_basic [05:38:29] [PASSED] ttm_resource_manager_set_used_basic [05:38:29] [PASSED] ttm_sys_man_alloc_basic [05:38:29] [PASSED] ttm_sys_man_free_basic [05:38:29] ================== [PASSED] ttm_resource =================== [05:38:29] =================== ttm_tt (15 subtests) =================== [05:38:29] ==================== ttm_tt_init_basic ==================== [05:38:29] [PASSED] Page-aligned size [05:38:29] [PASSED] Extra pages requested [05:38:29] ================ [PASSED] ttm_tt_init_basic ================ [05:38:29] [PASSED] ttm_tt_init_misaligned [05:38:29] [PASSED] ttm_tt_fini_basic [05:38:29] [PASSED] ttm_tt_fini_sg [05:38:29] [PASSED] ttm_tt_fini_shmem [05:38:29] [PASSED] ttm_tt_create_basic [05:38:29] [PASSED] ttm_tt_create_invalid_bo_type [05:38:29] [PASSED] ttm_tt_create_ttm_exists [05:38:29] [PASSED] ttm_tt_create_failed [05:38:29] [PASSED] ttm_tt_destroy_basic [05:38:29] [PASSED] ttm_tt_populate_null_ttm [05:38:29] [PASSED] ttm_tt_populate_populated_ttm [05:38:29] [PASSED] ttm_tt_unpopulate_basic [05:38:29] [PASSED] ttm_tt_unpopulate_empty_ttm [05:38:29] [PASSED] ttm_tt_swapin_basic [05:38:29] ===================== [PASSED] ttm_tt ====================== [05:38:29] =================== ttm_bo (14 subtests) =================== [05:38:29] =========== ttm_bo_reserve_optimistic_no_ticket =========== [05:38:29] [PASSED] Cannot be interrupted and sleeps [05:38:29] [PASSED] Cannot be interrupted, locks straight away [05:38:29] [PASSED] Can be interrupted, sleeps [05:38:29] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket ======= [05:38:29] [PASSED] ttm_bo_reserve_locked_no_sleep [05:38:29] [PASSED] ttm_bo_reserve_no_wait_ticket [05:38:29] [PASSED] ttm_bo_reserve_double_resv [05:38:29] [PASSED] ttm_bo_reserve_interrupted [05:38:29] [PASSED] ttm_bo_reserve_deadlock [05:38:29] [PASSED] ttm_bo_unreserve_basic [05:38:29] [PASSED] ttm_bo_unreserve_pinned [05:38:29] [PASSED] ttm_bo_unreserve_bulk [05:38:29] [PASSED] ttm_bo_fini_basic [05:38:29] [PASSED] ttm_bo_fini_shared_resv [05:38:29] [PASSED] ttm_bo_pin_basic [05:38:29] [PASSED] ttm_bo_pin_unpin_resource [05:38:29] [PASSED] ttm_bo_multiple_pin_one_unpin [05:38:29] ===================== [PASSED] ttm_bo ====================== [05:38:29] ============== ttm_bo_validate (21 subtests) =============== [05:38:29] ============== ttm_bo_init_reserved_sys_man =============== [05:38:29] [PASSED] Buffer object for userspace [05:38:29] [PASSED] Kernel buffer object [05:38:29] [PASSED] Shared buffer object [05:38:29] ========== [PASSED] ttm_bo_init_reserved_sys_man =========== [05:38:29] ============== ttm_bo_init_reserved_mock_man ============== [05:38:29] [PASSED] Buffer object for userspace [05:38:29] [PASSED] Kernel buffer object [05:38:29] [PASSED] Shared buffer object [05:38:29] ========== [PASSED] ttm_bo_init_reserved_mock_man ========== [05:38:29] [PASSED] ttm_bo_init_reserved_resv [05:38:29] ================== ttm_bo_validate_basic ================== [05:38:29] [PASSED] Buffer object for userspace [05:38:29] [PASSED] Kernel buffer object [05:38:29] [PASSED] Shared buffer object [05:38:29] ============== [PASSED] ttm_bo_validate_basic ============== [05:38:29] [PASSED] ttm_bo_validate_invalid_placement [05:38:29] ============= ttm_bo_validate_same_placement ============== [05:38:29] [PASSED] System manager [05:38:29] [PASSED] VRAM manager [05:38:29] ========= [PASSED] ttm_bo_validate_same_placement ========== [05:38:29] [PASSED] ttm_bo_validate_failed_alloc [05:38:29] [PASSED] ttm_bo_validate_pinned [05:38:29] [PASSED] ttm_bo_validate_busy_placement [05:38:29] ================ ttm_bo_validate_multihop ================= [05:38:29] [PASSED] Buffer object for userspace [05:38:29] [PASSED] Kernel buffer object [05:38:29] [PASSED] Shared buffer object [05:38:29] ============ [PASSED] ttm_bo_validate_multihop ============= [05:38:29] ========== ttm_bo_validate_no_placement_signaled ========== [05:38:29] [PASSED] Buffer object in system domain, no page vector [05:38:29] [PASSED] Buffer object in system domain with an existing page vector [05:38:29] ====== [PASSED] ttm_bo_validate_no_placement_signaled ====== [05:38:29] ======== ttm_bo_validate_no_placement_not_signaled ======== [05:38:29] [PASSED] Buffer object for userspace [05:38:29] [PASSED] Kernel buffer object [05:38:29] [PASSED] Shared buffer object [05:38:29] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ==== [05:38:29] [PASSED] ttm_bo_validate_move_fence_signaled [05:38:29] ========= ttm_bo_validate_move_fence_not_signaled ========= [05:38:29] [PASSED] Waits for GPU [05:38:29] [PASSED] Tries to lock straight away [05:38:29] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled ===== [05:38:29] [PASSED] ttm_bo_validate_happy_evict [05:38:29] [PASSED] ttm_bo_validate_all_pinned_evict [05:38:29] [PASSED] ttm_bo_validate_allowed_only_evict [05:38:29] [PASSED] ttm_bo_validate_deleted_evict [05:38:29] [PASSED] ttm_bo_validate_busy_domain_evict [05:38:29] [PASSED] ttm_bo_validate_evict_gutting [05:38:29] [PASSED] ttm_bo_validate_recrusive_evict stty: 'standard input': Inappropriate ioctl for device [05:38:29] ================= [PASSED] ttm_bo_validate ================= [05:38:29] ============================================================ [05:38:29] Testing complete. Ran 101 tests: passed: 101 [05:38:29] Elapsed time: 11.276s total, 1.699s configuring, 9.310s building, 0.216s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Xe.CI.BAT: success for Different page size handle in migrate layer (rev2) 2025-10-13 3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost ` (2 preceding siblings ...) 2025-10-13 5:38 ` ✓ CI.KUnit: success for Different page size handle in migrate layer (rev2) Patchwork @ 2025-10-13 6:23 ` Patchwork 2025-10-13 6:51 ` ✓ Xe.CI.Full: " Patchwork 4 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2025-10-13 6:23 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 873 bytes --] == Series Details == Series: Different page size handle in migrate layer (rev2) URL : https://patchwork.freedesktop.org/series/155794/ State : success == Summary == CI Bug Log - changes from xe-3904-085518a4da5bcf9b68ef798e27ef71d64443aad7_BAT -> xe-pw-155794v2_BAT ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Changes ------- No changes found Build changes ------------- * Linux: xe-3904-085518a4da5bcf9b68ef798e27ef71d64443aad7 -> xe-pw-155794v2 IGT_8582: 8582 xe-3904-085518a4da5bcf9b68ef798e27ef71d64443aad7: 085518a4da5bcf9b68ef798e27ef71d64443aad7 xe-pw-155794v2: 155794v2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155794v2/index.html [-- Attachment #2: Type: text/html, Size: 1421 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
* ✓ Xe.CI.Full: success for Different page size handle in migrate layer (rev2) 2025-10-13 3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost ` (3 preceding siblings ...) 2025-10-13 6:23 ` ✓ Xe.CI.BAT: " Patchwork @ 2025-10-13 6:51 ` Patchwork 4 siblings, 0 replies; 17+ messages in thread From: Patchwork @ 2025-10-13 6:51 UTC (permalink / raw) To: Matthew Brost; +Cc: intel-xe [-- Attachment #1: Type: text/plain, Size: 873 bytes --] == Series Details == Series: Different page size handle in migrate layer (rev2) URL : https://patchwork.freedesktop.org/series/155794/ State : success == Summary == CI Bug Log - changes from xe-3904-085518a4da5bcf9b68ef798e27ef71d64443aad7_FULL -> xe-pw-155794v2_FULL ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (4 -> 4) ------------------------------ No changes in participating hosts Changes ------- No changes found Build changes ------------- * Linux: xe-3904-085518a4da5bcf9b68ef798e27ef71d64443aad7 -> xe-pw-155794v2 IGT_8582: 8582 xe-3904-085518a4da5bcf9b68ef798e27ef71d64443aad7: 085518a4da5bcf9b68ef798e27ef71d64443aad7 xe-pw-155794v2: 155794v2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155794v2/index.html [-- Attachment #2: Type: text/html, Size: 1421 bytes --] ^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2025-10-14 3:08 UTC | newest] Thread overview: 17+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-13 3:45 [PATCH v5 0/2] Different page size handle in migrate layer Matthew Brost 2025-10-13 3:45 ` [PATCH v5 1/2] drm/xe: Fix build_pt_update_batch_sram for non-4K PAGE_SIZE Matthew Brost 2025-10-13 16:38 ` [v5,1/2] " Simon Richter 2025-10-13 16:53 ` [PATCH v5 1/2] " Summers, Stuart 2025-10-13 3:45 ` [PATCH v5 2/2] drm/xe: Enable 2M pages in xe_migrate_vram Matthew Brost 2025-10-13 17:08 ` Summers, Stuart 2025-10-13 17:14 ` Matthew Brost 2025-10-13 17:22 ` Summers, Stuart 2025-10-13 17:34 ` Matthew Brost 2025-10-13 18:01 ` Summers, Stuart 2025-10-14 2:17 ` Simon Richter 2025-10-14 3:08 ` Summers, Stuart 2025-10-13 17:29 ` Simon.Richter 2025-10-13 17:32 ` Matthew Brost 2025-10-13 5:38 ` ✓ CI.KUnit: success for Different page size handle in migrate layer (rev2) Patchwork 2025-10-13 6:23 ` ✓ Xe.CI.BAT: " Patchwork 2025-10-13 6:51 ` ✓ Xe.CI.Full: " Patchwork
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