[PATCH v4 00/13] CMTG enablement

[PATCH v4 00/13] CMTG enablement

[Animesh Manna]

Common mode timing generator (CMTG) support is added NVL onwards.
Enable CMTG which will be needed by other fearure like dynamic dc
state enablement later.

Testing ongoing, currently counters are incrementing as expected.

Animesh Manna (12):
  drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
  drm/i915/cmtg: Set CMTG clock select
  drm/i915/cmtg: Set timings for CMTG
  drm/i915/cmtg: Program VRR registers of CMTG
  drm/i915/cmtg: Set transcoder mn for CMTG
  drm/i915/cmtg: Add hook to enable CMTG with sync to port
  drm/i915/cmtg: Add a hook to make eDP transcoder secondary
  drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed()
  drm/i915/cmtg: Add trigger to enable/disable cmtg
  drm/i915/cmtg: Add CMTG interrupt handling
  drm/i915/cmtg: Disable CMTG if dc3co is not allowed
  drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm

Dibin Moolakadan Subrahmanian (1):
  drm/i915/cmtg: Modify existing hook to disable CMTG

 drivers/gpu/drm/i915/display/intel_cmtg.c     | 260 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  14 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  70 ++++-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   5 +
 drivers/gpu/drm/i915/display/intel_display.c  |  19 ++
 .../gpu/drm/i915/display/intel_display_irq.c  |  12 +
 .../gpu/drm/i915/display/intel_display_regs.h |   6 +
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   8 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |   5 +
 10 files changed, 393 insertions(+), 10 deletions(-)

-- 
2.29.0

[PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Animesh Manna]

CMTG will be enabled only with DC3co, so add a separate function
intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
DC3co will be enabled in a separate patch.

v2:
- Remove separate flag for DC3co from crtc_state. [Uma, Dibin]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index e1fdc6fe9762..1debed43cf2c 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_device.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
+#include "intel_display_types.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -185,3 +186,17 @@ void intel_cmtg_sanitize(struct intel_display *display)
 
 	intel_cmtg_disable(display, &cmtg_config);
 }
+
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	    power_domains->target_dc_state == DC_STATE_EN_DC3CO)
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index ba62199adaa2..7692cc98cf87 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -7,7 +7,9 @@
 #define __INTEL_CMTG_H__
 
 struct intel_display;
+struct intel_crtc_state;
 
 void intel_cmtg_sanitize(struct intel_display *display);
+bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
-- 
2.29.0

[PATCH v4 02/13] drm/i915/cmtg: Set CMTG clock select

[Animesh Manna]

Program the CMTG Clock Select register based on the transcoder used.

v2:
- Correct mask for PHY B. [Jani]
- Use REG_FIELD_PREP() for enable value. [Dibin]
- Extend cmtg clock select for xe3plpd. [Dibin]

v3:
- CMTG support removed for old platform.

v4:
- Optimize further with else-if. [Uma]
- Correct CMTG_CLK_SEL_B_MASK. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 22 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  5 +++++
 4 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 1debed43cf2c..403f9e10a8dc 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -200,3 +200,25 @@ bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 
 	return false;
 }
+
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 clk_sel_clr = 0;
+	u32 clk_sel_set = 0;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A) {
+		clk_sel_clr = CMTG_CLK_SEL_A_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYA_ENABLE;
+	} else if (cpu_transcoder == TRANSCODER_B) {
+		clk_sel_clr = CMTG_CLK_SEL_B_MASK;
+		clk_sel_set = CMTG_CLK_SELECT_PHYB_ENABLE;
+	}
+
+	if (clk_sel_set)
+		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 7692cc98cf87..660ec513626e 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -9,6 +9,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 945a35578284..4a80b88d88fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -10,8 +10,10 @@
 
 #define CMTG_CLK_SEL			_MMIO(0x46160)
 #define CMTG_CLK_SEL_A_MASK		REG_GENMASK(31, 29)
+#define CMTG_CLK_SELECT_PHYA_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0x4)
 #define CMTG_CLK_SEL_A_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_A_MASK, 0)
 #define CMTG_CLK_SEL_B_MASK		REG_GENMASK(15, 13)
+#define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
 #define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7e59409bbf01..38f3adeac791 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -9,6 +9,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_display_regs.h"
@@ -3418,10 +3419,14 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
+
+	if (HAS_LT_PHY(display))
+		intel_cmtg_set_clk_select(crtc_state);
 }
 
 /*
-- 
2.29.0

[PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Animesh Manna]

Timing registers are separate for CMTG, read transcoder register
and program cmtg transcoder with those values.

v2:
- Use sw state instead of reading directly from hardware. [Jani]
- Move set_timing later after encoder enable. [Dibin]

v3:
- Replace id with trans. [Jani]
- Program cmtg set_timing() along with primary transcoder timing.

v4:
- Use _MMIO_TRANS() for cmtg registers instead of direct
multiplication. [Jani]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 61 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
 drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
 4 files changed, 98 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 403f9e10a8dc..a3db1368bd83 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -4,7 +4,6 @@
  */
 
 #include <linux/string_choices.h>
-#include <linux/types.h>
 
 #include <drm/drm_device.h>
 #include <drm/drm_print.h>
@@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
 	if (clk_sel_set)
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
+
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
+
+	/*
+	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
+	 * bits are not required. Since the support for these bits is going to
+	 * be deprecated in upcoming platforms, avoid writing these bits for the
+	 * platforms that do not use legacy Timing Generator.
+	 */
+	crtc_vtotal = 1;
+
+	/*
+	 * VBLANK_START not used by hw, just clear it
+	 * to make it stand out in register dumps.
+	 */
+	crtc_vblank_start = 1;
+
+	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
+
+	if (lrr) {
+		intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
+			       VACTIVE(crtc_vdisplay - 1) |
+			       VTOTAL(crtc_vtotal - 1));
+		intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
+			       VBLANK_START(crtc_vblank_start - 1) |
+			       VBLANK_END(crtc_vblank_end - 1));
+		return;
+	}
+
+	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
+		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+		       HTOTAL(adjusted_mode->crtc_htotal - 1));
+	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
+		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
+	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
+		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
+	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
+		       VACTIVE(crtc_vdisplay - 1) |
+		       VTOTAL(crtc_vtotal - 1));
+	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
+		       VBLANK_START(crtc_vblank_start - 1) |
+		       VBLANK_END(crtc_vblank_end - 1));
+	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
+		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
+	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
+		       crtc_state->set_context_latency);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 660ec513626e..53a44f505dd2 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -6,9 +6,12 @@
 #ifndef __INTEL_CMTG_H__
 #define __INTEL_CMTG_H__
 
+#include <linux/types.h>
+
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index 4a80b88d88fd..f7fc812d8ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -20,4 +20,35 @@
 #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
 #define  CMTG_ENABLE			REG_BIT(31)
 
+#define _TRANS_HTOTAL_CMTG_A		0x6F000
+#define _TRANS_HTOTAL_CMTG_B		0x6F100
+#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
+						    _TRANS_HTOTAL_CMTG_A, _TRANS_HTOTAL_CMTG_B)
+#define _TRANS_HBLANK_CMTG_A		0x6F004
+#define _TRANS_HBLANK_CMTG_B		0x6F104
+#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
+						    _TRANS_HBLANK_CMTG_A, _TRANS_HBLANK_CMTG_B)
+#define _TRANS_HSYNC_CMTG_A		0x6F008
+#define _TRANS_HSYNC_CMTG_B		0x6F108
+#define TRANS_HSYNC_CMTG(trans)		_MMIO_TRANS((trans), \
+						    _TRANS_HSYNC_CMTG_A, _TRANS_HSYNC_CMTG_B)
+#define _TRANS_VTOTAL_CMTG_A		0x6F00C
+#define _TRANS_VTOTAL_CMTG_B		0x6F10C
+#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
+						    _TRANS_VTOTAL_CMTG_A, _TRANS_VTOTAL_CMTG_B)
+#define _TRANS_VBLANK_CMTG_A		0x6F010
+#define _TRANS_VBLANK_CMTG_B		0x6F110
+#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
+						    _TRANS_VBLANK_CMTG_A, _TRANS_VBLANK_CMTG_B)
+#define _TRANS_VSYNC_CMTG_A		0x6F014
+#define _TRANS_VSYNC_CMTG_B		0x6F114
+#define TRANS_VSYNC_CMTG(trans)		_MMIO_TRANS((trans), \
+						    _TRANS_VSYNC_CMTG_A, _TRANS_VSYNC_CMTG_B)
+
+#define _TRANS_SET_CTX_LATENCY_CMTG_A	0x6F07C
+#define _TRANS_SET_CTX_LATENCY_CMTG_B	0x6F17C
+#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO_TRANS((trans), \
+							    _TRANS_SET_CTX_LATENCY_CMTG_A, \
+							    _TRANS_SET_CTX_LATENCY_CMTG_B)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 58a654ca0d20..bf58ae5d3535 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -60,6 +60,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_clock_gating.h"
+#include "intel_cmtg.h"
 #include "intel_color.h"
 #include "intel_crt.h"
 #include "intel_crtc.h"
@@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
 			       crtc_state->min_hblank);
 	}
+
+	intel_cmtg_set_timings(crtc_state, false);
 }
 
 static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
@@ -2814,6 +2817,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 		       VACTIVE(crtc_vdisplay - 1) |
 		       VTOTAL(crtc_vtotal - 1));
 
+	intel_cmtg_set_timings(crtc_state, true);
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 	intel_vrr_transcoder_enable(crtc_state);
 }
-- 
2.29.0

[PATCH v4 04/13] drm/i915/cmtg: Program VRR registers of CMTG

[Animesh Manna]

Program the VRR registers of CMTG, as the VRR timing generator
will always be enabled for NVL.

v2: Use sw state instead of reading from hardware. [Jani]
v3: Program cmtg vrr control and timing registers along with
vrr transcoder registers.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 33 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 ++
 .../gpu/drm/i915/display/intel_cmtg_regs.h    | 20 +++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      |  5 +++
 4 files changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index a3db1368bd83..c5ef9de2e408 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -16,6 +16,7 @@
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
+#include "intel_vrr_regs.h"
 
 /**
  * DOC: Common Primary Timing Generator (CMTG)
@@ -281,3 +282,35 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
 		       crtc_state->set_context_latency);
 }
+
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_VRR_VMIN_CMTG(cpu_transcoder), crtc_state->vrr.vmin);
+	intel_de_write(display, TRANS_VRR_VMAX_CMTG(cpu_transcoder), crtc_state->vrr.vmax);
+	intel_de_write(display, TRANS_VRR_FLIPLINE_CMTG(cpu_transcoder), crtc_state->vrr.flipline);
+}
+
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 vrr_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	vrr_ctl = VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN |
+		  XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+
+	/* TODO: The code below may need to be revisited once CMRR is enabled */
+	if (crtc_state->cmrr.enable)
+		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
+
+	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), vrr_ctl);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 53a44f505dd2..c92e3a62ff0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,8 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index f7fc812d8ef0..b50ada371262 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -51,4 +51,24 @@
 							    _TRANS_SET_CTX_LATENCY_CMTG_A, \
 							    _TRANS_SET_CTX_LATENCY_CMTG_B)
 
+#define _TRANS_VRR_CTL_CMTG_A		0x6F420
+#define _TRANS_VRR_CTL_CMTG_B		0x6F520
+#define TRANS_VRR_CTL_CMTG(trans)	_MMIO_TRANS((trans), \
+						     _TRANS_VRR_CTL_CMTG_A, _TRANS_VRR_CTL_CMTG_B)
+#define _TRANS_VRR_VMAX_CMTG_A		0x6F424
+#define _TRANS_VRR_VMAX_CMTG_B		0x6F524
+#define TRANS_VRR_VMAX_CMTG(trans)	_MMIO_TRANS((trans), \
+						     _TRANS_VRR_VMAX_CMTG_A, \
+						     _TRANS_VRR_VMAX_CMTG_B)
+#define _TRANS_VRR_VMIN_CMTG_A		0x6F434
+#define _TRANS_VRR_VMIN_CMTG_B		0x6F534
+#define TRANS_VRR_VMIN_CMTG(trans)	_MMIO_TRANS((trans), \
+						     _TRANS_VRR_VMIN_CMTG_A, \
+						     _TRANS_VRR_VMIN_CMTG_B)
+#define _TRANS_VRR_FLIPLINE_CMTG_A	0x6F438
+#define _TRANS_VRR_FLIPLINE_CMTG_B	0x6F538
+#define TRANS_VRR_FLIPLINE_CMTG(trans)	_MMIO_TRANS((trans), \
+						     _TRANS_VRR_FLIPLINE_CMTG_A, \
+						     _TRANS_VRR_FLIPLINE_CMTG_B)
+
 #endif /* __INTEL_CMTG_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index fae1186a90b2..ce71cf35fba5 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -7,6 +7,7 @@
 #include <drm/drm_print.h>
 
 #include "intel_alpm.h"
+#include "intel_cmtg.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
@@ -324,6 +325,8 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
 	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
 		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
+
+	intel_cmtg_set_vrr_timings(crtc_state);
 }
 
 static
@@ -922,6 +925,8 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
 	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+
+	intel_cmtg_set_vrr_ctl(crtc_state);
 }
 
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.29.0

[PATCH v4 05/13] drm/i915/cmtg: Set transcoder mn for CMTG

[Animesh Manna]

Program CMTG link M/N.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c      | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h      |  1 +
 drivers/gpu/drm/i915/display/intel_cmtg_regs.h |  9 +++++++++
 drivers/gpu/drm/i915/display/intel_display.c   |  1 +
 4 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c5ef9de2e408..aecee4157405 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -314,3 +314,16 @@ void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_VRR_CTL_CMTG(cpu_transcoder), vrr_ctl);
 }
+
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	const struct intel_link_m_n *m_n = &crtc_state->dp_m_n;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
+	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index c92e3a62ff0d..6796eb727eef 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b50ada371262..b6a549aec033 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -45,6 +45,15 @@
 #define TRANS_VSYNC_CMTG(trans)		_MMIO_TRANS((trans), \
 						    _TRANS_VSYNC_CMTG_A, _TRANS_VSYNC_CMTG_B)
 
+#define _TRANS_LINKM1_CMTG_A		0x6F040
+#define _TRANS_LINKM1_CMTG_B		0x6F140
+#define TRANS_LINKM1_CMTG(trans)	_MMIO_TRANS((trans), \
+						    _TRANS_LINKM1_CMTG_A, _TRANS_LINKM1_CMTG_B)
+#define _TRANS_LINKN1_CMTG_A		0x6F044
+#define _TRANS_LINKN1_CMTG_B		0x6F144
+#define TRANS_LINKN1_CMTG(trans)	_MMIO_TRANS((trans), \
+						    _TRANS_LINKN1_CMTG_A, _TRANS_LINKN1_CMTG_B)
+
 #define _TRANS_SET_CTX_LATENCY_CMTG_A	0x6F07C
 #define _TRANS_SET_CTX_LATENCY_CMTG_B	0x6F17C
 #define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO_TRANS((trans), \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf58ae5d3535..e8470b7ce13f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1615,6 +1615,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
 					       &crtc_state->dp_m2_n2);
 	}
 
+	intel_cmtg_set_m_n(crtc_state);
 	intel_set_transcoder_timings(crtc_state);
 
 	if (cpu_transcoder != TRANSCODER_EDP)
-- 
2.29.0

[PATCH v4 06/13] drm/i915/cmtg: Add hook to enable CMTG with sync to port

[Animesh Manna]

Add a hook to enable CMTG by programming CMTG CTL with Sync to Port.
When CMTG starts running, the Sync to Port bit will be cleared. Add
a wait to check its running status and trigger WARN_ON() on timeout.

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 27 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  7 +++--
 3 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index aecee4157405..be8b513cde45 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -104,11 +104,11 @@ static void intel_cmtg_get_config(struct intel_display *display,
 {
 	u32 val;
 
-	val = intel_de_read(display, TRANS_CMTG_CTL_A);
+	val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_A));
 	cmtg_config->cmtg_a_enable = val & CMTG_ENABLE;
 
 	if (intel_cmtg_has_cmtg_b(display)) {
-		val = intel_de_read(display, TRANS_CMTG_CTL_B);
+		val = intel_de_read(display, TRANS_CMTG_CTL(TRANSCODER_B));
 		cmtg_config->cmtg_b_enable = val & CMTG_ENABLE;
 	}
 
@@ -141,14 +141,14 @@ static void intel_cmtg_disable(struct intel_display *display,
 
 	if (cmtg_config->cmtg_a_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG A\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_A), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_A_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_A_DISABLED;
 	}
 
 	if (cmtg_config->cmtg_b_enable) {
 		drm_dbg_kms(display->drm, "Disabling CMTG B\n");
-		intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0);
+		intel_de_rmw(display, TRANS_CMTG_CTL(TRANSCODER_B), CMTG_ENABLE, 0);
 		clk_sel_clr |= CMTG_CLK_SEL_B_MASK;
 		clk_sel_set |= CMTG_CLK_SEL_B_DISABLED;
 	}
@@ -327,3 +327,22 @@ void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state)
 	intel_de_write(display, TRANS_LINKM1_CMTG(cpu_transcoder), m_n->link_m);
 	intel_de_write(display, TRANS_LINKN1_CMTG(cpu_transcoder), m_n->link_n);
 }
+
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 cmtg_ctl;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	cmtg_ctl = CMTG_SYNC_TO_PORT | CMTG_ENABLE;
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), 0, cmtg_ctl);
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder),
+				       CMTG_SYNC_TO_PORT, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s enable timeout\n",
+			 transcoder_name(cpu_transcoder));
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 6796eb727eef..64ff6a19948a 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_ctl(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index b6a549aec033..d447a72bd9fa 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -16,9 +16,12 @@
 #define CMTG_CLK_SELECT_PHYB_ENABLE	REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0x6)
 #define CMTG_CLK_SEL_B_DISABLED		REG_FIELD_PREP(CMTG_CLK_SEL_B_MASK, 0)
 
-#define TRANS_CMTG_CTL_A		_MMIO(0x6fa88)
-#define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
+#define _TRANS_CMTG_CTL_A		0x6fa88
+#define _TRANS_CMTG_CTL_B		0x6fb88
+#define TRANS_CMTG_CTL(trans)		_MMIO_TRANS((trans), \
+						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
+#define  CMTG_SYNC_TO_PORT		REG_BIT(29)
 
 #define _TRANS_HTOTAL_CMTG_A		0x6F000
 #define _TRANS_HTOTAL_CMTG_B		0x6F100
-- 
2.29.0

[PATCH v4 07/13] drm/i915/cmtg: Add a hook to make eDP transcoder secondary

[Animesh Manna]

Program DDI_FUNC_CTL2 to configure the eDP transcoder as secondary
to the CMTG transcoder.

v2:
- Update commit header to be more clear. [Uma]

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 13 +++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index be8b513cde45..f9cfb639b9fd 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -346,3 +346,16 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 			 transcoder_name(cpu_transcoder));
 	}
 }
+
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_allowed(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
+
+	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 64ff6a19948a..12abbafa7d08 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_vrr_timings(const struct intel_crtc_state *crtc_state);
-- 
2.29.0

[PATCH v4 08/13] drm/i915/cmtg: Split CMTG support check from intel_cmtg_is_allowed()

[Animesh Manna]

Introduce a dedicated hook to check whether CMTG is supported. This
helper is used in both the enable and disable sequences, while
intel_cmtg_is_allowed() is now used only in enable path.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index f9cfb639b9fd..c043fb4f9789 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -82,6 +82,18 @@ static void intel_cmtg_dump_config(struct intel_display *display,
 		    str_yes_no(cmtg_config->trans_b_secondary));
 }
 
+static bool intel_cmtg_is_supported(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
+	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return true;
+
+	return false;
+}
+
 static bool intel_cmtg_transcoder_is_secondary(struct intel_display *display,
 					       enum transcoder trans)
 {
@@ -190,11 +202,9 @@ void intel_cmtg_sanitize(struct intel_display *display)
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	struct i915_power_domains *power_domains = &display->power.domains;
 
-	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
-	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	if (intel_cmtg_is_supported(crtc_state) &&
 	    power_domains->target_dc_state == DC_STATE_EN_DC3CO)
 		return true;
 
-- 
2.29.0

[PATCH v4 09/13] drm/i915/cmtg: Modify existing hook to disable CMTG

[Animesh Manna]

From: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>

Earlier cmtg_disable() used to disable all instances of CMTG
which cannot handle individual request for specific CMTG instance.
Introduce cmtg_disable_all() which will disable all cmtg instances
and cmtg_disable() only disable specific instance.

v2:
- Use intel_de_rmw to simplify. [Uma]

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 30 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  1 +
 .../gpu/drm/i915/display/intel_cmtg_regs.h    |  1 +
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index c043fb4f9789..00e5bdd1b063 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -137,8 +137,8 @@ static bool intel_cmtg_disable_requires_modeset(struct intel_display *display,
 	return cmtg_config->trans_a_secondary || cmtg_config->trans_b_secondary;
 }
 
-static void intel_cmtg_disable(struct intel_display *display,
-			       struct intel_cmtg_config *cmtg_config)
+static void intel_cmtg_disable_all(struct intel_display *display,
+				   struct intel_cmtg_config *cmtg_config)
 {
 	u32 clk_sel_clr = 0;
 	u32 clk_sel_set = 0;
@@ -169,6 +169,30 @@ static void intel_cmtg_disable(struct intel_display *display,
 		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
 }
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!intel_cmtg_is_supported(crtc_state))
+		return;
+
+	intel_de_rmw(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
+		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
+
+	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
+		     PORT_SYNC_MODE_ENABLE, 0);
+
+	intel_de_rmw(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_ENABLE, 0);
+
+	if (intel_de_wait_for_clear_ms(display, TRANS_CMTG_CTL(cpu_transcoder), CMTG_STATE, 50)) {
+		drm_WARN(display->drm, 1, "CMTG: %s disable timeout\n",
+			 transcoder_name(cpu_transcoder));
+		return;
+	}
+
+	drm_dbg_kms(display->drm, "CMTG: %s disabled\n", transcoder_name(cpu_transcoder));
+}
 /*
  * Read out CMTG configuration and, on platforms that allow disabling it without
  * a modeset, do it.
@@ -196,7 +220,7 @@ void intel_cmtg_sanitize(struct intel_display *display)
 	if (intel_cmtg_disable_requires_modeset(display, &cmtg_config))
 		return;
 
-	intel_cmtg_disable(display, &cmtg_config);
+	intel_cmtg_disable_all(display, &cmtg_config);
 }
 
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 12abbafa7d08..79785afccc51 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -11,6 +11,7 @@
 struct intel_display;
 struct intel_crtc_state;
 
+void intel_cmtg_disable(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_set_m_n(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
index d447a72bd9fa..d2f83829b8a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
@@ -22,6 +22,7 @@
 						    _TRANS_CMTG_CTL_A, _TRANS_CMTG_CTL_B)
 #define  CMTG_ENABLE			REG_BIT(31)
 #define  CMTG_SYNC_TO_PORT		REG_BIT(29)
+#define  CMTG_STATE			REG_BIT(23)
 
 #define _TRANS_HTOTAL_CMTG_A		0x6F000
 #define _TRANS_HTOTAL_CMTG_B		0x6F100
-- 
2.29.0

[PATCH v4 10/13] drm/i915/cmtg: Add trigger to enable/disable cmtg

[Animesh Manna]

Enable CMTG with fixed refresh rate mode and with dynamic
dc state enabled.

Disable CMTG with transcoder disable or if there is a transition
to vrr mode from fixed refresh rate mode.

v2:
- Move the enabled flag update to avoid issue in the disable timeout
path. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c          |  5 +++++
 drivers/gpu/drm/i915/display/intel_display.c       | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_display_types.h |  4 ++++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index 00e5bdd1b063..fc4595efec2d 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -172,11 +172,14 @@ static void intel_cmtg_disable_all(struct intel_display *display,
 void intel_cmtg_disable(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!intel_cmtg_is_supported(crtc_state))
 		return;
 
+	crtc->cmtg.enabled = false;
+
 	intel_de_rmw(display, TRANS_VRR_CTL_CMTG(cpu_transcoder),
 		     VRR_CTL_VRR_ENABLE | VRR_CTL_FLIP_LINE_EN, 0);
 
@@ -384,6 +387,7 @@ void intel_cmtg_enable_sync(const struct intel_crtc_state *crtc_state)
 void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
 	if (!intel_cmtg_is_allowed(crtc_state))
@@ -391,5 +395,6 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 
 	intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, cpu_transcoder), 0, CMTG_SECONDARY_MODE);
 
+	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e8470b7ce13f..30bc209d8fb6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1061,6 +1061,11 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 		intel_alpm_lobf_enable(new_crtc_state);
 
 	intel_psr_post_plane_update(state, crtc);
+
+	if (!crtc->cmtg.enabled && intel_vrr_is_fixed_rr(new_crtc_state)) {
+		intel_cmtg_enable_sync(new_crtc_state);
+		intel_cmtg_enable_ddi(new_crtc_state);
+	}
 }
 
 static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
@@ -1771,6 +1776,8 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 	struct intel_crtc *pipe_crtc;
 	int i;
 
+	if (crtc->cmtg.enabled)
+		intel_cmtg_disable(old_crtc_state);
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
@@ -6865,6 +6872,9 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	if (intel_crtc_needs_fastset(new_crtc_state) &&
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
+
+	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc))
+		intel_cmtg_disable(new_crtc_state);
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ca2581fb7bbd..f5c9ceb87e58 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1571,6 +1571,10 @@ struct intel_crtc {
 #endif
 
 	bool vblank_psr_notify;
+
+	struct {
+		bool enabled;
+	} cmtg;
 };
 
 struct intel_plane_error {
-- 
2.29.0

[PATCH v4 11/13] drm/i915/cmtg: Add CMTG interrupt handling

[Animesh Manna]

Add support fot vsync, vblank, and delayed vlank interrupts of
CMTG which are part of DE port interrupt.

v2:
- Use consistent DC3co check as used in earlier patches. [Uma]
- Use else-if instead of separate if block. [Uma]
- Merge mask and unmask function as it is similar. [Uma]
- Modify DISPLAY_VER() check. [Uma]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cmtg.c     | 31 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cmtg.h     |  2 ++
 drivers/gpu/drm/i915/display/intel_display.c  |  5 ++-
 .../gpu/drm/i915/display/intel_display_irq.c  | 12 +++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  6 ++++
 5 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
index fc4595efec2d..e49123fac595 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.c
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
@@ -13,6 +13,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_device.h"
+#include "intel_display_irq.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -398,3 +399,33 @@ void intel_cmtg_enable_ddi(const struct intel_crtc_state *crtc_state)
 	crtc->cmtg.enabled = true;
 	drm_dbg_kms(display->drm, "CMTG: %s enabled\n", transcoder_name(cpu_transcoder));
 }
+
+static void intel_cmtg_mask_interrupt(const struct intel_crtc_state *crtc_state, bool mask)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 interrupt_mask = 0;
+
+	if (!intel_cmtg_is_supported(crtc_state))
+		return;
+
+	if (cpu_transcoder == TRANSCODER_A)
+		interrupt_mask = CMTG_VBLANK_A | CMTG_DELAYED_VBLANK_A | CMTG_VSYNC_A;
+	else if (cpu_transcoder == TRANSCODER_B)
+		interrupt_mask = CMTG_VBLANK_B | CMTG_DELAYED_VBLANK_B | CMTG_VSYNC_B;
+
+	if (mask)
+		bdw_update_port_irq(display, interrupt_mask, 0);
+	else
+		bdw_update_port_irq(display, interrupt_mask, interrupt_mask);
+}
+
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	intel_cmtg_mask_interrupt(crtc_state, false);
+}
+
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state)
+{
+	intel_cmtg_mask_interrupt(crtc_state, true);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
index 79785afccc51..8fcb44d6398f 100644
--- a/drivers/gpu/drm/i915/display/intel_cmtg.h
+++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
@@ -21,5 +21,7 @@ void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
 void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
 void intel_cmtg_sanitize(struct intel_display *display);
 bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_enable_interrupt(const struct intel_crtc_state *crtc_state);
+void intel_cmtg_disable_interrupt(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_CMTG_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 30bc209d8fb6..3d683d290fa6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1065,6 +1065,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	if (!crtc->cmtg.enabled && intel_vrr_is_fixed_rr(new_crtc_state)) {
 		intel_cmtg_enable_sync(new_crtc_state);
 		intel_cmtg_enable_ddi(new_crtc_state);
+		intel_cmtg_enable_interrupt(new_crtc_state);
 	}
 }
 
@@ -6873,8 +6874,10 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
 
-	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc))
+	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc)) {
 		intel_cmtg_disable(new_crtc_state);
+		intel_cmtg_disable_interrupt(new_crtc_state);
+	}
 }
 
 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 70c1bba7c0a8..6754c131b007 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1467,6 +1467,18 @@ void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl)
 				found = true;
 			}
 
+			if (DISPLAY_VER(display) == 35) {
+				if (iir & (CMTG_VBLANK_A | CMTG_VSYNC_A | CMTG_DELAYED_VBLANK_A)) {
+					intel_handle_vblank(display, PIPE_A);
+					found = true;
+				}
+
+				if (iir & (CMTG_VBLANK_B | CMTG_VSYNC_B | CMTG_DELAYED_VBLANK_B)) {
+					intel_handle_vblank(display, PIPE_B);
+					found = true;
+				}
+			}
+
 			if (DISPLAY_VER(display) >= 11) {
 				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index dada8dc27ea4..0a641daf22c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1427,6 +1427,12 @@
 #define  GEN9_AUX_CHANNEL_B		(1 << 25)
 #define  DSI1_TE			(1 << 24)
 #define  DSI0_TE			(1 << 23)
+#define  CMTG_VSYNC_B			(1 << 19)
+#define  CMTG_DELAYED_VBLANK_B		(1 << 18)
+#define  CMTG_VBLANK_B			(1 << 17)
+#define  CMTG_VSYNC_A			(1 << 16)
+#define  CMTG_DELAYED_VBLANK_A		(1 << 15)
+#define  CMTG_VBLANK_A			(1 << 14)
 #define  GEN8_DE_PORT_HOTPLUG(hpd_pin)	REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
 #define  BXT_DE_PORT_HOTPLUG_MASK	(GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
 					 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
-- 
2.29.0

[PATCH v4 12/13] drm/i915/cmtg: Disable CMTG if dc3co is not allowed

[Animesh Manna]

DC3co entry condition can change dymamically and disable
CMTG if entry condition is not met for DC3co.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 3d683d290fa6..9c5985ae89e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6874,7 +6874,8 @@ static void intel_update_crtc(struct intel_atomic_state *state,
 	    old_crtc_state->inherited)
 		intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
 
-	if (crtc->cmtg.enabled && intel_crtc_vrr_enabling(state, crtc)) {
+	if (crtc->cmtg.enabled && (intel_crtc_vrr_enabling(state, crtc) ||
+				   !intel_cmtg_is_allowed(new_crtc_state))) {
 		intel_cmtg_disable(new_crtc_state);
 		intel_cmtg_disable_interrupt(new_crtc_state);
 	}
-- 
2.29.0

[PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm

[Animesh Manna]

Set the target_dc_state in specific scenarios such as LOBF/PSR2/PR-ALPM,
where DC3CO enablement will be targeted, allowing CMTG to be programmed.
DC3CO enablement will be implemented in a separate patch series.

Note: This patch currently added to test cmtg and need to revisit once
DC3co enablement design in finilized.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index b8b6d62fb275..5de6cfde8bf5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7342,6 +7342,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 				 struct intel_crtc_state *crtc_state,
 				 struct drm_connector_state *conn_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	int ret;
 
@@ -7353,6 +7354,13 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 
 	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
 
+	if (DISPLAY_VER(display) >= 35 && intel_dp_is_edp(intel_dp) &&
+	    (crtc_state->has_lobf || crtc_state->has_sel_update ||
+	     crtc_state->has_panel_replay))
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
+	else
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
+
 	return 0;
 }
 
-- 
2.29.0

✓ CI.KUnit: success for CMTG enablement (rev5)

[Patchwork]

== Series Details ==

Series: CMTG enablement (rev5)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[11:15:28] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:15:33] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:16:04] Starting KUnit Kernel (1/1)...
[11:16:04] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:16:04] ================== guc_buf (11 subtests) ===================
[11:16:04] [PASSED] test_smallest
[11:16:04] [PASSED] test_largest
[11:16:04] [PASSED] test_granular
[11:16:04] [PASSED] test_unique
[11:16:04] [PASSED] test_overlap
[11:16:04] [PASSED] test_reusable
[11:16:04] [PASSED] test_too_big
[11:16:04] [PASSED] test_flush
[11:16:04] [PASSED] test_lookup
[11:16:04] [PASSED] test_data
[11:16:04] [PASSED] test_class
[11:16:04] ===================== [PASSED] guc_buf =====================
[11:16:04] =================== guc_dbm (7 subtests) ===================
[11:16:04] [PASSED] test_empty
[11:16:04] [PASSED] test_default
[11:16:04] ======================== test_size  ========================
[11:16:04] [PASSED] 4
[11:16:04] [PASSED] 8
[11:16:04] [PASSED] 32
[11:16:04] [PASSED] 256
[11:16:04] ==================== [PASSED] test_size ====================
[11:16:04] ======================= test_reuse  ========================
[11:16:04] [PASSED] 4
[11:16:04] [PASSED] 8
[11:16:04] [PASSED] 32
[11:16:04] [PASSED] 256
[11:16:04] =================== [PASSED] test_reuse ====================
[11:16:04] =================== test_range_overlap  ====================
[11:16:04] [PASSED] 4
[11:16:04] [PASSED] 8
[11:16:04] [PASSED] 32
[11:16:04] [PASSED] 256
[11:16:04] =============== [PASSED] test_range_overlap ================
[11:16:04] =================== test_range_compact  ====================
[11:16:04] [PASSED] 4
[11:16:04] [PASSED] 8
[11:16:04] [PASSED] 32
[11:16:04] [PASSED] 256
[11:16:04] =============== [PASSED] test_range_compact ================
[11:16:04] ==================== test_range_spare  =====================
[11:16:04] [PASSED] 4
[11:16:04] [PASSED] 8
[11:16:04] [PASSED] 32
[11:16:04] [PASSED] 256
[11:16:04] ================ [PASSED] test_range_spare =================
[11:16:04] ===================== [PASSED] guc_dbm =====================
[11:16:04] =================== guc_idm (6 subtests) ===================
[11:16:04] [PASSED] bad_init
[11:16:04] [PASSED] no_init
[11:16:04] [PASSED] init_fini
[11:16:04] [PASSED] check_used
[11:16:04] [PASSED] check_quota
[11:16:04] [PASSED] check_all
[11:16:04] ===================== [PASSED] guc_idm =====================
[11:16:04] ================== no_relay (3 subtests) ===================
[11:16:04] [PASSED] xe_drops_guc2pf_if_not_ready
[11:16:04] [PASSED] xe_drops_guc2vf_if_not_ready
[11:16:04] [PASSED] xe_rejects_send_if_not_ready
[11:16:04] ==================== [PASSED] no_relay =====================
[11:16:04] ================== pf_relay (14 subtests) ==================
[11:16:04] [PASSED] pf_rejects_guc2pf_too_short
[11:16:04] [PASSED] pf_rejects_guc2pf_too_long
[11:16:04] [PASSED] pf_rejects_guc2pf_no_payload
[11:16:04] [PASSED] pf_fails_no_payload
[11:16:04] [PASSED] pf_fails_bad_origin
[11:16:04] [PASSED] pf_fails_bad_type
[11:16:04] [PASSED] pf_txn_reports_error
[11:16:04] [PASSED] pf_txn_sends_pf2guc
[11:16:04] [PASSED] pf_sends_pf2guc
[11:16:04] [SKIPPED] pf_loopback_nop
[11:16:04] [SKIPPED] pf_loopback_echo
[11:16:04] [SKIPPED] pf_loopback_fail
[11:16:04] [SKIPPED] pf_loopback_busy
[11:16:04] [SKIPPED] pf_loopback_retry
[11:16:04] ==================== [PASSED] pf_relay =====================
[11:16:04] ================== vf_relay (3 subtests) ===================
[11:16:04] [PASSED] vf_rejects_guc2vf_too_short
[11:16:04] [PASSED] vf_rejects_guc2vf_too_long
[11:16:04] [PASSED] vf_rejects_guc2vf_no_payload
[11:16:04] ==================== [PASSED] vf_relay =====================
[11:16:04] ================ pf_gt_config (9 subtests) =================
[11:16:04] [PASSED] fair_contexts_1vf
[11:16:04] [PASSED] fair_doorbells_1vf
[11:16:04] [PASSED] fair_ggtt_1vf
[11:16:04] ====================== fair_vram_1vf  ======================
[11:16:04] [PASSED] 3.50 GiB
[11:16:04] [PASSED] 11.5 GiB
[11:16:04] [PASSED] 15.5 GiB
[11:16:04] [PASSED] 31.5 GiB
[11:16:04] [PASSED] 63.5 GiB
[11:16:04] [PASSED] 1.91 GiB
[11:16:04] ================== [PASSED] fair_vram_1vf ==================
[11:16:04] ================ fair_vram_1vf_admin_only  =================
[11:16:04] [PASSED] 3.50 GiB
[11:16:04] [PASSED] 11.5 GiB
[11:16:04] [PASSED] 15.5 GiB
[11:16:04] [PASSED] 31.5 GiB
[11:16:04] [PASSED] 63.5 GiB
[11:16:04] [PASSED] 1.91 GiB
[11:16:04] ============ [PASSED] fair_vram_1vf_admin_only =============
[11:16:04] ====================== fair_contexts  ======================
[11:16:04] [PASSED] 1 VF
[11:16:04] [PASSED] 2 VFs
[11:16:04] [PASSED] 3 VFs
[11:16:04] [PASSED] 4 VFs
[11:16:04] [PASSED] 5 VFs
[11:16:04] [PASSED] 6 VFs
[11:16:04] [PASSED] 7 VFs
[11:16:04] [PASSED] 8 VFs
[11:16:04] [PASSED] 9 VFs
[11:16:04] [PASSED] 10 VFs
[11:16:04] [PASSED] 11 VFs
[11:16:04] [PASSED] 12 VFs
[11:16:04] [PASSED] 13 VFs
[11:16:04] [PASSED] 14 VFs
[11:16:04] [PASSED] 15 VFs
[11:16:04] [PASSED] 16 VFs
[11:16:04] [PASSED] 17 VFs
[11:16:04] [PASSED] 18 VFs
[11:16:04] [PASSED] 19 VFs
[11:16:04] [PASSED] 20 VFs
[11:16:04] [PASSED] 21 VFs
[11:16:04] [PASSED] 22 VFs
[11:16:04] [PASSED] 23 VFs
[11:16:04] [PASSED] 24 VFs
[11:16:04] [PASSED] 25 VFs
[11:16:04] [PASSED] 26 VFs
[11:16:04] [PASSED] 27 VFs
[11:16:04] [PASSED] 28 VFs
[11:16:04] [PASSED] 29 VFs
[11:16:04] [PASSED] 30 VFs
[11:16:04] [PASSED] 31 VFs
[11:16:04] [PASSED] 32 VFs
[11:16:04] [PASSED] 33 VFs
[11:16:04] [PASSED] 34 VFs
[11:16:04] [PASSED] 35 VFs
[11:16:04] [PASSED] 36 VFs
[11:16:04] [PASSED] 37 VFs
[11:16:04] [PASSED] 38 VFs
[11:16:04] [PASSED] 39 VFs
[11:16:04] [PASSED] 40 VFs
[11:16:04] [PASSED] 41 VFs
[11:16:04] [PASSED] 42 VFs
[11:16:04] [PASSED] 43 VFs
[11:16:04] [PASSED] 44 VFs
[11:16:04] [PASSED] 45 VFs
[11:16:04] [PASSED] 46 VFs
[11:16:04] [PASSED] 47 VFs
[11:16:04] [PASSED] 48 VFs
[11:16:04] [PASSED] 49 VFs
[11:16:04] [PASSED] 50 VFs
[11:16:04] [PASSED] 51 VFs
[11:16:04] [PASSED] 52 VFs
[11:16:04] [PASSED] 53 VFs
[11:16:04] [PASSED] 54 VFs
[11:16:04] [PASSED] 55 VFs
[11:16:04] [PASSED] 56 VFs
[11:16:04] [PASSED] 57 VFs
[11:16:04] [PASSED] 58 VFs
[11:16:04] [PASSED] 59 VFs
[11:16:04] [PASSED] 60 VFs
[11:16:04] [PASSED] 61 VFs
[11:16:04] [PASSED] 62 VFs
[11:16:04] [PASSED] 63 VFs
[11:16:04] ================== [PASSED] fair_contexts ==================
[11:16:04] ===================== fair_doorbells  ======================
[11:16:04] [PASSED] 1 VF
[11:16:04] [PASSED] 2 VFs
[11:16:04] [PASSED] 3 VFs
[11:16:04] [PASSED] 4 VFs
[11:16:04] [PASSED] 5 VFs
[11:16:04] [PASSED] 6 VFs
[11:16:04] [PASSED] 7 VFs
[11:16:04] [PASSED] 8 VFs
[11:16:04] [PASSED] 9 VFs
[11:16:04] [PASSED] 10 VFs
[11:16:04] [PASSED] 11 VFs
[11:16:04] [PASSED] 12 VFs
[11:16:04] [PASSED] 13 VFs
[11:16:04] [PASSED] 14 VFs
[11:16:04] [PASSED] 15 VFs
[11:16:04] [PASSED] 16 VFs
[11:16:04] [PASSED] 17 VFs
[11:16:04] [PASSED] 18 VFs
[11:16:04] [PASSED] 19 VFs
[11:16:04] [PASSED] 20 VFs
[11:16:04] [PASSED] 21 VFs
[11:16:04] [PASSED] 22 VFs
[11:16:04] [PASSED] 23 VFs
[11:16:04] [PASSED] 24 VFs
[11:16:04] [PASSED] 25 VFs
[11:16:04] [PASSED] 26 VFs
[11:16:04] [PASSED] 27 VFs
[11:16:04] [PASSED] 28 VFs
[11:16:04] [PASSED] 29 VFs
[11:16:04] [PASSED] 30 VFs
[11:16:04] [PASSED] 31 VFs
[11:16:04] [PASSED] 32 VFs
[11:16:04] [PASSED] 33 VFs
[11:16:04] [PASSED] 34 VFs
[11:16:04] [PASSED] 35 VFs
[11:16:04] [PASSED] 36 VFs
[11:16:04] [PASSED] 37 VFs
[11:16:04] [PASSED] 38 VFs
[11:16:04] [PASSED] 39 VFs
[11:16:04] [PASSED] 40 VFs
[11:16:04] [PASSED] 41 VFs
[11:16:04] [PASSED] 42 VFs
[11:16:04] [PASSED] 43 VFs
[11:16:04] [PASSED] 44 VFs
[11:16:04] [PASSED] 45 VFs
[11:16:04] [PASSED] 46 VFs
[11:16:04] [PASSED] 47 VFs
[11:16:04] [PASSED] 48 VFs
[11:16:04] [PASSED] 49 VFs
[11:16:04] [PASSED] 50 VFs
[11:16:04] [PASSED] 51 VFs
[11:16:04] [PASSED] 52 VFs
[11:16:04] [PASSED] 53 VFs
[11:16:04] [PASSED] 54 VFs
[11:16:04] [PASSED] 55 VFs
[11:16:04] [PASSED] 56 VFs
[11:16:04] [PASSED] 57 VFs
[11:16:04] [PASSED] 58 VFs
[11:16:04] [PASSED] 59 VFs
[11:16:04] [PASSED] 60 VFs
[11:16:04] [PASSED] 61 VFs
[11:16:04] [PASSED] 62 VFs
[11:16:04] [PASSED] 63 VFs
[11:16:04] ================= [PASSED] fair_doorbells ==================
[11:16:04] ======================== fair_ggtt  ========================
[11:16:04] [PASSED] 1 VF
[11:16:04] [PASSED] 2 VFs
[11:16:04] [PASSED] 3 VFs
[11:16:04] [PASSED] 4 VFs
[11:16:04] [PASSED] 5 VFs
[11:16:04] [PASSED] 6 VFs
[11:16:04] [PASSED] 7 VFs
[11:16:04] [PASSED] 8 VFs
[11:16:04] [PASSED] 9 VFs
[11:16:04] [PASSED] 10 VFs
[11:16:04] [PASSED] 11 VFs
[11:16:04] [PASSED] 12 VFs
[11:16:04] [PASSED] 13 VFs
[11:16:04] [PASSED] 14 VFs
[11:16:04] [PASSED] 15 VFs
[11:16:04] [PASSED] 16 VFs
[11:16:04] [PASSED] 17 VFs
[11:16:04] [PASSED] 18 VFs
[11:16:04] [PASSED] 19 VFs
[11:16:04] [PASSED] 20 VFs
[11:16:04] [PASSED] 21 VFs
[11:16:04] [PASSED] 22 VFs
[11:16:04] [PASSED] 23 VFs
[11:16:04] [PASSED] 24 VFs
[11:16:04] [PASSED] 25 VFs
[11:16:04] [PASSED] 26 VFs
[11:16:04] [PASSED] 27 VFs
[11:16:04] [PASSED] 28 VFs
[11:16:04] [PASSED] 29 VFs
[11:16:04] [PASSED] 30 VFs
[11:16:04] [PASSED] 31 VFs
[11:16:04] [PASSED] 32 VFs
[11:16:04] [PASSED] 33 VFs
[11:16:04] [PASSED] 34 VFs
[11:16:04] [PASSED] 35 VFs
[11:16:04] [PASSED] 36 VFs
[11:16:04] [PASSED] 37 VFs
[11:16:04] [PASSED] 38 VFs
[11:16:04] [PASSED] 39 VFs
[11:16:04] [PASSED] 40 VFs
[11:16:04] [PASSED] 41 VFs
[11:16:04] [PASSED] 42 VFs
[11:16:04] [PASSED] 43 VFs
[11:16:04] [PASSED] 44 VFs
[11:16:04] [PASSED] 45 VFs
[11:16:04] [PASSED] 46 VFs
[11:16:04] [PASSED] 47 VFs
[11:16:04] [PASSED] 48 VFs
[11:16:04] [PASSED] 49 VFs
[11:16:04] [PASSED] 50 VFs
[11:16:04] [PASSED] 51 VFs
[11:16:04] [PASSED] 52 VFs
[11:16:04] [PASSED] 53 VFs
[11:16:04] [PASSED] 54 VFs
[11:16:04] [PASSED] 55 VFs
[11:16:04] [PASSED] 56 VFs
[11:16:04] [PASSED] 57 VFs
[11:16:04] [PASSED] 58 VFs
[11:16:04] [PASSED] 59 VFs
[11:16:04] [PASSED] 60 VFs
[11:16:04] [PASSED] 61 VFs
[11:16:04] [PASSED] 62 VFs
[11:16:04] [PASSED] 63 VFs
[11:16:04] ==================== [PASSED] fair_ggtt ====================
[11:16:04] ======================== fair_vram  ========================
[11:16:04] [PASSED] 1 VF
[11:16:04] [PASSED] 2 VFs
[11:16:04] [PASSED] 3 VFs
[11:16:04] [PASSED] 4 VFs
[11:16:04] [PASSED] 5 VFs
[11:16:04] [PASSED] 6 VFs
[11:16:04] [PASSED] 7 VFs
[11:16:04] [PASSED] 8 VFs
[11:16:04] [PASSED] 9 VFs
[11:16:04] [PASSED] 10 VFs
[11:16:04] [PASSED] 11 VFs
[11:16:04] [PASSED] 12 VFs
[11:16:04] [PASSED] 13 VFs
[11:16:04] [PASSED] 14 VFs
[11:16:04] [PASSED] 15 VFs
[11:16:04] [PASSED] 16 VFs
[11:16:04] [PASSED] 17 VFs
[11:16:04] [PASSED] 18 VFs
[11:16:04] [PASSED] 19 VFs
[11:16:04] [PASSED] 20 VFs
[11:16:04] [PASSED] 21 VFs
[11:16:04] [PASSED] 22 VFs
[11:16:04] [PASSED] 23 VFs
[11:16:04] [PASSED] 24 VFs
[11:16:04] [PASSED] 25 VFs
[11:16:04] [PASSED] 26 VFs
[11:16:04] [PASSED] 27 VFs
[11:16:04] [PASSED] 28 VFs
[11:16:04] [PASSED] 29 VFs
[11:16:04] [PASSED] 30 VFs
[11:16:04] [PASSED] 31 VFs
[11:16:04] [PASSED] 32 VFs
[11:16:04] [PASSED] 33 VFs
[11:16:04] [PASSED] 34 VFs
[11:16:04] [PASSED] 35 VFs
[11:16:04] [PASSED] 36 VFs
[11:16:04] [PASSED] 37 VFs
[11:16:04] [PASSED] 38 VFs
[11:16:04] [PASSED] 39 VFs
[11:16:04] [PASSED] 40 VFs
[11:16:04] [PASSED] 41 VFs
[11:16:04] [PASSED] 42 VFs
[11:16:04] [PASSED] 43 VFs
[11:16:04] [PASSED] 44 VFs
[11:16:04] [PASSED] 45 VFs
[11:16:04] [PASSED] 46 VFs
[11:16:04] [PASSED] 47 VFs
[11:16:04] [PASSED] 48 VFs
[11:16:04] [PASSED] 49 VFs
[11:16:04] [PASSED] 50 VFs
[11:16:04] [PASSED] 51 VFs
[11:16:04] [PASSED] 52 VFs
[11:16:04] [PASSED] 53 VFs
[11:16:04] [PASSED] 54 VFs
[11:16:04] [PASSED] 55 VFs
[11:16:04] [PASSED] 56 VFs
[11:16:04] [PASSED] 57 VFs
[11:16:04] [PASSED] 58 VFs
[11:16:04] [PASSED] 59 VFs
[11:16:04] [PASSED] 60 VFs
[11:16:04] [PASSED] 61 VFs
[11:16:04] [PASSED] 62 VFs
[11:16:04] [PASSED] 63 VFs
[11:16:04] ==================== [PASSED] fair_vram ====================
[11:16:04] ================== [PASSED] pf_gt_config ===================
[11:16:04] ===================== lmtt (1 subtest) =====================
[11:16:04] ======================== test_ops  =========================
[11:16:04] [PASSED] 2-level
[11:16:04] [PASSED] multi-level
[11:16:04] ==================== [PASSED] test_ops =====================
[11:16:04] ====================== [PASSED] lmtt =======================
[11:16:04] ================= pf_service (11 subtests) =================
[11:16:04] [PASSED] pf_negotiate_any
[11:16:04] [PASSED] pf_negotiate_base_match
[11:16:04] [PASSED] pf_negotiate_base_newer
[11:16:04] [PASSED] pf_negotiate_base_next
[11:16:04] [SKIPPED] pf_negotiate_base_older
[11:16:04] [PASSED] pf_negotiate_base_prev
[11:16:04] [PASSED] pf_negotiate_latest_match
[11:16:04] [PASSED] pf_negotiate_latest_newer
[11:16:04] [PASSED] pf_negotiate_latest_next
[11:16:04] [SKIPPED] pf_negotiate_latest_older
[11:16:04] [SKIPPED] pf_negotiate_latest_prev
[11:16:04] =================== [PASSED] pf_service ====================
[11:16:04] ================= xe_guc_g2g (2 subtests) ==================
[11:16:04] ============== xe_live_guc_g2g_kunit_default  ==============
[11:16:04] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[11:16:04] ============== xe_live_guc_g2g_kunit_allmem  ===============
[11:16:04] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[11:16:04] =================== [SKIPPED] xe_guc_g2g ===================
[11:16:04] =================== xe_mocs (2 subtests) ===================
[11:16:04] ================ xe_live_mocs_kernel_kunit  ================
[11:16:04] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[11:16:04] ================ xe_live_mocs_reset_kunit  =================
[11:16:04] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[11:16:04] ==================== [SKIPPED] xe_mocs =====================
[11:16:04] ================= xe_migrate (2 subtests) ==================
[11:16:04] ================= xe_migrate_sanity_kunit  =================
[11:16:04] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[11:16:04] ================== xe_validate_ccs_kunit  ==================
[11:16:04] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[11:16:04] =================== [SKIPPED] xe_migrate ===================
[11:16:04] ================== xe_dma_buf (1 subtest) ==================
[11:16:04] ==================== xe_dma_buf_kunit  =====================
[11:16:04] ================ [SKIPPED] xe_dma_buf_kunit ================
[11:16:04] =================== [SKIPPED] xe_dma_buf ===================
[11:16:04] ================= xe_bo_shrink (1 subtest) =================
[11:16:04] =================== xe_bo_shrink_kunit  ====================
[11:16:04] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[11:16:04] ================== [SKIPPED] xe_bo_shrink ==================
[11:16:04] ==================== xe_bo (2 subtests) ====================
[11:16:04] ================== xe_ccs_migrate_kunit  ===================
[11:16:04] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[11:16:04] ==================== xe_bo_evict_kunit  ====================
[11:16:04] =============== [SKIPPED] xe_bo_evict_kunit ================
[11:16:04] ===================== [SKIPPED] xe_bo ======================
[11:16:04] ==================== args (13 subtests) ====================
[11:16:04] [PASSED] count_args_test
[11:16:04] [PASSED] call_args_example
[11:16:04] [PASSED] call_args_test
[11:16:04] [PASSED] drop_first_arg_example
[11:16:04] [PASSED] drop_first_arg_test
[11:16:04] [PASSED] first_arg_example
[11:16:04] [PASSED] first_arg_test
[11:16:04] [PASSED] last_arg_example
[11:16:04] [PASSED] last_arg_test
[11:16:04] [PASSED] pick_arg_example
[11:16:04] [PASSED] if_args_example
[11:16:04] [PASSED] if_args_test
[11:16:04] [PASSED] sep_comma_example
[11:16:04] ====================== [PASSED] args =======================
[11:16:04] =================== xe_pci (3 subtests) ====================
[11:16:04] ==================== check_graphics_ip  ====================
[11:16:04] [PASSED] 12.00 Xe_LP
[11:16:04] [PASSED] 12.10 Xe_LP+
[11:16:04] [PASSED] 12.55 Xe_HPG
[11:16:04] [PASSED] 12.60 Xe_HPC
[11:16:04] [PASSED] 12.70 Xe_LPG
[11:16:04] [PASSED] 12.71 Xe_LPG
[11:16:04] [PASSED] 12.74 Xe_LPG+
[11:16:04] [PASSED] 20.01 Xe2_HPG
[11:16:04] [PASSED] 20.02 Xe2_HPG
[11:16:04] [PASSED] 20.04 Xe2_LPG
[11:16:04] [PASSED] 30.00 Xe3_LPG
[11:16:04] [PASSED] 30.01 Xe3_LPG
[11:16:04] [PASSED] 30.03 Xe3_LPG
[11:16:04] [PASSED] 30.04 Xe3_LPG
[11:16:04] [PASSED] 30.05 Xe3_LPG
[11:16:04] [PASSED] 35.10 Xe3p_LPG
[11:16:04] [PASSED] 35.11 Xe3p_XPC
[11:16:04] ================ [PASSED] check_graphics_ip ================
[11:16:04] ===================== check_media_ip  ======================
[11:16:04] [PASSED] 12.00 Xe_M
[11:16:04] [PASSED] 12.55 Xe_HPM
[11:16:04] [PASSED] 13.00 Xe_LPM+
[11:16:04] [PASSED] 13.01 Xe2_HPM
[11:16:04] [PASSED] 20.00 Xe2_LPM
[11:16:04] [PASSED] 30.00 Xe3_LPM
[11:16:04] [PASSED] 30.02 Xe3_LPM
[11:16:04] [PASSED] 35.00 Xe3p_LPM
[11:16:04] [PASSED] 35.03 Xe3p_HPM
[11:16:04] ================= [PASSED] check_media_ip ==================
[11:16:04] =================== check_platform_desc  ===================
[11:16:04] [PASSED] 0x9A60 (TIGERLAKE)
[11:16:04] [PASSED] 0x9A68 (TIGERLAKE)
[11:16:04] [PASSED] 0x9A70 (TIGERLAKE)
[11:16:04] [PASSED] 0x9A40 (TIGERLAKE)
[11:16:04] [PASSED] 0x9A49 (TIGERLAKE)
[11:16:04] [PASSED] 0x9A59 (TIGERLAKE)
[11:16:04] [PASSED] 0x9A78 (TIGERLAKE)
[11:16:04] [PASSED] 0x9AC0 (TIGERLAKE)
[11:16:04] [PASSED] 0x9AC9 (TIGERLAKE)
[11:16:04] [PASSED] 0x9AD9 (TIGERLAKE)
[11:16:04] [PASSED] 0x9AF8 (TIGERLAKE)
[11:16:04] [PASSED] 0x4C80 (ROCKETLAKE)
[11:16:04] [PASSED] 0x4C8A (ROCKETLAKE)
[11:16:04] [PASSED] 0x4C8B (ROCKETLAKE)
[11:16:04] [PASSED] 0x4C8C (ROCKETLAKE)
[11:16:04] [PASSED] 0x4C90 (ROCKETLAKE)
[11:16:04] [PASSED] 0x4C9A (ROCKETLAKE)
[11:16:04] [PASSED] 0x4680 (ALDERLAKE_S)
[11:16:04] [PASSED] 0x4682 (ALDERLAKE_S)
[11:16:04] [PASSED] 0x4688 (ALDERLAKE_S)
[11:16:04] [PASSED] 0x468A (ALDERLAKE_S)
[11:16:04] [PASSED] 0x468B (ALDERLAKE_S)
[11:16:04] [PASSED] 0x4690 (ALDERLAKE_S)
[11:16:04] [PASSED] 0x4692 (ALDERLAKE_S)
[11:16:04] [PASSED] 0x4693 (ALDERLAKE_S)
[11:16:04] [PASSED] 0x46A0 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46A1 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46A2 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46A3 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46A6 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46A8 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46AA (ALDERLAKE_P)
[11:16:04] [PASSED] 0x462A (ALDERLAKE_P)
[11:16:04] [PASSED] 0x4626 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x4628 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46B0 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46B1 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46B2 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46B3 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46C0 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46C1 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46C2 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46C3 (ALDERLAKE_P)
[11:16:04] [PASSED] 0x46D0 (ALDERLAKE_N)
[11:16:04] [PASSED] 0x46D1 (ALDERLAKE_N)
[11:16:04] [PASSED] 0x46D2 (ALDERLAKE_N)
[11:16:04] [PASSED] 0x46D3 (ALDERLAKE_N)
[11:16:04] [PASSED] 0x46D4 (ALDERLAKE_N)
[11:16:04] [PASSED] 0xA721 (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7A1 (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7A9 (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7AC (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7AD (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA720 (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7A0 (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7A8 (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7AA (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA7AB (ALDERLAKE_P)
[11:16:04] [PASSED] 0xA780 (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA781 (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA782 (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA783 (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA788 (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA789 (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA78A (ALDERLAKE_S)
[11:16:04] [PASSED] 0xA78B (ALDERLAKE_S)
[11:16:04] [PASSED] 0x4905 (DG1)
[11:16:04] [PASSED] 0x4906 (DG1)
[11:16:04] [PASSED] 0x4907 (DG1)
[11:16:04] [PASSED] 0x4908 (DG1)
[11:16:04] [PASSED] 0x4909 (DG1)
[11:16:04] [PASSED] 0x56C0 (DG2)
[11:16:04] [PASSED] 0x56C2 (DG2)
[11:16:04] [PASSED] 0x56C1 (DG2)
[11:16:04] [PASSED] 0x7D51 (METEORLAKE)
[11:16:04] [PASSED] 0x7DD1 (METEORLAKE)
[11:16:04] [PASSED] 0x7D41 (METEORLAKE)
[11:16:04] [PASSED] 0x7D67 (METEORLAKE)
[11:16:04] [PASSED] 0xB640 (METEORLAKE)
[11:16:04] [PASSED] 0x56A0 (DG2)
[11:16:04] [PASSED] 0x56A1 (DG2)
[11:16:04] [PASSED] 0x56A2 (DG2)
[11:16:04] [PASSED] 0x56BE (DG2)
[11:16:04] [PASSED] 0x56BF (DG2)
[11:16:04] [PASSED] 0x5690 (DG2)
[11:16:04] [PASSED] 0x5691 (DG2)
[11:16:04] [PASSED] 0x5692 (DG2)
[11:16:04] [PASSED] 0x56A5 (DG2)
[11:16:04] [PASSED] 0x56A6 (DG2)
[11:16:04] [PASSED] 0x56B0 (DG2)
[11:16:04] [PASSED] 0x56B1 (DG2)
[11:16:04] [PASSED] 0x56BA (DG2)
[11:16:04] [PASSED] 0x56BB (DG2)
[11:16:04] [PASSED] 0x56BC (DG2)
[11:16:04] [PASSED] 0x56BD (DG2)
[11:16:04] [PASSED] 0x5693 (DG2)
[11:16:04] [PASSED] 0x5694 (DG2)
[11:16:04] [PASSED] 0x5695 (DG2)
[11:16:04] [PASSED] 0x56A3 (DG2)
[11:16:04] [PASSED] 0x56A4 (DG2)
[11:16:04] [PASSED] 0x56B2 (DG2)
[11:16:04] [PASSED] 0x56B3 (DG2)
[11:16:04] [PASSED] 0x5696 (DG2)
[11:16:04] [PASSED] 0x5697 (DG2)
[11:16:04] [PASSED] 0xB69 (PVC)
[11:16:04] [PASSED] 0xB6E (PVC)
[11:16:04] [PASSED] 0xBD4 (PVC)
[11:16:04] [PASSED] 0xBD5 (PVC)
[11:16:04] [PASSED] 0xBD6 (PVC)
[11:16:04] [PASSED] 0xBD7 (PVC)
[11:16:04] [PASSED] 0xBD8 (PVC)
[11:16:04] [PASSED] 0xBD9 (PVC)
[11:16:04] [PASSED] 0xBDA (PVC)
[11:16:04] [PASSED] 0xBDB (PVC)
[11:16:04] [PASSED] 0xBE0 (PVC)
[11:16:04] [PASSED] 0xBE1 (PVC)
[11:16:04] [PASSED] 0xBE5 (PVC)
[11:16:04] [PASSED] 0x7D40 (METEORLAKE)
[11:16:04] [PASSED] 0x7D45 (METEORLAKE)
[11:16:04] [PASSED] 0x7D55 (METEORLAKE)
[11:16:04] [PASSED] 0x7D60 (METEORLAKE)
[11:16:04] [PASSED] 0x7DD5 (METEORLAKE)
[11:16:04] [PASSED] 0x6420 (LUNARLAKE)
[11:16:04] [PASSED] 0x64A0 (LUNARLAKE)
[11:16:04] [PASSED] 0x64B0 (LUNARLAKE)
[11:16:04] [PASSED] 0xE202 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE209 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE20B (BATTLEMAGE)
[11:16:04] [PASSED] 0xE20C (BATTLEMAGE)
[11:16:04] [PASSED] 0xE20D (BATTLEMAGE)
[11:16:04] [PASSED] 0xE210 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE211 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE212 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE216 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE220 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE221 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE222 (BATTLEMAGE)
[11:16:04] [PASSED] 0xE223 (BATTLEMAGE)
[11:16:04] [PASSED] 0xB080 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB081 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB082 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB083 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB084 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB085 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB086 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB087 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB08F (PANTHERLAKE)
[11:16:04] [PASSED] 0xB090 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB0A0 (PANTHERLAKE)
[11:16:04] [PASSED] 0xB0B0 (PANTHERLAKE)
[11:16:04] [PASSED] 0xFD80 (PANTHERLAKE)
[11:16:04] [PASSED] 0xFD81 (PANTHERLAKE)
[11:16:04] [PASSED] 0xD740 (NOVALAKE_S)
[11:16:04] [PASSED] 0xD741 (NOVALAKE_S)
[11:16:04] [PASSED] 0xD742 (NOVALAKE_S)
[11:16:04] [PASSED] 0xD743 (NOVALAKE_S)
[11:16:04] [PASSED] 0xD744 (NOVALAKE_S)
[11:16:04] [PASSED] 0xD745 (NOVALAKE_S)
[11:16:04] [PASSED] 0x674C (CRESCENTISLAND)
[11:16:04] [PASSED] 0xD750 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD751 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD752 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD753 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD754 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD755 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD756 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD757 (NOVALAKE_P)
[11:16:04] [PASSED] 0xD75F (NOVALAKE_P)
[11:16:04] =============== [PASSED] check_platform_desc ===============
[11:16:04] ===================== [PASSED] xe_pci ======================
[11:16:04] =================== xe_rtp (2 subtests) ====================
[11:16:04] =============== xe_rtp_process_to_sr_tests  ================
[11:16:04] [PASSED] coalesce-same-reg
[11:16:04] [PASSED] no-match-no-add
[11:16:04] [PASSED] match-or
[11:16:04] [PASSED] match-or-xfail
[11:16:04] [PASSED] no-match-no-add-multiple-rules
[11:16:04] [PASSED] two-regs-two-entries
[11:16:04] [PASSED] clr-one-set-other
[11:16:04] [PASSED] set-field
[11:16:04] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[11:16:04] [PASSED] conflict-not-disjoint
[11:16:04] [PASSED] conflict-reg-type
[11:16:04] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[11:16:04] ================== xe_rtp_process_tests  ===================
[11:16:04] [PASSED] active1
[11:16:04] [PASSED] active2
[11:16:04] [PASSED] active-inactive
[11:16:04] [PASSED] inactive-active
[11:16:04] [PASSED] inactive-1st_or_active-inactive
[11:16:04] [PASSED] inactive-2nd_or_active-inactive
[11:16:04] [PASSED] inactive-last_or_active-inactive
[11:16:04] [PASSED] inactive-no_or_active-inactive
[11:16:04] ============== [PASSED] xe_rtp_process_tests ===============
[11:16:04] ===================== [PASSED] xe_rtp ======================
[11:16:04] ==================== xe_wa (1 subtest) =====================
[11:16:04] ======================== xe_wa_gt  =========================
[11:16:04] [PASSED] TIGERLAKE B0
[11:16:04] [PASSED] DG1 A0
[11:16:04] [PASSED] DG1 B0
[11:16:04] [PASSED] ALDERLAKE_S A0
[11:16:04] [PASSED] ALDERLAKE_S B0
[11:16:04] [PASSED] ALDERLAKE_S C0
[11:16:04] [PASSED] ALDERLAKE_S D0
[11:16:04] [PASSED] ALDERLAKE_P A0
[11:16:04] [PASSED] ALDERLAKE_P B0
[11:16:04] [PASSED] ALDERLAKE_P C0
[11:16:04] [PASSED] ALDERLAKE_S RPLS D0
[11:16:04] [PASSED] ALDERLAKE_P RPLU E0
[11:16:04] [PASSED] DG2 G10 C0
[11:16:04] [PASSED] DG2 G11 B1
[11:16:04] [PASSED] DG2 G12 A1
[11:16:04] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:16:04] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[11:16:04] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[11:16:04] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[11:16:04] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[11:16:04] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[11:16:04] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[11:16:04] ==================== [PASSED] xe_wa_gt =====================
[11:16:04] ====================== [PASSED] xe_wa ======================
[11:16:04] ============================================================
[11:16:04] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[11:16:04] Elapsed time: 35.919s total, 4.257s configuring, 31.045s building, 0.606s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[11:16:04] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:16:06] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:16:30] Starting KUnit Kernel (1/1)...
[11:16:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:16:30] ============ drm_test_pick_cmdline (2 subtests) ============
[11:16:30] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[11:16:30] =============== drm_test_pick_cmdline_named  ===============
[11:16:30] [PASSED] NTSC
[11:16:30] [PASSED] NTSC-J
[11:16:30] [PASSED] PAL
[11:16:30] [PASSED] PAL-M
[11:16:30] =========== [PASSED] drm_test_pick_cmdline_named ===========
[11:16:30] ============== [PASSED] drm_test_pick_cmdline ==============
[11:16:30] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[11:16:30] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[11:16:30] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[11:16:30] =========== drm_validate_clone_mode (2 subtests) ===========
[11:16:30] ============== drm_test_check_in_clone_mode  ===============
[11:16:30] [PASSED] in_clone_mode
[11:16:30] [PASSED] not_in_clone_mode
[11:16:30] ========== [PASSED] drm_test_check_in_clone_mode ===========
[11:16:30] =============== drm_test_check_valid_clones  ===============
[11:16:30] [PASSED] not_in_clone_mode
[11:16:30] [PASSED] valid_clone
[11:16:30] [PASSED] invalid_clone
[11:16:30] =========== [PASSED] drm_test_check_valid_clones ===========
[11:16:30] ============= [PASSED] drm_validate_clone_mode =============
[11:16:30] ============= drm_validate_modeset (1 subtest) =============
[11:16:30] [PASSED] drm_test_check_connector_changed_modeset
[11:16:30] ============== [PASSED] drm_validate_modeset ===============
[11:16:30] ====== drm_test_bridge_get_current_state (2 subtests) ======
[11:16:30] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[11:16:30] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[11:16:30] ======== [PASSED] drm_test_bridge_get_current_state ========
[11:16:31] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[11:16:31] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[11:16:31] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[11:16:31] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[11:16:31] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[11:16:31] ============== drm_bridge_alloc (2 subtests) ===============
[11:16:31] [PASSED] drm_test_drm_bridge_alloc_basic
[11:16:31] [PASSED] drm_test_drm_bridge_alloc_get_put
[11:16:31] ================ [PASSED] drm_bridge_alloc =================
[11:16:31] ============= drm_cmdline_parser (40 subtests) =============
[11:16:31] [PASSED] drm_test_cmdline_force_d_only
[11:16:31] [PASSED] drm_test_cmdline_force_D_only_dvi
[11:16:31] [PASSED] drm_test_cmdline_force_D_only_hdmi
[11:16:31] [PASSED] drm_test_cmdline_force_D_only_not_digital
[11:16:31] [PASSED] drm_test_cmdline_force_e_only
[11:16:31] [PASSED] drm_test_cmdline_res
[11:16:31] [PASSED] drm_test_cmdline_res_vesa
[11:16:31] [PASSED] drm_test_cmdline_res_vesa_rblank
[11:16:31] [PASSED] drm_test_cmdline_res_rblank
[11:16:31] [PASSED] drm_test_cmdline_res_bpp
[11:16:31] [PASSED] drm_test_cmdline_res_refresh
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[11:16:31] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[11:16:31] [PASSED] drm_test_cmdline_res_margins_force_on
[11:16:31] [PASSED] drm_test_cmdline_res_vesa_margins
[11:16:31] [PASSED] drm_test_cmdline_name
[11:16:31] [PASSED] drm_test_cmdline_name_bpp
[11:16:31] [PASSED] drm_test_cmdline_name_option
[11:16:31] [PASSED] drm_test_cmdline_name_bpp_option
[11:16:31] [PASSED] drm_test_cmdline_rotate_0
[11:16:31] [PASSED] drm_test_cmdline_rotate_90
[11:16:31] [PASSED] drm_test_cmdline_rotate_180
[11:16:31] [PASSED] drm_test_cmdline_rotate_270
[11:16:31] [PASSED] drm_test_cmdline_hmirror
[11:16:31] [PASSED] drm_test_cmdline_vmirror
[11:16:31] [PASSED] drm_test_cmdline_margin_options
[11:16:31] [PASSED] drm_test_cmdline_multiple_options
[11:16:31] [PASSED] drm_test_cmdline_bpp_extra_and_option
[11:16:31] [PASSED] drm_test_cmdline_extra_and_option
[11:16:31] [PASSED] drm_test_cmdline_freestanding_options
[11:16:31] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[11:16:31] [PASSED] drm_test_cmdline_panel_orientation
[11:16:31] ================ drm_test_cmdline_invalid  =================
[11:16:31] [PASSED] margin_only
[11:16:31] [PASSED] interlace_only
[11:16:31] [PASSED] res_missing_x
[11:16:31] [PASSED] res_missing_y
[11:16:31] [PASSED] res_bad_y
[11:16:31] [PASSED] res_missing_y_bpp
[11:16:31] [PASSED] res_bad_bpp
[11:16:31] [PASSED] res_bad_refresh
[11:16:31] [PASSED] res_bpp_refresh_force_on_off
[11:16:31] [PASSED] res_invalid_mode
[11:16:31] [PASSED] res_bpp_wrong_place_mode
[11:16:31] [PASSED] name_bpp_refresh
[11:16:31] [PASSED] name_refresh
[11:16:31] [PASSED] name_refresh_wrong_mode
[11:16:31] [PASSED] name_refresh_invalid_mode
[11:16:31] [PASSED] rotate_multiple
[11:16:31] [PASSED] rotate_invalid_val
[11:16:31] [PASSED] rotate_truncated
[11:16:31] [PASSED] invalid_option
[11:16:31] [PASSED] invalid_tv_option
[11:16:31] [PASSED] truncated_tv_option
[11:16:31] ============ [PASSED] drm_test_cmdline_invalid =============
[11:16:31] =============== drm_test_cmdline_tv_options  ===============
[11:16:31] [PASSED] NTSC
[11:16:31] [PASSED] NTSC_443
[11:16:31] [PASSED] NTSC_J
[11:16:31] [PASSED] PAL
[11:16:31] [PASSED] PAL_M
[11:16:31] [PASSED] PAL_N
[11:16:31] [PASSED] SECAM
[11:16:31] [PASSED] MONO_525
[11:16:31] [PASSED] MONO_625
[11:16:31] =========== [PASSED] drm_test_cmdline_tv_options ===========
[11:16:31] =============== [PASSED] drm_cmdline_parser ================
[11:16:31] ========== drmm_connector_hdmi_init (20 subtests) ==========
[11:16:31] [PASSED] drm_test_connector_hdmi_init_valid
[11:16:31] [PASSED] drm_test_connector_hdmi_init_bpc_8
[11:16:31] [PASSED] drm_test_connector_hdmi_init_bpc_10
[11:16:31] [PASSED] drm_test_connector_hdmi_init_bpc_12
[11:16:31] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[11:16:31] [PASSED] drm_test_connector_hdmi_init_bpc_null
[11:16:31] [PASSED] drm_test_connector_hdmi_init_formats_empty
[11:16:31] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[11:16:31] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[11:16:31] [PASSED] supported_formats=0x9 yuv420_allowed=1
[11:16:31] [PASSED] supported_formats=0x9 yuv420_allowed=0
[11:16:31] [PASSED] supported_formats=0x5 yuv420_allowed=1
[11:16:31] [PASSED] supported_formats=0x5 yuv420_allowed=0
[11:16:31] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[11:16:31] [PASSED] drm_test_connector_hdmi_init_null_ddc
[11:16:31] [PASSED] drm_test_connector_hdmi_init_null_product
[11:16:31] [PASSED] drm_test_connector_hdmi_init_null_vendor
[11:16:31] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[11:16:31] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[11:16:31] [PASSED] drm_test_connector_hdmi_init_product_valid
[11:16:31] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[11:16:31] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[11:16:31] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[11:16:31] ========= drm_test_connector_hdmi_init_type_valid  =========
[11:16:31] [PASSED] HDMI-A
[11:16:31] [PASSED] HDMI-B
[11:16:31] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[11:16:31] ======== drm_test_connector_hdmi_init_type_invalid  ========
[11:16:31] [PASSED] Unknown
[11:16:31] [PASSED] VGA
[11:16:31] [PASSED] DVI-I
[11:16:31] [PASSED] DVI-D
[11:16:31] [PASSED] DVI-A
[11:16:31] [PASSED] Composite
[11:16:31] [PASSED] SVIDEO
[11:16:31] [PASSED] LVDS
[11:16:31] [PASSED] Component
[11:16:31] [PASSED] DIN
[11:16:31] [PASSED] DP
[11:16:31] [PASSED] TV
[11:16:31] [PASSED] eDP
[11:16:31] [PASSED] Virtual
[11:16:31] [PASSED] DSI
[11:16:31] [PASSED] DPI
[11:16:31] [PASSED] Writeback
[11:16:31] [PASSED] SPI
[11:16:31] [PASSED] USB
[11:16:31] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[11:16:31] ============ [PASSED] drmm_connector_hdmi_init =============
[11:16:31] ============= drmm_connector_init (3 subtests) =============
[11:16:31] [PASSED] drm_test_drmm_connector_init
[11:16:31] [PASSED] drm_test_drmm_connector_init_null_ddc
[11:16:31] ========= drm_test_drmm_connector_init_type_valid  =========
[11:16:31] [PASSED] Unknown
[11:16:31] [PASSED] VGA
[11:16:31] [PASSED] DVI-I
[11:16:31] [PASSED] DVI-D
[11:16:31] [PASSED] DVI-A
[11:16:31] [PASSED] Composite
[11:16:31] [PASSED] SVIDEO
[11:16:31] [PASSED] LVDS
[11:16:31] [PASSED] Component
[11:16:31] [PASSED] DIN
[11:16:31] [PASSED] DP
[11:16:31] [PASSED] HDMI-A
[11:16:31] [PASSED] HDMI-B
[11:16:31] [PASSED] TV
[11:16:31] [PASSED] eDP
[11:16:31] [PASSED] Virtual
[11:16:31] [PASSED] DSI
[11:16:31] [PASSED] DPI
[11:16:31] [PASSED] Writeback
[11:16:31] [PASSED] SPI
[11:16:31] [PASSED] USB
[11:16:31] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[11:16:31] =============== [PASSED] drmm_connector_init ===============
[11:16:31] ========= drm_connector_dynamic_init (6 subtests) ==========
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_init
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_init_properties
[11:16:31] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[11:16:31] [PASSED] Unknown
[11:16:31] [PASSED] VGA
[11:16:31] [PASSED] DVI-I
[11:16:31] [PASSED] DVI-D
[11:16:31] [PASSED] DVI-A
[11:16:31] [PASSED] Composite
[11:16:31] [PASSED] SVIDEO
[11:16:31] [PASSED] LVDS
[11:16:31] [PASSED] Component
[11:16:31] [PASSED] DIN
[11:16:31] [PASSED] DP
[11:16:31] [PASSED] HDMI-A
[11:16:31] [PASSED] HDMI-B
[11:16:31] [PASSED] TV
[11:16:31] [PASSED] eDP
[11:16:31] [PASSED] Virtual
[11:16:31] [PASSED] DSI
[11:16:31] [PASSED] DPI
[11:16:31] [PASSED] Writeback
[11:16:31] [PASSED] SPI
[11:16:31] [PASSED] USB
[11:16:31] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[11:16:31] ======== drm_test_drm_connector_dynamic_init_name  =========
[11:16:31] [PASSED] Unknown
[11:16:31] [PASSED] VGA
[11:16:31] [PASSED] DVI-I
[11:16:31] [PASSED] DVI-D
[11:16:31] [PASSED] DVI-A
[11:16:31] [PASSED] Composite
[11:16:31] [PASSED] SVIDEO
[11:16:31] [PASSED] LVDS
[11:16:31] [PASSED] Component
[11:16:31] [PASSED] DIN
[11:16:31] [PASSED] DP
[11:16:31] [PASSED] HDMI-A
[11:16:31] [PASSED] HDMI-B
[11:16:31] [PASSED] TV
[11:16:31] [PASSED] eDP
[11:16:31] [PASSED] Virtual
[11:16:31] [PASSED] DSI
[11:16:31] [PASSED] DPI
[11:16:31] [PASSED] Writeback
[11:16:31] [PASSED] SPI
[11:16:31] [PASSED] USB
[11:16:31] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[11:16:31] =========== [PASSED] drm_connector_dynamic_init ============
[11:16:31] ==== drm_connector_dynamic_register_early (4 subtests) =====
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[11:16:31] ====== [PASSED] drm_connector_dynamic_register_early =======
[11:16:31] ======= drm_connector_dynamic_register (7 subtests) ========
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[11:16:31] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[11:16:31] ========= [PASSED] drm_connector_dynamic_register ==========
[11:16:31] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[11:16:31] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[11:16:31] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[11:16:31] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[11:16:31] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[11:16:31] ========== drm_test_get_tv_mode_from_name_valid  ===========
[11:16:31] [PASSED] NTSC
[11:16:31] [PASSED] NTSC-443
[11:16:31] [PASSED] NTSC-J
[11:16:31] [PASSED] PAL
[11:16:31] [PASSED] PAL-M
[11:16:31] [PASSED] PAL-N
[11:16:31] [PASSED] SECAM
[11:16:31] [PASSED] Mono
[11:16:31] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[11:16:31] [PASSED] drm_test_get_tv_mode_from_name_truncated
[11:16:31] ============ [PASSED] drm_get_tv_mode_from_name ============
[11:16:31] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[11:16:31] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[11:16:31] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[11:16:31] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[11:16:31] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[11:16:31] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[11:16:31] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[11:16:31] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[11:16:31] [PASSED] VIC 96
[11:16:31] [PASSED] VIC 97
[11:16:31] [PASSED] VIC 101
[11:16:31] [PASSED] VIC 102
[11:16:31] [PASSED] VIC 106
[11:16:31] [PASSED] VIC 107
[11:16:31] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[11:16:31] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[11:16:31] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[11:16:31] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[11:16:31] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[11:16:31] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[11:16:31] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[11:16:31] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[11:16:31] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[11:16:31] [PASSED] Automatic
[11:16:31] [PASSED] Full
[11:16:31] [PASSED] Limited 16:235
[11:16:31] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[11:16:31] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[11:16:31] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[11:16:31] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[11:16:31] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[11:16:31] [PASSED] RGB
[11:16:31] [PASSED] YUV 4:2:0
[11:16:31] [PASSED] YUV 4:2:2
[11:16:31] [PASSED] YUV 4:4:4
[11:16:31] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[11:16:31] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[11:16:31] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[11:16:31] ============= drm_damage_helper (21 subtests) ==============
[11:16:31] [PASSED] drm_test_damage_iter_no_damage
[11:16:31] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[11:16:31] [PASSED] drm_test_damage_iter_no_damage_src_moved
[11:16:31] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[11:16:31] [PASSED] drm_test_damage_iter_no_damage_not_visible
[11:16:31] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[11:16:31] [PASSED] drm_test_damage_iter_no_damage_no_fb
[11:16:31] [PASSED] drm_test_damage_iter_simple_damage
[11:16:31] [PASSED] drm_test_damage_iter_single_damage
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_outside_src
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_src_moved
[11:16:31] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[11:16:31] [PASSED] drm_test_damage_iter_damage
[11:16:31] [PASSED] drm_test_damage_iter_damage_one_intersect
[11:16:31] [PASSED] drm_test_damage_iter_damage_one_outside
[11:16:31] [PASSED] drm_test_damage_iter_damage_src_moved
[11:16:31] [PASSED] drm_test_damage_iter_damage_not_visible
[11:16:31] ================ [PASSED] drm_damage_helper ================
[11:16:31] ============== drm_dp_mst_helper (3 subtests) ==============
[11:16:31] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[11:16:31] [PASSED] Clock 154000 BPP 30 DSC disabled
[11:16:31] [PASSED] Clock 234000 BPP 30 DSC disabled
[11:16:31] [PASSED] Clock 297000 BPP 24 DSC disabled
[11:16:31] [PASSED] Clock 332880 BPP 24 DSC enabled
[11:16:31] [PASSED] Clock 324540 BPP 24 DSC enabled
[11:16:31] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[11:16:31] ============== drm_test_dp_mst_calc_pbn_div  ===============
[11:16:31] [PASSED] Link rate 2000000 lane count 4
[11:16:31] [PASSED] Link rate 2000000 lane count 2
[11:16:31] [PASSED] Link rate 2000000 lane count 1
[11:16:31] [PASSED] Link rate 1350000 lane count 4
[11:16:31] [PASSED] Link rate 1350000 lane count 2
[11:16:31] [PASSED] Link rate 1350000 lane count 1
[11:16:31] [PASSED] Link rate 1000000 lane count 4
[11:16:31] [PASSED] Link rate 1000000 lane count 2
[11:16:31] [PASSED] Link rate 1000000 lane count 1
[11:16:31] [PASSED] Link rate 810000 lane count 4
[11:16:31] [PASSED] Link rate 810000 lane count 2
[11:16:31] [PASSED] Link rate 810000 lane count 1
[11:16:31] [PASSED] Link rate 540000 lane count 4
[11:16:31] [PASSED] Link rate 540000 lane count 2
[11:16:31] [PASSED] Link rate 540000 lane count 1
[11:16:31] [PASSED] Link rate 270000 lane count 4
[11:16:31] [PASSED] Link rate 270000 lane count 2
[11:16:31] [PASSED] Link rate 270000 lane count 1
[11:16:31] [PASSED] Link rate 162000 lane count 4
[11:16:31] [PASSED] Link rate 162000 lane count 2
[11:16:31] [PASSED] Link rate 162000 lane count 1
[11:16:31] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[11:16:31] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[11:16:31] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[11:16:31] [PASSED] DP_POWER_UP_PHY with port number
[11:16:31] [PASSED] DP_POWER_DOWN_PHY with port number
[11:16:31] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[11:16:31] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[11:16:31] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[11:16:31] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[11:16:31] [PASSED] DP_QUERY_PAYLOAD with port number
[11:16:31] [PASSED] DP_QUERY_PAYLOAD with VCPI
[11:16:31] [PASSED] DP_REMOTE_DPCD_READ with port number
[11:16:31] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[11:16:31] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[11:16:31] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[11:16:31] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[11:16:31] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[11:16:31] [PASSED] DP_REMOTE_I2C_READ with port number
[11:16:31] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[11:16:31] [PASSED] DP_REMOTE_I2C_READ with transactions array
[11:16:31] [PASSED] DP_REMOTE_I2C_WRITE with port number
[11:16:31] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[11:16:31] [PASSED] DP_REMOTE_I2C_WRITE with data array
[11:16:31] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[11:16:31] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[11:16:31] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[11:16:31] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[11:16:31] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[11:16:31] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[11:16:31] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[11:16:31] ================ [PASSED] drm_dp_mst_helper ================
[11:16:31] ================== drm_exec (7 subtests) ===================
[11:16:31] [PASSED] sanitycheck
[11:16:31] [PASSED] test_lock
[11:16:31] [PASSED] test_lock_unlock
[11:16:31] [PASSED] test_duplicates
[11:16:31] [PASSED] test_prepare
[11:16:31] [PASSED] test_prepare_array
[11:16:31] [PASSED] test_multiple_loops
[11:16:31] ==================== [PASSED] drm_exec =====================
[11:16:31] =========== drm_format_helper_test (17 subtests) ===========
[11:16:31] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[11:16:31] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[11:16:31] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[11:16:31] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[11:16:31] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[11:16:31] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[11:16:31] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[11:16:31] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[11:16:31] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[11:16:31] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[11:16:31] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[11:16:31] ============== drm_test_fb_xrgb8888_to_mono  ===============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[11:16:31] ==================== drm_test_fb_swab  =====================
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ================ [PASSED] drm_test_fb_swab =================
[11:16:31] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[11:16:31] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[11:16:31] [PASSED] single_pixel_source_buffer
[11:16:31] [PASSED] single_pixel_clip_rectangle
[11:16:31] [PASSED] well_known_colors
[11:16:31] [PASSED] destination_pitch
[11:16:31] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[11:16:31] ================= drm_test_fb_clip_offset  =================
[11:16:31] [PASSED] pass through
[11:16:31] [PASSED] horizontal offset
[11:16:31] [PASSED] vertical offset
[11:16:31] [PASSED] horizontal and vertical offset
[11:16:31] [PASSED] horizontal offset (custom pitch)
[11:16:31] [PASSED] vertical offset (custom pitch)
[11:16:31] [PASSED] horizontal and vertical offset (custom pitch)
[11:16:31] ============= [PASSED] drm_test_fb_clip_offset =============
[11:16:31] =================== drm_test_fb_memcpy  ====================
[11:16:31] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[11:16:31] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[11:16:31] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[11:16:31] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[11:16:31] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[11:16:31] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[11:16:31] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[11:16:31] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[11:16:31] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[11:16:31] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[11:16:31] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[11:16:31] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[11:16:31] =============== [PASSED] drm_test_fb_memcpy ================
[11:16:31] ============= [PASSED] drm_format_helper_test ==============
[11:16:31] ================= drm_format (18 subtests) =================
[11:16:31] [PASSED] drm_test_format_block_width_invalid
[11:16:31] [PASSED] drm_test_format_block_width_one_plane
[11:16:31] [PASSED] drm_test_format_block_width_two_plane
[11:16:31] [PASSED] drm_test_format_block_width_three_plane
[11:16:31] [PASSED] drm_test_format_block_width_tiled
[11:16:31] [PASSED] drm_test_format_block_height_invalid
[11:16:31] [PASSED] drm_test_format_block_height_one_plane
[11:16:31] [PASSED] drm_test_format_block_height_two_plane
[11:16:31] [PASSED] drm_test_format_block_height_three_plane
[11:16:31] [PASSED] drm_test_format_block_height_tiled
[11:16:31] [PASSED] drm_test_format_min_pitch_invalid
[11:16:31] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[11:16:31] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[11:16:31] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[11:16:31] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[11:16:31] [PASSED] drm_test_format_min_pitch_two_plane
[11:16:31] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[11:16:31] [PASSED] drm_test_format_min_pitch_tiled
[11:16:31] =================== [PASSED] drm_format ====================
[11:16:31] ============== drm_framebuffer (10 subtests) ===============
[11:16:31] ========== drm_test_framebuffer_check_src_coords  ==========
[11:16:31] [PASSED] Success: source fits into fb
[11:16:31] [PASSED] Fail: overflowing fb with x-axis coordinate
[11:16:31] [PASSED] Fail: overflowing fb with y-axis coordinate
[11:16:31] [PASSED] Fail: overflowing fb with source width
[11:16:31] [PASSED] Fail: overflowing fb with source height
[11:16:31] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[11:16:31] [PASSED] drm_test_framebuffer_cleanup
[11:16:31] =============== drm_test_framebuffer_create  ===============
[11:16:31] [PASSED] ABGR8888 normal sizes
[11:16:31] [PASSED] ABGR8888 max sizes
[11:16:31] [PASSED] ABGR8888 pitch greater than min required
[11:16:31] [PASSED] ABGR8888 pitch less than min required
[11:16:31] [PASSED] ABGR8888 Invalid width
[11:16:31] [PASSED] ABGR8888 Invalid buffer handle
[11:16:31] [PASSED] No pixel format
[11:16:31] [PASSED] ABGR8888 Width 0
[11:16:31] [PASSED] ABGR8888 Height 0
[11:16:31] [PASSED] ABGR8888 Out of bound height * pitch combination
[11:16:31] [PASSED] ABGR8888 Large buffer offset
[11:16:31] [PASSED] ABGR8888 Buffer offset for inexistent plane
[11:16:31] [PASSED] ABGR8888 Invalid flag
[11:16:31] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[11:16:31] [PASSED] ABGR8888 Valid buffer modifier
[11:16:31] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[11:16:31] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] NV12 Normal sizes
[11:16:31] [PASSED] NV12 Max sizes
[11:16:31] [PASSED] NV12 Invalid pitch
[11:16:31] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[11:16:31] [PASSED] NV12 different  modifier per-plane
[11:16:31] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[11:16:31] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] NV12 Modifier for inexistent plane
[11:16:31] [PASSED] NV12 Handle for inexistent plane
[11:16:31] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[11:16:31] [PASSED] YVU420 Normal sizes
[11:16:31] [PASSED] YVU420 Max sizes
[11:16:31] [PASSED] YVU420 Invalid pitch
[11:16:31] [PASSED] YVU420 Different pitches
[11:16:31] [PASSED] YVU420 Different buffer offsets/pitches
[11:16:31] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[11:16:31] [PASSED] YVU420 Valid modifier
[11:16:31] [PASSED] YVU420 Different modifiers per plane
[11:16:31] [PASSED] YVU420 Modifier for inexistent plane
[11:16:31] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[11:16:31] [PASSED] X0L2 Normal sizes
[11:16:31] [PASSED] X0L2 Max sizes
[11:16:31] [PASSED] X0L2 Invalid pitch
[11:16:31] [PASSED] X0L2 Pitch greater than minimum required
[11:16:31] [PASSED] X0L2 Handle for inexistent plane
[11:16:31] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[11:16:31] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[11:16:31] [PASSED] X0L2 Valid modifier
[11:16:31] [PASSED] X0L2 Modifier for inexistent plane
[11:16:31] =========== [PASSED] drm_test_framebuffer_create ===========
[11:16:31] [PASSED] drm_test_framebuffer_free
[11:16:31] [PASSED] drm_test_framebuffer_init
[11:16:31] [PASSED] drm_test_framebuffer_init_bad_format
[11:16:31] [PASSED] drm_test_framebuffer_init_dev_mismatch
[11:16:31] [PASSED] drm_test_framebuffer_lookup
[11:16:31] [PASSED] drm_test_framebuffer_lookup_inexistent
[11:16:31] [PASSED] drm_test_framebuffer_modifiers_not_supported
[11:16:31] ================= [PASSED] drm_framebuffer =================
[11:16:31] ================ drm_gem_shmem (8 subtests) ================
[11:16:31] [PASSED] drm_gem_shmem_test_obj_create
[11:16:31] [PASSED] drm_gem_shmem_test_obj_create_private
[11:16:31] [PASSED] drm_gem_shmem_test_pin_pages
[11:16:31] [PASSED] drm_gem_shmem_test_vmap
[11:16:31] [PASSED] drm_gem_shmem_test_get_sg_table
[11:16:31] [PASSED] drm_gem_shmem_test_get_pages_sgt
[11:16:31] [PASSED] drm_gem_shmem_test_madvise
[11:16:31] [PASSED] drm_gem_shmem_test_purge
[11:16:31] ================== [PASSED] drm_gem_shmem ==================
[11:16:31] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[11:16:31] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[11:16:31] [PASSED] Automatic
[11:16:31] [PASSED] Full
[11:16:31] [PASSED] Limited 16:235
[11:16:31] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[11:16:31] [PASSED] drm_test_check_disable_connector
[11:16:31] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[11:16:31] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[11:16:31] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[11:16:31] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[11:16:31] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[11:16:31] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[11:16:31] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[11:16:31] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[11:16:31] [PASSED] drm_test_check_output_bpc_dvi
[11:16:31] [PASSED] drm_test_check_output_bpc_format_vic_1
[11:16:31] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[11:16:31] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[11:16:31] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[11:16:31] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[11:16:31] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[11:16:31] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[11:16:31] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[11:16:31] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[11:16:31] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[11:16:31] [PASSED] drm_test_check_broadcast_rgb_value
[11:16:31] [PASSED] drm_test_check_bpc_8_value
[11:16:31] [PASSED] drm_test_check_bpc_10_value
[11:16:31] [PASSED] drm_test_check_bpc_12_value
[11:16:31] [PASSED] drm_test_check_format_value
[11:16:31] [PASSED] drm_test_check_tmds_char_value
[11:16:31] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[11:16:31] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[11:16:31] [PASSED] drm_test_check_mode_valid
[11:16:31] [PASSED] drm_test_check_mode_valid_reject
[11:16:31] [PASSED] drm_test_check_mode_valid_reject_rate
[11:16:31] [PASSED] drm_test_check_mode_valid_reject_max_clock
[11:16:31] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[11:16:31] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[11:16:31] [PASSED] drm_test_check_infoframes
[11:16:31] [PASSED] drm_test_check_reject_avi_infoframe
[11:16:31] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[11:16:31] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[11:16:31] [PASSED] drm_test_check_reject_audio_infoframe
[11:16:31] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[11:16:31] ================= drm_managed (2 subtests) =================
[11:16:31] [PASSED] drm_test_managed_release_action
[11:16:31] [PASSED] drm_test_managed_run_action
[11:16:31] =================== [PASSED] drm_managed ===================
[11:16:31] =================== drm_mm (6 subtests) ====================
[11:16:31] [PASSED] drm_test_mm_init
[11:16:31] [PASSED] drm_test_mm_debug
[11:16:31] [PASSED] drm_test_mm_align32
[11:16:31] [PASSED] drm_test_mm_align64
[11:16:31] [PASSED] drm_test_mm_lowest
[11:16:31] [PASSED] drm_test_mm_highest
[11:16:31] ===================== [PASSED] drm_mm ======================
[11:16:31] ============= drm_modes_analog_tv (5 subtests) =============
[11:16:31] [PASSED] drm_test_modes_analog_tv_mono_576i
[11:16:31] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[11:16:31] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[11:16:31] [PASSED] drm_test_modes_analog_tv_pal_576i
[11:16:31] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[11:16:31] =============== [PASSED] drm_modes_analog_tv ===============
[11:16:31] ============== drm_plane_helper (2 subtests) ===============
[11:16:31] =============== drm_test_check_plane_state  ================
[11:16:31] [PASSED] clipping_simple
[11:16:31] [PASSED] clipping_rotate_reflect
[11:16:31] [PASSED] positioning_simple
[11:16:31] [PASSED] upscaling
[11:16:31] [PASSED] downscaling
[11:16:31] [PASSED] rounding1
[11:16:31] [PASSED] rounding2
[11:16:31] [PASSED] rounding3
[11:16:31] [PASSED] rounding4
[11:16:31] =========== [PASSED] drm_test_check_plane_state ============
[11:16:31] =========== drm_test_check_invalid_plane_state  ============
[11:16:31] [PASSED] positioning_invalid
[11:16:31] [PASSED] upscaling_invalid
[11:16:31] [PASSED] downscaling_invalid
[11:16:31] ======= [PASSED] drm_test_check_invalid_plane_state ========
[11:16:31] ================ [PASSED] drm_plane_helper =================
[11:16:31] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[11:16:31] ====== drm_test_connector_helper_tv_get_modes_check  =======
[11:16:31] [PASSED] None
[11:16:31] [PASSED] PAL
[11:16:31] [PASSED] NTSC
[11:16:31] [PASSED] Both, NTSC Default
[11:16:31] [PASSED] Both, PAL Default
[11:16:31] [PASSED] Both, NTSC Default, with PAL on command-line
[11:16:31] [PASSED] Both, PAL Default, with NTSC on command-line
[11:16:31] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[11:16:31] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[11:16:31] ================== drm_rect (9 subtests) ===================
[11:16:31] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[11:16:31] [PASSED] drm_test_rect_clip_scaled_not_clipped
[11:16:31] [PASSED] drm_test_rect_clip_scaled_clipped
[11:16:31] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[11:16:31] ================= drm_test_rect_intersect  =================
[11:16:31] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[11:16:31] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[11:16:31] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[11:16:31] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[11:16:31] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[11:16:31] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[11:16:31] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[11:16:31] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[11:16:31] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[11:16:31] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[11:16:31] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[11:16:31] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[11:16:31] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[11:16:31] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[11:16:31] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[11:16:31] ============= [PASSED] drm_test_rect_intersect =============
[11:16:31] ================ drm_test_rect_calc_hscale  ================
[11:16:31] [PASSED] normal use
[11:16:31] [PASSED] out of max range
[11:16:31] [PASSED] out of min range
[11:16:31] [PASSED] zero dst
[11:16:31] [PASSED] negative src
[11:16:31] [PASSED] negative dst
[11:16:31] ============ [PASSED] drm_test_rect_calc_hscale ============
[11:16:31] ================ drm_test_rect_calc_vscale  ================
[11:16:31] [PASSED] normal use
[11:16:31] [PASSED] out of max range
[11:16:31] [PASSED] out of min range
[11:16:31] [PASSED] zero dst
[11:16:31] [PASSED] negative src
[11:16:31] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[11:16:31] ============ [PASSED] drm_test_rect_calc_vscale ============
[11:16:31] ================== drm_test_rect_rotate  ===================
[11:16:31] [PASSED] reflect-x
[11:16:31] [PASSED] reflect-y
[11:16:31] [PASSED] rotate-0
[11:16:31] [PASSED] rotate-90
[11:16:31] [PASSED] rotate-180
[11:16:31] [PASSED] rotate-270
[11:16:31] ============== [PASSED] drm_test_rect_rotate ===============
[11:16:31] ================ drm_test_rect_rotate_inv  =================
[11:16:31] [PASSED] reflect-x
[11:16:31] [PASSED] reflect-y
[11:16:31] [PASSED] rotate-0
[11:16:31] [PASSED] rotate-90
[11:16:31] [PASSED] rotate-180
[11:16:31] [PASSED] rotate-270
[11:16:31] ============ [PASSED] drm_test_rect_rotate_inv =============
[11:16:31] ==================== [PASSED] drm_rect =====================
[11:16:31] ============ drm_sysfb_modeset_test (1 subtest) ============
[11:16:31] ============ drm_test_sysfb_build_fourcc_list  =============
[11:16:31] [PASSED] no native formats
[11:16:31] [PASSED] XRGB8888 as native format
[11:16:31] [PASSED] remove duplicates
[11:16:31] [PASSED] convert alpha formats
[11:16:31] [PASSED] random formats
[11:16:31] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[11:16:31] ============= [PASSED] drm_sysfb_modeset_test ==============
[11:16:31] ================== drm_fixp (2 subtests) ===================
[11:16:31] [PASSED] drm_test_int2fixp
[11:16:31] [PASSED] drm_test_sm2fixp
[11:16:31] ==================== [PASSED] drm_fixp =====================
[11:16:31] ============================================================
[11:16:31] Testing complete. Ran 621 tests: passed: 621
[11:16:31] Elapsed time: 26.226s total, 1.686s configuring, 24.369s building, 0.138s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[11:16:31] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[11:16:32] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[11:16:42] Starting KUnit Kernel (1/1)...
[11:16:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[11:16:42] ================= ttm_device (5 subtests) ==================
[11:16:42] [PASSED] ttm_device_init_basic
[11:16:42] [PASSED] ttm_device_init_multiple
[11:16:42] [PASSED] ttm_device_fini_basic
[11:16:42] [PASSED] ttm_device_init_no_vma_man
[11:16:42] ================== ttm_device_init_pools  ==================
[11:16:42] [PASSED] No DMA allocations, no DMA32 required
[11:16:42] [PASSED] DMA allocations, DMA32 required
[11:16:42] [PASSED] No DMA allocations, DMA32 required
[11:16:42] [PASSED] DMA allocations, no DMA32 required
[11:16:42] ============== [PASSED] ttm_device_init_pools ==============
[11:16:42] =================== [PASSED] ttm_device ====================
[11:16:42] ================== ttm_pool (8 subtests) ===================
[11:16:42] ================== ttm_pool_alloc_basic  ===================
[11:16:42] [PASSED] One page
[11:16:42] [PASSED] More than one page
[11:16:42] [PASSED] Above the allocation limit
[11:16:42] [PASSED] One page, with coherent DMA mappings enabled
[11:16:42] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:16:42] ============== [PASSED] ttm_pool_alloc_basic ===============
[11:16:42] ============== ttm_pool_alloc_basic_dma_addr  ==============
[11:16:42] [PASSED] One page
[11:16:42] [PASSED] More than one page
[11:16:42] [PASSED] Above the allocation limit
[11:16:42] [PASSED] One page, with coherent DMA mappings enabled
[11:16:42] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[11:16:42] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[11:16:42] [PASSED] ttm_pool_alloc_order_caching_match
[11:16:42] [PASSED] ttm_pool_alloc_caching_mismatch
[11:16:42] [PASSED] ttm_pool_alloc_order_mismatch
[11:16:42] [PASSED] ttm_pool_free_dma_alloc
[11:16:42] [PASSED] ttm_pool_free_no_dma_alloc
[11:16:42] [PASSED] ttm_pool_fini_basic
[11:16:42] ==================== [PASSED] ttm_pool =====================
[11:16:42] ================ ttm_resource (8 subtests) =================
[11:16:42] ================= ttm_resource_init_basic  =================
[11:16:42] [PASSED] Init resource in TTM_PL_SYSTEM
[11:16:42] [PASSED] Init resource in TTM_PL_VRAM
[11:16:42] [PASSED] Init resource in a private placement
[11:16:42] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[11:16:42] ============= [PASSED] ttm_resource_init_basic =============
[11:16:42] [PASSED] ttm_resource_init_pinned
[11:16:42] [PASSED] ttm_resource_fini_basic
[11:16:42] [PASSED] ttm_resource_manager_init_basic
[11:16:42] [PASSED] ttm_resource_manager_usage_basic
[11:16:42] [PASSED] ttm_resource_manager_set_used_basic
[11:16:42] [PASSED] ttm_sys_man_alloc_basic
[11:16:42] [PASSED] ttm_sys_man_free_basic
[11:16:42] ================== [PASSED] ttm_resource ===================
[11:16:42] =================== ttm_tt (15 subtests) ===================
[11:16:42] ==================== ttm_tt_init_basic  ====================
[11:16:42] [PASSED] Page-aligned size
[11:16:42] [PASSED] Extra pages requested
[11:16:42] ================ [PASSED] ttm_tt_init_basic ================
[11:16:42] [PASSED] ttm_tt_init_misaligned
[11:16:42] [PASSED] ttm_tt_fini_basic
[11:16:42] [PASSED] ttm_tt_fini_sg
[11:16:42] [PASSED] ttm_tt_fini_shmem
[11:16:42] [PASSED] ttm_tt_create_basic
[11:16:42] [PASSED] ttm_tt_create_invalid_bo_type
[11:16:42] [PASSED] ttm_tt_create_ttm_exists
[11:16:42] [PASSED] ttm_tt_create_failed
[11:16:42] [PASSED] ttm_tt_destroy_basic
[11:16:42] [PASSED] ttm_tt_populate_null_ttm
[11:16:42] [PASSED] ttm_tt_populate_populated_ttm
[11:16:42] [PASSED] ttm_tt_unpopulate_basic
[11:16:42] [PASSED] ttm_tt_unpopulate_empty_ttm
[11:16:42] [PASSED] ttm_tt_swapin_basic
[11:16:42] ===================== [PASSED] ttm_tt ======================
[11:16:42] =================== ttm_bo (14 subtests) ===================
[11:16:42] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[11:16:42] [PASSED] Cannot be interrupted and sleeps
[11:16:42] [PASSED] Cannot be interrupted, locks straight away
[11:16:42] [PASSED] Can be interrupted, sleeps
[11:16:42] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[11:16:42] [PASSED] ttm_bo_reserve_locked_no_sleep
[11:16:42] [PASSED] ttm_bo_reserve_no_wait_ticket
[11:16:42] [PASSED] ttm_bo_reserve_double_resv
[11:16:42] [PASSED] ttm_bo_reserve_interrupted
[11:16:42] [PASSED] ttm_bo_reserve_deadlock
[11:16:42] [PASSED] ttm_bo_unreserve_basic
[11:16:42] [PASSED] ttm_bo_unreserve_pinned
[11:16:42] [PASSED] ttm_bo_unreserve_bulk
[11:16:42] [PASSED] ttm_bo_fini_basic
[11:16:42] [PASSED] ttm_bo_fini_shared_resv
[11:16:42] [PASSED] ttm_bo_pin_basic
[11:16:42] [PASSED] ttm_bo_pin_unpin_resource
[11:16:42] [PASSED] ttm_bo_multiple_pin_one_unpin
[11:16:42] ===================== [PASSED] ttm_bo ======================
[11:16:42] ============== ttm_bo_validate (22 subtests) ===============
[11:16:42] ============== ttm_bo_init_reserved_sys_man  ===============
[11:16:42] [PASSED] Buffer object for userspace
[11:16:42] [PASSED] Kernel buffer object
[11:16:42] [PASSED] Shared buffer object
[11:16:42] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[11:16:42] ============== ttm_bo_init_reserved_mock_man  ==============
[11:16:42] [PASSED] Buffer object for userspace
[11:16:42] [PASSED] Kernel buffer object
[11:16:42] [PASSED] Shared buffer object
[11:16:42] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[11:16:42] [PASSED] ttm_bo_init_reserved_resv
[11:16:42] ================== ttm_bo_validate_basic  ==================
[11:16:42] [PASSED] Buffer object for userspace
[11:16:42] [PASSED] Kernel buffer object
[11:16:42] [PASSED] Shared buffer object
[11:16:42] ============== [PASSED] ttm_bo_validate_basic ==============
[11:16:42] [PASSED] ttm_bo_validate_invalid_placement
[11:16:42] ============= ttm_bo_validate_same_placement  ==============
[11:16:42] [PASSED] System manager
[11:16:42] [PASSED] VRAM manager
[11:16:42] ========= [PASSED] ttm_bo_validate_same_placement ==========
[11:16:42] [PASSED] ttm_bo_validate_failed_alloc
[11:16:42] [PASSED] ttm_bo_validate_pinned
[11:16:42] [PASSED] ttm_bo_validate_busy_placement
[11:16:42] ================ ttm_bo_validate_multihop  =================
[11:16:42] [PASSED] Buffer object for userspace
[11:16:42] [PASSED] Kernel buffer object
[11:16:42] [PASSED] Shared buffer object
[11:16:42] ============ [PASSED] ttm_bo_validate_multihop =============
[11:16:42] ========== ttm_bo_validate_no_placement_signaled  ==========
[11:16:42] [PASSED] Buffer object in system domain, no page vector
[11:16:42] [PASSED] Buffer object in system domain with an existing page vector
[11:16:42] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[11:16:42] ======== ttm_bo_validate_no_placement_not_signaled  ========
[11:16:42] [PASSED] Buffer object for userspace
[11:16:42] [PASSED] Kernel buffer object
[11:16:42] [PASSED] Shared buffer object
[11:16:42] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[11:16:42] [PASSED] ttm_bo_validate_move_fence_signaled
[11:16:42] ========= ttm_bo_validate_move_fence_not_signaled  =========
[11:16:42] [PASSED] Waits for GPU
[11:16:42] [PASSED] Tries to lock straight away
[11:16:42] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[11:16:42] [PASSED] ttm_bo_validate_swapout
[11:16:42] [PASSED] ttm_bo_validate_happy_evict
[11:16:42] [PASSED] ttm_bo_validate_all_pinned_evict
[11:16:42] [PASSED] ttm_bo_validate_allowed_only_evict
[11:16:42] [PASSED] ttm_bo_validate_deleted_evict
[11:16:42] [PASSED] ttm_bo_validate_busy_domain_evict
[11:16:42] [PASSED] ttm_bo_validate_evict_gutting
[11:16:42] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[11:16:42] ================= [PASSED] ttm_bo_validate =================
[11:16:42] ============================================================
[11:16:42] Testing complete. Ran 102 tests: passed: 102
[11:16:42] Elapsed time: 11.318s total, 1.656s configuring, 9.446s building, 0.180s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for CMTG enablement (rev5)

[Patchwork]

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== Series Details ==

Series: CMTG enablement (rev5)
URL   : https://patchwork.freedesktop.org/series/157663/
State : success

== Summary ==

CI Bug Log - changes from xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb_BAT -> xe-pw-157663v5_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (14 -> 14)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-157663v5_BAT that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [PASS][1] -> [ABORT][2] ([Intel XE#7249] / [Intel XE#7578])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
    - bat-adlp-7:         [PASS][3] -> [DMESG-WARN][4] ([Intel XE#7483])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - bat-adlp-7:         [DMESG-WARN][5] ([Intel XE#7483]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  
  [Intel XE#7249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7249
  [Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483
  [Intel XE#7578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7578


Build changes
-------------

  * Linux: xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb -> xe-pw-157663v5

  IGT_8854: 93abaf0170728f69bc27577e5b405f7a2a01b6fd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb: afe01cbdd453cb1b141b29ea6153f64ef0f151fb
  xe-pw-157663v5: 157663v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/index.html

[-- Attachment #2: Type: text/html, Size: 3199 bytes --]

✗ Xe.CI.FULL: failure for CMTG enablement (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 35266 bytes --]

== Series Details ==

Series: CMTG enablement (rev5)
URL   : https://patchwork.freedesktop.org/series/157663/
State : failure

== Summary ==

CI Bug Log - changes from xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb_FULL -> xe-pw-157663v5_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-157663v5_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-157663v5_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-157663v5_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp2:
    - shard-bmg:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp2.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp2.html

  
Known issues
------------

  Here are the changes found in xe-pw-157663v5_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#2327])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#1124]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#367] / [Intel XE#7354])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_bw@linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2652]) +8 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2887])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2252])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_chamelium_hpd@hdmi-hpd-storm.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][9] ([Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-lnl:          NOTRUN -> [SKIP][10] ([Intel XE#1424])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@kms_cursor_crc@cursor-onscreen-128x42.html
    - shard-bmg:          NOTRUN -> [SKIP][11] ([Intel XE#2320])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][12] -> [FAIL][13] ([Intel XE#7571])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#1340] / [Intel XE#7435])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-3.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#4354] / [Intel XE#7386])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-lnl:          [PASS][16] -> [FAIL][17] ([Intel XE#301]) +3 other tests fail
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
    - shard-bmg:          [PASS][18] -> [FAIL][19] ([Intel XE#7545])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-panning-interruptible@d-dp2:
    - shard-bmg:          [PASS][20] -> [ABORT][21] ([Intel XE#5545] / [Intel XE#6652] / [Intel XE#7200]) +3 other tests abort
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@kms_flip@flip-vs-panning-interruptible@d-dp2.html
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-2/igt@kms_flip@flip-vs-panning-interruptible@d-dp2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7178] / [Intel XE#7351])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#2311]) +5 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html
    - shard-lnl:          NOTRUN -> [SKIP][24] ([Intel XE#6312] / [Intel XE#651])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#4141])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#656]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#2313]) +6 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#7283])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#7283])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#5021] / [Intel XE#7377])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-lnl:          [PASS][32] -> [FAIL][33] ([Intel XE#7340])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-lnl-1/igt@kms_pm_dc@dc5-psr.html
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#3309] / [Intel XE#7368])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#1489]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@kms_psr2_sf@psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr@psr2-sprite-blt:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_psr@psr2-sprite-blt.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#1127] / [Intel XE#5813])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2330] / [Intel XE#5813])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-bmg:          NOTRUN -> [SKIP][39] ([Intel XE#3904] / [Intel XE#7342])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-bmg:          NOTRUN -> [SKIP][40] ([Intel XE#1499])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@xe_eudebug@basic-vm-access-parameters-faultable:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#7636])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@xe_eudebug@basic-vm-access-parameters-faultable.html

  * igt@xe_eudebug_online@set-breakpoint-faultable:
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#7636]) +2 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_eudebug_online@set-breakpoint-faultable.html

  * igt@xe_evict@evict-beng-large-cm:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#6540] / [Intel XE#688])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@xe_evict@evict-beng-large-cm.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [PASS][44] -> [INCOMPLETE][45] ([Intel XE#6321])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-7/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_exec_basic@multigpu-once-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][46] ([Intel XE#2322] / [Intel XE#7372])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_exec_basic@multigpu-once-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-imm:
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#7136]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_exec_fault_mode@many-multi-queue-userptr-invalidate-race-imm.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-imm:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#7136]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-imm.html

  * igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][49] ([Intel XE#6874]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_exec_multi_queue@few-execs-preempt-mode-userptr-invalidate.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#6874])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-close-fd-smem.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][51] ([Intel XE#7138])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-rebind.html

  * igt@xe_multigpu_svm@mgpu-latency-copy-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][52] ([Intel XE#6964])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@xe_multigpu_svm@mgpu-latency-copy-prefetch.html

  * igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy:
    - shard-bmg:          NOTRUN -> [SKIP][53] ([Intel XE#4733] / [Intel XE#7417])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_pxp@pxp-src-to-pxp-dest-rendercopy.html

  * igt@xe_sriov_auto_provisioning@exclusive-ranges:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#4130] / [Intel XE#7366])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-4/igt@xe_sriov_auto_provisioning@exclusive-ranges.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][55] ([Intel XE#5545])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_wedged@wedged-at-any-timeout.html

  
#### Possible fixes ####

  * igt@kms_atomic@crtc-invalid-params-fence@pipe-a-dp-2:
    - shard-bmg:          [DMESG-WARN][56] ([Intel XE#7725]) -> [PASS][57] +11 other tests pass
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_atomic@crtc-invalid-params-fence@pipe-a-dp-2.html
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_atomic@crtc-invalid-params-fence@pipe-a-dp-2.html

  * igt@kms_color@deep-color:
    - shard-bmg:          [SKIP][58] -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_color@deep-color.html
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@kms_color@deep-color.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-bmg:          [SKIP][60] ([Intel XE#2291] / [Intel XE#7343]) -> [PASS][61]
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-bmg:          [DMESG-WARN][62] -> [PASS][63] +7 other tests pass
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_flip@2x-blocking-wf_vblank.html
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][64] ([Intel XE#1503]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_hdr@invalid-hdr.html

  * igt@kms_vblank@wait-idle@pipe-d-dp-2:
    - shard-bmg:          [FAIL][66] -> [PASS][67] +1 other test pass
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_vblank@wait-idle@pipe-d-dp-2.html
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_vblank@wait-idle@pipe-d-dp-2.html

  * igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute:
    - shard-bmg:          [ABORT][68] ([Intel XE#7200]) -> [PASS][69] +1 other test pass
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute.html
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@xe_compute_preempt@compute-preempt-many-vram-evict@engine-drm_xe_engine_class_compute.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
    - shard-lnl:          [FAIL][70] ([Intel XE#5625]) -> [PASS][71] +1 other test pass
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-lnl-3/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-lnl-5/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early:
    - shard-bmg:          [ABORT][72] ([Intel XE#7578]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-1/igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early.html
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_fault_injection@inject-fault-probe-function-xe_pcode_probe_early.html

  
#### Warnings ####

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][74] ([Intel XE#2312]) -> [SKIP][75] ([Intel XE#4141])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][76] ([Intel XE#2312]) -> [SKIP][77] ([Intel XE#2311])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move:
    - shard-bmg:          [SKIP][78] ([Intel XE#2312]) -> [SKIP][79] ([Intel XE#2313])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][80] ([Intel XE#3544]) -> [SKIP][81] ([Intel XE#3374] / [Intel XE#3544])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@kms_hdr@brightness-with-hdr.html
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          [SKIP][82] ([Intel XE#2426] / [Intel XE#5848]) -> [FAIL][83] ([Intel XE#1729] / [Intel XE#7424])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern.html
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-10/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][84] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][85] ([Intel XE#2509] / [Intel XE#7437])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [SKIP][111]) ([Intel XE#2457] / [Intel XE#7405]) -> ([DMESG-WARN][112], [DMESG-WARN][113], [DMESG-WARN][114], [DMESG-WARN][115], [DMESG-WARN][116], [PASS][117], [PASS][118], [PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [SKIP][136], [PASS][137]) ([Intel XE#2457] / [Intel XE#7405] / [Intel XE#7725])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_module_load@load.html
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-1/igt@xe_module_load@load.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@xe_module_load@load.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@xe_module_load@load.html
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_module_load@load.html
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@xe_module_load@load.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@xe_module_load@load.html
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@xe_module_load@load.html
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@xe_module_load@load.html
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-7/igt@xe_module_load@load.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-10/igt@xe_module_load@load.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@xe_module_load@load.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-5/igt@xe_module_load@load.html
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-9/igt@xe_module_load@load.html
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@xe_module_load@load.html
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-6/igt@xe_module_load@load.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@xe_module_load@load.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-8/igt@xe_module_load@load.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-7/igt@xe_module_load@load.html
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-7/igt@xe_module_load@load.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-2/igt@xe_module_load@load.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-1/igt@xe_module_load@load.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb/shard-bmg-3/igt@xe_module_load@load.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-6/igt@xe_module_load@load.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-6/igt@xe_module_load@load.html
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-6/igt@xe_module_load@load.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-6/igt@xe_module_load@load.html
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-6/igt@xe_module_load@load.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@xe_module_load@load.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-10/igt@xe_module_load@load.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-10/igt@xe_module_load@load.html
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_module_load@load.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-2/igt@xe_module_load@load.html
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-7/igt@xe_module_load@load.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@xe_module_load@load.html
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-7/igt@xe_module_load@load.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-3/igt@xe_module_load@load.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-3/igt@xe_module_load@load.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@xe_module_load@load.html
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@xe_module_load@load.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-8/igt@xe_module_load@load.html
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-2/igt@xe_module_load@load.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-2/igt@xe_module_load@load.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_module_load@load.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-7/igt@xe_module_load@load.html
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-5/igt@xe_module_load@load.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-9/igt@xe_module_load@load.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-1/igt@xe_module_load@load.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/shard-bmg-9/igt@xe_module_load@load.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2330
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5545
  [Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#6652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6652
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7200]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7200
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7340
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
  [Intel XE#7435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7435
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7545
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7578]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7578
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7725]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7725


Build changes
-------------

  * Linux: xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb -> xe-pw-157663v5

  IGT_8854: 93abaf0170728f69bc27577e5b405f7a2a01b6fd @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4887-afe01cbdd453cb1b141b29ea6153f64ef0f151fb: afe01cbdd453cb1b141b29ea6153f64ef0f151fb
  xe-pw-157663v5: 157663v5

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157663v5/index.html

[-- Attachment #2: Type: text/html, Size: 38539 bytes --]

Re: [PATCH v4 13/13] drm/i915/cmtg: Set target_dc_state flag for lobf/psr2/pr-alpm

[Dibin Moolakadan Subrahmanian]

On 12-04-2026 16:07, Animesh Manna wrote:
> Set the target_dc_state in specific scenarios such as LOBF/PSR2/PR-ALPM,
> where DC3CO enablement will be targeted, allowing CMTG to be programmed.
> DC3CO enablement will be implemented in a separate patch series.
>
> Note: This patch currently added to test cmtg and need to revisit once
> DC3co enablement design in finilized.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index b8b6d62fb275..5de6cfde8bf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7342,6 +7342,7 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
>   				 struct intel_crtc_state *crtc_state,
>   				 struct drm_connector_state *conn_state)
>   {
> +	struct intel_display *display = to_intel_display(crtc_state);
>   	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>   	int ret;
>   
> @@ -7353,6 +7354,13 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
>   
>   	intel_alpm_lobf_compute_config_late(intel_dp, crtc_state);
>   
> +	if (DISPLAY_VER(display) >= 35 && intel_dp_is_edp(intel_dp) &&
> +	    (crtc_state->has_lobf || crtc_state->has_sel_update ||
> +	     crtc_state->has_panel_replay))
> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
> +	else
> +		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
> +
>   	return 0;
>   }
>   

I have two concerns here:

1. intel_dp_compute_config_late() is part of the atomic check path. Calling
intel_display_power_set_target_dc_state() here introduces a global power
policy side effect during state computation. This is also the wrong phase
to potentially wake the display (refer intel_display_power_set_target_dc_state()),
since the atomic check path should not affect runtime power state. Normally,
the display is woken up in intel_atomic_commit_tail().

2. The target DC state is a global display power decision and should not be
derived directly from a single crtc_state. This should be computed after
considering all active CRTCs in the atomic state.

Re: [PATCH v4 01/13] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG

[Jani Nikula]

On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> CMTG will be enabled only with DC3co, so add a separate function
> intel_cmtg_is_allowed() to check the prerequisites for enabling CMTG.
> DC3co will be enabled in a separate patch.
>
> v2:
> - Remove separate flag for DC3co from crtc_state. [Uma, Dibin]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/display/intel_cmtg.h |  2 ++
>  2 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index e1fdc6fe9762..1debed43cf2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -16,6 +16,7 @@
>  #include "intel_display_device.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
> +#include "intel_display_types.h"
>  
>  /**
>   * DOC: Common Primary Timing Generator (CMTG)
> @@ -185,3 +186,17 @@ void intel_cmtg_sanitize(struct intel_display *display)
>  
>  	intel_cmtg_disable(display, &cmtg_config);
>  }
> +
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +
> +	if ((cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B) &&
> +	    DISPLAY_VER(display) == 35 && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> +	    power_domains->target_dc_state == DC_STATE_EN_DC3CO)

intel_cmtg.c has no business accessing struct i915_power_domains members
directly. It belongs to intel_display_power.c.

BR,
Jani.

> +		return true;
> +
> +	return false;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index ba62199adaa2..7692cc98cf87 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -7,7 +7,9 @@
>  #define __INTEL_CMTG_H__
>  
>  struct intel_display;
> +struct intel_crtc_state;
>  
>  void intel_cmtg_sanitize(struct intel_display *display);
> +bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_CMTG_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Jani Nikula]

On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Timing registers are separate for CMTG, read transcoder register
> and program cmtg transcoder with those values.
>
> v2:
> - Use sw state instead of reading directly from hardware. [Jani]
> - Move set_timing later after encoder enable. [Dibin]
>
> v3:
> - Replace id with trans. [Jani]
> - Program cmtg set_timing() along with primary transcoder timing.
>
> v4:
> - Use _MMIO_TRANS() for cmtg registers instead of direct
> multiplication. [Jani]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
>  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
>  4 files changed, 98 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c b/drivers/gpu/drm/i915/display/intel_cmtg.c
> index 403f9e10a8dc..a3db1368bd83 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> @@ -4,7 +4,6 @@
>   */
>  
>  #include <linux/string_choices.h>
> -#include <linux/types.h>
>  
>  #include <drm/drm_device.h>
>  #include <drm/drm_print.h>
> @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state)
>  	if (clk_sel_set)
>  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set);
>  }
> +
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> +
> +	if (!intel_cmtg_is_allowed(crtc_state))
> +		return;
> +
> +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> +
> +	/*
> +	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
> +	 * bits are not required. Since the support for these bits is going to
> +	 * be deprecated in upcoming platforms, avoid writing these bits for the
> +	 * platforms that do not use legacy Timing Generator.
> +	 */
> +	crtc_vtotal = 1;
> +
> +	/*
> +	 * VBLANK_START not used by hw, just clear it
> +	 * to make it stand out in register dumps.
> +	 */
> +	crtc_vblank_start = 1;
> +
> +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> +
> +	if (lrr) {
> +		intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> +			       VACTIVE(crtc_vdisplay - 1) |
> +			       VTOTAL(crtc_vtotal - 1));
> +		intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> +			       VBLANK_START(crtc_vblank_start - 1) |
> +			       VBLANK_END(crtc_vblank_end - 1));
> +		return;
> +	}
> +
> +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> +		       VACTIVE(crtc_vdisplay - 1) |
> +		       VTOTAL(crtc_vtotal - 1));
> +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> +		       VBLANK_START(crtc_vblank_start - 1) |
> +		       VBLANK_END(crtc_vblank_end - 1));
> +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> +	intel_de_write(display, TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> +		       crtc_state->set_context_latency);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h b/drivers/gpu/drm/i915/display/intel_cmtg.h
> index 660ec513626e..53a44f505dd2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> @@ -6,9 +6,12 @@
>  #ifndef __INTEL_CMTG_H__
>  #define __INTEL_CMTG_H__
>  
> +#include <linux/types.h>
> +
>  struct intel_display;
>  struct intel_crtc_state;
>  
> +void intel_cmtg_set_timings(const struct intel_crtc_state *crtc_state, bool lrr);
>  void intel_cmtg_set_clk_select(const struct intel_crtc_state *crtc_state);
>  void intel_cmtg_sanitize(struct intel_display *display);
>  bool intel_cmtg_is_allowed(const struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> index 4a80b88d88fd..f7fc812d8ef0 100644
> --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> @@ -20,4 +20,35 @@
>  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
>  #define  CMTG_ENABLE			REG_BIT(31)
>  
> +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> +#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> +						    _TRANS_HTOTAL_CMTG_A, _TRANS_HTOTAL_CMTG_B)
> +#define _TRANS_HBLANK_CMTG_A		0x6F004
> +#define _TRANS_HBLANK_CMTG_B		0x6F104
> +#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> +						    _TRANS_HBLANK_CMTG_A, _TRANS_HBLANK_CMTG_B)
> +#define _TRANS_HSYNC_CMTG_A		0x6F008
> +#define _TRANS_HSYNC_CMTG_B		0x6F108
> +#define TRANS_HSYNC_CMTG(trans)		_MMIO_TRANS((trans), \
> +						    _TRANS_HSYNC_CMTG_A, _TRANS_HSYNC_CMTG_B)
> +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> +#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> +						    _TRANS_VTOTAL_CMTG_A, _TRANS_VTOTAL_CMTG_B)
> +#define _TRANS_VBLANK_CMTG_A		0x6F010
> +#define _TRANS_VBLANK_CMTG_B		0x6F110
> +#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> +						    _TRANS_VBLANK_CMTG_A, _TRANS_VBLANK_CMTG_B)
> +#define _TRANS_VSYNC_CMTG_A		0x6F014
> +#define _TRANS_VSYNC_CMTG_B		0x6F114
> +#define TRANS_VSYNC_CMTG(trans)		_MMIO_TRANS((trans), \
> +						    _TRANS_VSYNC_CMTG_A, _TRANS_VSYNC_CMTG_B)

I though there was already feedback that these match the regular
transcoder registers.

BR,
Jani.

> +
> +#define _TRANS_SET_CTX_LATENCY_CMTG_A	0x6F07C
> +#define _TRANS_SET_CTX_LATENCY_CMTG_B	0x6F17C
> +#define TRANS_SET_CTX_LATENCY_CMTG(trans)	_MMIO_TRANS((trans), \
> +							    _TRANS_SET_CTX_LATENCY_CMTG_A, \
> +							    _TRANS_SET_CTX_LATENCY_CMTG_B)
> +
>  #endif /* __INTEL_CMTG_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 58a654ca0d20..bf58ae5d3535 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -60,6 +60,7 @@
>  #include "intel_bw.h"
>  #include "intel_cdclk.h"
>  #include "intel_clock_gating.h"
> +#include "intel_cmtg.h"
>  #include "intel_color.h"
>  #include "intel_crt.h"
>  #include "intel_crtc.h"
> @@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>  		intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
>  			       crtc_state->min_hblank);
>  	}
> +
> +	intel_cmtg_set_timings(crtc_state, false);
>  }
>  
>  static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
> @@ -2814,6 +2817,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
>  		       VACTIVE(crtc_vdisplay - 1) |
>  		       VTOTAL(crtc_vtotal - 1));
>  
> +	intel_cmtg_set_timings(crtc_state, true);
>  	intel_vrr_set_fixed_rr_timings(crtc_state);
>  	intel_vrr_transcoder_enable(crtc_state);
>  }

-- 
Jani Nikula, Intel

RE: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, April 14, 2026 7:03 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Manna,
> Animesh <animesh.manna@intel.com>
> Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> 
> On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Timing registers are separate for CMTG, read transcoder register and
> > program cmtg transcoder with those values.
> >
> > v2:
> > - Use sw state instead of reading directly from hardware. [Jani]
> > - Move set_timing later after encoder enable. [Dibin]
> >
> > v3:
> > - Replace id with trans. [Jani]
> > - Program cmtg set_timing() along with primary transcoder timing.
> >
> > v4:
> > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > multiplication. [Jani]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61 ++++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
> >  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
> >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
> >  4 files changed, 98 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > index 403f9e10a8dc..a3db1368bd83 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > @@ -4,7 +4,6 @@
> >   */
> >
> >  #include <linux/string_choices.h>
> > -#include <linux/types.h>
> >
> >  #include <drm/drm_device.h>
> >  #include <drm/drm_print.h>
> > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct
> intel_crtc_state *crtc_state)
> >  	if (clk_sel_set)
> >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> clk_sel_set);  }
> > +
> > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state, bool lrr) {
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> >hw.adjusted_mode;
> > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > +
> > +	if (!intel_cmtg_is_allowed(crtc_state))
> > +		return;
> > +
> > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > +
> > +	/*
> > +	 * For platforms that always use VRR Timing Generator, the
> VTOTAL.Vtotal
> > +	 * bits are not required. Since the support for these bits is going to
> > +	 * be deprecated in upcoming platforms, avoid writing these bits for
> the
> > +	 * platforms that do not use legacy Timing Generator.
> > +	 */
> > +	crtc_vtotal = 1;
> > +
> > +	/*
> > +	 * VBLANK_START not used by hw, just clear it
> > +	 * to make it stand out in register dumps.
> > +	 */
> > +	crtc_vblank_start = 1;
> > +
> > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > +
> > +	if (lrr) {
> > +		intel_de_write(display,
> TRANS_VTOTAL_CMTG(cpu_transcoder),
> > +			       VACTIVE(crtc_vdisplay - 1) |
> > +			       VTOTAL(crtc_vtotal - 1));
> > +		intel_de_write(display,
> TRANS_VBLANK_CMTG(cpu_transcoder),
> > +			       VBLANK_START(crtc_vblank_start - 1) |
> > +			       VBLANK_END(crtc_vblank_end - 1));
> > +		return;
> > +	}
> > +
> > +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> > +		       VACTIVE(crtc_vdisplay - 1) |
> > +		       VTOTAL(crtc_vtotal - 1));
> > +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> > +		       VBLANK_START(crtc_vblank_start - 1) |
> > +		       VBLANK_END(crtc_vblank_end - 1));
> > +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > +	intel_de_write(display,
> TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > +		       crtc_state->set_context_latency); }
> > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > index 660ec513626e..53a44f505dd2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > @@ -6,9 +6,12 @@
> >  #ifndef __INTEL_CMTG_H__
> >  #define __INTEL_CMTG_H__
> >
> > +#include <linux/types.h>
> > +
> >  struct intel_display;
> >  struct intel_crtc_state;
> >
> > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > +*crtc_state, bool lrr);
> >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > *display);  bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > index 4a80b88d88fd..f7fc812d8ef0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > @@ -20,4 +20,35 @@
> >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> >  #define  CMTG_ENABLE			REG_BIT(31)
> >
> > +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> > +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > +						    _TRANS_HTOTAL_CMTG_A,
> _TRANS_HTOTAL_CMTG_B)
> > +#define _TRANS_HBLANK_CMTG_A		0x6F004
> > +#define _TRANS_HBLANK_CMTG_B		0x6F104
> > +#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > +						    _TRANS_HBLANK_CMTG_A,
> _TRANS_HBLANK_CMTG_B)
> > +#define _TRANS_HSYNC_CMTG_A		0x6F008
> > +#define _TRANS_HSYNC_CMTG_B		0x6F108
> > +#define TRANS_HSYNC_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > +						    _TRANS_HSYNC_CMTG_A,
> _TRANS_HSYNC_CMTG_B)
> > +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> > +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > +						    _TRANS_VTOTAL_CMTG_A,
> _TRANS_VTOTAL_CMTG_B)
> > +#define _TRANS_VBLANK_CMTG_A		0x6F010
> > +#define _TRANS_VBLANK_CMTG_B		0x6F110
> > +#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > +						    _TRANS_VBLANK_CMTG_A,
> _TRANS_VBLANK_CMTG_B)
> > +#define _TRANS_VSYNC_CMTG_A		0x6F014
> > +#define _TRANS_VSYNC_CMTG_B		0x6F114
> > +#define TRANS_VSYNC_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > +						    _TRANS_VSYNC_CMTG_A,
> _TRANS_VSYNC_CMTG_B)
> 
> I though there was already feedback that these match the regular transcoder
> registers.

_TRANS_HTOTAL_A         0x60000
_TRANS_HTOTAL_B         0x61000

_TRANS_HTOTAL_CMTG_A            0x6F000
_TRANS_HTOTAL_CMTG_B            0x6F100

I am not clear how to match?

Regards,
Animesh
> 
> BR,
> Jani.
> 
> > +
> > +#define _TRANS_SET_CTX_LATENCY_CMTG_A	0x6F07C
> > +#define _TRANS_SET_CTX_LATENCY_CMTG_B	0x6F17C
> > +#define TRANS_SET_CTX_LATENCY_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > +
> _TRANS_SET_CTX_LATENCY_CMTG_A, \
> > +
> _TRANS_SET_CTX_LATENCY_CMTG_B)
> > +
> >  #endif /* __INTEL_CMTG_REGS_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 58a654ca0d20..bf58ae5d3535 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -60,6 +60,7 @@
> >  #include "intel_bw.h"
> >  #include "intel_cdclk.h"
> >  #include "intel_clock_gating.h"
> > +#include "intel_cmtg.h"
> >  #include "intel_color.h"
> >  #include "intel_crt.h"
> >  #include "intel_crtc.h"
> > @@ -2753,6 +2754,8 @@ static void intel_set_transcoder_timings(const
> struct intel_crtc_state *crtc_sta
> >  		intel_de_write(display,
> DP_MIN_HBLANK_CTL(cpu_transcoder),
> >  			       crtc_state->min_hblank);
> >  	}
> > +
> > +	intel_cmtg_set_timings(crtc_state, false);
> >  }
> >
> >  static void intel_set_transcoder_timings_lrr(const struct
> > intel_crtc_state *crtc_state) @@ -2814,6 +2817,7 @@ static void
> intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
> >  		       VACTIVE(crtc_vdisplay - 1) |
> >  		       VTOTAL(crtc_vtotal - 1));
> >
> > +	intel_cmtg_set_timings(crtc_state, true);
> >  	intel_vrr_set_fixed_rr_timings(crtc_state);
> >  	intel_vrr_transcoder_enable(crtc_state);
> >  }
> 
> --
> Jani Nikula, Intel

Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Ville Syrjälä]

On Fri, Apr 17, 2026 at 06:03:52AM +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Nikula, Jani <jani.nikula@intel.com>
> > Sent: Tuesday, April 14, 2026 7:03 PM
> > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> > Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Manna,
> > Animesh <animesh.manna@intel.com>
> > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> > 
> > On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > > Timing registers are separate for CMTG, read transcoder register and
> > > program cmtg transcoder with those values.
> > >
> > > v2:
> > > - Use sw state instead of reading directly from hardware. [Jani]
> > > - Move set_timing later after encoder enable. [Dibin]
> > >
> > > v3:
> > > - Replace id with trans. [Jani]
> > > - Program cmtg set_timing() along with primary transcoder timing.
> > >
> > > v4:
> > > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > > multiplication. [Jani]
> > >
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61 ++++++++++++++++++-
> > >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
> > >  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
> > >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
> > >  4 files changed, 98 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > index 403f9e10a8dc..a3db1368bd83 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > @@ -4,7 +4,6 @@
> > >   */
> > >
> > >  #include <linux/string_choices.h>
> > > -#include <linux/types.h>
> > >
> > >  #include <drm/drm_device.h>
> > >  #include <drm/drm_print.h>
> > > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct
> > intel_crtc_state *crtc_state)
> > >  	if (clk_sel_set)
> > >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> > clk_sel_set);  }
> > > +
> > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > +*crtc_state, bool lrr) {
> > > +	struct intel_display *display = to_intel_display(crtc_state);
> > > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> > >hw.adjusted_mode;
> > > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> > > +
> > > +	if (!intel_cmtg_is_allowed(crtc_state))
> > > +		return;
> > > +
> > > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > +
> > > +	/*
> > > +	 * For platforms that always use VRR Timing Generator, the
> > VTOTAL.Vtotal
> > > +	 * bits are not required. Since the support for these bits is going to
> > > +	 * be deprecated in upcoming platforms, avoid writing these bits for
> > the
> > > +	 * platforms that do not use legacy Timing Generator.
> > > +	 */
> > > +	crtc_vtotal = 1;
> > > +
> > > +	/*
> > > +	 * VBLANK_START not used by hw, just clear it
> > > +	 * to make it stand out in register dumps.
> > > +	 */
> > > +	crtc_vblank_start = 1;
> > > +
> > > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > +
> > > +	if (lrr) {
> > > +		intel_de_write(display,
> > TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > +			       VACTIVE(crtc_vdisplay - 1) |
> > > +			       VTOTAL(crtc_vtotal - 1));
> > > +		intel_de_write(display,
> > TRANS_VBLANK_CMTG(cpu_transcoder),
> > > +			       VBLANK_START(crtc_vblank_start - 1) |
> > > +			       VBLANK_END(crtc_vblank_end - 1));
> > > +		return;
> > > +	}
> > > +
> > > +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> > > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > > +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> > > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > > +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> > > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > > +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > +		       VACTIVE(crtc_vdisplay - 1) |
> > > +		       VTOTAL(crtc_vtotal - 1));
> > > +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> > > +		       VBLANK_START(crtc_vblank_start - 1) |
> > > +		       VBLANK_END(crtc_vblank_end - 1));
> > > +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > > +	intel_de_write(display,
> > TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > > +		       crtc_state->set_context_latency); }
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > index 660ec513626e..53a44f505dd2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > @@ -6,9 +6,12 @@
> > >  #ifndef __INTEL_CMTG_H__
> > >  #define __INTEL_CMTG_H__
> > >
> > > +#include <linux/types.h>
> > > +
> > >  struct intel_display;
> > >  struct intel_crtc_state;
> > >
> > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > +*crtc_state, bool lrr);
> > >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > > *display);  bool intel_cmtg_is_allowed(const struct intel_crtc_state
> > > *crtc_state); diff --git
> > > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > index 4a80b88d88fd..f7fc812d8ef0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > @@ -20,4 +20,35 @@
> > >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> > >  #define  CMTG_ENABLE			REG_BIT(31)
> > >
> > > +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> > > +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> > > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > +						    _TRANS_HTOTAL_CMTG_A,
> > _TRANS_HTOTAL_CMTG_B)
> > > +#define _TRANS_HBLANK_CMTG_A		0x6F004
> > > +#define _TRANS_HBLANK_CMTG_B		0x6F104
> > > +#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > +						    _TRANS_HBLANK_CMTG_A,
> > _TRANS_HBLANK_CMTG_B)
> > > +#define _TRANS_HSYNC_CMTG_A		0x6F008
> > > +#define _TRANS_HSYNC_CMTG_B		0x6F108
> > > +#define TRANS_HSYNC_CMTG(trans)
> > 	_MMIO_TRANS((trans), \
> > > +						    _TRANS_HSYNC_CMTG_A,
> > _TRANS_HSYNC_CMTG_B)
> > > +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> > > +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> > > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > +						    _TRANS_VTOTAL_CMTG_A,
> > _TRANS_VTOTAL_CMTG_B)
> > > +#define _TRANS_VBLANK_CMTG_A		0x6F010
> > > +#define _TRANS_VBLANK_CMTG_B		0x6F110
> > > +#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > +						    _TRANS_VBLANK_CMTG_A,
> > _TRANS_VBLANK_CMTG_B)
> > > +#define _TRANS_VSYNC_CMTG_A		0x6F014
> > > +#define _TRANS_VSYNC_CMTG_B		0x6F114
> > > +#define TRANS_VSYNC_CMTG(trans)
> > 	_MMIO_TRANS((trans), \
> > > +						    _TRANS_VSYNC_CMTG_A,
> > _TRANS_VSYNC_CMTG_B)
> > 
> > I though there was already feedback that these match the regular transcoder
> > registers.
> 
> _TRANS_HTOTAL_A         0x60000
> _TRANS_HTOTAL_B         0x61000
> 
> _TRANS_HTOTAL_CMTG_A            0x6F000
> _TRANS_HTOTAL_CMTG_B            0x6F100
> 
> I am not clear how to match?

#define TRANSCODER_CMTG0_OFFSET 0x6F000
#define TRANSCODER_CMTG1_OFFSET 0x6F100

-- 
Ville Syrjälä
Intel

RE: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, April 17, 2026 3:57 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> 
> On Fri, Apr 17, 2026 at 06:03:52AM +0000, Manna, Animesh wrote:
> >
> >
> > > -----Original Message-----
> > > From: Nikula, Jani <jani.nikula@intel.com>
> > > Sent: Tuesday, April 14, 2026 7:03 PM
> > > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > > gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> > > Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Manna,
> > > Animesh <animesh.manna@intel.com>
> > > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> > >
> > > On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com>
> wrote:
> > > > Timing registers are separate for CMTG, read transcoder register
> > > > and program cmtg transcoder with those values.
> > > >
> > > > v2:
> > > > - Use sw state instead of reading directly from hardware. [Jani]
> > > > - Move set_timing later after encoder enable. [Dibin]
> > > >
> > > > v3:
> > > > - Replace id with trans. [Jani]
> > > > - Program cmtg set_timing() along with primary transcoder timing.
> > > >
> > > > v4:
> > > > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > > > multiplication. [Jani]
> > > >
> > > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61
> ++++++++++++++++++-
> > > >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
> > > >  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
> > > >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
> > > >  4 files changed, 98 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > index 403f9e10a8dc..a3db1368bd83 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > @@ -4,7 +4,6 @@
> > > >   */
> > > >
> > > >  #include <linux/string_choices.h> -#include <linux/types.h>
> > > >
> > > >  #include <drm/drm_device.h>
> > > >  #include <drm/drm_print.h>
> > > > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct
> > > intel_crtc_state *crtc_state)
> > > >  	if (clk_sel_set)
> > > >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> > > clk_sel_set);  }
> > > > +
> > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > +*crtc_state, bool lrr) {
> > > > +	struct intel_display *display = to_intel_display(crtc_state);
> > > > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> > > >hw.adjusted_mode;
> > > > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start,
> > > > +crtc_vblank_end;
> > > > +
> > > > +	if (!intel_cmtg_is_allowed(crtc_state))
> > > > +		return;
> > > > +
> > > > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > > +
> > > > +	/*
> > > > +	 * For platforms that always use VRR Timing Generator, the
> > > VTOTAL.Vtotal
> > > > +	 * bits are not required. Since the support for these bits is going to
> > > > +	 * be deprecated in upcoming platforms, avoid writing these bits
> > > > +for
> > > the
> > > > +	 * platforms that do not use legacy Timing Generator.
> > > > +	 */
> > > > +	crtc_vtotal = 1;
> > > > +
> > > > +	/*
> > > > +	 * VBLANK_START not used by hw, just clear it
> > > > +	 * to make it stand out in register dumps.
> > > > +	 */
> > > > +	crtc_vblank_start = 1;
> > > > +
> > > > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > > +
> > > > +	if (lrr) {
> > > > +		intel_de_write(display,
> > > TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > +			       VACTIVE(crtc_vdisplay - 1) |
> > > > +			       VTOTAL(crtc_vtotal - 1));
> > > > +		intel_de_write(display,
> > > TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > +			       VBLANK_START(crtc_vblank_start - 1) |
> > > > +			       VBLANK_END(crtc_vblank_end - 1));
> > > > +		return;
> > > > +	}
> > > > +
> > > > +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> > > > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > > > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > > > +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> > > > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > > > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > > > +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> > > > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > > > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > > > +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > +		       VACTIVE(crtc_vdisplay - 1) |
> > > > +		       VTOTAL(crtc_vtotal - 1));
> > > > +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > +		       VBLANK_START(crtc_vblank_start - 1) |
> > > > +		       VBLANK_END(crtc_vblank_end - 1));
> > > > +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > > > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > > > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > > > +	intel_de_write(display,
> > > TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > > > +		       crtc_state->set_context_latency); }
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > index 660ec513626e..53a44f505dd2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > @@ -6,9 +6,12 @@
> > > >  #ifndef __INTEL_CMTG_H__
> > > >  #define __INTEL_CMTG_H__
> > > >
> > > > +#include <linux/types.h>
> > > > +
> > > >  struct intel_display;
> > > >  struct intel_crtc_state;
> > > >
> > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > +*crtc_state, bool lrr);
> > > >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > > > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > > > *display);  bool intel_cmtg_is_allowed(const struct
> > > > intel_crtc_state *crtc_state); diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > index 4a80b88d88fd..f7fc812d8ef0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > @@ -20,4 +20,35 @@
> > > >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> > > >  #define  CMTG_ENABLE			REG_BIT(31)
> > > >
> > > > +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> > > > +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> > > > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_HTOTAL_CMTG_A,
> > > _TRANS_HTOTAL_CMTG_B)
> > > > +#define _TRANS_HBLANK_CMTG_A		0x6F004
> > > > +#define _TRANS_HBLANK_CMTG_B		0x6F104
> > > > +#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_HBLANK_CMTG_A,
> > > _TRANS_HBLANK_CMTG_B)
> > > > +#define _TRANS_HSYNC_CMTG_A		0x6F008
> > > > +#define _TRANS_HSYNC_CMTG_B		0x6F108
> > > > +#define TRANS_HSYNC_CMTG(trans)
> > > 	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_HSYNC_CMTG_A,
> > > _TRANS_HSYNC_CMTG_B)
> > > > +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> > > > +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> > > > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_VTOTAL_CMTG_A,
> > > _TRANS_VTOTAL_CMTG_B)
> > > > +#define _TRANS_VBLANK_CMTG_A		0x6F010
> > > > +#define _TRANS_VBLANK_CMTG_B		0x6F110
> > > > +#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_VBLANK_CMTG_A,
> > > _TRANS_VBLANK_CMTG_B)
> > > > +#define _TRANS_VSYNC_CMTG_A		0x6F014
> > > > +#define _TRANS_VSYNC_CMTG_B		0x6F114
> > > > +#define TRANS_VSYNC_CMTG(trans)
> > > 	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_VSYNC_CMTG_A,
> > > _TRANS_VSYNC_CMTG_B)
> > >
> > > I though there was already feedback that these match the regular
> > > transcoder registers.
> >
> > _TRANS_HTOTAL_A         0x60000
> > _TRANS_HTOTAL_B         0x61000
> >
> > _TRANS_HTOTAL_CMTG_A            0x6F000
> > _TRANS_HTOTAL_CMTG_B            0x6F100
> >
> > I am not clear how to match?
> 
> #define TRANSCODER_CMTG0_OFFSET 0x6F000
> #define TRANSCODER_CMTG1_OFFSET 0x6F100

Ok, just to double check my understanding, I am putting below all the changes which maybe you are suggesting. 
Can please confirm or if I am missing something please let me know.

Step1: Define offset macro.
#define TRANSCODER_CMTGA_OFFSET 0x6F000
#define TRANSCODER_CMTGB_OFFSET 0x6F100

Step2: Add trans_cmtg_offset array in intel_display_device_info structure and initialize.
.trans_cmtg_offsets = {                                                      \
                [TRANSCODER_A] = TRANSCODER_CMTGA_OFFSET,                           \
                [TRANSCODER_B] = TRANSCODER_CMTGB_OFFSET,
},

Step3: Define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET which will use trans_cmtg_offset
#define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET(display, trans) \
        (DISPLAY_INFO((display))->trans_cmtg_offsets[(trans)] - \
         DISPLAY_INFO((display))->trans_cmtg_offsets[TRANSCODER_A] + \
        (DISPLAY_INFO((display))->trans_offsets[(trans)] - \
         DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \
         DISPLAY_MMIO_BASE((display)))

Step4: Define _MMIO_TRANS2_CMTG which will use INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET
#define _MMIO_TRANS2_CMTG(display, trans, reg)       _MMIO(INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET((display), (trans)) + (reg))

Step5: Define TRANS_HTOTAL_CMTG
#define TRANS_HTOTAL_CMTG(display, trans)	_MMIO_TRANS2_CMTG(display, (trans), _TRANS_HTOTAL_A)
#define TRANS_HBLANK_CMTG(display, trans)   _MMIO_TRANS2_CMTG(display, (trans), _TRANS_HBLANK_A)
...
...

Regards,
Animesh
 
> 
> --
> Ville Syrjälä
> Intel

RE: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Friday, April 17, 2026 3:57 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> 
> On Fri, Apr 17, 2026 at 06:03:52AM +0000, Manna, Animesh wrote:
> >
> >
> > > -----Original Message-----
> > > From: Nikula, Jani <jani.nikula@intel.com>
> > > Sent: Tuesday, April 14, 2026 7:03 PM
> > > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > > gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> > > Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Manna,
> > > Animesh <animesh.manna@intel.com>
> > > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> > >
> > > On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com>
> wrote:
> > > > Timing registers are separate for CMTG, read transcoder register
> > > > and program cmtg transcoder with those values.
> > > >
> > > > v2:
> > > > - Use sw state instead of reading directly from hardware. [Jani]
> > > > - Move set_timing later after encoder enable. [Dibin]
> > > >
> > > > v3:
> > > > - Replace id with trans. [Jani]
> > > > - Program cmtg set_timing() along with primary transcoder timing.
> > > >
> > > > v4:
> > > > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > > > multiplication. [Jani]
> > > >
> > > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61
> ++++++++++++++++++-
> > > >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
> > > >  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
> > > >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
> > > >  4 files changed, 98 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > index 403f9e10a8dc..a3db1368bd83 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > @@ -4,7 +4,6 @@
> > > >   */
> > > >
> > > >  #include <linux/string_choices.h> -#include <linux/types.h>
> > > >
> > > >  #include <drm/drm_device.h>
> > > >  #include <drm/drm_print.h>
> > > > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct
> > > intel_crtc_state *crtc_state)
> > > >  	if (clk_sel_set)
> > > >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> > > clk_sel_set);  }
> > > > +
> > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > +*crtc_state, bool lrr) {
> > > > +	struct intel_display *display = to_intel_display(crtc_state);
> > > > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> > > >hw.adjusted_mode;
> > > > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start,
> > > > +crtc_vblank_end;
> > > > +
> > > > +	if (!intel_cmtg_is_allowed(crtc_state))
> > > > +		return;
> > > > +
> > > > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > > +
> > > > +	/*
> > > > +	 * For platforms that always use VRR Timing Generator, the
> > > VTOTAL.Vtotal
> > > > +	 * bits are not required. Since the support for these bits is going to
> > > > +	 * be deprecated in upcoming platforms, avoid writing these bits
> > > > +for
> > > the
> > > > +	 * platforms that do not use legacy Timing Generator.
> > > > +	 */
> > > > +	crtc_vtotal = 1;
> > > > +
> > > > +	/*
> > > > +	 * VBLANK_START not used by hw, just clear it
> > > > +	 * to make it stand out in register dumps.
> > > > +	 */
> > > > +	crtc_vblank_start = 1;
> > > > +
> > > > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > > +
> > > > +	if (lrr) {
> > > > +		intel_de_write(display,
> > > TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > +			       VACTIVE(crtc_vdisplay - 1) |
> > > > +			       VTOTAL(crtc_vtotal - 1));
> > > > +		intel_de_write(display,
> > > TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > +			       VBLANK_START(crtc_vblank_start - 1) |
> > > > +			       VBLANK_END(crtc_vblank_end - 1));
> > > > +		return;
> > > > +	}
> > > > +
> > > > +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> > > > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > > > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > > > +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> > > > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > > > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > > > +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> > > > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > > > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > > > +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > +		       VACTIVE(crtc_vdisplay - 1) |
> > > > +		       VTOTAL(crtc_vtotal - 1));
> > > > +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > +		       VBLANK_START(crtc_vblank_start - 1) |
> > > > +		       VBLANK_END(crtc_vblank_end - 1));
> > > > +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > > > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > > > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > > > +	intel_de_write(display,
> > > TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > > > +		       crtc_state->set_context_latency); }
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > index 660ec513626e..53a44f505dd2 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > @@ -6,9 +6,12 @@
> > > >  #ifndef __INTEL_CMTG_H__
> > > >  #define __INTEL_CMTG_H__
> > > >
> > > > +#include <linux/types.h>
> > > > +
> > > >  struct intel_display;
> > > >  struct intel_crtc_state;
> > > >
> > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > +*crtc_state, bool lrr);
> > > >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > > > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > > > *display);  bool intel_cmtg_is_allowed(const struct
> > > > intel_crtc_state *crtc_state); diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > index 4a80b88d88fd..f7fc812d8ef0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > @@ -20,4 +20,35 @@
> > > >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> > > >  #define  CMTG_ENABLE			REG_BIT(31)
> > > >
> > > > +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> > > > +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> > > > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_HTOTAL_CMTG_A,
> > > _TRANS_HTOTAL_CMTG_B)
> > > > +#define _TRANS_HBLANK_CMTG_A		0x6F004
> > > > +#define _TRANS_HBLANK_CMTG_B		0x6F104
> > > > +#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_HBLANK_CMTG_A,
> > > _TRANS_HBLANK_CMTG_B)
> > > > +#define _TRANS_HSYNC_CMTG_A		0x6F008
> > > > +#define _TRANS_HSYNC_CMTG_B		0x6F108
> > > > +#define TRANS_HSYNC_CMTG(trans)
> > > 	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_HSYNC_CMTG_A,
> > > _TRANS_HSYNC_CMTG_B)
> > > > +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> > > > +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> > > > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_VTOTAL_CMTG_A,
> > > _TRANS_VTOTAL_CMTG_B)
> > > > +#define _TRANS_VBLANK_CMTG_A		0x6F010
> > > > +#define _TRANS_VBLANK_CMTG_B		0x6F110
> > > > +#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_VBLANK_CMTG_A,
> > > _TRANS_VBLANK_CMTG_B)
> > > > +#define _TRANS_VSYNC_CMTG_A		0x6F014
> > > > +#define _TRANS_VSYNC_CMTG_B		0x6F114
> > > > +#define TRANS_VSYNC_CMTG(trans)
> > > 	_MMIO_TRANS((trans), \
> > > > +						    _TRANS_VSYNC_CMTG_A,
> > > _TRANS_VSYNC_CMTG_B)
> > >
> > > I though there was already feedback that these match the regular
> > > transcoder registers.
> >
> > _TRANS_HTOTAL_A         0x60000
> > _TRANS_HTOTAL_B         0x61000
> >
> > _TRANS_HTOTAL_CMTG_A            0x6F000
> > _TRANS_HTOTAL_CMTG_B            0x6F100
> >
> > I am not clear how to match?
> 
> #define TRANSCODER_CMTG0_OFFSET 0x6F000
> #define TRANSCODER_CMTG1_OFFSET 0x6F100

Ok, just to double check my understanding, I am putting below all the changes which maybe you are suggesting. 
Can please confirm or if I am missing something please let me know.

Step1: Define offset macro.
#define TRANSCODER_CMTGA_OFFSET 0x6F000
#define TRANSCODER_CMTGB_OFFSET 0x6F100

Step2: Add trans_cmtg_offset array in intel_display_device_info structure and initialize.
.trans_cmtg_offsets = {                                                      \
                [TRANSCODER_A] = TRANSCODER_CMTGA_OFFSET,                           \
                [TRANSCODER_B] = TRANSCODER_CMTGB_OFFSET,
},

Step3: Define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET which will use trans_cmtg_offset
#define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET(display, trans) \
        (DISPLAY_INFO((display))->trans_cmtg_offsets[(trans)] - \
         DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \
         DISPLAY_MMIO_BASE((display)))

Step4: Define _MMIO_TRANS2_CMTG which will use INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET
#define _MMIO_TRANS2_CMTG(display, trans, reg)       _MMIO(INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET((display), (trans)) + (reg))

Step5: Define TRANS_HTOTAL_CMTG
#define TRANS_HTOTAL_CMTG(display, trans)	_MMIO_TRANS2_CMTG(display, (trans), _TRANS_HTOTAL_A)
#define TRANS_HBLANK_CMTG(display, trans)   _MMIO_TRANS2_CMTG(display, (trans), _TRANS_HBLANK_A)
...
...

Regards,
Animesh
> 
> --
> Ville Syrjälä
> Intel

Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Ville Syrjälä]

On Thu, Apr 23, 2026 at 04:55:55AM +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: Friday, April 17, 2026 3:57 PM
> > To: Manna, Animesh <animesh.manna@intel.com>
> > Cc: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org;
> > intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> > Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> > 
> > On Fri, Apr 17, 2026 at 06:03:52AM +0000, Manna, Animesh wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Nikula, Jani <jani.nikula@intel.com>
> > > > Sent: Tuesday, April 14, 2026 7:03 PM
> > > > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > > > gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > > Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> > > > Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Manna,
> > > > Animesh <animesh.manna@intel.com>
> > > > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> > > >
> > > > On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com>
> > wrote:
> > > > > Timing registers are separate for CMTG, read transcoder register
> > > > > and program cmtg transcoder with those values.
> > > > >
> > > > > v2:
> > > > > - Use sw state instead of reading directly from hardware. [Jani]
> > > > > - Move set_timing later after encoder enable. [Dibin]
> > > > >
> > > > > v3:
> > > > > - Replace id with trans. [Jani]
> > > > > - Program cmtg set_timing() along with primary transcoder timing.
> > > > >
> > > > > v4:
> > > > > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > > > > multiplication. [Jani]
> > > > >
> > > > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > > > ---
> > > > >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61
> > ++++++++++++++++++-
> > > > >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
> > > > >  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
> > > > >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
> > > > >  4 files changed, 98 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > index 403f9e10a8dc..a3db1368bd83 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > @@ -4,7 +4,6 @@
> > > > >   */
> > > > >
> > > > >  #include <linux/string_choices.h> -#include <linux/types.h>
> > > > >
> > > > >  #include <drm/drm_device.h>
> > > > >  #include <drm/drm_print.h>
> > > > > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const struct
> > > > intel_crtc_state *crtc_state)
> > > > >  	if (clk_sel_set)
> > > > >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> > > > clk_sel_set);  }
> > > > > +
> > > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > > +*crtc_state, bool lrr) {
> > > > > +	struct intel_display *display = to_intel_display(crtc_state);
> > > > > +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> > > > > +	const struct drm_display_mode *adjusted_mode = &crtc_state-
> > > > >hw.adjusted_mode;
> > > > > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start,
> > > > > +crtc_vblank_end;
> > > > > +
> > > > > +	if (!intel_cmtg_is_allowed(crtc_state))
> > > > > +		return;
> > > > > +
> > > > > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > > > +
> > > > > +	/*
> > > > > +	 * For platforms that always use VRR Timing Generator, the
> > > > VTOTAL.Vtotal
> > > > > +	 * bits are not required. Since the support for these bits is going to
> > > > > +	 * be deprecated in upcoming platforms, avoid writing these bits
> > > > > +for
> > > > the
> > > > > +	 * platforms that do not use legacy Timing Generator.
> > > > > +	 */
> > > > > +	crtc_vtotal = 1;
> > > > > +
> > > > > +	/*
> > > > > +	 * VBLANK_START not used by hw, just clear it
> > > > > +	 * to make it stand out in register dumps.
> > > > > +	 */
> > > > > +	crtc_vblank_start = 1;
> > > > > +
> > > > > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > > > +
> > > > > +	if (lrr) {
> > > > > +		intel_de_write(display,
> > > > TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > > +			       VACTIVE(crtc_vdisplay - 1) |
> > > > > +			       VTOTAL(crtc_vtotal - 1));
> > > > > +		intel_de_write(display,
> > > > TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > > +			       VBLANK_START(crtc_vblank_start - 1) |
> > > > > +			       VBLANK_END(crtc_vblank_end - 1));
> > > > > +		return;
> > > > > +	}
> > > > > +
> > > > > +	intel_de_write(display, TRANS_HTOTAL_CMTG(cpu_transcoder),
> > > > > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > > > > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > > > > +	intel_de_write(display, TRANS_HBLANK_CMTG(cpu_transcoder),
> > > > > +		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> > > > > +		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> > > > > +	intel_de_write(display, TRANS_HSYNC_CMTG(cpu_transcoder),
> > > > > +		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> > > > > +		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
> > > > > +	intel_de_write(display, TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > > +		       VACTIVE(crtc_vdisplay - 1) |
> > > > > +		       VTOTAL(crtc_vtotal - 1));
> > > > > +	intel_de_write(display, TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > > +		       VBLANK_START(crtc_vblank_start - 1) |
> > > > > +		       VBLANK_END(crtc_vblank_end - 1));
> > > > > +	intel_de_write(display, TRANS_VSYNC_CMTG(cpu_transcoder),
> > > > > +		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> > > > > +		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
> > > > > +	intel_de_write(display,
> > > > TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > > > > +		       crtc_state->set_context_latency); }
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > index 660ec513626e..53a44f505dd2 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > @@ -6,9 +6,12 @@
> > > > >  #ifndef __INTEL_CMTG_H__
> > > > >  #define __INTEL_CMTG_H__
> > > > >
> > > > > +#include <linux/types.h>
> > > > > +
> > > > >  struct intel_display;
> > > > >  struct intel_crtc_state;
> > > > >
> > > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > > +*crtc_state, bool lrr);
> > > > >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > > > > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > > > > *display);  bool intel_cmtg_is_allowed(const struct
> > > > > intel_crtc_state *crtc_state); diff --git
> > > > > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > index 4a80b88d88fd..f7fc812d8ef0 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > @@ -20,4 +20,35 @@
> > > > >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> > > > >  #define  CMTG_ENABLE			REG_BIT(31)
> > > > >
> > > > > +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> > > > > +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> > > > > +#define TRANS_HTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > > +						    _TRANS_HTOTAL_CMTG_A,
> > > > _TRANS_HTOTAL_CMTG_B)
> > > > > +#define _TRANS_HBLANK_CMTG_A		0x6F004
> > > > > +#define _TRANS_HBLANK_CMTG_B		0x6F104
> > > > > +#define TRANS_HBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > > +						    _TRANS_HBLANK_CMTG_A,
> > > > _TRANS_HBLANK_CMTG_B)
> > > > > +#define _TRANS_HSYNC_CMTG_A		0x6F008
> > > > > +#define _TRANS_HSYNC_CMTG_B		0x6F108
> > > > > +#define TRANS_HSYNC_CMTG(trans)
> > > > 	_MMIO_TRANS((trans), \
> > > > > +						    _TRANS_HSYNC_CMTG_A,
> > > > _TRANS_HSYNC_CMTG_B)
> > > > > +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> > > > > +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> > > > > +#define TRANS_VTOTAL_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > > +						    _TRANS_VTOTAL_CMTG_A,
> > > > _TRANS_VTOTAL_CMTG_B)
> > > > > +#define _TRANS_VBLANK_CMTG_A		0x6F010
> > > > > +#define _TRANS_VBLANK_CMTG_B		0x6F110
> > > > > +#define TRANS_VBLANK_CMTG(trans)	_MMIO_TRANS((trans), \
> > > > > +						    _TRANS_VBLANK_CMTG_A,
> > > > _TRANS_VBLANK_CMTG_B)
> > > > > +#define _TRANS_VSYNC_CMTG_A		0x6F014
> > > > > +#define _TRANS_VSYNC_CMTG_B		0x6F114
> > > > > +#define TRANS_VSYNC_CMTG(trans)
> > > > 	_MMIO_TRANS((trans), \
> > > > > +						    _TRANS_VSYNC_CMTG_A,
> > > > _TRANS_VSYNC_CMTG_B)
> > > >
> > > > I though there was already feedback that these match the regular
> > > > transcoder registers.
> > >
> > > _TRANS_HTOTAL_A         0x60000
> > > _TRANS_HTOTAL_B         0x61000
> > >
> > > _TRANS_HTOTAL_CMTG_A            0x6F000
> > > _TRANS_HTOTAL_CMTG_B            0x6F100
> > >
> > > I am not clear how to match?
> > 
> > #define TRANSCODER_CMTG0_OFFSET 0x6F000
> > #define TRANSCODER_CMTG1_OFFSET 0x6F100
> 
> Ok, just to double check my understanding, I am putting below all the changes which maybe you are suggesting. 
> Can please confirm or if I am missing something please let me know.
> 
> Step1: Define offset macro.
> #define TRANSCODER_CMTGA_OFFSET 0x6F000
> #define TRANSCODER_CMTGB_OFFSET 0x6F100

s/AB/01/ to actually match the spec.

> Step2: Add trans_cmtg_offset array in intel_display_device_info structure and initialize.
> .trans_cmtg_offsets = {                                                      \
>                 [TRANSCODER_A] = TRANSCODER_CMTGA_OFFSET,                           \
>                 [TRANSCODER_B] = TRANSCODER_CMTGB_OFFSET,
> },

They are just transcoders, so they go into .trans_offsets.
If there are any pipe register that are actually transcoder
registers then we may also need a sort of fake .pipe_offsets
(like we have for the EDP transcoder)

> Step3: Define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET which will use trans_cmtg_offset
> #define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET(display, trans) \
>         (DISPLAY_INFO((display))->trans_cmtg_offsets[(trans)] - \
>          DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \
>          DISPLAY_MMIO_BASE((display)))
> 
> Step4: Define _MMIO_TRANS2_CMTG which will use INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET
> #define _MMIO_TRANS2_CMTG(display, trans, reg)       _MMIO(INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET((display), (trans)) + (reg))
> 
> Step5: Define TRANS_HTOTAL_CMTG
> #define TRANS_HTOTAL_CMTG(display, trans)	_MMIO_TRANS2_CMTG(display, (trans), _TRANS_HTOTAL_A)
> #define TRANS_HBLANK_CMTG(display, trans)   _MMIO_TRANS2_CMTG(display, (trans), _TRANS_HBLANK_A)

No, you just use TRANS_HTOTAL() and co.

Or at least that's my current thinking. Avoids all the duplicated stuff.

-- 
Ville Syrjälä
Intel

RE: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG

[Manna, Animesh]

> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, April 23, 2026 4:22 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>;
> Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> 
> On Thu, Apr 23, 2026 at 04:55:55AM +0000, Manna, Animesh wrote:
> >
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: Friday, April 17, 2026 3:57 PM
> > > To: Manna, Animesh <animesh.manna@intel.com>
> > > Cc: Nikula, Jani <jani.nikula@intel.com>;
> > > intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org;
> > > Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> Subrahmanian
> > > <dibin.moolakadan.subrahmanian@intel.com>
> > > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for CMTG
> > >
> > > On Fri, Apr 17, 2026 at 06:03:52AM +0000, Manna, Animesh wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Nikula, Jani <jani.nikula@intel.com>
> > > > > Sent: Tuesday, April 14, 2026 7:03 PM
> > > > > To: Manna, Animesh <animesh.manna@intel.com>; intel-
> > > > > gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > > > > Cc: Shankar, Uma <uma.shankar@intel.com>; Dibin Moolakadan
> > > > > Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>;
> Manna,
> > > > > Animesh <animesh.manna@intel.com>
> > > > > Subject: Re: [PATCH v4 03/13] drm/i915/cmtg: Set timings for
> > > > > CMTG
> > > > >
> > > > > On Sun, 12 Apr 2026, Animesh Manna <animesh.manna@intel.com>
> > > wrote:
> > > > > > Timing registers are separate for CMTG, read transcoder
> > > > > > register and program cmtg transcoder with those values.
> > > > > >
> > > > > > v2:
> > > > > > - Use sw state instead of reading directly from hardware.
> > > > > > [Jani]
> > > > > > - Move set_timing later after encoder enable. [Dibin]
> > > > > >
> > > > > > v3:
> > > > > > - Replace id with trans. [Jani]
> > > > > > - Program cmtg set_timing() along with primary transcoder timing.
> > > > > >
> > > > > > v4:
> > > > > > - Use _MMIO_TRANS() for cmtg registers instead of direct
> > > > > > multiplication. [Jani]
> > > > > >
> > > > > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > > > > ---
> > > > > >  drivers/gpu/drm/i915/display/intel_cmtg.c     | 61
> > > ++++++++++++++++++-
> > > > > >  drivers/gpu/drm/i915/display/intel_cmtg.h     |  3 +
> > > > > >  .../gpu/drm/i915/display/intel_cmtg_regs.h    | 31 ++++++++++
> > > > > >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++
> > > > > >  4 files changed, 98 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > > index 403f9e10a8dc..a3db1368bd83 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.c
> > > > > > @@ -4,7 +4,6 @@
> > > > > >   */
> > > > > >
> > > > > >  #include <linux/string_choices.h> -#include <linux/types.h>
> > > > > >
> > > > > >  #include <drm/drm_device.h>
> > > > > >  #include <drm/drm_print.h>
> > > > > > @@ -222,3 +221,63 @@ void intel_cmtg_set_clk_select(const
> > > > > > struct
> > > > > intel_crtc_state *crtc_state)
> > > > > >  	if (clk_sel_set)
> > > > > >  		intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr,
> > > > > clk_sel_set);  }
> > > > > > +
> > > > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > > > +*crtc_state, bool lrr) {
> > > > > > +	struct intel_display *display = to_intel_display(crtc_state);
> > > > > > +	enum transcoder cpu_transcoder = crtc_state-
> >cpu_transcoder;
> > > > > > +	const struct drm_display_mode *adjusted_mode =
> &crtc_state-
> > > > > >hw.adjusted_mode;
> > > > > > +	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start,
> > > > > > +crtc_vblank_end;
> > > > > > +
> > > > > > +	if (!intel_cmtg_is_allowed(crtc_state))
> > > > > > +		return;
> > > > > > +
> > > > > > +	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> > > > > > +
> > > > > > +	/*
> > > > > > +	 * For platforms that always use VRR Timing Generator, the
> > > > > VTOTAL.Vtotal
> > > > > > +	 * bits are not required. Since the support for these bits is
> going to
> > > > > > +	 * be deprecated in upcoming platforms, avoid writing these
> > > > > > +bits for
> > > > > the
> > > > > > +	 * platforms that do not use legacy Timing Generator.
> > > > > > +	 */
> > > > > > +	crtc_vtotal = 1;
> > > > > > +
> > > > > > +	/*
> > > > > > +	 * VBLANK_START not used by hw, just clear it
> > > > > > +	 * to make it stand out in register dumps.
> > > > > > +	 */
> > > > > > +	crtc_vblank_start = 1;
> > > > > > +
> > > > > > +	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
> > > > > > +
> > > > > > +	if (lrr) {
> > > > > > +		intel_de_write(display,
> > > > > TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > > > +			       VACTIVE(crtc_vdisplay - 1) |
> > > > > > +			       VTOTAL(crtc_vtotal - 1));
> > > > > > +		intel_de_write(display,
> > > > > TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > > > +			       VBLANK_START(crtc_vblank_start - 1) |
> > > > > > +			       VBLANK_END(crtc_vblank_end - 1));
> > > > > > +		return;
> > > > > > +	}
> > > > > > +
> > > > > > +	intel_de_write(display,
> TRANS_HTOTAL_CMTG(cpu_transcoder),
> > > > > > +		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> > > > > > +		       HTOTAL(adjusted_mode->crtc_htotal - 1));
> > > > > > +	intel_de_write(display,
> TRANS_HBLANK_CMTG(cpu_transcoder),
> > > > > > +		       HBLANK_START(adjusted_mode-
> >crtc_hblank_start - 1) |
> > > > > > +		       HBLANK_END(adjusted_mode->crtc_hblank_end
> - 1));
> > > > > > +	intel_de_write(display,
> TRANS_HSYNC_CMTG(cpu_transcoder),
> > > > > > +		       HSYNC_START(adjusted_mode->crtc_hsync_start
> - 1) |
> > > > > > +		       HSYNC_END(adjusted_mode->crtc_hsync_end -
> 1));
> > > > > > +	intel_de_write(display,
> TRANS_VTOTAL_CMTG(cpu_transcoder),
> > > > > > +		       VACTIVE(crtc_vdisplay - 1) |
> > > > > > +		       VTOTAL(crtc_vtotal - 1));
> > > > > > +	intel_de_write(display,
> TRANS_VBLANK_CMTG(cpu_transcoder),
> > > > > > +		       VBLANK_START(crtc_vblank_start - 1) |
> > > > > > +		       VBLANK_END(crtc_vblank_end - 1));
> > > > > > +	intel_de_write(display,
> TRANS_VSYNC_CMTG(cpu_transcoder),
> > > > > > +		       VSYNC_START(adjusted_mode->crtc_vsync_start -
> 1) |
> > > > > > +		       VSYNC_END(adjusted_mode->crtc_vsync_end -
> 1));
> > > > > > +	intel_de_write(display,
> > > > > TRANS_SET_CTX_LATENCY_CMTG(cpu_transcoder),
> > > > > > +		       crtc_state->set_context_latency); }
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > > index 660ec513626e..53a44f505dd2 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg.h
> > > > > > @@ -6,9 +6,12 @@
> > > > > >  #ifndef __INTEL_CMTG_H__
> > > > > >  #define __INTEL_CMTG_H__
> > > > > >
> > > > > > +#include <linux/types.h>
> > > > > > +
> > > > > >  struct intel_display;
> > > > > >  struct intel_crtc_state;
> > > > > >
> > > > > > +void intel_cmtg_set_timings(const struct intel_crtc_state
> > > > > > +*crtc_state, bool lrr);
> > > > > >  void intel_cmtg_set_clk_select(const struct intel_crtc_state
> > > > > > *crtc_state);  void intel_cmtg_sanitize(struct intel_display
> > > > > > *display);  bool intel_cmtg_is_allowed(const struct
> > > > > > intel_crtc_state *crtc_state); diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > > index 4a80b88d88fd..f7fc812d8ef0 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_cmtg_regs.h
> > > > > > @@ -20,4 +20,35 @@
> > > > > >  #define TRANS_CMTG_CTL_B		_MMIO(0x6fb88)
> > > > > >  #define  CMTG_ENABLE			REG_BIT(31)
> > > > > >
> > > > > > +#define _TRANS_HTOTAL_CMTG_A		0x6F000
> > > > > > +#define _TRANS_HTOTAL_CMTG_B		0x6F100
> > > > > > +#define TRANS_HTOTAL_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > > > > > +
> _TRANS_HTOTAL_CMTG_A,
> > > > > _TRANS_HTOTAL_CMTG_B)
> > > > > > +#define _TRANS_HBLANK_CMTG_A		0x6F004
> > > > > > +#define _TRANS_HBLANK_CMTG_B		0x6F104
> > > > > > +#define TRANS_HBLANK_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > > > > > +
> _TRANS_HBLANK_CMTG_A,
> > > > > _TRANS_HBLANK_CMTG_B)
> > > > > > +#define _TRANS_HSYNC_CMTG_A		0x6F008
> > > > > > +#define _TRANS_HSYNC_CMTG_B		0x6F108
> > > > > > +#define TRANS_HSYNC_CMTG(trans)
> > > > > 	_MMIO_TRANS((trans), \
> > > > > > +
> _TRANS_HSYNC_CMTG_A,
> > > > > _TRANS_HSYNC_CMTG_B)
> > > > > > +#define _TRANS_VTOTAL_CMTG_A		0x6F00C
> > > > > > +#define _TRANS_VTOTAL_CMTG_B		0x6F10C
> > > > > > +#define TRANS_VTOTAL_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > > > > > +
> _TRANS_VTOTAL_CMTG_A,
> > > > > _TRANS_VTOTAL_CMTG_B)
> > > > > > +#define _TRANS_VBLANK_CMTG_A		0x6F010
> > > > > > +#define _TRANS_VBLANK_CMTG_B		0x6F110
> > > > > > +#define TRANS_VBLANK_CMTG(trans)
> 	_MMIO_TRANS((trans), \
> > > > > > +
> _TRANS_VBLANK_CMTG_A,
> > > > > _TRANS_VBLANK_CMTG_B)
> > > > > > +#define _TRANS_VSYNC_CMTG_A		0x6F014
> > > > > > +#define _TRANS_VSYNC_CMTG_B		0x6F114
> > > > > > +#define TRANS_VSYNC_CMTG(trans)
> > > > > 	_MMIO_TRANS((trans), \
> > > > > > +
> _TRANS_VSYNC_CMTG_A,
> > > > > _TRANS_VSYNC_CMTG_B)
> > > > >
> > > > > I though there was already feedback that these match the regular
> > > > > transcoder registers.
> > > >
> > > > _TRANS_HTOTAL_A         0x60000
> > > > _TRANS_HTOTAL_B         0x61000
> > > >
> > > > _TRANS_HTOTAL_CMTG_A            0x6F000
> > > > _TRANS_HTOTAL_CMTG_B            0x6F100
> > > >
> > > > I am not clear how to match?
> > >
> > > #define TRANSCODER_CMTG0_OFFSET 0x6F000 #define
> > > TRANSCODER_CMTG1_OFFSET 0x6F100
> >
> > Ok, just to double check my understanding, I am putting below all the
> changes which maybe you are suggesting.
> > Can please confirm or if I am missing something please let me know.
> >
> > Step1: Define offset macro.
> > #define TRANSCODER_CMTGA_OFFSET 0x6F000 #define
> > TRANSCODER_CMTGB_OFFSET 0x6F100
> 
> s/AB/01/ to actually match the spec.

Ok.

> 
> > Step2: Add trans_cmtg_offset array in intel_display_device_info structure
> and initialize.
> > .trans_cmtg_offsets = {                                                      \
> >                 [TRANSCODER_A] = TRANSCODER_CMTGA_OFFSET,
> \
> >                 [TRANSCODER_B] = TRANSCODER_CMTGB_OFFSET, },
> 
> They are just transcoders, so they go into .trans_offsets.
> If there are any pipe register that are actually transcoder registers then we
> may also need a sort of fake .pipe_offsets (like we have for the EDP
> transcoder)

Only CMTG transcoder is not enough, cmtg transcoder will be enabled along with normal transcoder.
Normal transcoder will use .trans_offsets and cmtg transcoder need separate structure .trans_cmtg_offsets for storing offset. So added separately.

> 
> > Step3: Define INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET which will use
> > trans_cmtg_offset #define
> INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET(display, trans) \
> >         (DISPLAY_INFO((display))->trans_cmtg_offsets[(trans)] - \
> >          DISPLAY_INFO((display))->trans_offsets[TRANSCODER_A] + \
> >          DISPLAY_MMIO_BASE((display)))
> >
> > Step4: Define _MMIO_TRANS2_CMTG which will use
> INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET
> > #define _MMIO_TRANS2_CMTG(display, trans, reg)
> _MMIO(INTEL_DISPLAY_DEVICE_TRANS_CMTG_OFFSET((display), (trans)) +
> (reg))
> >
> > Step5: Define TRANS_HTOTAL_CMTG
> > #define TRANS_HTOTAL_CMTG(display, trans)
> 	_MMIO_TRANS2_CMTG(display, (trans), _TRANS_HTOTAL_A)
> > #define TRANS_HBLANK_CMTG(display, trans)
> _MMIO_TRANS2_CMTG(display, (trans), _TRANS_HBLANK_A)
> 
> No, you just use TRANS_HTOTAL() and co.
> 
> Or at least that's my current thinking. Avoids all the duplicated stuff.

Same like above - Only CMTG transcoder is not enough, cmtg transcoder will be enabled along with normal transcoder.
So, we need both TRANS_HTOTAL() and TRANS_HTOTAL_CMTG().
Please let me know for any additional details and the above change still needed or not. Because only NVL will be supporting CMTG.

Regards,
Animesh
> 
> --
> Ville Syrjälä
> Intel