[PATCH 00/11] Enable per exec queue MSI-X vector assignment

[PATCH 00/11] Enable per exec queue MSI-X vector assignment

[Stuart Summers]

This series adds support for per exec queue MSI-X vector
assignment as well as a per exec queue wait queue in the
wait user fence ioctl. MSI-X vectors are dynamically assigned
during exec queue creation up to a set maximum. Once the max
is reached, everything else falls back to the default vector.

These dynamic vectors allow us to wake up a targeted wait
queue and user thread instead of broadcasting out to all
potential user threads like we're doing today. This is interesting
when we have many user threads outstanding as we don't want
to wake them up in a storm for each interrupt coming in.

Additionally, there have been changes in the memirq code lately
to isolate some of the interrupts handled here. Starting with
xe3p, however, we have new interrupts available for compute walker
post sync interrupts. Currently these are enabled for legacy MSI
use cases, but the bits are also available for MSI-X. Enable
those bits here.

v2: Drop the drm_dbg change patch
    Directly call xe_hw_engine_handle_irq() from xe_memirq_hwe_handler()
    Only add to ufence_list for user queues

Stuart Summers (11):
  drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl()
  drm/xe: Handle NULL in xe_exec_queue_get_unless_zero()
  drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS
  drm/xe: Assign dedicated MSI-X vectors to exec queues
  drm/xe: Add configfs max_msix_vecs attribute
  drm/xe: Remove memirq status and source checks for engine interrupts
  drm/xe: Add per-exec-queue user fence wait queue
  drm/xe: Track all exec queues in a device-level ufence list
  drm/xe: Hook up per queue thread wake to the unique MSI-X vector
    allocation
  drm/xe: Enable per-queue ufence wake in ioctl and wake function
  drm/xe/memirq: Enable compute walker post-sync interrupt

 drivers/gpu/drm/xe/regs/xe_lrc_layout.h  |  3 +
 drivers/gpu/drm/xe/xe_configfs.c         | 71 ++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h         |  6 ++
 drivers/gpu/drm/xe/xe_device.c           |  2 +
 drivers/gpu/drm/xe/xe_device_types.h     | 11 ++++
 drivers/gpu/drm/xe/xe_exec_queue.c       | 51 ++++++++++++++++-
 drivers/gpu/drm/xe/xe_exec_queue.h       |  2 +-
 drivers/gpu/drm/xe/xe_exec_queue_types.h |  6 ++
 drivers/gpu/drm/xe/xe_guc_submit.c       |  6 +-
 drivers/gpu/drm/xe/xe_hw_engine.c        |  6 +-
 drivers/gpu/drm/xe/xe_hw_engine.h        |  3 +-
 drivers/gpu/drm/xe/xe_irq.c              | 36 ++++++++++--
 drivers/gpu/drm/xe/xe_irq.h              |  9 +++
 drivers/gpu/drm/xe/xe_lrc.c              | 15 ++++-
 drivers/gpu/drm/xe/xe_memirq.c           | 59 +++++++++-----------
 drivers/gpu/drm/xe/xe_memirq.h           |  4 +-
 drivers/gpu/drm/xe/xe_sync.c             |  3 +-
 drivers/gpu/drm/xe/xe_wait_user_fence.c  | 64 ++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++
 19 files changed, 310 insertions(+), 51 deletions(-)

-- 
2.43.0

[PATCH 01/11] drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl()

[Stuart Summers]

Document the function use case and expectations. Planning
upcoming changes in this file that add some behavioral changes
to the wait queue implementation here, so having the documentation
up front is helpful when describing those upcoming changes.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_wait_user_fence.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c
index 51eb940ceb4e..12ceb3efa8ea 100644
--- a/drivers/gpu/drm/xe/xe_wait_user_fence.c
+++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c
@@ -97,6 +97,28 @@ static long to_jiffies_timeout(struct xe_device *xe,
 	return timeout ?: 1;
 }
 
+/**
+ * xe_wait_user_fence_ioctl() - Wait on a user fence
+ * @dev: DRM device
+ * @data: pointer to a &drm_xe_wait_user_fence
+ * @file: DRM file
+ *
+ * Waits until the value at a user-provided memory address satisfies a
+ * comparison condition, or until a timeout expires. The comparison is
+ * performed as (@addr & @mask) OP @value, where OP is one of the
+ * %DRM_XE_UFENCE_WAIT_OP_* operators.
+ *
+ * If an exec queue ID is provided, the wait is aborted early if the
+ * queue enters a reset state. The device-level wait queue is used for
+ * wakeups.
+ *
+ * On return, @timeout is updated to reflect the remaining time (or zero
+ * on expiry), unless %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME is set.
+ *
+ * Return: 0 on success, -ETIME if the timeout expired before the
+ * condition was met, -ERESTARTSYS if interrupted by a signal, -EIO if
+ * the exec queue was reset, or a negative error code on invalid input.
+ */
 int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
 			     struct drm_file *file)
 {
-- 
2.43.0

[PATCH 02/11] drm/xe: Handle NULL in xe_exec_queue_get_unless_zero()

[Stuart Summers]

The function currently dereferences @q unconditionally. Add a NULL
guard so callers can pass NULL without a crash, which simplifies
call sites that conditionally wrap the call.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_exec_queue.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h
index 0225426c57b0..2624aa676517 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue.h
@@ -38,7 +38,7 @@ void xe_exec_queue_assign_name(struct xe_exec_queue *q, u32 instance);
 static inline struct xe_exec_queue *
 xe_exec_queue_get_unless_zero(struct xe_exec_queue *q)
 {
-	if (kref_get_unless_zero(&q->refcount))
+	if (q && kref_get_unless_zero(&q->refcount))
 		return q;
 
 	return NULL;
-- 
2.43.0

[PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS

[Stuart Summers]

Introduce XE_MSIX_MAX_VECS (1024) as a software cap on the total number
of MSI-X vectors the driver will use. We want a way to cap the number
of vectors separately from the PCIe capability. This way we can more
easily manage certain system-wide configurations that might differ
from the per-device level configuration.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_irq.c | 2 +-
 drivers/gpu/drm/xe/xe_irq.h | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9e49e2241da4..3429bb305293 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -895,7 +895,7 @@ static int xe_irq_msix_init(struct xe_device *xe)
 		return nvec;
 	}
 
-	xe->irq.msix.nvec = nvec;
+	xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
 	xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
index a28bd577ba52..5f48249dae8a 100644
--- a/drivers/gpu/drm/xe/xe_irq.h
+++ b/drivers/gpu/drm/xe/xe_irq.h
@@ -10,6 +10,13 @@
 
 #define XE_IRQ_DEFAULT_MSIX 1
 
+/*
+ * Software cap on the total number of MSI-X vectors the driver will use.
+ * Allows the supported vectors to be managed independent of the PCI
+ * config space report.
+ */
+#define XE_MSIX_MAX_VECS 1024
+
 struct xe_device;
 struct xe_tile;
 struct xe_gt;
-- 
2.43.0

Re: [PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS

[Maarten Lankhorst]

Hello,

On 6/10/26 23:28, Stuart Summers wrote:
> Introduce XE_MSIX_MAX_VECS (1024) as a software cap on the total number
> of MSI-X vectors the driver will use. We want a way to cap the number
> of vectors separately from the PCIe capability. This way we can more
> easily manage certain system-wide configurations that might differ
> from the per-device level configuration.
>
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Assisted-by: Copilot:claude-sonnet-4.6
> ---
>  drivers/gpu/drm/xe/xe_irq.c | 2 +-
>  drivers/gpu/drm/xe/xe_irq.h | 7 +++++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 9e49e2241da4..3429bb305293 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -895,7 +895,7 @@ static int xe_irq_msix_init(struct xe_device *xe)
>  		return nvec;
>  	}
>  
> -	xe->irq.msix.nvec = nvec;
> +	xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
>  	xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
>  	return 0;
>  }
> diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
> index a28bd577ba52..5f48249dae8a 100644
> --- a/drivers/gpu/drm/xe/xe_irq.h
> +++ b/drivers/gpu/drm/xe/xe_irq.h
> @@ -10,6 +10,13 @@
>  
>  #define XE_IRQ_DEFAULT_MSIX 1
>  
> +/*
> + * Software cap on the total number of MSI-X vectors the driver will use.
> + * Allows the supported vectors to be managed independent of the PCI
> + * config space report.
> + */
> +#define XE_MSIX_MAX_VECS 1024
> +
>  struct xe_device;
>  struct xe_tile;
>  struct xe_gt;

I took a quick look at the PCI docs for the kernel.

pci_alloc_irq_vectors will request a minimum of 1024 vectors in this case,
but is allowed to allocate more.

Although we should set a sensible default using pci_msix_vec_count(),
I'm not sure it makes sense to specifically limit them if we can use as many as we like.

The return value of pci_alloc_irq_vectors returns the amount of vectors actually available, so this patch clamps the amount available without necessity.

What about this instead, and drop configfs?

xe->irq.msix.nvec = err = pci_alloc_irq_vectors(pdev, NUM_OF_STATIC_MSIX, pci_msix_vec_count()) ?

In this case, we get the maximum amount of vectors available, without requiring any caps or requiring configfs.

If MSI-X vectors really provide a speedup, would it be beneficial to use those on the migration queues as well?

Kind regards,
~Maarten Lankhorst

Re: [PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS

[Summers, Stuart]

On Thu, 2026-06-11 at 12:47 +0200, Maarten Lankhorst wrote:
> Hello,
> 
> On 6/10/26 23:28, Stuart Summers wrote:
> > Introduce XE_MSIX_MAX_VECS (1024) as a software cap on the total
> > number
> > of MSI-X vectors the driver will use. We want a way to cap the
> > number
> > of vectors separately from the PCIe capability. This way we can
> > more
> > easily manage certain system-wide configurations that might differ
> > from the per-device level configuration.
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Assisted-by: Copilot:claude-sonnet-4.6
> > ---
> >  drivers/gpu/drm/xe/xe_irq.c | 2 +-
> >  drivers/gpu/drm/xe/xe_irq.h | 7 +++++++
> >  2 files changed, 8 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c
> > b/drivers/gpu/drm/xe/xe_irq.c
> > index 9e49e2241da4..3429bb305293 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -895,7 +895,7 @@ static int xe_irq_msix_init(struct xe_device
> > *xe)
> >                 return nvec;
> >         }
> >  
> > -       xe->irq.msix.nvec = nvec;
> > +       xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
> >         xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
> >         return 0;
> >  }
> > diff --git a/drivers/gpu/drm/xe/xe_irq.h
> > b/drivers/gpu/drm/xe/xe_irq.h
> > index a28bd577ba52..5f48249dae8a 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.h
> > +++ b/drivers/gpu/drm/xe/xe_irq.h
> > @@ -10,6 +10,13 @@
> >  
> >  #define XE_IRQ_DEFAULT_MSIX 1
> >  
> > +/*
> > + * Software cap on the total number of MSI-X vectors the driver
> > will use.
> > + * Allows the supported vectors to be managed independent of the
> > PCI
> > + * config space report.
> > + */
> > +#define XE_MSIX_MAX_VECS 1024
> > +
> >  struct xe_device;
> >  struct xe_tile;
> >  struct xe_gt;
> 
> I took a quick look at the PCI docs for the kernel.
> 
> pci_alloc_irq_vectors will request a minimum of 1024 vectors in this
> case,
> but is allowed to allocate more.
> 
> Although we should set a sensible default using pci_msix_vec_count(),
> I'm not sure it makes sense to specifically limit them if we can use
> as many as we like.
> 
> The return value of pci_alloc_irq_vectors returns the amount of
> vectors actually available, so this patch clamps the amount available
> without necessity.
> 
> What about this instead, and drop configfs?
> 
> xe->irq.msix.nvec = err = pci_alloc_irq_vectors(pdev,
> NUM_OF_STATIC_MSIX, pci_msix_vec_count()) ?
> 
> In this case, we get the maximum amount of vectors available, without
> requiring any caps or requiring configfs.
> 
> If MSI-X vectors really provide a speedup, would it be beneficial to
> use those on the migration queues as well?

So there are two issues I'm trying to solve with this and the configfs
patch (mostly the configfs patch).

1) Our hardware might report a value, but depending on the generation,
the firmware might limit the amount we can realistically configure for
various reasons. I realize we don't want to necessarily override the
PCIe config without reason, but we also want to make sure we aren't
trying to allocate more than the firmware has set up for us in terms of
security, etc. We want to catch this kind of thing in software if
possible rather than allocating vectors that are masked in hardware and
only find out when the user apps start hanging (because the interrupts
they expected aren't coming in).

2) There are use cases like vmware that limit not by the device, but by
the entire system. Our device and firmware might support something like
1024, but we are just one of many devices in the system and in the
hypervisor we want a way to limit this without having to change the
BIOS configuration.

Thanks,
Stuart

> 
> Kind regards,
> ~Maarten Lankhorst

Re: [PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS

[Maarten Lankhorst]

Hey,

On 6/12/26 00:49, Summers, Stuart wrote:
> On Thu, 2026-06-11 at 12:47 +0200, Maarten Lankhorst wrote:
>> Hello,
>>
>> On 6/10/26 23:28, Stuart Summers wrote:
>>> Introduce XE_MSIX_MAX_VECS (1024) as a software cap on the total
>>> number
>>> of MSI-X vectors the driver will use. We want a way to cap the
>>> number
>>> of vectors separately from the PCIe capability. This way we can
>>> more
>>> easily manage certain system-wide configurations that might differ
>>> from the per-device level configuration.
>>>
>>> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
>>> Assisted-by: Copilot:claude-sonnet-4.6
>>> ---
>>>  drivers/gpu/drm/xe/xe_irq.c | 2 +-
>>>  drivers/gpu/drm/xe/xe_irq.h | 7 +++++++
>>>  2 files changed, 8 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.c
>>> b/drivers/gpu/drm/xe/xe_irq.c
>>> index 9e49e2241da4..3429bb305293 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.c
>>> +++ b/drivers/gpu/drm/xe/xe_irq.c
>>> @@ -895,7 +895,7 @@ static int xe_irq_msix_init(struct xe_device
>>> *xe)
>>>                 return nvec;
>>>         }
>>>  
>>> -       xe->irq.msix.nvec = nvec;
>>> +       xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
>>>         xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
>>>         return 0;
>>>  }
>>> diff --git a/drivers/gpu/drm/xe/xe_irq.h
>>> b/drivers/gpu/drm/xe/xe_irq.h
>>> index a28bd577ba52..5f48249dae8a 100644
>>> --- a/drivers/gpu/drm/xe/xe_irq.h
>>> +++ b/drivers/gpu/drm/xe/xe_irq.h
>>> @@ -10,6 +10,13 @@
>>>  
>>>  #define XE_IRQ_DEFAULT_MSIX 1
>>>  
>>> +/*
>>> + * Software cap on the total number of MSI-X vectors the driver
>>> will use.
>>> + * Allows the supported vectors to be managed independent of the
>>> PCI
>>> + * config space report.
>>> + */
>>> +#define XE_MSIX_MAX_VECS 1024
>>> +
>>>  struct xe_device;
>>>  struct xe_tile;
>>>  struct xe_gt;
>> I took a quick look at the PCI docs for the kernel.
>>
>> pci_alloc_irq_vectors will request a minimum of 1024 vectors in this
>> case,
>> but is allowed to allocate more.
>>
>> Although we should set a sensible default using pci_msix_vec_count(),
>> I'm not sure it makes sense to specifically limit them if we can use
>> as many as we like.
>>
>> The return value of pci_alloc_irq_vectors returns the amount of
>> vectors actually available, so this patch clamps the amount available
>> without necessity.
>>
>> What about this instead, and drop configfs?
>>
>> xe->irq.msix.nvec = err = pci_alloc_irq_vectors(pdev,
>> NUM_OF_STATIC_MSIX, pci_msix_vec_count()) ?
>>
>> In this case, we get the maximum amount of vectors available, without
>> requiring any caps or requiring configfs.
>>
>> If MSI-X vectors really provide a speedup, would it be beneficial to
>> use those on the migration queues as well?
> So there are two issues I'm trying to solve with this and the configfs
> patch (mostly the configfs patch).
>
> 1) Our hardware might report a value, but depending on the generation,
> the firmware might limit the amount we can realistically configure for
> various reasons. I realize we don't want to necessarily override the
> PCIe config without reason, but we also want to make sure we aren't
> trying to allocate more than the firmware has set up for us in terms of
> security, etc. We want to catch this kind of thing in software if
> possible rather than allocating vectors that are masked in hardware and
> only find out when the user apps start hanging (because the interrupts
> they expected aren't coming in).
>
> 2) There are use cases like vmware that limit not by the device, but by
> the entire system. Our device and firmware might support something like
> 1024, but we are just one of many devices in the system and in the
> hypervisor we want a way to limit this without having to change the
> BIOS configuration.

Yeah makes sense. Is the firmware here GuC or UEFI?

If our device supports only 1024 then it's safe to have it as limit.

Kind regards,

~Maarten Lankhorst

Re: [PATCH 03/11] drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS

[Summers, Stuart]

On Fri, 2026-06-12 at 10:50 +0200, Maarten Lankhorst wrote:
> Hey,
> 
> On 6/12/26 00:49, Summers, Stuart wrote:
> > On Thu, 2026-06-11 at 12:47 +0200, Maarten Lankhorst wrote:
> > > Hello,
> > > 
> > > On 6/10/26 23:28, Stuart Summers wrote:
> > > > Introduce XE_MSIX_MAX_VECS (1024) as a software cap on the
> > > > total
> > > > number
> > > > of MSI-X vectors the driver will use. We want a way to cap the
> > > > number
> > > > of vectors separately from the PCIe capability. This way we can
> > > > more
> > > > easily manage certain system-wide configurations that might
> > > > differ
> > > > from the per-device level configuration.
> > > > 
> > > > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > > > Assisted-by: Copilot:claude-sonnet-4.6
> > > > ---
> > > >  drivers/gpu/drm/xe/xe_irq.c | 2 +-
> > > >  drivers/gpu/drm/xe/xe_irq.h | 7 +++++++
> > > >  2 files changed, 8 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_irq.c
> > > > b/drivers/gpu/drm/xe/xe_irq.c
> > > > index 9e49e2241da4..3429bb305293 100644
> > > > --- a/drivers/gpu/drm/xe/xe_irq.c
> > > > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > > > @@ -895,7 +895,7 @@ static int xe_irq_msix_init(struct
> > > > xe_device
> > > > *xe)
> > > >                 return nvec;
> > > >         }
> > > >  
> > > > -       xe->irq.msix.nvec = nvec;
> > > > +       xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
> > > >         xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
> > > >         return 0;
> > > >  }
> > > > diff --git a/drivers/gpu/drm/xe/xe_irq.h
> > > > b/drivers/gpu/drm/xe/xe_irq.h
> > > > index a28bd577ba52..5f48249dae8a 100644
> > > > --- a/drivers/gpu/drm/xe/xe_irq.h
> > > > +++ b/drivers/gpu/drm/xe/xe_irq.h
> > > > @@ -10,6 +10,13 @@
> > > >  
> > > >  #define XE_IRQ_DEFAULT_MSIX 1
> > > >  
> > > > +/*
> > > > + * Software cap on the total number of MSI-X vectors the
> > > > driver
> > > > will use.
> > > > + * Allows the supported vectors to be managed independent of
> > > > the
> > > > PCI
> > > > + * config space report.
> > > > + */
> > > > +#define XE_MSIX_MAX_VECS 1024
> > > > +
> > > >  struct xe_device;
> > > >  struct xe_tile;
> > > >  struct xe_gt;
> > > I took a quick look at the PCI docs for the kernel.
> > > 
> > > pci_alloc_irq_vectors will request a minimum of 1024 vectors in
> > > this
> > > case,
> > > but is allowed to allocate more.
> > > 
> > > Although we should set a sensible default using
> > > pci_msix_vec_count(),
> > > I'm not sure it makes sense to specifically limit them if we can
> > > use
> > > as many as we like.
> > > 
> > > The return value of pci_alloc_irq_vectors returns the amount of
> > > vectors actually available, so this patch clamps the amount
> > > available
> > > without necessity.
> > > 
> > > What about this instead, and drop configfs?
> > > 
> > > xe->irq.msix.nvec = err = pci_alloc_irq_vectors(pdev,
> > > NUM_OF_STATIC_MSIX, pci_msix_vec_count()) ?
> > > 
> > > In this case, we get the maximum amount of vectors available,
> > > without
> > > requiring any caps or requiring configfs.
> > > 
> > > If MSI-X vectors really provide a speedup, would it be beneficial
> > > to
> > > use those on the migration queues as well?
> > So there are two issues I'm trying to solve with this and the
> > configfs
> > patch (mostly the configfs patch).
> > 
> > 1) Our hardware might report a value, but depending on the
> > generation,
> > the firmware might limit the amount we can realistically configure
> > for
> > various reasons. I realize we don't want to necessarily override
> > the
> > PCIe config without reason, but we also want to make sure we aren't
> > trying to allocate more than the firmware has set up for us in
> > terms of
> > security, etc. We want to catch this kind of thing in software if
> > possible rather than allocating vectors that are masked in hardware
> > and
> > only find out when the user apps start hanging (because the
> > interrupts
> > they expected aren't coming in).
> > 
> > 2) There are use cases like vmware that limit not by the device,
> > but by
> > the entire system. Our device and firmware might support something
> > like
> > 1024, but we are just one of many devices in the system and in the
> > hypervisor we want a way to limit this without having to change the
> > BIOS configuration.
> 
> Yeah makes sense. Is the firmware here GuC or UEFI?

This answer will be different depending on the platform... It's either
a preboot firmware in the UEFI space or something at runtime. GuC isn't
generally involved here though.

> 
> If our device supports only 1024 then it's safe to have it as limit.

That said... maybe what we really should be doing here is dropping the
macro I have and just use the configfs? Then with a default configfs,
we just use what the device presents but give a sysadmin the option of
changing that for the reasons I mentioned above? Of course we might
still need to change this depending on specific hardware generation
requirements (maybe even change the configfs default, etc). But that
would maybe be the best of both worlds in the meantime...

Thanks,
Stuart

> 
> Kind regards,
> 
> ~Maarten Lankhorst
> 

[PATCH 04/11] drm/xe: Assign dedicated MSI-X vectors to exec queues

[Stuart Summers]

Assign a dedicated MSI-X interrupt vector to each user exec queue at
creation time when the platform supports MSI-X. If allocation fails
for any other reason, the queue silently falls back to the shared
default MSI-X vector.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_device_types.h |  5 ++++
 drivers/gpu/drm/xe/xe_exec_queue.c   | 34 +++++++++++++++++++++++++++-
 drivers/gpu/drm/xe/xe_irq.c          | 27 ++++++++++++++++++++--
 drivers/gpu/drm/xe/xe_irq.h          |  2 ++
 4 files changed, 65 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 32dd2ffbc796..ff15de34fd17 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -255,6 +255,11 @@ struct xe_device {
 			u16 nvec;
 			/** @irq.msix.indexes: used to allocate MSI-X indexes */
 			struct xarray indexes;
+			/**
+			 * @irq.msix.vec_count: total number of MSI-X vectors
+			 * currently allocated (static + dynamic)
+			 */
+			atomic_t vec_count;
 		} msix;
 	} irq;
 
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 1b5ca3ce578a..6c101b4f6488 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -16,6 +16,7 @@
 #include "xe_bo.h"
 #include "xe_dep_scheduler.h"
 #include "xe_device.h"
+#include "xe_drv.h"
 #include "xe_gt.h"
 #include "xe_gt_sriov_pf.h"
 #include "xe_gt_sriov_vf.h"
@@ -138,6 +139,34 @@ static void xe_exec_queue_group_cleanup(struct xe_exec_queue *q)
 	kfree(group);
 }
 
+static void exec_queue_msix_init(struct xe_device *xe, struct xe_exec_queue *q)
+{
+	int err;
+	u16 msix;
+
+	if (!xe_device_has_msix(xe) || q->flags & EXEC_QUEUE_FLAG_KERNEL)
+		goto use_default;
+
+	err = xe_irq_msix_request_irq(xe, xe_irq_msix_hwe_handler, q,
+				      DRIVER_NAME "-exec-queue", true, &msix);
+	if (err)
+		goto use_default;
+
+	q->msix_vec = msix;
+	return;
+
+use_default:
+	q->msix_vec = XE_IRQ_DEFAULT_MSIX;
+}
+
+static void exec_queue_msix_fini(struct xe_exec_queue *q)
+{
+	struct xe_device *xe = gt_to_xe(q->gt);
+
+	if (q->msix_vec != XE_IRQ_DEFAULT_MSIX)
+		xe_irq_msix_free_irq(xe, q->msix_vec);
+}
+
 static void __xe_exec_queue_free(struct xe_exec_queue *q)
 {
 	int i;
@@ -152,6 +181,8 @@ static void __xe_exec_queue_free(struct xe_exec_queue *q)
 	if (xe_exec_queue_is_multi_queue(q))
 		xe_exec_queue_group_cleanup(q);
 
+	exec_queue_msix_fini(q);
+
 	if (q->vm) {
 		xe_vm_remove_exec_queue(q->vm, q);
 		xe_vm_put(q->vm);
@@ -220,7 +251,6 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
 	q->gt = gt;
 	q->class = hwe->class;
 	q->width = width;
-	q->msix_vec = XE_IRQ_DEFAULT_MSIX;
 	q->logical_mask = logical_mask;
 	q->fence_irq = &gt->fence_irq[hwe->class];
 	q->ring_ops = gt->ring_ops[hwe->class];
@@ -436,6 +466,8 @@ struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *v
 	if (IS_ERR(q))
 		return q;
 
+	exec_queue_msix_init(xe, q);
+
 	err = __xe_exec_queue_init(q, flags);
 	if (err)
 		goto err_post_alloc;
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 3429bb305293..c84d2283dd6a 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -13,6 +13,7 @@
 #include "regs/xe_irq_regs.h"
 #include "xe_device.h"
 #include "xe_drv.h"
+#include "xe_exec_queue.h"
 #include "xe_gsc_proxy.h"
 #include "xe_gt.h"
 #include "xe_guc.h"
@@ -930,6 +931,19 @@ static irqreturn_t xe_irq_msix_default_hwe_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
+irqreturn_t xe_irq_msix_hwe_handler(int irq, void *arg)
+{
+	struct xe_exec_queue *q = arg;
+	struct xe_tile *tile = gt_to_tile(q->hwe->gt);
+
+	if (!atomic_read(&tile->xe->irq.enabled))
+		return IRQ_NONE;
+
+	xe_memirq_hwe_handler(&tile->memirq, q->hwe);
+
+	return IRQ_HANDLED;
+}
+
 static int xe_irq_msix_alloc_vector(struct xe_device *xe, void *irq_buf,
 				    bool dynamic_msix, u16 *msix)
 {
@@ -976,18 +990,26 @@ int xe_irq_msix_request_irq(struct xe_device *xe, irq_handler_t handler, void *i
 {
 	int ret;
 
+	if (!atomic_add_unless(&xe->irq.msix.vec_count, 1,
+			       xe->irq.msix.nvec))
+		return -ENOSPC;
+
 	ret = xe_irq_msix_alloc_vector(xe, irq_buf, dynamic_msix, msix);
 	if (ret)
-		return ret;
+		goto err_dec;
 
 	ret = xe_irq_msix_request_irq_internal(xe, handler, irq_buf, name, *msix);
 	if (ret) {
 		drm_err(&xe->drm, "Failed to request IRQ for MSI-X %u\n", *msix);
 		xe_irq_msix_release_vector(xe, *msix);
-		return ret;
+		goto err_dec;
 	}
 
 	return 0;
+
+err_dec:
+	atomic_dec(&xe->irq.msix.vec_count);
+	return ret;
 }
 
 void xe_irq_msix_free_irq(struct xe_device *xe, u16 msix)
@@ -1008,6 +1030,7 @@ void xe_irq_msix_free_irq(struct xe_device *xe, u16 msix)
 
 	free_irq(irq, irq_buf);
 	xe_irq_msix_release_vector(xe, msix);
+	atomic_dec(&xe->irq.msix.vec_count);
 }
 
 int xe_irq_msix_request_irqs(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_irq.h b/drivers/gpu/drm/xe/xe_irq.h
index 5f48249dae8a..6c76004d6442 100644
--- a/drivers/gpu/drm/xe/xe_irq.h
+++ b/drivers/gpu/drm/xe/xe_irq.h
@@ -18,6 +18,7 @@
 #define XE_MSIX_MAX_VECS 1024
 
 struct xe_device;
+struct xe_exec_queue;
 struct xe_tile;
 struct xe_gt;
 
@@ -29,5 +30,6 @@ void xe_irq_enable_hwe(struct xe_gt *gt);
 int xe_irq_msix_request_irq(struct xe_device *xe, irq_handler_t handler, void *irq_buf,
 			    const char *name, bool dynamic_msix, u16 *msix);
 void xe_irq_msix_free_irq(struct xe_device *xe, u16 msix);
+irqreturn_t xe_irq_msix_hwe_handler(int irq, void *arg);
 
 #endif
-- 
2.43.0

[PATCH 05/11] drm/xe: Add configfs max_msix_vecs attribute

[Stuart Summers]

Add a configfs attribute to cap the total number of MSI-X vectors used
by the driver. This intends to cover all assigned vectors.

This let's us configure at runtime (prior to driver load) how many
vectors we want to be able to allocate during driver runtime without
changing anything in the PCIe capabilities. For VMWARE and other use
cases where system-wide vector count is strictly maintained rather
than per-device maximums, this helps provide this configurability
by a system administrator.

Example to cap the driver to 64 MSI-X vectors total:

  # echo 64 > /sys/kernel/config/xe/0000:03:00.0/max_msix_vecs

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_configfs.c | 71 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_configfs.h |  6 +++
 drivers/gpu/drm/xe/xe_irq.c      |  5 ++-
 3 files changed, 81 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c
index 32102600a148..5dc1f8196fe1 100644
--- a/drivers/gpu/drm/xe/xe_configfs.c
+++ b/drivers/gpu/drm/xe/xe_configfs.c
@@ -237,6 +237,23 @@
  *
  * This setting only takes effect when probing the device.
  *
+ * Max MSI-X exec queue vectors:
+ * ------------------------------
+ *
+ * Limit the total number of MSI-X vectors used by the driver. This cap is
+ * applied at device init time and covers all vectors: GuC-to-host, the
+ * shared default HWE vector, and any per-exec-queue dedicated vectors.
+ * Once the cap is reached, no additional dynamic vectors can be allocated
+ * and exec queues fall back to sharing the default vector. The value must
+ * be a non-zero positive integer; the default matches the compile-time
+ * limit (XE_MSIX_MAX_VECS).
+ *
+ * This attribute can only be set before binding to the device.
+ *
+ * Example to cap the driver to 64 MSI-X vectors total::
+ *
+ *	# echo 64 > /sys/kernel/config/xe/0000:03:00.0/max_msix_vecs
+ *
  * Remove devices
  * ==============
  *
@@ -262,6 +279,7 @@ struct xe_config_group_device {
 		struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX];
 		bool survivability_mode;
 		bool enable_psmi;
+		unsigned int max_msix_vecs;
 		struct {
 			unsigned int max_vfs;
 			bool admin_only_pf;
@@ -281,6 +299,7 @@ static const struct xe_config_device device_defaults = {
 	.engines_allowed = U64_MAX,
 	.survivability_mode = false,
 	.enable_psmi = false,
+	.max_msix_vecs = XE_MSIX_MAX_VECS,
 	.sriov = {
 		.max_vfs = XE_DEFAULT_MAX_VFS,
 		.admin_only_pf = XE_DEFAULT_ADMIN_ONLY_PF,
@@ -794,6 +813,35 @@ static ssize_t wa_bb_store(struct wa_bb wa_bb[static XE_ENGINE_CLASS_MAX],
 	return len;
 }
 
+static ssize_t max_msix_vecs_show(struct config_item *item, char *page)
+{
+	struct xe_config_device *dev = to_xe_config_device(item);
+
+	return sprintf(page, "%u\n", dev->max_msix_vecs);
+}
+
+static ssize_t max_msix_vecs_store(struct config_item *item, const char *page, size_t len)
+{
+	struct xe_config_group_device *dev = to_xe_config_group_device(item);
+	unsigned int max_msix_vecs;
+	int ret;
+
+	ret = kstrtouint(page, 0, &max_msix_vecs);
+	if (ret)
+		return ret;
+
+	if (!max_msix_vecs || max_msix_vecs > XE_MSIX_MAX_VECS)
+		return -EINVAL;
+
+	guard(mutex)(&dev->lock);
+	if (is_bound(dev))
+		return -EBUSY;
+
+	dev->config.max_msix_vecs = max_msix_vecs;
+
+	return len;
+}
+
 static ssize_t ctx_restore_mid_bb_store(struct config_item *item,
 					const char *data, size_t sz)
 {
@@ -816,6 +864,7 @@ CONFIGFS_ATTR(, enable_psmi);
 CONFIGFS_ATTR(, engines_allowed);
 CONFIGFS_ATTR(, gt_types_allowed);
 CONFIGFS_ATTR(, survivability_mode);
+CONFIGFS_ATTR(, max_msix_vecs);
 
 static struct configfs_attribute *xe_config_device_attrs[] = {
 	&attr_ctx_restore_mid_bb,
@@ -824,6 +873,7 @@ static struct configfs_attribute *xe_config_device_attrs[] = {
 	&attr_engines_allowed,
 	&attr_gt_types_allowed,
 	&attr_survivability_mode,
+	&attr_max_msix_vecs,
 	NULL,
 };
 
@@ -1099,6 +1149,7 @@ static void dump_custom_dev_config(struct pci_dev *pdev,
 	PRI_CUSTOM_ATTR("%llx", engines_allowed);
 	PRI_CUSTOM_ATTR("%d", enable_psmi);
 	PRI_CUSTOM_ATTR("%d", survivability_mode);
+	PRI_CUSTOM_ATTR("%u", max_msix_vecs);
 	PRI_CUSTOM_ATTR("%u", sriov.admin_only_pf);
 
 #undef PRI_CUSTOM_ATTR
@@ -1277,6 +1328,26 @@ u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev,
 	return len;
 }
 
+/**
+ * xe_configfs_get_max_msix_vecs - get configfs max_msix_vecs setting
+ * @pdev: pci device
+ *
+ * Return: maximum total number of MSI-X vectors the driver may use
+ */
+unsigned int xe_configfs_get_max_msix_vecs(struct pci_dev *pdev)
+{
+	struct xe_config_group_device *dev = find_xe_config_group_device(pdev);
+	unsigned int val;
+
+	if (!dev)
+		return device_defaults.max_msix_vecs;
+
+	val = dev->config.max_msix_vecs;
+	config_group_put(&dev->group);
+
+	return val;
+}
+
 #ifdef CONFIG_PCI_IOV
 /**
  * xe_configfs_admin_only_pf() - Get PF's operational mode.
diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h
index 07d62bf0c152..68115bff0fa0 100644
--- a/drivers/gpu/drm/xe/xe_configfs.h
+++ b/drivers/gpu/drm/xe/xe_configfs.h
@@ -10,6 +10,7 @@
 
 #include "xe_defaults.h"
 #include "xe_hw_engine_types.h"
+#include "xe_irq.h"
 #include "xe_module.h"
 
 struct pci_dev;
@@ -29,6 +30,7 @@ u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
 u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev,
 					enum xe_engine_class class,
 					const u32 **cs);
+unsigned int xe_configfs_get_max_msix_vecs(struct pci_dev *pdev);
 #ifdef CONFIG_PCI_IOV
 unsigned int xe_configfs_get_max_vfs(struct pci_dev *pdev);
 bool xe_configfs_admin_only_pf(struct pci_dev *pdev);
@@ -48,6 +50,10 @@ static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev,
 static inline u32 xe_configfs_get_ctx_restore_post_bb(struct pci_dev *pdev,
 						      enum xe_engine_class class,
 						      const u32 **cs) { return 0; }
+static inline unsigned int xe_configfs_get_max_msix_vecs(struct pci_dev *pdev)
+{
+	return XE_MSIX_MAX_VECS;
+}
 #ifdef CONFIG_PCI_IOV
 static inline unsigned int xe_configfs_get_max_vfs(struct pci_dev *pdev)
 {
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index c84d2283dd6a..40d3d43e492f 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -11,6 +11,7 @@
 
 #include "display/xe_display.h"
 #include "regs/xe_irq_regs.h"
+#include "xe_configfs.h"
 #include "xe_device.h"
 #include "xe_drv.h"
 #include "xe_exec_queue.h"
@@ -896,7 +897,9 @@ static int xe_irq_msix_init(struct xe_device *xe)
 		return nvec;
 	}
 
-	xe->irq.msix.nvec = min_t(int, nvec, XE_MSIX_MAX_VECS);
+	xe->irq.msix.nvec =
+		min_t(int, nvec, xe_configfs_get_max_msix_vecs(pdev));
+
 	xa_init_flags(&xe->irq.msix.indexes, XA_FLAGS_ALLOC);
 	return 0;
 }
-- 
2.43.0

[PATCH 06/11] drm/xe: Remove memirq status and source checks for engine interrupts

[Stuart Summers]

For engine-specific, memory-based interrupts, hardware will not fill in
the source and status offsets, assuming that software will utilize the
vector ID to determine the destination for a particular interrupt.

GuC and VF based interrupts are still handled the same - explicitly
checking these offsets.

Bspec: 62316
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_memirq.c | 36 ++++++++++------------------------
 1 file changed, 10 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 9dfe965cb46e..96ab2c59c5d7 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -447,21 +447,6 @@ static void memirq_assume_received(struct xe_memirq *memirq, const char *source,
 	memirq_debug(memirq, "ASSUME %s %s(%u)\n", source, status, offset);
 }
 
-static void memirq_dispatch_engine(struct xe_memirq *memirq, struct iosys_map *status,
-				   struct xe_hw_engine *hwe)
-{
-	memirq_debug(memirq, "STATUS %s %*ph\n", hwe->name, 16, status->vaddr);
-
-	/*
-	 * The programming note says to assume that GT_MI_USER_INTERRUPT is always
-	 * set. Check and clear related status byte just for a debug.
-	 */
-	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEMIRQ) &&
-	    !memirq_received(memirq, status, ilog2(GT_MI_USER_INTERRUPT), hwe->name))
-		memirq_assume_received(memirq, hwe->name, ilog2(GT_MI_USER_INTERRUPT), "USER");
-	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
-}
-
 static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *status,
 				struct xe_guc *guc)
 {
@@ -499,17 +484,16 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat
  */
 void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
 {
-	struct iosys_map source =
-		IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
-				      XE_MEMIRQ_SOURCE_OFFSET(hwe->irq_page));
-
-	if (memirq_received(memirq, &source, hwe->irq_offset, "SRC")) {
-		struct iosys_map status =
-			IOSYS_MAP_INIT_OFFSET(&memirq->bo->vmap,
-					      XE_MEMIRQ_VECTOR_OFFSET(hwe->irq_page,
-								      hwe->irq_offset));
-		memirq_dispatch_engine(memirq, &status, hwe);
-	}
+	memirq_debug(memirq, "dispatching engine %s\n", hwe->name);
+
+	/*
+	 * On MSI-X platforms hardware does not fill in the source and status
+	 * fields for engine-based interrupts (only GuC and VF interrupts have
+	 * a valid source/status). The dma-fence check for the fence completion
+	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
+	 * that check.
+	 */
+	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
 }
 
 /**
-- 
2.43.0

[PATCH 07/11] drm/xe: Add per-exec-queue user fence wait queue

[Stuart Summers]

Add a new ufence_wq wait queue to struct xe_exec_queue and initialize it
at queue allocation time. Also introduce xe_wait_user_fence_wake() to
centralize the ufence wake call sites.

This patch just adds the infrastructure in place to do this and doesn't
actually start using it. The reason being that we need to be careful
when handling a case where a user does a VM bind without a bind queue
and mistakenly passes a non-bind queue to the wait user fence. There
are a couple of IGT cases at least that are doing this today and to
avoid regressing any user code around this, we'll add some additional
handling in a subsequent patch before connecting this to the actual
wait user fence code.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_exec_queue.c       |  1 +
 drivers/gpu/drm/xe/xe_exec_queue_types.h |  3 +++
 drivers/gpu/drm/xe/xe_guc_submit.c       |  6 ++----
 drivers/gpu/drm/xe/xe_hw_engine.c        |  6 ++++--
 drivers/gpu/drm/xe/xe_hw_engine.h        |  3 ++-
 drivers/gpu/drm/xe/xe_irq.c              |  2 +-
 drivers/gpu/drm/xe/xe_memirq.c           |  2 +-
 drivers/gpu/drm/xe/xe_sync.c             |  3 ++-
 drivers/gpu/drm/xe/xe_wait_user_fence.c  | 16 +++++++++++++++-
 drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++++
 10 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 6c101b4f6488..aa49400b67ba 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -260,6 +260,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
 	INIT_LIST_HEAD(&q->multi_gt_link);
 	INIT_LIST_HEAD(&q->hw_engine_group_link);
 	INIT_LIST_HEAD(&q->pxp.link);
+	init_waitqueue_head(&q->ufence_wq);
 	spin_lock_init(&q->multi_queue.lock);
 	spin_lock_init(&q->lrc_lookup_lock);
 	q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index d27ce24daae5..fdc7baaa952e 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -231,6 +231,9 @@ struct xe_exec_queue {
 		struct list_head link;
 	} pxp;
 
+	/** @ufence_wq: per-queue user fence wait queue */
+	wait_queue_head_t ufence_wq;
+
 	/** @ufence_syncobj: User fence syncobj */
 	struct drm_syncobj *ufence_syncobj;
 
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index b29cc08e6291..16d609e7b40f 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -21,6 +21,7 @@
 #include "xe_device.h"
 #include "xe_exec_queue.h"
 #include "xe_force_wake.h"
+#include "xe_wait_user_fence.h"
 #include "xe_gpu_scheduler.h"
 #include "xe_gt.h"
 #include "xe_gt_clock.h"
@@ -555,11 +556,8 @@ static bool vf_recovery(struct xe_guc *guc)
 
 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
 {
-	struct xe_guc *guc = exec_queue_to_guc(q);
-	struct xe_device *xe = guc_to_xe(guc);
-
 	/** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
-	wake_up_all(&xe->ufence_wq);
+	xe_wait_user_fence_wake(gt_to_xe(q->gt), q);
 
 	xe_sched_tdr_queue_imm(&q->guc->sched);
 }
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 98265293f2dc..05780bd5beba 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -42,6 +42,7 @@
 #include "xe_tuning.h"
 #include "xe_uc_fw.h"
 #include "xe_wa.h"
+#include "xe_wait_user_fence.h"
 
 #define MAX_MMIO_BASES 3
 struct engine_info {
@@ -894,9 +895,10 @@ int xe_hw_engines_init(struct xe_gt *gt)
 	return 0;
 }
 
-void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)
+void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec,
+			     struct xe_exec_queue *q)
 {
-	wake_up_all(&gt_to_xe(hwe->gt)->ufence_wq);
+	xe_wait_user_fence_wake(gt_to_xe(hwe->gt), q);
 
 	if (hwe->irq_handler)
 		hwe->irq_handler(hwe, intr_vec);
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h
index c3ee37f8cfc0..7501c9051a71 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine.h
@@ -51,7 +51,8 @@ struct xe_exec_queue;
 
 int xe_hw_engines_init_early(struct xe_gt *gt);
 int xe_hw_engines_init(struct xe_gt *gt);
-void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec);
+void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec,
+			     struct xe_exec_queue *q);
 void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
 u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
 				enum xe_engine_class engine_class);
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 40d3d43e492f..fc99d021405f 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -385,7 +385,7 @@ static void gt_irq_handler(struct xe_tile *tile,
 
 			hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
 			if (hwe) {
-				xe_hw_engine_handle_irq(hwe, intr_vec);
+				xe_hw_engine_handle_irq(hwe, intr_vec, NULL);
 				continue;
 			}
 
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 96ab2c59c5d7..318ef7c72eba 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -493,7 +493,7 @@ void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
 	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
 	 * that check.
 	 */
-	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
+	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, NULL);
 }
 
 /**
diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c
index 37866768d64c..652341f22460 100644
--- a/drivers/gpu/drm/xe/xe_sync.c
+++ b/drivers/gpu/drm/xe/xe_sync.c
@@ -18,6 +18,7 @@
 #include "xe_exec_queue.h"
 #include "xe_macros.h"
 #include "xe_sched_job_types.h"
+#include "xe_wait_user_fence.h"
 
 struct xe_user_fence {
 	struct xe_device *xe;
@@ -92,7 +93,7 @@ static void user_fence_worker(struct work_struct *w)
 	 * Wake up waiters only after updating the ufence state, allowing the UMD
 	 * to safely reuse the same ufence without encountering -EBUSY errors.
 	 */
-	wake_up_all(&ufence->xe->ufence_wq);
+	xe_wait_user_fence_wake(ufence->xe, NULL);
 	user_fence_put(ufence);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c
index 12ceb3efa8ea..7c9d52b50580 100644
--- a/drivers/gpu/drm/xe/xe_wait_user_fence.c
+++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c
@@ -54,6 +54,20 @@ static int do_compare(u64 addr, u64 value, u64 mask, u16 op)
 #define VALID_FLAGS	DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
 #define MAX_OP		DRM_XE_UFENCE_WAIT_OP_LTE
 
+/**
+ * xe_wait_user_fence_wake() - Wake user fence waiters
+ * @xe: the xe device
+ * @q: exec queue (reserved; per-queue wake-up is enabled in a later patch)
+ *
+ * Wakes all user fence waiters on the device-level wait queue.
+ * Per-exec-queue and ufence_list broadcast support are introduced in
+ * subsequent patches once the full infrastructure is in place.
+ */
+void xe_wait_user_fence_wake(struct xe_device *xe, struct xe_exec_queue *q)
+{
+	wake_up_all(&xe->ufence_wq);
+}
+
 static long to_jiffies_timeout(struct xe_device *xe,
 			       struct drm_xe_wait_user_fence *args)
 {
@@ -110,7 +124,7 @@ static long to_jiffies_timeout(struct xe_device *xe,
  *
  * If an exec queue ID is provided, the wait is aborted early if the
  * queue enters a reset state. The device-level wait queue is used for
- * wakeups.
+ * wakeups in all cases.
  *
  * On return, @timeout is updated to reflect the remaining time (or zero
  * on expiry), unless %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME is set.
diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.h b/drivers/gpu/drm/xe/xe_wait_user_fence.h
index 0e268978f9e6..64e5000eabb4 100644
--- a/drivers/gpu/drm/xe/xe_wait_user_fence.h
+++ b/drivers/gpu/drm/xe/xe_wait_user_fence.h
@@ -8,6 +8,10 @@
 
 struct drm_device;
 struct drm_file;
+struct xe_device;
+struct xe_exec_queue;
+
+void xe_wait_user_fence_wake(struct xe_device *xe, struct xe_exec_queue *q);
 
 int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
 			     struct drm_file *file);
-- 
2.43.0

Re: [PATCH 07/11] drm/xe: Add per-exec-queue user fence wait queue

[Matthew Brost]

On Wed, Jun 10, 2026 at 09:28:39PM +0000, Stuart Summers wrote:
> Add a new ufence_wq wait queue to struct xe_exec_queue and initialize it
> at queue allocation time. Also introduce xe_wait_user_fence_wake() to
> centralize the ufence wake call sites.
> 
> This patch just adds the infrastructure in place to do this and doesn't
> actually start using it. The reason being that we need to be careful
> when handling a case where a user does a VM bind without a bind queue
> and mistakenly passes a non-bind queue to the wait user fence. There
> are a couple of IGT cases at least that are doing this today and to
> avoid regressing any user code around this, we'll add some additional
> handling in a subsequent patch before connecting this to the actual
> wait user fence code.
> 
> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> Assisted-by: Copilot:claude-sonnet-4.6
> ---
>  drivers/gpu/drm/xe/xe_exec_queue.c       |  1 +
>  drivers/gpu/drm/xe/xe_exec_queue_types.h |  3 +++
>  drivers/gpu/drm/xe/xe_guc_submit.c       |  6 ++----
>  drivers/gpu/drm/xe/xe_hw_engine.c        |  6 ++++--
>  drivers/gpu/drm/xe/xe_hw_engine.h        |  3 ++-
>  drivers/gpu/drm/xe/xe_irq.c              |  2 +-
>  drivers/gpu/drm/xe/xe_memirq.c           |  2 +-
>  drivers/gpu/drm/xe/xe_sync.c             |  3 ++-
>  drivers/gpu/drm/xe/xe_wait_user_fence.c  | 16 +++++++++++++++-
>  drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++++
>  10 files changed, 35 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
> index 6c101b4f6488..aa49400b67ba 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> @@ -260,6 +260,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
>  	INIT_LIST_HEAD(&q->multi_gt_link);
>  	INIT_LIST_HEAD(&q->hw_engine_group_link);
>  	INIT_LIST_HEAD(&q->pxp.link);
> +	init_waitqueue_head(&q->ufence_wq);

Would it be better to make this a pointer and malloc/initialize a
wait_queue if it has a unique MSIX vector; otherwise, point it to
xe->ufence_wq? Likewise, if a platform doesn’t support MSIX, could we
just point it to xe->ufence_wq?

This ties into a suggestion below.

>  	spin_lock_init(&q->multi_queue.lock);
>  	spin_lock_init(&q->lrc_lookup_lock);
>  	q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
> diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> index d27ce24daae5..fdc7baaa952e 100644
> --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
> +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> @@ -231,6 +231,9 @@ struct xe_exec_queue {
>  		struct list_head link;
>  	} pxp;
>  
> +	/** @ufence_wq: per-queue user fence wait queue */
> +	wait_queue_head_t ufence_wq;
> +
>  	/** @ufence_syncobj: User fence syncobj */
>  	struct drm_syncobj *ufence_syncobj;
>  
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index b29cc08e6291..16d609e7b40f 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -21,6 +21,7 @@
>  #include "xe_device.h"
>  #include "xe_exec_queue.h"
>  #include "xe_force_wake.h"
> +#include "xe_wait_user_fence.h"
>  #include "xe_gpu_scheduler.h"
>  #include "xe_gt.h"
>  #include "xe_gt_clock.h"
> @@ -555,11 +556,8 @@ static bool vf_recovery(struct xe_guc *guc)
>  
>  static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
>  {
> -	struct xe_guc *guc = exec_queue_to_guc(q);
> -	struct xe_device *xe = guc_to_xe(guc);
> -
>  	/** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
> -	wake_up_all(&xe->ufence_wq);
> +	xe_wait_user_fence_wake(gt_to_xe(q->gt), q);
>  
>  	xe_sched_tdr_queue_imm(&q->guc->sched);
>  }
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index 98265293f2dc..05780bd5beba 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -42,6 +42,7 @@
>  #include "xe_tuning.h"
>  #include "xe_uc_fw.h"
>  #include "xe_wa.h"
> +#include "xe_wait_user_fence.h"
>  
>  #define MAX_MMIO_BASES 3
>  struct engine_info {
> @@ -894,9 +895,10 @@ int xe_hw_engines_init(struct xe_gt *gt)
>  	return 0;
>  }
>  
> -void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec)
> +void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec,
> +			     struct xe_exec_queue *q)
>  {
> -	wake_up_all(&gt_to_xe(hwe->gt)->ufence_wq);
> +	xe_wait_user_fence_wake(gt_to_xe(hwe->gt), q);
>  
>  	if (hwe->irq_handler)
>  		hwe->irq_handler(hwe, intr_vec);
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h
> index c3ee37f8cfc0..7501c9051a71 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.h
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.h
> @@ -51,7 +51,8 @@ struct xe_exec_queue;
>  
>  int xe_hw_engines_init_early(struct xe_gt *gt);
>  int xe_hw_engines_init(struct xe_gt *gt);
> -void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec);
> +void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec,
> +			     struct xe_exec_queue *q);
>  void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
>  u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
>  				enum xe_engine_class engine_class);
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 40d3d43e492f..fc99d021405f 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -385,7 +385,7 @@ static void gt_irq_handler(struct xe_tile *tile,
>  
>  			hwe = xe_gt_hw_engine(engine_gt, class, instance, false);
>  			if (hwe) {
> -				xe_hw_engine_handle_irq(hwe, intr_vec);
> +				xe_hw_engine_handle_irq(hwe, intr_vec, NULL);
>  				continue;
>  			}
>  
> diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
> index 96ab2c59c5d7..318ef7c72eba 100644
> --- a/drivers/gpu/drm/xe/xe_memirq.c
> +++ b/drivers/gpu/drm/xe/xe_memirq.c
> @@ -493,7 +493,7 @@ void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
>  	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
>  	 * that check.
>  	 */
> -	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
> +	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, NULL);
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/xe/xe_sync.c b/drivers/gpu/drm/xe/xe_sync.c
> index 37866768d64c..652341f22460 100644
> --- a/drivers/gpu/drm/xe/xe_sync.c
> +++ b/drivers/gpu/drm/xe/xe_sync.c
> @@ -18,6 +18,7 @@
>  #include "xe_exec_queue.h"
>  #include "xe_macros.h"
>  #include "xe_sched_job_types.h"
> +#include "xe_wait_user_fence.h"
>  
>  struct xe_user_fence {
>  	struct xe_device *xe;
> @@ -92,7 +93,7 @@ static void user_fence_worker(struct work_struct *w)
>  	 * Wake up waiters only after updating the ufence state, allowing the UMD
>  	 * to safely reuse the same ufence without encountering -EBUSY errors.
>  	 */
> -	wake_up_all(&ufence->xe->ufence_wq);
> +	xe_wait_user_fence_wake(ufence->xe, NULL);

Is this the only call site where q is NULL? I’m certain we can obtain q
from the exec IOCTL and VM bind IOCTLs and pass into the sync layer.

OA also uses syncs and appears to have a q as well; however, I’m not
that familiar with that code, though I’m sure we can work out any
OA-related details.

Given this, starting with the first suggestion above, I would wire in q
from the exec IOCTL, VM bind IOCTLs, and OA IOCTLs. Next, I would
completely drop ufence_list, as it doesn’t appear to be needed.

Finally, I would rewrite xe_wait_user_fence_wake in patch #10 as
follows:

void xe_wait_user_fence_wake(struct xe_device *xe, struct xe_exec_queue *q)
{
	/* Wakeup non-attached queue waiters */
	wake_up_all(&xe->ufence_wq);

	/*
	 * XXX: Maybe even bail before xe_exec_queue_get_unless_zero if
	 * MSIX isn't supported.
	 */

	q = xe_exec_queue_get_unless_zero(q);
	if (q) {
		if (q->ufence_wq != &xe->ufence_wq)
			wake_up_all(&q->ufence_wq);
		xe_exec_queue_put(q);
	}
}

I’m fairly certain this will work and be a bit simpler.

Also, I believe patch #10 contains a bug: if xe_wait_user_fence_wake is
passed a valid q and a wait IOCTL omits q, then xe->ufence_wq isn’t
woken. I’m pretty sure my suggestion here resolves that as well.

What do you think?

Matt

>  	user_fence_put(ufence);
>  }
>  
> diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c
> index 12ceb3efa8ea..7c9d52b50580 100644
> --- a/drivers/gpu/drm/xe/xe_wait_user_fence.c
> +++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c
> @@ -54,6 +54,20 @@ static int do_compare(u64 addr, u64 value, u64 mask, u16 op)
>  #define VALID_FLAGS	DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
>  #define MAX_OP		DRM_XE_UFENCE_WAIT_OP_LTE
>  
> +/**
> + * xe_wait_user_fence_wake() - Wake user fence waiters
> + * @xe: the xe device
> + * @q: exec queue (reserved; per-queue wake-up is enabled in a later patch)
> + *
> + * Wakes all user fence waiters on the device-level wait queue.
> + * Per-exec-queue and ufence_list broadcast support are introduced in
> + * subsequent patches once the full infrastructure is in place.
> + */
> +void xe_wait_user_fence_wake(struct xe_device *xe, struct xe_exec_queue *q)
> +{
> +	wake_up_all(&xe->ufence_wq);
> +}
> +
>  static long to_jiffies_timeout(struct xe_device *xe,
>  			       struct drm_xe_wait_user_fence *args)
>  {
> @@ -110,7 +124,7 @@ static long to_jiffies_timeout(struct xe_device *xe,
>   *
>   * If an exec queue ID is provided, the wait is aborted early if the
>   * queue enters a reset state. The device-level wait queue is used for
> - * wakeups.
> + * wakeups in all cases.
>   *
>   * On return, @timeout is updated to reflect the remaining time (or zero
>   * on expiry), unless %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME is set.
> diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.h b/drivers/gpu/drm/xe/xe_wait_user_fence.h
> index 0e268978f9e6..64e5000eabb4 100644
> --- a/drivers/gpu/drm/xe/xe_wait_user_fence.h
> +++ b/drivers/gpu/drm/xe/xe_wait_user_fence.h
> @@ -8,6 +8,10 @@
>  
>  struct drm_device;
>  struct drm_file;
> +struct xe_device;
> +struct xe_exec_queue;
> +
> +void xe_wait_user_fence_wake(struct xe_device *xe, struct xe_exec_queue *q);
>  
>  int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
>  			     struct drm_file *file);
> -- 
> 2.43.0
> 

Re: [PATCH 07/11] drm/xe: Add per-exec-queue user fence wait queue

[Summers, Stuart]

On Wed, 2026-06-10 at 16:35 -0700, Matthew Brost wrote:
> On Wed, Jun 10, 2026 at 09:28:39PM +0000, Stuart Summers wrote:
> > Add a new ufence_wq wait queue to struct xe_exec_queue and
> > initialize it
> > at queue allocation time. Also introduce xe_wait_user_fence_wake()
> > to
> > centralize the ufence wake call sites.
> > 
> > This patch just adds the infrastructure in place to do this and
> > doesn't
> > actually start using it. The reason being that we need to be
> > careful
> > when handling a case where a user does a VM bind without a bind
> > queue
> > and mistakenly passes a non-bind queue to the wait user fence.
> > There
> > are a couple of IGT cases at least that are doing this today and to
> > avoid regressing any user code around this, we'll add some
> > additional
> > handling in a subsequent patch before connecting this to the actual
> > wait user fence code.
> > 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> > Assisted-by: Copilot:claude-sonnet-4.6
> > ---
> >  drivers/gpu/drm/xe/xe_exec_queue.c       |  1 +
> >  drivers/gpu/drm/xe/xe_exec_queue_types.h |  3 +++
> >  drivers/gpu/drm/xe/xe_guc_submit.c       |  6 ++----
> >  drivers/gpu/drm/xe/xe_hw_engine.c        |  6 ++++--
> >  drivers/gpu/drm/xe/xe_hw_engine.h        |  3 ++-
> >  drivers/gpu/drm/xe/xe_irq.c              |  2 +-
> >  drivers/gpu/drm/xe/xe_memirq.c           |  2 +-
> >  drivers/gpu/drm/xe/xe_sync.c             |  3 ++-
> >  drivers/gpu/drm/xe/xe_wait_user_fence.c  | 16 +++++++++++++++-
> >  drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++++
> >  10 files changed, 35 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c
> > b/drivers/gpu/drm/xe/xe_exec_queue.c
> > index 6c101b4f6488..aa49400b67ba 100644
> > --- a/drivers/gpu/drm/xe/xe_exec_queue.c
> > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c
> > @@ -260,6 +260,7 @@ static struct xe_exec_queue
> > *__xe_exec_queue_alloc(struct xe_device *xe,
> >         INIT_LIST_HEAD(&q->multi_gt_link);
> >         INIT_LIST_HEAD(&q->hw_engine_group_link);
> >         INIT_LIST_HEAD(&q->pxp.link);
> > +       init_waitqueue_head(&q->ufence_wq);
> 
> Would it be better to make this a pointer and malloc/initialize a
> wait_queue if it has a unique MSIX vector; otherwise, point it to
> xe->ufence_wq? Likewise, if a platform doesn’t support MSIX, could we
> just point it to xe->ufence_wq?
> 
> This ties into a suggestion below.
> 
> >         spin_lock_init(&q->multi_queue.lock);
> >         spin_lock_init(&q->lrc_lookup_lock);
> >         q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
> > diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h
> > b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> > index d27ce24daae5..fdc7baaa952e 100644
> > --- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
> > +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
> > @@ -231,6 +231,9 @@ struct xe_exec_queue {
> >                 struct list_head link;
> >         } pxp;
> >  
> > +       /** @ufence_wq: per-queue user fence wait queue */
> > +       wait_queue_head_t ufence_wq;
> > +
> >         /** @ufence_syncobj: User fence syncobj */
> >         struct drm_syncobj *ufence_syncobj;
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c
> > b/drivers/gpu/drm/xe/xe_guc_submit.c
> > index b29cc08e6291..16d609e7b40f 100644
> > --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> > @@ -21,6 +21,7 @@
> >  #include "xe_device.h"
> >  #include "xe_exec_queue.h"
> >  #include "xe_force_wake.h"
> > +#include "xe_wait_user_fence.h"
> >  #include "xe_gpu_scheduler.h"
> >  #include "xe_gt.h"
> >  #include "xe_gt_clock.h"
> > @@ -555,11 +556,8 @@ static bool vf_recovery(struct xe_guc *guc)
> >  
> >  static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue
> > *q)
> >  {
> > -       struct xe_guc *guc = exec_queue_to_guc(q);
> > -       struct xe_device *xe = guc_to_xe(guc);
> > -
> >         /** to wakeup xe_wait_user_fence ioctl if exec queue is
> > reset */
> > -       wake_up_all(&xe->ufence_wq);
> > +       xe_wait_user_fence_wake(gt_to_xe(q->gt), q);
> >  
> >         xe_sched_tdr_queue_imm(&q->guc->sched);
> >  }
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
> > b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index 98265293f2dc..05780bd5beba 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > @@ -42,6 +42,7 @@
> >  #include "xe_tuning.h"
> >  #include "xe_uc_fw.h"
> >  #include "xe_wa.h"
> > +#include "xe_wait_user_fence.h"
> >  
> >  #define MAX_MMIO_BASES 3
> >  struct engine_info {
> > @@ -894,9 +895,10 @@ int xe_hw_engines_init(struct xe_gt *gt)
> >         return 0;
> >  }
> >  
> > -void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16
> > intr_vec)
> > +void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16
> > intr_vec,
> > +                            struct xe_exec_queue *q)
> >  {
> > -       wake_up_all(&gt_to_xe(hwe->gt)->ufence_wq);
> > +       xe_wait_user_fence_wake(gt_to_xe(hwe->gt), q);
> >  
> >         if (hwe->irq_handler)
> >                 hwe->irq_handler(hwe, intr_vec);
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h
> > b/drivers/gpu/drm/xe/xe_hw_engine.h
> > index c3ee37f8cfc0..7501c9051a71 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.h
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.h
> > @@ -51,7 +51,8 @@ struct xe_exec_queue;
> >  
> >  int xe_hw_engines_init_early(struct xe_gt *gt);
> >  int xe_hw_engines_init(struct xe_gt *gt);
> > -void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16
> > intr_vec);
> > +void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16
> > intr_vec,
> > +                            struct xe_exec_queue *q);
> >  void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe);
> >  u32 xe_hw_engine_mask_per_class(struct xe_gt *gt,
> >                                 enum xe_engine_class engine_class);
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c
> > b/drivers/gpu/drm/xe/xe_irq.c
> > index 40d3d43e492f..fc99d021405f 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -385,7 +385,7 @@ static void gt_irq_handler(struct xe_tile
> > *tile,
> >  
> >                         hwe = xe_gt_hw_engine(engine_gt, class,
> > instance, false);
> >                         if (hwe) {
> > -                               xe_hw_engine_handle_irq(hwe,
> > intr_vec);
> > +                               xe_hw_engine_handle_irq(hwe,
> > intr_vec, NULL);
> >                                 continue;
> >                         }
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_memirq.c
> > b/drivers/gpu/drm/xe/xe_memirq.c
> > index 96ab2c59c5d7..318ef7c72eba 100644
> > --- a/drivers/gpu/drm/xe/xe_memirq.c
> > +++ b/drivers/gpu/drm/xe/xe_memirq.c
> > @@ -493,7 +493,7 @@ void xe_memirq_hwe_handler(struct xe_memirq
> > *memirq, struct xe_hw_engine *hwe)
> >          * is opportunistic, unconditionally pass MI_USER_INTERRUPT
> > to issue
> >          * that check.
> >          */
> > -       xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT);
> > +       xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, NULL);
> >  }
> >  
> >  /**
> > diff --git a/drivers/gpu/drm/xe/xe_sync.c
> > b/drivers/gpu/drm/xe/xe_sync.c
> > index 37866768d64c..652341f22460 100644
> > --- a/drivers/gpu/drm/xe/xe_sync.c
> > +++ b/drivers/gpu/drm/xe/xe_sync.c
> > @@ -18,6 +18,7 @@
> >  #include "xe_exec_queue.h"
> >  #include "xe_macros.h"
> >  #include "xe_sched_job_types.h"
> > +#include "xe_wait_user_fence.h"
> >  
> >  struct xe_user_fence {
> >         struct xe_device *xe;
> > @@ -92,7 +93,7 @@ static void user_fence_worker(struct work_struct
> > *w)
> >          * Wake up waiters only after updating the ufence state,
> > allowing the UMD
> >          * to safely reuse the same ufence without encountering -
> > EBUSY errors.
> >          */
> > -       wake_up_all(&ufence->xe->ufence_wq);
> > +       xe_wait_user_fence_wake(ufence->xe, NULL);
> 
> Is this the only call site where q is NULL? I’m certain we can obtain
> q
> from the exec IOCTL and VM bind IOCTLs and pass into the sync layer.
> 
> OA also uses syncs and appears to have a q as well; however, I’m not
> that familiar with that code, though I’m sure we can work out any
> OA-related details.
> 
> Given this, starting with the first suggestion above, I would wire in
> q
> from the exec IOCTL, VM bind IOCTLs, and OA IOCTLs. Next, I would
> completely drop ufence_list, as it doesn’t appear to be needed.
> 
> Finally, I would rewrite xe_wait_user_fence_wake in patch #10 as
> follows:
> 
> void xe_wait_user_fence_wake(struct xe_device *xe, struct
> xe_exec_queue *q)
> {
>         /* Wakeup non-attached queue waiters */
>         wake_up_all(&xe->ufence_wq);
> 
>         /*
>          * XXX: Maybe even bail before xe_exec_queue_get_unless_zero
> if
>          * MSIX isn't supported.
>          */
> 
>         q = xe_exec_queue_get_unless_zero(q);
>         if (q) {
>                 if (q->ufence_wq != &xe->ufence_wq)
>                         wake_up_all(&q->ufence_wq);
>                 xe_exec_queue_put(q);
>         }
> }
> 
> I’m fairly certain this will work and be a bit simpler.
> 
> Also, I believe patch #10 contains a bug: if xe_wait_user_fence_wake
> is
> passed a valid q and a wait IOCTL omits q, then xe->ufence_wq isn’t
> woken. I’m pretty sure my suggestion here resolves that as well.
> 
> What do you think?

Ok let me go through this before reposting, but generally I like this
idea better than what I have. Let me see what I can get in the next
update here.

Thanks for the feedback!
Stuart

> 
> Matt
> 
> >         user_fence_put(ufence);
> >  }
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c
> > b/drivers/gpu/drm/xe/xe_wait_user_fence.c
> > index 12ceb3efa8ea..7c9d52b50580 100644
> > --- a/drivers/gpu/drm/xe/xe_wait_user_fence.c
> > +++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c
> > @@ -54,6 +54,20 @@ static int do_compare(u64 addr, u64 value, u64
> > mask, u16 op)
> >  #define VALID_FLAGS    DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
> >  #define MAX_OP         DRM_XE_UFENCE_WAIT_OP_LTE
> >  
> > +/**
> > + * xe_wait_user_fence_wake() - Wake user fence waiters
> > + * @xe: the xe device
> > + * @q: exec queue (reserved; per-queue wake-up is enabled in a
> > later patch)
> > + *
> > + * Wakes all user fence waiters on the device-level wait queue.
> > + * Per-exec-queue and ufence_list broadcast support are introduced
> > in
> > + * subsequent patches once the full infrastructure is in place.
> > + */
> > +void xe_wait_user_fence_wake(struct xe_device *xe, struct
> > xe_exec_queue *q)
> > +{
> > +       wake_up_all(&xe->ufence_wq);
> > +}
> > +
> >  static long to_jiffies_timeout(struct xe_device *xe,
> >                                struct drm_xe_wait_user_fence *args)
> >  {
> > @@ -110,7 +124,7 @@ static long to_jiffies_timeout(struct xe_device
> > *xe,
> >   *
> >   * If an exec queue ID is provided, the wait is aborted early if
> > the
> >   * queue enters a reset state. The device-level wait queue is used
> > for
> > - * wakeups.
> > + * wakeups in all cases.
> >   *
> >   * On return, @timeout is updated to reflect the remaining time
> > (or zero
> >   * on expiry), unless %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME is set.
> > diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.h
> > b/drivers/gpu/drm/xe/xe_wait_user_fence.h
> > index 0e268978f9e6..64e5000eabb4 100644
> > --- a/drivers/gpu/drm/xe/xe_wait_user_fence.h
> > +++ b/drivers/gpu/drm/xe/xe_wait_user_fence.h
> > @@ -8,6 +8,10 @@
> >  
> >  struct drm_device;
> >  struct drm_file;
> > +struct xe_device;
> > +struct xe_exec_queue;
> > +
> > +void xe_wait_user_fence_wake(struct xe_device *xe, struct
> > xe_exec_queue *q);
> >  
> >  int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
> >                              struct drm_file *file);
> > -- 
> > 2.43.0
> > 

[PATCH 08/11] drm/xe: Track all exec queues in a device-level ufence list

[Stuart Summers]

Add ufence_link to struct xe_exec_queue and maintain a device-level
ufence_list (protected by ufence_list_lock) so the default MSI-X vector
handler can reach every queue's per-queue wait queue.

As mentioned in a prior patch that adds the per queue wait queue,
we can't guarantee userspace will pass something appropriate in
the wait user fence ioctl. And in fact I have found cases in IGT
where it does not - basically it issues a VM bind without a bind
exec queue and then adds a non-bind queue to the wait user fence
call. Of course I'd argue this is a test bug, but also we want
to avoid any large regressions from the UAPI perspective, so
this ufence list is used to walk through all potential per exec queue
wait queues users might have pending to make sure we wake all of
them up if we get an MSI-X interrupt in without a corresponding
exec queue.

Note that actually hooking up the wait user fence piece of this
is deferred to a later patch.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_device.c           |  2 ++
 drivers/gpu/drm/xe/xe_device_types.h     |  6 ++++++
 drivers/gpu/drm/xe/xe_exec_queue.c       | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_exec_queue_types.h |  3 +++
 4 files changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 51e3a2dd7b22..a0fabeabc9d7 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -549,6 +549,8 @@ int xe_device_init_early(struct xe_device *xe)
 	xe_validation_device_init(&xe->val);
 
 	init_waitqueue_head(&xe->ufence_wq);
+	spin_lock_init(&xe->ufence_list_lock);
+	INIT_LIST_HEAD(&xe->ufence_list);
 
 	init_rwsem(&xe->usm.lock);
 
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index ff15de34fd17..bf421d8cd0b1 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -351,6 +351,12 @@ struct xe_device {
 	/** @ufence_wq: user fence wait queue */
 	wait_queue_head_t ufence_wq;
 
+	/** @ufence_list_lock: protects @ufence_list */
+	spinlock_t ufence_list_lock;
+
+	/** @ufence_list: list of all exec queues for default-vector ufence wake */
+	struct list_head ufence_list;
+
 	/** @preempt_fence_wq: used to serialize preempt fences */
 	struct workqueue_struct *preempt_fence_wq;
 
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index aa49400b67ba..585eb1100a01 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -169,8 +169,16 @@ static void exec_queue_msix_fini(struct xe_exec_queue *q)
 
 static void __xe_exec_queue_free(struct xe_exec_queue *q)
 {
+	struct xe_device *xe = gt_to_xe(q->gt);
+	unsigned long irq_flags;
 	int i;
 
+	if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) {
+		spin_lock_irqsave(&xe->ufence_list_lock, irq_flags);
+		list_del_init(&q->ufence_link);
+		spin_unlock_irqrestore(&xe->ufence_list_lock, irq_flags);
+	}
+
 	for (i = 0; i < XE_EXEC_QUEUE_TLB_INVAL_COUNT; ++i)
 		if (q->tlb_inval[i].dep_scheduler)
 			xe_dep_scheduler_fini(q->tlb_inval[i].dep_scheduler);
@@ -236,6 +244,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
 {
 	struct xe_exec_queue *q;
 	struct xe_gt *gt = hwe->gt;
+	unsigned long irq_flags;
 	int err;
 
 	/* only kernel queues can be permanent */
@@ -260,7 +269,14 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
 	INIT_LIST_HEAD(&q->multi_gt_link);
 	INIT_LIST_HEAD(&q->hw_engine_group_link);
 	INIT_LIST_HEAD(&q->pxp.link);
+	INIT_LIST_HEAD(&q->ufence_link);
 	init_waitqueue_head(&q->ufence_wq);
+
+	if (!(flags & EXEC_QUEUE_FLAG_KERNEL)) {
+		spin_lock_irqsave(&xe->ufence_list_lock, irq_flags);
+		list_add(&q->ufence_link, &xe->ufence_list);
+		spin_unlock_irqrestore(&xe->ufence_list_lock, irq_flags);
+	}
 	spin_lock_init(&q->multi_queue.lock);
 	spin_lock_init(&q->lrc_lookup_lock);
 	q->multi_queue.priority = XE_MULTI_QUEUE_PRIORITY_NORMAL;
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index fdc7baaa952e..150237f173c2 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -234,6 +234,9 @@ struct xe_exec_queue {
 	/** @ufence_wq: per-queue user fence wait queue */
 	wait_queue_head_t ufence_wq;
 
+	/** @ufence_link: link into xe_device.ufence_list for default-vector wake */
+	struct list_head ufence_link;
+
 	/** @ufence_syncobj: User fence syncobj */
 	struct drm_syncobj *ufence_syncobj;
 
-- 
2.43.0

[PATCH 09/11] drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation

[Stuart Summers]

When a dedicated MSI-X vector fires for a specific exec queue, the
interrupt handler already has the queue pointer available.  Thread it
through the call chain so we can wake the per-queue ufence_wq without
impact any other user threads.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_irq.c    |  4 ++--
 drivers/gpu/drm/xe/xe_memirq.c | 13 +++++++++----
 drivers/gpu/drm/xe/xe_memirq.h |  4 +++-
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index fc99d021405f..b25cfcdc4b43 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -927,7 +927,7 @@ static irqreturn_t xe_irq_msix_default_hwe_handler(int irq, void *arg)
 				continue;
 
 			for_each_hw_engine(hwe, gt, id)
-				xe_memirq_hwe_handler(memirq, hwe);
+				xe_memirq_hwe_handler(memirq, hwe, NULL);
 		}
 	}
 
@@ -942,7 +942,7 @@ irqreturn_t xe_irq_msix_hwe_handler(int irq, void *arg)
 	if (!atomic_read(&tile->xe->irq.enabled))
 		return IRQ_NONE;
 
-	xe_memirq_hwe_handler(&tile->memirq, q->hwe);
+	xe_memirq_hwe_handler(&tile->memirq, q->hwe, q);
 
 	return IRQ_HANDLED;
 }
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index 318ef7c72eba..dc21f154db71 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -479,10 +479,15 @@ static void memirq_dispatch_guc(struct xe_memirq *memirq, struct iosys_map *stat
  * xe_memirq_hwe_handler - Check and process interrupts for a specific HW engine.
  * @memirq: the &xe_memirq
  * @hwe: the hw engine to process
+ * @q: the exec queue associated with this interrupt, or NULL
  *
- * This function reads and dispatches `Memory Based Interrupts` for the provided HW engine.
+ * This function reads and dispatches `Memory Based Interrupts` for the provided
+ * HW engine. When @q is non-NULL (e.g. called from a dedicated MSI-X vector
+ * handler), it is passed through so the per-queue user fence wait queue is
+ * woken rather than the device-level one.
  */
-void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
+void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe,
+			   struct xe_exec_queue *q)
 {
 	memirq_debug(memirq, "dispatching engine %s\n", hwe->name);
 
@@ -493,7 +498,7 @@ void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe)
 	 * is opportunistic, unconditionally pass MI_USER_INTERRUPT to issue
 	 * that check.
 	 */
-	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, NULL);
+	xe_hw_engine_handle_irq(hwe, GT_MI_USER_INTERRUPT, q);
 }
 
 /**
@@ -553,7 +558,7 @@ void xe_memirq_handler(struct xe_memirq *memirq)
 			continue;
 
 		for_each_hw_engine(hwe, gt, id)
-			xe_memirq_hwe_handler(memirq, hwe);
+			xe_memirq_hwe_handler(memirq, hwe, NULL);
 	}
 
 	/* GuC and media GuC (if present) must be checked separately */
diff --git a/drivers/gpu/drm/xe/xe_memirq.h b/drivers/gpu/drm/xe/xe_memirq.h
index e25d2234ab87..7e2229ad1d38 100644
--- a/drivers/gpu/drm/xe/xe_memirq.h
+++ b/drivers/gpu/drm/xe/xe_memirq.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct xe_exec_queue;
 struct xe_guc;
 struct xe_hw_engine;
 struct xe_memirq;
@@ -20,7 +21,8 @@ u32 xe_memirq_enable_ptr(struct xe_memirq *memirq);
 
 void xe_memirq_reset(struct xe_memirq *memirq);
 void xe_memirq_postinstall(struct xe_memirq *memirq);
-void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe);
+void xe_memirq_hwe_handler(struct xe_memirq *memirq, struct xe_hw_engine *hwe,
+			   struct xe_exec_queue *q);
 void xe_memirq_handler(struct xe_memirq *memirq);
 
 int xe_memirq_init_guc(struct xe_memirq *memirq, struct xe_guc *guc);
-- 
2.43.0

[PATCH 10/11] drm/xe: Enable per-queue ufence wake in ioctl and wake function

[Stuart Summers]

Hook up the per-exec-queue user fence wait queue infrastructure
introduced in the previous patches:

- xe_wait_user_fence_wake(): if a specific user exec queue is supplied
  (non-NULL, still alive), wake only that queue's ufence_wq.  If no
  queue is supplied (default MSI-X vector), broadcast to xe->ufence_wq
  and every queue in ufence_list so no waiter is missed.  Kernel queues
  always use the default MSI-X vector and pass NULL, so any non-NULL @q
  here is guaranteed to be a user queue.

- xe_wait_user_fence_ioctl(): add and remove the wait entry on the
  per-queue ufence_wq when a queue is provided, falling back to the
  device-level ufence_wq otherwise.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/xe_wait_user_fence.c | 44 +++++++++++++++++++------
 1 file changed, 34 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_wait_user_fence.c b/drivers/gpu/drm/xe/xe_wait_user_fence.c
index 7c9d52b50580..1c14d89dff43 100644
--- a/drivers/gpu/drm/xe/xe_wait_user_fence.c
+++ b/drivers/gpu/drm/xe/xe_wait_user_fence.c
@@ -57,15 +57,39 @@ static int do_compare(u64 addr, u64 value, u64 mask, u16 op)
 /**
  * xe_wait_user_fence_wake() - Wake user fence waiters
  * @xe: the xe device
- * @q: exec queue (reserved; per-queue wake-up is enabled in a later patch)
+ * @q: exec queue whose user fence wait queue to wake, or NULL
  *
- * Wakes all user fence waiters on the device-level wait queue.
- * Per-exec-queue and ufence_list broadcast support are introduced in
- * subsequent patches once the full infrastructure is in place.
+ * If @q is non-NULL and still alive (a reference can be taken), wakes
+ * only that queue's per-queue wait queue.  Kernel queues always use the
+ * default MSI-X vector, which passes NULL here, so any non-NULL @q is
+ * always a user queue.
+ *
+ * If @q is NULL (default MSI-X vector or sync path), wakes the device-level
+ * wait queue and every per-exec-queue wait queue in ufence_list to ensure
+ * no waiter is missed.
  */
 void xe_wait_user_fence_wake(struct xe_device *xe, struct xe_exec_queue *q)
 {
-	wake_up_all(&xe->ufence_wq);
+	/*
+	 * Take a reference on the queue to guard against it being freed
+	 * concurrently. xe_exec_queue_get_unless_zero() handles a NULL @q,
+	 * so callers that don't specify a queue fall through to the broadcast.
+	 */
+	q = xe_exec_queue_get_unless_zero(q);
+	if (q) {
+		wake_up_all(&q->ufence_wq);
+		xe_exec_queue_put(q);
+	} else {
+		struct xe_exec_queue *iter;
+		unsigned long flags;
+
+		wake_up_all(&xe->ufence_wq);
+
+		spin_lock_irqsave(&xe->ufence_list_lock, flags);
+		list_for_each_entry(iter, &xe->ufence_list, ufence_link)
+			wake_up_all(&iter->ufence_wq);
+		spin_unlock_irqrestore(&xe->ufence_list_lock, flags);
+	}
 }
 
 static long to_jiffies_timeout(struct xe_device *xe,
@@ -122,9 +146,9 @@ static long to_jiffies_timeout(struct xe_device *xe,
  * performed as (@addr & @mask) OP @value, where OP is one of the
  * %DRM_XE_UFENCE_WAIT_OP_* operators.
  *
- * If an exec queue ID is provided, the wait is aborted early if the
- * queue enters a reset state. The device-level wait queue is used for
- * wakeups in all cases.
+ * If an exec queue ID is provided, the wait is scoped to that queue's
+ * per-queue wait queue and the wait is aborted early if the queue enters
+ * a reset state. Otherwise the device-level wait queue is used.
  *
  * On return, @timeout is updated to reflect the remaining time (or zero
  * on expiry), unless %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME is set.
@@ -170,7 +194,7 @@ int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
 
 	start = ktime_get();
 
-	add_wait_queue(&xe->ufence_wq, &w_wait);
+	add_wait_queue(q ? &q->ufence_wq : &xe->ufence_wq, &w_wait);
 	for (;;) {
 		err = do_compare(addr, args->value, args->mask, args->op);
 		if (err <= 0)
@@ -203,7 +227,7 @@ int xe_wait_user_fence_ioctl(struct drm_device *dev, void *data,
 
 		timeout = wait_woken(&w_wait, TASK_INTERRUPTIBLE, timeout);
 	}
-	remove_wait_queue(&xe->ufence_wq, &w_wait);
+	remove_wait_queue(q ? &q->ufence_wq : &xe->ufence_wq, &w_wait);
 
 	if (!(args->flags & DRM_XE_UFENCE_WAIT_FLAG_ABSTIME)) {
 		args->timeout -= ktime_to_ns(ktime_sub(ktime_get(), start));
-- 
2.43.0

[PATCH 11/11] drm/xe/memirq: Enable compute walker post-sync interrupt

[Stuart Summers]

Commit 2ddedd4b7b7c ("drm/xe/memirq: Enable GT_MI_USER_INTERRUPT only")
narrowed the MEMIRQ enable mask to GT_MI_USER_INTERRUPT only. Add
the interrupt enable bit for the compute walker post sync interrupt
as well to allow those to go through.

Additionally, the compute walker post sync interrupt vector offset
in the LRC register is currently incorrect. Fix that here.

Bspec: 62346, 72547
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/regs/xe_lrc_layout.h |  3 +++
 drivers/gpu/drm/xe/xe_lrc.c             | 15 ++++++++++++++-
 drivers/gpu/drm/xe/xe_memirq.c          | 12 +++++++++---
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
index 4ab86fc369fd..3c0babaa7902 100644
--- a/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
+++ b/drivers/gpu/drm/xe/regs/xe_lrc_layout.h
@@ -31,6 +31,9 @@
 #define CTX_INT_SRC_REPORT_REG		(CTX_LRI_INT_REPORT_PTR + 3)
 #define CTX_INT_SRC_REPORT_PTR		(CTX_LRI_INT_REPORT_PTR + 4)
 
+#define CTX_CS_INT_VEC_USER_MASK	REG_GENMASK(9, 0)
+#define CTX_CS_INT_VEC_COMPUTE_MASK	REG_GENMASK(19, 10)
+
 #define CTX_CS_INT_VEC_REG		0x5a
 #define CTX_CS_INT_VEC_DATA		(CTX_CS_INT_VEC_REG + 1)
 
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index a4292a11391d..d6677980be2d 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1527,11 +1527,24 @@ static int xe_lrc_ctx_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, struct
 		xe_lrc_set_ppgtt(lrc, vm);
 
 	if (xe_device_has_msix(xe)) {
+		/*
+		 * Each exec queue is only assigned one MSI-X vector, however
+		 * the LRC allows for different vectors for MI_USER_INT and
+		 * compute walker post sync interrupts. For now, just use the
+		 * same vector for each of the vector types.
+		 */
+		u32 lrc_msix_vec =
+			REG_FIELD_PREP(CTX_CS_INT_VEC_USER_MASK, msix_vec);
+
+		if (GRAPHICS_VERx100(xe) >= 3511)
+			lrc_msix_vec |=
+				REG_FIELD_PREP(CTX_CS_INT_VEC_COMPUTE_MASK, msix_vec);
+
 		xe_lrc_write_ctx_reg(lrc, CTX_INT_STATUS_REPORT_PTR,
 				     xe_memirq_status_ptr(&tile->memirq, hwe));
 		xe_lrc_write_ctx_reg(lrc, CTX_INT_SRC_REPORT_PTR,
 				     xe_memirq_source_ptr(&tile->memirq, hwe));
-		xe_lrc_write_ctx_reg(lrc, CTX_CS_INT_VEC_DATA, msix_vec << 16 | msix_vec);
+		xe_lrc_write_ctx_reg(lrc, CTX_CS_INT_VEC_DATA, lrc_msix_vec);
 	}
 
 	if (xe_gt_has_indirect_ring_state(gt)) {
diff --git a/drivers/gpu/drm/xe/xe_memirq.c b/drivers/gpu/drm/xe/xe_memirq.c
index dc21f154db71..d89f063a6c1f 100644
--- a/drivers/gpu/drm/xe/xe_memirq.c
+++ b/drivers/gpu/drm/xe/xe_memirq.c
@@ -238,12 +238,18 @@ static int memirq_alloc_pages(struct xe_memirq *memirq)
 
 static void memirq_set_enable(struct xe_memirq *memirq, bool enable)
 {
+	struct xe_device *xe = memirq_to_xe(memirq);
+	u32 int_enables = GT_MI_USER_INTERRUPT;
+
+	if (GRAPHICS_VERx100(xe) >= 3511)
+		int_enables |= GT_COMPUTE_WALKER_INTERRUPT;
+
 	/*
-	 * We only care about the GT_MI_USER_INTERRUPT from the engines and
-	 * the GuC does not look at the ENABLE mask at all.
+	 * Enable MI_USER_INTERRUPT and compute walker post-sync interrupts
+	 * from engines. The GuC does not look at the ENABLE mask at all.
 	 */
 	iosys_map_wr(&memirq->bo->vmap, XE_MEMIRQ_ENABLE_OFFSET, u32,
-		     enable ? GT_MI_USER_INTERRUPT : 0);
+		     enable ? int_enables : 0);
 
 	memirq->enabled = enable;
 }
-- 
2.43.0

✗ CI.checkpatch: warning for Enable per exec queue MSI-X vector assignment (rev2)

[Patchwork]

== Series Details ==

Series: Enable per exec queue MSI-X vector assignment (rev2)
URL   : https://patchwork.freedesktop.org/series/167990/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
061140b9bc586ae7f40abc1249c97e1cc72d1b9d
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 33fc1d8767829aaf250b4ffe4a772c18ce2701bc
Author: Stuart Summers <stuart.summers@intel.com>
Date:   Wed Jun 10 21:28:43 2026 +0000

    drm/xe/memirq: Enable compute walker post-sync interrupt
    
    Commit 2ddedd4b7b7c ("drm/xe/memirq: Enable GT_MI_USER_INTERRUPT only")
    narrowed the MEMIRQ enable mask to GT_MI_USER_INTERRUPT only. Add
    the interrupt enable bit for the compute walker post sync interrupt
    as well to allow those to go through.
    
    Additionally, the compute walker post sync interrupt vector offset
    in the LRC register is currently incorrect. Fix that here.
    
    Bspec: 62346, 72547
    Signed-off-by: Stuart Summers <stuart.summers@intel.com>
    Assisted-by: Copilot:claude-sonnet-4.6
+ /mt/dim checkpatch 10db0c83b0ccc3211990b54235475abb9d383851 drm-intel
b5ebdbe67b87 drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl()
742902c42f72 drm/xe: Handle NULL in xe_exec_queue_get_unless_zero()
f9b602aae9a1 drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS
54695ce6ded9 drm/xe: Assign dedicated MSI-X vectors to exec queues
0de3e94c9efb drm/xe: Add configfs max_msix_vecs attribute
abd7ff83ba08 drm/xe: Remove memirq status and source checks for engine interrupts
79f3b5447163 drm/xe: Add per-exec-queue user fence wait queue
ccd760eeb155 drm/xe: Track all exec queues in a device-level ufence list
508bf23f0e63 drm/xe: Hook up per queue thread wake to the unique MSI-X vector allocation
d7769620f6e7 drm/xe: Enable per-queue ufence wake in ioctl and wake function
-:53: WARNING:PREFER_FALLTHROUGH: Prefer 'fallthrough;' over fallthrough comment
#53: FILE: drivers/gpu/drm/xe/xe_wait_user_fence.c:76:
+	 * so callers that don't specify a queue fall through to the broadcast.

total: 0 errors, 1 warnings, 0 checks, 72 lines checked
33fc1d876782 drm/xe/memirq: Enable compute walker post-sync interrupt

✓ CI.KUnit: success for Enable per exec queue MSI-X vector assignment (rev2)

[Patchwork]

== Series Details ==

Series: Enable per exec queue MSI-X vector assignment (rev2)
URL   : https://patchwork.freedesktop.org/series/167990/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:06:21] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:06:25] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:06:57] Starting KUnit Kernel (1/1)...
[22:06:57] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:06:57] ================== guc_buf (11 subtests) ===================
[22:06:57] [PASSED] test_smallest
[22:06:57] [PASSED] test_largest
[22:06:57] [PASSED] test_granular
[22:06:57] [PASSED] test_unique
[22:06:57] [PASSED] test_overlap
[22:06:57] [PASSED] test_reusable
[22:06:57] [PASSED] test_too_big
[22:06:57] [PASSED] test_flush
[22:06:57] [PASSED] test_lookup
[22:06:57] [PASSED] test_data
[22:06:57] [PASSED] test_class
[22:06:57] ===================== [PASSED] guc_buf =====================
[22:06:57] =================== guc_dbm (7 subtests) ===================
[22:06:57] [PASSED] test_empty
[22:06:57] [PASSED] test_default
[22:06:57] ======================== test_size  ========================
[22:06:57] [PASSED] 4
[22:06:57] [PASSED] 8
[22:06:57] [PASSED] 32
[22:06:57] [PASSED] 256
[22:06:57] ==================== [PASSED] test_size ====================
[22:06:57] ======================= test_reuse  ========================
[22:06:57] [PASSED] 4
[22:06:57] [PASSED] 8
[22:06:57] [PASSED] 32
[22:06:57] [PASSED] 256
[22:06:57] =================== [PASSED] test_reuse ====================
[22:06:57] =================== test_range_overlap  ====================
[22:06:57] [PASSED] 4
[22:06:57] [PASSED] 8
[22:06:57] [PASSED] 32
[22:06:57] [PASSED] 256
[22:06:57] =============== [PASSED] test_range_overlap ================
[22:06:57] =================== test_range_compact  ====================
[22:06:57] [PASSED] 4
[22:06:57] [PASSED] 8
[22:06:57] [PASSED] 32
[22:06:57] [PASSED] 256
[22:06:57] =============== [PASSED] test_range_compact ================
[22:06:57] ==================== test_range_spare  =====================
[22:06:57] [PASSED] 4
[22:06:57] [PASSED] 8
[22:06:57] [PASSED] 32
[22:06:57] [PASSED] 256
[22:06:57] ================ [PASSED] test_range_spare =================
[22:06:57] ===================== [PASSED] guc_dbm =====================
[22:06:57] =================== guc_idm (6 subtests) ===================
[22:06:57] [PASSED] bad_init
[22:06:57] [PASSED] no_init
[22:06:57] [PASSED] init_fini
[22:06:57] [PASSED] check_used
[22:06:57] [PASSED] check_quota
[22:06:57] [PASSED] check_all
[22:06:57] ===================== [PASSED] guc_idm =====================
[22:06:57] ================== no_relay (3 subtests) ===================
[22:06:57] [PASSED] xe_drops_guc2pf_if_not_ready
[22:06:57] [PASSED] xe_drops_guc2vf_if_not_ready
[22:06:57] [PASSED] xe_rejects_send_if_not_ready
[22:06:57] ==================== [PASSED] no_relay =====================
[22:06:57] ================== pf_relay (14 subtests) ==================
[22:06:57] [PASSED] pf_rejects_guc2pf_too_short
[22:06:57] [PASSED] pf_rejects_guc2pf_too_long
[22:06:57] [PASSED] pf_rejects_guc2pf_no_payload
[22:06:57] [PASSED] pf_fails_no_payload
[22:06:57] [PASSED] pf_fails_bad_origin
[22:06:57] [PASSED] pf_fails_bad_type
[22:06:57] [PASSED] pf_txn_reports_error
[22:06:57] [PASSED] pf_txn_sends_pf2guc
[22:06:57] [PASSED] pf_sends_pf2guc
[22:06:57] [SKIPPED] pf_loopback_nop
[22:06:57] [SKIPPED] pf_loopback_echo
[22:06:57] [SKIPPED] pf_loopback_fail
[22:06:57] [SKIPPED] pf_loopback_busy
[22:06:57] [SKIPPED] pf_loopback_retry
[22:06:57] ==================== [PASSED] pf_relay =====================
[22:06:57] ================== vf_relay (3 subtests) ===================
[22:06:57] [PASSED] vf_rejects_guc2vf_too_short
[22:06:57] [PASSED] vf_rejects_guc2vf_too_long
[22:06:57] [PASSED] vf_rejects_guc2vf_no_payload
[22:06:57] ==================== [PASSED] vf_relay =====================
[22:06:57] ================ pf_gt_config (9 subtests) =================
[22:06:57] [PASSED] fair_contexts_1vf
[22:06:57] [PASSED] fair_doorbells_1vf
[22:06:57] [PASSED] fair_ggtt_1vf
[22:06:57] ====================== fair_vram_1vf  ======================
[22:06:57] [PASSED] 3.50 GiB
[22:06:57] [PASSED] 11.5 GiB
[22:06:57] [PASSED] 15.5 GiB
[22:06:57] [PASSED] 31.5 GiB
[22:06:57] [PASSED] 63.5 GiB
[22:06:57] [PASSED] 1.91 GiB
[22:06:57] ================== [PASSED] fair_vram_1vf ==================
[22:06:57] ================ fair_vram_1vf_admin_only  =================
[22:06:57] [PASSED] 3.50 GiB
[22:06:57] [PASSED] 11.5 GiB
[22:06:57] [PASSED] 15.5 GiB
[22:06:57] [PASSED] 31.5 GiB
[22:06:57] [PASSED] 63.5 GiB
[22:06:57] [PASSED] 1.91 GiB
[22:06:57] ============ [PASSED] fair_vram_1vf_admin_only =============
[22:06:57] ====================== fair_contexts  ======================
[22:06:57] [PASSED] 1 VF
[22:06:57] [PASSED] 2 VFs
[22:06:57] [PASSED] 3 VFs
[22:06:57] [PASSED] 4 VFs
[22:06:57] [PASSED] 5 VFs
[22:06:57] [PASSED] 6 VFs
[22:06:57] [PASSED] 7 VFs
[22:06:57] [PASSED] 8 VFs
[22:06:57] [PASSED] 9 VFs
[22:06:57] [PASSED] 10 VFs
[22:06:57] [PASSED] 11 VFs
[22:06:57] [PASSED] 12 VFs
[22:06:57] [PASSED] 13 VFs
[22:06:57] [PASSED] 14 VFs
[22:06:57] [PASSED] 15 VFs
[22:06:57] [PASSED] 16 VFs
[22:06:57] [PASSED] 17 VFs
[22:06:57] [PASSED] 18 VFs
[22:06:57] [PASSED] 19 VFs
[22:06:57] [PASSED] 20 VFs
[22:06:57] [PASSED] 21 VFs
[22:06:57] [PASSED] 22 VFs
[22:06:57] [PASSED] 23 VFs
[22:06:57] [PASSED] 24 VFs
[22:06:57] [PASSED] 25 VFs
[22:06:57] [PASSED] 26 VFs
[22:06:57] [PASSED] 27 VFs
[22:06:57] [PASSED] 28 VFs
[22:06:57] [PASSED] 29 VFs
[22:06:57] [PASSED] 30 VFs
[22:06:57] [PASSED] 31 VFs
[22:06:57] [PASSED] 32 VFs
[22:06:57] [PASSED] 33 VFs
[22:06:57] [PASSED] 34 VFs
[22:06:57] [PASSED] 35 VFs
[22:06:57] [PASSED] 36 VFs
[22:06:57] [PASSED] 37 VFs
[22:06:57] [PASSED] 38 VFs
[22:06:57] [PASSED] 39 VFs
[22:06:57] [PASSED] 40 VFs
[22:06:57] [PASSED] 41 VFs
[22:06:57] [PASSED] 42 VFs
[22:06:57] [PASSED] 43 VFs
[22:06:57] [PASSED] 44 VFs
[22:06:57] [PASSED] 45 VFs
[22:06:57] [PASSED] 46 VFs
[22:06:57] [PASSED] 47 VFs
[22:06:57] [PASSED] 48 VFs
[22:06:57] [PASSED] 49 VFs
[22:06:57] [PASSED] 50 VFs
[22:06:57] [PASSED] 51 VFs
[22:06:57] [PASSED] 52 VFs
[22:06:57] [PASSED] 53 VFs
[22:06:57] [PASSED] 54 VFs
[22:06:57] [PASSED] 55 VFs
[22:06:57] [PASSED] 56 VFs
[22:06:57] [PASSED] 57 VFs
[22:06:57] [PASSED] 58 VFs
[22:06:57] [PASSED] 59 VFs
[22:06:57] [PASSED] 60 VFs
[22:06:57] [PASSED] 61 VFs
[22:06:57] [PASSED] 62 VFs
[22:06:57] [PASSED] 63 VFs
[22:06:57] ================== [PASSED] fair_contexts ==================
[22:06:57] ===================== fair_doorbells  ======================
[22:06:57] [PASSED] 1 VF
[22:06:57] [PASSED] 2 VFs
[22:06:57] [PASSED] 3 VFs
[22:06:57] [PASSED] 4 VFs
[22:06:57] [PASSED] 5 VFs
[22:06:57] [PASSED] 6 VFs
[22:06:57] [PASSED] 7 VFs
[22:06:57] [PASSED] 8 VFs
[22:06:57] [PASSED] 9 VFs
[22:06:57] [PASSED] 10 VFs
[22:06:57] [PASSED] 11 VFs
[22:06:57] [PASSED] 12 VFs
[22:06:57] [PASSED] 13 VFs
[22:06:57] [PASSED] 14 VFs
[22:06:57] [PASSED] 15 VFs
[22:06:57] [PASSED] 16 VFs
[22:06:57] [PASSED] 17 VFs
[22:06:57] [PASSED] 18 VFs
[22:06:57] [PASSED] 19 VFs
[22:06:57] [PASSED] 20 VFs
[22:06:57] [PASSED] 21 VFs
[22:06:57] [PASSED] 22 VFs
[22:06:57] [PASSED] 23 VFs
[22:06:57] [PASSED] 24 VFs
[22:06:57] [PASSED] 25 VFs
[22:06:57] [PASSED] 26 VFs
[22:06:57] [PASSED] 27 VFs
[22:06:57] [PASSED] 28 VFs
[22:06:57] [PASSED] 29 VFs
[22:06:57] [PASSED] 30 VFs
[22:06:57] [PASSED] 31 VFs
[22:06:57] [PASSED] 32 VFs
[22:06:57] [PASSED] 33 VFs
[22:06:57] [PASSED] 34 VFs
[22:06:57] [PASSED] 35 VFs
[22:06:57] [PASSED] 36 VFs
[22:06:57] [PASSED] 37 VFs
[22:06:57] [PASSED] 38 VFs
[22:06:57] [PASSED] 39 VFs
[22:06:57] [PASSED] 40 VFs
[22:06:57] [PASSED] 41 VFs
[22:06:57] [PASSED] 42 VFs
[22:06:57] [PASSED] 43 VFs
[22:06:57] [PASSED] 44 VFs
[22:06:57] [PASSED] 45 VFs
[22:06:57] [PASSED] 46 VFs
[22:06:57] [PASSED] 47 VFs
[22:06:57] [PASSED] 48 VFs
[22:06:57] [PASSED] 49 VFs
[22:06:57] [PASSED] 50 VFs
[22:06:57] [PASSED] 51 VFs
[22:06:57] [PASSED] 52 VFs
[22:06:57] [PASSED] 53 VFs
[22:06:57] [PASSED] 54 VFs
[22:06:57] [PASSED] 55 VFs
[22:06:57] [PASSED] 56 VFs
[22:06:57] [PASSED] 57 VFs
[22:06:57] [PASSED] 58 VFs
[22:06:57] [PASSED] 59 VFs
[22:06:57] [PASSED] 60 VFs
[22:06:57] [PASSED] 61 VFs
[22:06:57] [PASSED] 62 VFs
[22:06:57] [PASSED] 63 VFs
[22:06:57] ================= [PASSED] fair_doorbells ==================
[22:06:57] ======================== fair_ggtt  ========================
[22:06:57] [PASSED] 1 VF
[22:06:57] [PASSED] 2 VFs
[22:06:57] [PASSED] 3 VFs
[22:06:57] [PASSED] 4 VFs
[22:06:57] [PASSED] 5 VFs
[22:06:57] [PASSED] 6 VFs
[22:06:57] [PASSED] 7 VFs
[22:06:57] [PASSED] 8 VFs
[22:06:57] [PASSED] 9 VFs
[22:06:57] [PASSED] 10 VFs
[22:06:57] [PASSED] 11 VFs
[22:06:57] [PASSED] 12 VFs
[22:06:57] [PASSED] 13 VFs
[22:06:57] [PASSED] 14 VFs
[22:06:57] [PASSED] 15 VFs
[22:06:57] [PASSED] 16 VFs
[22:06:57] [PASSED] 17 VFs
[22:06:57] [PASSED] 18 VFs
[22:06:57] [PASSED] 19 VFs
[22:06:57] [PASSED] 20 VFs
[22:06:57] [PASSED] 21 VFs
[22:06:57] [PASSED] 22 VFs
[22:06:57] [PASSED] 23 VFs
[22:06:57] [PASSED] 24 VFs
[22:06:57] [PASSED] 25 VFs
[22:06:57] [PASSED] 26 VFs
[22:06:57] [PASSED] 27 VFs
[22:06:57] [PASSED] 28 VFs
[22:06:57] [PASSED] 29 VFs
[22:06:57] [PASSED] 30 VFs
[22:06:57] [PASSED] 31 VFs
[22:06:57] [PASSED] 32 VFs
[22:06:57] [PASSED] 33 VFs
[22:06:57] [PASSED] 34 VFs
[22:06:57] [PASSED] 35 VFs
[22:06:57] [PASSED] 36 VFs
[22:06:57] [PASSED] 37 VFs
[22:06:57] [PASSED] 38 VFs
[22:06:57] [PASSED] 39 VFs
[22:06:57] [PASSED] 40 VFs
[22:06:57] [PASSED] 41 VFs
[22:06:57] [PASSED] 42 VFs
[22:06:57] [PASSED] 43 VFs
[22:06:57] [PASSED] 44 VFs
[22:06:57] [PASSED] 45 VFs
[22:06:57] [PASSED] 46 VFs
[22:06:57] [PASSED] 47 VFs
[22:06:57] [PASSED] 48 VFs
[22:06:57] [PASSED] 49 VFs
[22:06:57] [PASSED] 50 VFs
[22:06:57] [PASSED] 51 VFs
[22:06:57] [PASSED] 52 VFs
[22:06:57] [PASSED] 53 VFs
[22:06:57] [PASSED] 54 VFs
[22:06:57] [PASSED] 55 VFs
[22:06:57] [PASSED] 56 VFs
[22:06:57] [PASSED] 57 VFs
[22:06:57] [PASSED] 58 VFs
[22:06:57] [PASSED] 59 VFs
[22:06:57] [PASSED] 60 VFs
[22:06:57] [PASSED] 61 VFs
[22:06:57] [PASSED] 62 VFs
[22:06:57] [PASSED] 63 VFs
[22:06:57] ==================== [PASSED] fair_ggtt ====================
[22:06:57] ======================== fair_vram  ========================
[22:06:57] [PASSED] 1 VF
[22:06:57] [PASSED] 2 VFs
[22:06:57] [PASSED] 3 VFs
[22:06:57] [PASSED] 4 VFs
[22:06:57] [PASSED] 5 VFs
[22:06:57] [PASSED] 6 VFs
[22:06:57] [PASSED] 7 VFs
[22:06:57] [PASSED] 8 VFs
[22:06:57] [PASSED] 9 VFs
[22:06:57] [PASSED] 10 VFs
[22:06:57] [PASSED] 11 VFs
[22:06:57] [PASSED] 12 VFs
[22:06:57] [PASSED] 13 VFs
[22:06:57] [PASSED] 14 VFs
[22:06:57] [PASSED] 15 VFs
[22:06:57] [PASSED] 16 VFs
[22:06:57] [PASSED] 17 VFs
[22:06:57] [PASSED] 18 VFs
[22:06:57] [PASSED] 19 VFs
[22:06:57] [PASSED] 20 VFs
[22:06:57] [PASSED] 21 VFs
[22:06:57] [PASSED] 22 VFs
[22:06:57] [PASSED] 23 VFs
[22:06:57] [PASSED] 24 VFs
[22:06:57] [PASSED] 25 VFs
[22:06:57] [PASSED] 26 VFs
[22:06:57] [PASSED] 27 VFs
[22:06:57] [PASSED] 28 VFs
[22:06:57] [PASSED] 29 VFs
[22:06:57] [PASSED] 30 VFs
[22:06:57] [PASSED] 31 VFs
[22:06:57] [PASSED] 32 VFs
[22:06:57] [PASSED] 33 VFs
[22:06:57] [PASSED] 34 VFs
[22:06:57] [PASSED] 35 VFs
[22:06:57] [PASSED] 36 VFs
[22:06:57] [PASSED] 37 VFs
[22:06:57] [PASSED] 38 VFs
[22:06:57] [PASSED] 39 VFs
[22:06:57] [PASSED] 40 VFs
[22:06:57] [PASSED] 41 VFs
[22:06:57] [PASSED] 42 VFs
[22:06:57] [PASSED] 43 VFs
[22:06:57] [PASSED] 44 VFs
[22:06:57] [PASSED] 45 VFs
[22:06:57] [PASSED] 46 VFs
[22:06:57] [PASSED] 47 VFs
[22:06:57] [PASSED] 48 VFs
[22:06:57] [PASSED] 49 VFs
[22:06:57] [PASSED] 50 VFs
[22:06:57] [PASSED] 51 VFs
[22:06:57] [PASSED] 52 VFs
[22:06:57] [PASSED] 53 VFs
[22:06:57] [PASSED] 54 VFs
[22:06:57] [PASSED] 55 VFs
[22:06:57] [PASSED] 56 VFs
[22:06:57] [PASSED] 57 VFs
[22:06:57] [PASSED] 58 VFs
[22:06:57] [PASSED] 59 VFs
[22:06:57] [PASSED] 60 VFs
[22:06:57] [PASSED] 61 VFs
[22:06:57] [PASSED] 62 VFs
[22:06:57] [PASSED] 63 VFs
[22:06:57] ==================== [PASSED] fair_vram ====================
[22:06:57] ================== [PASSED] pf_gt_config ===================
[22:06:57] ===================== lmtt (1 subtest) =====================
[22:06:57] ======================== test_ops  =========================
[22:06:57] [PASSED] 2-level
[22:06:57] [PASSED] multi-level
[22:06:57] ==================== [PASSED] test_ops =====================
[22:06:57] ====================== [PASSED] lmtt =======================
[22:06:57] ================= pf_service (11 subtests) =================
[22:06:57] [PASSED] pf_negotiate_any
[22:06:57] [PASSED] pf_negotiate_base_match
[22:06:57] [PASSED] pf_negotiate_base_newer
[22:06:57] [PASSED] pf_negotiate_base_next
[22:06:57] [SKIPPED] pf_negotiate_base_older
[22:06:57] [PASSED] pf_negotiate_base_prev
[22:06:57] [PASSED] pf_negotiate_latest_match
[22:06:57] [PASSED] pf_negotiate_latest_newer
[22:06:57] [PASSED] pf_negotiate_latest_next
[22:06:57] [SKIPPED] pf_negotiate_latest_older
[22:06:57] [SKIPPED] pf_negotiate_latest_prev
[22:06:57] =================== [PASSED] pf_service ====================
[22:06:57] ================= xe_guc_g2g (2 subtests) ==================
[22:06:57] ============== xe_live_guc_g2g_kunit_default  ==============
[22:06:57] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[22:06:57] ============== xe_live_guc_g2g_kunit_allmem  ===============
[22:06:57] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[22:06:57] =================== [SKIPPED] xe_guc_g2g ===================
[22:06:57] =================== xe_mocs (2 subtests) ===================
[22:06:57] ================ xe_live_mocs_kernel_kunit  ================
[22:06:57] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:06:57] ================ xe_live_mocs_reset_kunit  =================
[22:06:57] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:06:57] ==================== [SKIPPED] xe_mocs =====================
[22:06:57] ================= xe_migrate (2 subtests) ==================
[22:06:57] ================= xe_migrate_sanity_kunit  =================
[22:06:57] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:06:57] ================== xe_validate_ccs_kunit  ==================
[22:06:57] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:06:57] =================== [SKIPPED] xe_migrate ===================
[22:06:57] ================== xe_dma_buf (1 subtest) ==================
[22:06:57] ==================== xe_dma_buf_kunit  =====================
[22:06:57] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:06:57] =================== [SKIPPED] xe_dma_buf ===================
[22:06:57] ================= xe_bo_shrink (1 subtest) =================
[22:06:57] =================== xe_bo_shrink_kunit  ====================
[22:06:57] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:06:57] ================== [SKIPPED] xe_bo_shrink ==================
[22:06:57] ==================== xe_bo (2 subtests) ====================
[22:06:57] ================== xe_ccs_migrate_kunit  ===================
[22:06:57] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:06:57] ==================== xe_bo_evict_kunit  ====================
[22:06:57] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:06:57] ===================== [SKIPPED] xe_bo ======================
[22:06:57] ==================== args (13 subtests) ====================
[22:06:57] [PASSED] count_args_test
[22:06:57] [PASSED] call_args_example
[22:06:57] [PASSED] call_args_test
[22:06:57] [PASSED] drop_first_arg_example
[22:06:57] [PASSED] drop_first_arg_test
[22:06:57] [PASSED] first_arg_example
[22:06:57] [PASSED] first_arg_test
[22:06:57] [PASSED] last_arg_example
[22:06:57] [PASSED] last_arg_test
[22:06:57] [PASSED] pick_arg_example
[22:06:57] [PASSED] if_args_example
[22:06:57] [PASSED] if_args_test
[22:06:57] [PASSED] sep_comma_example
[22:06:57] ====================== [PASSED] args =======================
[22:06:57] =================== xe_pci (3 subtests) ====================
[22:06:57] ==================== check_graphics_ip  ====================
[22:06:57] [PASSED] 12.00 Xe_LP
[22:06:57] [PASSED] 12.10 Xe_LP+
[22:06:57] [PASSED] 12.55 Xe_HPG
[22:06:57] [PASSED] 12.60 Xe_HPC
[22:06:57] [PASSED] 12.70 Xe_LPG
[22:06:57] [PASSED] 12.71 Xe_LPG
[22:06:57] [PASSED] 12.74 Xe_LPG+
[22:06:57] [PASSED] 20.01 Xe2_HPG
[22:06:57] [PASSED] 20.02 Xe2_HPG
[22:06:57] [PASSED] 20.04 Xe2_LPG
[22:06:57] [PASSED] 30.00 Xe3_LPG
[22:06:57] [PASSED] 30.01 Xe3_LPG
[22:06:57] [PASSED] 30.03 Xe3_LPG
[22:06:57] [PASSED] 30.04 Xe3_LPG
[22:06:57] [PASSED] 30.05 Xe3_LPG
[22:06:57] [PASSED] 35.10 Xe3p_LPG
[22:06:57] [PASSED] 35.11 Xe3p_XPC
[22:06:57] ================ [PASSED] check_graphics_ip ================
[22:06:57] ===================== check_media_ip  ======================
[22:06:57] [PASSED] 12.00 Xe_M
[22:06:57] [PASSED] 12.55 Xe_HPM
[22:06:57] [PASSED] 13.00 Xe_LPM+
[22:06:57] [PASSED] 13.01 Xe2_HPM
[22:06:57] [PASSED] 20.00 Xe2_LPM
[22:06:57] [PASSED] 30.00 Xe3_LPM
[22:06:57] [PASSED] 30.02 Xe3_LPM
[22:06:57] [PASSED] 35.00 Xe3p_LPM
[22:06:57] [PASSED] 35.03 Xe3p_HPM
[22:06:57] ================= [PASSED] check_media_ip ==================
[22:06:57] =================== check_platform_desc  ===================
[22:06:57] [PASSED] 0x9A60 (TIGERLAKE)
[22:06:57] [PASSED] 0x9A68 (TIGERLAKE)
[22:06:57] [PASSED] 0x9A70 (TIGERLAKE)
[22:06:57] [PASSED] 0x9A40 (TIGERLAKE)
[22:06:57] [PASSED] 0x9A49 (TIGERLAKE)
[22:06:57] [PASSED] 0x9A59 (TIGERLAKE)
[22:06:57] [PASSED] 0x9A78 (TIGERLAKE)
[22:06:57] [PASSED] 0x9AC0 (TIGERLAKE)
[22:06:57] [PASSED] 0x9AC9 (TIGERLAKE)
[22:06:57] [PASSED] 0x9AD9 (TIGERLAKE)
[22:06:57] [PASSED] 0x9AF8 (TIGERLAKE)
[22:06:57] [PASSED] 0x4C80 (ROCKETLAKE)
[22:06:57] [PASSED] 0x4C8A (ROCKETLAKE)
[22:06:57] [PASSED] 0x4C8B (ROCKETLAKE)
[22:06:57] [PASSED] 0x4C8C (ROCKETLAKE)
[22:06:57] [PASSED] 0x4C90 (ROCKETLAKE)
[22:06:57] [PASSED] 0x4C9A (ROCKETLAKE)
[22:06:57] [PASSED] 0x4680 (ALDERLAKE_S)
[22:06:57] [PASSED] 0x4682 (ALDERLAKE_S)
[22:06:57] [PASSED] 0x4688 (ALDERLAKE_S)
[22:06:57] [PASSED] 0x468A (ALDERLAKE_S)
[22:06:57] [PASSED] 0x468B (ALDERLAKE_S)
[22:06:57] [PASSED] 0x4690 (ALDERLAKE_S)
[22:06:57] [PASSED] 0x4692 (ALDERLAKE_S)
[22:06:57] [PASSED] 0x4693 (ALDERLAKE_S)
[22:06:57] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46AA (ALDERLAKE_P)
[22:06:57] [PASSED] 0x462A (ALDERLAKE_P)
[22:06:57] [PASSED] 0x4626 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x4628 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46B0 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:06:57] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:06:57] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:06:57] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:06:57] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:06:57] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:06:57] [PASSED] 0xA721 (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA720 (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:06:57] [PASSED] 0xA780 (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA781 (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA782 (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA783 (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA788 (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA789 (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA78A (ALDERLAKE_S)
[22:06:57] [PASSED] 0xA78B (ALDERLAKE_S)
[22:06:57] [PASSED] 0x4905 (DG1)
[22:06:57] [PASSED] 0x4906 (DG1)
[22:06:57] [PASSED] 0x4907 (DG1)
[22:06:57] [PASSED] 0x4908 (DG1)
[22:06:57] [PASSED] 0x4909 (DG1)
[22:06:57] [PASSED] 0x56C0 (DG2)
[22:06:57] [PASSED] 0x56C2 (DG2)
[22:06:57] [PASSED] 0x56C1 (DG2)
[22:06:57] [PASSED] 0x7D51 (METEORLAKE)
[22:06:57] [PASSED] 0x7DD1 (METEORLAKE)
[22:06:57] [PASSED] 0x7D41 (METEORLAKE)
[22:06:57] [PASSED] 0x7D67 (METEORLAKE)
[22:06:57] [PASSED] 0xB640 (METEORLAKE)
[22:06:57] [PASSED] 0x56A0 (DG2)
[22:06:57] [PASSED] 0x56A1 (DG2)
[22:06:57] [PASSED] 0x56A2 (DG2)
[22:06:57] [PASSED] 0x56BE (DG2)
[22:06:57] [PASSED] 0x56BF (DG2)
[22:06:57] [PASSED] 0x5690 (DG2)
[22:06:57] [PASSED] 0x5691 (DG2)
[22:06:57] [PASSED] 0x5692 (DG2)
[22:06:57] [PASSED] 0x56A5 (DG2)
[22:06:57] [PASSED] 0x56A6 (DG2)
[22:06:57] [PASSED] 0x56B0 (DG2)
[22:06:57] [PASSED] 0x56B1 (DG2)
[22:06:57] [PASSED] 0x56BA (DG2)
[22:06:57] [PASSED] 0x56BB (DG2)
[22:06:57] [PASSED] 0x56BC (DG2)
[22:06:57] [PASSED] 0x56BD (DG2)
[22:06:57] [PASSED] 0x5693 (DG2)
[22:06:57] [PASSED] 0x5694 (DG2)
[22:06:57] [PASSED] 0x5695 (DG2)
[22:06:57] [PASSED] 0x56A3 (DG2)
[22:06:57] [PASSED] 0x56A4 (DG2)
[22:06:57] [PASSED] 0x56B2 (DG2)
[22:06:57] [PASSED] 0x56B3 (DG2)
[22:06:57] [PASSED] 0x5696 (DG2)
[22:06:57] [PASSED] 0x5697 (DG2)
[22:06:57] [PASSED] 0xB69 (PVC)
[22:06:57] [PASSED] 0xB6E (PVC)
[22:06:57] [PASSED] 0xBD4 (PVC)
[22:06:57] [PASSED] 0xBD5 (PVC)
[22:06:57] [PASSED] 0xBD6 (PVC)
[22:06:57] [PASSED] 0xBD7 (PVC)
[22:06:57] [PASSED] 0xBD8 (PVC)
[22:06:57] [PASSED] 0xBD9 (PVC)
[22:06:57] [PASSED] 0xBDA (PVC)
[22:06:57] [PASSED] 0xBDB (PVC)
[22:06:57] [PASSED] 0xBE0 (PVC)
[22:06:57] [PASSED] 0xBE1 (PVC)
[22:06:57] [PASSED] 0xBE5 (PVC)
[22:06:57] [PASSED] 0x7D40 (METEORLAKE)
[22:06:57] [PASSED] 0x7D45 (METEORLAKE)
[22:06:57] [PASSED] 0x7D55 (METEORLAKE)
[22:06:57] [PASSED] 0x7D60 (METEORLAKE)
[22:06:57] [PASSED] 0x7DD5 (METEORLAKE)
[22:06:57] [PASSED] 0x6420 (LUNARLAKE)
[22:06:57] [PASSED] 0x64A0 (LUNARLAKE)
[22:06:57] [PASSED] 0x64B0 (LUNARLAKE)
[22:06:57] [PASSED] 0xE202 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE209 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE20B (BATTLEMAGE)
[22:06:57] [PASSED] 0xE20C (BATTLEMAGE)
[22:06:57] [PASSED] 0xE20D (BATTLEMAGE)
[22:06:57] [PASSED] 0xE210 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE211 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE212 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE216 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE220 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE221 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE222 (BATTLEMAGE)
[22:06:57] [PASSED] 0xE223 (BATTLEMAGE)
[22:06:57] [PASSED] 0xB080 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB081 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB082 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB083 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB084 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB085 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB086 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB087 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB08F (PANTHERLAKE)
[22:06:57] [PASSED] 0xB090 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:06:57] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:06:57] [PASSED] 0xFD80 (PANTHERLAKE)
[22:06:57] [PASSED] 0xFD81 (PANTHERLAKE)
[22:06:57] [PASSED] 0xD740 (NOVALAKE_S)
[22:06:57] [PASSED] 0xD741 (NOVALAKE_S)
[22:06:57] [PASSED] 0xD742 (NOVALAKE_S)
[22:06:57] [PASSED] 0xD743 (NOVALAKE_S)
[22:06:57] [PASSED] 0xD745 (NOVALAKE_S)
[22:06:57] [PASSED] 0xD74A (NOVALAKE_S)
[22:06:57] [PASSED] 0xD74B (NOVALAKE_S)
[22:06:57] [PASSED] 0x674C (CRESCENTISLAND)
[22:06:57] [PASSED] 0x674D (CRESCENTISLAND)
[22:06:57] [PASSED] 0x674E (CRESCENTISLAND)
[22:06:57] [PASSED] 0x674F (CRESCENTISLAND)
[22:06:57] [PASSED] 0x6750 (CRESCENTISLAND)
[22:06:57] [PASSED] 0xD750 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD751 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD752 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD753 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD754 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD755 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD756 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD757 (NOVALAKE_P)
[22:06:57] [PASSED] 0xD75F (NOVALAKE_P)
[22:06:57] =============== [PASSED] check_platform_desc ===============
[22:06:57] ===================== [PASSED] xe_pci ======================
[22:06:57] ============= xe_rtp_tables_test (4 subtests) ==============
[22:06:57] ================== xe_rtp_table_gt_test  ===================
[22:06:57] [PASSED] gt_was/14011060649
[22:06:57] [PASSED] gt_was/14011059788
[22:06:57] [PASSED] gt_was/14015795083
[22:06:57] [PASSED] gt_was/16021867713
[22:06:57] [PASSED] gt_was/14019449301
[22:06:57] [PASSED] gt_was/16028005424
[22:06:57] [PASSED] gt_was/14026578760
[22:06:57] [PASSED] gt_was/1409420604
[22:06:57] [PASSED] gt_was/1408615072
[22:06:57] [PASSED] gt_was/22010523718
[22:06:57] [PASSED] gt_was/14011006942
[22:06:57] [PASSED] gt_was/14014830051
[22:06:57] [PASSED] gt_was/18018781329
[22:06:57] [PASSED] gt_was/1509235366
[22:06:57] [PASSED] gt_was/18018781329
[22:06:57] [PASSED] gt_was/16016694945
[22:06:57] [PASSED] gt_was/14018575942
[22:06:57] [PASSED] gt_was/22016670082
[22:06:57] [PASSED] gt_was/22016670082
[22:06:57] [PASSED] gt_was/14017421178
[22:06:57] [PASSED] gt_was/16025250150
[22:06:57] [PASSED] gt_was/14021871409
[22:06:57] [PASSED] gt_was/16021865536
[22:06:57] [PASSED] gt_was/14021486841
[22:06:57] [PASSED] gt_was/14025160223
[22:06:57] [PASSED] gt_was/14026144927, 16029437861
[22:06:57] [PASSED] gt_was/14025635424
[22:06:57] [PASSED] gt_was/16028005424
[22:06:57] ============== [PASSED] xe_rtp_table_gt_test ===============
[22:06:57] ================== xe_rtp_table_gt_test  ===================
[22:06:57] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[22:06:57] [PASSED] gt_tunings/Tuning: 32B Access Enable
[22:06:57] [PASSED] gt_tunings/Tuning: L3 cache
[22:06:57] [PASSED] gt_tunings/Tuning: L3 cache - media
[22:06:57] [PASSED] gt_tunings/Tuning: Compression Overfetch
[22:06:57] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[22:06:57] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[22:06:57] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[22:06:57] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[22:06:57] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[22:06:57] [PASSED] gt_tunings/Tuning: Stateless compression control
[22:06:57] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[22:06:57] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[22:06:57] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[22:06:57] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[22:06:57] ============== [PASSED] xe_rtp_table_gt_test ===============
[22:06:57] ================== xe_rtp_table_oob_test  ==================
[22:06:57] [PASSED] oob_was/1607983814
[22:06:57] [PASSED] oob_was/16010904313
[22:06:57] [PASSED] oob_was/18022495364
[22:06:57] [PASSED] oob_was/22012773006
[22:06:57] [PASSED] oob_was/14014475959
[22:06:57] [PASSED] oob_was/22011391025
[22:06:57] [PASSED] oob_was/22012727170
[22:06:57] [PASSED] oob_was/22012727685
[22:06:57] [PASSED] oob_was/22016596838
[22:06:57] [PASSED] oob_was/18020744125
[22:06:57] [PASSED] oob_was/1409600907
[22:06:57] [PASSED] oob_was/22014953428
[22:06:57] [PASSED] oob_was/16017236439
[22:06:57] [PASSED] oob_was/14019821291
[22:06:57] [PASSED] oob_was/14015076503
[22:06:57] [PASSED] oob_was/14018913170
[22:06:57] [PASSED] oob_was/14018094691
[22:06:57] [PASSED] oob_was/18024947630
[22:06:57] [PASSED] oob_was/16022287689
[22:06:57] [PASSED] oob_was/13011645652
[22:06:57] [PASSED] oob_was/14022293748
[22:06:57] [PASSED] oob_was/22019794406
[22:06:57] [PASSED] oob_was/22019338487
[22:06:57] [PASSED] oob_was/16023588340
[22:06:57] [PASSED] oob_was/14019789679
[22:06:57] [PASSED] oob_was/14022866841
[22:06:57] [PASSED] oob_was/16021333562
[22:06:57] [PASSED] oob_was/14016712196
[22:06:57] [PASSED] oob_was/14015568240
[22:06:57] [PASSED] oob_was/18013179988
[22:06:57] [PASSED] oob_was/1508761755
[22:06:57] [PASSED] oob_was/16023105232
[22:06:57] [PASSED] oob_was/16026508708
[22:06:57] [PASSED] oob_was/14020001231
[22:06:57] [PASSED] oob_was/16023683509
[22:06:57] [PASSED] oob_was/14025515070
[22:06:57] [PASSED] oob_was/15015404425_disable
[22:06:57] [PASSED] oob_was/16026007364
[22:06:57] [PASSED] oob_was/14020316580
[22:06:57] [PASSED] oob_was/14025883347
[22:06:57] ============== [PASSED] xe_rtp_table_oob_test ==============
[22:06:57] ================ xe_rtp_table_dev_oob_test  ================
[22:06:57] [PASSED] device_oob_was/22010954014
[22:06:57] [PASSED] device_oob_was/15015404425
[22:06:57] [PASSED] device_oob_was/22019338487_display
[22:06:57] [PASSED] device_oob_was/14022085890
[22:06:57] [PASSED] device_oob_was/14026539277
[22:06:57] [PASSED] device_oob_was/14026633728
[22:06:57] [PASSED] device_oob_was/14026746987
[22:06:57] [PASSED] device_oob_was/14026779378
[22:06:57] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[22:06:57] =============== [PASSED] xe_rtp_tables_test ================
[22:06:57] =================== xe_rtp (3 subtests) ====================
[22:06:57] =================== xe_rtp_rules_tests  ====================
[22:06:57] [PASSED] no
[22:06:57] [PASSED] yes
[22:06:57] [PASSED] no-and-no
[22:06:57] [PASSED] no-and-yes
[22:06:57] [PASSED] yes-and-no
[22:06:57] [PASSED] yes-and-yes
[22:06:57] [PASSED] no-or-no
[22:06:57] [PASSED] no-or-yes
[22:06:57] [PASSED] yes-or-no
[22:06:57] [PASSED] yes-or-yes
[22:06:57] [PASSED] no-yes-or-yes-no
[22:06:57] [PASSED] no-yes-or-yes-yes
[22:06:57] [PASSED] yes-yes-or-no-yes
[22:06:57] [PASSED] yes-yes-or-yes-yes
[22:06:57] [PASSED] no-no-or-yes-or-no
[22:06:57] [PASSED] or
[22:06:57] [PASSED] or-yes
[22:06:57] [PASSED] or-no
[22:06:57] [PASSED] yes-or
[22:06:57] [PASSED] no-or
[22:06:57] [PASSED] no-or-or-yes
[22:06:57] [PASSED] yes-or-or-no
[22:06:57] [PASSED] no-or-or-no
[22:06:57] [PASSED] missing-context-engine-class
[22:06:57] [PASSED] missing-context-engine-class-or-yes
[22:06:57] [PASSED] missing-context-engine-class-or-or-yes
[22:06:57] =============== [PASSED] xe_rtp_rules_tests ================
[22:06:57] =============== xe_rtp_process_to_sr_tests  ================
[22:06:57] [PASSED] coalesce-same-reg
[22:06:57] [PASSED] no-match-no-add
[22:06:57] [PASSED] two-regs-two-entries
[22:06:57] [PASSED] clr-one-set-other
[22:06:57] [PASSED] set-field
[22:06:57] [PASSED] conflict-duplicate
[22:06:57] [PASSED] conflict-not-disjoint
[22:06:57] [PASSED] conflict-reg-type
[22:06:57] [PASSED] bad-mcr-reg-forced-to-regular
[22:06:57] [PASSED] bad-regular-reg-forced-to-mcr
[22:06:57] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:06:57] ================== xe_rtp_process_tests  ===================
[22:06:57] [PASSED] active1
[22:06:57] [PASSED] active2
[22:06:57] [PASSED] active-inactive
[22:06:57] [PASSED] inactive-active
[22:06:57] [PASSED] inactive-active-inactive
[22:06:57] [PASSED] inactive-inactive-inactive
[22:06:57] ============== [PASSED] xe_rtp_process_tests ===============
[22:06:57] ===================== [PASSED] xe_rtp ======================
[22:06:57] ==================== xe_wa (1 subtest) =====================
[22:06:57] ======================== xe_wa_gt  =========================
[22:06:57] [PASSED] TIGERLAKE B0
[22:06:57] [PASSED] DG1 A0
[22:06:57] [PASSED] DG1 B0
[22:06:57] [PASSED] ALDERLAKE_S A0
[22:06:57] [PASSED] ALDERLAKE_S B0
[22:06:57] [PASSED] ALDERLAKE_S C0
[22:06:57] [PASSED] ALDERLAKE_S D0
[22:06:57] [PASSED] ALDERLAKE_P A0
[22:06:57] [PASSED] ALDERLAKE_P B0
[22:06:57] [PASSED] ALDERLAKE_P C0
[22:06:57] [PASSED] ALDERLAKE_S RPLS D0
[22:06:57] [PASSED] ALDERLAKE_P RPLU E0
[22:06:57] [PASSED] DG2 G10 C0
[22:06:57] [PASSED] DG2 G11 B1
[22:06:57] [PASSED] DG2 G12 A1
[22:06:57] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:06:57] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:06:57] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[22:06:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[22:06:57] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[22:06:57] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[22:06:57] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[22:06:57] ==================== [PASSED] xe_wa_gt =====================
[22:06:57] ====================== [PASSED] xe_wa ======================
[22:06:57] ============================================================
[22:06:57] Testing complete. Ran 716 tests: passed: 698, skipped: 18
[22:06:58] Elapsed time: 36.389s total, 4.315s configuring, 31.408s building, 0.631s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:06:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:06:59] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
In file included from ../drivers/gpu/drm/tests/drm_bridge_test.c:21:
../drivers/gpu/drm/tests/drm_kunit_edid.h:958:28: warning: ‘test_edid_hdmi_4k_rgb_yuv420_dc_max_340mhz’ defined but not used [-Wunused-const-variable=]
  958 | static const unsigned char test_edid_hdmi_4k_rgb_yuv420_dc_max_340mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:726:28: warning: ‘test_edid_hdmi_1080p_rgb_yuv_dc_max_340mhz’ defined but not used [-Wunused-const-variable=]
  726 | static const unsigned char test_edid_hdmi_1080p_rgb_yuv_dc_max_340mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:612:28: warning: ‘test_edid_hdmi_1080p_rgb_yuv_dc_max_200mhz’ defined but not used [-Wunused-const-variable=]
  612 | static const unsigned char test_edid_hdmi_1080p_rgb_yuv_dc_max_200mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:498:28: warning: ‘test_edid_hdmi_1080p_rgb_max_340mhz’ defined but not used [-Wunused-const-variable=]
  498 | static const unsigned char test_edid_hdmi_1080p_rgb_max_340mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:390:28: warning: ‘test_edid_hdmi_1080p_rgb_max_200mhz_hdr’ defined but not used [-Wunused-const-variable=]
  390 | static const unsigned char test_edid_hdmi_1080p_rgb_max_200mhz_hdr[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:271:28: warning: ‘test_edid_hdmi_1080p_rgb_max_200mhz’ defined but not used [-Wunused-const-variable=]
  271 | static const unsigned char test_edid_hdmi_1080p_rgb_max_200mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:163:28: warning: ‘test_edid_hdmi_1080p_rgb_max_100mhz’ defined but not used [-Wunused-const-variable=]
  163 | static const unsigned char test_edid_hdmi_1080p_rgb_max_100mhz[] = {
      |                            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/tests/drm_kunit_edid.h:57:28: warning: ‘test_edid_dvi_1080p’ defined but not used [-Wunused-const-variable=]
   57 | static const unsigned char test_edid_dvi_1080p[] = {
      |                            ^~~~~~~~~~~~~~~~~~~

[22:07:24] Starting KUnit Kernel (1/1)...
[22:07:24] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:07:24] ============ drm_test_pick_cmdline (2 subtests) ============
[22:07:24] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[22:07:24] =============== drm_test_pick_cmdline_named  ===============
[22:07:24] [PASSED] NTSC
[22:07:24] [PASSED] NTSC-J
[22:07:24] [PASSED] PAL
[22:07:24] [PASSED] PAL-M
[22:07:24] =========== [PASSED] drm_test_pick_cmdline_named ===========
[22:07:24] ============== [PASSED] drm_test_pick_cmdline ==============
[22:07:24] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[22:07:24] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[22:07:24] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[22:07:24] =========== drm_validate_clone_mode (2 subtests) ===========
[22:07:24] ============== drm_test_check_in_clone_mode  ===============
[22:07:24] [PASSED] in_clone_mode
[22:07:24] [PASSED] not_in_clone_mode
[22:07:24] ========== [PASSED] drm_test_check_in_clone_mode ===========
[22:07:24] =============== drm_test_check_valid_clones  ===============
[22:07:24] [PASSED] not_in_clone_mode
[22:07:24] [PASSED] valid_clone
[22:07:24] [PASSED] invalid_clone
[22:07:24] =========== [PASSED] drm_test_check_valid_clones ===========
[22:07:24] ============= [PASSED] drm_validate_clone_mode =============
[22:07:24] ============= drm_validate_modeset (1 subtest) =============
[22:07:24] [PASSED] drm_test_check_connector_changed_modeset
[22:07:24] ============== [PASSED] drm_validate_modeset ===============
[22:07:24] ====== drm_test_bridge_get_current_state (2 subtests) ======
[22:07:24] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[22:07:24] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[22:07:24] ======== [PASSED] drm_test_bridge_get_current_state ========
[22:07:24] ====== drm_test_bridge_helper_reset_crtc (4 subtests) ======
[22:07:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[22:07:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[22:07:24] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[22:07:24] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[22:07:24] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[22:07:24] ============== drm_bridge_alloc (2 subtests) ===============
[22:07:24] [PASSED] drm_test_drm_bridge_alloc_basic
[22:07:24] [PASSED] drm_test_drm_bridge_alloc_get_put
[22:07:24] ================ [PASSED] drm_bridge_alloc =================
[22:07:24] ============= drm_bridge_bus_fmt (5 subtests) ==============
[22:07:24] [PASSED] drm_test_bridge_rgb_yuv_rgb
[22:07:24] [PASSED] drm_test_bridge_must_convert_to_yuv444
[22:07:24] [PASSED] drm_test_bridge_hdmi_auto_rgb
[22:07:24] [PASSED] drm_test_bridge_auto_first
[22:07:24] [PASSED] drm_test_bridge_rgb_yuv_no_path
[22:07:24] =============== [PASSED] drm_bridge_bus_fmt ================
[22:07:24] ============= drm_cmdline_parser (40 subtests) =============
[22:07:24] [PASSED] drm_test_cmdline_force_d_only
[22:07:24] [PASSED] drm_test_cmdline_force_D_only_dvi
[22:07:24] [PASSED] drm_test_cmdline_force_D_only_hdmi
[22:07:24] [PASSED] drm_test_cmdline_force_D_only_not_digital
[22:07:24] [PASSED] drm_test_cmdline_force_e_only
[22:07:24] [PASSED] drm_test_cmdline_res
[22:07:24] [PASSED] drm_test_cmdline_res_vesa
[22:07:24] [PASSED] drm_test_cmdline_res_vesa_rblank
[22:07:24] [PASSED] drm_test_cmdline_res_rblank
[22:07:24] [PASSED] drm_test_cmdline_res_bpp
[22:07:24] [PASSED] drm_test_cmdline_res_refresh
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[22:07:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[22:07:24] [PASSED] drm_test_cmdline_res_margins_force_on
[22:07:24] [PASSED] drm_test_cmdline_res_vesa_margins
[22:07:24] [PASSED] drm_test_cmdline_name
[22:07:24] [PASSED] drm_test_cmdline_name_bpp
[22:07:24] [PASSED] drm_test_cmdline_name_option
[22:07:24] [PASSED] drm_test_cmdline_name_bpp_option
[22:07:24] [PASSED] drm_test_cmdline_rotate_0
[22:07:24] [PASSED] drm_test_cmdline_rotate_90
[22:07:24] [PASSED] drm_test_cmdline_rotate_180
[22:07:24] [PASSED] drm_test_cmdline_rotate_270
[22:07:24] [PASSED] drm_test_cmdline_hmirror
[22:07:24] [PASSED] drm_test_cmdline_vmirror
[22:07:24] [PASSED] drm_test_cmdline_margin_options
[22:07:24] [PASSED] drm_test_cmdline_multiple_options
[22:07:24] [PASSED] drm_test_cmdline_bpp_extra_and_option
[22:07:24] [PASSED] drm_test_cmdline_extra_and_option
[22:07:24] [PASSED] drm_test_cmdline_freestanding_options
[22:07:24] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[22:07:24] [PASSED] drm_test_cmdline_panel_orientation
[22:07:24] ================ drm_test_cmdline_invalid  =================
[22:07:24] [PASSED] margin_only
[22:07:24] [PASSED] interlace_only
[22:07:24] [PASSED] res_missing_x
[22:07:24] [PASSED] res_missing_y
[22:07:24] [PASSED] res_bad_y
[22:07:24] [PASSED] res_missing_y_bpp
[22:07:24] [PASSED] res_bad_bpp
[22:07:24] [PASSED] res_bad_refresh
[22:07:24] [PASSED] res_bpp_refresh_force_on_off
[22:07:24] [PASSED] res_invalid_mode
[22:07:24] [PASSED] res_bpp_wrong_place_mode
[22:07:24] [PASSED] name_bpp_refresh
[22:07:24] [PASSED] name_refresh
[22:07:24] [PASSED] name_refresh_wrong_mode
[22:07:24] [PASSED] name_refresh_invalid_mode
[22:07:24] [PASSED] rotate_multiple
[22:07:24] [PASSED] rotate_invalid_val
[22:07:24] [PASSED] rotate_truncated
[22:07:24] [PASSED] invalid_option
[22:07:24] [PASSED] invalid_tv_option
[22:07:24] [PASSED] truncated_tv_option
[22:07:24] ============ [PASSED] drm_test_cmdline_invalid =============
[22:07:24] =============== drm_test_cmdline_tv_options  ===============
[22:07:24] [PASSED] NTSC
[22:07:24] [PASSED] NTSC_443
[22:07:24] [PASSED] NTSC_J
[22:07:24] [PASSED] PAL
[22:07:24] [PASSED] PAL_M
[22:07:24] [PASSED] PAL_N
[22:07:24] [PASSED] SECAM
[22:07:24] [PASSED] MONO_525
[22:07:24] [PASSED] MONO_625
[22:07:24] =========== [PASSED] drm_test_cmdline_tv_options ===========
[22:07:24] =============== [PASSED] drm_cmdline_parser ================
[22:07:24] ========== drmm_connector_hdmi_init (20 subtests) ==========
[22:07:24] [PASSED] drm_test_connector_hdmi_init_valid
[22:07:24] [PASSED] drm_test_connector_hdmi_init_bpc_8
[22:07:24] [PASSED] drm_test_connector_hdmi_init_bpc_10
[22:07:24] [PASSED] drm_test_connector_hdmi_init_bpc_12
[22:07:24] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[22:07:24] [PASSED] drm_test_connector_hdmi_init_bpc_null
[22:07:24] [PASSED] drm_test_connector_hdmi_init_formats_empty
[22:07:24] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[22:07:24] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[22:07:24] [PASSED] supported_formats=0x9 yuv420_allowed=1
[22:07:24] [PASSED] supported_formats=0x9 yuv420_allowed=0
[22:07:24] [PASSED] supported_formats=0x5 yuv420_allowed=1
[22:07:24] [PASSED] supported_formats=0x5 yuv420_allowed=0
[22:07:24] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:07:24] [PASSED] drm_test_connector_hdmi_init_null_ddc
[22:07:24] [PASSED] drm_test_connector_hdmi_init_null_product
[22:07:24] [PASSED] drm_test_connector_hdmi_init_null_vendor
[22:07:24] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[22:07:24] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[22:07:24] [PASSED] drm_test_connector_hdmi_init_product_valid
[22:07:24] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[22:07:24] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[22:07:24] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[22:07:24] ========= drm_test_connector_hdmi_init_type_valid  =========
[22:07:24] [PASSED] HDMI-A
[22:07:24] [PASSED] HDMI-B
[22:07:24] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[22:07:24] ======== drm_test_connector_hdmi_init_type_invalid  ========
[22:07:24] [PASSED] Unknown
[22:07:24] [PASSED] VGA
[22:07:24] [PASSED] DVI-I
[22:07:24] [PASSED] DVI-D
[22:07:24] [PASSED] DVI-A
[22:07:24] [PASSED] Composite
[22:07:24] [PASSED] SVIDEO
[22:07:24] [PASSED] LVDS
[22:07:24] [PASSED] Component
[22:07:24] [PASSED] DIN
[22:07:24] [PASSED] DP
[22:07:24] [PASSED] TV
[22:07:24] [PASSED] eDP
[22:07:24] [PASSED] Virtual
[22:07:24] [PASSED] DSI
[22:07:24] [PASSED] DPI
[22:07:24] [PASSED] Writeback
[22:07:24] [PASSED] SPI
[22:07:24] [PASSED] USB
[22:07:24] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[22:07:24] ============ [PASSED] drmm_connector_hdmi_init =============
[22:07:24] ============= drmm_connector_init (3 subtests) =============
[22:07:24] [PASSED] drm_test_drmm_connector_init
[22:07:24] [PASSED] drm_test_drmm_connector_init_null_ddc
[22:07:24] ========= drm_test_drmm_connector_init_type_valid  =========
[22:07:24] [PASSED] Unknown
[22:07:24] [PASSED] VGA
[22:07:24] [PASSED] DVI-I
[22:07:24] [PASSED] DVI-D
[22:07:24] [PASSED] DVI-A
[22:07:24] [PASSED] Composite
[22:07:24] [PASSED] SVIDEO
[22:07:24] [PASSED] LVDS
[22:07:24] [PASSED] Component
[22:07:24] [PASSED] DIN
[22:07:24] [PASSED] DP
[22:07:24] [PASSED] HDMI-A
[22:07:24] [PASSED] HDMI-B
[22:07:24] [PASSED] TV
[22:07:24] [PASSED] eDP
[22:07:24] [PASSED] Virtual
[22:07:24] [PASSED] DSI
[22:07:24] [PASSED] DPI
[22:07:24] [PASSED] Writeback
[22:07:24] [PASSED] SPI
[22:07:24] [PASSED] USB
[22:07:24] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[22:07:24] =============== [PASSED] drmm_connector_init ===============
[22:07:24] ========= drm_connector_dynamic_init (6 subtests) ==========
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_init
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_init_properties
[22:07:24] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[22:07:24] [PASSED] Unknown
[22:07:24] [PASSED] VGA
[22:07:24] [PASSED] DVI-I
[22:07:24] [PASSED] DVI-D
[22:07:24] [PASSED] DVI-A
[22:07:24] [PASSED] Composite
[22:07:24] [PASSED] SVIDEO
[22:07:24] [PASSED] LVDS
[22:07:24] [PASSED] Component
[22:07:24] [PASSED] DIN
[22:07:24] [PASSED] DP
[22:07:24] [PASSED] HDMI-A
[22:07:24] [PASSED] HDMI-B
[22:07:24] [PASSED] TV
[22:07:24] [PASSED] eDP
[22:07:24] [PASSED] Virtual
[22:07:24] [PASSED] DSI
[22:07:24] [PASSED] DPI
[22:07:24] [PASSED] Writeback
[22:07:24] [PASSED] SPI
[22:07:24] [PASSED] USB
[22:07:24] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[22:07:24] ======== drm_test_drm_connector_dynamic_init_name  =========
[22:07:24] [PASSED] Unknown
[22:07:24] [PASSED] VGA
[22:07:24] [PASSED] DVI-I
[22:07:24] [PASSED] DVI-D
[22:07:24] [PASSED] DVI-A
[22:07:24] [PASSED] Composite
[22:07:24] [PASSED] SVIDEO
[22:07:24] [PASSED] LVDS
[22:07:24] [PASSED] Component
[22:07:24] [PASSED] DIN
[22:07:24] [PASSED] DP
[22:07:24] [PASSED] HDMI-A
[22:07:24] [PASSED] HDMI-B
[22:07:24] [PASSED] TV
[22:07:24] [PASSED] eDP
[22:07:24] [PASSED] Virtual
[22:07:24] [PASSED] DSI
[22:07:24] [PASSED] DPI
[22:07:24] [PASSED] Writeback
[22:07:24] [PASSED] SPI
[22:07:24] [PASSED] USB
[22:07:24] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[22:07:24] =========== [PASSED] drm_connector_dynamic_init ============
[22:07:24] ==== drm_connector_dynamic_register_early (4 subtests) =====
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[22:07:24] ====== [PASSED] drm_connector_dynamic_register_early =======
[22:07:24] ======= drm_connector_dynamic_register (7 subtests) ========
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[22:07:24] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[22:07:24] ========= [PASSED] drm_connector_dynamic_register ==========
[22:07:24] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[22:07:24] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[22:07:24] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[22:07:24] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[22:07:24] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[22:07:24] ========== drm_test_get_tv_mode_from_name_valid  ===========
[22:07:24] [PASSED] NTSC
[22:07:24] [PASSED] NTSC-443
[22:07:24] [PASSED] NTSC-J
[22:07:24] [PASSED] PAL
[22:07:24] [PASSED] PAL-M
[22:07:24] [PASSED] PAL-N
[22:07:24] [PASSED] SECAM
[22:07:24] [PASSED] Mono
[22:07:24] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[22:07:24] [PASSED] drm_test_get_tv_mode_from_name_truncated
[22:07:24] ============ [PASSED] drm_get_tv_mode_from_name ============
[22:07:24] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[22:07:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[22:07:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[22:07:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[22:07:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[22:07:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[22:07:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[22:07:24] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[22:07:24] [PASSED] VIC 96
[22:07:24] [PASSED] VIC 97
[22:07:24] [PASSED] VIC 101
[22:07:24] [PASSED] VIC 102
[22:07:24] [PASSED] VIC 106
[22:07:24] [PASSED] VIC 107
[22:07:24] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[22:07:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[22:07:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[22:07:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[22:07:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[22:07:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[22:07:24] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[22:07:24] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[22:07:24] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[22:07:24] [PASSED] Automatic
[22:07:24] [PASSED] Full
[22:07:24] [PASSED] Limited 16:235
[22:07:24] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[22:07:24] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[22:07:24] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[22:07:24] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[22:07:24] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[22:07:24] [PASSED] RGB
[22:07:24] [PASSED] YUV 4:2:0
[22:07:24] [PASSED] YUV 4:2:2
[22:07:24] [PASSED] YUV 4:4:4
[22:07:24] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[22:07:24] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[22:07:24] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[22:07:24] ============= drm_damage_helper (21 subtests) ==============
[22:07:24] [PASSED] drm_test_damage_iter_no_damage
[22:07:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[22:07:24] [PASSED] drm_test_damage_iter_no_damage_src_moved
[22:07:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[22:07:24] [PASSED] drm_test_damage_iter_no_damage_not_visible
[22:07:24] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[22:07:24] [PASSED] drm_test_damage_iter_no_damage_no_fb
[22:07:24] [PASSED] drm_test_damage_iter_simple_damage
[22:07:24] [PASSED] drm_test_damage_iter_single_damage
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_outside_src
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_src_moved
[22:07:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[22:07:24] [PASSED] drm_test_damage_iter_damage
[22:07:24] [PASSED] drm_test_damage_iter_damage_one_intersect
[22:07:24] [PASSED] drm_test_damage_iter_damage_one_outside
[22:07:24] [PASSED] drm_test_damage_iter_damage_src_moved
[22:07:24] [PASSED] drm_test_damage_iter_damage_not_visible
[22:07:24] ================ [PASSED] drm_damage_helper ================
[22:07:24] ============== drm_dp_mst_helper (3 subtests) ==============
[22:07:24] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[22:07:24] [PASSED] Clock 154000 BPP 30 DSC disabled
[22:07:24] [PASSED] Clock 234000 BPP 30 DSC disabled
[22:07:24] [PASSED] Clock 297000 BPP 24 DSC disabled
[22:07:24] [PASSED] Clock 332880 BPP 24 DSC enabled
[22:07:24] [PASSED] Clock 324540 BPP 24 DSC enabled
[22:07:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[22:07:24] ============== drm_test_dp_mst_calc_pbn_div  ===============
[22:07:24] [PASSED] Link rate 2000000 lane count 4
[22:07:24] [PASSED] Link rate 2000000 lane count 2
[22:07:24] [PASSED] Link rate 2000000 lane count 1
[22:07:24] [PASSED] Link rate 1350000 lane count 4
[22:07:24] [PASSED] Link rate 1350000 lane count 2
[22:07:24] [PASSED] Link rate 1350000 lane count 1
[22:07:24] [PASSED] Link rate 1000000 lane count 4
[22:07:24] [PASSED] Link rate 1000000 lane count 2
[22:07:24] [PASSED] Link rate 1000000 lane count 1
[22:07:24] [PASSED] Link rate 810000 lane count 4
[22:07:24] [PASSED] Link rate 810000 lane count 2
[22:07:24] [PASSED] Link rate 810000 lane count 1
[22:07:24] [PASSED] Link rate 540000 lane count 4
[22:07:24] [PASSED] Link rate 540000 lane count 2
[22:07:24] [PASSED] Link rate 540000 lane count 1
[22:07:24] [PASSED] Link rate 270000 lane count 4
[22:07:24] [PASSED] Link rate 270000 lane count 2
[22:07:24] [PASSED] Link rate 270000 lane count 1
[22:07:24] [PASSED] Link rate 162000 lane count 4
[22:07:24] [PASSED] Link rate 162000 lane count 2
[22:07:24] [PASSED] Link rate 162000 lane count 1
[22:07:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[22:07:24] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[22:07:24] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[22:07:24] [PASSED] DP_POWER_UP_PHY with port number
[22:07:24] [PASSED] DP_POWER_DOWN_PHY with port number
[22:07:24] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[22:07:24] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[22:07:24] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[22:07:24] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[22:07:24] [PASSED] DP_QUERY_PAYLOAD with port number
[22:07:24] [PASSED] DP_QUERY_PAYLOAD with VCPI
[22:07:24] [PASSED] DP_REMOTE_DPCD_READ with port number
[22:07:24] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[22:07:24] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[22:07:24] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[22:07:24] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[22:07:24] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[22:07:24] [PASSED] DP_REMOTE_I2C_READ with port number
[22:07:24] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[22:07:24] [PASSED] DP_REMOTE_I2C_READ with transactions array
[22:07:24] [PASSED] DP_REMOTE_I2C_WRITE with port number
[22:07:24] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[22:07:24] [PASSED] DP_REMOTE_I2C_WRITE with data array
[22:07:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[22:07:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[22:07:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[22:07:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[22:07:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[22:07:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[22:07:24] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[22:07:24] ================ [PASSED] drm_dp_mst_helper ================
[22:07:24] ================== drm_exec (7 subtests) ===================
[22:07:24] [PASSED] sanitycheck
[22:07:24] [PASSED] test_lock
[22:07:24] [PASSED] test_lock_unlock
[22:07:24] [PASSED] test_duplicates
[22:07:24] [PASSED] test_prepare
[22:07:24] [PASSED] test_prepare_array
[22:07:24] [PASSED] test_multiple_loops
[22:07:24] ==================== [PASSED] drm_exec =====================
[22:07:24] =========== drm_format_helper_test (17 subtests) ===========
[22:07:24] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[22:07:24] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[22:07:24] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[22:07:24] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[22:07:24] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[22:07:24] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[22:07:24] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[22:07:24] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[22:07:24] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[22:07:24] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[22:07:24] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[22:07:24] ============== drm_test_fb_xrgb8888_to_mono  ===============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[22:07:24] ==================== drm_test_fb_swab  =====================
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ================ [PASSED] drm_test_fb_swab =================
[22:07:24] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[22:07:24] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[22:07:24] [PASSED] single_pixel_source_buffer
[22:07:24] [PASSED] single_pixel_clip_rectangle
[22:07:24] [PASSED] well_known_colors
[22:07:24] [PASSED] destination_pitch
[22:07:24] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[22:07:24] ================= drm_test_fb_clip_offset  =================
[22:07:24] [PASSED] pass through
[22:07:24] [PASSED] horizontal offset
[22:07:24] [PASSED] vertical offset
[22:07:24] [PASSED] horizontal and vertical offset
[22:07:24] [PASSED] horizontal offset (custom pitch)
[22:07:24] [PASSED] vertical offset (custom pitch)
[22:07:24] [PASSED] horizontal and vertical offset (custom pitch)
[22:07:24] ============= [PASSED] drm_test_fb_clip_offset =============
[22:07:24] =================== drm_test_fb_memcpy  ====================
[22:07:24] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[22:07:24] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[22:07:24] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[22:07:24] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[22:07:24] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[22:07:24] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[22:07:24] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[22:07:24] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[22:07:24] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[22:07:24] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[22:07:24] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[22:07:24] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[22:07:24] =============== [PASSED] drm_test_fb_memcpy ================
[22:07:24] ============= [PASSED] drm_format_helper_test ==============
[22:07:24] ================= drm_format (18 subtests) =================
[22:07:24] [PASSED] drm_test_format_block_width_invalid
[22:07:24] [PASSED] drm_test_format_block_width_one_plane
[22:07:24] [PASSED] drm_test_format_block_width_two_plane
[22:07:24] [PASSED] drm_test_format_block_width_three_plane
[22:07:24] [PASSED] drm_test_format_block_width_tiled
[22:07:24] [PASSED] drm_test_format_block_height_invalid
[22:07:24] [PASSED] drm_test_format_block_height_one_plane
[22:07:24] [PASSED] drm_test_format_block_height_two_plane
[22:07:24] [PASSED] drm_test_format_block_height_three_plane
[22:07:24] [PASSED] drm_test_format_block_height_tiled
[22:07:24] [PASSED] drm_test_format_min_pitch_invalid
[22:07:24] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[22:07:24] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[22:07:24] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[22:07:24] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[22:07:24] [PASSED] drm_test_format_min_pitch_two_plane
[22:07:24] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[22:07:24] [PASSED] drm_test_format_min_pitch_tiled
[22:07:24] =================== [PASSED] drm_format ====================
[22:07:24] ============== drm_framebuffer (10 subtests) ===============
[22:07:24] ========== drm_test_framebuffer_check_src_coords  ==========
[22:07:24] [PASSED] Success: source fits into fb
[22:07:24] [PASSED] Fail: overflowing fb with x-axis coordinate
[22:07:24] [PASSED] Fail: overflowing fb with y-axis coordinate
[22:07:24] [PASSED] Fail: overflowing fb with source width
[22:07:24] [PASSED] Fail: overflowing fb with source height
[22:07:24] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[22:07:24] [PASSED] drm_test_framebuffer_cleanup
[22:07:24] =============== drm_test_framebuffer_create  ===============
[22:07:24] [PASSED] ABGR8888 normal sizes
[22:07:24] [PASSED] ABGR8888 max sizes
[22:07:24] [PASSED] ABGR8888 pitch greater than min required
[22:07:24] [PASSED] ABGR8888 pitch less than min required
[22:07:24] [PASSED] ABGR8888 Invalid width
[22:07:24] [PASSED] ABGR8888 Invalid buffer handle
[22:07:24] [PASSED] No pixel format
[22:07:24] [PASSED] ABGR8888 Width 0
[22:07:24] [PASSED] ABGR8888 Height 0
[22:07:24] [PASSED] ABGR8888 Out of bound height * pitch combination
[22:07:24] [PASSED] ABGR8888 Large buffer offset
[22:07:24] [PASSED] ABGR8888 Buffer offset for inexistent plane
[22:07:24] [PASSED] ABGR8888 Invalid flag
[22:07:24] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[22:07:24] [PASSED] ABGR8888 Valid buffer modifier
[22:07:24] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[22:07:24] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] NV12 Normal sizes
[22:07:24] [PASSED] NV12 Max sizes
[22:07:24] [PASSED] NV12 Invalid pitch
[22:07:24] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[22:07:24] [PASSED] NV12 different  modifier per-plane
[22:07:24] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[22:07:24] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] NV12 Modifier for inexistent plane
[22:07:24] [PASSED] NV12 Handle for inexistent plane
[22:07:24] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[22:07:24] [PASSED] YVU420 Normal sizes
[22:07:24] [PASSED] YVU420 Max sizes
[22:07:24] [PASSED] YVU420 Invalid pitch
[22:07:24] [PASSED] YVU420 Different pitches
[22:07:24] [PASSED] YVU420 Different buffer offsets/pitches
[22:07:24] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[22:07:24] [PASSED] YVU420 Valid modifier
[22:07:24] [PASSED] YVU420 Different modifiers per plane
[22:07:24] [PASSED] YVU420 Modifier for inexistent plane
[22:07:24] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[22:07:24] [PASSED] X0L2 Normal sizes
[22:07:24] [PASSED] X0L2 Max sizes
[22:07:24] [PASSED] X0L2 Invalid pitch
[22:07:24] [PASSED] X0L2 Pitch greater than minimum required
[22:07:24] [PASSED] X0L2 Handle for inexistent plane
[22:07:24] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[22:07:24] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[22:07:24] [PASSED] X0L2 Valid modifier
[22:07:24] [PASSED] X0L2 Modifier for inexistent plane
[22:07:24] =========== [PASSED] drm_test_framebuffer_create ===========
[22:07:24] [PASSED] drm_test_framebuffer_free
[22:07:24] [PASSED] drm_test_framebuffer_init
[22:07:24] [PASSED] drm_test_framebuffer_init_bad_format
[22:07:24] [PASSED] drm_test_framebuffer_init_dev_mismatch
[22:07:24] [PASSED] drm_test_framebuffer_lookup
[22:07:24] [PASSED] drm_test_framebuffer_lookup_inexistent
[22:07:24] [PASSED] drm_test_framebuffer_modifiers_not_supported
[22:07:24] ================= [PASSED] drm_framebuffer =================
[22:07:24] ================ drm_gem_shmem (8 subtests) ================
[22:07:24] [PASSED] drm_gem_shmem_test_obj_create
[22:07:24] [PASSED] drm_gem_shmem_test_obj_create_private
[22:07:24] [PASSED] drm_gem_shmem_test_pin_pages
[22:07:24] [PASSED] drm_gem_shmem_test_vmap
[22:07:24] [PASSED] drm_gem_shmem_test_get_sg_table
[22:07:24] [PASSED] drm_gem_shmem_test_get_pages_sgt
[22:07:24] [PASSED] drm_gem_shmem_test_madvise
[22:07:24] [PASSED] drm_gem_shmem_test_purge
[22:07:24] ================== [PASSED] drm_gem_shmem ==================
[22:07:24] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[22:07:24] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[22:07:24] [PASSED] Automatic
[22:07:24] [PASSED] Full
[22:07:24] [PASSED] Limited 16:235
[22:07:24] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[22:07:24] [PASSED] drm_test_check_disable_connector
[22:07:24] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[22:07:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[22:07:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[22:07:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[22:07:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[22:07:24] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[22:07:24] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[22:07:24] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[22:07:24] [PASSED] drm_test_check_output_bpc_dvi
[22:07:24] [PASSED] drm_test_check_output_bpc_format_vic_1
[22:07:24] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[22:07:24] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[22:07:24] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[22:07:24] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[22:07:24] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[22:07:24] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[22:07:24] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[22:07:24] ============ drm_test_check_hdmi_color_format  =============
[22:07:24] [PASSED] AUTO -> RGB
[22:07:24] [PASSED] YCBCR422 -> YUV422
[22:07:24] [PASSED] YCBCR420 -> YUV420
[22:07:24] [PASSED] YCBCR444 -> YUV444
[22:07:24] [PASSED] RGB -> RGB
[22:07:24] ======== [PASSED] drm_test_check_hdmi_color_format =========
[22:07:24] ======== drm_test_check_hdmi_color_format_420_only  ========
[22:07:24] [PASSED] RGB should fail
[22:07:24] [PASSED] YUV444 should fail
[22:07:24] [PASSED] YUV422 should fail
[22:07:24] [PASSED] YUV420 should work
[22:07:24] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[22:07:24] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[22:07:24] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[22:07:24] [PASSED] drm_test_check_broadcast_rgb_value
[22:07:24] [PASSED] drm_test_check_bpc_8_value
[22:07:24] [PASSED] drm_test_check_bpc_10_value
[22:07:24] [PASSED] drm_test_check_bpc_12_value
[22:07:24] [PASSED] drm_test_check_format_value
[22:07:24] [PASSED] drm_test_check_tmds_char_value
[22:07:24] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[22:07:24] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[22:07:24] [PASSED] drm_test_check_mode_valid
[22:07:24] [PASSED] drm_test_check_mode_valid_reject
[22:07:24] [PASSED] drm_test_check_mode_valid_reject_rate
[22:07:24] [PASSED] drm_test_check_mode_valid_reject_max_clock
[22:07:24] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[22:07:24] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[22:07:24] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[22:07:24] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[22:07:24] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[22:07:24] [PASSED] drm_test_check_infoframes
[22:07:24] [PASSED] drm_test_check_reject_avi_infoframe
[22:07:24] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[22:07:24] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[22:07:24] [PASSED] drm_test_check_reject_audio_infoframe
[22:07:24] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[22:07:24] ================= drm_managed (2 subtests) =================
[22:07:24] [PASSED] drm_test_managed_release_action
[22:07:24] [PASSED] drm_test_managed_run_action
[22:07:24] =================== [PASSED] drm_managed ===================
[22:07:24] =================== drm_mm (6 subtests) ====================
[22:07:24] [PASSED] drm_test_mm_init
[22:07:24] [PASSED] drm_test_mm_debug
[22:07:24] [PASSED] drm_test_mm_align32
[22:07:24] [PASSED] drm_test_mm_align64
[22:07:24] [PASSED] drm_test_mm_lowest
[22:07:24] [PASSED] drm_test_mm_highest
[22:07:24] ===================== [PASSED] drm_mm ======================
[22:07:24] ============= drm_modes_analog_tv (5 subtests) =============
[22:07:24] [PASSED] drm_test_modes_analog_tv_mono_576i
[22:07:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[22:07:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[22:07:24] [PASSED] drm_test_modes_analog_tv_pal_576i
[22:07:24] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[22:07:24] =============== [PASSED] drm_modes_analog_tv ===============
[22:07:24] ============== drm_plane_helper (2 subtests) ===============
[22:07:24] =============== drm_test_check_plane_state  ================
[22:07:24] [PASSED] clipping_simple
[22:07:24] [PASSED] clipping_rotate_reflect
[22:07:24] [PASSED] positioning_simple
[22:07:24] [PASSED] upscaling
[22:07:24] [PASSED] downscaling
[22:07:24] [PASSED] rounding1
[22:07:24] [PASSED] rounding2
[22:07:24] [PASSED] rounding3
[22:07:24] [PASSED] rounding4
[22:07:24] =========== [PASSED] drm_test_check_plane_state ============
[22:07:24] =========== drm_test_check_invalid_plane_state  ============
[22:07:24] [PASSED] positioning_invalid
[22:07:24] [PASSED] upscaling_invalid
[22:07:24] [PASSED] downscaling_invalid
[22:07:24] ======= [PASSED] drm_test_check_invalid_plane_state ========
[22:07:24] ================ [PASSED] drm_plane_helper =================
[22:07:24] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[22:07:24] ====== drm_test_connector_helper_tv_get_modes_check  =======
[22:07:24] [PASSED] None
[22:07:24] [PASSED] PAL
[22:07:24] [PASSED] NTSC
[22:07:24] [PASSED] Both, NTSC Default
[22:07:24] [PASSED] Both, PAL Default
[22:07:24] [PASSED] Both, NTSC Default, with PAL on command-line
[22:07:24] [PASSED] Both, PAL Default, with NTSC on command-line
[22:07:24] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[22:07:24] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[22:07:24] ================== drm_rect (9 subtests) ===================
[22:07:24] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[22:07:24] [PASSED] drm_test_rect_clip_scaled_not_clipped
[22:07:24] [PASSED] drm_test_rect_clip_scaled_clipped
[22:07:24] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[22:07:24] ================= drm_test_rect_intersect  =================
[22:07:24] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[22:07:24] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[22:07:24] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[22:07:24] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[22:07:24] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[22:07:24] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[22:07:24] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[22:07:24] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[22:07:24] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[22:07:24] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[22:07:24] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[22:07:24] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[22:07:24] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[22:07:24] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[22:07:24] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[22:07:24] ============= [PASSED] drm_test_rect_intersect =============
[22:07:24] ================ drm_test_rect_calc_hscale  ================
[22:07:24] [PASSED] normal use
[22:07:24] [PASSED] out of max range
[22:07:24] [PASSED] out of min range
[22:07:24] [PASSED] zero dst
[22:07:24] [PASSED] negative src
[22:07:24] [PASSED] negative dst
[22:07:24] ============ [PASSED] drm_test_rect_calc_hscale ============
[22:07:24] ================ drm_test_rect_calc_vscale  ================
[22:07:24] [PASSED] normal use
[22:07:24] [PASSED] out of max range
[22:07:24] [PASSED] out of min range
[22:07:24] [PASSED] zero dst
[22:07:24] [PASSED] negative src
[22:07:24] [PASSED] negative dst
[22:07:24] ============ [PASSED] drm_test_rect_calc_vscale ============
[22:07:24] ================== drm_test_rect_rotate  ===================
[22:07:24] [PASSED] reflect-x
[22:07:24] [PASSED] reflect-y
[22:07:24] [PASSED] rotate-0
[22:07:24] [PASSED] rotate-90
[22:07:24] [PASSED] rotate-180
[22:07:24] [PASSED] rotate-270
[22:07:24] ============== [PASSED] drm_test_rect_rotate ===============
[22:07:24] ================ drm_test_rect_rotate_inv  =================
[22:07:24] [PASSED] reflect-x
[22:07:24] [PASSED] reflect-y
[22:07:24] [PASSED] rotate-0
[22:07:24] [PASSED] rotate-90
[22:07:24] [PASSED] rotate-180
[22:07:24] [PASSED] rotate-270
[22:07:24] ============ [PASSED] drm_test_rect_rotate_inv =============
[22:07:24] ==================== [PASSED] drm_rect =====================
[22:07:24] ============ drm_sysfb_modeset_test (1 subtest) ============
[22:07:24] ============ drm_test_sysfb_build_fourcc_list  =============
[22:07:24] [PASSED] no native formats
[22:07:24] [PASSED] XRGB8888 as native format
[22:07:24] [PASSED] remove duplicates
[22:07:24] [PASSED] convert alpha formats
[22:07:24] [PASSED] random formats
[22:07:24] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[22:07:24] ============= [PASSED] drm_sysfb_modeset_test ==============
[22:07:24] ================== drm_fixp (2 subtests) ===================
[22:07:24] [PASSED] drm_test_int2fixp
[22:07:24] [PASSED] drm_test_sm2fixp
[22:07:24] ==================== [PASSED] drm_fixp =====================
[22:07:24] ============================================================
[22:07:24] Testing complete. Ran 639 tests: passed: 639
[22:07:24] Elapsed time: 26.225s total, 1.837s configuring, 24.218s building, 0.155s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[22:07:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:07:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:07:35] Starting KUnit Kernel (1/1)...
[22:07:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:07:35] ================= ttm_device (5 subtests) ==================
[22:07:35] [PASSED] ttm_device_init_basic
[22:07:35] [PASSED] ttm_device_init_multiple
[22:07:35] [PASSED] ttm_device_fini_basic
[22:07:35] [PASSED] ttm_device_init_no_vma_man
[22:07:35] ================== ttm_device_init_pools  ==================
[22:07:35] [PASSED] No DMA allocations, no DMA32 required
[22:07:35] [PASSED] DMA allocations, DMA32 required
[22:07:35] [PASSED] No DMA allocations, DMA32 required
[22:07:35] [PASSED] DMA allocations, no DMA32 required
[22:07:35] ============== [PASSED] ttm_device_init_pools ==============
[22:07:35] =================== [PASSED] ttm_device ====================
[22:07:35] ================== ttm_pool (8 subtests) ===================
[22:07:35] ================== ttm_pool_alloc_basic  ===================
[22:07:35] [PASSED] One page
[22:07:35] [PASSED] More than one page
[22:07:35] [PASSED] Above the allocation limit
[22:07:35] [PASSED] One page, with coherent DMA mappings enabled
[22:07:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:07:35] ============== [PASSED] ttm_pool_alloc_basic ===============
[22:07:35] ============== ttm_pool_alloc_basic_dma_addr  ==============
[22:07:35] [PASSED] One page
[22:07:35] [PASSED] More than one page
[22:07:35] [PASSED] Above the allocation limit
[22:07:35] [PASSED] One page, with coherent DMA mappings enabled
[22:07:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:07:35] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[22:07:35] [PASSED] ttm_pool_alloc_order_caching_match
[22:07:35] [PASSED] ttm_pool_alloc_caching_mismatch
[22:07:35] [PASSED] ttm_pool_alloc_order_mismatch
[22:07:35] [PASSED] ttm_pool_free_dma_alloc
[22:07:35] [PASSED] ttm_pool_free_no_dma_alloc
[22:07:35] [PASSED] ttm_pool_fini_basic
[22:07:35] ==================== [PASSED] ttm_pool =====================
[22:07:35] ================ ttm_resource (8 subtests) =================
[22:07:35] ================= ttm_resource_init_basic  =================
[22:07:35] [PASSED] Init resource in TTM_PL_SYSTEM
[22:07:35] [PASSED] Init resource in TTM_PL_VRAM
[22:07:35] [PASSED] Init resource in a private placement
[22:07:35] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[22:07:35] ============= [PASSED] ttm_resource_init_basic =============
[22:07:35] [PASSED] ttm_resource_init_pinned
[22:07:35] [PASSED] ttm_resource_fini_basic
[22:07:35] [PASSED] ttm_resource_manager_init_basic
[22:07:35] [PASSED] ttm_resource_manager_usage_basic
[22:07:35] [PASSED] ttm_resource_manager_set_used_basic
[22:07:35] [PASSED] ttm_sys_man_alloc_basic
[22:07:35] [PASSED] ttm_sys_man_free_basic
[22:07:35] ================== [PASSED] ttm_resource ===================
[22:07:35] =================== ttm_tt (15 subtests) ===================
[22:07:35] ==================== ttm_tt_init_basic  ====================
[22:07:35] [PASSED] Page-aligned size
[22:07:35] [PASSED] Extra pages requested
[22:07:35] ================ [PASSED] ttm_tt_init_basic ================
[22:07:35] [PASSED] ttm_tt_init_misaligned
[22:07:35] [PASSED] ttm_tt_fini_basic
[22:07:35] [PASSED] ttm_tt_fini_sg
[22:07:35] [PASSED] ttm_tt_fini_shmem
[22:07:35] [PASSED] ttm_tt_create_basic
[22:07:35] [PASSED] ttm_tt_create_invalid_bo_type
[22:07:35] [PASSED] ttm_tt_create_ttm_exists
[22:07:35] [PASSED] ttm_tt_create_failed
[22:07:35] [PASSED] ttm_tt_destroy_basic
[22:07:35] [PASSED] ttm_tt_populate_null_ttm
[22:07:35] [PASSED] ttm_tt_populate_populated_ttm
[22:07:35] [PASSED] ttm_tt_unpopulate_basic
[22:07:35] [PASSED] ttm_tt_unpopulate_empty_ttm
[22:07:35] [PASSED] ttm_tt_swapin_basic
[22:07:35] ===================== [PASSED] ttm_tt ======================
[22:07:35] =================== ttm_bo (14 subtests) ===================
[22:07:35] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[22:07:35] [PASSED] Cannot be interrupted and sleeps
[22:07:35] [PASSED] Cannot be interrupted, locks straight away
[22:07:35] [PASSED] Can be interrupted, sleeps
[22:07:35] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[22:07:35] [PASSED] ttm_bo_reserve_locked_no_sleep
[22:07:35] [PASSED] ttm_bo_reserve_no_wait_ticket
[22:07:35] [PASSED] ttm_bo_reserve_double_resv
[22:07:35] [PASSED] ttm_bo_reserve_interrupted
[22:07:35] [PASSED] ttm_bo_reserve_deadlock
[22:07:35] [PASSED] ttm_bo_unreserve_basic
[22:07:35] [PASSED] ttm_bo_unreserve_pinned
[22:07:35] [PASSED] ttm_bo_unreserve_bulk
[22:07:35] [PASSED] ttm_bo_fini_basic
[22:07:35] [PASSED] ttm_bo_fini_shared_resv
[22:07:35] [PASSED] ttm_bo_pin_basic
[22:07:35] [PASSED] ttm_bo_pin_unpin_resource
[22:07:35] [PASSED] ttm_bo_multiple_pin_one_unpin
[22:07:35] ===================== [PASSED] ttm_bo ======================
[22:07:35] ============== ttm_bo_validate (22 subtests) ===============
[22:07:35] ============== ttm_bo_init_reserved_sys_man  ===============
[22:07:35] [PASSED] Buffer object for userspace
[22:07:35] [PASSED] Kernel buffer object
[22:07:35] [PASSED] Shared buffer object
[22:07:35] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[22:07:35] ============== ttm_bo_init_reserved_mock_man  ==============
[22:07:35] [PASSED] Buffer object for userspace
[22:07:35] [PASSED] Kernel buffer object
[22:07:35] [PASSED] Shared buffer object
[22:07:35] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[22:07:35] [PASSED] ttm_bo_init_reserved_resv
[22:07:35] ================== ttm_bo_validate_basic  ==================
[22:07:35] [PASSED] Buffer object for userspace
[22:07:35] [PASSED] Kernel buffer object
[22:07:35] [PASSED] Shared buffer object
[22:07:35] ============== [PASSED] ttm_bo_validate_basic ==============
[22:07:35] [PASSED] ttm_bo_validate_invalid_placement
[22:07:35] ============= ttm_bo_validate_same_placement  ==============
[22:07:35] [PASSED] System manager
[22:07:35] [PASSED] VRAM manager
[22:07:35] ========= [PASSED] ttm_bo_validate_same_placement ==========
[22:07:35] [PASSED] ttm_bo_validate_failed_alloc
[22:07:35] [PASSED] ttm_bo_validate_pinned
[22:07:35] [PASSED] ttm_bo_validate_busy_placement
[22:07:35] ================ ttm_bo_validate_multihop  =================
[22:07:35] [PASSED] Buffer object for userspace
[22:07:35] [PASSED] Kernel buffer object
[22:07:35] [PASSED] Shared buffer object
[22:07:35] ============ [PASSED] ttm_bo_validate_multihop =============
[22:07:35] ========== ttm_bo_validate_no_placement_signaled  ==========
[22:07:35] [PASSED] Buffer object in system domain, no page vector
[22:07:35] [PASSED] Buffer object in system domain with an existing page vector
[22:07:35] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[22:07:35] ======== ttm_bo_validate_no_placement_not_signaled  ========
[22:07:35] [PASSED] Buffer object for userspace
[22:07:35] [PASSED] Kernel buffer object
[22:07:35] [PASSED] Shared buffer object
[22:07:35] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[22:07:35] [PASSED] ttm_bo_validate_move_fence_signaled
[22:07:36] ========= ttm_bo_validate_move_fence_not_signaled  =========
[22:07:36] [PASSED] Waits for GPU
[22:07:36] [PASSED] Tries to lock straight away
[22:07:36] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[22:07:36] [PASSED] ttm_bo_validate_swapout
[22:07:36] [PASSED] ttm_bo_validate_happy_evict
[22:07:36] [PASSED] ttm_bo_validate_all_pinned_evict
[22:07:36] [PASSED] ttm_bo_validate_allowed_only_evict
[22:07:36] [PASSED] ttm_bo_validate_deleted_evict
[22:07:36] [PASSED] ttm_bo_validate_busy_domain_evict
[22:07:36] [PASSED] ttm_bo_validate_evict_gutting
[22:07:36] [PASSED] ttm_bo_validate_recrusive_evict
[22:07:36] ================= [PASSED] ttm_bo_validate =================
[22:07:36] ============================================================
[22:07:36] Testing complete. Ran 102 tests: passed: 102
[22:07:36] Elapsed time: 11.598s total, 1.741s configuring, 9.593s building, 0.224s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable per exec queue MSI-X vector assignment (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 875 bytes --]

== Series Details ==

Series: Enable per exec queue MSI-X vector assignment (rev2)
URL   : https://patchwork.freedesktop.org/series/167990/
State : success

== Summary ==

CI Bug Log - changes from xe-5234-10db0c83b0ccc3211990b54235475abb9d383851_BAT -> xe-pw-167990v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-5234-10db0c83b0ccc3211990b54235475abb9d383851 -> xe-pw-167990v2

  IGT_8958: 8958
  xe-5234-10db0c83b0ccc3211990b54235475abb9d383851: 10db0c83b0ccc3211990b54235475abb9d383851
  xe-pw-167990v2: 167990v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/index.html

[-- Attachment #2: Type: text/html, Size: 1423 bytes --]

Re: [PATCH 00/11] Enable per exec queue MSI-X vector assignment

[Matthew Brost]

On Wed, Jun 10, 2026 at 09:28:32PM +0000, Stuart Summers wrote:
> This series adds support for per exec queue MSI-X vector
> assignment as well as a per exec queue wait queue in the

There’s another improvement we should consider once we have MSIX per
queue: assigning a unique xe_hw_fence_irq to each queue with a valid
MSIX vector. In the MSIX IRQ handler, we could map from the vector to q
and only trigger that queue’s xe_hw_fence_irq.

This should reduce IRQ overhead, as we would walk the individual queue’s
list of pending jobs/fences rather than all pending jobs/fences within
an engine class. We could also introduce a variant of
hw_fence_irq_run_cb for MSIX that immediately bails when it encounters
an unsignaled fence, since the list in xe_hw_fence_irq would now signal
in order.

This can be done as a follow-up, but it should provide a significant win
in certain cases.

Matt

> wait user fence ioctl. MSI-X vectors are dynamically assigned
> during exec queue creation up to a set maximum. Once the max
> is reached, everything else falls back to the default vector.

> 
> These dynamic vectors allow us to wake up a targeted wait
> queue and user thread instead of broadcasting out to all
> potential user threads like we're doing today. This is interesting
> when we have many user threads outstanding as we don't want
> to wake them up in a storm for each interrupt coming in.
> 
> Additionally, there have been changes in the memirq code lately
> to isolate some of the interrupts handled here. Starting with
> xe3p, however, we have new interrupts available for compute walker
> post sync interrupts. Currently these are enabled for legacy MSI
> use cases, but the bits are also available for MSI-X. Enable
> those bits here.
> 
> v2: Drop the drm_dbg change patch
>     Directly call xe_hw_engine_handle_irq() from xe_memirq_hwe_handler()
>     Only add to ufence_list for user queues
> 
> Stuart Summers (11):
>   drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl()
>   drm/xe: Handle NULL in xe_exec_queue_get_unless_zero()
>   drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS
>   drm/xe: Assign dedicated MSI-X vectors to exec queues
>   drm/xe: Add configfs max_msix_vecs attribute
>   drm/xe: Remove memirq status and source checks for engine interrupts
>   drm/xe: Add per-exec-queue user fence wait queue
>   drm/xe: Track all exec queues in a device-level ufence list
>   drm/xe: Hook up per queue thread wake to the unique MSI-X vector
>     allocation
>   drm/xe: Enable per-queue ufence wake in ioctl and wake function
>   drm/xe/memirq: Enable compute walker post-sync interrupt
> 
>  drivers/gpu/drm/xe/regs/xe_lrc_layout.h  |  3 +
>  drivers/gpu/drm/xe/xe_configfs.c         | 71 ++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_configfs.h         |  6 ++
>  drivers/gpu/drm/xe/xe_device.c           |  2 +
>  drivers/gpu/drm/xe/xe_device_types.h     | 11 ++++
>  drivers/gpu/drm/xe/xe_exec_queue.c       | 51 ++++++++++++++++-
>  drivers/gpu/drm/xe/xe_exec_queue.h       |  2 +-
>  drivers/gpu/drm/xe/xe_exec_queue_types.h |  6 ++
>  drivers/gpu/drm/xe/xe_guc_submit.c       |  6 +-
>  drivers/gpu/drm/xe/xe_hw_engine.c        |  6 +-
>  drivers/gpu/drm/xe/xe_hw_engine.h        |  3 +-
>  drivers/gpu/drm/xe/xe_irq.c              | 36 ++++++++++--
>  drivers/gpu/drm/xe/xe_irq.h              |  9 +++
>  drivers/gpu/drm/xe/xe_lrc.c              | 15 ++++-
>  drivers/gpu/drm/xe/xe_memirq.c           | 59 +++++++++-----------
>  drivers/gpu/drm/xe/xe_memirq.h           |  4 +-
>  drivers/gpu/drm/xe/xe_sync.c             |  3 +-
>  drivers/gpu/drm/xe/xe_wait_user_fence.c  | 64 ++++++++++++++++++++-
>  drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++
>  19 files changed, 310 insertions(+), 51 deletions(-)
> 
> -- 
> 2.43.0
> 

Re: [PATCH 00/11] Enable per exec queue MSI-X vector assignment

[Summers, Stuart]

On Wed, 2026-06-10 at 16:51 -0700, Matthew Brost wrote:
> On Wed, Jun 10, 2026 at 09:28:32PM +0000, Stuart Summers wrote:
> > This series adds support for per exec queue MSI-X vector
> > assignment as well as a per exec queue wait queue in the
> 
> There’s another improvement we should consider once we have MSIX per
> queue: assigning a unique xe_hw_fence_irq to each queue with a valid
> MSIX vector. In the MSIX IRQ handler, we could map from the vector to
> q
> and only trigger that queue’s xe_hw_fence_irq.
> 
> This should reduce IRQ overhead, as we would walk the individual
> queue’s
> list of pending jobs/fences rather than all pending jobs/fences
> within
> an engine class. We could also introduce a variant of
> hw_fence_irq_run_cb for MSIX that immediately bails when it
> encounters
> an unsignaled fence, since the list in xe_hw_fence_irq would now
> signal
> in order.
> 
> This can be done as a follow-up, but it should provide a significant
> win
> in certain cases.

So I was trying to limit in this first version to compute use cases,
but maybe you're right we should go ahead and include this for the non-
lr cases. I'll also review the sync case you mentioned I think in that
other comment.

I guess I'd rather keep all of that in this one series. On the one
hand, I do want to get some of these changes in sooner than later so we
have this use case aligned with a lot of the SRIOV related changes
going in here. But also, this isn't such a huge set of changes that it
should have that much of an impact. I'll take a look and get back if it
seems like something that should get split.

Thanks!
Stuart

> 
> Matt
> 
> > wait user fence ioctl. MSI-X vectors are dynamically assigned
> > during exec queue creation up to a set maximum. Once the max
> > is reached, everything else falls back to the default vector.
> 
> > 
> > These dynamic vectors allow us to wake up a targeted wait
> > queue and user thread instead of broadcasting out to all
> > potential user threads like we're doing today. This is interesting
> > when we have many user threads outstanding as we don't want
> > to wake them up in a storm for each interrupt coming in.
> > 
> > Additionally, there have been changes in the memirq code lately
> > to isolate some of the interrupts handled here. Starting with
> > xe3p, however, we have new interrupts available for compute walker
> > post sync interrupts. Currently these are enabled for legacy MSI
> > use cases, but the bits are also available for MSI-X. Enable
> > those bits here.
> > 
> > v2: Drop the drm_dbg change patch
> >     Directly call xe_hw_engine_handle_irq() from
> > xe_memirq_hwe_handler()
> >     Only add to ufence_list for user queues
> > 
> > Stuart Summers (11):
> >   drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl()
> >   drm/xe: Handle NULL in xe_exec_queue_get_unless_zero()
> >   drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS
> >   drm/xe: Assign dedicated MSI-X vectors to exec queues
> >   drm/xe: Add configfs max_msix_vecs attribute
> >   drm/xe: Remove memirq status and source checks for engine
> > interrupts
> >   drm/xe: Add per-exec-queue user fence wait queue
> >   drm/xe: Track all exec queues in a device-level ufence list
> >   drm/xe: Hook up per queue thread wake to the unique MSI-X vector
> >     allocation
> >   drm/xe: Enable per-queue ufence wake in ioctl and wake function
> >   drm/xe/memirq: Enable compute walker post-sync interrupt
> > 
> >  drivers/gpu/drm/xe/regs/xe_lrc_layout.h  |  3 +
> >  drivers/gpu/drm/xe/xe_configfs.c         | 71
> > ++++++++++++++++++++++++
> >  drivers/gpu/drm/xe/xe_configfs.h         |  6 ++
> >  drivers/gpu/drm/xe/xe_device.c           |  2 +
> >  drivers/gpu/drm/xe/xe_device_types.h     | 11 ++++
> >  drivers/gpu/drm/xe/xe_exec_queue.c       | 51 ++++++++++++++++-
> >  drivers/gpu/drm/xe/xe_exec_queue.h       |  2 +-
> >  drivers/gpu/drm/xe/xe_exec_queue_types.h |  6 ++
> >  drivers/gpu/drm/xe/xe_guc_submit.c       |  6 +-
> >  drivers/gpu/drm/xe/xe_hw_engine.c        |  6 +-
> >  drivers/gpu/drm/xe/xe_hw_engine.h        |  3 +-
> >  drivers/gpu/drm/xe/xe_irq.c              | 36 ++++++++++--
> >  drivers/gpu/drm/xe/xe_irq.h              |  9 +++
> >  drivers/gpu/drm/xe/xe_lrc.c              | 15 ++++-
> >  drivers/gpu/drm/xe/xe_memirq.c           | 59 +++++++++-----------
> >  drivers/gpu/drm/xe/xe_memirq.h           |  4 +-
> >  drivers/gpu/drm/xe/xe_sync.c             |  3 +-
> >  drivers/gpu/drm/xe/xe_wait_user_fence.c  | 64
> > ++++++++++++++++++++-
> >  drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++
> >  19 files changed, 310 insertions(+), 51 deletions(-)
> > 
> > -- 
> > 2.43.0
> > 

Re: [PATCH 00/11] Enable per exec queue MSI-X vector assignment

[Matthew Brost]

On Thu, Jun 11, 2026 at 05:08:07PM -0600, Summers, Stuart wrote:
> On Wed, 2026-06-10 at 16:51 -0700, Matthew Brost wrote:
> > On Wed, Jun 10, 2026 at 09:28:32PM +0000, Stuart Summers wrote:
> > > This series adds support for per exec queue MSI-X vector
> > > assignment as well as a per exec queue wait queue in the
> > 
> > There’s another improvement we should consider once we have MSIX per
> > queue: assigning a unique xe_hw_fence_irq to each queue with a valid
> > MSIX vector. In the MSIX IRQ handler, we could map from the vector to
> > q
> > and only trigger that queue’s xe_hw_fence_irq.
> > 
> > This should reduce IRQ overhead, as we would walk the individual
> > queue’s
> > list of pending jobs/fences rather than all pending jobs/fences
> > within
> > an engine class. We could also introduce a variant of
> > hw_fence_irq_run_cb for MSIX that immediately bails when it
> > encounters
> > an unsignaled fence, since the list in xe_hw_fence_irq would now
> > signal
> > in order.
> > 
> > This can be done as a follow-up, but it should provide a significant
> > win
> > in certain cases.
> 
> So I was trying to limit in this first version to compute use cases,
> but maybe you're right we should go ahead and include this for the non-
> lr cases. I'll also review the sync case you mentioned I think in that

LR jobs are now tracked in IRQ handler to support VF migration - so this
suggestion applies to everything now.

> other comment.
> 
> I guess I'd rather keep all of that in this one series. On the one
> hand, I do want to get some of these changes in sooner than later so we
> have this use case aligned with a lot of the SRIOV related changes
> going in here. But also, this isn't such a huge set of changes that it
> should have that much of an impact. I'll take a look and get back if it
> seems like something that should get split.
> 

I'm fine either way as long as someone picks up this suggestion sooner
or later. I suspect my suggestion here will be an overall larger perf win than
this series and shouldn't too difficult to implement.

Matt

> Thanks!
> Stuart
> 
> > 
> > Matt
> > 
> > > wait user fence ioctl. MSI-X vectors are dynamically assigned
> > > during exec queue creation up to a set maximum. Once the max
> > > is reached, everything else falls back to the default vector.
> > 
> > > 
> > > These dynamic vectors allow us to wake up a targeted wait
> > > queue and user thread instead of broadcasting out to all
> > > potential user threads like we're doing today. This is interesting
> > > when we have many user threads outstanding as we don't want
> > > to wake them up in a storm for each interrupt coming in.
> > > 
> > > Additionally, there have been changes in the memirq code lately
> > > to isolate some of the interrupts handled here. Starting with
> > > xe3p, however, we have new interrupts available for compute walker
> > > post sync interrupts. Currently these are enabled for legacy MSI
> > > use cases, but the bits are also available for MSI-X. Enable
> > > those bits here.
> > > 
> > > v2: Drop the drm_dbg change patch
> > >     Directly call xe_hw_engine_handle_irq() from
> > > xe_memirq_hwe_handler()
> > >     Only add to ufence_list for user queues
> > > 
> > > Stuart Summers (11):
> > >   drm/xe: Add kerneldoc to xe_wait_user_fence_ioctl()
> > >   drm/xe: Handle NULL in xe_exec_queue_get_unless_zero()
> > >   drm/xe: Cap MSI-X vector count to XE_MSIX_MAX_VECS
> > >   drm/xe: Assign dedicated MSI-X vectors to exec queues
> > >   drm/xe: Add configfs max_msix_vecs attribute
> > >   drm/xe: Remove memirq status and source checks for engine
> > > interrupts
> > >   drm/xe: Add per-exec-queue user fence wait queue
> > >   drm/xe: Track all exec queues in a device-level ufence list
> > >   drm/xe: Hook up per queue thread wake to the unique MSI-X vector
> > >     allocation
> > >   drm/xe: Enable per-queue ufence wake in ioctl and wake function
> > >   drm/xe/memirq: Enable compute walker post-sync interrupt
> > > 
> > >  drivers/gpu/drm/xe/regs/xe_lrc_layout.h  |  3 +
> > >  drivers/gpu/drm/xe/xe_configfs.c         | 71
> > > ++++++++++++++++++++++++
> > >  drivers/gpu/drm/xe/xe_configfs.h         |  6 ++
> > >  drivers/gpu/drm/xe/xe_device.c           |  2 +
> > >  drivers/gpu/drm/xe/xe_device_types.h     | 11 ++++
> > >  drivers/gpu/drm/xe/xe_exec_queue.c       | 51 ++++++++++++++++-
> > >  drivers/gpu/drm/xe/xe_exec_queue.h       |  2 +-
> > >  drivers/gpu/drm/xe/xe_exec_queue_types.h |  6 ++
> > >  drivers/gpu/drm/xe/xe_guc_submit.c       |  6 +-
> > >  drivers/gpu/drm/xe/xe_hw_engine.c        |  6 +-
> > >  drivers/gpu/drm/xe/xe_hw_engine.h        |  3 +-
> > >  drivers/gpu/drm/xe/xe_irq.c              | 36 ++++++++++--
> > >  drivers/gpu/drm/xe/xe_irq.h              |  9 +++
> > >  drivers/gpu/drm/xe/xe_lrc.c              | 15 ++++-
> > >  drivers/gpu/drm/xe/xe_memirq.c           | 59 +++++++++-----------
> > >  drivers/gpu/drm/xe/xe_memirq.h           |  4 +-
> > >  drivers/gpu/drm/xe/xe_sync.c             |  3 +-
> > >  drivers/gpu/drm/xe/xe_wait_user_fence.c  | 64
> > > ++++++++++++++++++++-
> > >  drivers/gpu/drm/xe/xe_wait_user_fence.h  |  4 ++
> > >  19 files changed, 310 insertions(+), 51 deletions(-)
> > > 
> > > -- 
> > > 2.43.0
> > > 
> 

✓ Xe.CI.FULL: success for Enable per exec queue MSI-X vector assignment (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 18702 bytes --]

== Series Details ==

Series: Enable per exec queue MSI-X vector assignment (rev2)
URL   : https://patchwork.freedesktop.org/series/167990/
State : success

== Summary ==

CI Bug Log - changes from xe-5234-10db0c83b0ccc3211990b54235475abb9d383851_FULL -> xe-pw-167990v2_FULL
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-167990v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-bmg:          NOTRUN -> [SKIP][1] ([Intel XE#2327])
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-bmg:          NOTRUN -> [SKIP][2] ([Intel XE#7059] / [Intel XE#7085])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][3] ([Intel XE#1124]) +2 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-1-displays-target-1920x1080p:
    - shard-bmg:          NOTRUN -> [SKIP][4] ([Intel XE#367])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_bw@linear-tiling-1-displays-target-1920x1080p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][5] ([Intel XE#2887]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html

  * igt@kms_chamelium_color@ctm-0-75:
    - shard-bmg:          NOTRUN -> [SKIP][6] ([Intel XE#2325] / [Intel XE#7358])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_chamelium_color@ctm-0-75.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2252])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-bmg:          NOTRUN -> [SKIP][8] ([Intel XE#2390] / [Intel XE#6974])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_cursor_crc@cursor-rapid-movement-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][9] ([Intel XE#2320])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_cursor_crc@cursor-rapid-movement-64x21.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#8265])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [PASS][11] -> [FAIL][12] ([Intel XE#301]) +1 other test fail
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#7178] / [Intel XE#7351])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#2311]) +10 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_frontbuffer_tracking@drrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#4141]) +6 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#7061] / [Intel XE#7356])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][17] ([Intel XE#2313]) +11 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2350] / [Intel XE#7503])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [PASS][19] -> [SKIP][20] ([Intel XE#1503])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-10/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010:
    - shard-bmg:          [PASS][21] -> [SKIP][22] ([Intel XE#7922]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-bmg-6/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-10/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-3-xrgb2101010.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-bmg:          NOTRUN -> [SKIP][23] ([Intel XE#7283])
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#1489]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr@fbc-pr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][25] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_psr@fbc-pr-primary-blt.html

  * igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1:
    - shard-lnl:          [PASS][26] -> [FAIL][27] ([Intel XE#2142]) +1 other test fail
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-lnl-7/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-lnl-3/igt@kms_vrr@seamless-rr-switch-virtual@pipe-a-edp-1.html

  * igt@xe_eudebug@basic-read-event:
    - shard-bmg:          NOTRUN -> [SKIP][28] ([Intel XE#7636]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_eudebug@basic-read-event.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#2322] / [Intel XE#7372]) +2 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-basic.html

  * igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind:
    - shard-bmg:          NOTRUN -> [SKIP][30] ([Intel XE#7136]) +2 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_exec_fault_mode@many-execqueues-multi-queue-rebind.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#6874]) +5 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr.html

  * igt@xe_exec_reset@multi-queue-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][32] ([Intel XE#7866])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_exec_reset@multi-queue-close-fd.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge:
    - shard-bmg:          NOTRUN -> [ABORT][33] ([Intel XE#8007])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-8/igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#7138]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr.html

  * igt@xe_mmap@small-bar:
    - shard-bmg:          NOTRUN -> [SKIP][35] ([Intel XE#586] / [Intel XE#7323] / [Intel XE#7384])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_mmap@small-bar.html

  * igt@xe_multigpu_svm@mgpu-coherency-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#6964])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_multigpu_svm@mgpu-coherency-prefetch.html

  * igt@xe_peer2peer@read:
    - shard-bmg:          NOTRUN -> [SKIP][37] ([Intel XE#2427] / [Intel XE#6953] / [Intel XE#7326] / [Intel XE#7353])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_peer2peer@read.html

  * igt@xe_query@multigpu-query-invalid-query:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#944])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_query@multigpu-query-invalid-query.html

  * igt@xe_sriov_flr@flr-vfs-parallel:
    - shard-bmg:          NOTRUN -> [FAIL][39] ([Intel XE#6569])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_sriov_flr@flr-vfs-parallel.html

  
#### Possible fixes ####

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
    - shard-lnl:          [FAIL][40] ([Intel XE#301]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          [FAIL][42] ([Intel XE#301] / [Intel XE#3149]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-bmg:          [SKIP][44] ([Intel XE#7915]) -> [PASS][45] +1 other test pass
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-bmg-8/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-free-nomemset:
    - shard-bmg:          [INCOMPLETE][46] ([Intel XE#8159]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-bmg-3/igt@xe_exec_system_allocator@threads-shared-vm-many-free-nomemset.html
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-9/igt@xe_exec_system_allocator@threads-shared-vm-many-free-nomemset.html

  * igt@xe_wedged@wedged-mode-toggle:
    - shard-bmg:          [ABORT][48] ([Intel XE#8007]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-bmg-4/igt@xe_wedged@wedged-mode-toggle.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-8/igt@xe_wedged@wedged-mode-toggle.html

  
#### Warnings ####

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][50] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935]) -> [SKIP][51] ([Intel XE#309] / [Intel XE#7343])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-lnl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [FAIL][52] ([Intel XE#7809]) -> [FAIL][53] ([Intel XE#7571])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-bmg-1/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-bmg-10/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-lnl:          [FAIL][54] ([Intel XE#301] / [Intel XE#3149]) -> [FAIL][55] ([Intel XE#301])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5234-10db0c83b0ccc3211990b54235475abb9d383851/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#2142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2142
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2350
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/586
  [Intel XE#6569]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6569
  [Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
  [Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
  [Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7323
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7384]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7384
  [Intel XE#7503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7503
  [Intel XE#7571]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7571
  [Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
  [Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
  [Intel XE#7866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7866
  [Intel XE#7915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7915
  [Intel XE#7922]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7922
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8159
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-5234-10db0c83b0ccc3211990b54235475abb9d383851 -> xe-pw-167990v2

  IGT_8958: 8958
  xe-5234-10db0c83b0ccc3211990b54235475abb9d383851: 10db0c83b0ccc3211990b54235475abb9d383851
  xe-pw-167990v2: 167990v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-167990v2/index.html

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