[PATCH v3 00/12] Add CPER logging support for CRI

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* [PATCH v3 00/12] Add CPER logging support for CRI
@ 2026-09-06 17:26 Badal Nilawar
  2026-09-06 17:16 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev3) Patchwork
                   ` (15 more replies)
  0 siblings, 16 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

This patch series adds CPER (Common Platform Error Record) logging support
for Correctable errors reported by Intel Xe GPUs. CPER logging is done
through trace event.

v2:
   - Extended CPER logging to Uncorrectable errors and xe_ras_get_counter
     request
   - Log CPER records via xe_log SIGID infra 

v3:
  - Added the patches in incremental order (Raag)
  - Fixed Sashiko warnings which are applicable 


Badal Nilawar (12):
  drm/xe/cper: Hardware error CPER reporting from xe_log
  drm/xe/cper: Retrieve the error counter record for CPER reporting
  drm/xe/cper: Add Intel specific CPER structures
  drm/xe/cper: Prepare CPER record
  drm/xe/xe_ras: Add support to retrieve info queue data for CRI
  drm/xe/cper: Prepare Intel CPER error info records
  drm/xe/cper: Log CPER records for aggregate counter retrival
  drm/xe/xe_ras: Report device memory errors using SIGID
  drm/xe/xe_ras: Report core compute errors using SIGID
  drm/xe/xe_ras: Report soc internal errors using SIGID
  drm/xe/xe_ras: Report correctable errors using SIGID
  drm/xe/cper: Emit cper record to trace buf

 drivers/gpu/drm/xe/Makefile                   |   3 +
 drivers/gpu/drm/xe/regs/xe_regs.h             |   2 +
 drivers/gpu/drm/xe/xe_cper.c                  | 479 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_cper.h                  |  25 +
 drivers/gpu/drm/xe/xe_cper_types.h            | 179 +++++++
 drivers/gpu/drm/xe/xe_drm_ras_types.h         |   3 +
 drivers/gpu/drm/xe/xe_log.c                   |  17 +-
 drivers/gpu/drm/xe/xe_ras.c                   | 358 +++++++++++--
 drivers/gpu/drm/xe/xe_ras.h                   |   6 +
 drivers/gpu/drm/xe/xe_ras_types.h             | 118 ++++-
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
 drivers/gpu/drm/xe/xe_trace_cper.c            |   9 +
 drivers/gpu/drm/xe/xe_trace_cper.h            |  66 +++
 13 files changed, 1211 insertions(+), 56 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_cper.h
 create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h

-- 
2.54.0


^ permalink raw reply	[flat|nested] 45+ messages in thread

* ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev3)
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
@ 2026-09-06 17:16 ` Patchwork
  2026-09-06 17:18 ` ✓ CI.KUnit: success " Patchwork
                   ` (14 subsequent siblings)
  15 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2026-09-06 17:16 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

== Series Details ==

Series: Add CPER logging support for CRI (rev3)
URL   : https://patchwork.freedesktop.org/series/169692/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
d875049d2b299159a272bd5151994970cdcd1e31
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5ac20c0b0e45727c00a5c0e8fcc09c55c5cbdeb4
Author: Badal Nilawar <badal.nilawar@intel.com>
Date:   Sun Sep 6 22:56:17 2026 +0530

    drm/xe/cper: Emit cper record to trace buf
    
    Emit cper record to trace buf.
    
    Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
    Assisted-by: Copilot:claude-sonnet-4.6
+ /mt/dim checkpatch 496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f drm-intel
bf79b8f3ab1a drm/xe/cper: Hardware error CPER reporting from xe_log
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#29: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 109 lines checked
141cf31d41cf drm/xe/cper: Retrieve the error counter record for CPER reporting
6685b95e2ce3 drm/xe/cper: Add Intel specific CPER structures
-:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 179 lines checked
bd3880851758 drm/xe/cper: Prepare CPER record
4096a2db3bbe drm/xe/xe_ras: Add support to retrieve info queue data for CRI
89d810b31219 drm/xe/cper: Prepare Intel CPER error info records
0e31637f9e43 drm/xe/cper: Log CPER records for aggregate counter retrival
f41469d09c7c drm/xe/xe_ras: Report device memory errors using SIGID
dc85559f3d5a drm/xe/xe_ras: Report core compute errors using SIGID
8943930df833 drm/xe/xe_ras: Report soc internal errors using SIGID
89b4de15bcf2 drm/xe/xe_ras: Report correctable errors using SIGID
5ac20c0b0e45 drm/xe/cper: Emit cper record to trace buf
-:48: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:21:
+TRACE_EVENT(xe_error_cper,
+	TP_PROTO(struct xe_device *xe,

-:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#89: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:22:
+	TP_PROTO(struct xe_device *xe,
+	    const guid_t *platform_id, const guid_t *fru_id,

-:95: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#95: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:28:
+	TP_STRUCT__entry(

-:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#105: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:38:
+	TP_fast_assign(

-:120: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#120: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:53:
+		__print_hex(__entry->ihdr_raw,
+		    sizeof(struct xe_cper_sec_intel_err_hdr)),

-:123: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#123: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:56:
+		__print_hex(__get_dynamic_array(cper),
+		    __entry->cper_len))

-:131: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#131: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                              ^

-:131: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#131: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                 ^

-:131: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#131: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                         ^

-:131: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#131: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                             ^

-:131: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#131: FILE: drivers/gpu/drm/xe/xe_trace_cper.h:64:
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
                                                 ^

total: 0 errors, 1 warnings, 11 checks, 100 lines checked



^ permalink raw reply	[flat|nested] 45+ messages in thread

* ✓ CI.KUnit: success for Add CPER logging support for CRI (rev3)
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
  2026-09-06 17:16 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev3) Patchwork
@ 2026-09-06 17:18 ` Patchwork
  2026-09-06 17:26 ` [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log Badal Nilawar
                   ` (13 subsequent siblings)
  15 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2026-09-06 17:18 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

== Series Details ==

Series: Add CPER logging support for CRI (rev3)
URL   : https://patchwork.freedesktop.org/series/169692/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[17:16:06] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:10] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:16:31] Starting KUnit Kernel (1/1)...
[17:16:31] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:31] ============= refcount_interrupt (4 subtests) ==============
[17:16:31] [PASSED] test_single_irq_change
[17:16:31] [PASSED] test_nested_irq_change
[17:16:31] [PASSED] test_multiple_irq_change
[17:16:31] [PASSED] test_irq_save
[17:16:31] =============== [PASSED] refcount_interrupt ================
[17:16:31] ================= gpu_buddy (14 subtests) ==================
[17:16:31] [PASSED] gpu_test_buddy_alloc_limit
[17:16:31] [PASSED] gpu_test_buddy_alloc_optimistic
[17:16:31] [PASSED] gpu_test_buddy_alloc_pessimistic
[17:16:31] [PASSED] gpu_test_buddy_alloc_pathological
[17:16:31] [PASSED] gpu_test_buddy_alloc_contiguous
[17:16:31] [PASSED] gpu_test_buddy_alloc_clear
[17:16:31] [PASSED] gpu_test_buddy_alloc_range
[17:16:31] [PASSED] gpu_test_buddy_alloc_range_bias
[17:16:32] [PASSED] gpu_test_buddy_fragmentation_performance
[17:16:33] [PASSED] gpu_test_buddy_dirty_tracker_performance
[17:16:33] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[17:16:33] [PASSED] gpu_test_buddy_offset_aligned_allocation
[17:16:33] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[17:16:33] [PASSED] gpu_test_buddy_addr_to_block
[17:16:33] ==================== [PASSED] gpu_buddy ====================
[17:16:33] ============================================================
[17:16:33] Testing complete. Ran 18 tests: passed: 18
[17:16:33] Elapsed time: 27.469s total, 4.458s configuring, 20.843s building, 2.094s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:16:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:17:10] Starting KUnit Kernel (1/1)...
[17:17:10] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:17:10] ============= refcount_interrupt (4 subtests) ==============
[17:17:10] [PASSED] test_single_irq_change
[17:17:10] [PASSED] test_nested_irq_change
[17:17:10] [PASSED] test_multiple_irq_change
[17:17:10] [PASSED] test_irq_save
[17:17:10] =============== [PASSED] refcount_interrupt ================
[17:17:10] ================== guc_buf (11 subtests) ===================
[17:17:10] [PASSED] test_smallest
[17:17:10] [PASSED] test_largest
[17:17:10] [PASSED] test_granular
[17:17:10] [PASSED] test_unique
[17:17:10] [PASSED] test_overlap
[17:17:10] [PASSED] test_reusable
[17:17:10] [PASSED] test_too_big
[17:17:10] [PASSED] test_flush
[17:17:10] [PASSED] test_lookup
[17:17:10] [PASSED] test_data
[17:17:10] [PASSED] test_class
[17:17:10] ===================== [PASSED] guc_buf =====================
[17:17:10] =================== guc_dbm (7 subtests) ===================
[17:17:10] [PASSED] test_empty
[17:17:10] [PASSED] test_default
[17:17:10] ======================== test_size  ========================
[17:17:10] [PASSED] 4
[17:17:10] [PASSED] 8
[17:17:10] [PASSED] 32
[17:17:10] [PASSED] 256
[17:17:10] ==================== [PASSED] test_size ====================
[17:17:10] ======================= test_reuse  ========================
[17:17:10] [PASSED] 4
[17:17:10] [PASSED] 8
[17:17:10] [PASSED] 32
[17:17:10] [PASSED] 256
[17:17:10] =================== [PASSED] test_reuse ====================
[17:17:10] =================== test_range_overlap  ====================
[17:17:10] [PASSED] 4
[17:17:10] [PASSED] 8
[17:17:10] [PASSED] 32
[17:17:10] [PASSED] 256
[17:17:10] =============== [PASSED] test_range_overlap ================
[17:17:10] =================== test_range_compact  ====================
[17:17:10] [PASSED] 4
[17:17:10] [PASSED] 8
[17:17:10] [PASSED] 32
[17:17:10] [PASSED] 256
[17:17:10] =============== [PASSED] test_range_compact ================
[17:17:10] ==================== test_range_spare  =====================
[17:17:10] [PASSED] 4
[17:17:10] [PASSED] 8
[17:17:10] [PASSED] 32
[17:17:10] [PASSED] 256
[17:17:10] ================ [PASSED] test_range_spare =================
[17:17:10] ===================== [PASSED] guc_dbm =====================
[17:17:10] =================== guc_idm (6 subtests) ===================
[17:17:10] [PASSED] bad_init
[17:17:10] [PASSED] no_init
[17:17:10] [PASSED] init_fini
[17:17:10] [PASSED] check_used
[17:17:10] [PASSED] check_quota
[17:17:10] [PASSED] check_all
[17:17:10] ===================== [PASSED] guc_idm =====================
[17:17:10] =============== guc_klv_helpers (9 subtests) ===============
[17:17:10] [PASSED] test_count
[17:17:10] [PASSED] test_encode_u32
[17:17:10] [PASSED] test_encode_u64
[17:17:10] [PASSED] test_encode_string
[17:17:10] [PASSED] test_encode_object_raw
[17:17:10] [PASSED] test_encode_object_klv
[17:17:10] [PASSED] test_encode_object_nested
[17:17:10] [PASSED] test_encode_object_basic
[17:17:10] [PASSED] test_print
[17:17:10] ================= [PASSED] guc_klv_helpers =================
[17:17:10] =================== xe_log (4 subtests) ====================
[17:17:10] [PASSED] demo_cper
[17:17:10] [PASSED] demo_dmesg
[17:17:10] ======================= test_dmesg  ========================
[17:17:10] [PASSED] test_fatal
[17:17:10] [PASSED] test_fatal_tile
[17:17:10] [PASSED] test_fatal_gt
[17:17:10] [PASSED] test_fatal_comp
[17:17:10] [PASSED] test_fatal_comp_tile
[17:17:10] [PASSED] test_fatal_comp_gt
[17:17:10] [PASSED] test_fatal_all
[17:17:10] [PASSED] test_recoverable
[17:17:10] [PASSED] test_recoverable_tile
[17:17:10] [PASSED] test_recoverable_gt
[17:17:10] [PASSED] test_recoverable_comp
[17:17:10] [PASSED] test_recoverable_comp_tile
[17:17:10] [PASSED] test_recoverable_comp_gt
[17:17:10] [PASSED] test_recoverable_all
[17:17:10] [PASSED] test_info
[17:17:10] [PASSED] test_info_tile
[17:17:10] [PASSED] test_info_gt
[17:17:10] [PASSED] test_info_err
[17:17:10] [PASSED] test_info_comp
[17:17:10] [PASSED] test_info_comp_tile
[17:17:10] [PASSED] test_info_comp_gt
[17:17:10] [PASSED] test_info_all
[17:17:10] [PASSED] test_hw_fatal
[17:17:10] [PASSED] test_hw_recoverable
[17:17:10] [PASSED] test_hw_corrected
[17:17:10] [PASSED] test_hw_informational
[17:17:10] =================== [PASSED] test_dmesg ====================
[17:17:10] ====================== test_invalid  =======================
[17:17:10] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[17:17:10] ================== [SKIPPED] test_invalid ==================
[17:17:10] ===================== [PASSED] xe_log ======================
[17:17:10] ================== no_relay (3 subtests) ===================
[17:17:10] [PASSED] xe_drops_guc2pf_if_not_ready
[17:17:10] [PASSED] xe_drops_guc2vf_if_not_ready
[17:17:10] [PASSED] xe_rejects_send_if_not_ready
[17:17:10] ==================== [PASSED] no_relay =====================
[17:17:10] ================== pf_relay (14 subtests) ==================
[17:17:10] [PASSED] pf_rejects_guc2pf_too_short
[17:17:10] [PASSED] pf_rejects_guc2pf_too_long
[17:17:10] [PASSED] pf_rejects_guc2pf_no_payload
[17:17:10] [PASSED] pf_fails_no_payload
[17:17:10] [PASSED] pf_fails_bad_origin
[17:17:10] [PASSED] pf_fails_bad_type
[17:17:10] [PASSED] pf_txn_reports_error
[17:17:10] [PASSED] pf_txn_sends_pf2guc
[17:17:10] [PASSED] pf_sends_pf2guc
[17:17:10] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:17:10] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:17:10] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:17:10] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:17:10] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[17:17:10] ==================== [PASSED] pf_relay =====================
[17:17:10] ================== vf_relay (3 subtests) ===================
[17:17:10] [PASSED] vf_rejects_guc2vf_too_short
[17:17:10] [PASSED] vf_rejects_guc2vf_too_long
[17:17:10] [PASSED] vf_rejects_guc2vf_no_payload
[17:17:10] ==================== [PASSED] vf_relay =====================
[17:17:10] ================ pf_gt_config (9 subtests) =================
[17:17:10] [PASSED] fair_contexts_1vf
[17:17:10] [PASSED] fair_doorbells_1vf
[17:17:10] [PASSED] fair_ggtt_1vf
[17:17:10] ====================== fair_vram_1vf  ======================
[17:17:10] [PASSED] 3.50 GiB
[17:17:10] [PASSED] 11.5 GiB
[17:17:10] [PASSED] 15.5 GiB
[17:17:10] [PASSED] 31.5 GiB
[17:17:10] [PASSED] 63.5 GiB
[17:17:10] [PASSED] 1.91 GiB
[17:17:10] ================== [PASSED] fair_vram_1vf ==================
[17:17:10] ================ fair_vram_1vf_admin_only  =================
[17:17:10] [PASSED] 3.50 GiB
[17:17:10] [PASSED] 11.5 GiB
[17:17:10] [PASSED] 15.5 GiB
[17:17:10] [PASSED] 31.5 GiB
[17:17:10] [PASSED] 63.5 GiB
[17:17:10] [PASSED] 1.91 GiB
[17:17:10] ============ [PASSED] fair_vram_1vf_admin_only =============
[17:17:10] ====================== fair_contexts  ======================
[17:17:10] [PASSED] 1 VF
[17:17:10] [PASSED] 2 VFs
[17:17:10] [PASSED] 3 VFs
[17:17:10] [PASSED] 4 VFs
[17:17:10] [PASSED] 5 VFs
[17:17:10] [PASSED] 6 VFs
[17:17:10] [PASSED] 7 VFs
[17:17:10] [PASSED] 8 VFs
[17:17:10] [PASSED] 9 VFs
[17:17:10] [PASSED] 10 VFs
[17:17:10] [PASSED] 11 VFs
[17:17:10] [PASSED] 12 VFs
[17:17:10] [PASSED] 13 VFs
[17:17:10] [PASSED] 14 VFs
[17:17:10] [PASSED] 15 VFs
[17:17:10] [PASSED] 16 VFs
[17:17:10] [PASSED] 17 VFs
[17:17:10] [PASSED] 18 VFs
[17:17:10] [PASSED] 19 VFs
[17:17:10] [PASSED] 20 VFs
[17:17:10] [PASSED] 21 VFs
[17:17:10] [PASSED] 22 VFs
[17:17:10] [PASSED] 23 VFs
[17:17:10] [PASSED] 24 VFs
[17:17:10] [PASSED] 25 VFs
[17:17:10] [PASSED] 26 VFs
[17:17:10] [PASSED] 27 VFs
[17:17:10] [PASSED] 28 VFs
[17:17:10] [PASSED] 29 VFs
[17:17:10] [PASSED] 30 VFs
[17:17:10] [PASSED] 31 VFs
[17:17:10] [PASSED] 32 VFs
[17:17:10] [PASSED] 33 VFs
[17:17:10] [PASSED] 34 VFs
[17:17:10] [PASSED] 35 VFs
[17:17:10] [PASSED] 36 VFs
[17:17:10] [PASSED] 37 VFs
[17:17:10] [PASSED] 38 VFs
[17:17:10] [PASSED] 39 VFs
[17:17:10] [PASSED] 40 VFs
[17:17:10] [PASSED] 41 VFs
[17:17:10] [PASSED] 42 VFs
[17:17:10] [PASSED] 43 VFs
[17:17:10] [PASSED] 44 VFs
[17:17:10] [PASSED] 45 VFs
[17:17:10] [PASSED] 46 VFs
[17:17:10] [PASSED] 47 VFs
[17:17:10] [PASSED] 48 VFs
[17:17:10] [PASSED] 49 VFs
[17:17:10] [PASSED] 50 VFs
[17:17:10] [PASSED] 51 VFs
[17:17:10] [PASSED] 52 VFs
[17:17:10] [PASSED] 53 VFs
[17:17:10] [PASSED] 54 VFs
[17:17:10] [PASSED] 55 VFs
[17:17:10] [PASSED] 56 VFs
[17:17:10] [PASSED] 57 VFs
[17:17:10] [PASSED] 58 VFs
[17:17:10] [PASSED] 59 VFs
[17:17:10] [PASSED] 60 VFs
[17:17:10] [PASSED] 61 VFs
[17:17:10] [PASSED] 62 VFs
[17:17:10] [PASSED] 63 VFs
[17:17:10] ================== [PASSED] fair_contexts ==================
[17:17:10] ===================== fair_doorbells  ======================
[17:17:10] [PASSED] 1 VF
[17:17:10] [PASSED] 2 VFs
[17:17:10] [PASSED] 3 VFs
[17:17:10] [PASSED] 4 VFs
[17:17:10] [PASSED] 5 VFs
[17:17:10] [PASSED] 6 VFs
[17:17:10] [PASSED] 7 VFs
[17:17:10] [PASSED] 8 VFs
[17:17:10] [PASSED] 9 VFs
[17:17:10] [PASSED] 10 VFs
[17:17:10] [PASSED] 11 VFs
[17:17:10] [PASSED] 12 VFs
[17:17:10] [PASSED] 13 VFs
[17:17:10] [PASSED] 14 VFs
[17:17:10] [PASSED] 15 VFs
[17:17:10] [PASSED] 16 VFs
[17:17:10] [PASSED] 17 VFs
[17:17:10] [PASSED] 18 VFs
[17:17:10] [PASSED] 19 VFs
[17:17:10] [PASSED] 20 VFs
[17:17:10] [PASSED] 21 VFs
[17:17:10] [PASSED] 22 VFs
[17:17:10] [PASSED] 23 VFs
[17:17:10] [PASSED] 24 VFs
[17:17:10] [PASSED] 25 VFs
[17:17:10] [PASSED] 26 VFs
[17:17:10] [PASSED] 27 VFs
[17:17:10] [PASSED] 28 VFs
[17:17:10] [PASSED] 29 VFs
[17:17:10] [PASSED] 30 VFs
[17:17:10] [PASSED] 31 VFs
[17:17:10] [PASSED] 32 VFs
[17:17:10] [PASSED] 33 VFs
[17:17:10] [PASSED] 34 VFs
[17:17:10] [PASSED] 35 VFs
[17:17:10] [PASSED] 36 VFs
[17:17:10] [PASSED] 37 VFs
[17:17:10] [PASSED] 38 VFs
[17:17:10] [PASSED] 39 VFs
[17:17:10] [PASSED] 40 VFs
[17:17:10] [PASSED] 41 VFs
[17:17:10] [PASSED] 42 VFs
[17:17:10] [PASSED] 43 VFs
[17:17:10] [PASSED] 44 VFs
[17:17:10] [PASSED] 45 VFs
[17:17:10] [PASSED] 46 VFs
[17:17:10] [PASSED] 47 VFs
[17:17:10] [PASSED] 48 VFs
[17:17:10] [PASSED] 49 VFs
[17:17:10] [PASSED] 50 VFs
[17:17:10] [PASSED] 51 VFs
[17:17:10] [PASSED] 52 VFs
[17:17:10] [PASSED] 53 VFs
[17:17:10] [PASSED] 54 VFs
[17:17:10] [PASSED] 55 VFs
[17:17:10] [PASSED] 56 VFs
[17:17:10] [PASSED] 57 VFs
[17:17:10] [PASSED] 58 VFs
[17:17:10] [PASSED] 59 VFs
[17:17:10] [PASSED] 60 VFs
[17:17:10] [PASSED] 61 VFs
[17:17:10] [PASSED] 62 VFs
[17:17:10] [PASSED] 63 VFs
[17:17:10] ================= [PASSED] fair_doorbells ==================
[17:17:10] ======================== fair_ggtt  ========================
[17:17:10] [PASSED] 1 VF
[17:17:10] [PASSED] 2 VFs
[17:17:10] [PASSED] 3 VFs
[17:17:10] [PASSED] 4 VFs
[17:17:10] [PASSED] 5 VFs
[17:17:10] [PASSED] 6 VFs
[17:17:10] [PASSED] 7 VFs
[17:17:10] [PASSED] 8 VFs
[17:17:10] [PASSED] 9 VFs
[17:17:10] [PASSED] 10 VFs
[17:17:10] [PASSED] 11 VFs
[17:17:10] [PASSED] 12 VFs
[17:17:10] [PASSED] 13 VFs
[17:17:10] [PASSED] 14 VFs
[17:17:10] [PASSED] 15 VFs
[17:17:10] [PASSED] 16 VFs
[17:17:10] [PASSED] 17 VFs
[17:17:10] [PASSED] 18 VFs
[17:17:10] [PASSED] 19 VFs
[17:17:10] [PASSED] 20 VFs
[17:17:10] [PASSED] 21 VFs
[17:17:10] [PASSED] 22 VFs
[17:17:10] [PASSED] 23 VFs
[17:17:10] [PASSED] 24 VFs
[17:17:10] [PASSED] 25 VFs
[17:17:10] [PASSED] 26 VFs
[17:17:10] [PASSED] 27 VFs
[17:17:10] [PASSED] 28 VFs
[17:17:10] [PASSED] 29 VFs
[17:17:10] [PASSED] 30 VFs
[17:17:10] [PASSED] 31 VFs
[17:17:10] [PASSED] 32 VFs
[17:17:10] [PASSED] 33 VFs
[17:17:10] [PASSED] 34 VFs
[17:17:10] [PASSED] 35 VFs
[17:17:10] [PASSED] 36 VFs
[17:17:10] [PASSED] 37 VFs
[17:17:10] [PASSED] 38 VFs
[17:17:10] [PASSED] 39 VFs
[17:17:10] [PASSED] 40 VFs
[17:17:10] [PASSED] 41 VFs
[17:17:10] [PASSED] 42 VFs
[17:17:10] [PASSED] 43 VFs
[17:17:10] [PASSED] 44 VFs
[17:17:10] [PASSED] 45 VFs
[17:17:10] [PASSED] 46 VFs
[17:17:10] [PASSED] 47 VFs
[17:17:10] [PASSED] 48 VFs
[17:17:10] [PASSED] 49 VFs
[17:17:10] [PASSED] 50 VFs
[17:17:10] [PASSED] 51 VFs
[17:17:10] [PASSED] 52 VFs
[17:17:10] [PASSED] 53 VFs
[17:17:10] [PASSED] 54 VFs
[17:17:10] [PASSED] 55 VFs
[17:17:10] [PASSED] 56 VFs
[17:17:10] [PASSED] 57 VFs
[17:17:10] [PASSED] 58 VFs
[17:17:10] [PASSED] 59 VFs
[17:17:10] [PASSED] 60 VFs
[17:17:10] [PASSED] 61 VFs
[17:17:10] [PASSED] 62 VFs
[17:17:10] [PASSED] 63 VFs
[17:17:10] ==================== [PASSED] fair_ggtt ====================
[17:17:10] ======================== fair_vram  ========================
[17:17:10] [PASSED] 1 VF
[17:17:10] [PASSED] 2 VFs
[17:17:10] [PASSED] 3 VFs
[17:17:10] [PASSED] 4 VFs
[17:17:10] [PASSED] 5 VFs
[17:17:10] [PASSED] 6 VFs
[17:17:10] [PASSED] 7 VFs
[17:17:10] [PASSED] 8 VFs
[17:17:10] [PASSED] 9 VFs
[17:17:10] [PASSED] 10 VFs
[17:17:10] [PASSED] 11 VFs
[17:17:10] [PASSED] 12 VFs
[17:17:10] [PASSED] 13 VFs
[17:17:10] [PASSED] 14 VFs
[17:17:10] [PASSED] 15 VFs
[17:17:10] [PASSED] 16 VFs
[17:17:10] [PASSED] 17 VFs
[17:17:10] [PASSED] 18 VFs
[17:17:10] [PASSED] 19 VFs
[17:17:10] [PASSED] 20 VFs
[17:17:10] [PASSED] 21 VFs
[17:17:10] [PASSED] 22 VFs
[17:17:10] [PASSED] 23 VFs
[17:17:10] [PASSED] 24 VFs
[17:17:10] [PASSED] 25 VFs
[17:17:10] [PASSED] 26 VFs
[17:17:10] [PASSED] 27 VFs
[17:17:10] [PASSED] 28 VFs
[17:17:10] [PASSED] 29 VFs
[17:17:10] [PASSED] 30 VFs
[17:17:10] [PASSED] 31 VFs
[17:17:10] [PASSED] 32 VFs
[17:17:10] [PASSED] 33 VFs
[17:17:10] [PASSED] 34 VFs
[17:17:10] [PASSED] 35 VFs
[17:17:10] [PASSED] 36 VFs
[17:17:10] [PASSED] 37 VFs
[17:17:10] [PASSED] 38 VFs
[17:17:10] [PASSED] 39 VFs
[17:17:10] [PASSED] 40 VFs
[17:17:10] [PASSED] 41 VFs
[17:17:10] [PASSED] 42 VFs
[17:17:10] [PASSED] 43 VFs
[17:17:10] [PASSED] 44 VFs
[17:17:10] [PASSED] 45 VFs
[17:17:10] [PASSED] 46 VFs
[17:17:10] [PASSED] 47 VFs
[17:17:10] [PASSED] 48 VFs
[17:17:10] [PASSED] 49 VFs
[17:17:10] [PASSED] 50 VFs
[17:17:10] [PASSED] 51 VFs
[17:17:10] [PASSED] 52 VFs
[17:17:10] [PASSED] 53 VFs
[17:17:10] [PASSED] 54 VFs
[17:17:10] [PASSED] 55 VFs
[17:17:10] [PASSED] 56 VFs
[17:17:10] [PASSED] 57 VFs
[17:17:10] [PASSED] 58 VFs
[17:17:10] [PASSED] 59 VFs
[17:17:10] [PASSED] 60 VFs
[17:17:10] [PASSED] 61 VFs
[17:17:10] [PASSED] 62 VFs
[17:17:10] [PASSED] 63 VFs
[17:17:10] ==================== [PASSED] fair_vram ====================
[17:17:10] ================== [PASSED] pf_gt_config ===================
[17:17:10] ===================== lmtt (1 subtest) =====================
[17:17:10] ======================== test_ops  =========================
[17:17:10] [PASSED] 2-level
[17:17:10] [PASSED] multi-level
[17:17:10] ==================== [PASSED] test_ops =====================
[17:17:10] ====================== [PASSED] lmtt =======================
[17:17:10] ================= sriov_packet (1 subtest) =================
[17:17:10] [PASSED] test_descriptor_init
[17:17:10] ================== [PASSED] sriov_packet ===================
[17:17:10] ================= pf_service (11 subtests) =================
[17:17:10] [PASSED] pf_negotiate_any
[17:17:10] [PASSED] pf_negotiate_base_match
[17:17:10] [PASSED] pf_negotiate_base_newer
[17:17:10] [PASSED] pf_negotiate_base_next
[17:17:10] [SKIPPED] pf_negotiate_base_older (no older minor)
[17:17:10] [PASSED] pf_negotiate_base_prev
[17:17:10] [PASSED] pf_negotiate_latest_match
[17:17:10] [PASSED] pf_negotiate_latest_newer
[17:17:10] [PASSED] pf_negotiate_latest_next
[17:17:10] [SKIPPED] pf_negotiate_latest_older (no older minor)
[17:17:10] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[17:17:10] =================== [PASSED] pf_service ====================
[17:17:10] ================= xe_guc_g2g (2 subtests) ==================
[17:17:10] ============== xe_live_guc_g2g_kunit_default  ==============
[17:17:10] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[17:17:10] ============== xe_live_guc_g2g_kunit_allmem  ===============
[17:17:10] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[17:17:10] =================== [SKIPPED] xe_guc_g2g ===================
[17:17:10] =================== xe_mocs (2 subtests) ===================
[17:17:10] ================ xe_live_mocs_kernel_kunit  ================
[17:17:10] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:17:10] ================ xe_live_mocs_reset_kunit  =================
[17:17:10] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:17:10] ==================== [SKIPPED] xe_mocs =====================
[17:17:10] ================= xe_migrate (2 subtests) ==================
[17:17:10] ================= xe_migrate_sanity_kunit  =================
[17:17:10] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:17:10] ================== xe_validate_ccs_kunit  ==================
[17:17:10] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:17:10] =================== [SKIPPED] xe_migrate ===================
[17:17:10] ================== xe_dma_buf (1 subtest) ==================
[17:17:10] ==================== xe_dma_buf_kunit  =====================
[17:17:10] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:17:10] =================== [SKIPPED] xe_dma_buf ===================
[17:17:10] ================= xe_bo_shrink (1 subtest) =================
[17:17:10] =================== xe_bo_shrink_kunit  ====================
[17:17:10] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:17:10] ================== [SKIPPED] xe_bo_shrink ==================
[17:17:10] ==================== xe_bo (2 subtests) ====================
[17:17:10] ================== xe_ccs_migrate_kunit  ===================
[17:17:10] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:17:10] ==================== xe_bo_evict_kunit  ====================
[17:17:10] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:17:10] ===================== [SKIPPED] xe_bo ======================
[17:17:10] =================== xe_any (9 subtests) ====================
[17:17:10] [PASSED] test_to_xe
[17:17:10] [PASSED] test_to_dev
[17:17:10] [PASSED] test_to_pdev
[17:17:10] [PASSED] test_to_drm
[17:17:10] [PASSED] test_if_pdev
[17:17:10] [PASSED] test_if_xe
[17:17:10] [PASSED] test_if_tile
[17:17:10] [PASSED] test_if_gt
[17:17:10] [PASSED] test_to_id
[17:17:10] ===================== [PASSED] xe_any ======================
[17:17:10] ==================== args (13 subtests) ====================
[17:17:10] [PASSED] count_args_test
[17:17:10] [PASSED] call_args_example
[17:17:10] [PASSED] call_args_test
[17:17:10] [PASSED] drop_first_arg_example
[17:17:10] [PASSED] drop_first_arg_test
[17:17:10] [PASSED] first_arg_example
[17:17:10] [PASSED] first_arg_test
[17:17:10] [PASSED] last_arg_example
[17:17:10] [PASSED] last_arg_test
[17:17:10] [PASSED] pick_arg_example
[17:17:10] [PASSED] if_args_example
[17:17:10] [PASSED] if_args_test
[17:17:10] [PASSED] sep_comma_example
[17:17:10] ====================== [PASSED] args =======================
[17:17:10] =================== xe_pci (3 subtests) ====================
[17:17:10] ==================== check_graphics_ip  ====================
[17:17:10] [PASSED] 12.00 Xe_LP
[17:17:10] [PASSED] 12.10 Xe_LP+
[17:17:10] [PASSED] 12.55 Xe_HPG
[17:17:10] [PASSED] 12.60 Xe_HPC
[17:17:10] [PASSED] 12.70 Xe_LPG
[17:17:10] [PASSED] 12.71 Xe_LPG
[17:17:10] [PASSED] 12.74 Xe_LPG+
[17:17:10] [PASSED] 20.01 Xe2_HPG
[17:17:10] [PASSED] 20.02 Xe2_HPG
[17:17:10] [PASSED] 20.04 Xe2_LPG
[17:17:10] [PASSED] 30.00 Xe3_LPG
[17:17:10] [PASSED] 30.01 Xe3_LPG
[17:17:10] [PASSED] 30.03 Xe3_LPG
[17:17:10] [PASSED] 30.04 Xe3_LPG
[17:17:10] [PASSED] 30.05 Xe3_LPG
[17:17:10] [PASSED] 35.10 Xe3p_LPG
[17:17:10] [PASSED] 35.11 Xe3p_XPC
[17:17:10] ================ [PASSED] check_graphics_ip ================
[17:17:10] ===================== check_media_ip  ======================
[17:17:10] [PASSED] 12.00 Xe_M
[17:17:10] [PASSED] 12.55 Xe_HPM
[17:17:10] [PASSED] 13.00 Xe_LPM+
[17:17:10] [PASSED] 13.01 Xe2_HPM
[17:17:10] [PASSED] 20.00 Xe2_LPM
[17:17:10] [PASSED] 30.00 Xe3_LPM
[17:17:10] [PASSED] 30.02 Xe3_LPM
[17:17:10] [PASSED] 35.00 Xe3p_LPM
[17:17:10] [PASSED] 35.03 Xe3p_HPM
[17:17:10] ================= [PASSED] check_media_ip ==================
[17:17:10] =================== check_platform_desc  ===================
[17:17:10] [PASSED] 0x9A60 (TIGERLAKE)
[17:17:10] [PASSED] 0x9A68 (TIGERLAKE)
[17:17:10] [PASSED] 0x9A70 (TIGERLAKE)
[17:17:10] [PASSED] 0x9A40 (TIGERLAKE)
[17:17:10] [PASSED] 0x9A49 (TIGERLAKE)
[17:17:10] [PASSED] 0x9A59 (TIGERLAKE)
[17:17:10] [PASSED] 0x9A78 (TIGERLAKE)
[17:17:10] [PASSED] 0x9AC0 (TIGERLAKE)
[17:17:10] [PASSED] 0x9AC9 (TIGERLAKE)
[17:17:10] [PASSED] 0x9AD9 (TIGERLAKE)
[17:17:10] [PASSED] 0x9AF8 (TIGERLAKE)
[17:17:10] [PASSED] 0x4C80 (ROCKETLAKE)
[17:17:10] [PASSED] 0x4C8A (ROCKETLAKE)
[17:17:10] [PASSED] 0x4C8B (ROCKETLAKE)
[17:17:10] [PASSED] 0x4C8C (ROCKETLAKE)
[17:17:10] [PASSED] 0x4C90 (ROCKETLAKE)
[17:17:10] [PASSED] 0x4C9A (ROCKETLAKE)
[17:17:10] [PASSED] 0x4680 (ALDERLAKE_S)
[17:17:10] [PASSED] 0x4682 (ALDERLAKE_S)
[17:17:10] [PASSED] 0x4688 (ALDERLAKE_S)
[17:17:10] [PASSED] 0x468A (ALDERLAKE_S)
[17:17:10] [PASSED] 0x468B (ALDERLAKE_S)
[17:17:10] [PASSED] 0x4690 (ALDERLAKE_S)
[17:17:10] [PASSED] 0x4692 (ALDERLAKE_S)
[17:17:10] [PASSED] 0x4693 (ALDERLAKE_S)
[17:17:10] [PASSED] 0x46A0 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46A1 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46A2 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46A3 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46A6 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46A8 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46AA (ALDERLAKE_P)
[17:17:10] [PASSED] 0x462A (ALDERLAKE_P)
[17:17:10] [PASSED] 0x4626 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x4628 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46B0 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46B1 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46B2 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46B3 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46C0 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46C1 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46C2 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46C3 (ALDERLAKE_P)
[17:17:10] [PASSED] 0x46D0 (ALDERLAKE_N)
[17:17:10] [PASSED] 0x46D1 (ALDERLAKE_N)
[17:17:10] [PASSED] 0x46D2 (ALDERLAKE_N)
[17:17:10] [PASSED] 0x46D3 (ALDERLAKE_N)
[17:17:10] [PASSED] 0x46D4 (ALDERLAKE_N)
[17:17:10] [PASSED] 0xA721 (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7A1 (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7A9 (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7AC (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7AD (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA720 (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7A0 (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7A8 (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7AA (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA7AB (ALDERLAKE_P)
[17:17:10] [PASSED] 0xA780 (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA781 (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA782 (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA783 (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA788 (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA789 (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA78A (ALDERLAKE_S)
[17:17:10] [PASSED] 0xA78B (ALDERLAKE_S)
[17:17:10] [PASSED] 0x4905 (DG1)
[17:17:10] [PASSED] 0x4906 (DG1)
[17:17:10] [PASSED] 0x4907 (DG1)
[17:17:10] [PASSED] 0x4908 (DG1)
[17:17:10] [PASSED] 0x4909 (DG1)
[17:17:10] [PASSED] 0x56C0 (DG2)
[17:17:10] [PASSED] 0x56C2 (DG2)
[17:17:10] [PASSED] 0x56C1 (DG2)
[17:17:10] [PASSED] 0x7D51 (METEORLAKE)
[17:17:10] [PASSED] 0x7DD1 (METEORLAKE)
[17:17:10] [PASSED] 0x7D41 (METEORLAKE)
[17:17:10] [PASSED] 0x7D67 (METEORLAKE)
[17:17:10] [PASSED] 0xB640 (METEORLAKE)
[17:17:10] [PASSED] 0x56A0 (DG2)
[17:17:10] [PASSED] 0x56A1 (DG2)
[17:17:10] [PASSED] 0x56A2 (DG2)
[17:17:10] [PASSED] 0x56BE (DG2)
[17:17:10] [PASSED] 0x56BF (DG2)
[17:17:10] [PASSED] 0x5690 (DG2)
[17:17:10] [PASSED] 0x5691 (DG2)
[17:17:10] [PASSED] 0x5692 (DG2)
[17:17:10] [PASSED] 0x56A5 (DG2)
[17:17:10] [PASSED] 0x56A6 (DG2)
[17:17:10] [PASSED] 0x56B0 (DG2)
[17:17:10] [PASSED] 0x56B1 (DG2)
[17:17:10] [PASSED] 0x56BA (DG2)
[17:17:10] [PASSED] 0x56BB (DG2)
[17:17:10] [PASSED] 0x56BC (DG2)
[17:17:10] [PASSED] 0x56BD (DG2)
[17:17:10] [PASSED] 0x5693 (DG2)
[17:17:10] [PASSED] 0x5694 (DG2)
[17:17:10] [PASSED] 0x5695 (DG2)
[17:17:10] [PASSED] 0x56A3 (DG2)
[17:17:10] [PASSED] 0x56A4 (DG2)
[17:17:10] [PASSED] 0x56B2 (DG2)
[17:17:10] [PASSED] 0x56B3 (DG2)
[17:17:10] [PASSED] 0x5696 (DG2)
[17:17:10] [PASSED] 0x5697 (DG2)
[17:17:10] [PASSED] 0xB69 (PVC)
[17:17:10] [PASSED] 0xB6E (PVC)
[17:17:10] [PASSED] 0xBD4 (PVC)
[17:17:10] [PASSED] 0xBD5 (PVC)
[17:17:10] [PASSED] 0xBD6 (PVC)
[17:17:10] [PASSED] 0xBD7 (PVC)
[17:17:10] [PASSED] 0xBD8 (PVC)
[17:17:10] [PASSED] 0xBD9 (PVC)
[17:17:10] [PASSED] 0xBDA (PVC)
[17:17:10] [PASSED] 0xBDB (PVC)
[17:17:10] [PASSED] 0xBE0 (PVC)
[17:17:10] [PASSED] 0xBE1 (PVC)
[17:17:10] [PASSED] 0xBE5 (PVC)
[17:17:10] [PASSED] 0x7D40 (METEORLAKE)
[17:17:10] [PASSED] 0x7D45 (METEORLAKE)
[17:17:10] [PASSED] 0x7D55 (METEORLAKE)
[17:17:10] [PASSED] 0x7D60 (METEORLAKE)
[17:17:10] [PASSED] 0x7DD5 (METEORLAKE)
[17:17:10] [PASSED] 0x6420 (LUNARLAKE)
[17:17:10] [PASSED] 0x64A0 (LUNARLAKE)
[17:17:10] [PASSED] 0x64B0 (LUNARLAKE)
[17:17:10] [PASSED] 0xE202 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE209 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE20B (BATTLEMAGE)
[17:17:10] [PASSED] 0xE20C (BATTLEMAGE)
[17:17:10] [PASSED] 0xE20D (BATTLEMAGE)
[17:17:10] [PASSED] 0xE210 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE211 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE212 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE216 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE220 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE221 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE222 (BATTLEMAGE)
[17:17:10] [PASSED] 0xE223 (BATTLEMAGE)
[17:17:10] [PASSED] 0xB080 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB081 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB082 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB083 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB084 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB085 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB086 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB087 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB08F (PANTHERLAKE)
[17:17:10] [PASSED] 0xB090 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB0A0 (PANTHERLAKE)
[17:17:10] [PASSED] 0xB0B0 (PANTHERLAKE)
[17:17:10] [PASSED] 0xFD80 (PANTHERLAKE)
[17:17:10] [PASSED] 0xFD81 (PANTHERLAKE)
[17:17:10] [PASSED] 0xD740 (NOVALAKE_S)
[17:17:10] [PASSED] 0xD741 (NOVALAKE_S)
[17:17:10] [PASSED] 0xD742 (NOVALAKE_S)
[17:17:10] [PASSED] 0xD743 (NOVALAKE_S)
[17:17:10] [PASSED] 0xD745 (NOVALAKE_S)
[17:17:10] [PASSED] 0xD74A (NOVALAKE_S)
[17:17:10] [PASSED] 0xD74B (NOVALAKE_S)
[17:17:10] [PASSED] 0x674C (CRESCENTISLAND)
[17:17:10] [PASSED] 0x674D (CRESCENTISLAND)
[17:17:10] [PASSED] 0x674E (CRESCENTISLAND)
[17:17:10] [PASSED] 0x674F (CRESCENTISLAND)
[17:17:10] [PASSED] 0x6750 (CRESCENTISLAND)
[17:17:10] [PASSED] 0xD750 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD751 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD752 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD753 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD754 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD755 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD756 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD757 (NOVALAKE_P)
[17:17:10] [PASSED] 0xD75F (NOVALAKE_P)
[17:17:10] =============== [PASSED] check_platform_desc ===============
[17:17:10] ===================== [PASSED] xe_pci ======================
[17:17:10] ============= xe_rtp_tables_test (5 subtests) ==============
[17:17:10] ================== xe_rtp_table_gt_test  ===================
[17:17:10] [PASSED] gt_was/14011060649
[17:17:10] [PASSED] gt_was/14011059788
[17:17:10] [PASSED] gt_was/14015795083
[17:17:10] [PASSED] gt_was/16021867713
[17:17:10] [PASSED] gt_was/14019449301
[17:17:10] [PASSED] gt_was/16028005424
[17:17:10] [PASSED] gt_was/14026578760
[17:17:10] [PASSED] gt_was/1409420604
[17:17:10] [PASSED] gt_was/1408615072
[17:17:10] [PASSED] gt_was/22010523718
[17:17:10] [PASSED] gt_was/14011006942
[17:17:10] [PASSED] gt_was/14014830051
[17:17:10] [PASSED] gt_was/18018781329
[17:17:10] [PASSED] gt_was/1509235366
[17:17:10] [PASSED] gt_was/18018781329
[17:17:10] [PASSED] gt_was/16016694945
[17:17:10] [PASSED] gt_was/14018575942
[17:17:10] [PASSED] gt_was/22016670082
[17:17:10] [PASSED] gt_was/22016670082
[17:17:10] [PASSED] gt_was/14017421178
[17:17:10] [PASSED] gt_was/16025250150
[17:17:10] [PASSED] gt_was/14021871409
[17:17:10] [PASSED] gt_was/16021865536
[17:17:10] [PASSED] gt_was/14021486841
[17:17:10] [PASSED] gt_was/14025160223
[17:17:10] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[17:17:10] [PASSED] gt_was/14025635424
[17:17:10] [PASSED] gt_was/16028005424
[17:17:10] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:17:10] ================== xe_rtp_table_gt_test  ===================
[17:17:10] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[17:17:10] [PASSED] gt_tunings/Tuning: 32B Access Enable
[17:17:10] [PASSED] gt_tunings/Tuning: L3 cache
[17:17:10] [PASSED] gt_tunings/Tuning: L3 cache - media
[17:17:10] [PASSED] gt_tunings/Tuning: Compression Overfetch
[17:17:10] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[17:17:10] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[17:17:10] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[17:17:10] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[17:17:10] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[17:17:10] [PASSED] gt_tunings/Tuning: Stateless compression control
[17:17:10] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[17:17:10] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[17:17:10] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[17:17:10] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[17:17:10] ============== [PASSED] xe_rtp_table_gt_test ===============
[17:17:10] ================== xe_rtp_table_oob_test  ==================
[17:17:10] [PASSED] oob_was/1607983814
[17:17:10] [PASSED] oob_was/16010904313
[17:17:10] [PASSED] oob_was/18022495364
[17:17:10] [PASSED] oob_was/22012773006
[17:17:10] [PASSED] oob_was/14014475959
[17:17:10] [PASSED] oob_was/22011391025
[17:17:10] [PASSED] oob_was/22012727170
[17:17:10] [PASSED] oob_was/22012727685
[17:17:10] [PASSED] oob_was/22016596838
[17:17:10] [PASSED] oob_was/18020744125
[17:17:10] [PASSED] oob_was/1409600907
[17:17:10] [PASSED] oob_was/22014953428
[17:17:10] [PASSED] oob_was/16017236439
[17:17:10] [PASSED] oob_was/14019821291
[17:17:10] [PASSED] oob_was/14015076503
[17:17:10] [PASSED] oob_was/14018913170
[17:17:10] [PASSED] oob_was/14018094691
[17:17:10] [PASSED] oob_was/18024947630
[17:17:10] [PASSED] oob_was/16022287689
[17:17:10] [PASSED] oob_was/13011645652
[17:17:10] [PASSED] oob_was/14022293748
[17:17:10] [PASSED] oob_was/22019794406
[17:17:10] [PASSED] oob_was/22019338487
[17:17:10] [PASSED] oob_was/16023588340
[17:17:10] [PASSED] oob_was/14019789679
[17:17:10] [PASSED] oob_was/14022866841
[17:17:10] [PASSED] oob_was/16021333562
[17:17:10] [PASSED] oob_was/14016712196
[17:17:10] [PASSED] oob_was/14015568240
[17:17:10] [PASSED] oob_was/18013179988
[17:17:10] [PASSED] oob_was/1508761755
[17:17:10] [PASSED] oob_was/16023105232
[17:17:10] [PASSED] oob_was/16026508708
[17:17:10] [PASSED] oob_was/14020001231
[17:17:10] [PASSED] oob_was/16023683509
[17:17:10] [PASSED] oob_was/14025515070
[17:17:10] [PASSED] oob_was/15015404425_disable
[17:17:10] [PASSED] oob_was/16026007364
[17:17:10] [PASSED] oob_was/14020316580
[17:17:10] [PASSED] oob_was/14025883347
[17:17:10] [PASSED] oob_was/16029380221
[17:17:10] [PASSED] oob_was/22022079272
[17:17:10] [PASSED] oob_was/16029897822
[17:17:10] [PASSED] oob_was/14027054324
[17:17:10] ============== [PASSED] xe_rtp_table_oob_test ==============
[17:17:10] ================ xe_rtp_table_dev_oob_test  ================
[17:17:10] [PASSED] device_oob_was/22010954014
[17:17:10] [PASSED] device_oob_was/15015404425
[17:17:10] [PASSED] device_oob_was/22019338487_display
[17:17:10] [PASSED] device_oob_was/14022085890
[17:17:10] [PASSED] device_oob_was/14026539277
[17:17:10] [PASSED] device_oob_was/14026633728
[17:17:10] [PASSED] device_oob_was/14026746987
[17:17:10] [PASSED] device_oob_was/14026779378
[17:17:10] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[17:17:10] ========== xe_rtp_table_missing_upper_bound_test  ==========
[17:17:10] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[17:17:10] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[17:17:10] [PASSED] register_whitelist/1806527549
[17:17:10] [PASSED] register_whitelist/allow_read_ctx_timestamp
[17:17:10] [PASSED] register_whitelist/allow_read_queue_timestamp
[17:17:10] [PASSED] register_whitelist/16014440446
[17:17:10] [PASSED] register_whitelist/16017236439
[17:17:10] [PASSED] register_whitelist/16020183090
[17:17:10] [PASSED] register_whitelist/14024997852
[17:17:10] [PASSED] register_whitelist/14024997852
[17:17:10] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[17:17:10] =============== [PASSED] xe_rtp_tables_test ================
[17:17:10] =================== xe_rtp (3 subtests) ====================
[17:17:10] =================== xe_rtp_rules_tests  ====================
[17:17:10] [PASSED] no
[17:17:10] [PASSED] yes
[17:17:10] [PASSED] no-and-no
[17:17:10] [PASSED] no-and-yes
[17:17:10] [PASSED] yes-and-no
[17:17:10] [PASSED] yes-and-yes
[17:17:10] [PASSED] no-or-no
[17:17:10] [PASSED] no-or-yes
[17:17:10] [PASSED] yes-or-no
[17:17:10] [PASSED] yes-or-yes
[17:17:10] [PASSED] no-yes-or-yes-no
[17:17:10] [PASSED] no-yes-or-yes-yes
[17:17:10] [PASSED] yes-yes-or-no-yes
[17:17:10] [PASSED] yes-yes-or-yes-yes
[17:17:10] [PASSED] no-no-or-yes-or-no
[17:17:10] [PASSED] or
[17:17:10] [PASSED] or-yes
[17:17:10] [PASSED] or-no
[17:17:10] [PASSED] yes-or
[17:17:10] [PASSED] no-or
[17:17:10] [PASSED] no-or-or-yes
[17:17:10] [PASSED] yes-or-or-no
[17:17:10] [PASSED] no-or-or-no
[17:17:11] [PASSED] missing-context-engine-class
[17:17:11] [PASSED] missing-context-engine-class-or-yes
[17:17:11] [PASSED] missing-context-engine-class-or-or-yes
[17:17:11] =============== [PASSED] xe_rtp_rules_tests ================
[17:17:11] =============== xe_rtp_process_to_sr_tests  ================
[17:17:11] [PASSED] coalesce-same-reg
[17:17:11] [PASSED] coalesce-same-reg-literal-and-func
[17:17:11] [PASSED] no-match-no-add
[17:17:11] [PASSED] two-regs-two-entries
[17:17:11] [PASSED] clr-one-set-other
[17:17:11] [PASSED] set-field
[17:17:11] [PASSED] conflict-duplicate
[17:17:11] [PASSED] conflict-not-disjoint
[17:17:11] [PASSED] conflict-not-disjoint-literal-and-func
[17:17:11] [PASSED] conflict-reg-type
[17:17:11] [PASSED] bad-mcr-reg-forced-to-regular
[17:17:11] [PASSED] bad-regular-reg-forced-to-mcr
[17:17:11] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:17:11] ================== xe_rtp_process_tests  ===================
[17:17:11] [PASSED] active1
[17:17:11] [PASSED] active2
[17:17:11] [PASSED] active-inactive
[17:17:11] [PASSED] inactive-active
[17:17:11] [PASSED] inactive-active-inactive
[17:17:11] [PASSED] inactive-inactive-inactive
[17:17:11] ============== [PASSED] xe_rtp_process_tests ===============
[17:17:11] ===================== [PASSED] xe_rtp ======================
[17:17:11] ==================== xe_wa (1 subtest) =====================
[17:17:11] ======================== xe_wa_gt  =========================
[17:17:11] [PASSED] TIGERLAKE B0
[17:17:11] [PASSED] DG1 A0
[17:17:11] [PASSED] DG1 B0
[17:17:11] [PASSED] ALDERLAKE_S A0
[17:17:11] [PASSED] ALDERLAKE_S B0
[17:17:11] [PASSED] ALDERLAKE_S C0
[17:17:11] [PASSED] ALDERLAKE_S D0
[17:17:11] [PASSED] ALDERLAKE_P A0
[17:17:11] [PASSED] ALDERLAKE_P B0
[17:17:11] [PASSED] ALDERLAKE_P C0
[17:17:11] [PASSED] ALDERLAKE_S RPLS D0
[17:17:11] [PASSED] ALDERLAKE_P RPLU E0
[17:17:11] [PASSED] DG2 G10 C0
[17:17:11] [PASSED] DG2 G11 B1
[17:17:11] [PASSED] DG2 G12 A1
[17:17:11] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:17:11] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[17:17:11] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[17:17:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[17:17:11] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[17:17:11] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[17:17:11] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[17:17:11] ==================== [PASSED] xe_wa_gt =====================
[17:17:11] ====================== [PASSED] xe_wa ======================
[17:17:11] ============================================================
[17:17:11] Testing complete. Ran 793 tests: passed: 765, skipped: 28
[17:17:11] Elapsed time: 37.110s total, 1.852s configuring, 34.542s building, 0.702s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:17:11] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:17:13] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:17:38] Starting KUnit Kernel (1/1)...
[17:17:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:17:38] ============= refcount_interrupt (4 subtests) ==============
[17:17:38] [PASSED] test_single_irq_change
[17:17:38] [PASSED] test_nested_irq_change
[17:17:38] [PASSED] test_multiple_irq_change
[17:17:38] [PASSED] test_irq_save
[17:17:38] =============== [PASSED] refcount_interrupt ================
[17:17:38] ============ drm_test_pick_cmdline (2 subtests) ============
[17:17:38] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[17:17:38] =============== drm_test_pick_cmdline_named  ===============
[17:17:38] [PASSED] NTSC
[17:17:38] [PASSED] NTSC-J
[17:17:38] [PASSED] PAL
[17:17:38] [PASSED] PAL-M
[17:17:38] =========== [PASSED] drm_test_pick_cmdline_named ===========
[17:17:38] ============== [PASSED] drm_test_pick_cmdline ==============
[17:17:38] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[17:17:38] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[17:17:38] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[17:17:38] =========== drm_validate_clone_mode (2 subtests) ===========
[17:17:38] ============== drm_test_check_in_clone_mode  ===============
[17:17:38] [PASSED] in_clone_mode
[17:17:38] [PASSED] not_in_clone_mode
[17:17:38] ========== [PASSED] drm_test_check_in_clone_mode ===========
[17:17:38] =============== drm_test_check_valid_clones  ===============
[17:17:38] [PASSED] not_in_clone_mode
[17:17:38] [PASSED] valid_clone
[17:17:38] [PASSED] invalid_clone
[17:17:38] =========== [PASSED] drm_test_check_valid_clones ===========
[17:17:38] ============= [PASSED] drm_validate_clone_mode =============
[17:17:38] ============= drm_validate_modeset (1 subtest) =============
[17:17:38] [PASSED] drm_test_check_connector_changed_modeset
[17:17:38] ============== [PASSED] drm_validate_modeset ===============
[17:17:38] ====== drm_test_bridge_get_current_state (1 subtest) =======
[17:17:38] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[17:17:38] ======== [PASSED] drm_test_bridge_get_current_state ========
[17:17:38] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[17:17:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[17:17:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[17:17:38] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[17:17:38] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[17:17:38] ============== drm_bridge_alloc (2 subtests) ===============
[17:17:38] [PASSED] drm_test_drm_bridge_alloc_basic
[17:17:38] [PASSED] drm_test_drm_bridge_alloc_get_put
[17:17:38] ================ [PASSED] drm_bridge_alloc =================
[17:17:38] ============= drm_bridge_bus_fmt (5 subtests) ==============
[17:17:38] [PASSED] drm_test_bridge_rgb_yuv_rgb
[17:17:38] [PASSED] drm_test_bridge_must_convert_to_yuv444
[17:17:38] [PASSED] drm_test_bridge_hdmi_auto_rgb
[17:17:38] [PASSED] drm_test_bridge_auto_first
[17:17:38] [PASSED] drm_test_bridge_rgb_yuv_no_path
[17:17:38] =============== [PASSED] drm_bridge_bus_fmt ================
[17:17:38] ============= drm_cmdline_parser (40 subtests) =============
[17:17:38] [PASSED] drm_test_cmdline_force_d_only
[17:17:38] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:17:38] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:17:38] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:17:38] [PASSED] drm_test_cmdline_force_e_only
[17:17:38] [PASSED] drm_test_cmdline_res
[17:17:38] [PASSED] drm_test_cmdline_res_vesa
[17:17:38] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:17:38] [PASSED] drm_test_cmdline_res_rblank
[17:17:38] [PASSED] drm_test_cmdline_res_bpp
[17:17:38] [PASSED] drm_test_cmdline_res_refresh
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:17:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:17:38] [PASSED] drm_test_cmdline_res_margins_force_on
[17:17:38] [PASSED] drm_test_cmdline_res_vesa_margins
[17:17:38] [PASSED] drm_test_cmdline_name
[17:17:38] [PASSED] drm_test_cmdline_name_bpp
[17:17:38] [PASSED] drm_test_cmdline_name_option
[17:17:38] [PASSED] drm_test_cmdline_name_bpp_option
[17:17:38] [PASSED] drm_test_cmdline_rotate_0
[17:17:38] [PASSED] drm_test_cmdline_rotate_90
[17:17:38] [PASSED] drm_test_cmdline_rotate_180
[17:17:38] [PASSED] drm_test_cmdline_rotate_270
[17:17:38] [PASSED] drm_test_cmdline_hmirror
[17:17:38] [PASSED] drm_test_cmdline_vmirror
[17:17:38] [PASSED] drm_test_cmdline_margin_options
[17:17:38] [PASSED] drm_test_cmdline_multiple_options
[17:17:38] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:17:38] [PASSED] drm_test_cmdline_extra_and_option
[17:17:38] [PASSED] drm_test_cmdline_freestanding_options
[17:17:38] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:17:38] [PASSED] drm_test_cmdline_panel_orientation
[17:17:38] ================ drm_test_cmdline_invalid  =================
[17:17:38] [PASSED] margin_only
[17:17:38] [PASSED] interlace_only
[17:17:38] [PASSED] res_missing_x
[17:17:38] [PASSED] res_missing_y
[17:17:38] [PASSED] res_bad_y
[17:17:38] [PASSED] res_missing_y_bpp
[17:17:38] [PASSED] res_bad_bpp
[17:17:38] [PASSED] res_bad_refresh
[17:17:38] [PASSED] res_bpp_refresh_force_on_off
[17:17:38] [PASSED] res_invalid_mode
[17:17:38] [PASSED] res_bpp_wrong_place_mode
[17:17:38] [PASSED] name_bpp_refresh
[17:17:38] [PASSED] name_refresh
[17:17:38] [PASSED] name_refresh_wrong_mode
[17:17:38] [PASSED] name_refresh_invalid_mode
[17:17:38] [PASSED] rotate_multiple
[17:17:38] [PASSED] rotate_invalid_val
[17:17:38] [PASSED] rotate_truncated
[17:17:38] [PASSED] invalid_option
[17:17:38] [PASSED] invalid_tv_option
[17:17:38] [PASSED] truncated_tv_option
[17:17:38] ============ [PASSED] drm_test_cmdline_invalid =============
[17:17:38] =============== drm_test_cmdline_tv_options  ===============
[17:17:38] [PASSED] NTSC
[17:17:38] [PASSED] NTSC_443
[17:17:38] [PASSED] NTSC_J
[17:17:38] [PASSED] PAL
[17:17:38] [PASSED] PAL_M
[17:17:38] [PASSED] PAL_N
[17:17:38] [PASSED] SECAM
[17:17:38] [PASSED] MONO_525
[17:17:38] [PASSED] MONO_625
[17:17:38] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:17:38] =============== [PASSED] drm_cmdline_parser ================
[17:17:38] ========== drmm_connector_hdmi_init (20 subtests) ==========
[17:17:38] [PASSED] drm_test_connector_hdmi_init_valid
[17:17:38] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:17:38] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:17:38] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:17:38] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:17:38] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:17:38] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:17:38] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:17:38] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[17:17:38] [PASSED] supported_formats=0x9 yuv420_allowed=1
[17:17:38] [PASSED] supported_formats=0x9 yuv420_allowed=0
[17:17:38] [PASSED] supported_formats=0x5 yuv420_allowed=1
[17:17:38] [PASSED] supported_formats=0x5 yuv420_allowed=0
[17:17:38] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[17:17:38] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:17:38] [PASSED] drm_test_connector_hdmi_init_null_product
[17:17:38] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:17:38] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:17:38] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:17:38] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:17:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:17:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:17:38] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:17:38] ========= drm_test_connector_hdmi_init_type_valid  =========
[17:17:38] [PASSED] HDMI-A
[17:17:38] [PASSED] HDMI-B
[17:17:38] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:17:38] ======== drm_test_connector_hdmi_init_type_invalid  ========
[17:17:38] [PASSED] Unknown
[17:17:38] [PASSED] VGA
[17:17:38] [PASSED] DVI-I
[17:17:38] [PASSED] DVI-D
[17:17:38] [PASSED] DVI-A
[17:17:38] [PASSED] Composite
[17:17:38] [PASSED] SVIDEO
[17:17:38] [PASSED] LVDS
[17:17:38] [PASSED] Component
[17:17:38] [PASSED] DIN
[17:17:38] [PASSED] DP
[17:17:38] [PASSED] TV
[17:17:38] [PASSED] eDP
[17:17:38] [PASSED] Virtual
[17:17:38] [PASSED] DSI
[17:17:38] [PASSED] DPI
[17:17:38] [PASSED] Writeback
[17:17:38] [PASSED] SPI
[17:17:38] [PASSED] USB
[17:17:38] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:17:38] ============ [PASSED] drmm_connector_hdmi_init =============
[17:17:38] ============= drmm_connector_init (3 subtests) =============
[17:17:38] [PASSED] drm_test_drmm_connector_init
[17:17:38] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:17:38] ========= drm_test_drmm_connector_init_type_valid  =========
[17:17:38] [PASSED] Unknown
[17:17:38] [PASSED] VGA
[17:17:38] [PASSED] DVI-I
[17:17:38] [PASSED] DVI-D
[17:17:38] [PASSED] DVI-A
[17:17:38] [PASSED] Composite
[17:17:38] [PASSED] SVIDEO
[17:17:38] [PASSED] LVDS
[17:17:38] [PASSED] Component
[17:17:38] [PASSED] DIN
[17:17:38] [PASSED] DP
[17:17:38] [PASSED] HDMI-A
[17:17:38] [PASSED] HDMI-B
[17:17:38] [PASSED] TV
[17:17:38] [PASSED] eDP
[17:17:38] [PASSED] Virtual
[17:17:38] [PASSED] DSI
[17:17:38] [PASSED] DPI
[17:17:38] [PASSED] Writeback
[17:17:38] [PASSED] SPI
[17:17:38] [PASSED] USB
[17:17:38] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:17:38] =============== [PASSED] drmm_connector_init ===============
[17:17:38] ========= drm_connector_dynamic_init (6 subtests) ==========
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_init
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_init_properties
[17:17:38] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[17:17:38] [PASSED] Unknown
[17:17:38] [PASSED] VGA
[17:17:38] [PASSED] DVI-I
[17:17:38] [PASSED] DVI-D
[17:17:38] [PASSED] DVI-A
[17:17:38] [PASSED] Composite
[17:17:38] [PASSED] SVIDEO
[17:17:38] [PASSED] LVDS
[17:17:38] [PASSED] Component
[17:17:38] [PASSED] DIN
[17:17:38] [PASSED] DP
[17:17:38] [PASSED] HDMI-A
[17:17:38] [PASSED] HDMI-B
[17:17:38] [PASSED] TV
[17:17:38] [PASSED] eDP
[17:17:38] [PASSED] Virtual
[17:17:38] [PASSED] DSI
[17:17:38] [PASSED] DPI
[17:17:38] [PASSED] Writeback
[17:17:38] [PASSED] SPI
[17:17:38] [PASSED] USB
[17:17:38] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[17:17:38] ======== drm_test_drm_connector_dynamic_init_name  =========
[17:17:38] [PASSED] Unknown
[17:17:38] [PASSED] VGA
[17:17:38] [PASSED] DVI-I
[17:17:38] [PASSED] DVI-D
[17:17:38] [PASSED] DVI-A
[17:17:38] [PASSED] Composite
[17:17:38] [PASSED] SVIDEO
[17:17:38] [PASSED] LVDS
[17:17:38] [PASSED] Component
[17:17:38] [PASSED] DIN
[17:17:38] [PASSED] DP
[17:17:38] [PASSED] HDMI-A
[17:17:38] [PASSED] HDMI-B
[17:17:38] [PASSED] TV
[17:17:38] [PASSED] eDP
[17:17:38] [PASSED] Virtual
[17:17:38] [PASSED] DSI
[17:17:38] [PASSED] DPI
[17:17:38] [PASSED] Writeback
[17:17:38] [PASSED] SPI
[17:17:38] [PASSED] USB
[17:17:38] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[17:17:38] =========== [PASSED] drm_connector_dynamic_init ============
[17:17:38] ==== drm_connector_dynamic_register_early (4 subtests) =====
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[17:17:38] ====== [PASSED] drm_connector_dynamic_register_early =======
[17:17:38] ======= drm_connector_dynamic_register (7 subtests) ========
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[17:17:38] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[17:17:38] ========= [PASSED] drm_connector_dynamic_register ==========
[17:17:38] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:17:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:17:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:17:38] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:17:38] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:17:38] ========== drm_test_get_tv_mode_from_name_valid  ===========
[17:17:38] [PASSED] NTSC
[17:17:38] [PASSED] NTSC-443
[17:17:38] [PASSED] NTSC-J
[17:17:38] [PASSED] PAL
[17:17:38] [PASSED] PAL-M
[17:17:38] [PASSED] PAL-N
[17:17:38] [PASSED] SECAM
[17:17:38] [PASSED] Mono
[17:17:38] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:17:38] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:17:38] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:17:38] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:17:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:17:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:17:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:17:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:17:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:17:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:17:38] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[17:17:38] [PASSED] VIC 96
[17:17:38] [PASSED] VIC 97
[17:17:38] [PASSED] VIC 101
[17:17:38] [PASSED] VIC 102
[17:17:38] [PASSED] VIC 106
[17:17:38] [PASSED] VIC 107
[17:17:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:17:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:17:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:17:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:17:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:17:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:17:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:17:38] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:17:38] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[17:17:38] [PASSED] Automatic
[17:17:38] [PASSED] Full
[17:17:38] [PASSED] Limited 16:235
[17:17:38] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:17:38] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:17:38] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:17:38] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:17:38] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[17:17:38] [PASSED] RGB
[17:17:38] [PASSED] YUV 4:2:0
[17:17:38] [PASSED] YUV 4:2:2
[17:17:38] [PASSED] YUV 4:4:4
[17:17:38] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:17:38] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:17:38] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:17:38] ============= drm_damage_helper (21 subtests) ==============
[17:17:38] [PASSED] drm_test_damage_iter_no_damage
[17:17:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:17:38] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:17:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:17:38] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:17:38] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:17:38] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:17:38] [PASSED] drm_test_damage_iter_simple_damage
[17:17:38] [PASSED] drm_test_damage_iter_single_damage
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:17:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:17:38] [PASSED] drm_test_damage_iter_damage
[17:17:38] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:17:38] [PASSED] drm_test_damage_iter_damage_one_outside
[17:17:38] [PASSED] drm_test_damage_iter_damage_src_moved
[17:17:38] [PASSED] drm_test_damage_iter_damage_not_visible
[17:17:38] ================ [PASSED] drm_damage_helper ================
[17:17:38] ============== drm_dp_mst_helper (3 subtests) ==============
[17:17:38] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[17:17:38] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:17:38] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:17:38] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:17:38] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:17:38] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:17:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:17:38] ============== drm_test_dp_mst_calc_pbn_div  ===============
[17:17:38] [PASSED] Link rate 2000000 lane count 4
[17:17:38] [PASSED] Link rate 2000000 lane count 2
[17:17:38] [PASSED] Link rate 2000000 lane count 1
[17:17:38] [PASSED] Link rate 1350000 lane count 4
[17:17:38] [PASSED] Link rate 1350000 lane count 2
[17:17:38] [PASSED] Link rate 1350000 lane count 1
[17:17:38] [PASSED] Link rate 1000000 lane count 4
[17:17:38] [PASSED] Link rate 1000000 lane count 2
[17:17:38] [PASSED] Link rate 1000000 lane count 1
[17:17:38] [PASSED] Link rate 810000 lane count 4
[17:17:38] [PASSED] Link rate 810000 lane count 2
[17:17:38] [PASSED] Link rate 810000 lane count 1
[17:17:38] [PASSED] Link rate 540000 lane count 4
[17:17:38] [PASSED] Link rate 540000 lane count 2
[17:17:38] [PASSED] Link rate 540000 lane count 1
[17:17:38] [PASSED] Link rate 270000 lane count 4
[17:17:38] [PASSED] Link rate 270000 lane count 2
[17:17:38] [PASSED] Link rate 270000 lane count 1
[17:17:38] [PASSED] Link rate 162000 lane count 4
[17:17:38] [PASSED] Link rate 162000 lane count 2
[17:17:38] [PASSED] Link rate 162000 lane count 1
[17:17:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:17:38] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[17:17:38] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:17:38] [PASSED] DP_POWER_UP_PHY with port number
[17:17:38] [PASSED] DP_POWER_DOWN_PHY with port number
[17:17:38] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:17:38] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:17:38] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:17:38] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:17:38] [PASSED] DP_QUERY_PAYLOAD with port number
[17:17:38] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:17:38] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:17:38] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:17:38] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:17:38] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:17:38] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:17:38] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:17:38] [PASSED] DP_REMOTE_I2C_READ with port number
[17:17:38] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:17:38] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:17:38] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:17:38] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:17:38] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:17:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:17:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:17:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:17:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:17:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:17:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:17:38] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:17:38] ================ [PASSED] drm_dp_mst_helper ================
[17:17:38] ================== drm_exec (7 subtests) ===================
[17:17:38] [PASSED] sanitycheck
[17:17:38] [PASSED] test_lock
[17:17:38] [PASSED] test_lock_unlock
[17:17:38] [PASSED] test_duplicates
[17:17:38] [PASSED] test_prepare
[17:17:38] [PASSED] test_prepare_array
[17:17:38] [PASSED] test_multiple_loops
[17:17:38] ==================== [PASSED] drm_exec =====================
[17:17:38] =========== drm_format_helper_test (17 subtests) ===========
[17:17:38] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:17:38] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:17:38] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:17:38] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:17:38] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:17:38] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:17:38] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:17:38] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[17:17:38] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:17:38] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:17:38] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:17:38] ============== drm_test_fb_xrgb8888_to_mono  ===============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:17:38] ==================== drm_test_fb_swab  =====================
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ================ [PASSED] drm_test_fb_swab =================
[17:17:38] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:17:38] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[17:17:38] [PASSED] single_pixel_source_buffer
[17:17:38] [PASSED] single_pixel_clip_rectangle
[17:17:38] [PASSED] well_known_colors
[17:17:38] [PASSED] destination_pitch
[17:17:38] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:17:38] ================= drm_test_fb_clip_offset  =================
[17:17:38] [PASSED] pass through
[17:17:38] [PASSED] horizontal offset
[17:17:38] [PASSED] vertical offset
[17:17:38] [PASSED] horizontal and vertical offset
[17:17:38] [PASSED] horizontal offset (custom pitch)
[17:17:38] [PASSED] vertical offset (custom pitch)
[17:17:38] [PASSED] horizontal and vertical offset (custom pitch)
[17:17:38] ============= [PASSED] drm_test_fb_clip_offset =============
[17:17:38] =================== drm_test_fb_memcpy  ====================
[17:17:38] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:17:38] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:17:38] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:17:38] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:17:38] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:17:38] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:17:38] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:17:38] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:17:38] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:17:38] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:17:38] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:17:38] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:17:38] =============== [PASSED] drm_test_fb_memcpy ================
[17:17:38] ============= [PASSED] drm_format_helper_test ==============
[17:17:38] ================= drm_format (18 subtests) =================
[17:17:38] [PASSED] drm_test_format_block_width_invalid
[17:17:38] [PASSED] drm_test_format_block_width_one_plane
[17:17:38] [PASSED] drm_test_format_block_width_two_plane
[17:17:38] [PASSED] drm_test_format_block_width_three_plane
[17:17:38] [PASSED] drm_test_format_block_width_tiled
[17:17:38] [PASSED] drm_test_format_block_height_invalid
[17:17:38] [PASSED] drm_test_format_block_height_one_plane
[17:17:38] [PASSED] drm_test_format_block_height_two_plane
[17:17:38] [PASSED] drm_test_format_block_height_three_plane
[17:17:38] [PASSED] drm_test_format_block_height_tiled
[17:17:38] [PASSED] drm_test_format_min_pitch_invalid
[17:17:38] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:17:38] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:17:38] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:17:38] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:17:38] [PASSED] drm_test_format_min_pitch_two_plane
[17:17:38] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:17:38] [PASSED] drm_test_format_min_pitch_tiled
[17:17:38] =================== [PASSED] drm_format ====================
[17:17:38] ============== drm_framebuffer (10 subtests) ===============
[17:17:38] ========== drm_test_framebuffer_check_src_coords  ==========
[17:17:38] [PASSED] Success: source fits into fb
[17:17:38] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:17:38] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:17:38] [PASSED] Fail: overflowing fb with source width
[17:17:38] [PASSED] Fail: overflowing fb with source height
[17:17:38] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:17:38] [PASSED] drm_test_framebuffer_cleanup
[17:17:38] =============== drm_test_framebuffer_create  ===============
[17:17:38] [PASSED] ABGR8888 normal sizes
[17:17:38] [PASSED] ABGR8888 max sizes
[17:17:38] [PASSED] ABGR8888 pitch greater than min required
[17:17:38] [PASSED] ABGR8888 pitch less than min required
[17:17:38] [PASSED] ABGR8888 Invalid width
[17:17:38] [PASSED] ABGR8888 Invalid buffer handle
[17:17:38] [PASSED] No pixel format
[17:17:38] [PASSED] ABGR8888 Width 0
[17:17:38] [PASSED] ABGR8888 Height 0
[17:17:38] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:17:38] [PASSED] ABGR8888 Large buffer offset
[17:17:38] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:17:38] [PASSED] ABGR8888 Invalid flag
[17:17:38] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:17:38] [PASSED] ABGR8888 Valid buffer modifier
[17:17:38] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:17:38] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] NV12 Normal sizes
[17:17:38] [PASSED] NV12 Max sizes
[17:17:38] [PASSED] NV12 Invalid pitch
[17:17:38] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:17:38] [PASSED] NV12 different  modifier per-plane
[17:17:38] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:17:38] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] NV12 Modifier for inexistent plane
[17:17:38] [PASSED] NV12 Handle for inexistent plane
[17:17:38] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:17:38] [PASSED] YVU420 Normal sizes
[17:17:38] [PASSED] YVU420 Max sizes
[17:17:38] [PASSED] YVU420 Invalid pitch
[17:17:38] [PASSED] YVU420 Different pitches
[17:17:38] [PASSED] YVU420 Different buffer offsets/pitches
[17:17:38] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:17:38] [PASSED] YVU420 Valid modifier
[17:17:38] [PASSED] YVU420 Different modifiers per plane
[17:17:38] [PASSED] YVU420 Modifier for inexistent plane
[17:17:38] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:17:38] [PASSED] X0L2 Normal sizes
[17:17:38] [PASSED] X0L2 Max sizes
[17:17:38] [PASSED] X0L2 Invalid pitch
[17:17:38] [PASSED] X0L2 Pitch greater than minimum required
[17:17:38] [PASSED] X0L2 Handle for inexistent plane
[17:17:38] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:17:38] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:17:38] [PASSED] X0L2 Valid modifier
[17:17:38] [PASSED] X0L2 Modifier for inexistent plane
[17:17:38] =========== [PASSED] drm_test_framebuffer_create ===========
[17:17:38] [PASSED] drm_test_framebuffer_free
[17:17:38] [PASSED] drm_test_framebuffer_init
[17:17:38] [PASSED] drm_test_framebuffer_init_bad_format
[17:17:38] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:17:38] [PASSED] drm_test_framebuffer_lookup
[17:17:38] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:17:38] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:17:38] ================= [PASSED] drm_framebuffer =================
[17:17:38] ================ drm_gem_shmem (8 subtests) ================
[17:17:38] [PASSED] drm_gem_shmem_test_obj_create
[17:17:38] [PASSED] drm_gem_shmem_test_obj_create_private
[17:17:38] [PASSED] drm_gem_shmem_test_pin_pages
[17:17:38] [PASSED] drm_gem_shmem_test_vmap
[17:17:38] [PASSED] drm_gem_shmem_test_get_sg_table
[17:17:38] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:17:38] [PASSED] drm_gem_shmem_test_madvise
[17:17:38] [PASSED] drm_gem_shmem_test_purge
[17:17:38] ================== [PASSED] drm_gem_shmem ==================
[17:17:38] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:17:38] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[17:17:38] [PASSED] Automatic
[17:17:38] [PASSED] Full
[17:17:38] [PASSED] Limited 16:235
[17:17:38] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:17:38] [PASSED] drm_test_check_disable_connector
[17:17:38] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:17:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[17:17:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[17:17:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[17:17:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[17:17:38] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[17:17:38] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:17:38] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:17:38] [PASSED] drm_test_check_output_bpc_dvi
[17:17:38] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:17:38] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:17:38] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:17:38] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:17:38] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:17:38] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:17:38] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:17:38] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:17:38] ============ drm_test_check_hdmi_color_format  =============
[17:17:38] [PASSED] AUTO -> RGB
[17:17:38] [PASSED] YCBCR422 -> YUV422
[17:17:38] [PASSED] YCBCR420 -> YUV420
[17:17:38] [PASSED] YCBCR444 -> YUV444
[17:17:38] [PASSED] RGB -> RGB
[17:17:38] ======== [PASSED] drm_test_check_hdmi_color_format =========
[17:17:38] ======== drm_test_check_hdmi_color_format_420_only  ========
[17:17:38] [PASSED] RGB should fail
[17:17:38] [PASSED] YUV444 should fail
[17:17:38] [PASSED] YUV422 should fail
[17:17:38] [PASSED] YUV420 should work
[17:17:38] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[17:17:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:17:38] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:17:38] [PASSED] drm_test_check_broadcast_rgb_value
[17:17:38] [PASSED] drm_test_check_bpc_8_value
[17:17:38] [PASSED] drm_test_check_bpc_10_value
[17:17:38] [PASSED] drm_test_check_bpc_12_value
[17:17:38] [PASSED] drm_test_check_format_value
[17:17:38] [PASSED] drm_test_check_tmds_char_value
[17:17:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:17:38] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[17:17:38] [PASSED] drm_test_check_mode_valid
[17:17:38] [PASSED] drm_test_check_mode_valid_reject
[17:17:38] [PASSED] drm_test_check_mode_valid_reject_rate
[17:17:38] [PASSED] drm_test_check_mode_valid_reject_max_clock
[17:17:38] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[17:17:38] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[17:17:38] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[17:17:38] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[17:17:38] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[17:17:38] [PASSED] drm_test_check_infoframes
[17:17:38] [PASSED] drm_test_check_reject_avi_infoframe
[17:17:38] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[17:17:38] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[17:17:38] [PASSED] drm_test_check_reject_audio_infoframe
[17:17:38] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[17:17:38] ================= drm_managed (2 subtests) =================
[17:17:38] [PASSED] drm_test_managed_release_action
[17:17:38] [PASSED] drm_test_managed_run_action
[17:17:38] =================== [PASSED] drm_managed ===================
[17:17:38] =================== drm_mm (6 subtests) ====================
[17:17:38] [PASSED] drm_test_mm_init
[17:17:38] [PASSED] drm_test_mm_debug
[17:17:38] [PASSED] drm_test_mm_align32
[17:17:38] [PASSED] drm_test_mm_align64
[17:17:38] [PASSED] drm_test_mm_lowest
[17:17:38] [PASSED] drm_test_mm_highest
[17:17:38] ===================== [PASSED] drm_mm ======================
[17:17:38] ============= drm_modes_analog_tv (5 subtests) =============
[17:17:38] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:17:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:17:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:17:38] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:17:38] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:17:38] =============== [PASSED] drm_modes_analog_tv ===============
[17:17:38] ============== drm_plane_helper (2 subtests) ===============
[17:17:38] =============== drm_test_check_plane_state  ================
[17:17:38] [PASSED] clipping_simple
[17:17:38] [PASSED] clipping_rotate_reflect
[17:17:38] [PASSED] positioning_simple
[17:17:38] [PASSED] upscaling
[17:17:38] [PASSED] downscaling
[17:17:38] [PASSED] rounding1
[17:17:38] [PASSED] rounding2
[17:17:38] [PASSED] rounding3
[17:17:38] [PASSED] rounding4
[17:17:38] =========== [PASSED] drm_test_check_plane_state ============
[17:17:38] =========== drm_test_check_invalid_plane_state  ============
[17:17:38] [PASSED] positioning_invalid
[17:17:38] [PASSED] upscaling_invalid
[17:17:38] [PASSED] downscaling_invalid
[17:17:38] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:17:38] ================ [PASSED] drm_plane_helper =================
[17:17:38] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:17:38] ====== drm_test_connector_helper_tv_get_modes_check  =======
[17:17:38] [PASSED] None
[17:17:38] [PASSED] PAL
[17:17:38] [PASSED] NTSC
[17:17:38] [PASSED] Both, NTSC Default
[17:17:38] [PASSED] Both, PAL Default
[17:17:38] [PASSED] Both, NTSC Default, with PAL on command-line
[17:17:38] [PASSED] Both, PAL Default, with NTSC on command-line
[17:17:38] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:17:38] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:17:38] ================== drm_rect (9 subtests) ===================
[17:17:38] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:17:38] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:17:38] [PASSED] drm_test_rect_clip_scaled_clipped
[17:17:38] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:17:38] ================= drm_test_rect_intersect  =================
[17:17:38] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:17:38] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:17:38] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:17:38] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:17:38] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:17:38] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:17:38] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:17:38] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:17:38] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:17:38] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:17:38] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:17:38] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:17:38] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:17:38] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:17:38] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:17:38] ============= [PASSED] drm_test_rect_intersect =============
[17:17:38] ================ drm_test_rect_calc_hscale  ================
[17:17:38] [PASSED] normal use
[17:17:38] [PASSED] out of max range
[17:17:38] [PASSED] out of min range
[17:17:38] [PASSED] zero dst
[17:17:38] [PASSED] negative src
[17:17:38] [PASSED] negative dst
[17:17:38] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:17:38] ================ drm_test_rect_calc_vscale  ================
[17:17:38] [PASSED] normal use
[17:17:38] [PASSED] out of max range
[17:17:38] [PASSED] out of min range
[17:17:38] [PASSED] zero dst
[17:17:38] [PASSED] negative src
[17:17:38] [PASSED] negative dst
[17:17:38] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:17:38] ================== drm_test_rect_rotate  ===================
[17:17:38] [PASSED] reflect-x
[17:17:38] [PASSED] reflect-y
[17:17:38] [PASSED] rotate-0
[17:17:38] [PASSED] rotate-90
[17:17:38] [PASSED] rotate-180
[17:17:38] [PASSED] rotate-270
[17:17:38] ============== [PASSED] drm_test_rect_rotate ===============
[17:17:38] ================ drm_test_rect_rotate_inv  =================
[17:17:38] [PASSED] reflect-x
[17:17:38] [PASSED] reflect-y
[17:17:38] [PASSED] rotate-0
[17:17:38] [PASSED] rotate-90
[17:17:38] [PASSED] rotate-180
[17:17:38] [PASSED] rotate-270
[17:17:38] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:17:38] ==================== [PASSED] drm_rect =====================
[17:17:38] ============ drm_sysfb_modeset_test (1 subtest) ============
[17:17:38] ============ drm_test_sysfb_build_fourcc_list  =============
[17:17:38] [PASSED] no native formats
[17:17:38] [PASSED] XRGB8888 as native format
[17:17:38] [PASSED] remove duplicates
[17:17:38] [PASSED] convert alpha formats
[17:17:38] [PASSED] random formats
[17:17:38] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[17:17:38] ============= [PASSED] drm_sysfb_modeset_test ==============
[17:17:38] ================== drm_fixp (2 subtests) ===================
[17:17:38] [PASSED] drm_test_int2fixp
[17:17:38] [PASSED] drm_test_sm2fixp
[17:17:38] ==================== [PASSED] drm_fixp =====================
[17:17:38] ============================================================
[17:17:38] Testing complete. Ran 641 tests: passed: 641
[17:17:38] Elapsed time: 27.387s total, 1.833s configuring, 25.387s building, 0.146s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:17:38] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:17:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:17:50] Starting KUnit Kernel (1/1)...
[17:17:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:17:50] ============= refcount_interrupt (4 subtests) ==============
[17:17:50] [PASSED] test_single_irq_change
[17:17:50] [PASSED] test_nested_irq_change
[17:17:50] [PASSED] test_multiple_irq_change
[17:17:50] [PASSED] test_irq_save
[17:17:50] =============== [PASSED] refcount_interrupt ================
[17:17:50] ================= ttm_device (5 subtests) ==================
[17:17:50] [PASSED] ttm_device_init_basic
[17:17:50] [PASSED] ttm_device_init_multiple
[17:17:50] [PASSED] ttm_device_fini_basic
[17:17:50] [PASSED] ttm_device_init_no_vma_man
[17:17:50] ================== ttm_device_init_pools  ==================
[17:17:50] [PASSED] No DMA allocations, no DMA32 required
[17:17:50] [PASSED] DMA allocations, DMA32 required
[17:17:50] [PASSED] No DMA allocations, DMA32 required
[17:17:50] [PASSED] DMA allocations, no DMA32 required
[17:17:50] ============== [PASSED] ttm_device_init_pools ==============
[17:17:50] =================== [PASSED] ttm_device ====================
[17:17:50] ================== ttm_pool (8 subtests) ===================
[17:17:50] ================== ttm_pool_alloc_basic  ===================
[17:17:50] [PASSED] One page
[17:17:50] [PASSED] More than one page
[17:17:50] [PASSED] Above the allocation limit
[17:17:50] [PASSED] One page, with coherent DMA mappings enabled
[17:17:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:17:50] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:17:50] ============== ttm_pool_alloc_basic_dma_addr  ==============
[17:17:50] [PASSED] One page
[17:17:50] [PASSED] More than one page
[17:17:50] [PASSED] Above the allocation limit
[17:17:50] [PASSED] One page, with coherent DMA mappings enabled
[17:17:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:17:50] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:17:50] [PASSED] ttm_pool_alloc_order_caching_match
[17:17:50] [PASSED] ttm_pool_alloc_caching_mismatch
[17:17:50] [PASSED] ttm_pool_alloc_order_mismatch
[17:17:50] [PASSED] ttm_pool_free_dma_alloc
[17:17:50] [PASSED] ttm_pool_free_no_dma_alloc
[17:17:50] [PASSED] ttm_pool_fini_basic
[17:17:50] ==================== [PASSED] ttm_pool =====================
[17:17:50] ================ ttm_resource (8 subtests) =================
[17:17:50] ================= ttm_resource_init_basic  =================
[17:17:50] [PASSED] Init resource in TTM_PL_SYSTEM
[17:17:50] [PASSED] Init resource in TTM_PL_VRAM
[17:17:50] [PASSED] Init resource in a private placement
[17:17:50] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:17:50] ============= [PASSED] ttm_resource_init_basic =============
[17:17:50] [PASSED] ttm_resource_init_pinned
[17:17:50] [PASSED] ttm_resource_fini_basic
[17:17:50] [PASSED] ttm_resource_manager_init_basic
[17:17:50] [PASSED] ttm_resource_manager_usage_basic
[17:17:50] [PASSED] ttm_resource_manager_set_used_basic
[17:17:50] [PASSED] ttm_sys_man_alloc_basic
[17:17:50] [PASSED] ttm_sys_man_free_basic
[17:17:50] ================== [PASSED] ttm_resource ===================
[17:17:50] =================== ttm_tt (15 subtests) ===================
[17:17:50] ==================== ttm_tt_init_basic  ====================
[17:17:50] [PASSED] Page-aligned size
[17:17:50] [PASSED] Extra pages requested
[17:17:50] ================ [PASSED] ttm_tt_init_basic ================
[17:17:50] [PASSED] ttm_tt_init_misaligned
[17:17:50] [PASSED] ttm_tt_fini_basic
[17:17:50] [PASSED] ttm_tt_fini_sg
[17:17:50] [PASSED] ttm_tt_fini_shmem
[17:17:50] [PASSED] ttm_tt_create_basic
[17:17:50] [PASSED] ttm_tt_create_invalid_bo_type
[17:17:50] [PASSED] ttm_tt_create_ttm_exists
[17:17:50] [PASSED] ttm_tt_create_failed
[17:17:50] [PASSED] ttm_tt_destroy_basic
[17:17:50] [PASSED] ttm_tt_populate_null_ttm
[17:17:50] [PASSED] ttm_tt_populate_populated_ttm
[17:17:50] [PASSED] ttm_tt_unpopulate_basic
[17:17:50] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:17:50] [PASSED] ttm_tt_swapin_basic
[17:17:50] ===================== [PASSED] ttm_tt ======================
[17:17:50] =================== ttm_bo (14 subtests) ===================
[17:17:50] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[17:17:50] [PASSED] Cannot be interrupted and sleeps
[17:17:50] [PASSED] Cannot be interrupted, locks straight away
[17:17:50] [PASSED] Can be interrupted, sleeps
[17:17:50] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:17:50] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:17:50] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:17:50] [PASSED] ttm_bo_reserve_double_resv
[17:17:50] [PASSED] ttm_bo_reserve_interrupted
[17:17:50] [PASSED] ttm_bo_reserve_deadlock
[17:17:50] [PASSED] ttm_bo_unreserve_basic
[17:17:50] [PASSED] ttm_bo_unreserve_pinned
[17:17:50] [PASSED] ttm_bo_unreserve_bulk
[17:17:50] [PASSED] ttm_bo_fini_basic
[17:17:50] [PASSED] ttm_bo_fini_shared_resv
[17:17:50] [PASSED] ttm_bo_pin_basic
[17:17:50] [PASSED] ttm_bo_pin_unpin_resource
[17:17:50] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:17:50] ===================== [PASSED] ttm_bo ======================
[17:17:50] ============== ttm_bo_validate (22 subtests) ===============
[17:17:50] ============== ttm_bo_init_reserved_sys_man  ===============
[17:17:50] [PASSED] Buffer object for userspace
[17:17:50] [PASSED] Kernel buffer object
[17:17:50] [PASSED] Shared buffer object
[17:17:50] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:17:50] ============== ttm_bo_init_reserved_mock_man  ==============
[17:17:50] [PASSED] Buffer object for userspace
[17:17:50] [PASSED] Kernel buffer object
[17:17:50] [PASSED] Shared buffer object
[17:17:50] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:17:50] [PASSED] ttm_bo_init_reserved_resv
[17:17:50] ================== ttm_bo_validate_basic  ==================
[17:17:50] [PASSED] Buffer object for userspace
[17:17:50] [PASSED] Kernel buffer object
[17:17:50] [PASSED] Shared buffer object
[17:17:50] ============== [PASSED] ttm_bo_validate_basic ==============
[17:17:50] [PASSED] ttm_bo_validate_invalid_placement
[17:17:50] ============= ttm_bo_validate_same_placement  ==============
[17:17:50] [PASSED] System manager
[17:17:50] [PASSED] VRAM manager
[17:17:50] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:17:50] [PASSED] ttm_bo_validate_failed_alloc
[17:17:50] [PASSED] ttm_bo_validate_pinned
[17:17:50] [PASSED] ttm_bo_validate_busy_placement
[17:17:50] ================ ttm_bo_validate_multihop  =================
[17:17:50] [PASSED] Buffer object for userspace
[17:17:50] [PASSED] Kernel buffer object
[17:17:50] [PASSED] Shared buffer object
[17:17:50] ============ [PASSED] ttm_bo_validate_multihop =============
[17:17:50] ========== ttm_bo_validate_no_placement_signaled  ==========
[17:17:50] [PASSED] Buffer object in system domain, no page vector
[17:17:50] [PASSED] Buffer object in system domain with an existing page vector
[17:17:50] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:17:50] ======== ttm_bo_validate_no_placement_not_signaled  ========
[17:17:50] [PASSED] Buffer object for userspace
[17:17:50] [PASSED] Kernel buffer object
[17:17:50] [PASSED] Shared buffer object
[17:17:50] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:17:50] [PASSED] ttm_bo_validate_move_fence_signaled
[17:17:50] ========= ttm_bo_validate_move_fence_not_signaled  =========
[17:17:50] [PASSED] Waits for GPU
[17:17:50] [PASSED] Tries to lock straight away
[17:17:50] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:17:50] [PASSED] ttm_bo_validate_swapout
[17:17:50] [PASSED] ttm_bo_validate_happy_evict
[17:17:50] [PASSED] ttm_bo_validate_all_pinned_evict
[17:17:50] [PASSED] ttm_bo_validate_allowed_only_evict
[17:17:50] [PASSED] ttm_bo_validate_deleted_evict
[17:17:50] [PASSED] ttm_bo_validate_busy_domain_evict
[17:17:50] [PASSED] ttm_bo_validate_evict_gutting
[17:17:50] [PASSED] ttm_bo_validate_recrusive_evict
[17:17:50] ================= [PASSED] ttm_bo_validate =================
[17:17:50] ============================================================
[17:17:50] Testing complete. Ran 106 tests: passed: 106
[17:17:50] Elapsed time: 12.124s total, 1.754s configuring, 10.155s building, 0.185s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[17:17:50] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:17:52] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[17:18:01] Starting KUnit Kernel (1/1)...
[17:18:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:18:01] ============= refcount_interrupt (4 subtests) ==============
[17:18:01] [PASSED] test_single_irq_change
[17:18:01] [PASSED] test_nested_irq_change
[17:18:01] [PASSED] test_multiple_irq_change
[17:18:01] [PASSED] test_irq_save
[17:18:01] =============== [PASSED] refcount_interrupt ================
[17:18:01] =============== dma-buf-fence (12 subtests) ================
[17:18:01] [PASSED] test_sanitycheck
[17:18:01] [PASSED] test_signaling
[17:18:01] [PASSED] test_add_callback
[17:18:01] [PASSED] test_late_add_callback
[17:18:01] [PASSED] test_rm_callback
[17:18:01] [PASSED] test_late_rm_callback
[17:18:01] [PASSED] test_status
[17:18:01] [PASSED] test_error
[17:18:01] [PASSED] test_wait
[17:18:01] [PASSED] test_wait_timeout
[17:18:01] [PASSED] test_stub
[17:18:01] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[17:18:01] ================== [PASSED] dma-buf-fence ==================
[17:18:01] ============ dma-buf-fence-chain (11 subtests) =============
[17:18:01] [PASSED] test_sanitycheck
[17:18:01] [PASSED] test_find_seqno
[17:18:01] [PASSED] test_find_signaled
[17:18:01] [PASSED] test_find_out_of_order
[17:18:06] [PASSED] test_find_gap
[17:18:06] [PASSED] test_find_race
[17:18:06] [PASSED] test_signal_forward
[17:18:06] [PASSED] test_signal_backward
[17:18:06] [PASSED] test_wait_forward
[17:18:06] [PASSED] test_wait_backward
[17:18:06] [PASSED] test_wait_random
[17:18:06] =============== [PASSED] dma-buf-fence-chain ===============
[17:18:06] ============ dma-buf-fence-unwrap (10 subtests) ============
[17:18:06] [PASSED] test_sanitycheck
[17:18:06] [PASSED] test_unwrap_array
[17:18:06] [PASSED] test_unwrap_chain
[17:18:06] [PASSED] test_unwrap_chain_array
[17:18:06] [PASSED] test_unwrap_merge
[17:18:06] [PASSED] test_unwrap_merge_duplicate
[17:18:06] [PASSED] test_unwrap_merge_seqno
[17:18:06] [PASSED] test_unwrap_merge_order
[17:18:06] [PASSED] test_unwrap_merge_complex
[17:18:06] [PASSED] test_unwrap_merge_complex_seqno
[17:18:06] ============== [PASSED] dma-buf-fence-unwrap ===============
[17:18:06] ================ dma-buf-resv (5 subtests) =================
[17:18:06] [PASSED] test_sanitycheck
[17:18:06] ===================== test_signaling  ======================
[17:18:06] [PASSED] kernel
[17:18:06] [PASSED] write
[17:18:06] [PASSED] read
[17:18:06] [PASSED] bookkeep
[17:18:06] ================= [PASSED] test_signaling ==================
[17:18:06] ====================== test_for_each  ======================
[17:18:06] [PASSED] kernel
[17:18:06] [PASSED] write
[17:18:06] [PASSED] read
[17:18:06] [PASSED] bookkeep
[17:18:06] ================== [PASSED] test_for_each ==================
[17:18:06] ================= test_for_each_unlocked  ==================
[17:18:06] [PASSED] kernel
[17:18:06] [PASSED] write
[17:18:06] [PASSED] read
[17:18:06] [PASSED] bookkeep
[17:18:06] ============= [PASSED] test_for_each_unlocked ==============
[17:18:06] ===================== test_get_fences  =====================
[17:18:06] [PASSED] kernel
[17:18:06] [PASSED] write
[17:18:06] [PASSED] read
[17:18:06] [PASSED] bookkeep
[17:18:06] ================= [PASSED] test_get_fences =================
[17:18:06] ================== [PASSED] dma-buf-resv ===================
[17:18:06] ============================================================
[17:18:06] Testing complete. Ran 54 tests: passed: 53, skipped: 1
[17:18:06] Elapsed time: 15.882s total, 1.805s configuring, 8.706s building, 5.346s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel



^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
  2026-09-06 17:16 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev3) Patchwork
  2026-09-06 17:18 ` ✓ CI.KUnit: success " Patchwork
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:21   ` sashiko-bot
                     ` (2 more replies)
  2026-09-06 17:26 ` [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
                   ` (12 subsequent siblings)
  15 siblings, 3 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Introduce xe_emit_hardware_error_cper() as public entry point
for CPER reporting.

Wire xe_log to route hardware SIGIDs through the new helper.
No functional change is intended yet, as the CPER emission logic
is added in follow-up patches.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/xe/Makefile  |  2 ++
 drivers/gpu/drm/xe/xe_cper.c | 37 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_cper.h | 25 ++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_log.c  | 17 +++++++++++------
 4 files changed, 75 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_cper.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 67b8b5477639..06b064add77d 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -166,6 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
 xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
 xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
 
+xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o
+
 # graphics virtualization (SR-IOV) support
 xe-y += \
 	xe_gt_sriov_vf.o \
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
new file mode 100644
index 000000000000..e8017e3ee3a0
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/pci.h>
+
+#include <drm/drm_print.h>
+
+#include "xe_cper.h"
+#include "xe_device.h"
+#include "xe_ras_types.h"
+
+/**
+ * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
+ * @pdev: PCI device associated with the Xe device
+ * @cper_sev: CPER severity
+ * @sigid: Error signature identifier
+ * @error_class: Hardware error classification details
+ * @response: Response of get counter
+ *
+ * Emit a CPER record for a hardware error
+ */
+void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
+				 struct xe_ras_error_class *counter,
+				 struct xe_ras_get_counter_response *response)
+{
+	struct xe_device *xe = pdev_to_xe_device(pdev);
+
+	if (!xe)
+		return;
+
+	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
+		return;
+
+	/* TODO */
+}
diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
new file mode 100644
index 000000000000..c4be7f25a369
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPER_H_
+#define _XE_CPER_H_
+
+#include "abi/xe_sigid_abi.h"
+
+struct pci_dev;
+struct xe_ras_error_class;
+struct xe_ras_get_counter_response;
+
+#if IS_REACHABLE(CONFIG_UEFI_CPER_X86)
+void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
+				 struct xe_ras_error_class *counter,
+				 struct xe_ras_get_counter_response *response);
+#else
+static inline void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev,
+					       enum xe_sigid sigid,
+					       struct xe_ras_error_class *counter,
+					       struct xe_ras_get_counter_response *response) {}
+#endif
+#endif /* _XE_CPER_H_ */
diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
index 5549ef6966fd..2957adec41aa 100644
--- a/drivers/gpu/drm/xe/xe_log.c
+++ b/drivers/gpu/drm/xe/xe_log.c
@@ -8,17 +8,27 @@
 
 #include "abi/xe_log_abi.h"
 
+#include "xe_cper.h"
 #include "xe_device.h"
 #include "xe_log.h"
 #include "xe_printk.h"
 
+static bool is_hw_sigid(enum xe_sigid sigid)
+{
+	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
+}
+
 static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
 			  u32 component, u32 location, const void *data, size_t len,
 			  struct va_format *vaf)
 {
 	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
 				   component, location, data, len, vaf);
-	/* TODO */
+
+	if (is_hw_sigid(sigid) && !IS_ERR(data))
+		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
+					    (struct xe_ras_error_class *)data, NULL);
+	/* TODO software CPER */
 }
 
 static const char *log_unknown_component_prefix(u32 component)
@@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
 	return buf;
 }
 
-static bool is_hw_sigid(enum xe_sigid sigid)
-{
-	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
-}
-
 static bool is_sev_error(int cper_sev)
 {
 	return cper_sev != CPER_SEV_INFORMATIONAL;
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log
  2026-09-06 17:26 ` [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log Badal Nilawar
@ 2026-09-06 17:21   ` sashiko-bot
  2026-09-07 12:38   ` Michal Wajdeczko
  2026-09-08 10:12   ` Raag Jadav
  2 siblings, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:21 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The condition `if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)` in `xe_emit_hardware_error_cper()` is inverted, causing the function to immediately drop all hardware error signatures.
--

commit 8d5b33ea1e6386b119b58d344413a048df730b76
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Hardware error CPER reporting from xe_log

This commit introduces xe_emit_hardware_error_cper() as a public entry
point for CPER reporting. It also wires up xe_log to route hardware
SIGIDs through this new helper.

> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> new file mode 100644
> index 0000000000000..e8017e3ee3a09
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.c

[ ... ]

> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *counter,
> +				 struct xe_ras_get_counter_response *response)
> +{
> +	struct xe_device *xe = pdev_to_xe_device(pdev);
> +
> +	if (!xe)
> +		return;
> +
> +	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
> +		return;

[Severity: High]
Is the condition here inverted?

Looking at log_emit_cper() in xe_log.c, it ensures the signature is a
hardware error before calling this helper:

xe_log.c:log_emit_cper() {
    ...
    if (is_hw_sigid(sigid) && !IS_ERR(data))
        xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
                                    (struct xe_ras_error_class *)data, NULL);
    ...
}

Where is_hw_sigid() is defined as:

static bool is_hw_sigid(enum xe_sigid sigid)
{
    return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
}

Since xe_emit_hardware_error_cper() immediately returns if the signature
meets this exact same condition, doesn't this unintentionally drop all valid
hardware signatures and prevent the records from being emitted?

> +
> +	/* TODO */
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=1

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log
  2026-09-06 17:26 ` [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log Badal Nilawar
  2026-09-06 17:21   ` sashiko-bot
@ 2026-09-07 12:38   ` Michal Wajdeczko
  2026-09-10 11:39     ` Nilawar, Badal
  2026-09-08 10:12   ` Raag Jadav
  2 siblings, 1 reply; 45+ messages in thread
From: Michal Wajdeczko @ 2026-09-07 12:38 UTC (permalink / raw)
  To: Badal Nilawar, intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
	nitin.r.gote



On 9/6/2026 7:26 PM, Badal Nilawar wrote:
> Introduce xe_emit_hardware_error_cper() as public entry point
> for CPER reporting.
> 
> Wire xe_log to route hardware SIGIDs through the new helper.
> No functional change is intended yet, as the CPER emission logic
> is added in follow-up patches.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/Makefile  |  2 ++
>  drivers/gpu/drm/xe/xe_cper.c | 37 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_cper.h | 25 ++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_log.c  | 17 +++++++++++------
>  4 files changed, 75 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_cper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_cper.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 67b8b5477639..06b064add77d 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -166,6 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
>  xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>  xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
>  
> +xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o

shouldn't we use just CONFIG_UEFI_CPER ?

> +
>  # graphics virtualization (SR-IOV) support
>  xe-y += \
>  	xe_gt_sriov_vf.o \
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> new file mode 100644
> index 000000000000..e8017e3ee3a0
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/pci.h>
> +
> +#include <drm/drm_print.h>

do we need this?

> +
> +#include "xe_cper.h"
> +#include "xe_device.h"
> +#include "xe_ras_types.h"
> +
> +/**
> + * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
> + * @pdev: PCI device associated with the Xe device
> + * @cper_sev: CPER severity
> + * @sigid: Error signature identifier
> + * @error_class: Hardware error classification details
> + * @response: Response of get counter
> + *
> + * Emit a CPER record for a hardware error
> + */
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *counter,
> +				 struct xe_ras_get_counter_response *response)
> +{
> +	struct xe_device *xe = pdev_to_xe_device(pdev);
> +
> +	if (!xe)
> +		return;
> +
> +	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
> +		return;
> +
> +	/* TODO */
> +}
> diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
> new file mode 100644
> index 000000000000..c4be7f25a369
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_H_
> +#define _XE_CPER_H_
> +
> +#include "abi/xe_sigid_abi.h"

maybe just:

	enum xe_sigid sigid;

> +
> +struct pci_dev;
> +struct xe_ras_error_class;
> +struct xe_ras_get_counter_response;
> +
> +#if IS_REACHABLE(CONFIG_UEFI_CPER_X86)
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *counter,
> +				 struct xe_ras_get_counter_response *response);

since you're introducing xe_cper component, all its public functions
shall use xe_cper prefix:

	xe_cper_emit_hardware_error(

and since all HW errors are expected to come from the xe, no need for pdev:

	xe_cper_emit_hardware_error(struct xe_device *xe, 

also it's better to let the caller pass whatever data was given in xe_log macros:

	xe_cper_emit_hardware_error(struct xe_device *xe,
				int cper_sev, enum xe_sigid sigid,
				const void *data, size_t len)

and do any data validation/conversion inside xe_cper code

and since xe_ras_get_counter_response is now optional, just define another function (when needed) that takes already validated data:

	xe_cper_emit_hardware_error_details(struct xe_device *xe,
				int cper_sev, enum xe_sigid sigid,
				const struct xe_ras_error_class *counter,
				const struct xe_ras_get_counter_response *response);

> +#else
> +static inline void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev,
> +					       enum xe_sigid sigid,
> +					       struct xe_ras_error_class *counter,
> +					       struct xe_ras_get_counter_response *response) {}
> +#endif
> +#endif /* _XE_CPER_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
> index 5549ef6966fd..2957adec41aa 100644
> --- a/drivers/gpu/drm/xe/xe_log.c
> +++ b/drivers/gpu/drm/xe/xe_log.c
> @@ -8,17 +8,27 @@
>  
>  #include "abi/xe_log_abi.h"
>  
> +#include "xe_cper.h"
>  #include "xe_device.h"
>  #include "xe_log.h"
>  #include "xe_printk.h"
>  
> +static bool is_hw_sigid(enum xe_sigid sigid)
> +{
> +	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> +}
> +
>  static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>  			  u32 component, u32 location, const void *data, size_t len,
>  			  struct va_format *vaf)
>  {
>  	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
>  				   component, location, data, len, vaf);
> -	/* TODO */
> +
> +	if (is_hw_sigid(sigid) && !IS_ERR(data))
> +		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
> +					    (struct xe_ras_error_class *)data, NULL);

you shouldn't blindly convert data to xe_ras_error_class
you shall at least check if len == sizeof(xe_ras_error_class)
and IMO it would be better to move that checks to xe_cper code
(as maybe we can still emit some CPER records for ERR_PTR data?


> +	/* TODO software CPER */
>  }
>  
>  static const char *log_unknown_component_prefix(u32 component)
> @@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
>  	return buf;
>  }
>  
> -static bool is_hw_sigid(enum xe_sigid sigid)
> -{
> -	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> -}
> -
>  static bool is_sev_error(int cper_sev)
>  {
>  	return cper_sev != CPER_SEV_INFORMATIONAL;


^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log
  2026-09-07 12:38   ` Michal Wajdeczko
@ 2026-09-10 11:39     ` Nilawar, Badal
  0 siblings, 0 replies; 45+ messages in thread
From: Nilawar, Badal @ 2026-09-10 11:39 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	himal.prasad.ghimiray, arvind.yadav, syed.abdul.muqthyar.ahmed,
	nitin.r.gote

[-- Attachment #1: Type: text/plain, Size: 6816 bytes --]


On 07-09-2026 18:08, Michal Wajdeczko wrote:
>
> On 9/6/2026 7:26 PM, Badal Nilawar wrote:
>> Introduce xe_emit_hardware_error_cper() as public entry point
>> for CPER reporting.
>>
>> Wire xe_log to route hardware SIGIDs through the new helper.
>> No functional change is intended yet, as the CPER emission logic
>> is added in follow-up patches.
>>
>> Signed-off-by: Badal Nilawar<badal.nilawar@intel.com>
>> ---
>>   drivers/gpu/drm/xe/Makefile  |  2 ++
>>   drivers/gpu/drm/xe/xe_cper.c | 37 ++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_cper.h | 25 ++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_log.c  | 17 +++++++++++------
>>   4 files changed, 75 insertions(+), 6 deletions(-)
>>   create mode 100644 drivers/gpu/drm/xe/xe_cper.c
>>   create mode 100644 drivers/gpu/drm/xe/xe_cper.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 67b8b5477639..06b064add77d 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -166,6 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
>>   xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>>   xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
>>   
>> +xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o
> shouldn't we use just CONFIG_UEFI_CPER ?
Will check.
>
>> +
>>   # graphics virtualization (SR-IOV) support
>>   xe-y += \
>>   	xe_gt_sriov_vf.o \
>> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
>> new file mode 100644
>> index 000000000000..e8017e3ee3a0
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_cper.c
>> @@ -0,0 +1,37 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#include <linux/pci.h>
>> +
>> +#include <drm/drm_print.h>
> do we need this?
will add in the patch where it is needed.
>
>> +
>> +#include "xe_cper.h"
>> +#include "xe_device.h"
>> +#include "xe_ras_types.h"
>> +
>> +/**
>> + * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
>> + * @pdev: PCI device associated with the Xe device
>> + * @cper_sev: CPER severity
>> + * @sigid: Error signature identifier
>> + * @error_class: Hardware error classification details
>> + * @response: Response of get counter
>> + *
>> + * Emit a CPER record for a hardware error
>> + */
>> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>> +				 struct xe_ras_error_class *counter,
>> +				 struct xe_ras_get_counter_response *response)
>> +{
>> +	struct xe_device *xe = pdev_to_xe_device(pdev);
>> +
>> +	if (!xe)
>> +		return;
>> +
>> +	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
>> +		return;
>> +
>> +	/* TODO */
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
>> new file mode 100644
>> index 000000000000..c4be7f25a369
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_cper.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_CPER_H_
>> +#define _XE_CPER_H_
>> +
>> +#include "abi/xe_sigid_abi.h"
> maybe just:
>
> 	enum xe_sigid sigid;
Ok.
>
>> +
>> +struct pci_dev;
>> +struct xe_ras_error_class;
>> +struct xe_ras_get_counter_response;
>> +
>> +#if IS_REACHABLE(CONFIG_UEFI_CPER_X86)
>> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>> +				 struct xe_ras_error_class *counter,
>> +				 struct xe_ras_get_counter_response *response);
> since you're introducing xe_cper component, all its public functions
> shall use xe_cper prefix:
>
> 	xe_cper_emit_hardware_error(

Sure.  Kept _cper in the end to indicate cper record of hardware error 
is being emitted.

>
> and since all HW errors are expected to come from the xe, no need for pdev:
>
> 	xe_cper_emit_hardware_error(struct xe_device *xe,
Ok.
>
> also it's better to let the caller pass whatever data was given in xe_log macros:
>
> 	xe_cper_emit_hardware_error(struct xe_device *xe,
> 				int cper_sev, enum xe_sigid sigid,
> 				const void *data, size_t len)
>
> and do any data validation/conversion inside xe_cper code
>
> and since xe_ras_get_counter_response is now optional, just define another function (when needed) that takes already validated data:
>
> 	xe_cper_emit_hardware_error_details(struct xe_device *xe,
> 				int cper_sev, enum xe_sigid sigid,
> 				const struct xe_ras_error_class *counter,
> 				const struct xe_ras_get_counter_response *response);

Will think about this. Don't want to keep to many layers. May be a one 
more wrapper function in xe_cper.c, which will do validation and decide 
which path hw or fw cper to follow.
IMO inside log_emit_cper itself validation should be done.

>
>> +#else
>> +static inline void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev,
>> +					       enum xe_sigid sigid,
>> +					       struct xe_ras_error_class *counter,
>> +					       struct xe_ras_get_counter_response *response) {}
>> +#endif
>> +#endif /* _XE_CPER_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
>> index 5549ef6966fd..2957adec41aa 100644
>> --- a/drivers/gpu/drm/xe/xe_log.c
>> +++ b/drivers/gpu/drm/xe/xe_log.c
>> @@ -8,17 +8,27 @@
>>   
>>   #include "abi/xe_log_abi.h"
>>   
>> +#include "xe_cper.h"
>>   #include "xe_device.h"
>>   #include "xe_log.h"
>>   #include "xe_printk.h"
>>   
>> +static bool is_hw_sigid(enum xe_sigid sigid)
>> +{
>> +	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
>> +}
>> +
>>   static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>>   			  u32 component, u32 location, const void *data, size_t len,
>>   			  struct va_format *vaf)
>>   {
>>   	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
>>   				   component, location, data, len, vaf);
>> -	/* TODO */
>> +
>> +	if (is_hw_sigid(sigid) && !IS_ERR(data))
>> +		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
>> +					    (struct xe_ras_error_class *)data, NULL);
> you shouldn't blindly convert data to xe_ras_error_class
> you shall at least check if len == sizeof(xe_ras_error_class)
> and IMO it would be better to move that checks to xe_cper code
> (as maybe we can still emit some CPER records for ERR_PTR data?

Without valid error class no point in emitting hardware CPER. May be as 
software CPER this can be considered later.

Thanks,
Badal

>
>
>> +	/* TODO software CPER */
>>   }
>>   
>>   static const char *log_unknown_component_prefix(u32 component)
>> @@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
>>   	return buf;
>>   }
>>   
>> -static bool is_hw_sigid(enum xe_sigid sigid)
>> -{
>> -	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
>> -}
>> -
>>   static bool is_sev_error(int cper_sev)
>>   {
>>   	return cper_sev != CPER_SEV_INFORMATIONAL;

[-- Attachment #2: Type: text/html, Size: 9137 bytes --]

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log
  2026-09-06 17:26 ` [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log Badal Nilawar
  2026-09-06 17:21   ` sashiko-bot
  2026-09-07 12:38   ` Michal Wajdeczko
@ 2026-09-08 10:12   ` Raag Jadav
  2026-09-10 12:33     ` Nilawar, Badal
  2 siblings, 1 reply; 45+ messages in thread
From: Raag Jadav @ 2026-09-08 10:12 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:06PM +0530, Badal Nilawar wrote:
> Introduce xe_emit_hardware_error_cper() as public entry point
> for CPER reporting.
> 
> Wire xe_log to route hardware SIGIDs through the new helper.
> No functional change is intended yet, as the CPER emission logic
> is added in follow-up patches.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/Makefile  |  2 ++
>  drivers/gpu/drm/xe/xe_cper.c | 37 ++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_cper.h | 25 ++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_log.c  | 17 +++++++++++------
>  4 files changed, 75 insertions(+), 6 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_cper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_cper.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 67b8b5477639..06b064add77d 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -166,6 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
>  xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>  xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
>  
> +xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o

Why x86?

>  # graphics virtualization (SR-IOV) support
>  xe-y += \
>  	xe_gt_sriov_vf.o \
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> new file mode 100644
> index 000000000000..e8017e3ee3a0
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include <linux/pci.h>
> +
> +#include <drm/drm_print.h>
> +
> +#include "xe_cper.h"
> +#include "xe_device.h"
> +#include "xe_ras_types.h"
> +
> +/**
> + * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
> + * @pdev: PCI device associated with the Xe device
> + * @cper_sev: CPER severity
> + * @sigid: Error signature identifier
> + * @error_class: Hardware error classification details
> + * @response: Response of get counter
> + *
> + * Emit a CPER record for a hardware error
> + */
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,

Why the long names? Can't this be simply xe_cper_hw_emit()?

> +				 struct xe_ras_error_class *counter,
> +				 struct xe_ras_get_counter_response *response)
> +{
> +	struct xe_device *xe = pdev_to_xe_device(pdev);
> +
> +	if (!xe)
> +		return;
> +
> +	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
> +		return;
> +
> +	/* TODO */
> +}
> diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
> new file mode 100644
> index 000000000000..c4be7f25a369
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper.h
> @@ -0,0 +1,25 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_H_
> +#define _XE_CPER_H_
> +
> +#include "abi/xe_sigid_abi.h"
> +
> +struct pci_dev;
> +struct xe_ras_error_class;
> +struct xe_ras_get_counter_response;
> +
> +#if IS_REACHABLE(CONFIG_UEFI_CPER_X86)
> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> +				 struct xe_ras_error_class *counter,
> +				 struct xe_ras_get_counter_response *response);
> +#else
> +static inline void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev,
> +					       enum xe_sigid sigid,
> +					       struct xe_ras_error_class *counter,
> +					       struct xe_ras_get_counter_response *response) {}
> +#endif
> +#endif /* _XE_CPER_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
> index 5549ef6966fd..2957adec41aa 100644
> --- a/drivers/gpu/drm/xe/xe_log.c
> +++ b/drivers/gpu/drm/xe/xe_log.c
> @@ -8,17 +8,27 @@
>  
>  #include "abi/xe_log_abi.h"
>  
> +#include "xe_cper.h"
>  #include "xe_device.h"
>  #include "xe_log.h"
>  #include "xe_printk.h"
>  
> +static bool is_hw_sigid(enum xe_sigid sigid)
> +{
> +	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;

Shouldn't this be

	return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_GPU_XE_HARDWARE_END);

> +}
> +
>  static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>  			  u32 component, u32 location, const void *data, size_t len,
>  			  struct va_format *vaf)
>  {
>  	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
>  				   component, location, data, len, vaf);
> -	/* TODO */
> +
> +	if (is_hw_sigid(sigid) && !IS_ERR(data))

Why not !IS_ERR_OR_NULL(data)?

Raag

> +		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
> +					    (struct xe_ras_error_class *)data, NULL);
> +	/* TODO software CPER */
>  }
>  
>  static const char *log_unknown_component_prefix(u32 component)
> @@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
>  	return buf;
>  }
>  
> -static bool is_hw_sigid(enum xe_sigid sigid)
> -{
> -	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> -}
> -
>  static bool is_sev_error(int cper_sev)
>  {
>  	return cper_sev != CPER_SEV_INFORMATIONAL;
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log
  2026-09-08 10:12   ` Raag Jadav
@ 2026-09-10 12:33     ` Nilawar, Badal
  0 siblings, 0 replies; 45+ messages in thread
From: Nilawar, Badal @ 2026-09-10 12:33 UTC (permalink / raw)
  To: Raag Jadav
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote


On 08-09-2026 15:42, Raag Jadav wrote:
> On Sun, Sep 06, 2026 at 10:56:06PM +0530, Badal Nilawar wrote:
>> Introduce xe_emit_hardware_error_cper() as public entry point
>> for CPER reporting.
>>
>> Wire xe_log to route hardware SIGIDs through the new helper.
>> No functional change is intended yet, as the CPER emission logic
>> is added in follow-up patches.
>>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>>   drivers/gpu/drm/xe/Makefile  |  2 ++
>>   drivers/gpu/drm/xe/xe_cper.c | 37 ++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_cper.h | 25 ++++++++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_log.c  | 17 +++++++++++------
>>   4 files changed, 75 insertions(+), 6 deletions(-)
>>   create mode 100644 drivers/gpu/drm/xe/xe_cper.c
>>   create mode 100644 drivers/gpu/drm/xe/xe_cper.h
>>
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 67b8b5477639..06b064add77d 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -166,6 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
>>   xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>>   xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
>>   
>> +xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o
> Why x86?
Will change to  CONFIG_UEFI_CPER.
>
>>   # graphics virtualization (SR-IOV) support
>>   xe-y += \
>>   	xe_gt_sriov_vf.o \
>> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
>> new file mode 100644
>> index 000000000000..e8017e3ee3a0
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_cper.c
>> @@ -0,0 +1,37 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#include <linux/pci.h>
>> +
>> +#include <drm/drm_print.h>
>> +
>> +#include "xe_cper.h"
>> +#include "xe_device.h"
>> +#include "xe_ras_types.h"
>> +
>> +/**
>> + * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
>> + * @pdev: PCI device associated with the Xe device
>> + * @cper_sev: CPER severity
>> + * @sigid: Error signature identifier
>> + * @error_class: Hardware error classification details
>> + * @response: Response of get counter
>> + *
>> + * Emit a CPER record for a hardware error
>> + */
>> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> Why the long names? Can't this be simply xe_cper_hw_emit()?
Sure.
>
>> +				 struct xe_ras_error_class *counter,
>> +				 struct xe_ras_get_counter_response *response)
>> +{
>> +	struct xe_device *xe = pdev_to_xe_device(pdev);
>> +
>> +	if (!xe)
>> +		return;
>> +
>> +	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
>> +		return;
>> +
>> +	/* TODO */
>> +}
>> diff --git a/drivers/gpu/drm/xe/xe_cper.h b/drivers/gpu/drm/xe/xe_cper.h
>> new file mode 100644
>> index 000000000000..c4be7f25a369
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_cper.h
>> @@ -0,0 +1,25 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_CPER_H_
>> +#define _XE_CPER_H_
>> +
>> +#include "abi/xe_sigid_abi.h"
>> +
>> +struct pci_dev;
>> +struct xe_ras_error_class;
>> +struct xe_ras_get_counter_response;
>> +
>> +#if IS_REACHABLE(CONFIG_UEFI_CPER_X86)
>> +void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>> +				 struct xe_ras_error_class *counter,
>> +				 struct xe_ras_get_counter_response *response);
>> +#else
>> +static inline void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev,
>> +					       enum xe_sigid sigid,
>> +					       struct xe_ras_error_class *counter,
>> +					       struct xe_ras_get_counter_response *response) {}
>> +#endif
>> +#endif /* _XE_CPER_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_log.c b/drivers/gpu/drm/xe/xe_log.c
>> index 5549ef6966fd..2957adec41aa 100644
>> --- a/drivers/gpu/drm/xe/xe_log.c
>> +++ b/drivers/gpu/drm/xe/xe_log.c
>> @@ -8,17 +8,27 @@
>>   
>>   #include "abi/xe_log_abi.h"
>>   
>> +#include "xe_cper.h"
>>   #include "xe_device.h"
>>   #include "xe_log.h"
>>   #include "xe_printk.h"
>>   
>> +static bool is_hw_sigid(enum xe_sigid sigid)
>> +{
>> +	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
> Shouldn't this be
>
> 	return in_range(sigid, INTEL_SIGID_GPU_XE_HARDWARE_START, INTEL_SIGID_GPU_XE_HARDWARE_END);
Ok.
>
>> +}
>> +
>>   static void log_emit_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>>   			  u32 component, u32 location, const void *data, size_t len,
>>   			  struct va_format *vaf)
>>   {
>>   	KUNIT_STATIC_STUB_REDIRECT(log_emit_cper, pdev, cper_sev, sigid,
>>   				   component, location, data, len, vaf);
>> -	/* TODO */
>> +
>> +	if (is_hw_sigid(sigid) && !IS_ERR(data))
> Why not !IS_ERR_OR_NULL(data)?

Ok.

Thanks,
Badal

>
> Raag
>
>> +		xe_emit_hardware_error_cper(pdev, cper_sev, sigid,
>> +					    (struct xe_ras_error_class *)data, NULL);
>> +	/* TODO software CPER */
>>   }
>>   
>>   static const char *log_unknown_component_prefix(u32 component)
>> @@ -100,11 +110,6 @@ static const char *log_location_prefix(struct pci_dev *pdev, u32 location, char
>>   	return buf;
>>   }
>>   
>> -static bool is_hw_sigid(enum xe_sigid sigid)
>> -{
>> -	return (int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START;
>> -}
>> -
>>   static bool is_sev_error(int cper_sev)
>>   {
>>   	return cper_sev != CPER_SEV_INFORMATIONAL;
>> -- 
>> 2.54.0
>>

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (2 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:23   ` sashiko-bot
  2026-09-08 10:16   ` Raag Jadav
  2026-09-06 17:26 ` [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures Badal Nilawar
                   ` (11 subsequent siblings)
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Retrieve error counter record required to build a CPER record when
one not provided by the caller.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/xe/xe_cper.c |  15 ++++++
 drivers/gpu/drm/xe/xe_ras.c  | 100 ++++++++++++++++++++++-------------
 drivers/gpu/drm/xe/xe_ras.h  |   3 ++
 3 files changed, 80 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index e8017e3ee3a0..f04a91223a43 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -9,6 +9,8 @@
 
 #include "xe_cper.h"
 #include "xe_device.h"
+#include "xe_printk.h"
+#include "xe_ras.h"
 #include "xe_ras_types.h"
 
 /**
@@ -26,6 +28,8 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
 				 struct xe_ras_get_counter_response *response)
 {
 	struct xe_device *xe = pdev_to_xe_device(pdev);
+	struct xe_ras_get_counter_response local_resp = {};
+	struct xe_ras_get_counter_response *counter_response = response;
 
 	if (!xe)
 		return;
@@ -33,5 +37,16 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
 	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
 		return;
 
+	if (!counter || !xe_ras_counter_is_valid(xe, counter))
+		return;
+
+	if (!counter_response) {
+		counter_response = &local_resp;
+		if (xe_ras_get_counter_response(xe, counter, counter_response)) {
+			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
+			return;
+		}
+	}
+
 	/* TODO */
 }
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 7a85735c57d5..0fb9065cdd76 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -103,8 +103,6 @@ static const char * const gpu_health_states[] = {
 };
 static_assert(ARRAY_SIZE(gpu_health_states) == XE_RAS_HEALTH_MAX);
 
-static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value);
-
 static u8 drm_to_xe_ras_severity(u8 severity)
 {
 	switch (severity) {
@@ -201,24 +199,6 @@ static inline const char *comp_to_str(u8 component)
 	return xe_ras_components[component];
 }
 
-static bool ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter)
-{
-	u8 severity = counter->common.severity;
-	u8 component = counter->common.component;
-
-	if (!in_range(severity, XE_RAS_SEV_NOT_SUPPORTED + 1, XE_RAS_SEV_MAX - 1)) {
-		xe_err(xe, "sysctrl: unexpected severity %u\n", severity);
-		return false;
-	}
-
-	if (!in_range(component, XE_RAS_COMP_NOT_SUPPORTED + 1, XE_RAS_COMP_MAX - 1)) {
-		xe_err(xe, "sysctrl: unexpected component %u\n", component);
-		return false;
-	}
-
-	return true;
-}
-
 static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
 {
 	struct pci_dev *vsp;
@@ -284,21 +264,21 @@ static void ras_usp_aer_init(struct xe_device *xe)
 static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component)
 {
 	struct xe_ras_error_class counter = {0};
+	struct xe_ras_get_counter_response response = {0};
 	u8 drm_severity, drm_component;
-	u32 value;
 	int ret;
 
 	counter.common.severity = severity;
 	counter.common.component = component;
 
-	ret = get_counter(xe, &counter, &value);
+	ret = xe_ras_get_counter_response(xe, &counter, &response);
 	if (ret)
 		return;
 
 	drm_severity = xe_to_drm_ras_severity(severity);
 	drm_component = xe_to_drm_ras_component(component);
 
-	xe_drm_ras_event(xe, drm_component, drm_severity, value);
+	xe_drm_ras_event(xe, drm_component, drm_severity, response.value);
 }
 
 static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
@@ -395,6 +375,33 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
 	return XE_RAS_RECOVERY_ACTION_RECOVERED;
 }
 
+/**
+ * xe_ras_counter_is_valid() - Validate a RAS error counter
+ * @xe: Xe device instance
+ * @counter: RAS error class to validate
+ *
+ * Validate that counter represents a supported RAS error class
+ *
+ * Return: true if counter is valid, false otherwise.
+ */
+bool xe_ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter)
+{
+	u8 severity = counter->common.severity;
+	u8 component = counter->common.component;
+
+	if (!in_range(severity, XE_RAS_SEV_NOT_SUPPORTED + 1, XE_RAS_SEV_MAX - 1)) {
+		xe_err(xe, "sysctrl: unexpected severity %u\n", severity);
+		return false;
+	}
+
+	if (!in_range(component, XE_RAS_COMP_NOT_SUPPORTED + 1, XE_RAS_COMP_MAX - 1)) {
+		xe_err(xe, "sysctrl: unexpected component %u\n", component);
+		return false;
+	}
+
+	return true;
+}
+
 void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 				      struct xe_sysctrl_event_response *response)
 {
@@ -418,7 +425,7 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 		severity = errors[id].common.severity;
 		component = errors[id].common.component;
 
-		if (!ras_counter_is_valid(xe, &errors[id]))
+		if (!xe_ras_counter_is_valid(xe, &errors[id]))
 			continue;
 
 		xe_warn(xe, "[RAS]: %s %s detected\n",
@@ -433,19 +440,30 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 	}
 }
 
-static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter, u32 *value)
+/**
+ * xe_ras_get_counter_response() - Get error counter record
+ * @xe: Xe device instance
+ * @counter: ras error class
+ * @out: Counter record retrieved
+ *
+ * This function retrieves the counter record of specific error counter
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int xe_ras_get_counter_response(struct xe_device *xe, struct xe_ras_error_class *counter,
+				struct xe_ras_get_counter_response *out)
 {
-	struct xe_ras_get_counter_response response = {0};
 	struct xe_ras_get_counter_request request = {0};
 	struct xe_sysctrl_mailbox_command command = {0};
 	struct xe_ras_error_common *common;
 	size_t rlen;
 	int ret;
 
+	memset(out, 0, sizeof(*out));
 	request.counter = *counter;
 
 	xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP, XE_SYSCTRL_CMD_GET_COUNTER,
-				  &request, sizeof(request), &response, sizeof(response));
+				  &request, sizeof(request), out, sizeof(*out));
 
 	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
 	if (ret) {
@@ -453,19 +471,18 @@ static int get_counter(struct xe_device *xe, struct xe_ras_error_class *counter,
 		return ret;
 	}
 
-	if (rlen != sizeof(response)) {
+	if (rlen != sizeof(*out)) {
 		xe_err(xe, "sysctrl: unexpected get counter response length %zu (expected %zu)\n",
-		       rlen, sizeof(response));
+		       rlen, sizeof(*out));
 		return -EIO;
 	}
 
-	if (!ras_counter_is_valid(xe, &response.counter))
+	if (!xe_ras_counter_is_valid(xe, &out->counter))
 		return -EBADMSG;
 
-	common = &response.counter.common;
-	*value = response.value;
+	common = &out->counter.common;
 
-	xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", *value, comp_to_str(common->component),
+	xe_dbg(xe, "[RAS]: get counter %u for %s %s\n", out->value, comp_to_str(common->component),
 	       sev_to_str(common->severity));
 
 	return 0;
@@ -534,7 +551,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 			component = arr->counter.common.component;
 			severity = arr->counter.common.severity;
 
-			if (!ras_counter_is_valid(xe, &arr->counter))
+			if (!xe_ras_counter_is_valid(xe, &arr->counter))
 				continue;
 
 			xe_info(xe, "[RAS]: %s %s detected\n", comp_to_str(component),
@@ -596,12 +613,19 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value)
 {
 	struct xe_ras_error_class counter = {0};
+	struct xe_ras_get_counter_response response = {0};
+	int ret;
 
 	counter.common.severity = drm_to_xe_ras_severity(severity);
 	counter.common.component = drm_to_xe_ras_component(component);
 
 	guard(xe_pm_runtime)(xe);
-	return get_counter(xe, &counter, value);
+	ret = xe_ras_get_counter_response(xe, &counter, &response);
+	if (ret)
+		return ret;
+
+	*value = response.value;
+	return 0;
 }
 
 /**
@@ -653,7 +677,7 @@ int xe_ras_clear_counter(struct xe_device *xe, u8 severity, u8 component)
 
 	counter = &response.counter;
 
-	if (!ras_counter_is_valid(xe, counter))
+	if (!xe_ras_counter_is_valid(xe, counter))
 		return -EBADMSG;
 
 	xe_dbg(xe, "[RAS]: clear counter for %s %s\n", comp_to_str(counter->common.component),
@@ -703,7 +727,7 @@ int xe_ras_get_threshold(struct xe_device *xe, u8 severity, u8 component, u32 *t
 		return -EIO;
 	}
 
-	if (!ras_counter_is_valid(xe, &response.counter))
+	if (!xe_ras_counter_is_valid(xe, &response.counter))
 		return -EBADMSG;
 
 	counter = &response.counter;
@@ -765,7 +789,7 @@ int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 th
 
 	counter = &response.counter;
 
-	if (!ras_counter_is_valid(xe, counter))
+	if (!xe_ras_counter_is_valid(xe, counter))
 		return -EBADMSG;
 
 	xe_dbg(xe, "[RAS]: set threshold %u for %s %s\n", response.threshold,
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index 0b8669f28d56..e83e022cd363 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -20,5 +20,8 @@ int xe_ras_get_threshold(struct xe_device *xe, u8 severity, u8 component, u32 *t
 int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 threshold);
 void xe_ras_init(struct xe_device *xe);
 enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
+int xe_ras_get_counter_response(struct xe_device *xe, struct xe_ras_error_class *counter,
+				struct xe_ras_get_counter_response *out);
+bool xe_ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter);
 
 #endif
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting
  2026-09-06 17:26 ` [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
@ 2026-09-06 17:23   ` sashiko-bot
  2026-09-08 10:16   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:23 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:

New issues:
- [High] Fetching error counters from the generic logging emission path introduces a might_sleep() restriction into generic logging macros.
- [High] xe_emit_hardware_error_cper reads MMIO registers via sysctrl command without ensuring the device is awake, leading to potential system crashes or PCIe AER errors if called when the device is in D3cold.
- [Medium] The patch introduces redundant, synchronous sysctrl mailbox commands to fetch counter values that the driver either already possesses or fetches again immediately.

Pre-existing issues:
- [High] Preexisting logic bug causes xe_emit_hardware_error_cper to immediately abort for hardware SIGIDs, making the newly added code unreachable.
--

commit ea598ea85d76d6f40d20fe1e15edf6a22c8e705c
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Retrieve the error counter record for CPER reporting

Retrieve the error counter record required to build a CPER record when
one is not provided by the caller.

> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index e8017e3ee3a09..f04a91223a43c 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> @@ -26,6 +28,8 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  				 struct xe_ras_get_counter_response *response)
>  {
>  	struct xe_device *xe = pdev_to_xe_device(pdev);
> +	struct xe_ras_get_counter_response local_resp = {};
> +	struct xe_ras_get_counter_response *counter_response = response;
>  
>  	if (!xe)
>  		return;
> @@ -33,5 +37,16 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
>  		return;

[Severity: High]
This isn't a bug introduced by this patch, but does this condition in
xe_emit_hardware_error_cper() prevent the newly added code from executing?

Since hardware SIGIDs are strictly greater than or equal to
INTEL_SIGID_GPU_XE_HARDWARE_START, checking if sigid is greater than or
equal to this constant seems to cause an immediate return for all hardware
errors, silently disabling the CPER record emission.

> +	if (!counter || !xe_ras_counter_is_valid(xe, counter))
> +		return;
> +
> +	if (!counter_response) {
> +		counter_response = &local_resp;
> +		if (xe_ras_get_counter_response(xe, counter, counter_response)) {

[Severity: High]
Does fetching error counters from the generic logging emission path
introduce a sleep restriction into logging macros?

If a generic macro like xe_log_comp_fatal() is called from an atomic context,
this synchronous fetch via xe_ras_get_counter_response() will invoke
xe_sysctrl_send_command(). The underlying sysctrl command asserts might_sleep()
and waits on a mutex, which could cause a bug or deadlock if triggered from an
interrupt handler or spinlock.

[Severity: High]
Also, does this hardware access ensure the device is runtime-resumed?

The sysctrl command path uses guard(xe_pm_runtime_noresume)(xe), which
increments the usage counter but avoids waking a suspended device. If this
logging path executes while the device is in D3cold, will the subsequent
MMIO reads hit powered-off hardware and trigger unhandled PCIe AER errors?

[Severity: Medium]
Finally, does this force a new mailbox command to fetch data that the caller
might already possess?

For example, in xe_ras_process_errors(), the driver already executes a
mailbox command that returns the counter values. However, it passes only a
pointer to the generic logging function, forcing
xe_emit_hardware_error_cper() to issue an entirely new, redundant synchronous
mailbox command to fetch the same value. Can this be optimized to reuse the
existing data and avoid extra latency during error handling?

> +			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
> +			return;
> +		}
> +	}
> +
>  	/* TODO */
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=2

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting
  2026-09-06 17:26 ` [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
  2026-09-06 17:23   ` sashiko-bot
@ 2026-09-08 10:16   ` Raag Jadav
  2026-09-09  6:12     ` Raag Jadav
  1 sibling, 1 reply; 45+ messages in thread
From: Raag Jadav @ 2026-09-08 10:16 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:07PM +0530, Badal Nilawar wrote:
> Retrieve error counter record required to build a CPER record when
> one not provided by the caller.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_cper.c |  15 ++++++
>  drivers/gpu/drm/xe/xe_ras.c  | 100 ++++++++++++++++++++++-------------
>  drivers/gpu/drm/xe/xe_ras.h  |   3 ++
>  3 files changed, 80 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index e8017e3ee3a0..f04a91223a43 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -9,6 +9,8 @@
>  
>  #include "xe_cper.h"
>  #include "xe_device.h"
> +#include "xe_printk.h"
> +#include "xe_ras.h"
>  #include "xe_ras_types.h"
>  
>  /**
> @@ -26,6 +28,8 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  				 struct xe_ras_get_counter_response *response)
>  {
>  	struct xe_device *xe = pdev_to_xe_device(pdev);
> +	struct xe_ras_get_counter_response local_resp = {};
> +	struct xe_ras_get_counter_response *counter_response = response;
>  
>  	if (!xe)
>  		return;
> @@ -33,5 +37,16 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
>  		return;
>  
> +	if (!counter || !xe_ras_counter_is_valid(xe, counter))

Why? Should we even be at this point without a valid counter?

> +		return;
> +
> +	if (!counter_response) {
> +		counter_response = &local_resp;
> +		if (xe_ras_get_counter_response(xe, counter, counter_response)) {

Dumb question, shouldn't the whole xe_emit_hardware_error_cper() be the
consequence of get_counter() and not the other way around?

Raag

> +			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
> +			return;
> +		}
> +	}
> +
>  	/* TODO */
>  }

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting
  2026-09-08 10:16   ` Raag Jadav
@ 2026-09-09  6:12     ` Raag Jadav
  2026-09-10 12:59       ` Nilawar, Badal
  0 siblings, 1 reply; 45+ messages in thread
From: Raag Jadav @ 2026-09-09  6:12 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Tue, Sep 08, 2026 at 12:16:27PM +0200, Raag Jadav wrote:
> On Sun, Sep 06, 2026 at 10:56:07PM +0530, Badal Nilawar wrote:
> > Retrieve error counter record required to build a CPER record when
> > one not provided by the caller.
> > 
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_cper.c |  15 ++++++
> >  drivers/gpu/drm/xe/xe_ras.c  | 100 ++++++++++++++++++++++-------------
> >  drivers/gpu/drm/xe/xe_ras.h  |   3 ++
> >  3 files changed, 80 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> > index e8017e3ee3a0..f04a91223a43 100644
> > --- a/drivers/gpu/drm/xe/xe_cper.c
> > +++ b/drivers/gpu/drm/xe/xe_cper.c
> > @@ -9,6 +9,8 @@
> >  
> >  #include "xe_cper.h"
> >  #include "xe_device.h"
> > +#include "xe_printk.h"
> > +#include "xe_ras.h"
> >  #include "xe_ras_types.h"
> >  
> >  /**
> > @@ -26,6 +28,8 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
> >  				 struct xe_ras_get_counter_response *response)
> >  {
> >  	struct xe_device *xe = pdev_to_xe_device(pdev);
> > +	struct xe_ras_get_counter_response local_resp = {};
> > +	struct xe_ras_get_counter_response *counter_response = response;
> >  
> >  	if (!xe)
> >  		return;
> > @@ -33,5 +37,16 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
> >  	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
> >  		return;
> >  
> > +	if (!counter || !xe_ras_counter_is_valid(xe, counter))
> 
> Why? Should we even be at this point without a valid counter?

ras_counter_is_valid() is already part of get_counter() and !counter
should be covered by IS_ERR_OR_NULL() in patch 1, which makes the entire
condition redundant.

> > +		return;
> > +
> > +	if (!counter_response) {
> > +		counter_response = &local_resp;
> > +		if (xe_ras_get_counter_response(xe, counter, counter_response)) {
> 
> Dumb question, shouldn't the whole xe_emit_hardware_error_cper() be the
> consequence of get_counter() and not the other way around?

Thanks for the offline pointers. From what I understand this is diverging
from the original hw cper design and correct for whatever we have in place.

Raag

> > +			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
> > +			return;
> > +		}
> > +	}
> > +
> >  	/* TODO */
> >  }

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting
  2026-09-09  6:12     ` Raag Jadav
@ 2026-09-10 12:59       ` Nilawar, Badal
  2026-09-10 13:19         ` Raag Jadav
  0 siblings, 1 reply; 45+ messages in thread
From: Nilawar, Badal @ 2026-09-10 12:59 UTC (permalink / raw)
  To: Raag Jadav
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote


On 09-09-2026 11:42, Raag Jadav wrote:
> On Tue, Sep 08, 2026 at 12:16:27PM +0200, Raag Jadav wrote:
>> On Sun, Sep 06, 2026 at 10:56:07PM +0530, Badal Nilawar wrote:
>>> Retrieve error counter record required to build a CPER record when
>>> one not provided by the caller.
>>>
>>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>>> ---
>>>   drivers/gpu/drm/xe/xe_cper.c |  15 ++++++
>>>   drivers/gpu/drm/xe/xe_ras.c  | 100 ++++++++++++++++++++++-------------
>>>   drivers/gpu/drm/xe/xe_ras.h  |   3 ++
>>>   3 files changed, 80 insertions(+), 38 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
>>> index e8017e3ee3a0..f04a91223a43 100644
>>> --- a/drivers/gpu/drm/xe/xe_cper.c
>>> +++ b/drivers/gpu/drm/xe/xe_cper.c
>>> @@ -9,6 +9,8 @@
>>>   
>>>   #include "xe_cper.h"
>>>   #include "xe_device.h"
>>> +#include "xe_printk.h"
>>> +#include "xe_ras.h"
>>>   #include "xe_ras_types.h"
>>>   
>>>   /**
>>> @@ -26,6 +28,8 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>>>   				 struct xe_ras_get_counter_response *response)
>>>   {
>>>   	struct xe_device *xe = pdev_to_xe_device(pdev);
>>> +	struct xe_ras_get_counter_response local_resp = {};
>>> +	struct xe_ras_get_counter_response *counter_response = response;
>>>   
>>>   	if (!xe)
>>>   		return;
>>> @@ -33,5 +37,16 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>>>   	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
>>>   		return;
>>>   
>>> +	if (!counter || !xe_ras_counter_is_valid(xe, counter))
>> Why? Should we even be at this point without a valid counter?
> ras_counter_is_valid() is already part of get_counter() and !counter
> should be covered by IS_ERR_OR_NULL() in patch 1, which makes the entire
> condition redundant.

get_counter is only validating ras response not caller provided counter.

Check is needed for data[] payload from xe_log.

>
>>> +		return;
>>> +
>>> +	if (!counter_response) {
>>> +		counter_response = &local_resp;
>>> +		if (xe_ras_get_counter_response(xe, counter, counter_response)) {
>> Dumb question, shouldn't the whole xe_emit_hardware_error_cper() be the
>> consequence of get_counter() and not the other way around?
> Thanks for the offline pointers. From what I understand this is diverging
> from the original hw cper design and correct for whatever we have in place.

Ok.

Badal

>
> Raag
>
>>> +			xe_err(xe, "[RAS]: CPER: failed to get counter, skipping record\n");
>>> +			return;
>>> +		}
>>> +	}
>>> +
>>>   	/* TODO */
>>>   }

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting
  2026-09-10 12:59       ` Nilawar, Badal
@ 2026-09-10 13:19         ` Raag Jadav
  0 siblings, 0 replies; 45+ messages in thread
From: Raag Jadav @ 2026-09-10 13:19 UTC (permalink / raw)
  To: Nilawar, Badal
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Thu, Sep 10, 2026 at 06:29:03PM +0530, Nilawar, Badal wrote:
> On 09-09-2026 11:42, Raag Jadav wrote:
> > On Tue, Sep 08, 2026 at 12:16:27PM +0200, Raag Jadav wrote:
> > > On Sun, Sep 06, 2026 at 10:56:07PM +0530, Badal Nilawar wrote:
> > > > Retrieve error counter record required to build a CPER record when
> > > > one not provided by the caller.
> > > > 
> > > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > > ---
> > > >   drivers/gpu/drm/xe/xe_cper.c |  15 ++++++
> > > >   drivers/gpu/drm/xe/xe_ras.c  | 100 ++++++++++++++++++++++-------------
> > > >   drivers/gpu/drm/xe/xe_ras.h  |   3 ++
> > > >   3 files changed, 80 insertions(+), 38 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> > > > index e8017e3ee3a0..f04a91223a43 100644
> > > > --- a/drivers/gpu/drm/xe/xe_cper.c
> > > > +++ b/drivers/gpu/drm/xe/xe_cper.c
> > > > @@ -9,6 +9,8 @@
> > > >   #include "xe_cper.h"
> > > >   #include "xe_device.h"
> > > > +#include "xe_printk.h"
> > > > +#include "xe_ras.h"
> > > >   #include "xe_ras_types.h"
> > > >   /**
> > > > @@ -26,6 +28,8 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
> > > >   				 struct xe_ras_get_counter_response *response)
> > > >   {
> > > >   	struct xe_device *xe = pdev_to_xe_device(pdev);
> > > > +	struct xe_ras_get_counter_response local_resp = {};
> > > > +	struct xe_ras_get_counter_response *counter_response = response;
> > > >   	if (!xe)
> > > >   		return;
> > > > @@ -33,5 +37,16 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
> > > >   	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
> > > >   		return;
> > > > +	if (!counter || !xe_ras_counter_is_valid(xe, counter))
> > > Why? Should we even be at this point without a valid counter?
> > ras_counter_is_valid() is already part of get_counter() and !counter
> > should be covered by IS_ERR_OR_NULL() in patch 1, which makes the entire
> > condition redundant.
> 
> get_counter is only validating ras response not caller provided counter.
> 
> Check is needed for data[] payload from xe_log.

In which case the caller is abusing xe_log and is expected to receive a
get_counter() failure, so let's not hide bugs.

Raag

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (3 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-07 13:13   ` Michal Wajdeczko
  2026-09-08 10:18   ` Raag Jadav
  2026-09-06 17:26 ` [PATCH v3 04/12] drm/xe/cper: Prepare CPER record Badal Nilawar
                   ` (10 subsequent siblings)
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Define Intel-specific data structures and GUIDs needed to build
Intel GPU CPER recoreds

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
v2: Fixed sashiko warning about bit fields usage
---
 drivers/gpu/drm/xe/xe_cper_types.h | 179 +++++++++++++++++++++++++++++
 1 file changed, 179 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h

diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
new file mode 100644
index 000000000000..b81b70501e0e
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_cper_types.h
@@ -0,0 +1,179 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_CPER_TYPES_H_
+#define _XE_CPER_TYPES_H_
+
+#include <linux/cper.h>
+#include <linux/types.h>
+#include <linux/uuid.h>
+
+/*
+ * Validation bits definition for validation_bits in struct
+ * xe_cper_sec_intel_err_hdr. When set, corresponding fields in header
+ * contains valid data
+ */
+#define XE_CPER_VALID_LOCATION		0x0001
+#define XE_CPER_VALID_FIRST_TIMESTAMP	0x0002
+#define XE_CPER_VALID_SIG_ID		0x0004
+#define XE_CPER_VALID_PCI_BDF		0x0008
+#define XE_CPER_VALID_DRV_VERSION	0x0010
+#define XE_CPER_VALID_FW_ID		0x0020
+
+/*
+ * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
+ *
+ * All values below are generated deterministically by uuid generator.
+ * Do not hand-edit the byte values.
+ */
+
+/* Creator IDs */
+#define INTEL_CPER_CREATOR_XEKMD \
+	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
+		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
+
+#define INTEL_CPER_CREATOR_AMC \
+	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
+		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
+
+/* Notification Types */
+#define INTEL_CPER_NOTIFY_GPU_ERROR \
+	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
+		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
+
+#define INTEL_CPER_NOTIFY_DRV_ERROR \
+	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
+		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
+
+/* Section Types */
+#define INTEL_CPER_SECTION_ACCEL_GENERIC \
+	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
+		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
+
+#pragma pack(push, 1)
+
+/**
+ * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header
+ *
+ * Fixed-size header for the Intel GPU error section of a CPER record.
+ * All multi-byte fields are little-endian; the structure is packed.
+ */
+struct xe_cper_sec_intel_err_hdr {
+	/** @error_class: Error classification (type, component, location, cause) */
+	union {
+		struct {
+			/** @error_class.error_type: RAS error severity */
+			u8  error_type;
+			/** @error_class.error_component: IP block that raised the error */
+			u8  error_component;
+			/** @error_class.tile: Tile number */
+			u8  tile;
+			/** @error_class.instance: Instance within the tile */
+			u32 instance;
+			/** @error_class.cause: Error cause code */
+			u32 cause;
+			/** @error_class.reserved: Reserved, must be zero */
+			u8  reserved;
+		} error_class;
+		/** @class: Raw byte view of the error class */
+		u8 class[12];
+	};
+	/** @first_timestamp: Timestamp of the first occurrence of this error class */
+	u64 first_timestamp;
+	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
+	u32 sig_id;
+	/** @error_count: Number of times this error has been observed */
+	u32 error_count;
+	/** @validation_bits: Raw u16 view of all valid bits */
+	u16 validation_bits;
+	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
+	char pci_bdf[16];
+	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
+	char drv_version[25];
+	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
+	char fw_id[256];
+	/** @reserved: Reserved for future use, must be zero */
+	u8 reserved[5];
+};
+
+/**
+ * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
+ *
+ * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
+ * is available. The @event_queue flexible array holds @event_queue_count
+ * packed &xe_intel_priv_event_entry records.
+ */
+struct xe_cper_sec_intel_error_info {
+	/** @error_class: Error classification (mirrors the header error_class) */
+	union {
+		struct {
+			u8  error_type;
+			u8  error_component;
+			u8  tile;
+			u32 instance;
+			u32 cause;
+			u8  reserved;
+		} error_class;
+		/** @class: Raw byte view of the error class */
+		u8 class[12];
+	};
+	/** @error_count: Total number of errors recorded */
+	u32 error_count;
+	/** @event_queue_length: Total byte size of the @event_queue array */
+	u32 event_queue_length;
+	/** @event_queue_count: Number of entries in @event_queue */
+	u32 event_queue_count;
+	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
+	u8 event_queue[];
+};
+
+/**
+ * struct xe_intel_priv_event_entry - Single error event in the event queue
+ *
+ * Each entry is variable-length; @entry_length gives the byte size of
+ * @metadata only (not including @entry_length or @timestamp).
+ */
+struct xe_intel_priv_event_entry {
+	/** @entry_length: Byte length of the @metadata payload */
+	u32 entry_length;
+	/** @timestamp: Hardware timestamp of this event */
+	u64 timestamp;
+	/** @metadata: Event-specific payload bytes */
+	u8  metadata[];
+};
+
+/**
+ * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
+ *
+ * Contains the standard CPER record header, section descriptor, and the
+ * Intel error section header. A &xe_cper_sec_intel_error_info payload
+ * (with its flexible @event_queue array) is appended dynamically.
+ */
+struct xe_cper_nonstd_record {
+	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
+	struct cper_record_header record_hdr;
+	/** @section_desc: CPER section descriptor */
+	struct cper_section_descriptor section_desc;
+	/** @intel_hdr: Intel-specific error section header */
+	struct xe_cper_sec_intel_err_hdr intel_hdr;
+};
+
+#pragma pack(pop)
+
+/**
+ * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
+ *
+ * Used to resolve the platform_id field in a CPER section descriptor.
+ * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
+ * with name string "platform/8086:<dev_id_hex_lower>".
+ */
+struct xe_platform_id_entry {
+	/** @device_id: PCI device ID */
+	u16       device_id;
+	/** @platform_id: Corresponding UUIDv5 platform GUID */
+	guid_t    platform_id;
+};
+
+#endif
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures
  2026-09-06 17:26 ` [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures Badal Nilawar
@ 2026-09-07 13:13   ` Michal Wajdeczko
  2026-09-10 11:57     ` Nilawar, Badal
  2026-09-08 10:18   ` Raag Jadav
  1 sibling, 1 reply; 45+ messages in thread
From: Michal Wajdeczko @ 2026-09-07 13:13 UTC (permalink / raw)
  To: Badal Nilawar, intel-xe, rodrigo.vivi
  Cc: anshuman.gupta, daniele.ceraolospurio, raag.jadav, riana.tauro,
	mallesh.koujalagi, aravind.iddamsetty, himal.prasad.ghimiray,
	arvind.yadav, syed.abdul.muqthyar.ahmed, nitin.r.gote



On 9/6/2026 7:26 PM, Badal Nilawar wrote:
> Define Intel-specific data structures and GUIDs needed to build
> Intel GPU CPER recoreds

typo

> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v2: Fixed sashiko warning about bit fields usage
> ---
>  drivers/gpu/drm/xe/xe_cper_types.h | 179 +++++++++++++++++++++++++++++
>  1 file changed, 179 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
> 
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> new file mode 100644
> index 000000000000..b81b70501e0e
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
> @@ -0,0 +1,179 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_TYPES_H_
> +#define _XE_CPER_TYPES_H_
> +
> +#include <linux/cper.h>
> +#include <linux/types.h>
> +#include <linux/uuid.h>
> +
> +/*
> + * Validation bits definition for validation_bits in struct
> + * xe_cper_sec_intel_err_hdr. When set, corresponding fields in header
> + * contains valid data
> + */
> +#define XE_CPER_VALID_LOCATION		0x0001
> +#define XE_CPER_VALID_FIRST_TIMESTAMP	0x0002
> +#define XE_CPER_VALID_SIG_ID		0x0004
> +#define XE_CPER_VALID_PCI_BDF		0x0008
> +#define XE_CPER_VALID_DRV_VERSION	0x0010
> +#define XE_CPER_VALID_FW_ID		0x0020

	BIT(0)
	BIT(1)
	...
or

enum xe_cper_valid_bits {
	XE_CPER_VALID_LOCATION = 0,
	XE_CPER_VALID_FIRST_TIMESTAMP,
	...	

	BIT(XE_CPER_VALID_LOCATION)
	BIT(XE_CPER_VALID_FIRST_TIMESTAMP)
	...

> +
> +/*
> + * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
> + *
> + * All values below are generated deterministically by uuid generator.
> + * Do not hand-edit the byte values.
> + */
> +
> +/* Creator IDs */
> +#define INTEL_CPER_CREATOR_XEKMD \
> +	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
> +		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
> +
> +#define INTEL_CPER_CREATOR_AMC \
> +	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
> +		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
> +
> +/* Notification Types */
> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
> +	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
> +		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)

only this one will be used for now, right?
maybe introduce other when needed?

> +
> +#define INTEL_CPER_NOTIFY_DRV_ERROR \
> +	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
> +		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
> +
> +/* Section Types */
> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
> +	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
> +		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)

as this seems to be new ABI, shouldn't we define it at least in our abi/ folder?

	drivers/gpu/drm/xe/abi/xe_cper_abi.h

> +
> +#pragma pack(push, 1)
> +
> +/**
> + * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header

if this is a Intel header, maybe it should start with intel_ prefix?

	intel_cper_section_...
> + *
> + * Fixed-size header for the Intel GPU error section of a CPER record.

if this is GPU section, shouldn't we have gpu_ tag in the struct name?

	intel_cper_section_gpu_error

> + * All multi-byte fields are little-endian; the structure is packed.
> + */
> +struct xe_cper_sec_intel_err_hdr {
> +	/** @error_class: Error classification (type, component, location, cause) */
> +	union {
> +		struct {
> +			/** @error_class.error_type: RAS error severity */
> +			u8  error_type;
> +			/** @error_class.error_component: IP block that raised the error */
> +			u8  error_component;
> +			/** @error_class.tile: Tile number */
> +			u8  tile;
> +			/** @error_class.instance: Instance within the tile */
> +			u32 instance;
> +			/** @error_class.cause: Error cause code */
> +			u32 cause;
> +			/** @error_class.reserved: Reserved, must be zero */
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @first_timestamp: Timestamp of the first occurrence of this error class */
> +	u64 first_timestamp;
> +	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
> +	u32 sig_id;
> +	/** @error_count: Number of times this error has been observed */
> +	u32 error_count;
> +	/** @validation_bits: Raw u16 view of all valid bits */
> +	u16 validation_bits;
> +	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
> +	char pci_bdf[16];
> +	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
> +	char drv_version[25];
> +	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
> +	char fw_id[256];
> +	/** @reserved: Reserved for future use, must be zero */
> +	u8 reserved[5];
> +};
> +
> +/**
> + * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
> + *
> + * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
> + * is available. The @event_queue flexible array holds @event_queue_count
> + * packed &xe_intel_priv_event_entry records.
> + */
> +struct xe_cper_sec_intel_error_info {
> +	/** @error_class: Error classification (mirrors the header error_class) */

if it is the same, shouldn't we define dedicated struct for it?
doing a plain copy/paste is error prone

> +	union {
> +		struct {
> +			u8  error_type;
> +			u8  error_component;
> +			u8  tile;
> +			u32 instance;
> +			u32 cause;
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @error_count: Total number of errors recorded */
> +	u32 error_count;
> +	/** @event_queue_length: Total byte size of the @event_queue array */
> +	u32 event_queue_length;
> +	/** @event_queue_count: Number of entries in @event_queue */
> +	u32 event_queue_count;
> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
> +	u8 event_queue[];
> +};
> +
> +/**
> + * struct xe_intel_priv_event_entry - Single error event in the event queue

no cper_ in the name?

> + *
> + * Each entry is variable-length; @entry_length gives the byte size of
> + * @metadata only (not including @entry_length or @timestamp).
> + */
> +struct xe_intel_priv_event_entry {
> +	/** @entry_length: Byte length of the @metadata payload */
> +	u32 entry_length;
> +	/** @timestamp: Hardware timestamp of this event */
> +	u64 timestamp;
> +	/** @metadata: Event-specific payload bytes */
> +	u8  metadata[];
> +};
> +
> +/**
> + * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
> + *
> + * Contains the standard CPER record header, section descriptor, and the
> + * Intel error section header. A &xe_cper_sec_intel_error_info payload
> + * (with its flexible @event_queue array) is appended dynamically.
> + */
> +struct xe_cper_nonstd_record {
> +	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
> +	struct cper_record_header record_hdr;
> +	/** @section_desc: CPER section descriptor */
> +	struct cper_section_descriptor section_desc;
> +	/** @intel_hdr: Intel-specific error section header */
> +	struct xe_cper_sec_intel_err_hdr intel_hdr;
> +};

hmm, this one looks like our helper struct, not a real ABI

[1] https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#format


> +
> +#pragma pack(pop)
> +
> +/**
> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
> + *
> + * Used to resolve the platform_id field in a CPER section descriptor.
> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
> + * with name string "platform/8086:<dev_id_hex_lower>".
> + */
> +struct xe_platform_id_entry {
> +	/** @device_id: PCI device ID */
> +	u16       device_id;
> +	/** @platform_id: Corresponding UUIDv5 platform GUID */
> +	guid_t    platform_id;
> +};
> +
> +#endif


^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures
  2026-09-07 13:13   ` Michal Wajdeczko
@ 2026-09-10 11:57     ` Nilawar, Badal
  0 siblings, 0 replies; 45+ messages in thread
From: Nilawar, Badal @ 2026-09-10 11:57 UTC (permalink / raw)
  To: Michal Wajdeczko, intel-xe, rodrigo.vivi
  Cc: anshuman.gupta, daniele.ceraolospurio, raag.jadav, riana.tauro,
	mallesh.koujalagi, aravind.iddamsetty, himal.prasad.ghimiray,
	arvind.yadav, syed.abdul.muqthyar.ahmed, nitin.r.gote


On 07-09-2026 18:43, Michal Wajdeczko wrote:
>
> On 9/6/2026 7:26 PM, Badal Nilawar wrote:
>> Define Intel-specific data structures and GUIDs needed to build
>> Intel GPU CPER recoreds
> typo
>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> v2: Fixed sashiko warning about bit fields usage
>> ---
>>   drivers/gpu/drm/xe/xe_cper_types.h | 179 +++++++++++++++++++++++++++++
>>   1 file changed, 179 insertions(+)
>>   create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
>> new file mode 100644
>> index 000000000000..b81b70501e0e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
>> @@ -0,0 +1,179 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_CPER_TYPES_H_
>> +#define _XE_CPER_TYPES_H_
>> +
>> +#include <linux/cper.h>
>> +#include <linux/types.h>
>> +#include <linux/uuid.h>
>> +
>> +/*
>> + * Validation bits definition for validation_bits in struct
>> + * xe_cper_sec_intel_err_hdr. When set, corresponding fields in header
>> + * contains valid data
>> + */
>> +#define XE_CPER_VALID_LOCATION		0x0001
>> +#define XE_CPER_VALID_FIRST_TIMESTAMP	0x0002
>> +#define XE_CPER_VALID_SIG_ID		0x0004
>> +#define XE_CPER_VALID_PCI_BDF		0x0008
>> +#define XE_CPER_VALID_DRV_VERSION	0x0010
>> +#define XE_CPER_VALID_FW_ID		0x0020
> 	BIT(0)
> 	BIT(1)
> 	...
> or
>
> enum xe_cper_valid_bits {
> 	XE_CPER_VALID_LOCATION = 0,
> 	XE_CPER_VALID_FIRST_TIMESTAMP,
> 	...	
>
> 	BIT(XE_CPER_VALID_LOCATION)
> 	BIT(XE_CPER_VALID_FIRST_TIMESTAMP)

Followed the include/linux/cper.h

/*
  * Validation bits definition for validation_bits in struct
  * cper_record_header. If set, corresponding fields in struct
  * cper_record_header contain valid information.
  */
#define CPER_VALID_PLATFORM_ID                0x0001
#define CPER_VALID_TIMESTAMP                    0x0002
#define CPER_VALID_PARTITION_ID                0x0004

> 	...
>
>> +
>> +/*
>> + * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
>> + *
>> + * All values below are generated deterministically by uuid generator.
>> + * Do not hand-edit the byte values.
>> + */
>> +
>> +/* Creator IDs */
>> +#define INTEL_CPER_CREATOR_XEKMD \
>> +	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
>> +		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
>> +
>> +#define INTEL_CPER_CREATOR_AMC \
>> +	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
>> +		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
>> +
>> +/* Notification Types */
>> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
>> +	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
>> +		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
> only this one will be used for now, right?
> maybe introduce other when needed?
Sure.
>
>> +
>> +#define INTEL_CPER_NOTIFY_DRV_ERROR \
>> +	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
>> +		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
>> +
>> +/* Section Types */
>> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
>> +	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
>> +		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
> as this seems to be new ABI, shouldn't we define it at least in our abi/ folder?
>
> 	drivers/gpu/drm/xe/abi/xe_cper_abi.h
You mean above GUIDs?
>
>> +
>> +#pragma pack(push, 1)
>> +
>> +/**
>> + * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header
> if this is a Intel header, maybe it should start with intel_ prefix?
>
> 	intel_cper_section_...
>> + *
>> + * Fixed-size header for the Intel GPU error section of a CPER record.
> if this is GPU section, shouldn't we have gpu_ tag in the struct name?
>
> 	intel_cper_section_gpu_error
Followed the specs. Fields from these structures will be overloaded for 
software CPER as well.
>
>> + * All multi-byte fields are little-endian; the structure is packed.
>> + */
>> +struct xe_cper_sec_intel_err_hdr {
>> +	/** @error_class: Error classification (type, component, location, cause) */
>> +	union {
>> +		struct {
>> +			/** @error_class.error_type: RAS error severity */
>> +			u8  error_type;
>> +			/** @error_class.error_component: IP block that raised the error */
>> +			u8  error_component;
>> +			/** @error_class.tile: Tile number */
>> +			u8  tile;
>> +			/** @error_class.instance: Instance within the tile */
>> +			u32 instance;
>> +			/** @error_class.cause: Error cause code */
>> +			u32 cause;
>> +			/** @error_class.reserved: Reserved, must be zero */
>> +			u8  reserved;
>> +		} error_class;
>> +		/** @class: Raw byte view of the error class */
>> +		u8 class[12];
>> +	};
>> +	/** @first_timestamp: Timestamp of the first occurrence of this error class */
>> +	u64 first_timestamp;
>> +	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
>> +	u32 sig_id;
>> +	/** @error_count: Number of times this error has been observed */
>> +	u32 error_count;
>> +	/** @validation_bits: Raw u16 view of all valid bits */
>> +	u16 validation_bits;
>> +	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
>> +	char pci_bdf[16];
>> +	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
>> +	char drv_version[25];
>> +	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
>> +	char fw_id[256];
>> +	/** @reserved: Reserved for future use, must be zero */
>> +	u8 reserved[5];
>> +};
>> +
>> +/**
>> + * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
>> + *
>> + * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
>> + * is available. The @event_queue flexible array holds @event_queue_count
>> + * packed &xe_intel_priv_event_entry records.
>> + */
>> +struct xe_cper_sec_intel_error_info {
>> +	/** @error_class: Error classification (mirrors the header error_class) */
> if it is the same, shouldn't we define dedicated struct for it?
> doing a plain copy/paste is error prone
Sure.
>
>> +	union {
>> +		struct {
>> +			u8  error_type;
>> +			u8  error_component;
>> +			u8  tile;
>> +			u32 instance;
>> +			u32 cause;
>> +			u8  reserved;
>> +		} error_class;
>> +		/** @class: Raw byte view of the error class */
>> +		u8 class[12];
>> +	};
>> +	/** @error_count: Total number of errors recorded */
>> +	u32 error_count;
>> +	/** @event_queue_length: Total byte size of the @event_queue array */
>> +	u32 event_queue_length;
>> +	/** @event_queue_count: Number of entries in @event_queue */
>> +	u32 event_queue_count;
>> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
>> +	u8 event_queue[];
>> +};
>> +
>> +/**
>> + * struct xe_intel_priv_event_entry - Single error event in the event queue
> no cper_ in the name?
will add.
>
>> + *
>> + * Each entry is variable-length; @entry_length gives the byte size of
>> + * @metadata only (not including @entry_length or @timestamp).
>> + */
>> +struct xe_intel_priv_event_entry {
>> +	/** @entry_length: Byte length of the @metadata payload */
>> +	u32 entry_length;
>> +	/** @timestamp: Hardware timestamp of this event */
>> +	u64 timestamp;
>> +	/** @metadata: Event-specific payload bytes */
>> +	u8  metadata[];
>> +};
>> +
>> +/**
>> + * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
>> + *
>> + * Contains the standard CPER record header, section descriptor, and the
>> + * Intel error section header. A &xe_cper_sec_intel_error_info payload
>> + * (with its flexible @event_queue array) is appended dynamically.
>> + */
>> +struct xe_cper_nonstd_record {
>> +	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
>> +	struct cper_record_header record_hdr;
>> +	/** @section_desc: CPER section descriptor */
>> +	struct cper_section_descriptor section_desc;
>> +	/** @intel_hdr: Intel-specific error section header */
>> +	struct xe_cper_sec_intel_err_hdr intel_hdr;
>> +};
> hmm, this one looks like our helper struct, not a real ABI
>
> [1] https://uefi.org/specs/UEFI/2.10/Apx_N_Common_Platform_Error_Record.html#format

Yes it is helper structure.

Thanks,
Badal

>
>
>> +
>> +#pragma pack(pop)
>> +
>> +/**
>> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
>> + *
>> + * Used to resolve the platform_id field in a CPER section descriptor.
>> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
>> + * with name string "platform/8086:<dev_id_hex_lower>".
>> + */
>> +struct xe_platform_id_entry {
>> +	/** @device_id: PCI device ID */
>> +	u16       device_id;
>> +	/** @platform_id: Corresponding UUIDv5 platform GUID */
>> +	guid_t    platform_id;
>> +};
>> +
>> +#endif

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures
  2026-09-06 17:26 ` [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures Badal Nilawar
  2026-09-07 13:13   ` Michal Wajdeczko
@ 2026-09-08 10:18   ` Raag Jadav
  2026-09-10 13:36     ` Nilawar, Badal
  1 sibling, 1 reply; 45+ messages in thread
From: Raag Jadav @ 2026-09-08 10:18 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:08PM +0530, Badal Nilawar wrote:
> Define Intel-specific data structures and GUIDs needed to build
> Intel GPU CPER recoreds

No standalone structs please! These need to be introduced in the patch
that use them.

Raag

> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> v2: Fixed sashiko warning about bit fields usage
> ---
>  drivers/gpu/drm/xe/xe_cper_types.h | 179 +++++++++++++++++++++++++++++
>  1 file changed, 179 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
> 
> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
> new file mode 100644
> index 000000000000..b81b70501e0e
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
> @@ -0,0 +1,179 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_CPER_TYPES_H_
> +#define _XE_CPER_TYPES_H_
> +
> +#include <linux/cper.h>
> +#include <linux/types.h>
> +#include <linux/uuid.h>
> +
> +/*
> + * Validation bits definition for validation_bits in struct
> + * xe_cper_sec_intel_err_hdr. When set, corresponding fields in header
> + * contains valid data
> + */
> +#define XE_CPER_VALID_LOCATION		0x0001
> +#define XE_CPER_VALID_FIRST_TIMESTAMP	0x0002
> +#define XE_CPER_VALID_SIG_ID		0x0004
> +#define XE_CPER_VALID_PCI_BDF		0x0008
> +#define XE_CPER_VALID_DRV_VERSION	0x0010
> +#define XE_CPER_VALID_FW_ID		0x0020
> +
> +/*
> + * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
> + *
> + * All values below are generated deterministically by uuid generator.
> + * Do not hand-edit the byte values.
> + */
> +
> +/* Creator IDs */
> +#define INTEL_CPER_CREATOR_XEKMD \
> +	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
> +		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
> +
> +#define INTEL_CPER_CREATOR_AMC \
> +	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
> +		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
> +
> +/* Notification Types */
> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
> +	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
> +		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
> +
> +#define INTEL_CPER_NOTIFY_DRV_ERROR \
> +	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
> +		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
> +
> +/* Section Types */
> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
> +	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
> +		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
> +
> +#pragma pack(push, 1)
> +
> +/**
> + * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header
> + *
> + * Fixed-size header for the Intel GPU error section of a CPER record.
> + * All multi-byte fields are little-endian; the structure is packed.
> + */
> +struct xe_cper_sec_intel_err_hdr {
> +	/** @error_class: Error classification (type, component, location, cause) */
> +	union {
> +		struct {
> +			/** @error_class.error_type: RAS error severity */
> +			u8  error_type;
> +			/** @error_class.error_component: IP block that raised the error */
> +			u8  error_component;
> +			/** @error_class.tile: Tile number */
> +			u8  tile;
> +			/** @error_class.instance: Instance within the tile */
> +			u32 instance;
> +			/** @error_class.cause: Error cause code */
> +			u32 cause;
> +			/** @error_class.reserved: Reserved, must be zero */
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @first_timestamp: Timestamp of the first occurrence of this error class */
> +	u64 first_timestamp;
> +	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
> +	u32 sig_id;
> +	/** @error_count: Number of times this error has been observed */
> +	u32 error_count;
> +	/** @validation_bits: Raw u16 view of all valid bits */
> +	u16 validation_bits;
> +	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
> +	char pci_bdf[16];
> +	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
> +	char drv_version[25];
> +	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
> +	char fw_id[256];
> +	/** @reserved: Reserved for future use, must be zero */
> +	u8 reserved[5];
> +};
> +
> +/**
> + * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
> + *
> + * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
> + * is available. The @event_queue flexible array holds @event_queue_count
> + * packed &xe_intel_priv_event_entry records.
> + */
> +struct xe_cper_sec_intel_error_info {
> +	/** @error_class: Error classification (mirrors the header error_class) */
> +	union {
> +		struct {
> +			u8  error_type;
> +			u8  error_component;
> +			u8  tile;
> +			u32 instance;
> +			u32 cause;
> +			u8  reserved;
> +		} error_class;
> +		/** @class: Raw byte view of the error class */
> +		u8 class[12];
> +	};
> +	/** @error_count: Total number of errors recorded */
> +	u32 error_count;
> +	/** @event_queue_length: Total byte size of the @event_queue array */
> +	u32 event_queue_length;
> +	/** @event_queue_count: Number of entries in @event_queue */
> +	u32 event_queue_count;
> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
> +	u8 event_queue[];
> +};
> +
> +/**
> + * struct xe_intel_priv_event_entry - Single error event in the event queue
> + *
> + * Each entry is variable-length; @entry_length gives the byte size of
> + * @metadata only (not including @entry_length or @timestamp).
> + */
> +struct xe_intel_priv_event_entry {
> +	/** @entry_length: Byte length of the @metadata payload */
> +	u32 entry_length;
> +	/** @timestamp: Hardware timestamp of this event */
> +	u64 timestamp;
> +	/** @metadata: Event-specific payload bytes */
> +	u8  metadata[];
> +};
> +
> +/**
> + * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
> + *
> + * Contains the standard CPER record header, section descriptor, and the
> + * Intel error section header. A &xe_cper_sec_intel_error_info payload
> + * (with its flexible @event_queue array) is appended dynamically.
> + */
> +struct xe_cper_nonstd_record {
> +	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
> +	struct cper_record_header record_hdr;
> +	/** @section_desc: CPER section descriptor */
> +	struct cper_section_descriptor section_desc;
> +	/** @intel_hdr: Intel-specific error section header */
> +	struct xe_cper_sec_intel_err_hdr intel_hdr;
> +};
> +
> +#pragma pack(pop)
> +
> +/**
> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
> + *
> + * Used to resolve the platform_id field in a CPER section descriptor.
> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
> + * with name string "platform/8086:<dev_id_hex_lower>".
> + */
> +struct xe_platform_id_entry {
> +	/** @device_id: PCI device ID */
> +	u16       device_id;
> +	/** @platform_id: Corresponding UUIDv5 platform GUID */
> +	guid_t    platform_id;
> +};
> +
> +#endif
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures
  2026-09-08 10:18   ` Raag Jadav
@ 2026-09-10 13:36     ` Nilawar, Badal
  0 siblings, 0 replies; 45+ messages in thread
From: Nilawar, Badal @ 2026-09-10 13:36 UTC (permalink / raw)
  To: Raag Jadav
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote


On 08-09-2026 15:48, Raag Jadav wrote:
> On Sun, Sep 06, 2026 at 10:56:08PM +0530, Badal Nilawar wrote:
>> Define Intel-specific data structures and GUIDs needed to build
>> Intel GPU CPER recoreds
> No standalone structs please! These need to be introduced in the patch
> that use them.

Ok, intent was to keep all the Intel-specific CPER structures in a 
single patch for easier review.

Thanks,
Badal

>
> Raag
>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> v2: Fixed sashiko warning about bit fields usage
>> ---
>>   drivers/gpu/drm/xe/xe_cper_types.h | 179 +++++++++++++++++++++++++++++
>>   1 file changed, 179 insertions(+)
>>   create mode 100644 drivers/gpu/drm/xe/xe_cper_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/xe_cper_types.h b/drivers/gpu/drm/xe/xe_cper_types.h
>> new file mode 100644
>> index 000000000000..b81b70501e0e
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_cper_types.h
>> @@ -0,0 +1,179 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_CPER_TYPES_H_
>> +#define _XE_CPER_TYPES_H_
>> +
>> +#include <linux/cper.h>
>> +#include <linux/types.h>
>> +#include <linux/uuid.h>
>> +
>> +/*
>> + * Validation bits definition for validation_bits in struct
>> + * xe_cper_sec_intel_err_hdr. When set, corresponding fields in header
>> + * contains valid data
>> + */
>> +#define XE_CPER_VALID_LOCATION		0x0001
>> +#define XE_CPER_VALID_FIRST_TIMESTAMP	0x0002
>> +#define XE_CPER_VALID_SIG_ID		0x0004
>> +#define XE_CPER_VALID_PCI_BDF		0x0008
>> +#define XE_CPER_VALID_DRV_VERSION	0x0010
>> +#define XE_CPER_VALID_FW_ID		0x0020
>> +
>> +/*
>> + * Intel CPER GUID Namespace — RFC 9562 UUIDv5 (SHA-1 name-based)
>> + *
>> + * All values below are generated deterministically by uuid generator.
>> + * Do not hand-edit the byte values.
>> + */
>> +
>> +/* Creator IDs */
>> +#define INTEL_CPER_CREATOR_XEKMD \
>> +	GUID_INIT(0x9a42070f, 0xdf9d, 0x555e, \
>> +		  0xba, 0x02, 0x7c, 0xbc, 0x86, 0x3d, 0x37, 0x1c)
>> +
>> +#define INTEL_CPER_CREATOR_AMC \
>> +	GUID_INIT(0x215803da, 0xfc7a, 0x5925, \
>> +		  0xb7, 0x8b, 0x1f, 0xc1, 0x19, 0x61, 0x58, 0xd1)
>> +
>> +/* Notification Types */
>> +#define INTEL_CPER_NOTIFY_GPU_ERROR \
>> +	GUID_INIT(0x4ae12aef, 0x8745, 0x5fc7, \
>> +		  0xb9, 0x96, 0x71, 0xee, 0xbb, 0x51, 0xf2, 0x23)
>> +
>> +#define INTEL_CPER_NOTIFY_DRV_ERROR \
>> +	GUID_INIT(0xcef7e934, 0x51e7, 0x535f, \
>> +		  0xa6, 0x78, 0x5a, 0x4c, 0xcc, 0xb6, 0x96, 0x09)
>> +
>> +/* Section Types */
>> +#define INTEL_CPER_SECTION_ACCEL_GENERIC \
>> +	GUID_INIT(0xea9d8f84, 0x4258, 0x5227, \
>> +		  0x80, 0x28, 0xb9, 0xb1, 0x3e, 0x6d, 0x58, 0xb0)
>> +
>> +#pragma pack(push, 1)
>> +
>> +/**
>> + * struct xe_cper_sec_intel_err_hdr - Intel-specific CPER error section header
>> + *
>> + * Fixed-size header for the Intel GPU error section of a CPER record.
>> + * All multi-byte fields are little-endian; the structure is packed.
>> + */
>> +struct xe_cper_sec_intel_err_hdr {
>> +	/** @error_class: Error classification (type, component, location, cause) */
>> +	union {
>> +		struct {
>> +			/** @error_class.error_type: RAS error severity */
>> +			u8  error_type;
>> +			/** @error_class.error_component: IP block that raised the error */
>> +			u8  error_component;
>> +			/** @error_class.tile: Tile number */
>> +			u8  tile;
>> +			/** @error_class.instance: Instance within the tile */
>> +			u32 instance;
>> +			/** @error_class.cause: Error cause code */
>> +			u32 cause;
>> +			/** @error_class.reserved: Reserved, must be zero */
>> +			u8  reserved;
>> +		} error_class;
>> +		/** @class: Raw byte view of the error class */
>> +		u8 class[12];
>> +	};
>> +	/** @first_timestamp: Timestamp of the first occurrence of this error class */
>> +	u64 first_timestamp;
>> +	/** @sig_id: Aggregated error class SIG ID; set to U32_MAX if unknown */
>> +	u32 sig_id;
>> +	/** @error_count: Number of times this error has been observed */
>> +	u32 error_count;
>> +	/** @validation_bits: Raw u16 view of all valid bits */
>> +	u16 validation_bits;
>> +	/** @pci_bdf: PCI location string, format "DDDD:bb:dd.f" */
>> +	char pci_bdf[16];
>> +	/** @drv_version: Driver source version string (THIS_MODULE->srcversion) */
>> +	char drv_version[25];
>> +	/** @fw_id: Firmware version string (GFSP+PCODE+CSC+GUC or MNG+NUC+RAS+GUC) */
>> +	char fw_id[256];
>> +	/** @reserved: Reserved for future use, must be zero */
>> +	u8 reserved[5];
>> +};
>> +
>> +/**
>> + * struct xe_cper_sec_intel_error_info - Variable-length Intel GPU error payload
>> + *
>> + * Appended after &xe_cper_sec_intel_err_hdr when detailed per-event data
>> + * is available. The @event_queue flexible array holds @event_queue_count
>> + * packed &xe_intel_priv_event_entry records.
>> + */
>> +struct xe_cper_sec_intel_error_info {
>> +	/** @error_class: Error classification (mirrors the header error_class) */
>> +	union {
>> +		struct {
>> +			u8  error_type;
>> +			u8  error_component;
>> +			u8  tile;
>> +			u32 instance;
>> +			u32 cause;
>> +			u8  reserved;
>> +		} error_class;
>> +		/** @class: Raw byte view of the error class */
>> +		u8 class[12];
>> +	};
>> +	/** @error_count: Total number of errors recorded */
>> +	u32 error_count;
>> +	/** @event_queue_length: Total byte size of the @event_queue array */
>> +	u32 event_queue_length;
>> +	/** @event_queue_count: Number of entries in @event_queue */
>> +	u32 event_queue_count;
>> +	/** @event_queue: Packed array of &xe_intel_priv_event_entry records */
>> +	u8 event_queue[];
>> +};
>> +
>> +/**
>> + * struct xe_intel_priv_event_entry - Single error event in the event queue
>> + *
>> + * Each entry is variable-length; @entry_length gives the byte size of
>> + * @metadata only (not including @entry_length or @timestamp).
>> + */
>> +struct xe_intel_priv_event_entry {
>> +	/** @entry_length: Byte length of the @metadata payload */
>> +	u32 entry_length;
>> +	/** @timestamp: Hardware timestamp of this event */
>> +	u64 timestamp;
>> +	/** @metadata: Event-specific payload bytes */
>> +	u8  metadata[];
>> +};
>> +
>> +/**
>> + * struct xe_cper_nonstd_record - Fixed-size portion of an Intel GPU CPER record
>> + *
>> + * Contains the standard CPER record header, section descriptor, and the
>> + * Intel error section header. A &xe_cper_sec_intel_error_info payload
>> + * (with its flexible @event_queue array) is appended dynamically.
>> + */
>> +struct xe_cper_nonstd_record {
>> +	/** @record_hdr: Standard CPER record header (UEFI Appendix N.2.1) */
>> +	struct cper_record_header record_hdr;
>> +	/** @section_desc: CPER section descriptor */
>> +	struct cper_section_descriptor section_desc;
>> +	/** @intel_hdr: Intel-specific error section header */
>> +	struct xe_cper_sec_intel_err_hdr intel_hdr;
>> +};
>> +
>> +#pragma pack(pop)
>> +
>> +/**
>> + * struct xe_platform_id_entry - Mapping from PCI device ID to CPER platform GUID
>> + *
>> + * Used to resolve the platform_id field in a CPER section descriptor.
>> + * GUIDs are UUIDv5 (RFC 9562, SHA-1) derived from the Intel CPER namespace
>> + * with name string "platform/8086:<dev_id_hex_lower>".
>> + */
>> +struct xe_platform_id_entry {
>> +	/** @device_id: PCI device ID */
>> +	u16       device_id;
>> +	/** @platform_id: Corresponding UUIDv5 platform GUID */
>> +	guid_t    platform_id;
>> +};
>> +
>> +#endif
>> -- 
>> 2.54.0
>>

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 04/12] drm/xe/cper: Prepare CPER record
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (4 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:27   ` sashiko-bot
  2026-09-08 10:20   ` Raag Jadav
  2026-09-06 17:26 ` [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI Badal Nilawar
                   ` (9 subsequent siblings)
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Initialize Intel-specific CPER metadata and construct
CPER record for Intel GPU hardware errors.

v2:
 - Encode cper_record_header timestamp in BCD format (sashiko)
 - Guard against NULL THIS_MODULE->srcversion (sashiko)

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_regs.h |   2 +
 drivers/gpu/drm/xe/xe_cper.c      | 171 ++++++++++++++++++++++++++++++
 2 files changed, 173 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index ef4746b7b5d3..580c3dad858a 100644
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -30,6 +30,8 @@
 #define XEHP_MTCFG_ADDR				XE_REG(0x101800)
 #define   TILE_COUNT				REG_GENMASK(15, 8)
 
+#define CRI_FRU_ID				XE_REG(0x102008)
+
 #define GGC					XE_REG(0x108040)
 #define   GMS_MASK				REG_GENMASK(15, 8)
 #define   GGMS_MASK				REG_GENMASK(7, 6)
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index f04a91223a43..31ca53ce1aa7 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -3,16 +3,176 @@
  * Copyright © 2026 Intel Corporation
  */
 
+#include <linux/bcd.h>
 #include <linux/pci.h>
 
 #include <drm/drm_print.h>
 
+#include "regs/xe_regs.h"
 #include "xe_cper.h"
+#include "xe_cper_types.h"
 #include "xe_device.h"
+#include "xe_mmio.h"
 #include "xe_printk.h"
 #include "xe_ras.h"
 #include "xe_ras_types.h"
 
+static const struct xe_platform_id_entry xe_platform_ids[] = {
+	/* 0x674C  platform/8086:674c */
+	{ 0x674C, GUID_INIT(0x9046afe5, 0x9041, 0x5124,
+			    0x86, 0x14, 0x92, 0x55, 0x0d, 0x9e, 0x9d, 0xa6) },
+};
+
+static const guid_t *lookup_platform_id(const struct pci_dev *pdev)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(xe_platform_ids); i++)
+		if (xe_platform_ids[i].device_id == pdev->device)
+			return &xe_platform_ids[i].platform_id;
+	return NULL;
+}
+
+static u64 cper_timestamp_now(void)
+{
+	struct tm tm;
+	u64 ts = 0;
+	u8 *p = (u8 *)&ts;
+	int year;
+
+	time64_to_tm(ktime_get_real_seconds(), 0, &tm);
+
+	year = tm.tm_year + 1900;
+
+	p[0] = bin2bcd(tm.tm_sec);
+	p[1] = bin2bcd(tm.tm_min);
+	p[2] = bin2bcd(tm.tm_hour);
+	p[3] = 0x1; /* precise time */
+	p[4] = bin2bcd(tm.tm_mday);
+	p[5] = bin2bcd(tm.tm_mon + 1);
+	p[6] = bin2bcd(year % 100);
+	p[7] = bin2bcd(year / 100);
+
+	return ts;
+}
+
+static guid_t read_fru_id(struct xe_device *xe)
+{
+	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
+	guid_t guid = GUID_INIT(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
+	u64 val;
+
+	val = xe_mmio_read64_2x32(mmio, CRI_FRU_ID);
+
+	memcpy(&guid, &val, sizeof(val));
+
+	return guid;
+}
+
+static void fill_fw_id(struct xe_device *xe, struct xe_cper_sec_intel_err_hdr *ihdr)
+{
+	/* TODO: populate ihdr->fw_id from firmware version queries */
+}
+
+static void xe_cper_init_intel_err_hdr(struct xe_device *xe, const u8 location[12],
+				       u64 first_timestamp, u32 sig_id, u32 error_count,
+				       struct xe_cper_sec_intel_err_hdr *ihdr)
+{
+	if (location) {
+		memcpy(&ihdr->error_class, location, sizeof(ihdr->error_class));
+		ihdr->validation_bits |= XE_CPER_VALID_LOCATION;
+	}
+
+	if (first_timestamp) {
+		ihdr->first_timestamp = first_timestamp;
+		ihdr->validation_bits |= XE_CPER_VALID_FIRST_TIMESTAMP;
+	}
+
+	if (sig_id != U32_MAX) {
+		ihdr->sig_id = sig_id;
+		ihdr->validation_bits |= XE_CPER_VALID_SIG_ID;
+	}
+
+	ihdr->error_count = error_count;
+
+	strscpy(ihdr->pci_bdf, pci_name(to_pci_dev(xe->drm.dev)), sizeof(ihdr->pci_bdf));
+	ihdr->validation_bits |= XE_CPER_VALID_PCI_BDF;
+
+#ifdef MODULE
+	if (THIS_MODULE->srcversion) {
+		strscpy(ihdr->drv_version, THIS_MODULE->srcversion, sizeof(ihdr->drv_version));
+		ihdr->validation_bits |= XE_CPER_VALID_DRV_VERSION;
+	}
+#endif
+
+	fill_fw_id(xe, ihdr);
+}
+
+static void xe_cper_record_emit(struct xe_device *xe, u8 severity,
+				guid_t *notification_type,
+				struct xe_cper_sec_intel_err_hdr *ihdr,
+				const void *einfo, u32 einfo_len)
+{
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+	const guid_t *platform_id = lookup_platform_id(pdev);
+	u32 total_len = sizeof(struct xe_cper_nonstd_record) + einfo_len;
+	struct cper_section_descriptor *sdesc;
+	struct cper_record_header *rhdr;
+	struct xe_cper_nonstd_record *rec;
+
+	rec = kzalloc(total_len, GFP_KERNEL);
+	if (!rec)
+		return;
+
+	rhdr  = &rec->record_hdr;
+	sdesc = &rec->section_desc;
+
+	/* Assemble the CPER record header (UEFI Appendix N.2.1) */
+	memcpy(rhdr->signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
+	rhdr->revision          = CPER_RECORD_REV;
+	rhdr->signature_end     = CPER_SIG_END;
+	rhdr->section_count     = 1;
+	rhdr->error_severity    = severity;
+	rhdr->validation_bits   = CPER_VALID_TIMESTAMP;
+	rhdr->record_length     = total_len;
+	rhdr->timestamp         = cper_timestamp_now();
+	if (platform_id) {
+		rhdr->platform_id      = *platform_id;
+		rhdr->validation_bits |= CPER_VALID_PLATFORM_ID;
+	}
+	rhdr->creator_id        = INTEL_CPER_CREATOR_XEKMD;
+	rhdr->notification_type = *notification_type;
+	rhdr->record_id         = cper_next_record_id();
+	rhdr->flags             = 0;
+
+	/* Assemble the section descriptor (UEFI Appendix N.2.2) */
+	sdesc->section_offset   = sizeof(struct cper_record_header) +
+				  sizeof(struct cper_section_descriptor);
+	sdesc->section_length   = sizeof(struct xe_cper_sec_intel_err_hdr) + einfo_len;
+	sdesc->revision         = CPER_RECORD_REV;
+	/*
+	 * Set validation_bits using CPER_SEC_VALID_FRU_ID / CPER_SEC_VALID_FRU_TEXT
+	 * when the corresponding fields are populated.
+	 */
+	sdesc->validation_bits  = 0;
+	sdesc->reserved         = 0;
+	sdesc->flags            = 0;
+	sdesc->section_type     = INTEL_CPER_SECTION_ACCEL_GENERIC;
+	sdesc->fru_id = read_fru_id(xe);
+	sdesc->validation_bits |= CPER_SEC_VALID_FRU_ID;
+	sdesc->section_severity = severity;
+
+	/* Copy the Intel-specific section header (updated with BDF/version) */
+	rec->intel_hdr = *ihdr;
+
+	/* Append optional variable-length error info */
+	if (einfo && einfo_len)
+		memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
+
+	/* TODO: Emit trace event */
+
+	kfree(rec);
+}
 /**
  * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
  * @pdev: PCI device associated with the Xe device
@@ -30,6 +190,7 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
 	struct xe_device *xe = pdev_to_xe_device(pdev);
 	struct xe_ras_get_counter_response local_resp = {};
 	struct xe_ras_get_counter_response *counter_response = response;
+	struct xe_cper_sec_intel_err_hdr ihdr = {};
 
 	if (!xe)
 		return;
@@ -48,5 +209,15 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
 		}
 	}
 
+	xe_cper_init_intel_err_hdr(xe,
+				   (const u8 *)counter,
+				   counter_response->timestamp,
+				   sigid,
+				   counter_response->value,
+				   &ihdr);
+
+	xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
+			    &ihdr, NULL, 0);
+
 	/* TODO */
 }
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 04/12] drm/xe/cper: Prepare CPER record
  2026-09-06 17:26 ` [PATCH v3 04/12] drm/xe/cper: Prepare CPER record Badal Nilawar
@ 2026-09-06 17:27   ` sashiko-bot
  2026-09-08 10:20   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:27 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [High] Reading the PF-only CRI_FRU_ID SOC_BASE MMIO resource from a Virtual Function (VF) context will cause a hardware timeout.

Pre-existing issues:
- [High] Logic inversion in `xe_emit_hardware_error_cper` prevents emitting CPER records for hardware errors.
--

commit 9f7667556e38b9fe8c03f7e28c7370b664d666ce
Author: Badal Nilawar <badal.nilawar@intel.com>
Date:   Sun Sep 6 17:26:09 2026 +0000

    drm/xe/cper: Prepare CPER record

    Initialize Intel-specific CPER metadata and construct
    CPER record for Intel GPU hardware errors.

> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index f04a91223a43c..31ca53ce1aa75 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> +static guid_t read_fru_id(struct xe_device *xe)
> +{
> +	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> +	guid_t guid = GUID_INIT(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
> +	u64 val;
> +
> +	val = xe_mmio_read64_2x32(mmio, CRI_FRU_ID);
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

[Severity: High]
Does this code execute safely on Virtual Functions?

Accessing PF-only SOC_BASE registers from a VF causes hardware failures or
MMIO timeouts. The CRI_FRU_ID register is in the SOC_BASE region.

When a hardware error is logged from a Virtual Function,
xe_emit_hardware_error_cper() calls xe_cper_record_emit() which
unconditionally calls read_fru_id(). Shouldn't this read be guarded with an
IS_SRIOV_VF(xe) check to prevent a driver crash or wedged device?

> +
> +	memcpy(&guid, &val, sizeof(val));
> +
> +	return guid;
> +}
[ ... ]
> @@ -48,5 +209,15 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  		}
>  	}
>  
> +	xe_cper_init_intel_err_hdr(xe,
> +				   (const u8 *)counter,
> +				   counter_response->timestamp,
> +				   sigid,
> +				   counter_response->value,
> +				   &ihdr);
> +
> +	xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +			    &ihdr, NULL, 0);
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

[Severity: High]
This isn't a bug introduced by this patch, but will this code ever execute
for hardware errors?

Earlier in xe_emit_hardware_error_cper(), there is a pre-existing check:

	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
		return;

This appears to abort execution for all valid hardware SIGIDs, meaning the
new CPER record generation will act as dead code and fail to emit records
for genuine hardware errors. Could we fix that logic inversion?

> +
>  	/* TODO */
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=4

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 04/12] drm/xe/cper: Prepare CPER record
  2026-09-06 17:26 ` [PATCH v3 04/12] drm/xe/cper: Prepare CPER record Badal Nilawar
  2026-09-06 17:27   ` sashiko-bot
@ 2026-09-08 10:20   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: Raag Jadav @ 2026-09-08 10:20 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:09PM +0530, Badal Nilawar wrote:
> Initialize Intel-specific CPER metadata and construct
> CPER record for Intel GPU hardware errors.

...

> @@ -48,5 +209,15 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  		}
>  	}
>  
> +	xe_cper_init_intel_err_hdr(xe,
> +				   (const u8 *)counter,
> +				   counter_response->timestamp,
> +				   sigid,
> +				   counter_response->value,
> +				   &ihdr);
> +
> +	xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +			    &ihdr, NULL, 0);

Hm, can these two calls be split in their own patches which also
introduce their respective structs?

Raag

> +
>  	/* TODO */
>  }
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (5 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 04/12] drm/xe/cper: Prepare CPER record Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:17   ` sashiko-bot
  2026-09-09  8:03   ` Raag Jadav
  2026-09-06 17:26 ` [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records Badal Nilawar
                   ` (8 subsequent siblings)
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Retrieve the RAS info queue data, in multiple chunks, and assemble
it into flat raw buffer. Follow up patch will use this data to
prepare cper error info.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-opus-4.8
---
 drivers/gpu/drm/xe/xe_ras.c                   | 139 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_ras.h                   |   3 +
 drivers/gpu/drm/xe/xe_ras_types.h             | 118 ++++++++++++++-
 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
 4 files changed, 260 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 0fb9065cdd76..7e3e62750448 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -797,6 +797,145 @@ int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 th
 	return 0;
 }
 
+static int get_info_queue_data(struct xe_device *xe,
+			       const struct xe_ras_get_info_queue_data_request *req,
+			       struct xe_ras_get_info_queue_data_response *out)
+{
+	struct xe_ras_get_info_queue_data_response response = {0};
+	struct xe_sysctrl_mailbox_command command = {0};
+	size_t rlen;
+	int ret;
+
+	xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP,
+				  XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA,
+				  (void *)req, sizeof(*req), &response, sizeof(response));
+
+	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
+	if (ret) {
+		xe_err(xe, "sysctrl: failed to get info queue data %d\n", ret);
+		return ret;
+	}
+
+	if (rlen != sizeof(response)) {
+		xe_err(xe, "sysctrl: unexpected get info queue data response length %zu (expected %zu)\n",
+		       rlen, sizeof(response));
+		return -EIO;
+	}
+
+	xe_dbg(xe, "[RAS]: info queue data: status=%u chunk_size=%u flags=0x%x\n",
+	       response.operation_status,
+	       response.queue_response.queue_header.chunk_size,
+	       response.queue_response.queue_header.flags);
+
+	*out = response;
+	return 0;
+}
+
+/**
+ * xe_ras_drain_info_queue_raw - Drain the full RAS info queue into a flat buffer.
+ * @xe: xe device
+ * @counter_resp: counter response carrying the first embedded chunk and the
+ *                counter identifier used as the source context for subsequent
+ *                GET_INFO_QUEUE_DATA fetches
+ * @raw_buf: destination buffer supplied by the caller
+ * @raw_buf_size: size of @raw_buf in bytes; also caps the total amount of data
+ *                assembled from the info queue
+ *
+ * Copies the first chunk already embedded in @counter_resp, then loops
+ * issuing GET_INFO_QUEUE_DATA to fetch any remaining chunks until the queue
+ * signals no more data or a transport/bounds error is encountered.  On
+ * transport or bounds errors the function stops and returns whatever has
+ * been assembled so far.
+ *
+ * Returns: number of valid bytes written into @raw_buf.  Zero if @raw_buf is
+ *          NULL or @raw_buf_size is 0.
+ */
+u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
+				const struct xe_ras_get_counter_response *counter_resp,
+				u8 *raw_buf, u32 raw_buf_size)
+{
+	const struct xe_ras_info_queue_header *first_qhdr =
+		&counter_resp->info_queue.queue_header;
+	struct xe_ras_get_info_queue_data_request iq_req = {0};
+	struct xe_ras_get_info_queue_data_response iq_response = {0};
+	u32 iq_offset = 0;
+	u32 end;
+	bool complete = true;
+
+	if (!raw_buf || !raw_buf_size)
+		return 0;
+
+	/* Copy first chunk already embedded in the counter response */
+	if (first_qhdr->chunk_size &&
+	    first_qhdr->chunk_size <= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE &&
+	    !check_add_overflow(first_qhdr->chunk_offset, first_qhdr->chunk_size, &end) &&
+	    end <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE && end <= raw_buf_size) {
+		memcpy(raw_buf + first_qhdr->chunk_offset,
+		       counter_resp->info_queue.queue_data, first_qhdr->chunk_size);
+		iq_offset = first_qhdr->chunk_size;
+	}
+
+	/* Fetch any remaining chunks */
+	if (first_qhdr->flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) {
+		iq_req.source_command			= XE_SYSCTRL_CMD_GET_COUNTER;
+		iq_req.source_context			= counter_resp->counter;
+		iq_req.queue_request.requested_size	= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE;
+		iq_req.queue_request.session_id		= counter_resp->counter;
+
+		do {
+			struct xe_ras_info_queue_header *qhdr;
+			u32 end;
+
+			iq_req.queue_request.requested_offset = iq_offset;
+
+			if (get_info_queue_data(xe, &iq_req, &iq_response)) {
+				complete = false;
+				xe_err(xe,
+				       "[RAS]: info queue drain aborted: fetch at offset=%u failed\n",
+				       iq_offset);
+				break;
+			}
+
+			qhdr = &iq_response.queue_response.queue_header;
+
+			if (!qhdr->chunk_size) {
+				complete = false;
+				break;
+			}
+
+			if (qhdr->chunk_size > XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE) {
+				complete = false;
+				xe_warn(xe,
+					"[RAS]: CPER: invalid chunk size %u\n", qhdr->chunk_size);
+				break;
+			}
+
+			if (check_add_overflow(qhdr->chunk_offset, qhdr->chunk_size, &end) ||
+			    end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE || end > raw_buf_size) {
+				complete = false;
+				xe_warn(xe,
+					"[RAS]: info queue chunk out of bounds (offset=%u size=%u)\n",
+					qhdr->chunk_offset, qhdr->chunk_size);
+				break;
+			}
+
+			memcpy(raw_buf + qhdr->chunk_offset,
+			       iq_response.queue_response.queue_data,
+			       qhdr->chunk_size);
+
+			iq_offset += qhdr->chunk_size;
+		} while (iq_response.queue_response.queue_header.flags &
+			 XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);
+	}
+
+	if (!complete)
+		return iq_offset;
+
+	return first_qhdr->total_size
+	       ? min3(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, raw_buf_size)
+	       : iq_offset;
+}
+
 static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
 	struct xe_ras_get_health_response response = {0};
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
index e83e022cd363..d31e093c0fe9 100644
--- a/drivers/gpu/drm/xe/xe_ras.h
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -23,5 +23,8 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
 int xe_ras_get_counter_response(struct xe_device *xe, struct xe_ras_error_class *counter,
 				struct xe_ras_get_counter_response *out);
 bool xe_ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter);
+u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
+				const struct xe_ras_get_counter_response *counter_resp,
+				u8 *raw_buf, u32 raw_buf_size);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index fe6f3658a2a4..44fa5136cd81 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -16,6 +16,10 @@
 #define XE_RAS_MEMORY_DB_ECC			BIT(1)
 #define XE_RAS_MEMORY_POISON			BIT(2)
 #define XE_RAS_MEMORY_DATA_PARITY		BIT(5)
+#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE	200
+#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE	5120
+#define XE_RAS_INFO_QUEUE_FLAG_AVAILABLE	0x01
+#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA	0x02
 
 /**
  * enum xe_ras_recovery_action - RAS recovery actions
@@ -95,6 +99,109 @@ struct xe_ras_threshold_crossed {
 	struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
 } __packed;
 
+/**
+ * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
+ *
+ * Provides chunk metadata for commands that support extended info queue
+ * functionality. Used when the total data exceeds a single mailbox response.
+ */
+struct xe_ras_info_queue_header {
+	/** @total_size: Total size of the complete info queue data in bytes */
+	u32 total_size;
+	/** @chunk_offset: Offset of this chunk within the total data in bytes */
+	u32 chunk_offset;
+	/** @chunk_size: Size of the data in this chunk in bytes */
+	u32 chunk_size;
+	/** @sequence_number: Sequence number for this chunk, starts at 0 */
+	u32 sequence_number;
+	/** @flags: Info queue control flags (RAS_INFO_QUEUE_FLAG_*) */
+	u32 flags:8;
+	/** @compression_type: Compression algorithm used; 0 = none */
+	u32 compression_type:4;
+	/** @num_headers: Number of detailed counter headers at start of queue_data */
+	u32 num_headers:5;
+	/** @reserved: Reserved for future use */
+	u32 reserved:15;
+	/** @checksum: CRC32 checksum of this chunk data */
+	u32 checksum;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_request - Request for a specific chunk of info queue data
+ *
+ * Allows the driver to request continuation of large info queue transfers
+ * by specifying an offset and size within the full data set.
+ */
+struct xe_ras_info_queue_request {
+	/** @requested_offset: Byte offset of the requested data chunk */
+	u32 requested_offset;
+	/** @requested_size: Maximum size of the requested chunk in bytes */
+	u32 requested_size;
+	/** @session_id: Session ID to correlate multi-chunk transfers */
+	struct xe_ras_error_class session_id;
+	/** @reserved: Reserved for future use */
+	u32 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_response - Generic response for commands with info queues
+ *
+ * Standard response format for any command that returns an info queue
+ * payload. May be embedded in a command-specific response structure.
+ */
+struct xe_ras_info_queue_response {
+	/** @queue_header: Info queue metadata for this chunk */
+	struct xe_ras_info_queue_header queue_header;
+	/** @queue_data: Info queue data for this chunk */
+	u8 queue_data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];
+} __packed;
+
+/**
+ * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
+ *
+ * When a session requests aggregate counter data, one header per matching
+ * dynamic counter class is prepended to the queue data. The @counter field
+ * indicates how many subsequent error log entries belong to this class.
+ */
+struct xe_ras_info_queue_dynamic_counter_hdr {
+	/** @error_class: Error class associated with this counter group */
+	struct xe_ras_error_class error_class;
+	/** @counter: Number of error log entries that follow for this class */
+	u32 counter;
+} __packed;
+
+/**
+ * struct xe_ras_error_log - Single error log entry following dynamic counter headers
+ */
+struct xe_ras_error_log {
+	/** @timestamp: Timestamp when the error was recorded */
+	u64 timestamp;
+	/** @error_details: Error-specific details */
+	u32 error_details[16];
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_data_request - Request for RAS_CMD_GET_INFO_QUEUE_DATA
+ */
+struct xe_ras_get_info_queue_data_request {
+	/** @queue_request: Info queue request parameters */
+	struct xe_ras_info_queue_request queue_request;
+	/** @source_command: Original command that generated the info queue */
+	u32 source_command;
+	/** @source_context: Context from original command, if applicable */
+	struct xe_ras_error_class source_context;
+} __packed;
+
+/**
+ * struct xe_ras_get_info_queue_data_response - Response for RAS_CMD_GET_INFO_QUEUE_DATA
+ */
+struct xe_ras_get_info_queue_data_response {
+	/** @operation_status: Status of the retrieval operation */
+	u32 operation_status;
+	/** @queue_response: Info queue data chunk */
+	struct xe_ras_info_queue_response queue_response;
+} __packed;
+
 /**
  * struct xe_ras_get_counter_request - Request structure for get counter
  */
@@ -117,8 +224,14 @@ struct xe_ras_get_counter_response {
 	u64 timestamp;
 	/** @threshold: Threshold value for the counter */
 	u32 threshold;
-	/** @reserved: Reserved  */
-	u32 reserved[57];
+	/** @reserved: Reserved for future use */
+	u32 reserved:9;
+	/** @has_info_queue: Set if info queue is available */
+	u32 has_info_queue:1;
+	/** @reserved1: Reserved for future use */
+	u32 reserved1:22;
+	/** @info_queue: Initial info queue data (first chunk) if available */
+	struct xe_ras_info_queue_response info_queue;
 } __packed;
 
 /**
@@ -336,4 +449,5 @@ struct xe_ras_set_health_response {
 	/** @reserved1: Reserved for future use */
 	u32 reserved1[2];
 } __packed;
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
index 66e7cbcc3f91..c00fe0e69fda 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -30,6 +30,7 @@ enum xe_sysctrl_group {
  * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
  * @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
  * @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
+ * @XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA: Retrieve a chunk of info queue data
  */
 enum xe_sysctrl_gfsp_cmd {
 	XE_SYSCTRL_CMD_GET_SOC_ERROR		= 0x01,
@@ -40,6 +41,7 @@ enum xe_sysctrl_gfsp_cmd {
 	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
 	XE_SYSCTRL_CMD_GET_HEALTH		= 0x0B,
 	XE_SYSCTRL_CMD_SET_HEALTH		= 0x0C,
+	XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA	= 0x0D,
 };
 
 /**
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI
  2026-09-06 17:26 ` [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI Badal Nilawar
@ 2026-09-06 17:17   ` sashiko-bot
  2026-09-09  8:03   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:17 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Inconsistent handling of queue offsets and blindly trusting the hardware's total_size leads to sparse buffer writes and returning an inflated valid byte count.
- [High] Missing contiguous progress validation allows a misbehaving or compromised firmware to cause an infinite loop in the kernel.
- [Medium] get_info_queue_data ignores the hardware operation_status, returning success on logical command failures.
--

commit beae2ef0daf0b18e6a50c5076d39abd256ed8593
Author: Badal Nilawar <badal.nilawar@intel.com>
Subject: drm/xe/xe_ras: Add support to retrieve info queue data for CRI

Retrieve the RAS info queue data, in multiple chunks, and assemble
it into flat raw buffer. Follow up patch will use this data to
prepare cper error info.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 0fb9065cdd76f..7e3e627504485 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
[ ... ]
> +static int get_info_queue_data(struct xe_device *xe,
> +			       const struct xe_ras_get_info_queue_data_request *req,
> +			       struct xe_ras_get_info_queue_data_response *out)
> +{
[ ... ]
> +	if (rlen != sizeof(response)) {
> +		xe_err(xe, "sysctrl: unexpected get info queue data response length %zu (expected %zu)\n",
> +		       rlen, sizeof(response));
> +		return -EIO;
> +	}
> +
> +	xe_dbg(xe, "[RAS]: info queue data: status=%u chunk_size=%u flags=0x%x\n",
> +	       response.operation_status,
> +	       response.queue_response.queue_header.chunk_size,
> +	       response.queue_response.queue_header.flags);
> +
> +	*out = response;
> +	return 0;
> +}

[Severity: Medium]
Does get_info_queue_data() ignore the hardware operation_status? It looks like
it returns success on logical command failures. If the GET_INFO_QUEUE_DATA
command fails at the firmware level, returning an error code in
response.operation_status, the function only checks the transport status and
returns 0. Can this cause the driver to process an empty or garbage
queue_response payload as valid data?

[ ... ]
> +u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
> +				const struct xe_ras_get_counter_response *counter_resp,
> +				u8 *raw_buf, u32 raw_buf_size)
> +{
[ ... ]
> +	if (!raw_buf || !raw_buf_size)
> +		return 0;
> +
> +	/* Copy first chunk already embedded in the counter response */
> +	if (first_qhdr->chunk_size &&
> +	    first_qhdr->chunk_size <= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE &&
> +	    !check_add_overflow(first_qhdr->chunk_offset, first_qhdr->chunk_size, &end) &&
> +	    end <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE && end <= raw_buf_size) {
> +		memcpy(raw_buf + first_qhdr->chunk_offset,
> +		       counter_resp->info_queue.queue_data, first_qhdr->chunk_size);
> +		iq_offset = first_qhdr->chunk_size;
> +	}

[Severity: High]
Does the initialization of iq_offset incorrectly assume that the first chunk's
offset is exactly 0? Also, if the bounds check fails, the copy is skipped but
the complete variable is left as true. Could this result in miscalculating
iq_offset (e.g., iq_offset = chunk_size instead of chunk_offset + chunk_size)
and returning an inflated valid byte count?

> +
> +	/* Fetch any remaining chunks */
> +	if (first_qhdr->flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) {
[ ... ]
> +			if (check_add_overflow(qhdr->chunk_offset, qhdr->chunk_size, &end) ||
> +			    end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE || end > raw_buf_size) {
> +				complete = false;
> +				xe_warn(xe,
> +					"[RAS]: info queue chunk out of bounds (offset=%u size=%u)\n",
> +					qhdr->chunk_offset, qhdr->chunk_size);
> +				break;
> +			}

[Severity: High]
The bounds check uses qhdr->chunk_offset but lacks a check like
qhdr->chunk_offset == iq_offset to guarantee monotonic forward progress.
Could this missing contiguous progress validation allow a misbehaving or
compromised firmware to cause an infinite loop in the kernel? Firmware could
repeatedly return a valid small chunk (e.g., chunk_offset = 0, chunk_size = 1)
with the MORE_DATA flag set. The bounds check would pass every time, and
iq_offset would grow indefinitely without terminating the loop.

> +
> +			memcpy(raw_buf + qhdr->chunk_offset,
> +			       iq_response.queue_response.queue_data,
> +			       qhdr->chunk_size);
> +
> +			iq_offset += qhdr->chunk_size;

[Severity: High]
Does this missing contiguous offset validation (e.g.
qhdr->chunk_offset == iq_offset) allow uninitialized gaps in the destination
buffer, and blindly advance the requested offset? This could lead to the caller
parsing zeroed or uninitialized memory as valid CPER error logs, resulting
in corrupted error reports if firmware returns chunks with gaps.

> +		} while (iq_response.queue_response.queue_header.flags &
> +			 XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);

[Severity: High]
Does the loop rely entirely on the untrusted hardware clearing the MORE_DATA
flag to terminate, without any software fallback limiting total iterations or
checking accumulated size?

> +	}
> +
> +	if (!complete)
> +		return iq_offset;
> +
> +	return first_qhdr->total_size
> +	       ? min3(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, raw_buf_size)
> +	       : iq_offset;
> +}

[Severity: High]
Is it safe to return an unverified hardware-provided total_size instead of the
dynamically accumulated written byte count? If firmware returns
MORE_DATA == 0 early or returns chunks with gaps, this exposes uninitialized
memory at the tail of the buffer.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=5

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI
  2026-09-06 17:26 ` [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI Badal Nilawar
  2026-09-06 17:17   ` sashiko-bot
@ 2026-09-09  8:03   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: Raag Jadav @ 2026-09-09  8:03 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:10PM +0530, Badal Nilawar wrote:
> Retrieve the RAS info queue data, in multiple chunks, and assemble
> it into flat raw buffer. Follow up patch will use this data to
> prepare cper error info.

A mailbox abstracted as a sysctrl protocol, which again abstracted as info
queue chunks at ras level while also introducing special headers for the
type of counter, all of which is then duplicated as part of both GET_COUNTER
and GET_INFO_QUEUE responses to copy and emit a simple buffer.

The whole RAS FW was sold as a solution to make things "simpler", but this
is creeping into the over engineering territory IMNSHO.

> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Assisted-by: Copilot:claude-opus-4.8
> ---
>  drivers/gpu/drm/xe/xe_ras.c                   | 139 ++++++++++++++++++
>  drivers/gpu/drm/xe/xe_ras.h                   |   3 +
>  drivers/gpu/drm/xe/xe_ras_types.h             | 118 ++++++++++++++-
>  drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |   2 +
>  4 files changed, 260 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 0fb9065cdd76..7e3e62750448 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -797,6 +797,145 @@ int xe_ras_set_threshold(struct xe_device *xe, u8 severity, u8 component, u32 th
>  	return 0;
>  }
>  
> +static int get_info_queue_data(struct xe_device *xe,
> +			       const struct xe_ras_get_info_queue_data_request *req,

Not much point of const if we're also going to cast it away.

> +			       struct xe_ras_get_info_queue_data_response *out)
> +{
> +	struct xe_ras_get_info_queue_data_response response = {0};
> +	struct xe_sysctrl_mailbox_command command = {0};
> +	size_t rlen;
> +	int ret;
> +
> +	xe_sysctrl_create_command(&command, XE_SYSCTRL_GROUP_GFSP,
> +				  XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA,
> +				  (void *)req, sizeof(*req), &response, sizeof(response));
> +
> +	ret = xe_sysctrl_send_command(&xe->sc, &command, &rlen);
> +	if (ret) {
> +		xe_err(xe, "sysctrl: failed to get info queue data %d\n", ret);
> +		return ret;
> +	}
> +
> +	if (rlen != sizeof(response)) {
> +		xe_err(xe, "sysctrl: unexpected get info queue data response length %zu (expected %zu)\n",
> +		       rlen, sizeof(response));
> +		return -EIO;
> +	}
> +
> +	xe_dbg(xe, "[RAS]: info queue data: status=%u chunk_size=%u flags=0x%x\n",
> +	       response.operation_status,
> +	       response.queue_response.queue_header.chunk_size,
> +	       response.queue_response.queue_header.flags);

This would be a bit more readable with local variables, please use them.

> +
> +	*out = response;
> +	return 0;
> +}
> +
> +/**
> + * xe_ras_drain_info_queue_raw - Drain the full RAS info queue into a flat buffer.
> + * @xe: xe device
> + * @counter_resp: counter response carrying the first embedded chunk and the
> + *                counter identifier used as the source context for subsequent
> + *                GET_INFO_QUEUE_DATA fetches
> + * @raw_buf: destination buffer supplied by the caller

So perhaps 'dest_buf'?

> + * @raw_buf_size: size of @raw_buf in bytes; also caps the total amount of data
> + *                assembled from the info queue

Ditto for 'dest_size'.

> + * Copies the first chunk already embedded in @counter_resp, then loops
> + * issuing GET_INFO_QUEUE_DATA to fetch any remaining chunks until the queue
> + * signals no more data or a transport/bounds error is encountered.  On
> + * transport or bounds errors the function stops and returns whatever has
> + * been assembled so far.
> + *
> + * Returns: number of valid bytes written into @raw_buf.  Zero if @raw_buf is
> + *          NULL or @raw_buf_size is 0.
> + */
> +u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
> +				const struct xe_ras_get_counter_response *counter_resp,
> +				u8 *raw_buf, u32 raw_buf_size)
> +{
> +	const struct xe_ras_info_queue_header *first_qhdr =
> +		&counter_resp->info_queue.queue_header;
> +	struct xe_ras_get_info_queue_data_request iq_req = {0};
> +	struct xe_ras_get_info_queue_data_response iq_response = {0};
> +	u32 iq_offset = 0;
> +	u32 end;
> +	bool complete = true;
> +
> +	if (!raw_buf || !raw_buf_size)
> +		return 0;
> +
> +	/* Copy first chunk already embedded in the counter response */
> +	if (first_qhdr->chunk_size &&
> +	    first_qhdr->chunk_size <= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE &&
> +	    !check_add_overflow(first_qhdr->chunk_offset, first_qhdr->chunk_size, &end) &&
> +	    end <= XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE && end <= raw_buf_size) {

This entire condition can be something like chunk_is_valid().

> +		memcpy(raw_buf + first_qhdr->chunk_offset,
> +		       counter_resp->info_queue.queue_data, first_qhdr->chunk_size);
> +		iq_offset = first_qhdr->chunk_size;
> +	}
> +
> +	/* Fetch any remaining chunks */
> +	if (first_qhdr->flags & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA) {

IIUC this entire block can be

	while (flag & XE_RAS_INFO_QUEUE_FLAG_MORE_DATA)
	{
		...
	}
	
with flag as a local variable with initial value from first_qhdr and
updated on each iteration.

> +		iq_req.source_command			= XE_SYSCTRL_CMD_GET_COUNTER;
> +		iq_req.source_context			= counter_resp->counter;
> +		iq_req.queue_request.requested_size	= XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE;
> +		iq_req.queue_request.session_id		= counter_resp->counter;
> +
> +		do {
> +			struct xe_ras_info_queue_header *qhdr;
> +			u32 end;
> +
> +			iq_req.queue_request.requested_offset = iq_offset;
> +
> +			if (get_info_queue_data(xe, &iq_req, &iq_response)) {
> +				complete = false;
> +				xe_err(xe,
> +				       "[RAS]: info queue drain aborted: fetch at offset=%u failed\n",
> +				       iq_offset);
> +				break;
> +			}
> +
> +			qhdr = &iq_response.queue_response.queue_header;
> +
> +			if (!qhdr->chunk_size) {
> +				complete = false;
> +				break;
> +			}
> +
> +			if (qhdr->chunk_size > XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE) {
> +				complete = false;
> +				xe_warn(xe,
> +					"[RAS]: CPER: invalid chunk size %u\n", qhdr->chunk_size);
> +				break;
> +			}
> +
> +			if (check_add_overflow(qhdr->chunk_offset, qhdr->chunk_size, &end) ||
> +			    end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE || end > raw_buf_size) {
> + *

Hm, an opportunity to reuse chunk_is_valid() here.

> +				complete = false;
> +				xe_warn(xe,
> +					"[RAS]: info queue chunk out of bounds (offset=%u size=%u)\n",
> +					qhdr->chunk_offset, qhdr->chunk_size);
> +				break;
> +			}
> +
> +			memcpy(raw_buf + qhdr->chunk_offset,
> +			       iq_response.queue_response.queue_data,
> +			       qhdr->chunk_size);
> +
> +			iq_offset += qhdr->chunk_size;
> +		} while (iq_response.queue_response.queue_header.flags &
> +			 XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);
> +	}
> +
> +	if (!complete)
> +		return iq_offset;
> +
> +	return first_qhdr->total_size
> +	       ? min3(first_qhdr->total_size, XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, raw_buf_size)
> +	       : iq_offset;

Same as above, this can be something like min_info_queue_size().

> +}
> +
>  static ssize_t gpu_health_show(struct device *dev, struct device_attribute *attr, char *buf)
>  {
>  	struct xe_ras_get_health_response response = {0};
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index e83e022cd363..d31e093c0fe9 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -23,5 +23,8 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe);
>  int xe_ras_get_counter_response(struct xe_device *xe, struct xe_ras_error_class *counter,
>  				struct xe_ras_get_counter_response *out);
>  bool xe_ras_counter_is_valid(struct xe_device *xe, struct xe_ras_error_class *counter);
> +u32 xe_ras_drain_info_queue_raw(struct xe_device *xe,
> +				const struct xe_ras_get_counter_response *counter_resp,
> +				u8 *raw_buf, u32 raw_buf_size);
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index fe6f3658a2a4..44fa5136cd81 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -16,6 +16,10 @@
>  #define XE_RAS_MEMORY_DB_ECC			BIT(1)
>  #define XE_RAS_MEMORY_POISON			BIT(2)
>  #define XE_RAS_MEMORY_DATA_PARITY		BIT(5)

These are unrelated to existing defs, please leave a blank line here.

> +#define XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE	200
> +#define XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE	5120
> +#define XE_RAS_INFO_QUEUE_FLAG_AVAILABLE	0x01

Any user?

> +#define XE_RAS_INFO_QUEUE_FLAG_MORE_DATA	0x02
>  
>  /**
>   * enum xe_ras_recovery_action - RAS recovery actions
> @@ -95,6 +99,109 @@ struct xe_ras_threshold_crossed {
>  	struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
>  } __packed;
>  
> +/**
> + * struct xe_ras_info_queue_header - Metadata for large info queue data transfers
> + *
> + * Provides chunk metadata for commands that support extended info queue
> + * functionality. Used when the total data exceeds a single mailbox response.
> + */
> +struct xe_ras_info_queue_header {
> +	/** @total_size: Total size of the complete info queue data in bytes */
> +	u32 total_size;
> +	/** @chunk_offset: Offset of this chunk within the total data in bytes */
> +	u32 chunk_offset;
> +	/** @chunk_size: Size of the data in this chunk in bytes */
> +	u32 chunk_size;
> +	/** @sequence_number: Sequence number for this chunk, starts at 0 */
> +	u32 sequence_number;

Unless it's used here, please mark it as reserved.

> +	/** @flags: Info queue control flags (RAS_INFO_QUEUE_FLAG_*) */
> +	u32 flags:8;
> +	/** @compression_type: Compression algorithm used; 0 = none */
> +	u32 compression_type:4;

Ditto.

> +	/** @num_headers: Number of detailed counter headers at start of queue_data */
> +	u32 num_headers:5;
> +	/** @reserved: Reserved for future use */
> +	u32 reserved:15;
> +	/** @checksum: CRC32 checksum of this chunk data */
> +	u32 checksum;
> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_request - Request for a specific chunk of info queue data

As per description this should be 'xe_ras_info_queue_data_request'.

> + *
> + * Allows the driver to request continuation of large info queue transfers
> + * by specifying an offset and size within the full data set.
> + */
> +struct xe_ras_info_queue_request {
> +	/** @requested_offset: Byte offset of the requested data chunk */
> +	u32 requested_offset;

I know this is from spec but it's full of needless verbiage. Since
this is already part of _request struct, it can simple but 'offset'.

> +	/** @requested_size: Maximum size of the requested chunk in bytes */
> +	u32 requested_size;

Ditto for 'size'.

> +	/** @session_id: Session ID to correlate multi-chunk transfers */
> +	struct xe_ras_error_class session_id;
> +	/** @reserved: Reserved for future use */
> +	u32 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_response - Generic response for commands with info queues

Same as above, 'xe_ras_info_queue_data_response'.

> + *
> + * Standard response format for any command that returns an info queue
> + * payload. May be embedded in a command-specific response structure.
> + */
> +struct xe_ras_info_queue_response {
> +	/** @queue_header: Info queue metadata for this chunk */
> +	struct xe_ras_info_queue_header queue_header;

Can be just 'header'.

> +	/** @queue_data: Info queue data for this chunk */
> +	u8 queue_data[XE_RAS_INFO_QUEUE_MAX_CHUNK_SIZE];

Ditto for 'data'.

> +} __packed;
> +
> +/**
> + * struct xe_ras_info_queue_dynamic_counter_hdr - Aggregate counter header entry
> + *
> + * When a session requests aggregate counter data, one header per matching
> + * dynamic counter class is prepended to the queue data. The @counter field
> + * indicates how many subsequent error log entries belong to this class.
> + */
> +struct xe_ras_info_queue_dynamic_counter_hdr {
> +	/** @error_class: Error class associated with this counter group */
> +	struct xe_ras_error_class error_class;
> +	/** @counter: Number of error log entries that follow for this class */
> +	u32 counter;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_log - Single error log entry following dynamic counter headers
> + */
> +struct xe_ras_error_log {
> +	/** @timestamp: Timestamp when the error was recorded */
> +	u64 timestamp;
> +	/** @error_details: Error-specific details */
> +	u32 error_details[16];
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_info_queue_data_request - Request for RAS_CMD_GET_INFO_QUEUE_DATA
> + */
> +struct xe_ras_get_info_queue_data_request {
> +	/** @queue_request: Info queue request parameters */
> +	struct xe_ras_info_queue_request queue_request;
> +	/** @source_command: Original command that generated the info queue */
> +	u32 source_command;
> +	/** @source_context: Context from original command, if applicable */
> +	struct xe_ras_error_class source_context;
> +} __packed;
> +
> +/**
> + * struct xe_ras_get_info_queue_data_response - Response for RAS_CMD_GET_INFO_QUEUE_DATA

So redundant 'data'? See below.

> + */
> +struct xe_ras_get_info_queue_data_response {
> +	/** @operation_status: Status of the retrieval operation */
> +	u32 operation_status;
> +	/** @queue_response: Info queue data chunk */
> +	struct xe_ras_info_queue_response queue_response;

Since the data[] is abstracted here, 'xe_ras_get_info_queue_data_response'
is more suitable for this.

> +} __packed;
> +
>  /**
>   * struct xe_ras_get_counter_request - Request structure for get counter
>   */
> @@ -117,8 +224,14 @@ struct xe_ras_get_counter_response {
>  	u64 timestamp;
>  	/** @threshold: Threshold value for the counter */
>  	u32 threshold;
> -	/** @reserved: Reserved  */
> -	u32 reserved[57];
> +	/** @reserved: Reserved for future use */
> +	u32 reserved:9;
> +	/** @has_info_queue: Set if info queue is available */
> +	u32 has_info_queue:1;
> +	/** @reserved1: Reserved for future use */
> +	u32 reserved1:22;
> +	/** @info_queue: Initial info queue data (first chunk) if available */
> +	struct xe_ras_info_queue_response info_queue;

So 'first'?

>  } __packed;
>  
>  /**
> @@ -336,4 +449,5 @@ struct xe_ras_set_health_response {
>  	/** @reserved1: Reserved for future use */
>  	u32 reserved1[2];
>  } __packed;
> +
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> index 66e7cbcc3f91..c00fe0e69fda 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
> @@ -30,6 +30,7 @@ enum xe_sysctrl_group {
>   * @XE_SYSCTRL_CMD_GET_PENDING_EVENT: Retrieve pending event
>   * @XE_SYSCTRL_CMD_GET_HEALTH: Retrieve gpu health
>   * @XE_SYSCTRL_CMD_SET_HEALTH: Set gpu health
> + * @XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA: Retrieve a chunk of info queue data
>   */
>  enum xe_sysctrl_gfsp_cmd {
>  	XE_SYSCTRL_CMD_GET_SOC_ERROR		= 0x01,
> @@ -40,6 +41,7 @@ enum xe_sysctrl_gfsp_cmd {
>  	XE_SYSCTRL_CMD_GET_PENDING_EVENT	= 0x07,
>  	XE_SYSCTRL_CMD_GET_HEALTH		= 0x0B,
>  	XE_SYSCTRL_CMD_SET_HEALTH		= 0x0C,
> +	XE_SYSCTRL_CMD_GET_INFO_QUEUE_DATA	= 0x0D,

Redundant 'DATA'.

Raag

>  };
>  
>  /**
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (6 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:30   ` sashiko-bot
  2026-09-09 11:58   ` Raag Jadav
  2026-09-06 17:26 ` [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival Badal Nilawar
                   ` (7 subsequent siblings)
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Prepare xe_cper_sec_intel_error_info records from RAS
info queue data. Depending on the error class type,
detail or aggregate, one or more error info records
may be generated and embedded in the CPER record.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-opus-4.8
---
v2:
  - Fix sashiko warnings
---
 drivers/gpu/drm/xe/xe_cper.c | 272 +++++++++++++++++++++++++++++++++--
 1 file changed, 263 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index 31ca53ce1aa7..ebf4dc4ab2bb 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -173,6 +173,233 @@ static void xe_cper_record_emit(struct xe_device *xe, u8 severity,
 
 	kfree(rec);
 }
+
+/**
+ * struct xe_cper_einfo_entry - One CPER error-info buffer with its byte size
+ * @hdr: dynamic-counter header carrying the per-entry error_class and counter
+ *       value; used by the caller to build a dedicated xe_cper_sec_intel_err_hdr
+ *       for each CPER record
+ * @einfo: allocated error-info payload (caller must kfree)
+ * @einfo_size: byte size of @einfo including any event_queue data
+ * @timestamp: timestamp of first occurrence of dynamic-counter
+ */
+struct xe_cper_einfo_entry {
+	struct xe_ras_info_queue_dynamic_counter_hdr hdr;
+	struct xe_cper_sec_intel_error_info *einfo;
+	u32 einfo_size;
+	u64 timestamp;
+};
+
+static void fill_einfo_error_class(struct xe_cper_sec_intel_error_info *einfo,
+				   const struct xe_ras_error_class *ec)
+{
+	einfo->error_class.error_type      = ec->common.severity;
+	einfo->error_class.error_component = ec->common.component;
+	einfo->error_class.tile            = ec->product.unit.tile;
+	einfo->error_class.instance        = ec->product.unit.instance;
+	einfo->error_class.cause           = ec->product.cause.cause;
+}
+
+static struct xe_cper_sec_intel_error_info *
+build_einfo(const struct xe_ras_error_log *logs, u32 num_logs,
+	    const struct xe_ras_error_class *ec, u32 error_count,
+	    u32 *size_out, u64 *ts_out)
+{
+	/*
+	 * Although xe_intel_priv_event_entry has a flexible metadata[] array,
+	 * every entry we emit carries the fixed-length error_details payload
+	 * from xe_ras_error_log, so the per-entry stride is constant here.
+	 */
+	u32 entry_size = offsetof(struct xe_intel_priv_event_entry, metadata) +
+			 sizeof_field(struct xe_ras_error_log, error_details);
+	struct xe_cper_sec_intel_error_info *einfo;
+	struct xe_intel_priv_event_entry *entry;
+	u32 einfo_size = sizeof(*einfo) + num_logs * entry_size;
+	u32 i;
+
+	einfo = kzalloc(einfo_size, GFP_KERNEL);
+	if (!einfo)
+		return NULL;
+
+	einfo->error_count        = error_count;
+	einfo->event_queue_length = num_logs * entry_size;
+	einfo->event_queue_count  = num_logs;
+	fill_einfo_error_class(einfo, ec);
+
+	entry = (struct xe_intel_priv_event_entry *)einfo->event_queue;
+	for (i = 0; i < num_logs; i++) {
+		entry->entry_length = sizeof_field(struct xe_ras_error_log, error_details);
+		entry->timestamp    = logs[i].timestamp;
+		memcpy(entry->metadata, logs[i].error_details, sizeof(logs[i].error_details));
+		entry = (struct xe_intel_priv_event_entry *)((u8 *)entry + entry_size);
+	}
+
+	*size_out = einfo_size;
+	*ts_out   = logs[0].timestamp;
+	return einfo;
+}
+
+static void free_einfo_arr(struct xe_cper_einfo_entry *einfo_arr, u32 count)
+{
+	u32 i;
+
+	if (!einfo_arr)
+		return;
+
+	for (i = 0; i < count; i++)
+		kfree(einfo_arr[i].einfo);
+	kfree(einfo_arr);
+}
+
+/**
+ * xe_prepare_cper_error_info - Build the CPER error info records from RAS info queue data
+ * @xe: xe device instance
+ * @counter_resp: counter response containing the first embedded chunk
+ * @error_class: RAS error class used to populate the einfo error_class fields
+ * @einfo_size_out: output size of the allocated einfo buffer
+ *
+ * Assembles the complete raw info queue data from the first chunk already
+ * embedded in @counter_resp and any additional chunks fetched via
+ * GET_INFO_QUEUE_DATA.  Two use cases are supported based on num_headers in
+ * the info queue header:
+ *
+ * Detail error counter (num_headers == 0)::
+ *
+ *   [xe_ras_error_log * N]
+ *
+ *   Returns one xe_cper_einfo_entry covering all N logs.
+ *
+ * Aggregate error counter (num_headers > 0)::
+ *
+ *   [xe_ras_info_queue_dynamic_counter_hdr * num_headers]
+ *   [xe_ras_error_log * N]
+ *
+ *   Returns one xe_cper_einfo_entry per header.  Each header's @counter field
+ *   gives the number of consecutive xe_ras_error_log entries belonging to it
+ *   and its @error_class is used to populate the entry's einfo->error_class.
+ *
+ * Returns: allocated xe_cper_einfo_entry array on success (caller must kfree
+ *          each entry's einfo then kfree the array), NULL on failure.
+ *          @count_out is set to the number of entries in the array.
+ */
+static struct xe_cper_einfo_entry *
+xe_prepare_cper_error_info(struct xe_device *xe,
+			   const struct xe_ras_get_counter_response *counter_resp,
+			   const struct xe_ras_error_class *error_class,
+			   u32 *count_out)
+{
+	const struct xe_ras_info_queue_header *first_qhdr =
+		&counter_resp->info_queue.queue_header;
+	struct xe_cper_einfo_entry *einfo_arr;
+	u32 num_headers, headers_size;
+	u32 raw_total;
+	u8 *raw_buf;
+	u32 i;
+
+	raw_buf = kzalloc(XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, GFP_KERNEL);
+	if (!raw_buf)
+		return NULL;
+
+	raw_total = xe_ras_drain_info_queue_raw(xe, counter_resp, raw_buf,
+						XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
+	if (!raw_total) {
+		kfree(raw_buf);
+		return NULL;
+	}
+
+	num_headers  = first_qhdr->num_headers;
+	headers_size = num_headers * sizeof(struct xe_ras_info_queue_dynamic_counter_hdr);
+
+	if (headers_size > raw_total) {
+		xe_warn(xe, "[RAS]: CPER: aggregate headers size (%u) exceeds raw total (%u)\n",
+			headers_size, raw_total);
+		kfree(raw_buf);
+		return NULL;
+	}
+
+	if (num_headers == 0) {
+		/* Detailed counter case: single einfo covering all log entries */
+		u32 num_logs = raw_total / sizeof(struct xe_ras_error_log);
+		const struct xe_ras_error_log *logs =
+			(const struct xe_ras_error_log *)raw_buf;
+		struct xe_cper_sec_intel_error_info *einfo;
+
+		if (!num_logs) {
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		einfo_arr = kzalloc_objs(*einfo_arr, 1, GFP_KERNEL);
+		if (!einfo_arr) {
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		einfo = build_einfo(logs, num_logs, error_class, counter_resp->value,
+				    &einfo_arr[0].einfo_size, &einfo_arr[0].timestamp);
+		if (!einfo) {
+			kfree(einfo_arr);
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		einfo_arr[0].hdr.error_class = *error_class;
+		einfo_arr[0].hdr.counter     = counter_resp->value;
+		einfo_arr[0].einfo           = einfo;
+		*count_out = 1;
+
+	} else {
+		/* Aggregate conter case: one einfo per dynamic-counter header */
+		const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs =
+			(const struct xe_ras_info_queue_dynamic_counter_hdr *)raw_buf;
+		const struct xe_ras_error_log *all_logs =
+			(const struct xe_ras_error_log *)(raw_buf + headers_size);
+		u32 avail_logs = (raw_total - headers_size) / sizeof(struct xe_ras_error_log);
+		u32 log_offset = 0;
+		u32 einfo_count = 0;
+
+		einfo_arr = kzalloc_objs(*einfo_arr, num_headers, GFP_KERNEL);
+		if (!einfo_arr) {
+			kfree(raw_buf);
+			return NULL;
+		}
+
+		for (i = 0; i < num_headers; i++) {
+			u32 num_logs = min_t(u32, hdrs[i].counter, XE_RAS_NUM_COUNTERS);
+			struct xe_cper_sec_intel_error_info *einfo;
+
+			if (log_offset + num_logs > avail_logs) {
+				xe_warn(xe, "[RAS]: CPER: header[%u] claims %u logs but only %u remain\n",
+					i, num_logs, avail_logs - log_offset);
+				break;
+			}
+
+			if (!num_logs)
+				continue;
+
+			einfo = build_einfo(&all_logs[log_offset], num_logs,
+					    &hdrs[i].error_class, num_logs,
+					    &einfo_arr[einfo_count].einfo_size,
+					    &einfo_arr[einfo_count].timestamp);
+			if (!einfo) {
+				free_einfo_arr(einfo_arr, einfo_count);
+				kfree(raw_buf);
+				return NULL;
+			}
+
+			einfo_arr[einfo_count].hdr   = hdrs[i];
+			einfo_arr[einfo_count].einfo = einfo;
+			log_offset += num_logs;
+			einfo_count++;
+		}
+
+		*count_out = einfo_count;
+	}
+
+	kfree(raw_buf);
+	return einfo_arr;
+}
+
 /**
  * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
  * @pdev: PCI device associated with the Xe device
@@ -191,6 +418,9 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
 	struct xe_ras_get_counter_response local_resp = {};
 	struct xe_ras_get_counter_response *counter_response = response;
 	struct xe_cper_sec_intel_err_hdr ihdr = {};
+	struct xe_cper_einfo_entry *einfo_arr = NULL;
+	u32 einfo_count = 0;
+	u32 i;
 
 	if (!xe)
 		return;
@@ -209,15 +439,39 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
 		}
 	}
 
-	xe_cper_init_intel_err_hdr(xe,
-				   (const u8 *)counter,
-				   counter_response->timestamp,
-				   sigid,
-				   counter_response->value,
-				   &ihdr);
+	if (counter_response->has_info_queue) {
+		einfo_arr = xe_prepare_cper_error_info(xe, counter_response, counter, &einfo_count);
+		if (!einfo_arr)
+			xe_err(xe, "[RAS]: CPER: failed to build einfo from info queue\n");
+	}
+
+	if (einfo_count > 0) {
+		for (i = 0; i < einfo_count; i++) {
+			struct xe_cper_sec_intel_err_hdr entry_ihdr = {};
 
-	xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
-			    &ihdr, NULL, 0);
+			xe_cper_init_intel_err_hdr(xe,
+						   (const u8 *)&einfo_arr[i].hdr.error_class,
+						   einfo_arr[i].timestamp,
+						   sigid, einfo_arr[i].hdr.counter,
+						   &entry_ihdr);
+
+			xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
+					    &entry_ihdr, einfo_arr[i].einfo,
+					    einfo_arr[i].einfo_size);
+		}
+	} else {
+		xe_cper_init_intel_err_hdr(xe,
+					   (const u8 *)counter,
+					   counter_response->timestamp,
+					   sigid, counter_response->value, &ihdr);
+
+		xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
+				    &ihdr, NULL, 0);
+	}
+
+	if (einfo_arr) {
+		free_einfo_arr(einfo_arr, einfo_count);
+		einfo_arr = NULL;
+	}
 
-	/* TODO */
 }
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records
  2026-09-06 17:26 ` [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records Badal Nilawar
@ 2026-09-06 17:30   ` sashiko-bot
  2026-09-09 11:58   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:30 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [High] Incorrect parsing of aggregate info queue logs causes offset corruption and truncated error counts.

Pre-existing issues:
- [High] Inverted hardware SIGID check causes the hardware error handler to unconditionally abort.
- [High] Unbounded loop in `xe_ras_drain_info_queue_raw` leading to Denial of Service.
--

commit 08c625ea20b49a15a86e85dcc258d1ff791d3145
Author: Badal Nilawar <badal.nilawar@intel.com>
drm/xe/cper: Prepare Intel CPER error info records

This patch prepares xe_cper_sec_intel_error_info records from RAS info
queue data. Depending on the error class type, one or more error info
records are generated and embedded in the CPER record.

> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
[ ... ]
> +static struct xe_cper_einfo_entry *
> +xe_prepare_cper_error_info(struct xe_device *xe,
> +			   const struct xe_ras_get_counter_response *counter_resp,
> +			   const struct xe_ras_error_class *error_class,
> +			   u32 *count_out)
> +{
[ ... ]
> +	raw_buf = kzalloc(XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, GFP_KERNEL);
> +	if (!raw_buf)
> +		return NULL;
> +
> +	raw_total = xe_ras_drain_info_queue_raw(xe, counter_resp, raw_buf,
> +						XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);

[Severity: High]
This is a pre-existing issue, but since this patch adds a call to it here,
can xe_ras_drain_info_queue_raw() cause a denial of service if the
hardware misbehaves?

Looking at xe_ras_drain_info_queue_raw() in drivers/gpu/drm/xe/xe_ras.c,
the loop bounds check evaluates the received chunk offset:

    if (check_add_overflow(qhdr->chunk_offset, qhdr->chunk_size, &end) ||
        end > XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE || end > raw_buf_size) {

However, the loop termination relies entirely on the MORE_DATA flag:

    } while (iq_response.queue_response.queue_header.flags &
             XE_RAS_INFO_QUEUE_FLAG_MORE_DATA);

It never checks if the accumulated iq_offset exceeds the total maximum
limit across iterations. Could a malfunctioning or malicious firmware
hang the kernel by continuously returning valid small chunks with the
MORE_DATA flag set?

[ ... ]
> +		for (i = 0; i < num_headers; i++) {
> +			u32 num_logs = min_t(u32, hdrs[i].counter, XE_RAS_NUM_COUNTERS);
> +			struct xe_cper_sec_intel_error_info *einfo;
> +
> +			if (log_offset + num_logs > avail_logs) {
> +				xe_warn(xe, "[RAS]: CPER: header[%u] claims %u logs but only %u remain\n",
> +					i, num_logs, avail_logs - log_offset);
> +				break;
> +			}
> +
> +			if (!num_logs)
> +				continue;
> +
> +			einfo = build_einfo(&all_logs[log_offset], num_logs,
> +					    &hdrs[i].error_class, num_logs,
> +					    &einfo_arr[einfo_count].einfo_size,
> +					    &einfo_arr[einfo_count].timestamp);

[Severity: High]
Does clamping num_logs to XE_RAS_NUM_COUNTERS here cause parsing
desynchronization?

If the hardware returns an aggregate info queue where hdrs[i].counter is
greater than XE_RAS_NUM_COUNTERS, num_logs is clamped. But this clamped
value is also passed to build_einfo() as the error_count, leading to
truncated error counts.

> +			if (!einfo) {
> +				free_einfo_arr(einfo_arr, einfo_count);
> +				kfree(raw_buf);
> +				return NULL;
> +			}
> +
> +			einfo_arr[einfo_count].hdr   = hdrs[i];
> +			einfo_arr[einfo_count].einfo = einfo;
> +			log_offset += num_logs;

[Severity: High]
Additionally, does incrementing log_offset by the clamped amount rather
than the claimed amount cause subsequent headers to read the wrong log
data? It seems like it would leave unconsumed logs in the stream,
corrupting the offset for the next iteration.

[ ... ]
>  void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
>  				 struct xe_ras_error_class *counter,
>  				 struct xe_ras_get_counter_response *response)
>  {
>  	struct xe_device *xe = pdev_to_xe_device(pdev);
>  	struct xe_ras_get_counter_response local_resp = {};
>  	struct xe_ras_get_counter_response *counter_response = response;
>  	struct xe_cper_sec_intel_err_hdr ihdr = {};
> +	struct xe_cper_einfo_entry *einfo_arr = NULL;
> +	u32 einfo_count = 0;
> +	u32 i;
>  
>  	if (!xe)
>  		return;
>  
>  	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
>  		return;

[Severity: High]
This is a pre-existing issue, but is this check inverted?

It aborts if the error is >= INTEL_SIGID_GPU_XE_HARDWARE_START, which
seems to dead-code the entire hardware error logging feature. Since this
occurs on every hardware error, does this check completely neutralize
xe_emit_hardware_error_cper() for hardware errors?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=6

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records
  2026-09-06 17:26 ` [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records Badal Nilawar
  2026-09-06 17:30   ` sashiko-bot
@ 2026-09-09 11:58   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: Raag Jadav @ 2026-09-09 11:58 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:11PM +0530, Badal Nilawar wrote:
> Prepare xe_cper_sec_intel_error_info records from RAS
> info queue data. Depending on the error class type,
> detail or aggregate, one or more error info records
> may be generated and embedded in the CPER record.

Please utilize the full 75 character space where possible.

> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Assisted-by: Copilot:claude-opus-4.8
> ---
> v2:
>   - Fix sashiko warnings
> ---
>  drivers/gpu/drm/xe/xe_cper.c | 272 +++++++++++++++++++++++++++++++++--
>  1 file changed, 263 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index 31ca53ce1aa7..ebf4dc4ab2bb 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -173,6 +173,233 @@ static void xe_cper_record_emit(struct xe_device *xe, u8 severity,
>  
>  	kfree(rec);
>  }
> +
> +/**
> + * struct xe_cper_einfo_entry - One CPER error-info buffer with its byte size
> + * @hdr: dynamic-counter header carrying the per-entry error_class and counter
> + *       value; used by the caller to build a dedicated xe_cper_sec_intel_err_hdr
> + *       for each CPER record
> + * @einfo: allocated error-info payload (caller must kfree)
> + * @einfo_size: byte size of @einfo including any event_queue data
> + * @timestamp: timestamp of first occurrence of dynamic-counter
> + */
> +struct xe_cper_einfo_entry {
> +	struct xe_ras_info_queue_dynamic_counter_hdr hdr;
> +	struct xe_cper_sec_intel_error_info *einfo;
> +	u32 einfo_size;
> +	u64 timestamp;
> +};

Doesn't this belong in xe_cper_types.h?

> +static void fill_einfo_error_class(struct xe_cper_sec_intel_error_info *einfo,
> +				   const struct xe_ras_error_class *ec)
> +{
> +	einfo->error_class.error_type      = ec->common.severity;
> +	einfo->error_class.error_component = ec->common.component;
> +	einfo->error_class.tile            = ec->product.unit.tile;
> +	einfo->error_class.instance        = ec->product.unit.instance;
> +	einfo->error_class.cause           = ec->product.cause.cause;

Why can't this be a simple memcpy()?

> +}
> +
> +static struct xe_cper_sec_intel_error_info *
> +build_einfo(const struct xe_ras_error_log *logs, u32 num_logs,
> +	    const struct xe_ras_error_class *ec, u32 error_count,
> +	    u32 *size_out, u64 *ts_out)
> +{
> +	/*
> +	 * Although xe_intel_priv_event_entry has a flexible metadata[] array,
> +	 * every entry we emit carries the fixed-length error_details payload
> +	 * from xe_ras_error_log, so the per-entry stride is constant here.
> +	 */
> +	u32 entry_size = offsetof(struct xe_intel_priv_event_entry, metadata) +
> +			 sizeof_field(struct xe_ras_error_log, error_details);

All this magic should be below the declarations, preferably after
kzalloc().

> +	struct xe_cper_sec_intel_error_info *einfo;
> +	struct xe_intel_priv_event_entry *entry;
> +	u32 einfo_size = sizeof(*einfo) + num_logs * entry_size;

Ditto, and with that you can probably declare all u32 in a single line.

> +	u32 i;
> +
> +	einfo = kzalloc(einfo_size, GFP_KERNEL);

We've started moving over to kzalloc_obj() and friends.

> +	if (!einfo)
> +		return NULL;
> +
> +	einfo->error_count        = error_count;
> +	einfo->event_queue_length = num_logs * entry_size;
> +	einfo->event_queue_count  = num_logs;
> +	fill_einfo_error_class(einfo, ec);
> +
> +	entry = (struct xe_intel_priv_event_entry *)einfo->event_queue;
> +	for (i = 0; i < num_logs; i++) {
> +		entry->entry_length = sizeof_field(struct xe_ras_error_log, error_details);
> +		entry->timestamp    = logs[i].timestamp;
> +		memcpy(entry->metadata, logs[i].error_details, sizeof(logs[i].error_details));
> +		entry = (struct xe_intel_priv_event_entry *)((u8 *)entry + entry_size);
> +	}
> +
> +	*size_out = einfo_size;
> +	*ts_out   = logs[0].timestamp;

Why is 0 special?

> +	return einfo;
> +}
> +
> +static void free_einfo_arr(struct xe_cper_einfo_entry *einfo_arr, u32 count)
> +{
> +	u32 i;
> +
> +	if (!einfo_arr)

Should we be at this point without einfo_arr?

> +		return;
> +
> +	for (i = 0; i < count; i++)
> +		kfree(einfo_arr[i].einfo);
> +	kfree(einfo_arr);
> +}
> +
> +/**
> + * xe_prepare_cper_error_info - Build the CPER error info records from RAS info queue data
> + * @xe: xe device instance
> + * @counter_resp: counter response containing the first embedded chunk
> + * @error_class: RAS error class used to populate the einfo error_class fields
> + * @einfo_size_out: output size of the allocated einfo buffer
> + *
> + * Assembles the complete raw info queue data from the first chunk already
> + * embedded in @counter_resp and any additional chunks fetched via
> + * GET_INFO_QUEUE_DATA.  Two use cases are supported based on num_headers in
> + * the info queue header:
> + *
> + * Detail error counter (num_headers == 0)::
> + *
> + *   [xe_ras_error_log * N]
> + *
> + *   Returns one xe_cper_einfo_entry covering all N logs.
> + *
> + * Aggregate error counter (num_headers > 0)::
> + *
> + *   [xe_ras_info_queue_dynamic_counter_hdr * num_headers]
> + *   [xe_ras_error_log * N]
> + *
> + *   Returns one xe_cper_einfo_entry per header.  Each header's @counter field
> + *   gives the number of consecutive xe_ras_error_log entries belonging to it
> + *   and its @error_class is used to populate the entry's einfo->error_class.
> + *
> + * Returns: allocated xe_cper_einfo_entry array on success (caller must kfree
> + *          each entry's einfo then kfree the array), NULL on failure.
> + *          @count_out is set to the number of entries in the array.
> + */
> +static struct xe_cper_einfo_entry *
> +xe_prepare_cper_error_info(struct xe_device *xe,
> +			   const struct xe_ras_get_counter_response *counter_resp,
> +			   const struct xe_ras_error_class *error_class,
> +			   u32 *count_out)
> +{
> +	const struct xe_ras_info_queue_header *first_qhdr =
> +		&counter_resp->info_queue.queue_header;
> +	struct xe_cper_einfo_entry *einfo_arr;
> +	u32 num_headers, headers_size;
> +	u32 raw_total;
> +	u8 *raw_buf;
> +	u32 i;
> +
> +	raw_buf = kzalloc(XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE, GFP_KERNEL);

I'm not following here, shouldn't we only allocate for the data we actually
have?

> +	if (!raw_buf)
> +		return NULL;
> +
> +	raw_total = xe_ras_drain_info_queue_raw(xe, counter_resp, raw_buf,
> +						XE_RAS_INFO_QUEUE_MAX_TOTAL_SIZE);
> +	if (!raw_total) {
> +		kfree(raw_buf);
> +		return NULL;
> +	}
> +
> +	num_headers  = first_qhdr->num_headers;
> +	headers_size = num_headers * sizeof(struct xe_ras_info_queue_dynamic_counter_hdr);
> +
> +	if (headers_size > raw_total) {
> +		xe_warn(xe, "[RAS]: CPER: aggregate headers size (%u) exceeds raw total (%u)\n",

Is this a hardware error? Is [RAS] tag correct? (And in all other places
where applicable)

> +			headers_size, raw_total);
> +		kfree(raw_buf);
> +		return NULL;
> +	}
> +
> +	if (num_headers == 0) {

I like the build_einfo() helper but similar to that, can this be
consolidated into its own helper which works with 'num_headers' as
an argument? If it makes things camplicated, just split the cases
into their own functions.

> +		/* Detailed counter case: single einfo covering all log entries */
> +		u32 num_logs = raw_total / sizeof(struct xe_ras_error_log);
> +		const struct xe_ras_error_log *logs =
> +			(const struct xe_ras_error_log *)raw_buf;
> +		struct xe_cper_sec_intel_error_info *einfo;
> +
> +		if (!num_logs) {
> +			kfree(raw_buf);
> +			return NULL;
> +		}
> +
> +		einfo_arr = kzalloc_objs(*einfo_arr, 1, GFP_KERNEL);
> +		if (!einfo_arr) {
> +			kfree(raw_buf);
> +			return NULL;
> +		}
> +
> +		einfo = build_einfo(logs, num_logs, error_class, counter_resp->value,
> +				    &einfo_arr[0].einfo_size, &einfo_arr[0].timestamp);
> +		if (!einfo) {
> +			kfree(einfo_arr);
> +			kfree(raw_buf);
> +			return NULL;
> +		}
> +
> +		einfo_arr[0].hdr.error_class = *error_class;
> +		einfo_arr[0].hdr.counter     = counter_resp->value;
> +		einfo_arr[0].einfo           = einfo;
> +		*count_out = 1;
> +
> +	} else {
> +		/* Aggregate conter case: one einfo per dynamic-counter header */
> +		const struct xe_ras_info_queue_dynamic_counter_hdr *hdrs =
> +			(const struct xe_ras_info_queue_dynamic_counter_hdr *)raw_buf;
> +		const struct xe_ras_error_log *all_logs =
> +			(const struct xe_ras_error_log *)(raw_buf + headers_size);
> +		u32 avail_logs = (raw_total - headers_size) / sizeof(struct xe_ras_error_log);
> +		u32 log_offset = 0;
> +		u32 einfo_count = 0;
> +
> +		einfo_arr = kzalloc_objs(*einfo_arr, num_headers, GFP_KERNEL);
> +		if (!einfo_arr) {
> +			kfree(raw_buf);
> +			return NULL;
> +		}
> +
> +		for (i = 0; i < num_headers; i++) {
> +			u32 num_logs = min_t(u32, hdrs[i].counter, XE_RAS_NUM_COUNTERS);
> +			struct xe_cper_sec_intel_error_info *einfo;
> +
> +			if (log_offset + num_logs > avail_logs) {
> +				xe_warn(xe, "[RAS]: CPER: header[%u] claims %u logs but only %u remain\n",
> +					i, num_logs, avail_logs - log_offset);
> +				break;
> +			}
> +
> +			if (!num_logs)
> +				continue;
> +
> +			einfo = build_einfo(&all_logs[log_offset], num_logs,
> +					    &hdrs[i].error_class, num_logs,
> +					    &einfo_arr[einfo_count].einfo_size,
> +					    &einfo_arr[einfo_count].timestamp);
> +			if (!einfo) {
> +				free_einfo_arr(einfo_arr, einfo_count);
> +				kfree(raw_buf);
> +				return NULL;
> +			}
> +
> +			einfo_arr[einfo_count].hdr   = hdrs[i];
> +			einfo_arr[einfo_count].einfo = einfo;
> +			log_offset += num_logs;
> +			einfo_count++;
> +		}
> +
> +		*count_out = einfo_count;
> +	}
> +
> +	kfree(raw_buf);
> +	return einfo_arr;
> +}
> +
>  /**
>   * xe_emit_hardware_error_cper() - Emit a hardware error CPER record
>   * @pdev: PCI device associated with the Xe device
> @@ -191,6 +418,9 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  	struct xe_ras_get_counter_response local_resp = {};
>  	struct xe_ras_get_counter_response *counter_response = response;
>  	struct xe_cper_sec_intel_err_hdr ihdr = {};
> +	struct xe_cper_einfo_entry *einfo_arr = NULL;
> +	u32 einfo_count = 0;
> +	u32 i;
>  
>  	if (!xe)
>  		return;
> @@ -209,15 +439,39 @@ void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sig
>  		}
>  	}
>  
> -	xe_cper_init_intel_err_hdr(xe,
> -				   (const u8 *)counter,
> -				   counter_response->timestamp,
> -				   sigid,
> -				   counter_response->value,
> -				   &ihdr);
> +	if (counter_response->has_info_queue) {
> +		einfo_arr = xe_prepare_cper_error_info(xe, counter_response, counter, &einfo_count);
> +		if (!einfo_arr)
> +			xe_err(xe, "[RAS]: CPER: failed to build einfo from info queue\n");

Shouldn't this return an error? If no, why xe_err()?

> +	}
> +
> +	if (einfo_count > 0) {
> +		for (i = 0; i < einfo_count; i++) {
> +			struct xe_cper_sec_intel_err_hdr entry_ihdr = {};
>  
> -	xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
> -			    &ihdr, NULL, 0);
> +			xe_cper_init_intel_err_hdr(xe,
> +						   (const u8 *)&einfo_arr[i].hdr.error_class,
> +						   einfo_arr[i].timestamp,
> +						   sigid, einfo_arr[i].hdr.counter,
> +						   &entry_ihdr);
> +
> +			xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +					    &entry_ihdr, einfo_arr[i].einfo,
> +					    einfo_arr[i].einfo_size);

Same as above, can these be made robust to work with 'num_headers' as an
argument (in the respective patches which introduce them)?

Raag

> +		}
> +	} else {
> +		xe_cper_init_intel_err_hdr(xe,
> +					   (const u8 *)counter,
> +					   counter_response->timestamp,
> +					   sigid, counter_response->value, &ihdr);
> +
> +		xe_cper_record_emit(xe, cper_sev, &INTEL_CPER_NOTIFY_GPU_ERROR,
> +				    &ihdr, NULL, 0);
> +	}
> +
> +	if (einfo_arr) {
> +		free_einfo_arr(einfo_arr, einfo_count);
> +		einfo_arr = NULL;
> +	}
>  
> -	/* TODO */
>  }
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (7 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:23   ` sashiko-bot
  2026-09-10  6:27   ` Raag Jadav
  2026-09-06 17:26 ` [PATCH v3 08/12] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
                   ` (6 subsequent siblings)
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Log CPER records for aggregate counter retrieval from userspace
when cper_on_query sysfs is enabled.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/xe/xe_drm_ras_types.h |  3 +
 drivers/gpu/drm/xe/xe_ras.c           | 91 ++++++++++++++++++++++++++-
 2 files changed, 93 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
index 0be218ba2db7..8fb5d6457c53 100644
--- a/drivers/gpu/drm/xe/xe_drm_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
@@ -46,6 +46,9 @@ struct xe_drm_ras {
 
 	/** @disable_vram_page_offline: cached configfs policy, immutable after init */
 	bool disable_vram_page_offline;
+
+	/** @cper_on_query: emit a CPER record on each counter query */
+	bool cper_on_query;
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 7e3e62750448..288dbc0942f5 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -4,6 +4,7 @@
  */
 
 #include "xe_configfs.h"
+#include "xe_cper.h"
 #include "xe_debugfs.h"
 #include "xe_device.h"
 #include "xe_drm_ras.h"
@@ -199,6 +200,34 @@ static inline const char *comp_to_str(u8 component)
 	return xe_ras_components[component];
 }
 
+static u32 ras_comp_to_hw_sigid(u8 component)
+{
+	switch (component) {
+	case XE_RAS_COMP_DEVICE_MEMORY:
+		return XE_SIGID_DEVICE_MEMORY;
+	case XE_RAS_COMP_CORE_COMPUTE:
+		return XE_SIGID_CORE_COMPUTE;
+	case XE_RAS_COMP_PCIE:
+		return XE_SIGID_PCIE;
+	case XE_RAS_COMP_FABRIC:
+		return XE_SIGID_FABRIC;
+	case XE_RAS_COMP_SOC_INTERNAL:
+		return XE_SIGID_SOC_INTERNAL;
+	default:
+		return U32_MAX;
+	}
+}
+
+static u8 ras_sev_to_cper_sev(u8 ras_sev)
+{
+	switch (ras_sev) {
+	case XE_RAS_SEV_CORRECTABLE:   return CPER_SEV_CORRECTED;
+	case XE_RAS_SEV_UNCORRECTABLE: return CPER_SEV_RECOVERABLE;
+	case XE_RAS_SEV_INFORMATIONAL: return CPER_SEV_INFORMATIONAL;
+	default:                       return CPER_SEV_RECOVERABLE;
+	}
+}
+
 static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
 {
 	struct pci_dev *vsp;
@@ -612,6 +641,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
  */
 int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value)
 {
+	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
 	struct xe_ras_error_class counter = {0};
 	struct xe_ras_get_counter_response response = {0};
 	int ret;
@@ -623,8 +653,13 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
 	ret = xe_ras_get_counter_response(xe, &counter, &response);
 	if (ret)
 		return ret;
-
 	*value = response.value;
+
+	if (xe->ras.cper_on_query)
+		xe_emit_hardware_error_cper(pdev, ras_sev_to_cper_sev(counter.common.severity),
+					    ras_comp_to_hw_sigid(counter.common.component),
+					    (struct xe_ras_error_class *)&counter,
+					    (struct xe_ras_get_counter_response *)&response);
 	return 0;
 }
 
@@ -1069,6 +1104,56 @@ static const struct attribute_group gpu_health_group = {
 	.attrs = gpu_health_attrs,
 };
 
+static ssize_t cper_on_query_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct xe_device *xe = kdev_to_xe_device(dev);
+
+	return sysfs_emit(buf, "%u\n", xe->ras.cper_on_query);
+}
+
+static ssize_t cper_on_query_store(struct device *dev, struct device_attribute *attr,
+				   const char *buf, size_t count)
+{
+	struct xe_device *xe = kdev_to_xe_device(dev);
+	bool enable;
+	int ret;
+
+	ret = kstrtobool(buf, &enable);
+	if (ret)
+		return ret;
+
+	xe->ras.cper_on_query = enable;
+
+	return count;
+}
+static DEVICE_ATTR_ADMIN_RW(cper_on_query);
+
+static struct attribute *cper_on_query_attrs[] = {
+	&dev_attr_cper_on_query.attr,
+	NULL
+};
+
+/**
+ * DOC: CPER on query
+ *
+ * On Intel Xe platforms that support the RAS error reporting interface,
+ * the driver can emit a CPER (Common Platform Error Record) each time an
+ * error counter is queried. This behaviour is controlled through the
+ * following sysfs attribute::
+ *
+ *     /sys/bus/pci/devices/<device>/cper_on_query
+ *
+ * The attribute is a boolean (``0`` or ``1``). When set to ``1``, every
+ * counter query emits a CPER record built from the associated info queue
+ * data; when set to ``0`` (default) no record is emitted on query.
+ *
+ * Reading the attribute is available to all users and returns the current
+ * setting, whereas writing is restricted to administrative users.
+ */
+static const struct attribute_group cper_on_query_group = {
+	.attrs = cper_on_query_attrs,
+};
+
 /**
  * xe_ras_init - Initialize Xe RAS
  * @xe: xe device instance
@@ -1098,4 +1183,8 @@ void xe_ras_init(struct xe_device *xe)
 	ret = devm_device_add_group(xe->drm.dev, &gpu_health_group);
 	if (ret)
 		xe_err(xe, "Failed to create GPU health sysfs, err=%d\n", ret);
+
+	ret = devm_device_add_group(xe->drm.dev, &cper_on_query_group);
+	if (ret)
+		xe_err(xe, "Failed to create cper_on_query sysfs, err=%d\n", ret);
 }
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival
  2026-09-06 17:26 ` [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival Badal Nilawar
@ 2026-09-06 17:23   ` sashiko-bot
  2026-09-10  6:27   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:23 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:

New issues:
- [Medium] Passing incompletely initialized query counter struct to CPER logging instead of the fully populated response counter returned by hardware.
- [Low] The sysfs attribute `cper_on_query` is created with 0600 permissions, contradicting its documentation which states it is readable by all users.

Pre-existing issues:
- [High] The preexisting `xe_emit_hardware_error_cper` function silently aborts when passed a valid hardware sigid, completely breaking the new CPER logging functionality.
--

commit 4840bdedfff2abbfbb8ce20f95bb4403db40e936
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Log CPER records for aggregate counter retrival

This commit adds support to log CPER records for aggregate counter
retrieval from userspace. It introduces a new sysfs attribute
cper_on_query to control this behavior.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 7e3e627504485..288dbc0942f58 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
[ ... ]
> @@ -612,6 +641,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
>   */
>  int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value)
>  {
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>  	struct xe_ras_error_class counter = {0};
>  	struct xe_ras_get_counter_response response = {0};
>  	int ret;
> @@ -623,8 +653,13 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
>  	ret = xe_ras_get_counter_response(xe, &counter, &response);
>  	if (ret)
>  		return ret;
> -
>  	*value = response.value;
> +
> +	if (xe->ras.cper_on_query)
> +		xe_emit_hardware_error_cper(pdev, ras_sev_to_cper_sev(counter.common.severity),
> +					    ras_comp_to_hw_sigid(counter.common.component),
> +					    (struct xe_ras_error_class *)&counter,

[Severity: Medium]
Does this code pass the incompletely initialized query counter instead of the 
fully populated &response.counter returned by hardware? 

The CPER record emitted will be missing the product-specific hardware
classification fields (like tile, instance, cause), leading to information loss
in RAS logging.

[Severity: High]
This is a pre-existing issue, but xe_emit_hardware_error_cper() silently
aborts when passed a valid hardware sigid (which are all 
>= INTEL_SIGID_GPU_XE_HARDWARE_START) due to a backwards check:

drivers/gpu/drm/xe/xe_cper.c:xe_emit_hardware_error_cper() {
	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
		return;
    ...
}

Does this completely break the new CPER logging functionality intended by 
this patch?

> +					    (struct xe_ras_get_counter_response *)&response);
>  	return 0;
>  }
>  
[ ... ]
> @@ -1069,6 +1104,56 @@ static const struct attribute_group gpu_health_group = {
>  	.attrs = gpu_health_attrs,
>  };
>  
> +static ssize_t cper_on_query_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct xe_device *xe = kdev_to_xe_device(dev);
> +
> +	return sysfs_emit(buf, "%u\n", xe->ras.cper_on_query);
> +}
> +
> +static ssize_t cper_on_query_store(struct device *dev, struct device_attribute *attr,
> +				   const char *buf, size_t count)
> +{
> +	struct xe_device *xe = kdev_to_xe_device(dev);
> +	bool enable;
> +	int ret;
> +
> +	ret = kstrtobool(buf, &enable);
> +	if (ret)
> +		return ret;
> +
> +	xe->ras.cper_on_query = enable;
> +
> +	return count;
> +}
> +static DEVICE_ATTR_ADMIN_RW(cper_on_query);

[Severity: Low]
Does this incorrectly enforce 0600 permissions, preventing non-root users from 
reading the value? 

The documentation below states it should be readable by all users:

> +
> +static struct attribute *cper_on_query_attrs[] = {
> +	&dev_attr_cper_on_query.attr,
> +	NULL
> +};
> +
> +/**
> + * DOC: CPER on query
> + *
> + * On Intel Xe platforms that support the RAS error reporting interface,
> + * the driver can emit a CPER (Common Platform Error Record) each time an
> + * error counter is queried. This behaviour is controlled through the
> + * following sysfs attribute::
> + *
> + *     /sys/bus/pci/devices/<device>/cper_on_query
> + *
> + * The attribute is a boolean (``0`` or ``1``). When set to ``1``, every
> + * counter query emits a CPER record built from the associated info queue
> + * data; when set to ``0`` (default) no record is emitted on query.
> + *
> + * Reading the attribute is available to all users and returns the current
> + * setting, whereas writing is restricted to administrative users.
> + */

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=7

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival
  2026-09-06 17:26 ` [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival Badal Nilawar
  2026-09-06 17:23   ` sashiko-bot
@ 2026-09-10  6:27   ` Raag Jadav
  2026-09-10 22:29     ` Rodrigo Vivi
  1 sibling, 1 reply; 45+ messages in thread
From: Raag Jadav @ 2026-09-10  6:27 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:12PM +0530, Badal Nilawar wrote:
> Log CPER records for aggregate counter retrieval from userspace
> when cper_on_query sysfs is enabled.
> 
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_drm_ras_types.h |  3 +
>  drivers/gpu/drm/xe/xe_ras.c           | 91 ++++++++++++++++++++++++++-
>  2 files changed, 93 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
> index 0be218ba2db7..8fb5d6457c53 100644
> --- a/drivers/gpu/drm/xe/xe_drm_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
> @@ -46,6 +46,9 @@ struct xe_drm_ras {
>  
>  	/** @disable_vram_page_offline: cached configfs policy, immutable after init */
>  	bool disable_vram_page_offline;
> +
> +	/** @cper_on_query: emit a CPER record on each counter query */
> +	bool cper_on_query;

Nack, cper is unrelated to drm_ras and should not be mixed here.
This belongs to xe_device with its own state that is maintained
as something like struct xe_cper.

Same goes for disable_vram_page_offline, but that I think is upto
the maintainers.

>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 7e3e62750448..288dbc0942f5 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -4,6 +4,7 @@
>   */
>  
>  #include "xe_configfs.h"
> +#include "xe_cper.h"
>  #include "xe_debugfs.h"
>  #include "xe_device.h"
>  #include "xe_drm_ras.h"
> @@ -199,6 +200,34 @@ static inline const char *comp_to_str(u8 component)
>  	return xe_ras_components[component];
>  }
>  
> +static u32 ras_comp_to_hw_sigid(u8 component)

All the switcheroos are above sev_to_str(), it'd be quite sad for these
to be left alone here.

> +{
> +	switch (component) {
> +	case XE_RAS_COMP_DEVICE_MEMORY:
> +		return XE_SIGID_DEVICE_MEMORY;
> +	case XE_RAS_COMP_CORE_COMPUTE:
> +		return XE_SIGID_CORE_COMPUTE;
> +	case XE_RAS_COMP_PCIE:
> +		return XE_SIGID_PCIE;
> +	case XE_RAS_COMP_FABRIC:
> +		return XE_SIGID_FABRIC;
> +	case XE_RAS_COMP_SOC_INTERNAL:
> +		return XE_SIGID_SOC_INTERNAL;
> +	default:
> +		return U32_MAX;
> +	}
> +}
> +
> +static u8 ras_sev_to_cper_sev(u8 ras_sev)

Ditto.

> +{
> +	switch (ras_sev) {
> +	case XE_RAS_SEV_CORRECTABLE:   return CPER_SEV_CORRECTED;
> +	case XE_RAS_SEV_UNCORRECTABLE: return CPER_SEV_RECOVERABLE;
> +	case XE_RAS_SEV_INFORMATIONAL: return CPER_SEV_INFORMATIONAL;
> +	default:                       return CPER_SEV_RECOVERABLE;

I like this formatting but these should be consistent with similar existing
switcheroos. So whatever your preference, please make all of them consistent.

> +	}
> +}
> +
>  static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
>  {
>  	struct pci_dev *vsp;
> @@ -612,6 +641,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
>   */
>  int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value)
>  {
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>  	struct xe_ras_error_class counter = {0};
>  	struct xe_ras_get_counter_response response = {0};
>  	int ret;
> @@ -623,8 +653,13 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
>  	ret = xe_ras_get_counter_response(xe, &counter, &response);
>  	if (ret)
>  		return ret;
> -

Why?

>  	*value = response.value;
> +
> +	if (xe->ras.cper_on_query)
> +		xe_emit_hardware_error_cper(pdev, ras_sev_to_cper_sev(counter.common.severity),
> +					    ras_comp_to_hw_sigid(counter.common.component),
> +					    (struct xe_ras_error_class *)&counter,
> +					    (struct xe_ras_get_counter_response *)&response);

Why the casting? What changed?

>  	return 0;
>  }
>  
> @@ -1069,6 +1104,56 @@ static const struct attribute_group gpu_health_group = {
>  	.attrs = gpu_health_attrs,
>  };
>  
> +static ssize_t cper_on_query_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct xe_device *xe = kdev_to_xe_device(dev);
> +
> +	return sysfs_emit(buf, "%u\n", xe->ras.cper_on_query);
> +}
> +
> +static ssize_t cper_on_query_store(struct device *dev, struct device_attribute *attr,
> +				   const char *buf, size_t count)
> +{
> +	struct xe_device *xe = kdev_to_xe_device(dev);
> +	bool enable;
> +	int ret;
> +
> +	ret = kstrtobool(buf, &enable);
> +	if (ret)
> +		return ret;
> +
> +	xe->ras.cper_on_query = enable;
> +
> +	return count;
> +}
> +static DEVICE_ATTR_ADMIN_RW(cper_on_query);
> +
> +static struct attribute *cper_on_query_attrs[] = {
> +	&dev_attr_cper_on_query.attr,
> +	NULL
> +};
> +
> +/**
> + * DOC: CPER on query

Is this actually hooked to the docs?

> + *
> + * On Intel Xe platforms that support the RAS error reporting interface,
> + * the driver can emit a CPER (Common Platform Error Record) each time an
> + * error counter is queried. This behaviour is controlled through the
> + * following sysfs attribute::
> + *
> + *     /sys/bus/pci/devices/<device>/cper_on_query
> + *
> + * The attribute is a boolean (``0`` or ``1``). When set to ``1``, every
> + * counter query emits a CPER record built from the associated info queue
> + * data; when set to ``0`` (default) no record is emitted on query.
> + *
> + * Reading the attribute is available to all users and returns the current
> + * setting, whereas writing is restricted to administrative users.
> + */
> +static const struct attribute_group cper_on_query_group = {
> +	.attrs = cper_on_query_attrs,
> +};
> +
>  /**
>   * xe_ras_init - Initialize Xe RAS
>   * @xe: xe device instance
> @@ -1098,4 +1183,8 @@ void xe_ras_init(struct xe_device *xe)
>  	ret = devm_device_add_group(xe->drm.dev, &gpu_health_group);
>  	if (ret)
>  		xe_err(xe, "Failed to create GPU health sysfs, err=%d\n", ret);
> +
> +	ret = devm_device_add_group(xe->drm.dev, &cper_on_query_group);
> +	if (ret)
> +		xe_err(xe, "Failed to create cper_on_query sysfs, err=%d\n", ret);

I really dislike that we're ignoring error here. Same was done with
gpu_health_group. I know they're non-fatal but it just makes them
harder to root cause when something else breaks as a side-effect of
this. But again, not my call.

Raag

>  }
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival
  2026-09-10  6:27   ` Raag Jadav
@ 2026-09-10 22:29     ` Rodrigo Vivi
  0 siblings, 0 replies; 45+ messages in thread
From: Rodrigo Vivi @ 2026-09-10 22:29 UTC (permalink / raw)
  To: Raag Jadav
  Cc: Badal Nilawar, intel-xe, anshuman.gupta, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Thu, Sep 10, 2026 at 08:27:44AM +0200, Raag Jadav wrote:
> On Sun, Sep 06, 2026 at 10:56:12PM +0530, Badal Nilawar wrote:
> > Log CPER records for aggregate counter retrieval from userspace
> > when cper_on_query sysfs is enabled.
> > 
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_drm_ras_types.h |  3 +
> >  drivers/gpu/drm/xe/xe_ras.c           | 91 ++++++++++++++++++++++++++-
> >  2 files changed, 93 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_drm_ras_types.h b/drivers/gpu/drm/xe/xe_drm_ras_types.h
> > index 0be218ba2db7..8fb5d6457c53 100644
> > --- a/drivers/gpu/drm/xe/xe_drm_ras_types.h
> > +++ b/drivers/gpu/drm/xe/xe_drm_ras_types.h
> > @@ -46,6 +46,9 @@ struct xe_drm_ras {
> >  
> >  	/** @disable_vram_page_offline: cached configfs policy, immutable after init */
> >  	bool disable_vram_page_offline;
> > +
> > +	/** @cper_on_query: emit a CPER record on each counter query */
> > +	bool cper_on_query;
> 
> Nack, cper is unrelated to drm_ras and should not be mixed here.
> This belongs to xe_device with its own state that is maintained
> as something like struct xe_cper.

agree

> 
> Same goes for disable_vram_page_offline, but that I think is upto
> the maintainers.

agree as well, at least until we don't get that mem page offline that Aravind is doing.

> 
> >  };
> >  
> >  #endif
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > index 7e3e62750448..288dbc0942f5 100644
> > --- a/drivers/gpu/drm/xe/xe_ras.c
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > @@ -4,6 +4,7 @@
> >   */
> >  
> >  #include "xe_configfs.h"
> > +#include "xe_cper.h"
> >  #include "xe_debugfs.h"
> >  #include "xe_device.h"
> >  #include "xe_drm_ras.h"
> > @@ -199,6 +200,34 @@ static inline const char *comp_to_str(u8 component)
> >  	return xe_ras_components[component];
> >  }
> >  
> > +static u32 ras_comp_to_hw_sigid(u8 component)
> 
> All the switcheroos are above sev_to_str(), it'd be quite sad for these
> to be left alone here.
> 
> > +{
> > +	switch (component) {
> > +	case XE_RAS_COMP_DEVICE_MEMORY:
> > +		return XE_SIGID_DEVICE_MEMORY;
> > +	case XE_RAS_COMP_CORE_COMPUTE:
> > +		return XE_SIGID_CORE_COMPUTE;
> > +	case XE_RAS_COMP_PCIE:
> > +		return XE_SIGID_PCIE;
> > +	case XE_RAS_COMP_FABRIC:
> > +		return XE_SIGID_FABRIC;
> > +	case XE_RAS_COMP_SOC_INTERNAL:
> > +		return XE_SIGID_SOC_INTERNAL;
> > +	default:
> > +		return U32_MAX;
> > +	}
> > +}
> > +
> > +static u8 ras_sev_to_cper_sev(u8 ras_sev)
> 
> Ditto.
> 
> > +{
> > +	switch (ras_sev) {
> > +	case XE_RAS_SEV_CORRECTABLE:   return CPER_SEV_CORRECTED;
> > +	case XE_RAS_SEV_UNCORRECTABLE: return CPER_SEV_RECOVERABLE;
> > +	case XE_RAS_SEV_INFORMATIONAL: return CPER_SEV_INFORMATIONAL;
> > +	default:                       return CPER_SEV_RECOVERABLE;
> 
> I like this formatting but these should be consistent with similar existing
> switcheroos. So whatever your preference, please make all of them consistent.
> 
> > +	}
> > +}
> > +
> >  static struct pci_dev *find_usp_dev(struct pci_dev *pdev)
> >  {
> >  	struct pci_dev *vsp;
> > @@ -612,6 +641,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
> >   */
> >  int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *value)
> >  {
> > +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> >  	struct xe_ras_error_class counter = {0};
> >  	struct xe_ras_get_counter_response response = {0};
> >  	int ret;
> > @@ -623,8 +653,13 @@ int xe_ras_get_counter(struct xe_device *xe, u8 severity, u8 component, u32 *val
> >  	ret = xe_ras_get_counter_response(xe, &counter, &response);
> >  	if (ret)
> >  		return ret;
> > -
> 
> Why?
> 
> >  	*value = response.value;
> > +
> > +	if (xe->ras.cper_on_query)
> > +		xe_emit_hardware_error_cper(pdev, ras_sev_to_cper_sev(counter.common.severity),
> > +					    ras_comp_to_hw_sigid(counter.common.component),
> > +					    (struct xe_ras_error_class *)&counter,
> > +					    (struct xe_ras_get_counter_response *)&response);
> 
> Why the casting? What changed?
> 
> >  	return 0;
> >  }
> >  
> > @@ -1069,6 +1104,56 @@ static const struct attribute_group gpu_health_group = {
> >  	.attrs = gpu_health_attrs,
> >  };
> >  
> > +static ssize_t cper_on_query_show(struct device *dev, struct device_attribute *attr, char *buf)
> > +{
> > +	struct xe_device *xe = kdev_to_xe_device(dev);
> > +
> > +	return sysfs_emit(buf, "%u\n", xe->ras.cper_on_query);
> > +}
> > +
> > +static ssize_t cper_on_query_store(struct device *dev, struct device_attribute *attr,
> > +				   const char *buf, size_t count)
> > +{
> > +	struct xe_device *xe = kdev_to_xe_device(dev);
> > +	bool enable;
> > +	int ret;
> > +
> > +	ret = kstrtobool(buf, &enable);
> > +	if (ret)
> > +		return ret;
> > +
> > +	xe->ras.cper_on_query = enable;
> > +
> > +	return count;
> > +}
> > +static DEVICE_ATTR_ADMIN_RW(cper_on_query);
> > +
> > +static struct attribute *cper_on_query_attrs[] = {
> > +	&dev_attr_cper_on_query.attr,
> > +	NULL
> > +};
> > +
> > +/**
> > + * DOC: CPER on query
> 
> Is this actually hooked to the docs?
> 
> > + *
> > + * On Intel Xe platforms that support the RAS error reporting interface,
> > + * the driver can emit a CPER (Common Platform Error Record) each time an
> > + * error counter is queried. This behaviour is controlled through the
> > + * following sysfs attribute::
> > + *
> > + *     /sys/bus/pci/devices/<device>/cper_on_query
> > + *
> > + * The attribute is a boolean (``0`` or ``1``). When set to ``1``, every
> > + * counter query emits a CPER record built from the associated info queue
> > + * data; when set to ``0`` (default) no record is emitted on query.
> > + *
> > + * Reading the attribute is available to all users and returns the current
> > + * setting, whereas writing is restricted to administrative users.
> > + */
> > +static const struct attribute_group cper_on_query_group = {
> > +	.attrs = cper_on_query_attrs,
> > +};
> > +
> >  /**
> >   * xe_ras_init - Initialize Xe RAS
> >   * @xe: xe device instance
> > @@ -1098,4 +1183,8 @@ void xe_ras_init(struct xe_device *xe)
> >  	ret = devm_device_add_group(xe->drm.dev, &gpu_health_group);
> >  	if (ret)
> >  		xe_err(xe, "Failed to create GPU health sysfs, err=%d\n", ret);
> > +
> > +	ret = devm_device_add_group(xe->drm.dev, &cper_on_query_group);
> > +	if (ret)
> > +		xe_err(xe, "Failed to create cper_on_query sysfs, err=%d\n", ret);
> 
> I really dislike that we're ignoring error here. Same was done with
> gpu_health_group. I know they're non-fatal but it just makes them
> harder to root cause when something else breaks as a side-effect of
> this. But again, not my call.
> 
> Raag
> 
> >  }
> > -- 
> > 2.54.0
> > 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 08/12] drm/xe/xe_ras: Report device memory errors using SIGID
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (8 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:27   ` sashiko-bot
  2026-09-06 17:26 ` [PATCH v3 09/12] drm/xe/xe_ras: Report core compute " Badal Nilawar
                   ` (5 subsequent siblings)
  15 siblings, 1 reply; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Use xe_log_comp_info helper to report device memory errors.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 288dbc0942f5..3a7f80370827 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -387,14 +387,17 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
 	 */
 	switch (info->category) {
 	case XE_RAS_MEMORY_POISON:
-		xe_info(xe, "[RAS]: Poison error detected\n");
+		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+				 "Poison error detected\n");
 		break;
 	case XE_RAS_MEMORY_DATA_PARITY:
-		xe_info(xe, "[RAS]: Data parity error detected\n");
+		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+				 "Data parity error detected\n");
 		break;
 	case XE_RAS_MEMORY_DB_ECC:
-		xe_info(xe, "[RAS]: Double-bit ECC error detected at sw address 0x%llx\n",
-			info->sw_address);
+		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
+				 "Double-bit ECC error detected at sw address 0x%llx\n",
+				 info->sw_address);
 		/* TODO: Add page offlining for Double-bit ECC error */
 		fallthrough;
 	default:
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 08/12] drm/xe/xe_ras: Report device memory errors using SIGID
  2026-09-06 17:26 ` [PATCH v3 08/12] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
@ 2026-09-06 17:27   ` sashiko-bot
  0 siblings, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:27 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Medium] Double-bit ECC memory errors are incorrectly reported with CPER_SEV_INFORMATIONAL severity despite being severe enough to trigger a device reset.

Pre-existing issues:
- [High] Hardware CPER records are silently discarded due to an inverted SIGID check.
--

commit 0369a03d8670385fb852c68b7ab519615f2c4e05
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/xe_ras: Report device memory errors using SIGID

This commit updates device memory error reporting to use the
xe_log_comp_info helper. It maps memory errors like poison, data parity,
and double-bit ECC to this new telemetry interface.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 288dbc0942f58..3a7f80370827e 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c

[ ... ]

> @@ -387,14 +387,17 @@ static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_
>  	 */
>  	switch (info->category) {
>  	case XE_RAS_MEMORY_POISON:
> -		xe_info(xe, "[RAS]: Poison error detected\n");
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Poison error detected\n");
>  		break;
>  	case XE_RAS_MEMORY_DATA_PARITY:
> -		xe_info(xe, "[RAS]: Data parity error detected\n");
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Data parity error detected\n");
>  		break;
>  	case XE_RAS_MEMORY_DB_ECC:
> -		xe_info(xe, "[RAS]: Double-bit ECC error detected at sw address 0x%llx\n",
> -			info->sw_address);
> +		xe_log_comp_info(xe, DEVICE_MEMORY, &arr->counter, sizeof(arr->counter),
> +				 "Double-bit ECC error detected at sw address 0x%llx\n",
> +				 info->sw_address);

[Severity: Medium]
Will this incorrectly report double-bit ECC memory errors with
CPER_SEV_INFORMATIONAL severity despite being severe enough to trigger a
device reset?

The xe_log_comp_info macro hardcodes the CPER severity to
CPER_SEV_INFORMATIONAL. After logging, the switch statement falls through
to the default case and returns XE_RAS_RECOVERY_ACTION_RESET. 

Could this break automated fleet management that acts on CPER severities
because a severe uncorrectable double-bit ECC error is logged as
informational while the driver actually resets the GPU?

>  		/* TODO: Add page offlining for Double-bit ECC error */
>  		fallthrough;
>  	default:
>  		return XE_RAS_RECOVERY_ACTION_RESET;
>  	}

[ ... ]

This isn't a bug introduced by this patch, but looking at the broader
telemetry handling in drivers/gpu/drm/xe/xe_cper.c:

> void xe_emit_hardware_error_cper(struct pci_dev *pdev, int cper_sev, enum xe_sigid sigid,
> 				 struct xe_ras_error_class *counter,
> 				 struct xe_ras_get_counter_response *response)
> {
> 	struct xe_device *xe = pdev_to_xe_device(pdev);
>       ...
> 
> 	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
> 		return;
>       ...

[Severity: High]
Are hardware CPER records being silently discarded here due to an inverted
SIGID check?

When xe_emit_hardware_error_cper() is called to emit a record for a hardware
error, the sigid parameter is greater than or equal to
INTEL_SIGID_GPU_XE_HARDWARE_START, which is the base value for all hardware
SIGIDs. 

This condition evaluates to true, causing the function to immediately return
before any CPER record is emitted, rendering the logging API calls
completely ineffective for hardware faults.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=8

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 09/12] drm/xe/xe_ras: Report core compute errors using SIGID
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (9 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 08/12] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:21   ` sashiko-bot
  2026-09-06 17:26 ` [PATCH v3 10/12] drm/xe/xe_ras: Report soc internal " Badal Nilawar
                   ` (4 subsequent siblings)
  15 siblings, 1 reply; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Use xe_log_* helpers to report core compute errors.

v2:
  - Pass RAS firmware reported severity to xe_log

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 3a7f80370827..78ea5e33e244 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -310,21 +310,27 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
 	xe_drm_ras_event(xe, drm_component, drm_severity, response.value);
 }
 
-static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
+static u8 handle_core_compute_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
 {
 	struct xe_ras_compute_error *error_info = (void *)arr->details;
+	u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
 	u8 uncorr_type;
 
 	uncorr_type = FIELD_GET(CORE_COMPUTE_UNCORR_TYPE, error_info->log_header);
 
 	/* Request a reset if error is global */
-	if (uncorr_type == GLOBAL_UNCORR_ERROR)
+	if (uncorr_type == GLOBAL_UNCORR_ERROR) {
+		xe_log_comp(xe, cper_sev, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
+			    "Global uncorrectable error detected\n");
 		return XE_RAS_RECOVERY_ACTION_RESET;
+	}
 
 	/*
 	 * No action needed for other errors.
 	 * Local errors are recovered using an engine reset by GuC.
 	 */
+	xe_log_comp(xe, cper_sev, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
+		    "Other compute errors\n");
 	return XE_RAS_RECOVERY_ACTION_RECOVERED;
 }
 
@@ -597,7 +603,7 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 
 			switch (component) {
 			case XE_RAS_COMP_CORE_COMPUTE:
-				action = handle_core_compute_errors(arr);
+				action = handle_core_compute_errors(xe, arr);
 				break;
 			case XE_RAS_COMP_SOC_INTERNAL:
 				action = handle_soc_internal_errors(xe, arr);
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 09/12] drm/xe/xe_ras: Report core compute errors using SIGID
  2026-09-06 17:26 ` [PATCH v3 09/12] drm/xe/xe_ras: Report core compute " Badal Nilawar
@ 2026-09-06 17:21   ` sashiko-bot
  0 siblings, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:21 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] Hardware error CPER emission is completely disabled due to an inverted condition check on the error signature ID.
--

commit 5c8af98618264b3c8466a350a075ee0f1ad606e7
Author: Badal Nilawar <badal.nilawar@intel.com>

    drm/xe/xe_ras: Report core compute errors using SIGID
    
    Use xe_log_* helpers to report core compute errors.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 3a7f80370827e..78ea5e33e244b 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -310,21 +310,27 @@ static void ras_send_error_event(struct xe_device *xe, u8 severity, u8 component
>  	xe_drm_ras_event(xe, drm_component, drm_severity, response.value);
>  }
>  
> -static u8 handle_core_compute_errors(struct xe_ras_error_array *arr)
> +static u8 handle_core_compute_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
>  {
>  	struct xe_ras_compute_error *error_info = (void *)arr->details;
> +	u8 cper_sev = ras_sev_to_cper_sev(arr->counter.common.severity);
>  	u8 uncorr_type;
>  
>  	uncorr_type = FIELD_GET(CORE_COMPUTE_UNCORR_TYPE, error_info->log_header);
>  
>  	/* Request a reset if error is global */
> -	if (uncorr_type == GLOBAL_UNCORR_ERROR)
> +	if (uncorr_type == GLOBAL_UNCORR_ERROR) {
> +		xe_log_comp(xe, cper_sev, CORE_COMPUTE, &arr->counter, sizeof(arr->counter),
> +			    "Global uncorrectable error detected\n");

[Severity: High]
This is a pre-existing issue, but will these hardware errors actually be emitted
by the CPER infrastructure?

Looking at xe_emit_hardware_error_cper() in drivers/gpu/drm/xe/xe_cper.c, which
processes these hardware SIGIDs, there appears to be an inverted condition check:

drivers/gpu/drm/xe/xe_cper.c:xe_emit_hardware_error_cper() {
	...
	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
		return;
	...
}

Any time xe_emit_hardware_error_cper() is called with a valid hardware SIGID,
does this inverted check silently drop the CPER record instead of processing it?

>  		return XE_RAS_RECOVERY_ACTION_RESET;
> +	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=9

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 10/12] drm/xe/xe_ras: Report soc internal errors using SIGID
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (10 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 09/12] drm/xe/xe_ras: Report core compute " Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:26 ` [PATCH v3 11/12] drm/xe/xe_ras: Report correctable " Badal Nilawar
                   ` (3 subsequent siblings)
  15 siblings, 0 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Use xe_log_* helpers to report soc internal errors.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Riana Tauro <riana.tauro@intel.com>
---
v2: Fix indentation
---
 drivers/gpu/drm/xe/xe_ras.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 78ea5e33e244..e93a989fc8f6 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -344,7 +344,6 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
 {
 	struct xe_ras_soc_error *info = (void *)arr->details;
 	struct xe_ras_soc_error_source *source = &info->source;
-	struct xe_ras_error_class *counter = &arr->counter;
 
 	if (source->csc) {
 		struct xe_ras_csc_error *csc_error = (void *)info->details;
@@ -358,9 +357,8 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
 		 * is required.
 		 */
 		if (csc_error->hec_fw_error) {
-			xe_err(xe, "[RAS]: CSC %s detected: 0x%x\n",
-			       sev_to_str(counter->common.severity),
-			       csc_error->hec_fw_error);
+			xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
+					  "CSC error detected: 0x%x\n", csc_error->hec_fw_error);
 			xe_survivability_mode_runtime_enable(xe);
 			return XE_RAS_RECOVERY_ACTION_DISCONNECT;
 		}
@@ -368,9 +366,9 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
 		struct xe_ras_ieh_error *ieh_error = (void *)info->details;
 
 		if (ieh_error->global_error_status & XE_RAS_SOC_IEH_PUNIT) {
-			xe_err(xe, "[RAS]: PUNIT %s detected: 0x%x\n",
-			       sev_to_str(counter->common.severity),
-			       ieh_error->global_error_status);
+			xe_log_comp_fatal(xe, SOC_INTERNAL, &arr->counter, sizeof(arr->counter),
+					  "PUNIT error detected: 0x%x\n",
+					   ieh_error->global_error_status);
 			punit_error_handler(xe);
 			return XE_RAS_RECOVERY_ACTION_DISCONNECT;
 		}
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH v3 11/12] drm/xe/xe_ras: Report correctable errors using SIGID
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (11 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 10/12] drm/xe/xe_ras: Report soc internal " Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:27   ` sashiko-bot
  2026-09-06 17:26 ` [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
                   ` (2 subsequent siblings)
  15 siblings, 1 reply; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Use xe_log_* helper to report correctable errors.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Cc: Raag Jadav <raag.jadav@intel.com>
---
 drivers/gpu/drm/xe/xe_ras.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index e93a989fc8f6..8cd6544b5336 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -464,8 +464,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 		if (!xe_ras_counter_is_valid(xe, &errors[id]))
 			continue;
 
-		xe_warn(xe, "[RAS]: %s %s detected\n",
-			comp_to_str(component), sev_to_str(severity));
+		xe_log_from(xe, ras_sev_to_cper_sev(severity),
+			    ras_comp_to_hw_sigid(component),
+			    component,
+			    &errors[id], sizeof(errors[id]),
+			    "error detected\n");
 
 		/* Send event once per component */
 		if (sent & BIT(component))
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 11/12] drm/xe/xe_ras: Report correctable errors using SIGID
  2026-09-06 17:26 ` [PATCH v3 11/12] drm/xe/xe_ras: Report correctable " Badal Nilawar
@ 2026-09-06 17:27   ` sashiko-bot
  0 siblings, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:27 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

New issues:
- [Medium] Raw hardware component ID passed to xe_log_from() instead of a structured log component identifier.

Pre-existing issues:
- [High] The function xe_emit_hardware_error_cper() contains an inverted condition that unconditionally skips hardware CPER emission.
--

commit 477ea5ac3298dd8da692c324d242eff3e7e49b28
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/xe_ras: Report correctable errors using SIGID

Use xe_log_* helper to report correctable errors.

> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index e93a989fc8f66..8cd6544b5336c 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -464,8 +464,11 @@ void xe_ras_counter_threshold_crossed(struct xe_device *xe,
>  		if (!xe_ras_counter_is_valid(xe, &errors[id]))
>  			continue;
>  
> -		xe_warn(xe, "[RAS]: %s %s detected\n",
> -			comp_to_str(component), sev_to_str(severity));
> +		xe_log_from(xe, ras_sev_to_cper_sev(severity),
> +			    ras_comp_to_hw_sigid(component),
> +			    component,

[Severity: Medium]
In drivers/gpu/drm/xe/xe_ras.c:xe_ras_counter_threshold_crossed(), does this
code pass the raw hardware component ID to xe_log_from() instead of a
structured log component identifier?

Passing the raw 8-bit component enum value instead of a properly formatted
value could trigger a runtime WARN trace when debug is enabled, and produce a
confusing "DRIVER? " prefix in the dmesg log instead of the correct hardware
component name.

> +			    &errors[id], sizeof(errors[id]),
> +			    "error detected\n");
>  
>  		/* Send event once per component */
>  		if (sent & BIT(component))

[Severity: High]
This is a pre-existing issue, but does xe_emit_hardware_error_cper() in
drivers/gpu/drm/xe/xe_cper.c skip CPER emission for valid hardware error
signatures?

drivers/gpu/drm/xe/xe_cper.c:xe_emit_hardware_error_cper() {
    ...
	if (!xe)
		return;

	if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
		return;

	if (!counter || !xe_ras_counter_is_valid(xe, counter))
		return;
    ...
}

It looks like the condition if ((int)sigid >= INTEL_SIGID_GPU_XE_HARDWARE_START)
might be inverted.  This appears to cause hardware RAS errors to silently fail
to generate CPER records when sigid is a valid hardware signature ID.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=11

^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (12 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 11/12] drm/xe/xe_ras: Report correctable " Badal Nilawar
@ 2026-09-06 17:26 ` Badal Nilawar
  2026-09-06 17:28   ` sashiko-bot
  2026-09-10  7:58   ` Raag Jadav
  2026-09-06 17:55 ` ✓ Xe.CI.BAT: success for Add CPER logging support for CRI (rev3) Patchwork
  2026-09-06 19:02 ` ✗ Xe.CI.FULL: failure " Patchwork
  15 siblings, 2 replies; 45+ messages in thread
From: Badal Nilawar @ 2026-09-06 17:26 UTC (permalink / raw)
  To: intel-xe
  Cc: anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio, raag.jadav,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

Emit cper record to trace buf.

Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Assisted-by: Copilot:claude-sonnet-4.6
---
 drivers/gpu/drm/xe/Makefile        |  3 +-
 drivers/gpu/drm/xe/xe_cper.c       |  4 +-
 drivers/gpu/drm/xe/xe_trace_cper.c |  9 ++++
 drivers/gpu/drm/xe/xe_trace_cper.h | 66 ++++++++++++++++++++++++++++++
 4 files changed, 80 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
 create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 06b064add77d..7831f7d94784 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -166,7 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
 xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
 xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
 
-xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o
+xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o \
+			      xe_trace_cper.o
 
 # graphics virtualization (SR-IOV) support
 xe-y += \
diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
index ebf4dc4ab2bb..0818ee6ae8ae 100644
--- a/drivers/gpu/drm/xe/xe_cper.c
+++ b/drivers/gpu/drm/xe/xe_cper.c
@@ -16,6 +16,7 @@
 #include "xe_printk.h"
 #include "xe_ras.h"
 #include "xe_ras_types.h"
+#include "xe_trace_cper.h"
 
 static const struct xe_platform_id_entry xe_platform_ids[] = {
 	/* 0x674C  platform/8086:674c */
@@ -169,7 +170,8 @@ static void xe_cper_record_emit(struct xe_device *xe, u8 severity,
 	if (einfo && einfo_len)
 		memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
 
-	/* TODO: Emit trace event */
+	trace_xe_error_cper(xe, &rhdr->platform_id, &sdesc->fru_id, severity,
+			    &rec->intel_hdr, total_len, (u8 *)rec);
 
 	kfree(rec);
 }
diff --git a/drivers/gpu/drm/xe/xe_trace_cper.c b/drivers/gpu/drm/xe/xe_trace_cper.c
new file mode 100644
index 000000000000..caea8783ab7c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_trace_cper.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __CHECKER__
+#define CREATE_TRACE_POINTS
+#include "xe_trace_cper.h"
+#endif
diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
new file mode 100644
index 000000000000..6d2dbf504888
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_trace_cper.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM xe
+
+#if !defined(_XE_TRACE_CPER_H_) || defined(TRACE_HEADER_MULTI_READ)
+#define _XE_TRACE_CPER_H_
+
+#include <linux/tracepoint.h>
+#include <linux/types.h>
+
+#include "xe_cper_types.h"
+#include "xe_device_types.h"
+
+#define __dev_name_xe(xe)	dev_name((xe)->drm.dev)
+
+TRACE_EVENT(xe_error_cper,
+	TP_PROTO(struct xe_device *xe,
+	    const guid_t *platform_id, const guid_t *fru_id,
+	    const u8 severity,
+	    const struct xe_cper_sec_intel_err_hdr *ihdr,
+	    u32 cper_len, const u8 *cper),
+	TP_ARGS(xe, platform_id, fru_id, severity, ihdr, cper_len, cper),
+
+	TP_STRUCT__entry(
+	    __string(dev, __dev_name_xe(xe))
+	    __array(char, platform_id, UUID_SIZE)
+	    __array(char, fru_id, UUID_SIZE)
+	    __field(u8, sev)
+	    __array(u8, ihdr_raw, sizeof(struct xe_cper_sec_intel_err_hdr))
+	    __field(u32, cper_len)
+	    __dynamic_array(u8, cper, cper_len)
+	    ),
+
+	TP_fast_assign(
+	    __assign_str(dev);
+	    __entry->sev = severity;
+	    memcpy(__entry->platform_id, platform_id, UUID_SIZE);
+	    memcpy(__entry->fru_id, fru_id, UUID_SIZE);
+	    memcpy(__entry->ihdr_raw, ihdr, sizeof(struct xe_cper_sec_intel_err_hdr));
+	    __entry->cper_len = cper_len;
+	    memcpy(__get_dynamic_array(cper), cper, cper_len);
+	    ),
+
+	TP_printk("dev=%s severity=%d platform_id=%pU fru_id=%pU "
+		"intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
+		__get_str(dev), __entry->sev,
+		__entry->platform_id, __entry->fru_id,
+		__print_hex(__entry->ihdr_raw,
+		    sizeof(struct xe_cper_sec_intel_err_hdr)),
+		__entry->cper_len,
+		__print_hex(__get_dynamic_array(cper),
+		    __entry->cper_len))
+);
+
+#endif
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
+#define TRACE_INCLUDE_FILE xe_trace_cper
+#include <trace/define_trace.h>
-- 
2.54.0


^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf
  2026-09-06 17:26 ` [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
@ 2026-09-06 17:28   ` sashiko-bot
  2026-09-10  7:58   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: sashiko-bot @ 2026-09-06 17:28 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Incorrect format specifier `%pU` is used to format `guid_t` variables, which will print them with the wrong byte order.
--

commit d2b3c6858920421ba035f9890d1e0ee71777bc35
Author: Badal Nilawar <badal.nilawar@intel.com>

drm/xe/cper: Emit cper record to trace buf

This commit emits CPER records to the trace buffer by adding a new
xe_error_cper tracepoint and calling it during xe_cper_record_emit().

> diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
> new file mode 100644
> index 0000000000000..6d2dbf5048884
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_trace_cper.h
[ ... ]
> +TRACE_EVENT(xe_error_cper,
> +	TP_PROTO(struct xe_device *xe,
> +	    const guid_t *platform_id, const guid_t *fru_id,
> +	    const u8 severity,
> +	    const struct xe_cper_sec_intel_err_hdr *ihdr,
> +	    u32 cper_len, const u8 *cper),
> +	TP_ARGS(xe, platform_id, fru_id, severity, ihdr, cper_len, cper),
[ ... ]
> +	TP_printk("dev=%s severity=%d platform_id=%pU fru_id=%pU "
> +		"intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",

[Severity: Low]
Will this print the GUIDs in the wrong byte order? The platform_id and fru_id
fields are populated from guid_t structures, which represent little-endian
GUIDs. The %pU format specifier expects a big-endian uuid_t, so it will output
the first three segments in reverse byte order.

Should this use %pUl instead to correctly format the little-endian guid_t?

> +		__get_str(dev), __entry->sev,
> +		__entry->platform_id, __entry->fru_id,
> +		__print_hex(__entry->ihdr_raw,
> +		    sizeof(struct xe_cper_sec_intel_err_hdr)),
> +		__entry->cper_len,
> +		__print_hex(__get_dynamic_array(cper),
> +		    __entry->cper_len))
> +);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260906172604.2215987-14-badal.nilawar@intel.com?part=12

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf
  2026-09-06 17:26 ` [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
  2026-09-06 17:28   ` sashiko-bot
@ 2026-09-10  7:58   ` Raag Jadav
  1 sibling, 0 replies; 45+ messages in thread
From: Raag Jadav @ 2026-09-10  7:58 UTC (permalink / raw)
  To: Badal Nilawar
  Cc: intel-xe, anshuman.gupta, rodrigo.vivi, daniele.ceraolospurio,
	riana.tauro, mallesh.koujalagi, aravind.iddamsetty,
	michal.wajdeczko, himal.prasad.ghimiray, arvind.yadav,
	syed.abdul.muqthyar.ahmed, nitin.r.gote

On Sun, Sep 06, 2026 at 10:56:17PM +0530, Badal Nilawar wrote:
> Emit cper record to trace buf.

Okay, so all the xe_log conversions are redundant until this is in place.
Please sequence them after this patch.

> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Assisted-by: Copilot:claude-sonnet-4.6
> ---
>  drivers/gpu/drm/xe/Makefile        |  3 +-
>  drivers/gpu/drm/xe/xe_cper.c       |  4 +-
>  drivers/gpu/drm/xe/xe_trace_cper.c |  9 ++++
>  drivers/gpu/drm/xe/xe_trace_cper.h | 66 ++++++++++++++++++++++++++++++
>  4 files changed, 80 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_trace_cper.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 06b064add77d..7831f7d94784 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -166,7 +166,8 @@ xe-$(CONFIG_HWMON) += xe_hwmon.o
>  xe-$(CONFIG_PERF_EVENTS) += xe_pmu.o
>  xe-$(CONFIG_CONFIGFS_FS) += xe_configfs.o
>  
> -xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o
> +xe-$(CONFIG_UEFI_CPER_X86) += xe_cper.o \
> +			      xe_trace_cper.o
>  
>  # graphics virtualization (SR-IOV) support
>  xe-y += \
> diff --git a/drivers/gpu/drm/xe/xe_cper.c b/drivers/gpu/drm/xe/xe_cper.c
> index ebf4dc4ab2bb..0818ee6ae8ae 100644
> --- a/drivers/gpu/drm/xe/xe_cper.c
> +++ b/drivers/gpu/drm/xe/xe_cper.c
> @@ -16,6 +16,7 @@
>  #include "xe_printk.h"
>  #include "xe_ras.h"
>  #include "xe_ras_types.h"
> +#include "xe_trace_cper.h"
>  
>  static const struct xe_platform_id_entry xe_platform_ids[] = {
>  	/* 0x674C  platform/8086:674c */
> @@ -169,7 +170,8 @@ static void xe_cper_record_emit(struct xe_device *xe, u8 severity,
>  	if (einfo && einfo_len)
>  		memcpy((u8 *)rec + sizeof(*rec), einfo, einfo_len);
>  
> -	/* TODO: Emit trace event */
> +	trace_xe_error_cper(xe, &rhdr->platform_id, &sdesc->fru_id, severity,
> +			    &rec->intel_hdr, total_len, (u8 *)rec);
>  
>  	kfree(rec);
>  }
> diff --git a/drivers/gpu/drm/xe/xe_trace_cper.c b/drivers/gpu/drm/xe/xe_trace_cper.c
> new file mode 100644
> index 000000000000..caea8783ab7c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_trace_cper.c
> @@ -0,0 +1,9 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef __CHECKER__
> +#define CREATE_TRACE_POINTS
> +#include "xe_trace_cper.h"
> +#endif

This looks like a redundant file that should not exist. Why not have the
TRACE_EVENT() as part of xe_trace.h and drop this?

Raag

> diff --git a/drivers/gpu/drm/xe/xe_trace_cper.h b/drivers/gpu/drm/xe/xe_trace_cper.h
> new file mode 100644
> index 000000000000..6d2dbf504888
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_trace_cper.h
> @@ -0,0 +1,66 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#undef TRACE_SYSTEM
> +#define TRACE_SYSTEM xe
> +
> +#if !defined(_XE_TRACE_CPER_H_) || defined(TRACE_HEADER_MULTI_READ)
> +#define _XE_TRACE_CPER_H_
> +
> +#include <linux/tracepoint.h>
> +#include <linux/types.h>
> +
> +#include "xe_cper_types.h"
> +#include "xe_device_types.h"
> +
> +#define __dev_name_xe(xe)	dev_name((xe)->drm.dev)
> +
> +TRACE_EVENT(xe_error_cper,
> +	TP_PROTO(struct xe_device *xe,
> +	    const guid_t *platform_id, const guid_t *fru_id,
> +	    const u8 severity,
> +	    const struct xe_cper_sec_intel_err_hdr *ihdr,
> +	    u32 cper_len, const u8 *cper),
> +	TP_ARGS(xe, platform_id, fru_id, severity, ihdr, cper_len, cper),
> +
> +	TP_STRUCT__entry(
> +	    __string(dev, __dev_name_xe(xe))
> +	    __array(char, platform_id, UUID_SIZE)
> +	    __array(char, fru_id, UUID_SIZE)
> +	    __field(u8, sev)
> +	    __array(u8, ihdr_raw, sizeof(struct xe_cper_sec_intel_err_hdr))
> +	    __field(u32, cper_len)
> +	    __dynamic_array(u8, cper, cper_len)
> +	    ),
> +
> +	TP_fast_assign(
> +	    __assign_str(dev);
> +	    __entry->sev = severity;
> +	    memcpy(__entry->platform_id, platform_id, UUID_SIZE);
> +	    memcpy(__entry->fru_id, fru_id, UUID_SIZE);
> +	    memcpy(__entry->ihdr_raw, ihdr, sizeof(struct xe_cper_sec_intel_err_hdr));
> +	    __entry->cper_len = cper_len;
> +	    memcpy(__get_dynamic_array(cper), cper, cper_len);
> +	    ),
> +
> +	TP_printk("dev=%s severity=%d platform_id=%pU fru_id=%pU "
> +		"intel_err_hdr_raw=%s cper_len=%u cper_raw=%s",
> +		__get_str(dev), __entry->sev,
> +		__entry->platform_id, __entry->fru_id,
> +		__print_hex(__entry->ihdr_raw,
> +		    sizeof(struct xe_cper_sec_intel_err_hdr)),
> +		__entry->cper_len,
> +		__print_hex(__get_dynamic_array(cper),
> +		    __entry->cper_len))
> +);
> +
> +#endif
> +
> +/* This part must be outside protection */
> +#undef TRACE_INCLUDE_PATH
> +#undef TRACE_INCLUDE_FILE
> +#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/xe
> +#define TRACE_INCLUDE_FILE xe_trace_cper
> +#include <trace/define_trace.h>
> -- 
> 2.54.0
> 

^ permalink raw reply	[flat|nested] 45+ messages in thread

* ✓ Xe.CI.BAT: success for Add CPER logging support for CRI (rev3)
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (13 preceding siblings ...)
  2026-09-06 17:26 ` [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
@ 2026-09-06 17:55 ` Patchwork
  2026-09-06 19:02 ` ✗ Xe.CI.FULL: failure " Patchwork
  15 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2026-09-06 17:55 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 1783 bytes --]

== Series Details ==

Series: Add CPER logging support for CRI (rev3)
URL   : https://patchwork.freedesktop.org/series/169692/
State : success

== Summary ==

CI Bug Log - changes from xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f_BAT -> xe-pw-169692v3_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-169692v3_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@xe_waitfence@engine:
    - bat-ptl-2:          [FAIL][1] ([Intel XE#9109]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/bat-ptl-2/igt@xe_waitfence@engine.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/bat-ptl-2/igt@xe_waitfence@engine.html
    - bat-wcl-1:          [FAIL][3] ([Intel XE#9103]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/bat-wcl-1/igt@xe_waitfence@engine.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/bat-wcl-1/igt@xe_waitfence@engine.html

  
  [Intel XE#9103]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9103
  [Intel XE#9109]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9109


Build changes
-------------

  * Linux: xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f -> xe-pw-169692v3

  IGT_9084: 9084
  xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f: 496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f
  xe-pw-169692v3: 169692v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/index.html

[-- Attachment #2: Type: text/html, Size: 2349 bytes --]

^ permalink raw reply	[flat|nested] 45+ messages in thread

* ✗ Xe.CI.FULL: failure for Add CPER logging support for CRI (rev3)
  2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
                   ` (14 preceding siblings ...)
  2026-09-06 17:55 ` ✓ Xe.CI.BAT: success for Add CPER logging support for CRI (rev3) Patchwork
@ 2026-09-06 19:02 ` Patchwork
  15 siblings, 0 replies; 45+ messages in thread
From: Patchwork @ 2026-09-06 19:02 UTC (permalink / raw)
  To: Badal Nilawar; +Cc: intel-xe

[-- Attachment #1: Type: text/plain, Size: 104553 bytes --]

== Series Details ==

Series: Add CPER logging support for CRI (rev3)
URL   : https://patchwork.freedesktop.org/series/169692/
State : failure

== Summary ==

CI Bug Log - changes from xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f_FULL -> xe-pw-169692v3_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-169692v3_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-169692v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (2 -> 2)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-169692v3_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_fb_coherency@memset-crc:
    - shard-lnl:          [PASS][1] -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_fb_coherency@memset-crc.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_fb_coherency@memset-crc.html

  
Known issues
------------

  Here are the changes found in xe-pw-169692v3_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [PASS][3] -> [FAIL][4] ([Intel XE#3718] / [Intel XE#6078])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2:
    - shard-bmg:          [PASS][5] -> [FAIL][6] ([Intel XE#6078])
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-4/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-dp-2.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-bmg:          NOTRUN -> [SKIP][7] ([Intel XE#2327]) +2 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][8] ([Intel XE#1407]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#7059] / [Intel XE#7085])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-bmg:          NOTRUN -> [SKIP][10] ([Intel XE#1124]) +6 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][11] ([Intel XE#1124]) +5 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][12] ([Intel XE#1428] / [Intel XE#7387])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#7679])
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_bw@connected-linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][14] ([Intel XE#7679]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_bw@connected-linear-tiling-4-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-2-displays-target-3840x2160p:
    - shard-bmg:          NOTRUN -> [SKIP][15] ([Intel XE#367])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_bw@linear-tiling-2-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][16] ([Intel XE#2887]) +7 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#2669] / [Intel XE#7389]) +2 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-a-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][18] ([Intel XE#3432])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#2887]) +8 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_chamelium_color@ctm-0-50:
    - shard-bmg:          NOTRUN -> [SKIP][20] ([Intel XE#2325] / [Intel XE#7358])
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_chamelium_color@ctm-0-50.html

  * igt@kms_chamelium_color@ctm-red-to-blue:
    - shard-lnl:          NOTRUN -> [SKIP][21] ([Intel XE#306] / [Intel XE#7358]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_chamelium_color@ctm-red-to-blue.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d:
    - shard-bmg:          NOTRUN -> [SKIP][22] ([Intel XE#7358])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_chamelium_color_pipeline@plane-lut1d.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#373]) +4 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-bmg:          NOTRUN -> [SKIP][24] ([Intel XE#2252]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_chamelium_sharpness_filter@filter-basic:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#6507])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_chamelium_sharpness_filter@filter-basic.html

  * igt@kms_color@deep-color:
    - shard-lnl:          [PASS][26] -> [SKIP][27] ([Intel XE#1511] / [Intel XE#3297])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_color@deep-color.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_color@deep-color.html

  * igt@kms_color@legacy-gamma-reset:
    - shard-lnl:          [PASS][28] -> [SKIP][29] ([Intel XE#3297])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_color@legacy-gamma-reset.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_color@legacy-gamma-reset.html

  * igt@kms_color_pipeline@plane-ctm3x4:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#7006])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_color_pipeline@plane-ctm3x4.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-a-plane-1:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#6969]) +7 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-a-plane-1.html

  * igt@kms_color_pipeline@plane-lut3d-green-only@pipe-c-plane-2:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#6969] / [Intel XE#7006])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_color_pipeline@plane-lut3d-green-only@pipe-c-plane-2.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-bmg:          NOTRUN -> [FAIL][33] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) +1 other test fail
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_content_protection@uevent:
    - shard-lnl:          NOTRUN -> [SKIP][34] ([Intel XE#7642]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1424])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-onscreen-32x10:
    - shard-bmg:          NOTRUN -> [SKIP][36] ([Intel XE#2320]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_cursor_crc@cursor-onscreen-32x10.html

  * igt@kms_cursor_crc@cursor-tearing-position-change:
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#9125]) +32 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_cursor_crc@cursor-tearing-position-change.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic:
    - shard-bmg:          [PASS][39] -> [FAIL][40] ([Intel XE#7809])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1508])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
    - shard-bmg:          NOTRUN -> [SKIP][42] ([Intel XE#1508])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#8265])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_dsc@dsc-fractional-bpp-with-bpc-bigjoiner.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-bmg:          NOTRUN -> [SKIP][44] ([Intel XE#4422] / [Intel XE#7442])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-bmg:          NOTRUN -> [SKIP][45] ([Intel XE#4156] / [Intel XE#7425])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_feature_discovery@display-3x:
    - shard-lnl:          NOTRUN -> [SKIP][46] ([Intel XE#703] / [Intel XE#7448])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_feature_discovery@display-3x.html
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2373] / [Intel XE#7448])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@dsc:
    - shard-bmg:          NOTRUN -> [SKIP][48] ([Intel XE#8586])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_feature_discovery@dsc.html

  * igt@kms_feature_discovery@hdr:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#8586])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_feature_discovery@hdr.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1421]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_flip@2x-blocking-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - shard-lnl:          [PASS][51] -> [SKIP][52] ([Intel XE#2482])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_flip@basic-flip-vs-modeset.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling:
    - shard-lnl:          [PASS][53] -> [SKIP][54] ([Intel XE#1745] / [Intel XE#9144])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#1745] / [Intel XE#9144])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#7178] / [Intel XE#7351]) +4 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#7178] / [Intel XE#7351])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          NOTRUN -> [SKIP][59] ([Intel XE#2311]) +18 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#6312] / [Intel XE#651]) +7 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][61] ([Intel XE#7061])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][62] ([Intel XE#4141]) +7 other tests skip
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render:
    - shard-lnl:          [PASS][63] -> [SKIP][64] ([Intel XE#7779])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][65] ([Intel XE#7779]) +24 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#6312]) +7 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][67] ([Intel XE#2548] / [Intel XE#7779]) +18 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#7865]) +10 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#7061]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsrhdr-argb161616f-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-lnl:          [PASS][71] -> [SKIP][72] ([Intel XE#2548] / [Intel XE#7779]) +8 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#656] / [Intel XE#7905]) +17 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-shrfb-msflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#7905]) +26 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][75] ([Intel XE#2313]) +26 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#1470])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#1503])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_invalid_mode@bad-vsync-end:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#2568])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_invalid_mode@bad-vsync-end.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#7086] / [Intel XE#7390])
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-bmg:          NOTRUN -> [SKIP][80] ([Intel XE#6911] / [Intel XE#7466])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_lease@lease-unleased-crtc:
    - shard-lnl:          [PASS][81] -> [SKIP][82] ([Intel XE#9125]) +24 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_lease@lease-unleased-crtc.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_lease@lease-unleased-crtc.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-lnl:          NOTRUN -> [SKIP][83] ([Intel XE#8348])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-bmg:          NOTRUN -> [SKIP][84] ([Intel XE#4329] / [Intel XE#6912] / [Intel XE#7375])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][85] ([Intel XE#7283]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_plane@pixel-format-4-tiled-dg2-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#7283]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@planar-pixel-format-settings:
    - shard-lnl:          [PASS][87] -> [SKIP][88] ([Intel XE#7780] / [Intel XE#9125])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_plane@planar-pixel-format-settings.html
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_plane@planar-pixel-format-settings.html

  * igt@kms_plane@plane-position-covered:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#9128]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_plane@plane-position-covered.html

  * igt@kms_plane_lowres@tiling-x@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#599] / [Intel XE#7382]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_plane_lowres@tiling-x@pipe-b-edp-1.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][91] ([Intel XE#599])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_plane_lowres@tiling-y.html
    - shard-bmg:          NOTRUN -> [SKIP][92] ([Intel XE#2393])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#4596] / [Intel XE#5854])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_plane_multiple@2x-tiling-y.html
    - shard-bmg:          NOTRUN -> [SKIP][94] ([Intel XE#5021] / [Intel XE#7377])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-lnl:          [PASS][95] -> [SKIP][96] ([Intel XE#2763] / [Intel XE#6886]) +5 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c:
    - shard-lnl:          [PASS][97] -> [SKIP][98] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) +5 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c.html
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#2763] / [Intel XE#6886]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-bmg:          NOTRUN -> [SKIP][101] ([Intel XE#7376] / [Intel XE#7760] / [Intel XE#870])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc5-pageflip-negative:
    - shard-lnl:          [PASS][102] -> [SKIP][103] ([Intel XE#6927] / [Intel XE#8854])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_pm_dc@dc5-pageflip-negative.html
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_pm_dc@dc5-pageflip-negative.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-bmg:          NOTRUN -> [SKIP][104] ([Intel XE#7794]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_rpm@drm-resources-equal:
    - shard-lnl:          [PASS][105] -> [SKIP][106] ([Intel XE#7106])
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_pm_rpm@drm-resources-equal.html
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_pm_rpm@drm-resources-equal.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-lnl:          NOTRUN -> [SKIP][107] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@system-suspend-modeset:
    - shard-bmg:          [PASS][109] -> [ABORT][110] ([Intel XE#9093])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-2/igt@kms_pm_rpm@system-suspend-modeset.html
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-1/igt@kms_pm_rpm@system-suspend-modeset.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#1489])
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][113] ([Intel XE#4608])
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][114] ([Intel XE#4608] / [Intel XE#7304])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#2893] / [Intel XE#7304])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][116] ([Intel XE#1489]) +3 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          [PASS][117] -> [SKIP][118] ([Intel XE#1489])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#1128] / [Intel XE#7413])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][120] ([Intel XE#2234] / [Intel XE#2850]) +4 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@kms_psr@fbc-pr-primary-blt.html

  * igt@kms_psr@fbc-psr2-primary-page-flip:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#1406] / [Intel XE#7345])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-page-flip.html

  * igt@kms_psr@fbc-psr2-primary-page-flip@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][122] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_psr@fbc-psr2-primary-page-flip@edp-1.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-lnl:          NOTRUN -> [SKIP][123] ([Intel XE#2850] / [Intel XE#929]) +3 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@pr-sprite-render:
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#1406])
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_psr@pr-sprite-render.html

  * igt@kms_psr@psr-dpms:
    - shard-lnl:          [PASS][125] -> [SKIP][126] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_psr@psr-dpms.html
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr@psr-dpms.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_sharpness_filter@invalid-filter-with-plane:
    - shard-bmg:          NOTRUN -> [SKIP][128] ([Intel XE#6503])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_sharpness_filter@invalid-filter-with-plane.html

  * igt@kms_vrr@flip-dpms:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#1499])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@kms_vrr@flip-dpms.html

  * igt@sriov_basic@pf-unbind-with-vf-probed:
    - shard-lnl:          NOTRUN -> [SKIP][130] ([Intel XE#8866])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@sriov_basic@pf-unbind-with-vf-probed.html

  * igt@xe_ccs@vm-bind-fault-mode-decompress:
    - shard-lnl:          NOTRUN -> [SKIP][131] ([Intel XE#7644])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@xe_ccs@vm-bind-fault-mode-decompress.html

  * igt@xe_evict@evict-beng-large-external-cm:
    - shard-lnl:          NOTRUN -> [SKIP][132] ([Intel XE#6540] / [Intel XE#688]) +7 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_evict@evict-beng-large-external-cm.html

  * igt@xe_evict@evict-small-external-multi-queue-cm:
    - shard-bmg:          NOTRUN -> [SKIP][133] ([Intel XE#8370])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@xe_evict@evict-small-external-multi-queue-cm.html

  * igt@xe_exec_balancer@many-cm-parallel-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#7482]) +13 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@xe_exec_balancer@many-cm-parallel-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][135] ([Intel XE#1392]) +6 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][136] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate.html

  * igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][137] ([Intel XE#8374]) +6 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_exec_fault_mode@many-multi-queue-rebind-prefetch.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm:
    - shard-lnl:          NOTRUN -> [SKIP][138] ([Intel XE#8374]) +6 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_exec_fault_mode@twice-multi-queue-userptr-imm.html

  * igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][139] ([Intel XE#8364]) +17 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_exec_multi_queue@many-execs-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][140] ([Intel XE#8364]) +22 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_reset@multi-queue-close-execqueues:
    - shard-bmg:          NOTRUN -> [SKIP][141] ([Intel XE#8369]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_exec_reset@multi-queue-close-execqueues.html

  * igt@xe_exec_reset@multi-queue-close-fd:
    - shard-lnl:          NOTRUN -> [SKIP][142] ([Intel XE#8369])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_exec_reset@multi-queue-close-fd.html

  * igt@xe_exec_system_allocator@many-large-mmap-nomemset:
    - shard-bmg:          [PASS][143] -> [INCOMPLETE][144] ([Intel XE#8159])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-9/igt@xe_exec_system_allocator@many-large-mmap-nomemset.html
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-2/igt@xe_exec_system_allocator@many-large-mmap-nomemset.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma:
    - shard-lnl:          NOTRUN -> [SKIP][145] ([Intel XE#6196])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-multi-vma.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr:
    - shard-bmg:          NOTRUN -> [SKIP][146] ([Intel XE#8378]) +3 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-mixed-fd-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-rebind-err:
    - shard-lnl:          NOTRUN -> [SKIP][147] ([Intel XE#8378]) +7 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_exec_threads@threads-multi-queue-rebind-err.html

  * igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode:
    - shard-bmg:          [PASS][148] -> [ABORT][149] ([Intel XE#8007])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-10/igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-7/igt@xe_fault_injection@inject-fault-probe-function-guc_wait_ucode.html

  * igt@xe_madvise@atomic-device:
    - shard-lnl:          NOTRUN -> [SKIP][150] ([Intel XE#7980])
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_madvise@atomic-device.html

  * igt@xe_multigpu_svm@mgpu-pagefault-conflict:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#6964]) +3 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_multigpu_svm@mgpu-pagefault-conflict.html

  * igt@xe_multigpu_svm@mgpu-pagefault-prefetch:
    - shard-bmg:          NOTRUN -> [SKIP][152] ([Intel XE#6964])
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_multigpu_svm@mgpu-pagefault-prefetch.html

  * igt@xe_page_reclaim@basic-mixed:
    - shard-lnl:          NOTRUN -> [SKIP][153] ([Intel XE#7793]) +1 other test skip
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_page_reclaim@basic-mixed.html

  * igt@xe_page_reclaim@prl-invalidate-full:
    - shard-bmg:          NOTRUN -> [SKIP][154] ([Intel XE#7793])
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_page_reclaim@prl-invalidate-full.html

  * igt@xe_pat@pat-index-xelpg:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#7590] / [Intel XE#979])
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_pat@pat-index-xelpg.html

  * igt@xe_pat@xa-app-transient-media-off:
    - shard-bmg:          NOTRUN -> [SKIP][156] ([Intel XE#7590])
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@xe_pat@xa-app-transient-media-off.html

  * igt@xe_pm@s3-d3cold-basic-exec:
    - shard-lnl:          NOTRUN -> [SKIP][157] ([Intel XE#2284] / [Intel XE#366] / [Intel XE#7370])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@xe_pm@s3-d3cold-basic-exec.html

  * igt@xe_pm@s3-vm-bind-unbind-all:
    - shard-lnl:          NOTRUN -> [SKIP][158] ([Intel XE#584] / [Intel XE#7369])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_pm@s3-vm-bind-unbind-all.html

  * igt@xe_pm@vram-d3cold-threshold:
    - shard-lnl:          NOTRUN -> [SKIP][159] ([Intel XE#579] / [Intel XE#7329] / [Intel XE#7456])
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_pm@vram-d3cold-threshold.html

  * igt@xe_pm_residency@aspm_link_residency:
    - shard-lnl:          NOTRUN -> [SKIP][160] ([Intel XE#7271])
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@xe_pm_residency@aspm_link_residency.html

  * igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
    - shard-bmg:          NOTRUN -> [SKIP][161] ([Intel XE#4733] / [Intel XE#7417]) +1 other test skip
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-bmg:          NOTRUN -> [SKIP][162] ([Intel XE#944])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-lnl:          NOTRUN -> [SKIP][163] ([Intel XE#944]) +2 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_sriov_admin@sched-priority-write-readback-vfs-disabled:
    - shard-lnl:          NOTRUN -> [SKIP][164] ([Intel XE#7174]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@xe_sriov_admin@sched-priority-write-readback-vfs-disabled.html

  * igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs:
    - shard-lnl:          NOTRUN -> [SKIP][165] ([Intel XE#4130] / [Intel XE#7366])
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_sriov_auto_provisioning@selfconfig-reprovision-increase-numvfs.html

  * igt@xe_sriov_vram@vf-access-provisioned:
    - shard-lnl:          NOTRUN -> [SKIP][166] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422])
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_sriov_vram@vf-access-provisioned.html

  * igt@xe_vm@overcommit-fault-vram-lr:
    - shard-lnl:          NOTRUN -> [SKIP][167] ([Intel XE#7892])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-7/igt@xe_vm@overcommit-fault-vram-lr.html

  
#### Possible fixes ####

  * igt@core_hotunplug@hotrebind-lateclose:
    - shard-bmg:          [ABORT][168] ([Intel XE#8007]) -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-8/igt@core_hotunplug@hotrebind-lateclose.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@core_hotunplug@hotrebind-lateclose.html

  * igt@kms_flip@busy-flip:
    - shard-lnl:          [SKIP][170] ([Intel XE#2482]) -> [PASS][171] +4 other tests pass
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_flip@busy-flip.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_flip@busy-flip.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][172] ([Intel XE#7779]) -> [PASS][173]
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
    - shard-lnl:          [SKIP][174] ([Intel XE#2548] / [Intel XE#7779]) -> [PASS][175] +9 other tests pass
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-bmg:          [SKIP][176] ([Intel XE#1503]) -> [PASS][177]
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-1/igt@kms_hdr@invalid-hdr.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-2/igt@kms_hdr@invalid-hdr.html

  * igt@kms_invalid_mode@zero-vdisplay:
    - shard-lnl:          [SKIP][178] ([Intel XE#2568]) -> [PASS][179]
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_invalid_mode@zero-vdisplay.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_invalid_mode@zero-vdisplay.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-lnl:          [SKIP][180] ([Intel XE#9128]) -> [PASS][181]
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
    - shard-lnl:          [SKIP][182] ([Intel XE#2763] / [Intel XE#6886]) -> [PASS][183] +3 other tests pass
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling:
    - shard-lnl:          [SKIP][184] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) -> [PASS][185] +3 other tests pass
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-lnl:          [SKIP][186] ([Intel XE#870]) -> [PASS][187]
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_pm_backlight@fade-with-dpms.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-lnl:          [SKIP][188] ([Intel XE#1439] / [Intel XE#7402] / [Intel XE#836]) -> [PASS][189]
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_psr@psr-no-drrs:
    - shard-lnl:          [SKIP][190] ([Intel XE#2850] / [Intel XE#929]) -> [PASS][191] +1 other test pass
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_psr@psr-no-drrs.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_psr@psr-no-drrs.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-lnl:          [SKIP][192] ([Intel XE#7795]) -> [PASS][193]
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-180:
    - shard-lnl:          [SKIP][194] ([Intel XE#9125]) -> [PASS][195] +24 other tests pass
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_rotation_crc@primary-x-tiled-reflect-x-180.html

  * igt@xe_exec_reset@gt-stress-reset-concurrent-submit:
    - shard-bmg:          [DMESG-WARN][196] ([Intel XE#8649] / [Intel XE#8652]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-6/igt@xe_exec_reset@gt-stress-reset-concurrent-submit.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-3/igt@xe_exec_reset@gt-stress-reset-concurrent-submit.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-bmg:          [FAIL][198] ([Intel XE#9096]) -> [PASS][199]
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-7/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-4/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_module_load@load:
    - shard-bmg:          ([PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [PASS][209], [PASS][210], [PASS][211], [SKIP][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225]) ([Intel XE#2457] / [Intel XE#7405]) -> ([PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234], [PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-3/igt@xe_module_load@load.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-8/igt@xe_module_load@load.html
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-9/igt@xe_module_load@load.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-9/igt@xe_module_load@load.html
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-8/igt@xe_module_load@load.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-6/igt@xe_module_load@load.html
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-6/igt@xe_module_load@load.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-6/igt@xe_module_load@load.html
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-7/igt@xe_module_load@load.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-1/igt@xe_module_load@load.html
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-1/igt@xe_module_load@load.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-1/igt@xe_module_load@load.html
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-1/igt@xe_module_load@load.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-10/igt@xe_module_load@load.html
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-10/igt@xe_module_load@load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-4/igt@xe_module_load@load.html
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-4/igt@xe_module_load@load.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-9/igt@xe_module_load@load.html
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-10/igt@xe_module_load@load.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-2/igt@xe_module_load@load.html
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-2/igt@xe_module_load@load.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-7/igt@xe_module_load@load.html
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-3/igt@xe_module_load@load.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-3/igt@xe_module_load@load.html
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-5/igt@xe_module_load@load.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-5/igt@xe_module_load@load.html
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-4/igt@xe_module_load@load.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@xe_module_load@load.html
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@xe_module_load@load.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-8/igt@xe_module_load@load.html
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-10/igt@xe_module_load@load.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-5/igt@xe_module_load@load.html
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-5/igt@xe_module_load@load.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-3/igt@xe_module_load@load.html
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-3/igt@xe_module_load@load.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-10/igt@xe_module_load@load.html
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-10/igt@xe_module_load@load.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-4/igt@xe_module_load@load.html
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_module_load@load.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_module_load@load.html
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-2/igt@xe_module_load@load.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-2/igt@xe_module_load@load.html
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-3/igt@xe_module_load@load.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-5/igt@xe_module_load@load.html
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-6/igt@xe_module_load@load.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-6/igt@xe_module_load@load.html
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-7/igt@xe_module_load@load.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-7/igt@xe_module_load@load.html
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-1/igt@xe_module_load@load.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-1/igt@xe_module_load@load.html
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-2/igt@xe_module_load@load.html

  
#### Warnings ####

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-lnl:          [SKIP][251] ([Intel XE#3279]) -> [SKIP][252] ([Intel XE#9125])
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_atomic_transition@plane-all-modeset-transition.html
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-lnl:          [SKIP][253] ([Intel XE#1407]) -> [SKIP][254] ([Intel XE#9125]) +3 other tests skip
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-lnl:          [SKIP][255] ([Intel XE#9125]) -> [SKIP][256] ([Intel XE#7059] / [Intel XE#7085])
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-lnl:          [SKIP][257] ([Intel XE#7059] / [Intel XE#7085]) -> [SKIP][258] ([Intel XE#9125])
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html
   [258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-lnl:          [SKIP][259] ([Intel XE#9125]) -> [SKIP][260] ([Intel XE#1407]) +1 other test skip
   [259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
   [260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
    - shard-lnl:          [SKIP][261] ([Intel XE#1124]) -> [SKIP][262] ([Intel XE#9125]) +5 other tests skip
   [261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
   [262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-lnl:          [SKIP][263] ([Intel XE#9125]) -> [SKIP][264] ([Intel XE#1477] / [Intel XE#7361])
   [263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
   [264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-lnl:          [SKIP][265] ([Intel XE#9125]) -> [SKIP][266] ([Intel XE#1124]) +4 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
   [266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p:
    - shard-lnl:          [SKIP][267] ([Intel XE#7679]) -> [SKIP][268] ([Intel XE#9125])
   [267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html
   [268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_bw@connected-linear-tiling-3-displays-target-2560x1440p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p:
    - shard-lnl:          [SKIP][269] ([Intel XE#8365]) -> [SKIP][270] ([Intel XE#9125])
   [269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html
   [270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_bw@connected-linear-tiling-4-displays-target-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p:
    - shard-lnl:          [SKIP][271] ([Intel XE#9125]) -> [SKIP][272] ([Intel XE#8365]) +1 other test skip
   [271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html
   [272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_bw@connected-linear-tiling-4-displays-target-2160x1440p.html

  * igt@kms_bw@linear-tiling-2-displays-target-2560x1440p:
    - shard-lnl:          [SKIP][273] ([Intel XE#9125]) -> [SKIP][274] ([Intel XE#367])
   [273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_bw@linear-tiling-2-displays-target-2560x1440p.html
   [274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_bw@linear-tiling-2-displays-target-2560x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-target-3840x2160p:
    - shard-lnl:          [SKIP][275] ([Intel XE#367]) -> [SKIP][276] ([Intel XE#9125])
   [275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html
   [276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          [SKIP][277] ([Intel XE#2887]) -> [SKIP][278] ([Intel XE#9125]) +7 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
   [278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-lnl:          [SKIP][279] ([Intel XE#9125]) -> [SKIP][280] ([Intel XE#2669] / [Intel XE#7389])
   [279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-lnl:          [SKIP][281] ([Intel XE#9125]) -> [SKIP][282] ([Intel XE#3432])
   [281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs:
    - shard-lnl:          [SKIP][283] ([Intel XE#3432]) -> [SKIP][284] ([Intel XE#9125])
   [283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html
   [284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
    - shard-lnl:          [SKIP][285] ([Intel XE#9125]) -> [SKIP][286] ([Intel XE#2887]) +6 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
   [286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html

  * igt@kms_color_pipeline@plane-lut3d-green-only:
    - shard-lnl:          [SKIP][287] ([Intel XE#7006]) -> [SKIP][288] ([Intel XE#6969] / [Intel XE#7006])
   [287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_color_pipeline@plane-lut3d-green-only.html
   [288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_color_pipeline@plane-lut3d-green-only.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-lnl:          [SKIP][289] ([Intel XE#9125]) -> [SKIP][290] ([Intel XE#6974])
   [289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_content_protection@dp-mst-type-0-hdcp14.html
   [290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_content_protection@lic-type-1:
    - shard-lnl:          [SKIP][291] ([Intel XE#9125]) -> [SKIP][292] ([Intel XE#7642]) +1 other test skip
   [291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_content_protection@lic-type-1.html
   [292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@srm:
    - shard-lnl:          [SKIP][293] ([Intel XE#7642]) -> [SKIP][294] ([Intel XE#9125])
   [293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_content_protection@srm.html
   [294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-onscreen-128x42:
    - shard-lnl:          [SKIP][295] ([Intel XE#9125]) -> [SKIP][296] ([Intel XE#1424]) +2 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_cursor_crc@cursor-onscreen-128x42.html
   [296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_cursor_crc@cursor-onscreen-128x42.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-lnl:          [SKIP][297] ([Intel XE#9125]) -> [SKIP][298] ([Intel XE#2321] / [Intel XE#7355])
   [297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_cursor_crc@cursor-random-512x512.html
   [298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-256x85:
    - shard-lnl:          [SKIP][299] ([Intel XE#1424]) -> [SKIP][300] ([Intel XE#9125])
   [299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html
   [300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-lnl:          [SKIP][301] ([Intel XE#2321] / [Intel XE#7355]) -> [SKIP][302] ([Intel XE#9125])
   [301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
   [302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          [SKIP][303] ([Intel XE#9125]) -> [SKIP][304] ([Intel XE#309] / [Intel XE#7343]) +2 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
   [304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-lnl:          [SKIP][305] ([Intel XE#323] / [Intel XE#6035]) -> [SKIP][306] ([Intel XE#9125])
   [305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-lnl:          [SKIP][307] ([Intel XE#4354] / [Intel XE#7386]) -> [SKIP][308] ([Intel XE#9125])
   [307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_dp_link_training@uhbr-mst.html
   [308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-lnl:          [SKIP][309] ([Intel XE#9125]) -> [SKIP][310] ([Intel XE#8265]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html
   [310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner:
    - shard-lnl:          [SKIP][311] ([Intel XE#8265]) -> [SKIP][312] ([Intel XE#9125]) +1 other test skip
   [311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html
   [312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling:
    - shard-lnl:          [SKIP][313] ([Intel XE#1745] / [Intel XE#9144]) -> [SKIP][314] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
   [313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html
   [314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-32bpp-linear-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][315] ([Intel XE#6312]) -> [SKIP][316] ([Intel XE#7779]) +4 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html
   [316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc:
    - shard-lnl:          [SKIP][317] ([Intel XE#7061] / [Intel XE#7356]) -> [SKIP][318] ([Intel XE#7779]) +2 other tests skip
   [317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc.html
   [318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-mmap-wc:
    - shard-lnl:          [SKIP][319] ([Intel XE#7779]) -> [SKIP][320] ([Intel XE#7061]) +1 other test skip
   [319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-mmap-wc.html
   [320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@drrshdr-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          [SKIP][321] ([Intel XE#656] / [Intel XE#7905]) -> [SKIP][322] ([Intel XE#2548] / [Intel XE#7779]) +20 other tests skip
   [321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html
   [322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy:
    - shard-lnl:          [SKIP][323] ([Intel XE#6312] / [Intel XE#651]) -> [SKIP][324] ([Intel XE#2548] / [Intel XE#7779]) +6 other tests skip
   [323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html
   [324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrs-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear:
    - shard-lnl:          [SKIP][325] ([Intel XE#2548] / [Intel XE#7779]) -> [SKIP][326] ([Intel XE#6312] / [Intel XE#651]) +8 other tests skip
   [325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html
   [326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrs-tiling-linear.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-onoff:
    - shard-lnl:          [SKIP][327] ([Intel XE#7779]) -> [SKIP][328] ([Intel XE#6312]) +8 other tests skip
   [327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-onoff.html
   [328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcdrrshdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][329] ([Intel XE#7779]) -> [SKIP][330] ([Intel XE#7865]) +12 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-lnl:          [SKIP][331] ([Intel XE#2548] / [Intel XE#7779]) -> [SKIP][332] ([Intel XE#1469] / [Intel XE#7399])
   [331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-lnl:          [SKIP][333] ([Intel XE#7865]) -> [SKIP][334] ([Intel XE#7779]) +17 other tests skip
   [333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc.html
   [334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff:
    - shard-lnl:          [SKIP][335] ([Intel XE#7905]) -> [SKIP][336] ([Intel XE#7779]) +20 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html
   [336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt:
    - shard-lnl:          [SKIP][337] ([Intel XE#2548] / [Intel XE#7779]) -> [SKIP][338] ([Intel XE#656] / [Intel XE#7905]) +20 other tests skip
   [337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html
   [338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move:
    - shard-lnl:          [SKIP][339] ([Intel XE#7779]) -> [SKIP][340] ([Intel XE#7905]) +21 other tests skip
   [339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move.html
   [340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-blt:
    - shard-lnl:          [SKIP][341] ([Intel XE#7061]) -> [SKIP][342] ([Intel XE#7779]) +2 other tests skip
   [341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-blt.html
   [342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_frontbuffer_tracking@psrhdr-argb161616f-draw-blt.html

  * igt@kms_hdr@static-toggle:
    - shard-lnl:          [SKIP][343] ([Intel XE#9125]) -> [SKIP][344] ([Intel XE#1503])
   [343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_hdr@static-toggle.html
   [344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_hdr@static-toggle.html

  * igt@kms_plane_lowres@tiling-x:
    - shard-lnl:          [SKIP][345] ([Intel XE#9125]) -> [SKIP][346] ([Intel XE#599] / [Intel XE#7382])
   [345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_plane_lowres@tiling-x.html
   [346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_plane_lowres@tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-lnl:          [SKIP][347] ([Intel XE#9125]) -> [SKIP][348] ([Intel XE#4596] / [Intel XE#5854])
   [347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_plane_multiple@2x-tiling-x.html
   [348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-lnl:          [SKIP][349] ([Intel XE#2763] / [Intel XE#6886] / [Intel XE#7687] / [Intel XE#9125]) -> [SKIP][350] ([Intel XE#2763] / [Intel XE#6886]) +1 other test skip
   [349]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
   [350]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [SKIP][351] ([Intel XE#7778]) -> [FAIL][352] ([Intel XE#2029] / [Intel XE#7395])
   [351]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_pm_dc@deep-pkgc.html
   [352]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-lnl:          [SKIP][353] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304]) -> [SKIP][354] ([Intel XE#1489]) +1 other test skip
   [353]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [354]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-lnl:          [SKIP][355] ([Intel XE#1489]) -> [SKIP][356] ([Intel XE#2893] / [Intel XE#7304]) +2 other tests skip
   [355]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html
   [356]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
    - shard-lnl:          [SKIP][357] ([Intel XE#2893] / [Intel XE#7304]) -> [SKIP][358] ([Intel XE#1489]) +1 other test skip
   [357]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html
   [358]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-lnl:          [SKIP][359] ([Intel XE#1122] / [Intel XE#7429]) -> [SKIP][360] ([Intel XE#1128] / [Intel XE#7413])
   [359]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_psr2_su@page_flip-p010.html
   [360]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@pr-basic:
    - shard-lnl:          [SKIP][361] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][362] ([Intel XE#1406]) +3 other tests skip
   [361]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_psr@pr-basic.html
   [362]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_psr@pr-basic.html

  * igt@kms_psr@pr-cursor-plane-move:
    - shard-lnl:          [SKIP][363] ([Intel XE#1406]) -> [SKIP][364] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [363]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_psr@pr-cursor-plane-move.html
   [364]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_psr@pr-cursor-plane-move.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-lnl:          [SKIP][365] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) -> [SKIP][366] ([Intel XE#9125])
   [365]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
   [366]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-lnl:          [SKIP][367] ([Intel XE#1127] / [Intel XE#5813]) -> [SKIP][368] ([Intel XE#9125])
   [367]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [368]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-lnl:          [SKIP][369] ([Intel XE#9125]) -> [SKIP][370] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342])
   [369]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [370]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][371] ([Intel XE#2426] / [Intel XE#5848]) -> [SKIP][372] ([Intel XE#2509] / [Intel XE#7437])
   [371]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [372]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_exec_reset@gt-reset-fault-injection:
    - shard-bmg:          [ABORT][373] ([Intel XE#9131] / [Intel XE#9145]) -> [DMESG-WARN][374] ([Intel XE#9130])
   [373]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-3/igt@xe_exec_reset@gt-reset-fault-injection.html
   [374]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_exec_reset@gt-reset-fault-injection.html
    - shard-lnl:          [ABORT][375] ([Intel XE#9140] / [Intel XE#9145]) -> [ABORT][376] ([Intel XE#9145])
   [375]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-3/igt@xe_exec_reset@gt-reset-fault-injection.html
   [376]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-2/igt@xe_exec_reset@gt-reset-fault-injection.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add:
    - shard-bmg:          [ABORT][377] ([Intel XE#8007]) -> [SKIP][378] ([Intel XE#6281] / [Intel XE#7426])
   [377]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-5/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html
   [378]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-9/igt@xe_fault_injection@exec-queue-create-fail-xe_pxp_exec_queue_add.html

  * igt@xe_wedged@basic-wedged:
    - shard-lnl:          [DMESG-WARN][379] ([Intel XE#8963]) -> [ABORT][380] ([Intel XE#8963])
   [379]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-lnl-1/igt@xe_wedged@basic-wedged.html
   [380]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-lnl-1/igt@xe_wedged@basic-wedged.html

  * igt@xe_wedged@wedged-at-any-timeout:
    - shard-bmg:          [DMESG-WARN][381] ([Intel XE#8963]) -> [ABORT][382] ([Intel XE#8007] / [Intel XE#8963])
   [381]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f/shard-bmg-1/igt@xe_wedged@wedged-at-any-timeout.html
   [382]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/shard-bmg-2/igt@xe_wedged@wedged-at-any-timeout.html

  
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1428
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1470]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1470
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1511]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1511
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2393]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2393
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2457
  [Intel XE#2482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2482
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2548]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2548
  [Intel XE#2568]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2568
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#3279]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3279
  [Intel XE#3297]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3297
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4156]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4156
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
  [Intel XE#6035]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6035
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6281]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6281
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
  [Intel XE#6507]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6507
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6911]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6911
  [Intel XE#6912]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6912
  [Intel XE#6927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6927
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6969]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6969
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7006]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7006
  [Intel XE#703]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/703
  [Intel XE#7059]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7059
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7085]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7085
  [Intel XE#7086]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7086
  [Intel XE#7106]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7106
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7271
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7329
  [Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7366
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7375
  [Intel XE#7376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7376
  [Intel XE#7377]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7377
  [Intel XE#7382]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7382
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7386]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7386
  [Intel XE#7387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7387
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7390
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7402
  [Intel XE#7405]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7405
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7417]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7417
  [Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
  [Intel XE#7425]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7425
  [Intel XE#7426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7426
  [Intel XE#7429]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7429
  [Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
  [Intel XE#7442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7442
  [Intel XE#7448]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7448
  [Intel XE#7456]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7456
  [Intel XE#7466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7466
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7590]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7590
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7644]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7644
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7687]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7687
  [Intel XE#7760]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7760
  [Intel XE#7778]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7778
  [Intel XE#7779]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7779
  [Intel XE#7780]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7780
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7794
  [Intel XE#7795]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7795
  [Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7980]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7980
  [Intel XE#8007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8007
  [Intel XE#8159]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8159
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8348]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8348
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8365]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8365
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8370
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8586
  [Intel XE#8649]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8649
  [Intel XE#8652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8652
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#8854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8854
  [Intel XE#8866]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8866
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#9093]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9093
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9125
  [Intel XE#9128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9128
  [Intel XE#9130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9130
  [Intel XE#9131]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9131
  [Intel XE#9140]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9140
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9145]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9145
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#979]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/979


Build changes
-------------

  * Linux: xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f -> xe-pw-169692v3

  IGT_9084: 9084
  xe-5696-496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f: 496ff8213a2d2e1e5b1c8efe8b55e1dcdc3e3f8f
  xe-pw-169692v3: 169692v3

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-169692v3/index.html

[-- Attachment #2: Type: text/html, Size: 127128 bytes --]

^ permalink raw reply	[flat|nested] 45+ messages in thread

end of thread, other threads:[~2026-09-10 22:30 UTC | newest]

Thread overview: 45+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-06 17:26 [PATCH v3 00/12] Add CPER logging support for CRI Badal Nilawar
2026-09-06 17:16 ` ✗ CI.checkpatch: warning for Add CPER logging support for CRI (rev3) Patchwork
2026-09-06 17:18 ` ✓ CI.KUnit: success " Patchwork
2026-09-06 17:26 ` [PATCH v3 01/12] drm/xe/cper: Hardware error CPER reporting from xe_log Badal Nilawar
2026-09-06 17:21   ` sashiko-bot
2026-09-07 12:38   ` Michal Wajdeczko
2026-09-10 11:39     ` Nilawar, Badal
2026-09-08 10:12   ` Raag Jadav
2026-09-10 12:33     ` Nilawar, Badal
2026-09-06 17:26 ` [PATCH v3 02/12] drm/xe/cper: Retrieve the error counter record for CPER reporting Badal Nilawar
2026-09-06 17:23   ` sashiko-bot
2026-09-08 10:16   ` Raag Jadav
2026-09-09  6:12     ` Raag Jadav
2026-09-10 12:59       ` Nilawar, Badal
2026-09-10 13:19         ` Raag Jadav
2026-09-06 17:26 ` [PATCH v3 03/12] drm/xe/cper: Add Intel specific CPER structures Badal Nilawar
2026-09-07 13:13   ` Michal Wajdeczko
2026-09-10 11:57     ` Nilawar, Badal
2026-09-08 10:18   ` Raag Jadav
2026-09-10 13:36     ` Nilawar, Badal
2026-09-06 17:26 ` [PATCH v3 04/12] drm/xe/cper: Prepare CPER record Badal Nilawar
2026-09-06 17:27   ` sashiko-bot
2026-09-08 10:20   ` Raag Jadav
2026-09-06 17:26 ` [PATCH v3 05/12] drm/xe/xe_ras: Add support to retrieve info queue data for CRI Badal Nilawar
2026-09-06 17:17   ` sashiko-bot
2026-09-09  8:03   ` Raag Jadav
2026-09-06 17:26 ` [PATCH v3 06/12] drm/xe/cper: Prepare Intel CPER error info records Badal Nilawar
2026-09-06 17:30   ` sashiko-bot
2026-09-09 11:58   ` Raag Jadav
2026-09-06 17:26 ` [PATCH v3 07/12] drm/xe/cper: Log CPER records for aggregate counter retrival Badal Nilawar
2026-09-06 17:23   ` sashiko-bot
2026-09-10  6:27   ` Raag Jadav
2026-09-10 22:29     ` Rodrigo Vivi
2026-09-06 17:26 ` [PATCH v3 08/12] drm/xe/xe_ras: Report device memory errors using SIGID Badal Nilawar
2026-09-06 17:27   ` sashiko-bot
2026-09-06 17:26 ` [PATCH v3 09/12] drm/xe/xe_ras: Report core compute " Badal Nilawar
2026-09-06 17:21   ` sashiko-bot
2026-09-06 17:26 ` [PATCH v3 10/12] drm/xe/xe_ras: Report soc internal " Badal Nilawar
2026-09-06 17:26 ` [PATCH v3 11/12] drm/xe/xe_ras: Report correctable " Badal Nilawar
2026-09-06 17:27   ` sashiko-bot
2026-09-06 17:26 ` [PATCH v3 12/12] drm/xe/cper: Emit cper record to trace buf Badal Nilawar
2026-09-06 17:28   ` sashiko-bot
2026-09-10  7:58   ` Raag Jadav
2026-09-06 17:55 ` ✓ Xe.CI.BAT: success for Add CPER logging support for CRI (rev3) Patchwork
2026-09-06 19:02 ` ✗ Xe.CI.FULL: failure " Patchwork

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