From: Francois Dugast <francois.dugast@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v7 17/24] drm/xe: Add device flag to enable PT mirroring across tiles
Date: Fri, 25 Sep 2026 11:51:06 +0200 [thread overview]
Message-ID: <arZEAWldjKQXDjsy@fdugast-desk> (raw)
In-Reply-To: <20260925045320.1325860-18-matthew.brost@intel.com>
On Thu, Sep 24, 2026 at 09:53:13PM -0700, Matthew Brost wrote:
> Some multi-tile devices may want to mirror page tables across tiles for
> memory-bandwidth reasons, while others may not. Add a device flag that
> allows enabling or disabling page-table mirroring across tiles.
>
> Setting the flag to true (the existing behavior) on PVC, but both modes
> have been tested and are working on PVC.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Francois Dugast <francois.dugast@intel.com>
>
> ---
> v7:
> - Rework pt_mirroring_disabled_for_tile (Himal)
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 2 ++
> drivers/gpu/drm/xe/xe_migrate.c | 5 ++--
> drivers/gpu/drm/xe/xe_pci.c | 2 ++
> drivers/gpu/drm/xe/xe_pci_types.h | 3 ++-
> drivers/gpu/drm/xe/xe_pt.c | 36 +++++++++++++++++++++++++--
> drivers/gpu/drm/xe/xe_vm.c | 37 +++++++++++++++++++++++++---
> drivers/gpu/drm/xe/xe_vm.h | 3 +++
> 7 files changed, 79 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index aff2e5c8b656..cd9ed8ff2940 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -229,6 +229,8 @@ struct xe_device {
> u8 has_usm:1;
> /** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
> u8 has_64bit_timestamp:1;
> + /** @info.has_pt_mirror: Device has PT mirroring across tiles */
> + u8 has_pt_mirror:1;
> /** @info.is_dgfx: is discrete device */
> u8 is_dgfx:1;
> /** @info.needs_scratch: needs scratch page for oob prefetch to work */
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index f7e1a81434b2..471ae5741836 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -246,7 +246,8 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> struct xe_device *xe = tile_to_xe(tile);
> u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
> u8 id = tile->id;
> - u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
> + u32 num_entries = NUM_PT_SLOTS, num_level =
> + xe_vm_pt_root(vm, id)->level;
> #define VRAM_IDENTITY_MAP_PT_COUNT 4
> u32 num_setup = num_level + VRAM_IDENTITY_MAP_PT_COUNT;
> #undef VRAM_IDENTITY_MAP_PT_COUNT
> @@ -258,7 +259,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
> u64 l1_pt_ofs = xe_bo_size(bo) - 5 * XE_PAGE_SIZE;
>
> entry = vm->pt_ops->pde_encode_bo(bo, l1_pt_ofs);
> - xe_pt_write(xe, &vm->pt_root[id]->bo->vmap, 0, entry);
> + xe_pt_write(xe, &xe_vm_pt_root(vm, id)->bo->vmap, 0, entry);
>
> map_ofs = (num_entries - num_setup) * XE_PAGE_SIZE;
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index d64e873d9e71..28f37e034e02 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -371,6 +371,7 @@ static const __maybe_unused struct xe_device_desc pvc_desc = {
> .has_display = false,
> .has_drm_ras = true,
> .has_gsc_nvm = 1,
> + .has_pt_mirror = 1,
> .has_heci_gscfi = 1,
> .max_gt_per_tile = 1,
> .max_remote_tiles = 1,
> @@ -807,6 +808,7 @@ static int xe_info_init_early(struct xe_device *xe,
> xe->info.has_mert = desc->has_mert;
> xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
> xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
> + xe->info.has_pt_mirror = desc->has_pt_mirror;
> xe->info.has_pxp = desc->has_pxp;
> xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
> xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
> diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
> index fed509ff601e..71068cdb3558 100644
> --- a/drivers/gpu/drm/xe/xe_pci_types.h
> +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> @@ -52,8 +52,9 @@ struct xe_device_desc {
> u8 has_mbx_power_limits:1;
> u8 has_mbx_thermal_info:1;
> u8 has_mert:1;
> - u8 has_pre_prod_wa:1;
> u8 has_page_reclaim_hw_assist:1;
> + u8 has_pre_prod_wa:1;
> + u8 has_pt_mirror:1;
> u8 has_pxp:1;
> u8 has_soc_remapper_sysctrl:1;
> u8 has_soc_remapper_telem:1;
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index fbefcfc52dca..dcef29b56d63 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -804,7 +804,7 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
> .wupd.entries = entries,
> .clear_pt = clear_pt,
> };
> - struct xe_pt *pt = vm->pt_root[tile->id];
> + struct xe_pt *pt = xe_vm_pt_root(vm, tile->id);
> int ret;
> bool is_purged = false;
>
> @@ -1005,6 +1005,11 @@ static int xe_pt_zap_ptes_entry(struct xe_ptw *parent, pgoff_t offset,
> return 0;
> }
>
> +static bool pt_mirroring_disabled_for_tile(struct xe_vm *vm, u8 tile_id)
> +{
> + return !vm->xe->info.has_pt_mirror && tile_id;
> +}
> +
> static const struct xe_pt_walk_ops xe_pt_zap_ptes_ops = {
> .pt_entry = xe_pt_zap_ptes_entry,
> };
> @@ -1046,6 +1051,9 @@ bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma)
> if (!(pt_mask & BIT(tile->id)))
> return false;
>
> + if (pt_mirroring_disabled_for_tile(xe_vma_vm(vma), tile->id))
> + return true;
> +
> (void)xe_pt_walk_shared(&pt->base, pt->level, xe_vma_start(vma),
> xe_vma_end(vma), &xe_walk.base);
>
> @@ -1098,6 +1106,9 @@ bool xe_pt_zap_ptes_range(struct xe_tile *tile, struct xe_vm *vm,
> if (!(pt_mask & BIT(tile->id)))
> return false;
>
> + if (pt_mirroring_disabled_for_tile(vm, tile->id))
> + return true;
> +
> (void)xe_pt_walk_shared(&pt->base, pt->level, xe_svm_range_start(range),
> xe_svm_range_end(range), &xe_walk.base);
>
> @@ -1987,7 +1998,7 @@ static unsigned int xe_pt_stage_unbind(struct xe_tile *tile,
> .wupd.entries = entries,
> .prl = pt_update_op->prl,
> };
> - struct xe_pt *pt = vm->pt_root[tile->id];
> + struct xe_pt *pt = xe_vm_pt_root(vm, tile->id);
>
> (void)xe_pt_walk_shared(&pt->base, pt->level, start, end,
> &xe_walk.base);
> @@ -2539,9 +2550,21 @@ int xe_pt_update_ops_prepare(struct xe_device *xe, struct xe_vma_ops *vops)
> int id, err;
>
> for_each_tile(tile, xe, id) {
> + struct xe_vm_pgtable_update_ops *pt_update_ops =
> + &vops->pt_update_ops[id];
> +
> if (!vops->pt_update_ops[id].num_ops)
> continue;
>
> + if (pt_mirroring_disabled_for_tile(vops->vm, id)) {
> + struct xe_page_reclaim_list *prl = &pt_update_ops->prl;
> +
> + /* Transfer root PT update ops PRL to current */
> + *prl = vops->pt_update_ops[0].prl;
> + xe_page_reclaim_entries_get(prl->entries);
> + continue;
> + }
> +
> err = __xe_pt_update_ops_prepare(tile, vops);
> if (err)
> return err;
> @@ -2833,6 +2856,12 @@ xe_pt_update_ops_run(struct xe_device *xe, struct xe_vma_ops *vops)
> struct xe_vm_pgtable_update_ops *pt_update_ops =
> &vops->pt_update_ops[j];
>
> + if (pt_mirroring_disabled_for_tile(vm, j)) {
> + xe_tile_assert(tile, !get_current_op(pt_update_ops));
> + tile_mask |= BIT(tile->id);
> + continue;
> + }
> +
> for (i = 0; i < get_current_op(pt_update_ops); ++i) {
> struct xe_vm_pgtable_update_op *pt_op =
> to_pt_op(pt_update_ops, i);
> @@ -2946,6 +2975,9 @@ void xe_pt_update_ops_abort(struct xe_device *xe, struct xe_vma_ops *vops)
> &vops->pt_update_ops[id];
> int i;
>
> + if (pt_mirroring_disabled_for_tile(vops->vm, id))
> + continue;
> +
> for (i = pt_update_ops->num_ops - 1; i >= 0; --i) {
> struct xe_vm_pgtable_update_op *pt_op =
> to_pt_op(pt_update_ops, i);
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index 0f542f47b9a8..f450e1c6f750 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -846,6 +846,14 @@ int xe_vm_rebind(struct xe_vm *vm, bool rebind_worker)
> return err;
> }
>
> +static u8 adjust_rebind_tile_mask(struct xe_vm *vm, u8 tile_mask)
> +{
> + if (vm->xe->info.has_pt_mirror)
> + return tile_mask;
> +
> + return (0x1 << vm->xe->info.tile_count) - 1;
> +}
> +
> struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_mask)
> {
> struct dma_fence *fence = NULL;
> @@ -862,7 +870,8 @@ struct dma_fence *xe_vma_rebind(struct xe_vm *vm, struct xe_vma *vma, u8 tile_ma
> vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
> XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
>
> - err = xe_vm_ops_add_rebind(&vops, vma, tile_mask);
> + err = xe_vm_ops_add_rebind(&vops, vma,
> + adjust_rebind_tile_mask(vm, tile_mask));
> if (err)
> return ERR_PTR(err);
>
> @@ -949,7 +958,8 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm,
> vops.flags |= XE_VMA_OPS_FLAG_SKIP_TLB_WAIT |
> XE_VMA_OPS_FLAG_WAIT_VM_BOOKKEEP;
>
> - err = xe_vm_ops_add_range_rebind(&vops, vma, range, tile_mask);
> + err = xe_vm_ops_add_range_rebind(&vops, vma, range,
> + adjust_rebind_tile_mask(vm, tile_mask));
> if (err)
> return ERR_PTR(err);
>
> @@ -1739,7 +1749,8 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
>
> for_each_tile(tile, xe, id) {
> if (flags & XE_VM_FLAG_MIGRATION &&
> - tile->id != XE_VM_FLAG_TILE_ID(flags))
> + tile->id != XE_VM_FLAG_TILE_ID(flags) &&
> + (vm->xe->info.has_pt_mirror || id))
> continue;
>
> vm->pt_root[id] = xe_pt_create(vm, tile, xe->info.vm_max_level,
> @@ -2049,7 +2060,7 @@ struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id)
>
> u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile)
> {
> - return vm->pt_ops->pde_encode_bo(vm->pt_root[tile->id]->bo, 0);
> + return vm->pt_ops->pde_encode_bo(xe_vm_pt_root(vm, tile->id)->bo, 0);
> }
>
> static struct xe_exec_queue *
> @@ -5074,3 +5085,21 @@ void xe_vm_remove_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q)
> }
> up_write(&vm->exec_queues.lock);
> }
> +
> +/**
> + * xe_vm_pt_root() - Retrieve VM page-table root
> + * @vm: The VM.
> + * @tile_id: Tile ID
> + *
> + * Retrieve VM page-table root for a tile ID, used to abstract if PT mirroring is
> + * enabled across tiles.
> + *
> + * Return: VM page-table root for a tile ID
> + */
> +struct xe_pt *xe_vm_pt_root(struct xe_vm *vm, u8 tile_id)
> +{
> + if (vm->xe->info.has_pt_mirror)
> + return vm->pt_root[tile_id];
> +
> + return vm->pt_root[0];
> +}
> diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
> index c5b900f38ded..89c4f95984a2 100644
> --- a/drivers/gpu/drm/xe/xe_vm.h
> +++ b/drivers/gpu/drm/xe/xe_vm.h
> @@ -436,4 +436,7 @@ static inline struct drm_exec *xe_vm_validation_exec(struct xe_vm *vm)
> ((READ_ONCE(tile_present) & ~READ_ONCE(tile_invalidated)) & BIT((tile)->id))
>
> void xe_vma_mem_attr_copy(struct xe_vma_mem_attr *to, struct xe_vma_mem_attr *from);
> +
> +struct xe_pt *xe_vm_pt_root(struct xe_vm *vm, u8 tile_id);
> +
> #endif
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-09-25 9:51 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-25 4:52 [PATCH v7 00/24] CPU binds and ULLS on migration queue Matthew Brost
2026-09-25 4:52 ` [PATCH v7 01/24] drm/xe: reference VM from PT BOs Matthew Brost
2026-09-25 12:00 ` Francois Dugast
2026-09-25 16:10 ` Matthew Brost
2026-09-25 4:52 ` [PATCH v7 02/24] drm/xe: Drop struct xe_migrate_pt_update argument from populate/clear vfuns Matthew Brost
2026-09-25 4:52 ` [PATCH v7 03/24] drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper Matthew Brost
2026-09-25 4:53 ` [PATCH v7 04/24] drm/xe: Decouple exec queue idle check from LRC Matthew Brost
2026-09-25 4:53 ` [PATCH v7 05/24] drm/xe: Add job count to GuC exec queue snapshot Matthew Brost
2026-09-25 4:53 ` [PATCH v7 06/24] drm/xe: Update xe_bo_put_deferred arguments to include writeback flag Matthew Brost
2026-09-25 4:53 ` [PATCH v7 07/24] drm/xe: Update scheduler job layer to support PT jobs Matthew Brost
2026-09-25 11:23 ` Francois Dugast
2026-09-25 4:53 ` [PATCH v7 08/24] drm/xe: Add helpers to access PT ops Matthew Brost
2026-09-25 4:53 ` [PATCH v7 09/24] drm/xe: Add struct xe_pt_job_ops Matthew Brost
2026-09-25 4:53 ` [PATCH v7 10/24] drm/xe: Update GuC submission backend to run PT jobs Matthew Brost
2026-09-25 5:39 ` sashiko-bot
2026-09-25 5:58 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 11/24] drm/xe: Store level in struct xe_vm_pgtable_update Matthew Brost
2026-09-25 4:53 ` [PATCH v7 12/24] drm/xe: Don't use migrate exec queue for page fault binds Matthew Brost
2026-09-25 4:53 ` [PATCH v7 13/24] drm/xe: Enable CPU binds for jobs Matthew Brost
2026-09-25 6:03 ` sashiko-bot
2026-09-25 6:54 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 14/24] drm/xe: Remove unused arguments from xe_migrate_pt_update_ops Matthew Brost
2026-09-25 4:53 ` [PATCH v7 15/24] drm/xe: Make bind queues operate cross-tile Matthew Brost
2026-09-25 4:53 ` [PATCH v7 16/24] drm/xe: Add CPU bind layer Matthew Brost
2026-09-25 4:53 ` [PATCH v7 17/24] drm/xe: Add device flag to enable PT mirroring across tiles Matthew Brost
2026-09-25 6:25 ` sashiko-bot
2026-09-25 7:21 ` Matthew Brost
2026-09-25 9:51 ` Francois Dugast [this message]
2026-09-25 4:53 ` [PATCH v7 18/24] drm/xe: Add ULLS support to LRC Matthew Brost
2026-09-25 4:53 ` [PATCH v7 19/24] drm/xe: Add ULLS migration job support to migration layer Matthew Brost
2026-09-25 6:34 ` sashiko-bot
2026-09-25 7:17 ` Matthew Brost
2026-09-25 20:10 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 20/24] drm/xe: Add ULLS migration job support to ring ops Matthew Brost
2026-09-25 6:38 ` sashiko-bot
2026-09-25 7:02 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 21/24] drm/xe: Add ULLS migration job support to GuC submission Matthew Brost
2026-09-25 6:48 ` sashiko-bot
2026-09-25 7:08 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 22/24] drm/xe: Enter ULLS for migration jobs upon page fault or SVM prefetch Matthew Brost
2026-09-25 17:49 ` Maarten Lankhorst
2026-09-25 18:17 ` Matthew Brost
2026-09-25 18:26 ` Maarten Lankhorst
2026-09-25 19:38 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 23/24] drm/xe: add migrate ULLS period configfs attribute Matthew Brost
2026-09-25 6:51 ` sashiko-bot
2026-09-25 7:08 ` Matthew Brost
2026-09-25 4:53 ` [PATCH v7 24/24] drm/xe: Document ULLS for migration jobs Matthew Brost
2026-09-25 5:02 ` ✗ CI.checkpatch: warning for CPU binds and ULLS on migration queue (rev9) Patchwork
2026-09-25 5:04 ` ✓ CI.KUnit: success " Patchwork
2026-09-25 5:47 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-25 15:05 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-09-25 16:01 ` Matthew Brost
2026-09-25 18:08 ` [PATCH v7 00/24] CPU binds and ULLS on migration queue Maarten Lankhorst
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=arZEAWldjKQXDjsy@fdugast-desk \
--to=francois.dugast@intel.com \
--cc=intel-xe@lists.freedesktop.org \
--cc=matthew.brost@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox