Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Tauro, Riana" <riana.tauro@intel.com>
To: "Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>
Cc: <anshuman.gupta@intel.com>, <rodrigo.vivi@intel.com>,
	<aravind.iddamsetty@linux.intel.com>, <badal.nilawar@intel.com>,
	<raag.jadav@intel.com>, <ravi.kishore.koppuravuri@intel.com>,
	<soham.purkait@intel.com>, <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras
Date: Tue, 12 May 2026 12:28:32 +0530	[thread overview]
Message-ID: <b3c54a66-ab62-4231-8671-a7b5a4f8acdd@intel.com> (raw)
In-Reply-To: <4ac5d412-de6f-4e04-9000-f9b61e1bc5d3@intel.com>


On 5/8/2026 12:07 PM, Mallesh, Koujalagi wrote:
>
> On 04-05-2026 12:26 pm, Riana Tauro wrote:
>> Add additional Error components supported by XE drm_ras (Reliability,
>> Availability and Serviceability).
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>
>> ---
>>   include/uapi/drm/xe_drm.h | 11 ++++++++++-
>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
>> index 48e9f1fdb78d..50c80af4ad4e 100644
>> --- a/include/uapi/drm/xe_drm.h
>> +++ b/include/uapi/drm/xe_drm.h
>> @@ -2589,6 +2589,12 @@ enum drm_xe_ras_error_component {
>>       DRM_XE_RAS_ERR_COMP_CORE_COMPUTE = 1,
>>       /** @DRM_XE_RAS_ERR_COMP_SOC_INTERNAL: SoC Internal Error */
>>       DRM_XE_RAS_ERR_COMP_SOC_INTERNAL,
>> +    /** @DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY: Device Memory Error */
>> +    DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY,
>> +    /** @DRM_XE_RAS_ERR_COMP_PCIE: PCIe Subsystem Error */
>> +    DRM_XE_RAS_ERR_COMP_PCIE,
>> +    /** @DRM_XE_RAS_ERR_COMP_FABRIC: Fabric Subsystem Error */
>> +    DRM_XE_RAS_ERR_COMP_FABRIC,
>>       /** @DRM_XE_RAS_ERR_COMP_MAX: Max Error */
>>       DRM_XE_RAS_ERR_COMP_MAX    /* non-ABI */
>>   };
>> @@ -2606,7 +2612,10 @@ enum drm_xe_ras_error_component {
>>    */
>>   #define DRM_XE_RAS_ERROR_COMPONENT_NAMES {                \
>>       [DRM_XE_RAS_ERR_COMP_CORE_COMPUTE] = "core-compute",        \
>> -    [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal" \
>> +    [DRM_XE_RAS_ERR_COMP_SOC_INTERNAL] = "soc-internal", \
>> +    [DRM_XE_RAS_ERR_COMP_DEVICE_MEMORY] = "device-memory",        \
>> +    [DRM_XE_RAS_ERR_COMP_PCIE] = "pcie",                \
>> +    [DRM_XE_RAS_ERR_COMP_FABRIC] = "fabric",            \
>>   }
>
> Please add static assert check to keep names in sync.

This is a macro we cannot add static assert here.

Thanks
Riana

>
> With that addressed:
>
> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
>
> Thanks,
>
> -/Mallesh
>
>>     #if defined(__cplusplus)

  reply	other threads:[~2026-05-12  6:58 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-04  6:56 [PATCH v5 0/6] Add get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-04  6:43 ` ✗ CI.checkpatch: warning for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork
2026-05-04  6:45 ` ✓ CI.KUnit: success " Patchwork
2026-05-04  6:56 ` [PATCH v5 1/6] drm/xe/uapi: Add additional error components to xe drm_ras Riana Tauro
2026-05-08  6:37   ` Mallesh, Koujalagi
2026-05-12  6:58     ` Tauro, Riana [this message]
2026-05-04  6:56 ` [PATCH v5 2/6] drm/xe/xe_ras: Add support to get error counter in CRI Riana Tauro
2026-05-06  8:03   ` Mallesh, Koujalagi
2026-05-06  8:59     ` Tauro, Riana
2026-05-11 15:27   ` Raag Jadav
2026-05-12  5:27     ` Tauro, Riana
2026-05-12  5:47       ` Raag Jadav
2026-05-13  8:43         ` Tauro, Riana
2026-05-04  6:56 ` [PATCH v5 3/6] drm/xe/xe_ras: Add helper to clear error counter Riana Tauro
2026-05-08  7:50   ` Mallesh, Koujalagi
2026-05-11  6:20     ` Tauro, Riana
2026-05-11  7:42       ` Mallesh, Koujalagi
2026-05-11  7:49         ` Tauro, Riana
2026-05-11 15:32   ` Raag Jadav
2026-05-12  6:48     ` Tauro, Riana
2026-05-04  6:56 ` [PATCH v5 4/6] drm/xe/xe_drm_ras: Wire get-error-counter and clear-error-counter support for CRI Riana Tauro
2026-05-11 15:34   ` Raag Jadav
2026-05-12  5:08     ` Tauro, Riana
2026-05-04  6:56 ` [PATCH v5 5/6] drm/xe/xe_ras: Move xe drm_ras registration Riana Tauro
2026-05-04 10:53   ` Tauro, Riana
2026-05-04 16:22     ` Raag Jadav
2026-05-12  5:04       ` Tauro, Riana
2026-05-12 16:19         ` Anoop Vijay
2026-05-11 15:36   ` Raag Jadav
2026-05-04  6:56 ` [PATCH v5 6/6] drm/xe/xe_ras: Control xe drm_ras registration with a flag Riana Tauro
2026-05-11 15:46   ` Raag Jadav
2026-05-04  8:00 ` ✓ Xe.CI.BAT: success for Add get-error-counter and clear-error-counter support for CRI (rev4) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b3c54a66-ab62-4231-8671-a7b5a4f8acdd@intel.com \
    --to=riana.tauro@intel.com \
    --cc=anshuman.gupta@intel.com \
    --cc=aravind.iddamsetty@linux.intel.com \
    --cc=badal.nilawar@intel.com \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=mallesh.koujalagi@intel.com \
    --cc=raag.jadav@intel.com \
    --cc=ravi.kishore.koppuravuri@intel.com \
    --cc=rodrigo.vivi@intel.com \
    --cc=soham.purkait@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox