From: "Summers, Stuart" <stuart.summers@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"Brost, Matthew" <matthew.brost@intel.com>
Cc: "Roper, Matthew D" <matthew.d.roper@intel.com>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [PATCH v2 08/12] drm/xe: Add send_tlb_inval_ppgtt helper
Date: Thu, 6 Nov 2025 20:25:59 +0000 [thread overview]
Message-ID: <f0e8ad79ec0fa4440edd367a6cc465fdf3fb09e2.camel@intel.com> (raw)
In-Reply-To: <20251104195616.3339137-9-matthew.brost@intel.com>
On Tue, 2025-11-04 at 11:56 -0800, Matthew Brost wrote:
> Extract the common code that issues a TLB invalidation H2G for PPGTTs
> into a helper function. This helper can be reused for both ASID-based
> and context-based TLB invalidations.
>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> ---
> drivers/gpu/drm/xe/xe_guc_tlb_inval.c | 27 +++++++++++++++++++------
> --
> 1 file changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> index 42e9fbd062ba..6978ee8edf2e 100644
> --- a/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> +++ b/drivers/gpu/drm/xe/xe_guc_tlb_inval.c
> @@ -131,19 +131,15 @@ static u64 normalize_invalidation_range(struct
> xe_gt *gt, u64 *start, u64 *end)
> */
> #define MAX_RANGE_TLB_INVALIDATION_LENGTH
> (rounddown_pow_of_two(ULONG_MAX))
>
> -static int send_tlb_inval_asid_ppgtt(struct xe_tlb_inval *tlb_inval,
> u32 seqno,
> - u64 start, u64 end, u32 asid)
> +static int send_tlb_inval_ppgtt(struct xe_guc *guc, u32 seqno, u64
> start,
> + u64 end, u32 id, u32 type)
> {
> #define MAX_TLB_INVALIDATION_LEN 7
> - struct xe_guc *guc = tlb_inval->private;
> struct xe_gt *gt = guc_to_gt(guc);
> u32 action[MAX_TLB_INVALIDATION_LEN];
> u64 length = end - start;
> int len = 0;
>
> - if (guc_to_xe(guc)->info.force_execlist)
> - return -ECANCELED;
> -
> action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> action[len++] = seqno;
> if (!gt_to_xe(gt)->info.has_range_tlb_inval ||
> @@ -153,18 +149,33 @@ static int send_tlb_inval_asid_ppgtt(struct
> xe_tlb_inval *tlb_inval, u32 seqno,
> u64 normalize_len = normalize_invalidation_range(gt,
> &start,
>
> &end);
>
> - action[len++] =
> MAKE_INVAL_OP(XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
> - action[len++] = asid;
> + action[len++] = MAKE_INVAL_OP(type);
> + action[len++] = id;
> action[len++] = lower_32_bits(start);
> action[len++] = upper_32_bits(start);
> action[len++] = ilog2(normalize_len) - ilog2(SZ_4K);
> }
>
> xe_gt_assert(gt, len <= MAX_TLB_INVALIDATION_LEN);
> +#undef MAX_TLB_INVALIDATION_LEN
>
> return send_tlb_inval(guc, action, len);
> }
>
> +static int send_tlb_inval_asid_ppgtt(struct xe_tlb_inval *tlb_inval,
> u32 seqno,
> + u64 start, u64 end, u32 asid)
> +{
> + struct xe_guc *guc = tlb_inval->private;
> +
> + lockdep_assert_held(&tlb_inval->seqno_lock);
> +
> + if (guc_to_xe(guc)->info.force_execlist)
> + return -ECANCELED;
> +
> + return send_tlb_inval_ppgtt(guc, seqno, start, end, asid,
> + XE_GUC_TLB_INVAL_PAGE_SELECTIVE);
> +}
> +
> static bool tlb_inval_initialized(struct xe_tlb_inval *tlb_inval)
> {
> struct xe_guc *guc = tlb_inval->private;
next prev parent reply other threads:[~2025-11-06 20:26 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 19:56 [PATCH v2 00/12] Context based TLB invalidations Matthew Brost
2025-11-04 19:56 ` [PATCH v2 01/12] drm/xe: Add normalize_invalidation_range Matthew Brost
2025-11-06 20:03 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 02/12] drm/xe: Make usm.asid_to_vm allocation use GFP_NOWAIT Matthew Brost
2025-11-06 22:08 ` Summers, Stuart
2025-11-06 22:13 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 03/12] drm/xe: Add xe_device_asid_to_vm helper Matthew Brost
2025-12-11 22:07 ` Matt Atwood
2025-11-04 19:56 ` [PATCH v2 04/12] drm/xe: Add vm to exec queues association Matthew Brost
2025-11-06 22:15 ` Summers, Stuart
2025-12-12 21:03 ` Summers, Stuart
2025-12-12 21:24 ` Matthew Brost
2025-12-12 21:37 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 05/12] drm/xe: Taint TLB invalidation seqno lock with GFP_KERNEL Matthew Brost
2025-12-11 22:35 ` Matt Atwood
2025-11-04 19:56 ` [PATCH v2 06/12] drm/xe: Do not forward invalid TLB invalidation seqnos to upper layers Matthew Brost
2025-11-06 22:05 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 07/12] drm/xe: Rename send_tlb_inval_ppgtt to send_tlb_inval_asid_ppgtt Matthew Brost
2025-11-06 20:22 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 08/12] drm/xe: Add send_tlb_inval_ppgtt helper Matthew Brost
2025-11-06 20:25 ` Summers, Stuart [this message]
2025-11-04 19:56 ` [PATCH v2 09/12] drm/xe: Add xe_tlb_inval_idle helper Matthew Brost
2025-11-10 18:48 ` Summers, Stuart
2025-12-12 22:00 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 10/12] drm/xe: Add exec queue active vfunc Matthew Brost
2025-11-04 19:56 ` [PATCH v2 11/12] drm/xe: Add context-based invalidation to GuC TLB invalidation backend Matthew Brost
2025-11-06 21:50 ` Summers, Stuart
2025-11-07 7:01 ` Matthew Brost
2025-11-10 19:29 ` Summers, Stuart
2025-11-11 1:01 ` Matthew Brost
2025-12-12 22:30 ` Summers, Stuart
2025-11-04 19:56 ` [PATCH v2 12/12] drm/xe: Enable context TLB invalidations for CI Matthew Brost
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