[RFC 0/5] drm/xe: Add System Controller support for Xe3p dGPU platforms

[RFC 0/5] drm/xe: Add System Controller support for Xe3p dGPU platforms

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

This RFC series introduces System Controller (SC) driver support for Intel 
Xe3p dGPU platforms.

The series includes:

1. SoC Remapper Infrastructure (Patches 1-4) - Memory mapping infrastructure 
   for accessing system controller regions and SoC components.

2. System Controller Driver (Patch 5) - Core SC communication using MKHI 
   protocol over a mailbox interface for firmware communication.

Key features:
- Detection and initialization of the SC interface on Xe3p dGPU platforms
- Mailbox communication with SC firmware
- Fragmented message transfer for large command payloads

Note: Patch 5 (SC driver) is not tested on simulation platforms.

This implementation establishes the base for future SC feature
enablement and firmware command handling.

Anoop Vijay (1):
  drm/xe/sc: Add system controller component for Xe3p dGPU platforms

Umesh Nerlige Ramappa (4):
  drm/xe/soc_remapper: Initialize SoC remapper during Xe probe
  drm/xe/soc_remapper: Use SoC remapper herlper from VSEC code
  drm/xe/soc_remapper: Add system controller config for SoC remapper
  drm/xe/remapper: Reprogram remapper index on PM resume events

 drivers/gpu/drm/xe/Makefile                   |   3 +
 drivers/gpu/drm/xe/regs/xe_pmt.h              |   3 -
 drivers/gpu/drm/xe/regs/xe_sc_regs.h          |  49 +++
 drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h    |  14 +
 drivers/gpu/drm/xe/xe_device.c                |  10 +
 drivers/gpu/drm/xe/xe_device_types.h          |  17 +
 drivers/gpu/drm/xe/xe_pm.c                    |   5 +
 drivers/gpu/drm/xe/xe_sc.c                    |  89 +++++
 drivers/gpu/drm/xe/xe_sc.h                    |  15 +
 drivers/gpu/drm/xe/xe_sc_mailbox.c            | 374 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_sc_mailbox.h            |  61 +++
 drivers/gpu/drm/xe/xe_sc_types.h              |  35 ++
 drivers/gpu/drm/xe/xe_soc_remapper.c          |  54 +++
 drivers/gpu/drm/xe/xe_soc_remapper.h          |  18 +
 drivers/gpu/drm/xe/xe_vsec.c                  |  56 +--
 15 files changed, 720 insertions(+), 84 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_sc.c
 create mode 100644 drivers/gpu/drm/xe/xe_sc.h
 create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h

--
2.45.0

[RFC 1/5] drm/xe/soc_remapper: Initialize SoC remapper during Xe probe

[Anoop, Vijay]

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

SoC remapper is used to map different HW functions in the SoC to their
respective drivers. Initialize SoC remapper during driver load.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/Makefile          |  1 +
 drivers/gpu/drm/xe/xe_device.c       |  5 +++++
 drivers/gpu/drm/xe/xe_device_types.h |  6 ++++++
 drivers/gpu/drm/xe/xe_soc_remapper.c | 15 +++++++++++++++
 drivers/gpu/drm/xe/xe_soc_remapper.h | 15 +++++++++++++++
 5 files changed, 42 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/xe_soc_remapper.c
 create mode 100644 drivers/gpu/drm/xe/xe_soc_remapper.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 1a3aa041820d..7ebfbf9051bf 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -110,6 +110,7 @@ xe-y += xe_bb.o \
 	xe_range_fence.o \
 	xe_reg_sr.o \
 	xe_reg_whitelist.o \
+	xe_soc_remapper.o \
 	xe_ring_ops.o \
 	xe_rtp.o \
 	xe_sa.o \
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index 1197f914ef77..f15489c100af 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -60,6 +60,7 @@
 #include "xe_psmi.h"
 #include "xe_pxp.h"
 #include "xe_query.h"
+#include "xe_soc_remapper.h"
 #include "xe_shrinker.h"
 #include "xe_survivability_mode.h"
 #include "xe_sriov.h"
@@ -906,6 +907,10 @@ int xe_device_probe(struct xe_device *xe)
 
 	xe_nvm_init(xe);
 
+	err = xe_soc_remapper_init(xe);
+	if (err)
+		return err;
+
 	err = xe_heci_gsc_init(xe);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 0b2fa7c56d38..4d23b75bc728 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -552,6 +552,12 @@ struct xe_device {
 		struct mutex lock;
 	} pmt;
 
+	/* @soc_remapper: SoC remapper object */
+	struct {
+		/* Serialize access to SoC Remapper's index registers */
+		spinlock_t lock;
+	} soc_remapper;
+
 	/**
 	 * @pm_callback_task: Track the active task that is running in either
 	 * the runtime_suspend or runtime_resume callbacks.
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.c b/drivers/gpu/drm/xe/xe_soc_remapper.c
new file mode 100644
index 000000000000..f5a02abd6ab1
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.c
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/spinlock.h>
+
+#include "xe_soc_remapper.h"
+
+int xe_soc_remapper_init(struct xe_device *xe)
+{
+	spin_lock_init(&xe->soc_remapper.lock);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.h b/drivers/gpu/drm/xe/xe_soc_remapper.h
new file mode 100644
index 000000000000..3cfd44f1fd74
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SOC_REMAPPER_H_
+#define _XE_SOC_REMAPPER_H_
+
+#include <linux/types.h>
+
+#include "xe_device_types.h"
+
+int xe_soc_remapper_init(struct xe_device *xe);
+
+#endif
-- 
2.43.0

[RFC 2/5] drm/xe/soc_remapper: Use SoC remapper herlper from VSEC code

[Anoop, Vijay]

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Since different drivers can use SoC remapper, modify VSEC code to
access SoC remapper via a helper that would synchronize such accesses.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_pmt.h               |  3 ---
 drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h | 13 +++++++++++++
 drivers/gpu/drm/xe/xe_soc_remapper.c           | 18 ++++++++++++++++++
 drivers/gpu/drm/xe/xe_soc_remapper.h           |  1 +
 drivers/gpu/drm/xe/xe_vsec.c                   |  4 ++--
 5 files changed, 34 insertions(+), 5 deletions(-)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h

diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
index 0f79c0714454..240d57993ea6 100644
--- a/drivers/gpu/drm/xe/regs/xe_pmt.h
+++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
@@ -18,9 +18,6 @@
 #define BMG_TELEMETRY_BASE_OFFSET	0xE0000
 #define BMG_TELEMETRY_OFFSET		(SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
 
-#define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
-#define   SG_REMAP_BITS			REG_GENMASK(31, 24)
-
 #define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)
 #define BMG_G2_RESIDENCY_OFFSET		(0x530)
 #define BMG_G6_RESIDENCY_OFFSET		(0x538)
diff --git a/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h b/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
new file mode 100644
index 000000000000..9edf234227a9
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+#ifndef _XE_SOC_REMAPPER_REGS_H_
+#define _XE_SOC_REMAPPER_REGS_H_
+
+#include "xe_regs.h"
+
+#define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
+#define   SG_REMAP_TELEM_MASK		REG_GENMASK(31, 24)
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.c b/drivers/gpu/drm/xe/xe_soc_remapper.c
index f5a02abd6ab1..85d37a86117a 100644
--- a/drivers/gpu/drm/xe/xe_soc_remapper.c
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.c
@@ -5,8 +5,26 @@
 
 #include <linux/spinlock.h>
 
+#include "regs/xe_soc_remapper_regs.h"
+#include "xe_mmio.h"
 #include "xe_soc_remapper.h"
 
+static void xe_soc_remapper_set_region(struct xe_device *xe, struct xe_reg reg,
+				       u32 mask, u32 val)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&xe->soc_remapper.lock, flags);
+	xe_mmio_rmw32(xe_root_tile_mmio(xe), reg, mask, val);
+	spin_unlock_irqrestore(&xe->soc_remapper.lock, flags);
+}
+
+void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index)
+{
+	xe_soc_remapper_set_region(xe, SG_REMAP_INDEX1, SG_REMAP_TELEM_MASK,
+				   REG_FIELD_PREP(SG_REMAP_TELEM_MASK, index));
+}
+
 int xe_soc_remapper_init(struct xe_device *xe)
 {
 	spin_lock_init(&xe->soc_remapper.lock);
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.h b/drivers/gpu/drm/xe/xe_soc_remapper.h
index 3cfd44f1fd74..75431b94e66a 100644
--- a/drivers/gpu/drm/xe/xe_soc_remapper.h
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.h
@@ -11,5 +11,6 @@
 #include "xe_device_types.h"
 
 int xe_soc_remapper_init(struct xe_device *xe);
+void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c
index 8f23a27871b6..3e217fb75394 100644
--- a/drivers/gpu/drm/xe/xe_vsec.c
+++ b/drivers/gpu/drm/xe/xe_vsec.c
@@ -16,6 +16,7 @@
 #include "xe_mmio.h"
 #include "xe_platform_types.h"
 #include "xe_pm.h"
+#include "xe_soc_remapper.h"
 #include "xe_vsec.h"
 
 #include "regs/xe_pmt.h"
@@ -163,8 +164,7 @@ int xe_pmt_telem_read(struct pci_dev *pdev, u32 guid, u64 *data, loff_t user_off
 		return -ENODATA;
 
 	/* set SoC re-mapper index register based on GUID memory region */
-	xe_mmio_rmw32(xe_root_tile_mmio(xe), SG_REMAP_INDEX1, SG_REMAP_BITS,
-		      REG_FIELD_PREP(SG_REMAP_BITS, mem_region));
+	xe_soc_remapper_set_telem_region(xe, mem_region);
 
 	memcpy_fromio(data, telem_addr, count);
 	xe_pm_runtime_put(xe);
-- 
2.43.0

[RFC 3/5] drm/xe/soc_remapper: Add system controller config for SoC remapper

[Anoop, Vijay]

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Define system controller config bits and helpers for SoC remapper.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h | 1 +
 drivers/gpu/drm/xe/xe_soc_remapper.c           | 6 ++++++
 drivers/gpu/drm/xe/xe_soc_remapper.h           | 1 +
 3 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h b/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
index 9edf234227a9..be0eb37e73ad 100644
--- a/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
@@ -9,5 +9,6 @@
 
 #define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
 #define   SG_REMAP_TELEM_MASK		REG_GENMASK(31, 24)
+#define   SG_REMAP_SYSCTRL_MASK		REG_GENMASK(23, 16)
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.c b/drivers/gpu/drm/xe/xe_soc_remapper.c
index 85d37a86117a..ed6b6c594e51 100644
--- a/drivers/gpu/drm/xe/xe_soc_remapper.c
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.c
@@ -25,6 +25,12 @@ void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index)
 				   REG_FIELD_PREP(SG_REMAP_TELEM_MASK, index));
 }
 
+void xe_soc_remapper_set_sysctrl_region(struct xe_device *xe, u32 index)
+{
+	xe_soc_remapper_set_region(xe, SG_REMAP_INDEX1, SG_REMAP_SYSCTRL_MASK,
+				   REG_FIELD_PREP(SG_REMAP_SYSCTRL_MASK, index));
+}
+
 int xe_soc_remapper_init(struct xe_device *xe)
 {
 	spin_lock_init(&xe->soc_remapper.lock);
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.h b/drivers/gpu/drm/xe/xe_soc_remapper.h
index 75431b94e66a..289aa41c3408 100644
--- a/drivers/gpu/drm/xe/xe_soc_remapper.h
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.h
@@ -12,5 +12,6 @@
 
 int xe_soc_remapper_init(struct xe_device *xe);
 void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index);
+void xe_soc_remapper_set_sysctrl_region(struct xe_device *xe, u32 index);
 
 #endif
-- 
2.43.0

[RFC 4/5] drm/xe/remapper: Reprogram remapper index on PM resume events

[Anoop, Vijay]

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Device enters the D3 cold state during both runtime and system suspend,
which requires reprogramming the SoC re-mapper index

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/xe/xe_device_types.h |  6 ++++++
 drivers/gpu/drm/xe/xe_pm.c           |  5 +++++
 drivers/gpu/drm/xe/xe_soc_remapper.c | 17 ++++++++++++++++-
 drivers/gpu/drm/xe/xe_soc_remapper.h |  1 +
 4 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 4d23b75bc728..3f118c64a124 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -556,6 +556,12 @@ struct xe_device {
 	struct {
 		/* Serialize access to SoC Remapper's index registers */
 		spinlock_t lock;
+
+		/* Last value of INDEX1 register */
+		u32 state;
+
+		/* A flag indicating state is initialized */
+		bool state_initialized;
 	} soc_remapper;
 
 	/**
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index ad92a142dc7e..2196c21c4bb1 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -24,6 +24,7 @@
 #include "xe_late_bind_fw.h"
 #include "xe_pcode.h"
 #include "xe_pxp.h"
+#include "xe_soc_remapper.h"
 #include "xe_sriov_vf_ccs.h"
 #include "xe_trace.h"
 #include "xe_vm.h"
@@ -236,6 +237,8 @@ int xe_pm_resume(struct xe_device *xe)
 	drm_dbg(&xe->drm, "Resuming device\n");
 	trace_xe_pm_resume(xe, __builtin_return_address(0));
 
+	xe_soc_remapper_resume(xe);
+
 	for_each_gt(gt, xe, id)
 		xe_gt_idle_disable_c6(gt);
 
@@ -629,6 +632,8 @@ int xe_pm_runtime_resume(struct xe_device *xe)
 
 	xe_rpm_lockmap_acquire(xe);
 
+	xe_soc_remapper_resume(xe);
+
 	for_each_gt(gt, xe, id)
 		xe_gt_idle_disable_c6(gt);
 
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.c b/drivers/gpu/drm/xe/xe_soc_remapper.c
index ed6b6c594e51..c425195f7152 100644
--- a/drivers/gpu/drm/xe/xe_soc_remapper.c
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.c
@@ -13,9 +13,12 @@ static void xe_soc_remapper_set_region(struct xe_device *xe, struct xe_reg reg,
 				       u32 mask, u32 val)
 {
 	unsigned long flags;
+	u32 old;
 
 	spin_lock_irqsave(&xe->soc_remapper.lock, flags);
-	xe_mmio_rmw32(xe_root_tile_mmio(xe), reg, mask, val);
+	old = xe_mmio_rmw32(xe_root_tile_mmio(xe), reg, mask, val);
+	xe->soc_remapper.state = (old & ~mask) | val;
+	xe->soc_remapper.state_initialized = true;
 	spin_unlock_irqrestore(&xe->soc_remapper.lock, flags);
 }
 
@@ -31,6 +34,18 @@ void xe_soc_remapper_set_sysctrl_region(struct xe_device *xe, u32 index)
 				   REG_FIELD_PREP(SG_REMAP_SYSCTRL_MASK, index));
 }
 
+void xe_soc_remapper_resume(struct xe_device *xe)
+{
+	unsigned long flags;
+
+	if (!xe->soc_remapper.state_initialized)
+		return;
+
+	spin_lock_irqsave(&xe->soc_remapper.lock, flags);
+	xe_mmio_write32(xe_root_tile_mmio(xe), SG_REMAP_INDEX1, xe->soc_remapper.state);
+	spin_unlock_irqrestore(&xe->soc_remapper.lock, flags);
+}
+
 int xe_soc_remapper_init(struct xe_device *xe)
 {
 	spin_lock_init(&xe->soc_remapper.lock);
diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.h b/drivers/gpu/drm/xe/xe_soc_remapper.h
index 289aa41c3408..507701c74f6f 100644
--- a/drivers/gpu/drm/xe/xe_soc_remapper.h
+++ b/drivers/gpu/drm/xe/xe_soc_remapper.h
@@ -13,5 +13,6 @@
 int xe_soc_remapper_init(struct xe_device *xe);
 void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index);
 void xe_soc_remapper_set_sysctrl_region(struct xe_device *xe, u32 index);
+void xe_soc_remapper_resume(struct xe_device *xe);
 
 #endif
-- 
2.43.0

[RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Anoop, Vijay]

From: Anoop Vijay <anoop.c.vijay@intel.com>

Add a new system controller (SC) component for Intel Xe3p dGPU platforms.

This component provides the foundational infrastructure for communication
with the SC firmware using the MKHI protocol over a mailbox interface.

Key features introduced:
- Detection and initialization of the SC interface on Xe3p dGPU platforms
- Mailbox communication with SC firmware
- Fragmented message transfer for large command payloads

This implementation establishes the base for future SC feature
enablement and firmware command handling.

Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
---
 drivers/gpu/drm/xe/Makefile          |   2 +
 drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
 drivers/gpu/drm/xe/xe_device.c       |   5 +
 drivers/gpu/drm/xe/xe_device_types.h |   5 +
 drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
 drivers/gpu/drm/xe/xe_sc.h           |  15 ++
 drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
 drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
 drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
 9 files changed, 635 insertions(+)
 create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
 create mode 100644 drivers/gpu/drm/xe/xe_sc.c
 create mode 100644 drivers/gpu/drm/xe/xe_sc.h
 create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
 create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
 create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h

diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 7ebfbf9051bf..50e8dc86d915 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -114,7 +114,9 @@ xe-y += xe_bb.o \
 	xe_ring_ops.o \
 	xe_rtp.o \
 	xe_sa.o \
+	xe_sc.o \
 	xe_sched_job.o \
+	xe_sc_mailbox.o \
 	xe_shrinker.o \
 	xe_step.o \
 	xe_survivability_mode.o \
diff --git a/drivers/gpu/drm/xe/regs/xe_sc_regs.h b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
new file mode 100644
index 000000000000..2b7053586197
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SC_REGS_H_
+#define _XE_SC_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET		0xDB000
+#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX		0x03
+#define SC_BAR_LENGTH			0x1000
+
+#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
+#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
+#define   SC_MB_CTRL_IRQ		REG_BIT(30)
+#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
+#define   SC_MB_CTRL_PARAM3		REG_GENMASK(28, 24)
+#define   SC_MB_CTRL_PARAM2		REG_GENMASK(23, 16)
+#define   SC_MB_CTRL_PARAM1		REG_GENMASK(15, 8)
+#define   SC_MB_CTRL_COMMAND		REG_GENMASK(7, 0)
+
+#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
+#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
+#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
+#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
+
+#define MKHI_FRAME_PHASE		REG_BIT(24)
+#define MKHI_FRAME_CURRENT		REG_GENMASK(21, 16)
+#define MKHI_FRAME_TOTAL		REG_GENMASK(13, 8)
+#define MKHI_FRAME_COMMAND		REG_GENMASK(7, 0)
+
+#define MKHI_HDR_RESULT			REG_GENMASK(31, 24)
+#define MKHI_HDR_IS_RESPONSE		REG_BIT(15)
+#define MKHI_HDR_COMMAND		REG_GENMASK(14, 8)
+#define MKHI_HDR_GROUP_ID		REG_GENMASK(7, 0)
+
+#define SC_MB_FRAME_SIZE		16
+#define SC_MB_MAX_FRAMES		64
+#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
+#define SC_MKHI_COMMAND			5
+
+#define SC_MB_DEFAULT_TIMEOUT_MS	500
+#define SC_MB_RETRY_TIMEOUT_MS		20
+#define SC_MB_POLL_INTERVAL_US		100
+
+#endif /* _XE_SC_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index f15489c100af..9fbd0b084c74 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -60,6 +60,7 @@
 #include "xe_psmi.h"
 #include "xe_pxp.h"
 #include "xe_query.h"
+#include "xe_sc.h"
 #include "xe_soc_remapper.h"
 #include "xe_shrinker.h"
 #include "xe_survivability_mode.h"
@@ -963,6 +964,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err_unregister_display;
 
+	err = xe_sc_init(xe);
+	if (err)
+		goto err_unregister_display;
+
 	for_each_gt(gt, xe, id)
 		xe_gt_sanitize_freq(gt);
 
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 3f118c64a124..86a0c83c802d 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -314,6 +314,8 @@ struct xe_device {
 		u8 has_range_tlb_inval:1;
 		/** @info.has_sriov: Supports SR-IOV */
 		u8 has_sriov:1;
+		/** @info.has_sysctrl: Supports System Controller */
+		u8 has_sysctrl:1;
 		/** @info.has_usm: Device has unified shared memory support */
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -576,6 +578,9 @@ struct xe_device {
 	/** @heci_gsc: graphics security controller */
 	struct xe_heci_gsc heci_gsc;
 
+	/** @sc: System Controller */
+	struct xe_sc *sc;
+
 	/** @nvm: discrete graphics non-volatile memory */
 	struct intel_dg_nvm_dev *nvm;
 
diff --git a/drivers/gpu/drm/xe/xe_sc.c b/drivers/gpu/drm/xe/xe_sc.c
new file mode 100644
index 000000000000..18448efc173f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sc.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include "xe_sc.h"
+
+#include <linux/mutex.h>
+
+#include <drm/drm_managed.h>
+#include <drm/drm_print.h>
+
+#include "regs/xe_sc_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_platform_types.h"
+#include "xe_soc_remapper.h"
+#include "xe_sc_types.h"
+#include "xe_tile.h"
+
+static void xe_sc_remove(struct drm_device *drm, void *arg)
+{
+	struct xe_sc *sc = arg;
+	struct xe_device *xe;
+
+	if (!sc)
+		return;
+
+	xe = to_xe_device(drm);
+
+	mutex_destroy(&sc->cmd_lock);
+
+	xe_soc_remapper_set_sysctrl_region(xe, 0);
+
+	xe->sc = NULL;
+}
+
+static int xe_sc_probe(struct xe_device *xe)
+{
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+	struct xe_sc *sc;
+	int ret;
+
+	sc = drmm_kzalloc(&xe->drm, sizeof(*sc), GFP_KERNEL);
+	if (!sc)
+		return -ENOMEM;
+
+	sc->xe = xe;
+	xe->sc = sc;
+
+	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
+	if (ret) {
+		xe->sc = NULL;
+		return ret;
+	}
+
+	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
+
+	mutex_init(&sc->cmd_lock);
+
+	sc->phase_bit = 0;
+
+	return 0;
+}
+
+/**
+ * xe_sc_init - Initialize SC subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for SC initialization, called from xe_device_probe().
+ * This function checks platform support and calls the main probe function.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sc_init(struct xe_device *xe)
+{
+	int ret;
+
+	if (!xe->info.has_sysctrl)
+		return 0;
+
+	ret = xe_sc_probe(xe);
+	if (ret)
+		drm_err(&xe->drm, "sysctrl: Probe failed: %d\n", ret);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_sc.h b/drivers/gpu/drm/xe/xe_sc.h
new file mode 100644
index 000000000000..0e5c89ddc957
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sc.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __XE_SC_H__
+#define __XE_SC_H__
+
+#include <linux/types.h>
+
+struct xe_device;
+
+int xe_sc_init(struct xe_device *xe);
+
+#endif /* __XE_SC_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.c b/drivers/gpu/drm/xe/xe_sc_mailbox.c
new file mode 100644
index 000000000000..6f2500c63a3c
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sc_mailbox.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/errno.h>
+#include <linux/minmax.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/types.h>
+
+#include <drm/drm_print.h>
+
+#include "regs/xe_sc_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_sc.h"
+#include "xe_sc_mailbox.h"
+#include "xe_sc_types.h"
+
+static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
+				 unsigned int timeout_ms)
+{
+	int ret;
+
+	if (timeout_ms == 0) {
+		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
+					 0, NULL, false);
+	} else {
+		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
+					 timeout_ms * 1000, NULL, false);
+	}
+
+	return ret == 0;
+}
+
+static bool sc_mb_wait_bit_set(struct xe_sc *sc, u32 bit_mask,
+			       unsigned int timeout_ms)
+{
+	int ret;
+
+	if (timeout_ms == 0) {
+		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
+				     0, NULL, false);
+	} else {
+		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
+				     timeout_ms * 1000, NULL, false);
+	}
+
+	return ret == 0;
+}
+
+static void sc_mb_write_frame(struct xe_sc *sc, const void *buffer,
+			      size_t offset)
+{
+	const u32 *data = (const u32 *)((const u8 *)buffer + offset);
+
+	xe_mmio_write32(&sc->mmio, SC_MB_DATA0, data[0]);
+	xe_mmio_write32(&sc->mmio, SC_MB_DATA1, data[1]);
+	xe_mmio_write32(&sc->mmio, SC_MB_DATA2, data[2]);
+	xe_mmio_write32(&sc->mmio, SC_MB_DATA3, data[3]);
+}
+
+static void sc_mb_read_frame(struct xe_sc *sc, void *buffer,
+			     size_t offset)
+{
+	u32 *data = (u32 *)((u8 *)buffer + offset);
+
+	data[0] = xe_mmio_read32(&sc->mmio, SC_MB_DATA0);
+	data[1] = xe_mmio_read32(&sc->mmio, SC_MB_DATA1);
+	data[2] = xe_mmio_read32(&sc->mmio, SC_MB_DATA2);
+	data[3] = xe_mmio_read32(&sc->mmio, SC_MB_DATA3);
+}
+
+static void sc_mb_clear_response(struct xe_sc *sc)
+{
+	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);
+}
+
+static int sc_mb_prepare_command(struct xe_sc *sc,
+				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
+				 const void *data_in, size_t data_in_len,
+				 u8 **cmd_buffer, size_t *cmd_size)
+{
+	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
+
+	mkhi_hdr.group_id = msg_hdr->group_id;
+	mkhi_hdr.command = msg_hdr->command & 0x7F;
+	mkhi_hdr.is_response = 0;
+	mkhi_hdr.reserved = 0;
+	mkhi_hdr.result = 0;
+
+	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;
+
+	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
+		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
+			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
+		return -EINVAL;
+	}
+
+	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
+	if (!*cmd_buffer)
+		return -ENOMEM;
+
+	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));
+	if (data_in && data_in_len)
+		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
+		       data_in, data_in_len);
+
+	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
+		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
+
+	return 0;
+}
+
+static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
+			     size_t cmd_size, unsigned int timeout_ms)
+{
+	u32 ctrl_reg, total_frames, current_frame;
+	size_t bytes_sent, bytes_to_send;
+
+	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
+	if (total_frames > SC_MB_MAX_FRAMES) {
+		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
+			cmd_size, total_frames, SC_MB_MAX_FRAMES);
+		return -EINVAL;
+	}
+
+	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
+		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
+		return -EBUSY;
+	}
+
+	sc->phase_bit ^= 1;
+
+	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
+		cmd_size, total_frames, sc->phase_bit);
+
+	bytes_sent = 0;
+	for (current_frame = 0; current_frame < total_frames; current_frame++) {
+		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
+
+		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);
+
+		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
+			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
+			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
+			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
+		if (sc->phase_bit)
+			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
+
+		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
+
+		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
+			current_frame, total_frames - 1);
+
+		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
+			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
+				current_frame);
+			return -ETIMEDOUT;
+		}
+
+		bytes_sent += bytes_to_send;
+	}
+
+	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
+	return 0;
+}
+
+static int sc_mb_validate_response_header(struct xe_sc *sc,
+					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
+					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
+{
+	if (!resp_hdr->is_response ||
+	    resp_hdr->group_id != msg_hdr->group_id ||
+	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
+		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
+		return -EPROTO;
+	}
+
+	if (resp_hdr->result != 0) {
+		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
+			resp_hdr->result);
+		return -EIO;
+	}
+
+	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
+		resp_hdr->group_id, resp_hdr->command);
+
+	return 0;
+}
+
+static int sc_mb_receive_frames(struct xe_sc *sc,
+				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
+				void *data_out, size_t data_out_len,
+				size_t *bytes_received, unsigned int timeout_ms)
+{
+	u32 ctrl_reg, total_frames, current_frame;
+	size_t payload_size;
+	int ret;
+
+	*bytes_received = 0;
+
+	do {
+		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
+		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
+		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
+
+		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
+			current_frame, total_frames - 1);
+
+		if (current_frame == 0) {
+			u32 temp_frame[4];
+			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
+
+			sc_mb_read_frame(sc, temp_frame, 0);
+			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
+
+			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
+			if (ret)
+				return ret;
+
+			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
+			if (payload_size > data_out_len) {
+				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
+				return -ENOSPC;
+			}
+
+			memcpy(data_out,
+			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
+			       payload_size);
+			*bytes_received = payload_size;
+		} else {
+			size_t frame_size = SC_MB_FRAME_SIZE;
+
+			if (current_frame == total_frames - 1) {
+				size_t total_response = (total_frames - 1) *
+							SC_MB_FRAME_SIZE +
+							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
+				size_t remaining = total_response -
+						   *bytes_received -
+						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
+				frame_size = min(frame_size, remaining);
+			}
+
+			if (*bytes_received + frame_size > data_out_len) {
+				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
+				return -ENOSPC;
+			}
+
+			sc_mb_read_frame(sc, data_out, *bytes_received);
+			*bytes_received += frame_size;
+		}
+
+		sc_mb_clear_response(sc);
+
+		if (current_frame + 1 < total_frames &&
+		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
+				current_frame + 1);
+			return -ETIMEDOUT;
+		}
+
+	} while (current_frame + 1 < total_frames);
+
+	return 0;
+}
+
+static int sc_mb_send_command(struct xe_sc *sc,
+			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
+			      const u8 *cmd_buffer, size_t cmd_size,
+			      void *data_out, size_t data_out_len,
+			      size_t *rdata_len, unsigned int timeout_ms)
+{
+	size_t bytes_received;
+	int ret;
+
+	if (rdata_len)
+		*rdata_len = 0;
+
+	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
+	if (ret)
+		return ret;
+
+	if (!data_out) {
+		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
+		return 0;
+	}
+
+	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
+		return -ETIMEDOUT;
+	}
+
+	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
+				   &bytes_received, timeout_ms);
+	if (ret) {
+		sc_mb_clear_response(sc);
+		return ret;
+	}
+
+	if (rdata_len)
+		*rdata_len = bytes_received;
+
+	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
+		bytes_received);
+
+	return 0;
+}
+
+/**
+ * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
+ * @handle: XE device handle containing the system controller
+ * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
+ * @rdata_len: Pointer to store actual response data size (can be NULL)
+ *
+ * Send a command to the System Controller using MKHI protocol. Handles
+ * command preparation, fragmentation, transmission, and response reception.
+ * Optimized to move memory allocation outside the critical section.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
+{
+	struct xe_device *xe = handle;
+	struct xe_sc *sc;
+	struct xe_sc_mailbox_command *cmd = cmd_buffer;
+	u8 *command_buffer = NULL;
+	size_t command_size;
+	int ret;
+
+	if (!xe || !cmd)
+		return -EINVAL;
+
+	sc = xe->sc;
+	if (!sc)
+		return -ENODEV;
+
+	if (!cmd->data_in && cmd->data_in_len)
+		return -EINVAL;
+
+	if (!cmd->data_out && cmd->data_out_len)
+		return -EINVAL;
+
+	might_sleep();
+
+	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
+				    &command_buffer, &command_size);
+	if (ret) {
+		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
+		return ret;
+	}
+
+	mutex_lock(&sc->cmd_lock);
+
+	xe_pm_runtime_get(xe);
+
+	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
+				 cmd->data_out, cmd->data_out_len, rdata_len,
+				 SC_MB_DEFAULT_TIMEOUT_MS);
+	if (ret)
+		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
+
+	xe_pm_runtime_put(xe);
+
+	mutex_unlock(&sc->cmd_lock);
+
+	kfree(command_buffer);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
new file mode 100644
index 000000000000..d5ca43c40f1a
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __XE_SC_MAILBOX_H__
+#define __XE_SC_MAILBOX_H__
+
+#include <linux/types.h>
+
+struct xe_sc;
+
+/**
+ * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
+ */
+struct xe_sc_mailbox_mkhi_msg_hdr {
+	/** @group_id: Message group identifier */
+	u32 group_id    : 8;
+	/** @command: Command identifier within the group */
+	u32 command     : 7;
+	/** @is_response: Response flag - 0 for request, 1 for response */
+	u32 is_response : 1;
+	/** @reserved: Reserved field, must be zero */
+	u32 reserved    : 8;
+	/** @result: Result code from firmware */
+	u32 result      : 8;
+} __packed;
+
+/**
+ * struct xe_sc_mailbox_app_msg_hdr - Application message header
+ */
+struct xe_sc_mailbox_app_msg_hdr {
+	/** @group_id: Application group identifier */
+	u32 group_id  : 8;
+	/** @command: Specific command within the application group */
+	u32 command   : 8;
+	/** @version: Protocol version */
+	u32 version   : 8;
+	/** @reserved: Reserved field, must be zero */
+	u32 reserved  : 8;
+} __packed;
+
+/**
+ * struct xe_sc_mailbox_command - System Controller mailbox command structure
+ */
+struct xe_sc_mailbox_command {
+	/** @header: Application message header containing command information */
+	struct xe_sc_mailbox_app_msg_hdr header;
+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
+	void *data_in;
+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
+	size_t data_in_len;
+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+	void *data_out;
+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+	size_t data_out_len;
+};
+
+int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
+
+#endif /* __XE_SC_MAILBOX_H__ */
diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
new file mode 100644
index 000000000000..5ec2126cebe4
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sc_types.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef _XE_SC_TYPES_H_
+#define _XE_SC_TYPES_H_
+
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "xe_device_types.h"
+#include "xe_sc_mailbox.h"
+
+struct xe_device;
+
+/**
+ * struct xe_sc - System Controller driver context
+ */
+struct xe_sc {
+	/** @xe: Back pointer to xe_device */
+	struct xe_device *xe;
+	/** @mmio: MMIO region for SC registers */
+	struct xe_mmio mmio;
+
+	/** @cmd_lock: Mutex protecting mailbox command operations */
+	struct mutex cmd_lock;
+
+	/** @phase_bit: MKHI message boundary phase toggle bit */
+	u32 phase_bit;
+};
+
+#endif /* _XE_SC_TYPES_H_ */
-- 
2.43.0

Re: [RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Matthew Brost]

On Fri, Nov 21, 2025 at 08:58:07PM -0800, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Add a new system controller (SC) component for Intel Xe3p dGPU platforms.
> 
> This component provides the foundational infrastructure for communication
> with the SC firmware using the MKHI protocol over a mailbox interface.
> 
> Key features introduced:
> - Detection and initialization of the SC interface on Xe3p dGPU platforms
> - Mailbox communication with SC firmware
> - Fragmented message transfer for large command payloads
> 
> This implementation establishes the base for future SC feature
> enablement and firmware command handling.
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
>  drivers/gpu/drm/xe/Makefile          |   2 +
>  drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
>  drivers/gpu/drm/xe/xe_device.c       |   5 +
>  drivers/gpu/drm/xe/xe_device_types.h |   5 +
>  drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
>  drivers/gpu/drm/xe/xe_sc.h           |  15 ++
>  drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
>  drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
>  9 files changed, 635 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
>  create mode 100644 drivers/gpu/drm/xe/xe_sc.c
>  create mode 100644 drivers/gpu/drm/xe/xe_sc.h
>  create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
>  create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
>  create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 7ebfbf9051bf..50e8dc86d915 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -114,7 +114,9 @@ xe-y += xe_bb.o \
>  	xe_ring_ops.o \
>  	xe_rtp.o \
>  	xe_sa.o \
> +	xe_sc.o \
>  	xe_sched_job.o \
> +	xe_sc_mailbox.o \
>  	xe_shrinker.o \
>  	xe_step.o \
>  	xe_survivability_mode.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_sc_regs.h b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> new file mode 100644
> index 000000000000..2b7053586197
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SC_REGS_H_
> +#define _XE_SC_REGS_H_
> +
> +#include "xe_regs.h"
> +
> +#define SYSCTRL_BASE_OFFSET		0xDB000
> +#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
> +#define SYSCTRL_MAILBOX_INDEX		0x03
> +#define SC_BAR_LENGTH			0x1000
> +
> +#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
> +#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
> +#define   SC_MB_CTRL_IRQ		REG_BIT(30)
> +#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
> +#define   SC_MB_CTRL_PARAM3		REG_GENMASK(28, 24)
> +#define   SC_MB_CTRL_PARAM2		REG_GENMASK(23, 16)
> +#define   SC_MB_CTRL_PARAM1		REG_GENMASK(15, 8)
> +#define   SC_MB_CTRL_COMMAND		REG_GENMASK(7, 0)
> +
> +#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
> +#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
> +#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
> +#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
> +
> +#define MKHI_FRAME_PHASE		REG_BIT(24)
> +#define MKHI_FRAME_CURRENT		REG_GENMASK(21, 16)
> +#define MKHI_FRAME_TOTAL		REG_GENMASK(13, 8)
> +#define MKHI_FRAME_COMMAND		REG_GENMASK(7, 0)
> +
> +#define MKHI_HDR_RESULT			REG_GENMASK(31, 24)
> +#define MKHI_HDR_IS_RESPONSE		REG_BIT(15)
> +#define MKHI_HDR_COMMAND		REG_GENMASK(14, 8)
> +#define MKHI_HDR_GROUP_ID		REG_GENMASK(7, 0)
> +
> +#define SC_MB_FRAME_SIZE		16
> +#define SC_MB_MAX_FRAMES		64
> +#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
> +#define SC_MKHI_COMMAND			5
> +
> +#define SC_MB_DEFAULT_TIMEOUT_MS	500
> +#define SC_MB_RETRY_TIMEOUT_MS		20
> +#define SC_MB_POLL_INTERVAL_US		100
> +
> +#endif /* _XE_SC_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index f15489c100af..9fbd0b084c74 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -60,6 +60,7 @@
>  #include "xe_psmi.h"
>  #include "xe_pxp.h"
>  #include "xe_query.h"
> +#include "xe_sc.h"
>  #include "xe_soc_remapper.h"
>  #include "xe_shrinker.h"
>  #include "xe_survivability_mode.h"
> @@ -963,6 +964,10 @@ int xe_device_probe(struct xe_device *xe)
>  	if (err)
>  		goto err_unregister_display;
>  
> +	err = xe_sc_init(xe);
> +	if (err)
> +		goto err_unregister_display;
> +
>  	for_each_gt(gt, xe, id)
>  		xe_gt_sanitize_freq(gt);
>  
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 3f118c64a124..86a0c83c802d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -314,6 +314,8 @@ struct xe_device {
>  		u8 has_range_tlb_inval:1;
>  		/** @info.has_sriov: Supports SR-IOV */
>  		u8 has_sriov:1;
> +		/** @info.has_sysctrl: Supports System Controller */
> +		u8 has_sysctrl:1;
>  		/** @info.has_usm: Device has unified shared memory support */
>  		u8 has_usm:1;
>  		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
> @@ -576,6 +578,9 @@ struct xe_device {
>  	/** @heci_gsc: graphics security controller */
>  	struct xe_heci_gsc heci_gsc;
>  
> +	/** @sc: System Controller */
> +	struct xe_sc *sc;
> +
>  	/** @nvm: discrete graphics non-volatile memory */
>  	struct intel_dg_nvm_dev *nvm;
>  
> diff --git a/drivers/gpu/drm/xe/xe_sc.c b/drivers/gpu/drm/xe/xe_sc.c
> new file mode 100644
> index 000000000000..18448efc173f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "xe_sc.h"
> +
> +#include <linux/mutex.h>
> +
> +#include <drm/drm_managed.h>
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_sc_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_platform_types.h"
> +#include "xe_soc_remapper.h"
> +#include "xe_sc_types.h"
> +#include "xe_tile.h"
> +
> +static void xe_sc_remove(struct drm_device *drm, void *arg)
> +{
> +	struct xe_sc *sc = arg;
> +	struct xe_device *xe;
> +
> +	if (!sc)
> +		return;
> +
> +	xe = to_xe_device(drm);
> +
> +	mutex_destroy(&sc->cmd_lock);
> +
> +	xe_soc_remapper_set_sysctrl_region(xe, 0);
> +
> +	xe->sc = NULL;
> +}
> +
> +static int xe_sc_probe(struct xe_device *xe)
> +{
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +	struct xe_sc *sc;
> +	int ret;
> +
> +	sc = drmm_kzalloc(&xe->drm, sizeof(*sc), GFP_KERNEL);
> +	if (!sc)
> +		return -ENOMEM;
> +
> +	sc->xe = xe;
> +	xe->sc = sc;
> +
> +	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
> +	if (ret) {
> +		xe->sc = NULL;
> +		return ret;
> +	}
> +
> +	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> +
> +	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
> +
> +	mutex_init(&sc->cmd_lock);
> +
> +	sc->phase_bit = 0;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sc_init - Initialize SC subsystem
> + * @xe: xe device instance
> + *
> + * Entry point for SC initialization, called from xe_device_probe().
> + * This function checks platform support and calls the main probe function.
> + *
> + * Return: 0 on success, error code on failure
> + */
> +int xe_sc_init(struct xe_device *xe)
> +{
> +	int ret;
> +
> +	if (!xe->info.has_sysctrl)
> +		return 0;
> +
> +	ret = xe_sc_probe(xe);
> +	if (ret)
> +		drm_err(&xe->drm, "sysctrl: Probe failed: %d\n", ret);
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sc.h b/drivers/gpu/drm/xe/xe_sc.h
> new file mode 100644
> index 000000000000..0e5c89ddc957
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __XE_SC_H__
> +#define __XE_SC_H__
> +
> +#include <linux/types.h>
> +
> +struct xe_device;
> +
> +int xe_sc_init(struct xe_device *xe);
> +
> +#endif /* __XE_SC_H__ */
> diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.c b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> new file mode 100644
> index 000000000000..6f2500c63a3c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> @@ -0,0 +1,374 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/errno.h>
> +#include <linux/minmax.h>
> +#include <linux/mutex.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_sc_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_pm.h"
> +#include "xe_sc.h"
> +#include "xe_sc_mailbox.h"
> +#include "xe_sc_types.h"
> +
> +static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
> +				 unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	if (timeout_ms == 0) {
> +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +					 0, NULL, false);
> +	} else {
> +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +					 timeout_ms * 1000, NULL, false);
> +	}
> +
> +	return ret == 0;
> +}
> +
> +static bool sc_mb_wait_bit_set(struct xe_sc *sc, u32 bit_mask,
> +			       unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	if (timeout_ms == 0) {
> +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +				     0, NULL, false);
> +	} else {
> +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +				     timeout_ms * 1000, NULL, false);
> +	}
> +
> +	return ret == 0;
> +}
> +
> +static void sc_mb_write_frame(struct xe_sc *sc, const void *buffer,
> +			      size_t offset)
> +{
> +	const u32 *data = (const u32 *)((const u8 *)buffer + offset);
> +
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA0, data[0]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA1, data[1]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA2, data[2]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA3, data[3]);
> +}
> +
> +static void sc_mb_read_frame(struct xe_sc *sc, void *buffer,
> +			     size_t offset)
> +{
> +	u32 *data = (u32 *)((u8 *)buffer + offset);
> +
> +	data[0] = xe_mmio_read32(&sc->mmio, SC_MB_DATA0);
> +	data[1] = xe_mmio_read32(&sc->mmio, SC_MB_DATA1);
> +	data[2] = xe_mmio_read32(&sc->mmio, SC_MB_DATA2);
> +	data[3] = xe_mmio_read32(&sc->mmio, SC_MB_DATA3);
> +}
> +
> +static void sc_mb_clear_response(struct xe_sc *sc)
> +{
> +	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);
> +}
> +
> +static int sc_mb_prepare_command(struct xe_sc *sc,
> +				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +				 const void *data_in, size_t data_in_len,
> +				 u8 **cmd_buffer, size_t *cmd_size)
> +{
> +	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
> +
> +	mkhi_hdr.group_id = msg_hdr->group_id;
> +	mkhi_hdr.command = msg_hdr->command & 0x7F;
> +	mkhi_hdr.is_response = 0;
> +	mkhi_hdr.reserved = 0;
> +	mkhi_hdr.result = 0;
> +
> +	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;
> +
> +	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
> +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
> +			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
> +		return -EINVAL;
> +	}
> +
> +	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
> +	if (!*cmd_buffer)
> +		return -ENOMEM;
> +
> +	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));
> +	if (data_in && data_in_len)
> +		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> +		       data_in, data_in_len);
> +
> +	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
> +		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
> +			     size_t cmd_size, unsigned int timeout_ms)
> +{
> +	u32 ctrl_reg, total_frames, current_frame;
> +	size_t bytes_sent, bytes_to_send;
> +
> +	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
> +	if (total_frames > SC_MB_MAX_FRAMES) {
> +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
> +			cmd_size, total_frames, SC_MB_MAX_FRAMES);
> +		return -EINVAL;
> +	}
> +
> +	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
> +		return -EBUSY;
> +	}
> +
> +	sc->phase_bit ^= 1;
> +
> +	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
> +		cmd_size, total_frames, sc->phase_bit);
> +
> +	bytes_sent = 0;
> +	for (current_frame = 0; current_frame < total_frames; current_frame++) {
> +		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
> +
> +		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);
> +
> +		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
> +			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
> +			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
> +			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
> +		if (sc->phase_bit)
> +			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
> +
> +		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
> +
> +		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
> +			current_frame, total_frames - 1);
> +
> +		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
> +				current_frame);
> +			return -ETIMEDOUT;
> +		}
> +
> +		bytes_sent += bytes_to_send;
> +	}
> +
> +	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
> +	return 0;
> +}
> +
> +static int sc_mb_validate_response_header(struct xe_sc *sc,
> +					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
> +{
> +	if (!resp_hdr->is_response ||
> +	    resp_hdr->group_id != msg_hdr->group_id ||
> +	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
> +		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
> +		return -EPROTO;
> +	}
> +
> +	if (resp_hdr->result != 0) {
> +		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
> +			resp_hdr->result);
> +		return -EIO;
> +	}
> +
> +	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
> +		resp_hdr->group_id, resp_hdr->command);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_receive_frames(struct xe_sc *sc,
> +				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +				void *data_out, size_t data_out_len,
> +				size_t *bytes_received, unsigned int timeout_ms)
> +{
> +	u32 ctrl_reg, total_frames, current_frame;
> +	size_t payload_size;
> +	int ret;
> +
> +	*bytes_received = 0;
> +
> +	do {
> +		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
> +		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
> +		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
> +
> +		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
> +			current_frame, total_frames - 1);
> +
> +		if (current_frame == 0) {
> +			u32 temp_frame[4];
> +			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
> +
> +			sc_mb_read_frame(sc, temp_frame, 0);
> +			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
> +
> +			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
> +			if (ret)
> +				return ret;
> +
> +			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +			if (payload_size > data_out_len) {
> +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> +				return -ENOSPC;
> +			}
> +
> +			memcpy(data_out,
> +			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> +			       payload_size);
> +			*bytes_received = payload_size;
> +		} else {
> +			size_t frame_size = SC_MB_FRAME_SIZE;
> +
> +			if (current_frame == total_frames - 1) {
> +				size_t total_response = (total_frames - 1) *
> +							SC_MB_FRAME_SIZE +
> +							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +				size_t remaining = total_response -
> +						   *bytes_received -
> +						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +				frame_size = min(frame_size, remaining);
> +			}
> +
> +			if (*bytes_received + frame_size > data_out_len) {
> +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> +				return -ENOSPC;
> +			}
> +
> +			sc_mb_read_frame(sc, data_out, *bytes_received);
> +			*bytes_received += frame_size;
> +		}
> +
> +		sc_mb_clear_response(sc);
> +
> +		if (current_frame + 1 < total_frames &&
> +		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
> +				current_frame + 1);
> +			return -ETIMEDOUT;
> +		}
> +
> +	} while (current_frame + 1 < total_frames);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_send_command(struct xe_sc *sc,
> +			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +			      const u8 *cmd_buffer, size_t cmd_size,
> +			      void *data_out, size_t data_out_len,
> +			      size_t *rdata_len, unsigned int timeout_ms)
> +{
> +	size_t bytes_received;
> +	int ret;
> +
> +	if (rdata_len)
> +		*rdata_len = 0;
> +
> +	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
> +	if (ret)
> +		return ret;
> +
> +	if (!data_out) {
> +		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
> +		return 0;
> +	}
> +
> +	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
> +				   &bytes_received, timeout_ms);
> +	if (ret) {
> +		sc_mb_clear_response(sc);
> +		return ret;
> +	}
> +
> +	if (rdata_len)
> +		*rdata_len = bytes_received;
> +
> +	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
> +		bytes_received);
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
> + * @handle: XE device handle containing the system controller
> + * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
> + * @rdata_len: Pointer to store actual response data size (can be NULL)
> + *
> + * Send a command to the System Controller using MKHI protocol. Handles
> + * command preparation, fragmentation, transmission, and response reception.
> + * Optimized to move memory allocation outside the critical section.
> + *
> + * Return: 0 on success, negative error code on failure
> + */
> +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
> +{
> +	struct xe_device *xe = handle;
> +	struct xe_sc *sc;
> +	struct xe_sc_mailbox_command *cmd = cmd_buffer;
> +	u8 *command_buffer = NULL;
> +	size_t command_size;
> +	int ret;
> +
> +	if (!xe || !cmd)
> +		return -EINVAL;
> +
> +	sc = xe->sc;
> +	if (!sc)
> +		return -ENODEV;
> +
> +	if (!cmd->data_in && cmd->data_in_len)
> +		return -EINVAL;
> +
> +	if (!cmd->data_out && cmd->data_out_len)
> +		return -EINVAL;
> +
> +	might_sleep();
> +
> +	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
> +				    &command_buffer, &command_size);
> +	if (ret) {
> +		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
> +		return ret;
> +	}
> +
> +	mutex_lock(&sc->cmd_lock);
> +
> +	xe_pm_runtime_get(xe);
> +

Quick drive by comment - xe_pm_runtime_get can wake the device taking a
bunch of locks. Because of that, the preferred deisgn to take this at
outer most point possible (i.e., not holding other locks), so I'd
suggest moving PM get / put outside of the cmd_lock.

> +	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
> +				 cmd->data_out, cmd->data_out_len, rdata_len,
> +				 SC_MB_DEFAULT_TIMEOUT_MS);
> +	if (ret)
> +		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
> +
> +	xe_pm_runtime_put(xe);
> +
> +	mutex_unlock(&sc->cmd_lock);
> +
> +	kfree(command_buffer);
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> new file mode 100644
> index 000000000000..d5ca43c40f1a
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __XE_SC_MAILBOX_H__
> +#define __XE_SC_MAILBOX_H__
> +
> +#include <linux/types.h>
> +
> +struct xe_sc;
> +
> +/**
> + * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
> + */
> +struct xe_sc_mailbox_mkhi_msg_hdr {
> +	/** @group_id: Message group identifier */
> +	u32 group_id    : 8;
> +	/** @command: Command identifier within the group */
> +	u32 command     : 7;
> +	/** @is_response: Response flag - 0 for request, 1 for response */
> +	u32 is_response : 1;
> +	/** @reserved: Reserved field, must be zero */
> +	u32 reserved    : 8;
> +	/** @result: Result code from firmware */
> +	u32 result      : 8;

Another quick comment - bitfields layout can based on the CPU endianess
so prefer defines + macros to set fields if this used in a wire level
protocol.

Matt

> +} __packed;
> +
> +/**
> + * struct xe_sc_mailbox_app_msg_hdr - Application message header
> + */
> +struct xe_sc_mailbox_app_msg_hdr {
> +	/** @group_id: Application group identifier */
> +	u32 group_id  : 8;
> +	/** @command: Specific command within the application group */
> +	u32 command   : 8;
> +	/** @version: Protocol version */
> +	u32 version   : 8;
> +	/** @reserved: Reserved field, must be zero */
> +	u32 reserved  : 8;
> +} __packed;
> +
> +/**
> + * struct xe_sc_mailbox_command - System Controller mailbox command structure
> + */
> +struct xe_sc_mailbox_command {
> +	/** @header: Application message header containing command information */
> +	struct xe_sc_mailbox_app_msg_hdr header;
> +	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
> +	void *data_in;
> +	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
> +	size_t data_in_len;
> +	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
> +	void *data_out;
> +	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
> +	size_t data_out_len;
> +};
> +
> +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
> +
> +#endif /* __XE_SC_MAILBOX_H__ */
> diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
> new file mode 100644
> index 000000000000..5ec2126cebe4
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_types.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SC_TYPES_H_
> +#define _XE_SC_TYPES_H_
> +
> +#include <linux/completion.h>
> +#include <linux/mutex.h>
> +#include <linux/types.h>
> +#include <linux/workqueue.h>
> +
> +#include "xe_device_types.h"
> +#include "xe_sc_mailbox.h"
> +
> +struct xe_device;
> +
> +/**
> + * struct xe_sc - System Controller driver context
> + */
> +struct xe_sc {
> +	/** @xe: Back pointer to xe_device */
> +	struct xe_device *xe;
> +	/** @mmio: MMIO region for SC registers */
> +	struct xe_mmio mmio;
> +
> +	/** @cmd_lock: Mutex protecting mailbox command operations */
> +	struct mutex cmd_lock;
> +
> +	/** @phase_bit: MKHI message boundary phase toggle bit */
> +	u32 phase_bit;
> +};
> +
> +#endif /* _XE_SC_TYPES_H_ */
> -- 
> 2.43.0
> 

Re: [RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Matthew Brost]

On Fri, Nov 21, 2025 at 09:14:13PM -0800, Matthew Brost wrote:
> On Fri, Nov 21, 2025 at 08:58:07PM -0800, Anoop, Vijay wrote:
> > From: Anoop Vijay <anoop.c.vijay@intel.com>
> > 
> > Add a new system controller (SC) component for Intel Xe3p dGPU platforms.
> > 
> > This component provides the foundational infrastructure for communication
> > with the SC firmware using the MKHI protocol over a mailbox interface.
> > 
> > Key features introduced:
> > - Detection and initialization of the SC interface on Xe3p dGPU platforms
> > - Mailbox communication with SC firmware
> > - Fragmented message transfer for large command payloads
> > 
> > This implementation establishes the base for future SC feature
> > enablement and firmware command handling.
> > 
> > Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> > ---
> >  drivers/gpu/drm/xe/Makefile          |   2 +
> >  drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
> >  drivers/gpu/drm/xe/xe_device.c       |   5 +
> >  drivers/gpu/drm/xe/xe_device_types.h |   5 +
> >  drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
> >  drivers/gpu/drm/xe/xe_sc.h           |  15 ++
> >  drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
> >  drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
> >  drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
> >  9 files changed, 635 insertions(+)
> >  create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
> >  create mode 100644 drivers/gpu/drm/xe/xe_sc.c
> >  create mode 100644 drivers/gpu/drm/xe/xe_sc.h
> >  create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
> >  create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
> >  create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h
> > 
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index 7ebfbf9051bf..50e8dc86d915 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -114,7 +114,9 @@ xe-y += xe_bb.o \
> >  	xe_ring_ops.o \
> >  	xe_rtp.o \
> >  	xe_sa.o \
> > +	xe_sc.o \
> >  	xe_sched_job.o \
> > +	xe_sc_mailbox.o \
> >  	xe_shrinker.o \
> >  	xe_step.o \
> >  	xe_survivability_mode.o \
> > diff --git a/drivers/gpu/drm/xe/regs/xe_sc_regs.h b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> > new file mode 100644
> > index 000000000000..2b7053586197
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> > @@ -0,0 +1,49 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SC_REGS_H_
> > +#define _XE_SC_REGS_H_
> > +
> > +#include "xe_regs.h"
> > +
> > +#define SYSCTRL_BASE_OFFSET		0xDB000
> > +#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
> > +#define SYSCTRL_MAILBOX_INDEX		0x03
> > +#define SC_BAR_LENGTH			0x1000
> > +
> > +#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
> > +#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
> > +#define   SC_MB_CTRL_IRQ		REG_BIT(30)
> > +#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
> > +#define   SC_MB_CTRL_PARAM3		REG_GENMASK(28, 24)
> > +#define   SC_MB_CTRL_PARAM2		REG_GENMASK(23, 16)
> > +#define   SC_MB_CTRL_PARAM1		REG_GENMASK(15, 8)
> > +#define   SC_MB_CTRL_COMMAND		REG_GENMASK(7, 0)
> > +
> > +#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
> > +#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
> > +#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
> > +#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
> > +
> > +#define MKHI_FRAME_PHASE		REG_BIT(24)
> > +#define MKHI_FRAME_CURRENT		REG_GENMASK(21, 16)
> > +#define MKHI_FRAME_TOTAL		REG_GENMASK(13, 8)
> > +#define MKHI_FRAME_COMMAND		REG_GENMASK(7, 0)
> > +
> > +#define MKHI_HDR_RESULT			REG_GENMASK(31, 24)
> > +#define MKHI_HDR_IS_RESPONSE		REG_BIT(15)
> > +#define MKHI_HDR_COMMAND		REG_GENMASK(14, 8)
> > +#define MKHI_HDR_GROUP_ID		REG_GENMASK(7, 0)
> > +
> > +#define SC_MB_FRAME_SIZE		16
> > +#define SC_MB_MAX_FRAMES		64
> > +#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
> > +#define SC_MKHI_COMMAND			5
> > +
> > +#define SC_MB_DEFAULT_TIMEOUT_MS	500
> > +#define SC_MB_RETRY_TIMEOUT_MS		20
> > +#define SC_MB_POLL_INTERVAL_US		100
> > +
> > +#endif /* _XE_SC_REGS_H_ */
> > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> > index f15489c100af..9fbd0b084c74 100644
> > --- a/drivers/gpu/drm/xe/xe_device.c
> > +++ b/drivers/gpu/drm/xe/xe_device.c
> > @@ -60,6 +60,7 @@
> >  #include "xe_psmi.h"
> >  #include "xe_pxp.h"
> >  #include "xe_query.h"
> > +#include "xe_sc.h"
> >  #include "xe_soc_remapper.h"
> >  #include "xe_shrinker.h"
> >  #include "xe_survivability_mode.h"
> > @@ -963,6 +964,10 @@ int xe_device_probe(struct xe_device *xe)
> >  	if (err)
> >  		goto err_unregister_display;
> >  
> > +	err = xe_sc_init(xe);
> > +	if (err)
> > +		goto err_unregister_display;
> > +
> >  	for_each_gt(gt, xe, id)
> >  		xe_gt_sanitize_freq(gt);
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> > index 3f118c64a124..86a0c83c802d 100644
> > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > @@ -314,6 +314,8 @@ struct xe_device {
> >  		u8 has_range_tlb_inval:1;
> >  		/** @info.has_sriov: Supports SR-IOV */
> >  		u8 has_sriov:1;
> > +		/** @info.has_sysctrl: Supports System Controller */
> > +		u8 has_sysctrl:1;
> >  		/** @info.has_usm: Device has unified shared memory support */
> >  		u8 has_usm:1;
> >  		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
> > @@ -576,6 +578,9 @@ struct xe_device {
> >  	/** @heci_gsc: graphics security controller */
> >  	struct xe_heci_gsc heci_gsc;
> >  
> > +	/** @sc: System Controller */
> > +	struct xe_sc *sc;
> > +
> >  	/** @nvm: discrete graphics non-volatile memory */
> >  	struct intel_dg_nvm_dev *nvm;
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_sc.c b/drivers/gpu/drm/xe/xe_sc.c
> > new file mode 100644
> > index 000000000000..18448efc173f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sc.c
> > @@ -0,0 +1,89 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#include "xe_sc.h"
> > +
> > +#include <linux/mutex.h>
> > +
> > +#include <drm/drm_managed.h>
> > +#include <drm/drm_print.h>
> > +
> > +#include "regs/xe_sc_regs.h"
> > +#include "xe_device.h"
> > +#include "xe_mmio.h"
> > +#include "xe_platform_types.h"
> > +#include "xe_soc_remapper.h"
> > +#include "xe_sc_types.h"
> > +#include "xe_tile.h"
> > +
> > +static void xe_sc_remove(struct drm_device *drm, void *arg)
> > +{
> > +	struct xe_sc *sc = arg;
> > +	struct xe_device *xe;
> > +
> > +	if (!sc)
> > +		return;
> > +
> > +	xe = to_xe_device(drm);
> > +
> > +	mutex_destroy(&sc->cmd_lock);
> > +
> > +	xe_soc_remapper_set_sysctrl_region(xe, 0);
> > +
> > +	xe->sc = NULL;
> > +}
> > +
> > +static int xe_sc_probe(struct xe_device *xe)
> > +{
> > +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> > +	struct xe_sc *sc;
> > +	int ret;
> > +
> > +	sc = drmm_kzalloc(&xe->drm, sizeof(*sc), GFP_KERNEL);
> > +	if (!sc)
> > +		return -ENOMEM;
> > +
> > +	sc->xe = xe;
> > +	xe->sc = sc;
> > +
> > +	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
> > +	if (ret) {
> > +		xe->sc = NULL;
> > +		return ret;
> > +	}
> > +
> > +	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > +
> > +	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
> > +
> > +	mutex_init(&sc->cmd_lock);
> > +
> > +	sc->phase_bit = 0;
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * xe_sc_init - Initialize SC subsystem
> > + * @xe: xe device instance
> > + *
> > + * Entry point for SC initialization, called from xe_device_probe().
> > + * This function checks platform support and calls the main probe function.
> > + *
> > + * Return: 0 on success, error code on failure
> > + */
> > +int xe_sc_init(struct xe_device *xe)
> > +{
> > +	int ret;
> > +
> > +	if (!xe->info.has_sysctrl)
> > +		return 0;
> > +
> > +	ret = xe_sc_probe(xe);
> > +	if (ret)
> > +		drm_err(&xe->drm, "sysctrl: Probe failed: %d\n", ret);
> > +
> > +	return ret;
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sc.h b/drivers/gpu/drm/xe/xe_sc.h
> > new file mode 100644
> > index 000000000000..0e5c89ddc957
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sc.h
> > @@ -0,0 +1,15 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef __XE_SC_H__
> > +#define __XE_SC_H__
> > +
> > +#include <linux/types.h>
> > +
> > +struct xe_device;
> > +
> > +int xe_sc_init(struct xe_device *xe);
> > +
> > +#endif /* __XE_SC_H__ */
> > diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.c b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> > new file mode 100644
> > index 000000000000..6f2500c63a3c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> > @@ -0,0 +1,374 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/errno.h>
> > +#include <linux/minmax.h>
> > +#include <linux/mutex.h>
> > +#include <linux/slab.h>
> > +#include <linux/string.h>
> > +#include <linux/types.h>
> > +
> > +#include <drm/drm_print.h>
> > +
> > +#include "regs/xe_sc_regs.h"
> > +#include "xe_device.h"
> > +#include "xe_mmio.h"
> > +#include "xe_pm.h"
> > +#include "xe_sc.h"
> > +#include "xe_sc_mailbox.h"
> > +#include "xe_sc_types.h"
> > +
> > +static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
> > +				 unsigned int timeout_ms)
> > +{
> > +	int ret;
> > +
> > +	if (timeout_ms == 0) {
> > +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> > +					 0, NULL, false);
> > +	} else {
> > +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> > +					 timeout_ms * 1000, NULL, false);
> > +	}
> > +
> > +	return ret == 0;
> > +}
> > +
> > +static bool sc_mb_wait_bit_set(struct xe_sc *sc, u32 bit_mask,
> > +			       unsigned int timeout_ms)
> > +{
> > +	int ret;
> > +
> > +	if (timeout_ms == 0) {
> > +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> > +				     0, NULL, false);
> > +	} else {
> > +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> > +				     timeout_ms * 1000, NULL, false);
> > +	}
> > +
> > +	return ret == 0;
> > +}
> > +
> > +static void sc_mb_write_frame(struct xe_sc *sc, const void *buffer,
> > +			      size_t offset)
> > +{
> > +	const u32 *data = (const u32 *)((const u8 *)buffer + offset);
> > +
> > +	xe_mmio_write32(&sc->mmio, SC_MB_DATA0, data[0]);
> > +	xe_mmio_write32(&sc->mmio, SC_MB_DATA1, data[1]);
> > +	xe_mmio_write32(&sc->mmio, SC_MB_DATA2, data[2]);
> > +	xe_mmio_write32(&sc->mmio, SC_MB_DATA3, data[3]);
> > +}
> > +
> > +static void sc_mb_read_frame(struct xe_sc *sc, void *buffer,
> > +			     size_t offset)
> > +{
> > +	u32 *data = (u32 *)((u8 *)buffer + offset);
> > +
> > +	data[0] = xe_mmio_read32(&sc->mmio, SC_MB_DATA0);
> > +	data[1] = xe_mmio_read32(&sc->mmio, SC_MB_DATA1);
> > +	data[2] = xe_mmio_read32(&sc->mmio, SC_MB_DATA2);
> > +	data[3] = xe_mmio_read32(&sc->mmio, SC_MB_DATA3);
> > +}
> > +
> > +static void sc_mb_clear_response(struct xe_sc *sc)
> > +{
> > +	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);
> > +}
> > +
> > +static int sc_mb_prepare_command(struct xe_sc *sc,
> > +				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> > +				 const void *data_in, size_t data_in_len,
> > +				 u8 **cmd_buffer, size_t *cmd_size)
> > +{
> > +	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
> > +
> > +	mkhi_hdr.group_id = msg_hdr->group_id;
> > +	mkhi_hdr.command = msg_hdr->command & 0x7F;
> > +	mkhi_hdr.is_response = 0;
> > +	mkhi_hdr.reserved = 0;
> > +	mkhi_hdr.result = 0;
> > +
> > +	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;
> > +
> > +	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
> > +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
> > +			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
> > +		return -EINVAL;
> > +	}
> > +
> > +	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
> > +	if (!*cmd_buffer)
> > +		return -ENOMEM;
> > +
> > +	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));
> > +	if (data_in && data_in_len)
> > +		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> > +		       data_in, data_in_len);
> > +
> > +	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
> > +		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
> > +			     size_t cmd_size, unsigned int timeout_ms)
> > +{
> > +	u32 ctrl_reg, total_frames, current_frame;
> > +	size_t bytes_sent, bytes_to_send;
> > +
> > +	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
> > +	if (total_frames > SC_MB_MAX_FRAMES) {
> > +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
> > +			cmd_size, total_frames, SC_MB_MAX_FRAMES);
> > +		return -EINVAL;
> > +	}
> > +
> > +	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> > +		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
> > +		return -EBUSY;
> > +	}
> > +
> > +	sc->phase_bit ^= 1;
> > +
> > +	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
> > +		cmd_size, total_frames, sc->phase_bit);
> > +
> > +	bytes_sent = 0;
> > +	for (current_frame = 0; current_frame < total_frames; current_frame++) {
> > +		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
> > +
> > +		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);
> > +
> > +		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
> > +			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
> > +			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
> > +			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
> > +		if (sc->phase_bit)
> > +			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
> > +
> > +		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
> > +
> > +		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
> > +			current_frame, total_frames - 1);
> > +
> > +		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> > +			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
> > +				current_frame);
> > +			return -ETIMEDOUT;
> > +		}
> > +
> > +		bytes_sent += bytes_to_send;
> > +	}
> > +
> > +	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
> > +	return 0;
> > +}
> > +
> > +static int sc_mb_validate_response_header(struct xe_sc *sc,
> > +					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> > +					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
> > +{
> > +	if (!resp_hdr->is_response ||
> > +	    resp_hdr->group_id != msg_hdr->group_id ||
> > +	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
> > +		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
> > +		return -EPROTO;
> > +	}
> > +
> > +	if (resp_hdr->result != 0) {
> > +		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
> > +			resp_hdr->result);
> > +		return -EIO;
> > +	}
> > +
> > +	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
> > +		resp_hdr->group_id, resp_hdr->command);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sc_mb_receive_frames(struct xe_sc *sc,
> > +				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> > +				void *data_out, size_t data_out_len,
> > +				size_t *bytes_received, unsigned int timeout_ms)
> > +{
> > +	u32 ctrl_reg, total_frames, current_frame;
> > +	size_t payload_size;
> > +	int ret;
> > +
> > +	*bytes_received = 0;
> > +
> > +	do {
> > +		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
> > +		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
> > +		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
> > +
> > +		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
> > +			current_frame, total_frames - 1);
> > +
> > +		if (current_frame == 0) {
> > +			u32 temp_frame[4];
> > +			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
> > +
> > +			sc_mb_read_frame(sc, temp_frame, 0);
> > +			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
> > +
> > +			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
> > +			if (ret)
> > +				return ret;
> > +
> > +			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> > +			if (payload_size > data_out_len) {
> > +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> > +				return -ENOSPC;
> > +			}
> > +
> > +			memcpy(data_out,
> > +			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> > +			       payload_size);
> > +			*bytes_received = payload_size;
> > +		} else {
> > +			size_t frame_size = SC_MB_FRAME_SIZE;
> > +
> > +			if (current_frame == total_frames - 1) {
> > +				size_t total_response = (total_frames - 1) *
> > +							SC_MB_FRAME_SIZE +
> > +							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> > +				size_t remaining = total_response -
> > +						   *bytes_received -
> > +						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> > +				frame_size = min(frame_size, remaining);
> > +			}
> > +
> > +			if (*bytes_received + frame_size > data_out_len) {
> > +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> > +				return -ENOSPC;
> > +			}
> > +
> > +			sc_mb_read_frame(sc, data_out, *bytes_received);
> > +			*bytes_received += frame_size;
> > +		}
> > +
> > +		sc_mb_clear_response(sc);
> > +
> > +		if (current_frame + 1 < total_frames &&
> > +		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> > +			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
> > +				current_frame + 1);
> > +			return -ETIMEDOUT;
> > +		}
> > +
> > +	} while (current_frame + 1 < total_frames);
> > +
> > +	return 0;
> > +}
> > +
> > +static int sc_mb_send_command(struct xe_sc *sc,
> > +			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> > +			      const u8 *cmd_buffer, size_t cmd_size,
> > +			      void *data_out, size_t data_out_len,
> > +			      size_t *rdata_len, unsigned int timeout_ms)
> > +{
> > +	size_t bytes_received;
> > +	int ret;
> > +
> > +	if (rdata_len)
> > +		*rdata_len = 0;
> > +
> > +	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
> > +	if (ret)
> > +		return ret;
> > +
> > +	if (!data_out) {
> > +		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
> > +		return 0;
> > +	}
> > +
> > +	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> > +		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
> > +		return -ETIMEDOUT;
> > +	}
> > +
> > +	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
> > +				   &bytes_received, timeout_ms);
> > +	if (ret) {
> > +		sc_mb_clear_response(sc);
> > +		return ret;
> > +	}
> > +
> > +	if (rdata_len)
> > +		*rdata_len = bytes_received;
> > +
> > +	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
> > +		bytes_received);
> > +
> > +	return 0;
> > +}
> > +
> > +/**
> > + * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
> > + * @handle: XE device handle containing the system controller
> > + * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
> > + * @rdata_len: Pointer to store actual response data size (can be NULL)
> > + *
> > + * Send a command to the System Controller using MKHI protocol. Handles
> > + * command preparation, fragmentation, transmission, and response reception.
> > + * Optimized to move memory allocation outside the critical section.
> > + *
> > + * Return: 0 on success, negative error code on failure
> > + */
> > +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
> > +{
> > +	struct xe_device *xe = handle;
> > +	struct xe_sc *sc;
> > +	struct xe_sc_mailbox_command *cmd = cmd_buffer;
> > +	u8 *command_buffer = NULL;
> > +	size_t command_size;
> > +	int ret;
> > +
> > +	if (!xe || !cmd)
> > +		return -EINVAL;
> > +
> > +	sc = xe->sc;
> > +	if (!sc)
> > +		return -ENODEV;
> > +
> > +	if (!cmd->data_in && cmd->data_in_len)
> > +		return -EINVAL;
> > +
> > +	if (!cmd->data_out && cmd->data_out_len)
> > +		return -EINVAL;
> > +
> > +	might_sleep();
> > +
> > +	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
> > +				    &command_buffer, &command_size);
> > +	if (ret) {
> > +		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
> > +		return ret;
> > +	}
> > +
> > +	mutex_lock(&sc->cmd_lock);
> > +
> > +	xe_pm_runtime_get(xe);
> > +
> 
> Quick drive by comment - xe_pm_runtime_get can wake the device taking a
> bunch of locks. Because of that, the preferred deisgn to take this at
> outer most point possible (i.e., not holding other locks), so I'd
> suggest moving PM get / put outside of the cmd_lock.
> 
> > +	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
> > +				 cmd->data_out, cmd->data_out_len, rdata_len,
> > +				 SC_MB_DEFAULT_TIMEOUT_MS);
> > +	if (ret)
> > +		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
> > +
> > +	xe_pm_runtime_put(xe);
> > +
> > +	mutex_unlock(&sc->cmd_lock);
> > +
> > +	kfree(command_buffer);
> > +
> > +	return ret;
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> > new file mode 100644
> > index 000000000000..d5ca43c40f1a
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> > @@ -0,0 +1,61 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef __XE_SC_MAILBOX_H__
> > +#define __XE_SC_MAILBOX_H__
> > +
> > +#include <linux/types.h>
> > +
> > +struct xe_sc;
> > +
> > +/**
> > + * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
> > + */
> > +struct xe_sc_mailbox_mkhi_msg_hdr {
> > +	/** @group_id: Message group identifier */
> > +	u32 group_id    : 8;
> > +	/** @command: Command identifier within the group */
> > +	u32 command     : 7;
> > +	/** @is_response: Response flag - 0 for request, 1 for response */
> > +	u32 is_response : 1;
> > +	/** @reserved: Reserved field, must be zero */
> > +	u32 reserved    : 8;
> > +	/** @result: Result code from firmware */
> > +	u32 result      : 8;
> 
> Another quick comment - bitfields layout can based on the CPU endianess

s/can based/can change based/

Matt

> so prefer defines + macros to set fields if this used in a wire level
> protocol.
> 
> Matt
> 
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sc_mailbox_app_msg_hdr - Application message header
> > + */
> > +struct xe_sc_mailbox_app_msg_hdr {
> > +	/** @group_id: Application group identifier */
> > +	u32 group_id  : 8;
> > +	/** @command: Specific command within the application group */
> > +	u32 command   : 8;
> > +	/** @version: Protocol version */
> > +	u32 version   : 8;
> > +	/** @reserved: Reserved field, must be zero */
> > +	u32 reserved  : 8;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_sc_mailbox_command - System Controller mailbox command structure
> > + */
> > +struct xe_sc_mailbox_command {
> > +	/** @header: Application message header containing command information */
> > +	struct xe_sc_mailbox_app_msg_hdr header;
> > +	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
> > +	void *data_in;
> > +	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
> > +	size_t data_in_len;
> > +	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
> > +	void *data_out;
> > +	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
> > +	size_t data_out_len;
> > +};
> > +
> > +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
> > +
> > +#endif /* __XE_SC_MAILBOX_H__ */
> > diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
> > new file mode 100644
> > index 000000000000..5ec2126cebe4
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_sc_types.h
> > @@ -0,0 +1,35 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2025 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_SC_TYPES_H_
> > +#define _XE_SC_TYPES_H_
> > +
> > +#include <linux/completion.h>
> > +#include <linux/mutex.h>
> > +#include <linux/types.h>
> > +#include <linux/workqueue.h>
> > +
> > +#include "xe_device_types.h"
> > +#include "xe_sc_mailbox.h"
> > +
> > +struct xe_device;
> > +
> > +/**
> > + * struct xe_sc - System Controller driver context
> > + */
> > +struct xe_sc {
> > +	/** @xe: Back pointer to xe_device */
> > +	struct xe_device *xe;
> > +	/** @mmio: MMIO region for SC registers */
> > +	struct xe_mmio mmio;
> > +
> > +	/** @cmd_lock: Mutex protecting mailbox command operations */
> > +	struct mutex cmd_lock;
> > +
> > +	/** @phase_bit: MKHI message boundary phase toggle bit */
> > +	u32 phase_bit;
> > +};
> > +
> > +#endif /* _XE_SC_TYPES_H_ */
> > -- 
> > 2.43.0
> > 

Re: [RFC 1/5] drm/xe/soc_remapper: Initialize SoC remapper during Xe probe

[Michal Wajdeczko]

On 11/22/2025 5:58 AM, Anoop, Vijay wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> 
> SoC remapper is used to map different HW functions in the SoC to their
> respective drivers. Initialize SoC remapper during driver load.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  drivers/gpu/drm/xe/Makefile          |  1 +
>  drivers/gpu/drm/xe/xe_device.c       |  5 +++++
>  drivers/gpu/drm/xe/xe_device_types.h |  6 ++++++
>  drivers/gpu/drm/xe/xe_soc_remapper.c | 15 +++++++++++++++
>  drivers/gpu/drm/xe/xe_soc_remapper.h | 15 +++++++++++++++
>  5 files changed, 42 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/xe_soc_remapper.c
>  create mode 100644 drivers/gpu/drm/xe/xe_soc_remapper.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 1a3aa041820d..7ebfbf9051bf 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -110,6 +110,7 @@ xe-y += xe_bb.o \
>  	xe_range_fence.o \
>  	xe_reg_sr.o \
>  	xe_reg_whitelist.o \
> +	xe_soc_remapper.o \

please keep .o in alphabetical order

>  	xe_ring_ops.o \
>  	xe_rtp.o \
>  	xe_sa.o \
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index 1197f914ef77..f15489c100af 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -60,6 +60,7 @@
>  #include "xe_psmi.h"
>  #include "xe_pxp.h"
>  #include "xe_query.h"
> +#include "xe_soc_remapper.h"

please keep includes in alphabetical order

>  #include "xe_shrinker.h"
>  #include "xe_survivability_mode.h"
>  #include "xe_sriov.h"
> @@ -906,6 +907,10 @@ int xe_device_probe(struct xe_device *xe)
>  
>  	xe_nvm_init(xe);
>  
> +	err = xe_soc_remapper_init(xe);
> +	if (err)
> +		return err;
> +
>  	err = xe_heci_gsc_init(xe);
>  	if (err)
>  		return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 0b2fa7c56d38..4d23b75bc728 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -552,6 +552,12 @@ struct xe_device {
>  		struct mutex lock;
>  	} pmt;
>  
> +	/* @soc_remapper: SoC remapper object */

use proper kernel-doc format

	/** @soc_remapper: ...

> +	struct {
> +		/* Serialize access to SoC Remapper's index registers */

use proper kernel-doc format

		/** @soc_remapper.lock: ...

> +		spinlock_t lock;
> +	} soc_remapper;
> +
>  	/**
>  	 * @pm_callback_task: Track the active task that is running in either
>  	 * the runtime_suspend or runtime_resume callbacks.
> diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.c b/drivers/gpu/drm/xe/xe_soc_remapper.c
> new file mode 100644
> index 000000000000..f5a02abd6ab1
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_soc_remapper.c
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/spinlock.h>

likely not need, try instead:

   #include "xe_device_types.h"

> +
> +#include "xe_soc_remapper.h"
> +
> +int xe_soc_remapper_init(struct xe_device *xe)
> +{
> +	spin_lock_init(&xe->soc_remapper.lock);
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.h b/drivers/gpu/drm/xe/xe_soc_remapper.h
> new file mode 100644
> index 000000000000..3cfd44f1fd74
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_soc_remapper.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SOC_REMAPPER_H_
> +#define _XE_SOC_REMAPPER_H_
> +
> +#include <linux/types.h>
> +
> +#include "xe_device_types.h"

we don't need full include here, use forward declaration instead:

struct xe_device;

> +
> +int xe_soc_remapper_init(struct xe_device *xe);
> +
> +#endif

Re: [RFC 2/5] drm/xe/soc_remapper: Use SoC remapper herlper from VSEC code

[Michal Wajdeczko]

On 11/22/2025 5:58 AM, Anoop, Vijay wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> 
> Since different drivers can use SoC remapper, modify VSEC code to
> access SoC remapper via a helper that would synchronize such accesses.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_pmt.h               |  3 ---
>  drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h | 13 +++++++++++++
>  drivers/gpu/drm/xe/xe_soc_remapper.c           | 18 ++++++++++++++++++
>  drivers/gpu/drm/xe/xe_soc_remapper.h           |  1 +
>  drivers/gpu/drm/xe/xe_vsec.c                   |  4 ++--
>  5 files changed, 34 insertions(+), 5 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
> index 0f79c0714454..240d57993ea6 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pmt.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
> @@ -18,9 +18,6 @@
>  #define BMG_TELEMETRY_BASE_OFFSET	0xE0000
>  #define BMG_TELEMETRY_OFFSET		(SOC_BASE + BMG_TELEMETRY_BASE_OFFSET)
>  
> -#define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
> -#define   SG_REMAP_BITS			REG_GENMASK(31, 24)
> -
>  #define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)
>  #define BMG_G2_RESIDENCY_OFFSET		(0x530)
>  #define BMG_G6_RESIDENCY_OFFSET		(0x538)
> diff --git a/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h b/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
> new file mode 100644
> index 000000000000..9edf234227a9
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_soc_remapper_regs.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +#ifndef _XE_SOC_REMAPPER_REGS_H_
> +#define _XE_SOC_REMAPPER_REGS_H_
> +
> +#include "xe_regs.h"
> +
> +#define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
> +#define   SG_REMAP_TELEM_MASK		REG_GENMASK(31, 24)
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.c b/drivers/gpu/drm/xe/xe_soc_remapper.c
> index f5a02abd6ab1..85d37a86117a 100644
> --- a/drivers/gpu/drm/xe/xe_soc_remapper.c
> +++ b/drivers/gpu/drm/xe/xe_soc_remapper.c
> @@ -5,8 +5,26 @@
>  
>  #include <linux/spinlock.h>
>  
> +#include "regs/xe_soc_remapper_regs.h"
> +#include "xe_mmio.h"
>  #include "xe_soc_remapper.h"
>  
> +static void xe_soc_remapper_set_region(struct xe_device *xe, struct xe_reg reg,
> +				       u32 mask, u32 val)
> +{
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&xe->soc_remapper.lock, flags);

we are converting Xe to scoped based locks, so:

	guard(spinlock_irqsave)(&xe->soc_remapper.lock);

> +	xe_mmio_rmw32(xe_root_tile_mmio(xe), reg, mask, val);
> +	spin_unlock_irqrestore(&xe->soc_remapper.lock, flags);
> +}
> +

btw, all public functions must have kernel-doc

> +void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index)
> +{
> +	xe_soc_remapper_set_region(xe, SG_REMAP_INDEX1, SG_REMAP_TELEM_MASK,
> +				   REG_FIELD_PREP(SG_REMAP_TELEM_MASK, index));
> +}
> +
>  int xe_soc_remapper_init(struct xe_device *xe)
>  {
>  	spin_lock_init(&xe->soc_remapper.lock);
> diff --git a/drivers/gpu/drm/xe/xe_soc_remapper.h b/drivers/gpu/drm/xe/xe_soc_remapper.h
> index 3cfd44f1fd74..75431b94e66a 100644
> --- a/drivers/gpu/drm/xe/xe_soc_remapper.h
> +++ b/drivers/gpu/drm/xe/xe_soc_remapper.h
> @@ -11,5 +11,6 @@
>  #include "xe_device_types.h"
>  
>  int xe_soc_remapper_init(struct xe_device *xe);
> +void xe_soc_remapper_set_telem_region(struct xe_device *xe, u32 index);
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_vsec.c b/drivers/gpu/drm/xe/xe_vsec.c
> index 8f23a27871b6..3e217fb75394 100644
> --- a/drivers/gpu/drm/xe/xe_vsec.c
> +++ b/drivers/gpu/drm/xe/xe_vsec.c
> @@ -16,6 +16,7 @@
>  #include "xe_mmio.h"
>  #include "xe_platform_types.h"
>  #include "xe_pm.h"
> +#include "xe_soc_remapper.h"
>  #include "xe_vsec.h"
>  
>  #include "regs/xe_pmt.h"
> @@ -163,8 +164,7 @@ int xe_pmt_telem_read(struct pci_dev *pdev, u32 guid, u64 *data, loff_t user_off
>  		return -ENODATA;
>  
>  	/* set SoC re-mapper index register based on GUID memory region */
> -	xe_mmio_rmw32(xe_root_tile_mmio(xe), SG_REMAP_INDEX1, SG_REMAP_BITS,
> -		      REG_FIELD_PREP(SG_REMAP_BITS, mem_region));
> +	xe_soc_remapper_set_telem_region(xe, mem_region);
>  
>  	memcpy_fromio(data, telem_addr, count);
>  	xe_pm_runtime_put(xe);

Re: [RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Michal Wajdeczko]

On 11/22/2025 5:58 AM, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
> 
> Add a new system controller (SC) component for Intel Xe3p dGPU platforms.

in some messages instead of "SC" you're using "SYSCTRL" / "sysctrl" names
maybe functions/file should also use SYSCTRL ?


> 
> This component provides the foundational infrastructure for communication
> with the SC firmware using the MKHI protocol over a mailbox interface.
> 
> Key features introduced:
> - Detection and initialization of the SC interface on Xe3p dGPU platforms
> - Mailbox communication with SC firmware
> - Fragmented message transfer for large command payloads
> 
> This implementation establishes the base for future SC feature
> enablement and firmware command handling.
> 
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
>  drivers/gpu/drm/xe/Makefile          |   2 +
>  drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
>  drivers/gpu/drm/xe/xe_device.c       |   5 +
>  drivers/gpu/drm/xe/xe_device_types.h |   5 +
>  drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
>  drivers/gpu/drm/xe/xe_sc.h           |  15 ++
>  drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
>  drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
>  9 files changed, 635 insertions(+)
>  create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
>  create mode 100644 drivers/gpu/drm/xe/xe_sc.c
>  create mode 100644 drivers/gpu/drm/xe/xe_sc.h
>  create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
>  create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
>  create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 7ebfbf9051bf..50e8dc86d915 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -114,7 +114,9 @@ xe-y += xe_bb.o \
>  	xe_ring_ops.o \
>  	xe_rtp.o \
>  	xe_sa.o \
> +	xe_sc.o \
>  	xe_sched_job.o \
> +	xe_sc_mailbox.o \
>  	xe_shrinker.o \
>  	xe_step.o \
>  	xe_survivability_mode.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_sc_regs.h b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> new file mode 100644
> index 000000000000..2b7053586197
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SC_REGS_H_
> +#define _XE_SC_REGS_H_
> +
> +#include "xe_regs.h"
> +
> +#define SYSCTRL_BASE_OFFSET		0xDB000
> +#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
> +#define SYSCTRL_MAILBOX_INDEX		0x03
> +#define SC_BAR_LENGTH			0x1000
> +
> +#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
> +#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
> +#define   SC_MB_CTRL_IRQ		REG_BIT(30)
> +#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
> +#define   SC_MB_CTRL_PARAM3		REG_GENMASK(28, 24)
> +#define   SC_MB_CTRL_PARAM2		REG_GENMASK(23, 16)
> +#define   SC_MB_CTRL_PARAM1		REG_GENMASK(15, 8)
> +#define   SC_MB_CTRL_COMMAND		REG_GENMASK(7, 0)
> +
> +#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
> +#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
> +#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
> +#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
> +
> +#define MKHI_FRAME_PHASE		REG_BIT(24)
> +#define MKHI_FRAME_CURRENT		REG_GENMASK(21, 16)
> +#define MKHI_FRAME_TOTAL		REG_GENMASK(13, 8)
> +#define MKHI_FRAME_COMMAND		REG_GENMASK(7, 0)
> +
> +#define MKHI_HDR_RESULT			REG_GENMASK(31, 24)
> +#define MKHI_HDR_IS_RESPONSE		REG_BIT(15)
> +#define MKHI_HDR_COMMAND		REG_GENMASK(14, 8)
> +#define MKHI_HDR_GROUP_ID		REG_GENMASK(7, 0)
> +
> +#define SC_MB_FRAME_SIZE		16
> +#define SC_MB_MAX_FRAMES		64
> +#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
> +#define SC_MKHI_COMMAND			5
> +
> +#define SC_MB_DEFAULT_TIMEOUT_MS	500
> +#define SC_MB_RETRY_TIMEOUT_MS		20
> +#define SC_MB_POLL_INTERVAL_US		100
> +
> +#endif /* _XE_SC_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index f15489c100af..9fbd0b084c74 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -60,6 +60,7 @@
>  #include "xe_psmi.h"
>  #include "xe_pxp.h"
>  #include "xe_query.h"
> +#include "xe_sc.h"
>  #include "xe_soc_remapper.h"
>  #include "xe_shrinker.h"
>  #include "xe_survivability_mode.h"
> @@ -963,6 +964,10 @@ int xe_device_probe(struct xe_device *xe)
>  	if (err)
>  		goto err_unregister_display;
>  
> +	err = xe_sc_init(xe);
> +	if (err)
> +		goto err_unregister_display;
> +
>  	for_each_gt(gt, xe, id)
>  		xe_gt_sanitize_freq(gt);
>  
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 3f118c64a124..86a0c83c802d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -314,6 +314,8 @@ struct xe_device {
>  		u8 has_range_tlb_inval:1;
>  		/** @info.has_sriov: Supports SR-IOV */
>  		u8 has_sriov:1;
> +		/** @info.has_sysctrl: Supports System Controller */
> +		u8 has_sysctrl:1;
>  		/** @info.has_usm: Device has unified shared memory support */
>  		u8 has_usm:1;
>  		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
> @@ -576,6 +578,9 @@ struct xe_device {
>  	/** @heci_gsc: graphics security controller */
>  	struct xe_heci_gsc heci_gsc;
>  
> +	/** @sc: System Controller */
> +	struct xe_sc *sc;

maybe:

	struct xe_sysctrl *sc;

> +
>  	/** @nvm: discrete graphics non-volatile memory */
>  	struct intel_dg_nvm_dev *nvm;
>  
> diff --git a/drivers/gpu/drm/xe/xe_sc.c b/drivers/gpu/drm/xe/xe_sc.c
> new file mode 100644
> index 000000000000..18448efc173f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "xe_sc.h"

I guess we don't use this include pattern any more,
as we have HDRTEST makefile target

> +
> +#include <linux/mutex.h>
> +
> +#include <drm/drm_managed.h>
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_sc_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_platform_types.h"
> +#include "xe_soc_remapper.h"
> +#include "xe_sc_types.h"
> +#include "xe_tile.h"
> +
> +static void xe_sc_remove(struct drm_device *drm, void *arg)
> +{
> +	struct xe_sc *sc = arg;
> +	struct xe_device *xe;
> +
> +	if (!sc)
> +		return;

this shouldn't be needed, you are in control what is passed here

> +
> +	xe = to_xe_device(drm);
> +
> +	mutex_destroy(&sc->cmd_lock);
> +
> +	xe_soc_remapper_set_sysctrl_region(xe, 0);
> +
> +	xe->sc = NULL;

we usually don't do that on unwind

> +}
> +
> +static int xe_sc_probe(struct xe_device *xe)
> +{
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +	struct xe_sc *sc;
> +	int ret;
> +
> +	sc = drmm_kzalloc(&xe->drm, sizeof(*sc), GFP_KERNEL);
> +	if (!sc)
> +		return -ENOMEM;
> +
> +	sc->xe = xe;
> +	xe->sc = sc;
> +
> +	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
> +	if (ret) {
> +		xe->sc = NULL;
> +		return ret;
> +	}
> +
> +	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> +
> +	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
> +
> +	mutex_init(&sc->cmd_lock);

use drmm_mutex_init() instead

> +
> +	sc->phase_bit = 0;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sc_init - Initialize SC subsystem
> + * @xe: xe device instance
> + *
> + * Entry point for SC initialization, called from xe_device_probe().
> + * This function checks platform support and calls the main probe function.
> + *
> + * Return: 0 on success, error code on failure
> + */
> +int xe_sc_init(struct xe_device *xe)
> +{
> +	int ret;
> +
> +	if (!xe->info.has_sysctrl)
> +		return 0;
> +
> +	ret = xe_sc_probe(xe);
> +	if (ret)
> +		drm_err(&xe->drm, "sysctrl: Probe failed: %d\n", ret);

you can use xe_err(xe, ...) helper

> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sc.h b/drivers/gpu/drm/xe/xe_sc.h
> new file mode 100644
> index 000000000000..0e5c89ddc957
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __XE_SC_H__
> +#define __XE_SC_H__
> +
> +#include <linux/types.h>

not needed

> +
> +struct xe_device;
> +
> +int xe_sc_init(struct xe_device *xe);
> +
> +#endif /* __XE_SC_H__ */
> diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.c b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> new file mode 100644
> index 000000000000..6f2500c63a3c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> @@ -0,0 +1,374 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/errno.h>
> +#include <linux/minmax.h>
> +#include <linux/mutex.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_sc_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_pm.h"
> +#include "xe_sc.h"
> +#include "xe_sc_mailbox.h"
> +#include "xe_sc_types.h"
> +
> +static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
> +				 unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	if (timeout_ms == 0) {
> +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +					 0, NULL, false);
> +	} else {
> +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +					 timeout_ms * 1000, NULL, false);
> +	}
> +
> +	return ret == 0;
> +}
> +
> +static bool sc_mb_wait_bit_set(struct xe_sc *sc, u32 bit_mask,
> +			       unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	if (timeout_ms == 0) {
> +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +				     0, NULL, false);
> +	} else {
> +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +				     timeout_ms * 1000, NULL, false);
> +	}
> +
> +	return ret == 0;
> +}
> +
> +static void sc_mb_write_frame(struct xe_sc *sc, const void *buffer,
> +			      size_t offset)
> +{
> +	const u32 *data = (const u32 *)((const u8 *)buffer + offset);
> +
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA0, data[0]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA1, data[1]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA2, data[2]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA3, data[3]);
> +}
> +
> +static void sc_mb_read_frame(struct xe_sc *sc, void *buffer,
> +			     size_t offset)
> +{
> +	u32 *data = (u32 *)((u8 *)buffer + offset);
> +
> +	data[0] = xe_mmio_read32(&sc->mmio, SC_MB_DATA0);
> +	data[1] = xe_mmio_read32(&sc->mmio, SC_MB_DATA1);
> +	data[2] = xe_mmio_read32(&sc->mmio, SC_MB_DATA2);
> +	data[3] = xe_mmio_read32(&sc->mmio, SC_MB_DATA3);
> +}
> +
> +static void sc_mb_clear_response(struct xe_sc *sc)
> +{
> +	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);
> +}
> +
> +static int sc_mb_prepare_command(struct xe_sc *sc,
> +				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +				 const void *data_in, size_t data_in_len,
> +				 u8 **cmd_buffer, size_t *cmd_size)
> +{
> +	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
> +
> +	mkhi_hdr.group_id = msg_hdr->group_id;
> +	mkhi_hdr.command = msg_hdr->command & 0x7F;
> +	mkhi_hdr.is_response = 0;
> +	mkhi_hdr.reserved = 0;
> +	mkhi_hdr.result = 0;
> +
> +	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;
> +
> +	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
> +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
> +			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
> +		return -EINVAL;
> +	}
> +
> +	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
> +	if (!*cmd_buffer)
> +		return -ENOMEM;
> +
> +	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));
> +	if (data_in && data_in_len)
> +		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> +		       data_in, data_in_len);
> +
> +	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
> +		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
> +			     size_t cmd_size, unsigned int timeout_ms)
> +{
> +	u32 ctrl_reg, total_frames, current_frame;
> +	size_t bytes_sent, bytes_to_send;
> +
> +	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
> +	if (total_frames > SC_MB_MAX_FRAMES) {
> +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
> +			cmd_size, total_frames, SC_MB_MAX_FRAMES);
> +		return -EINVAL;
> +	}
> +
> +	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
> +		return -EBUSY;
> +	}
> +
> +	sc->phase_bit ^= 1;
> +
> +	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
> +		cmd_size, total_frames, sc->phase_bit);
> +
> +	bytes_sent = 0;
> +	for (current_frame = 0; current_frame < total_frames; current_frame++) {
> +		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
> +
> +		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);
> +
> +		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
> +			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
> +			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
> +			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
> +		if (sc->phase_bit)
> +			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
> +
> +		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
> +
> +		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
> +			current_frame, total_frames - 1);
> +
> +		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
> +				current_frame);
> +			return -ETIMEDOUT;
> +		}
> +
> +		bytes_sent += bytes_to_send;
> +	}
> +
> +	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
> +	return 0;
> +}
> +
> +static int sc_mb_validate_response_header(struct xe_sc *sc,
> +					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
> +{
> +	if (!resp_hdr->is_response ||
> +	    resp_hdr->group_id != msg_hdr->group_id ||
> +	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
> +		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
> +		return -EPROTO;
> +	}
> +
> +	if (resp_hdr->result != 0) {
> +		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
> +			resp_hdr->result);
> +		return -EIO;
> +	}
> +
> +	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
> +		resp_hdr->group_id, resp_hdr->command);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_receive_frames(struct xe_sc *sc,
> +				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +				void *data_out, size_t data_out_len,
> +				size_t *bytes_received, unsigned int timeout_ms)
> +{
> +	u32 ctrl_reg, total_frames, current_frame;
> +	size_t payload_size;
> +	int ret;
> +
> +	*bytes_received = 0;
> +
> +	do {
> +		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
> +		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
> +		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
> +
> +		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
> +			current_frame, total_frames - 1);
> +
> +		if (current_frame == 0) {
> +			u32 temp_frame[4];
> +			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
> +
> +			sc_mb_read_frame(sc, temp_frame, 0);
> +			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
> +
> +			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
> +			if (ret)
> +				return ret;
> +
> +			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +			if (payload_size > data_out_len) {
> +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> +				return -ENOSPC;
> +			}
> +
> +			memcpy(data_out,
> +			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> +			       payload_size);
> +			*bytes_received = payload_size;
> +		} else {
> +			size_t frame_size = SC_MB_FRAME_SIZE;
> +
> +			if (current_frame == total_frames - 1) {
> +				size_t total_response = (total_frames - 1) *
> +							SC_MB_FRAME_SIZE +
> +							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +				size_t remaining = total_response -
> +						   *bytes_received -
> +						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +				frame_size = min(frame_size, remaining);
> +			}
> +
> +			if (*bytes_received + frame_size > data_out_len) {
> +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> +				return -ENOSPC;
> +			}
> +
> +			sc_mb_read_frame(sc, data_out, *bytes_received);
> +			*bytes_received += frame_size;
> +		}
> +
> +		sc_mb_clear_response(sc);
> +
> +		if (current_frame + 1 < total_frames &&
> +		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
> +				current_frame + 1);
> +			return -ETIMEDOUT;
> +		}
> +
> +	} while (current_frame + 1 < total_frames);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_send_command(struct xe_sc *sc,
> +			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +			      const u8 *cmd_buffer, size_t cmd_size,
> +			      void *data_out, size_t data_out_len,
> +			      size_t *rdata_len, unsigned int timeout_ms)
> +{
> +	size_t bytes_received;
> +	int ret;
> +
> +	if (rdata_len)
> +		*rdata_len = 0;
> +
> +	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
> +	if (ret)
> +		return ret;
> +
> +	if (!data_out) {
> +		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
> +		return 0;
> +	}
> +
> +	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
> +				   &bytes_received, timeout_ms);
> +	if (ret) {
> +		sc_mb_clear_response(sc);
> +		return ret;
> +	}
> +
> +	if (rdata_len)
> +		*rdata_len = bytes_received;
> +
> +	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
> +		bytes_received);
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
> + * @handle: XE device handle containing the system controller
> + * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
> + * @rdata_len: Pointer to store actual response data size (can be NULL)
> + *
> + * Send a command to the System Controller using MKHI protocol. Handles
> + * command preparation, fragmentation, transmission, and response reception.
> + * Optimized to move memory allocation outside the critical section.
> + *
> + * Return: 0 on success, negative error code on failure
> + */
> +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
> +{
> +	struct xe_device *xe = handle;
> +	struct xe_sc *sc;
> +	struct xe_sc_mailbox_command *cmd = cmd_buffer;
> +	u8 *command_buffer = NULL;
> +	size_t command_size;
> +	int ret;
> +
> +	if (!xe || !cmd)
> +		return -EINVAL;
> +
> +	sc = xe->sc;
> +	if (!sc)
> +		return -ENODEV;
> +
> +	if (!cmd->data_in && cmd->data_in_len)
> +		return -EINVAL;
> +
> +	if (!cmd->data_out && cmd->data_out_len)
> +		return -EINVAL;
> +
> +	might_sleep();
> +
> +	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
> +				    &command_buffer, &command_size);
> +	if (ret) {
> +		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
> +		return ret;
> +	}
> +
> +	mutex_lock(&sc->cmd_lock);

	guard(mutex)(&sc->cmd_lock);

> +
> +	xe_pm_runtime_get(xe);

	guard(xe_pm_runtime)(xe);

> +
> +	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
> +				 cmd->data_out, cmd->data_out_len, rdata_len,
> +				 SC_MB_DEFAULT_TIMEOUT_MS);
> +	if (ret)
> +		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
> +
> +	xe_pm_runtime_put(xe);
> +
> +	mutex_unlock(&sc->cmd_lock);
> +
> +	kfree(command_buffer);
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> new file mode 100644
> index 000000000000..d5ca43c40f1a
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __XE_SC_MAILBOX_H__
> +#define __XE_SC_MAILBOX_H__
> +
> +#include <linux/types.h>
> +
> +struct xe_sc;
> +
> +/**
> + * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
> + */
> +struct xe_sc_mailbox_mkhi_msg_hdr {
> +	/** @group_id: Message group identifier */
> +	u32 group_id    : 8;
> +	/** @command: Command identifier within the group */
> +	u32 command     : 7;
> +	/** @is_response: Response flag - 0 for request, 1 for response */
> +	u32 is_response : 1;
> +	/** @reserved: Reserved field, must be zero */
> +	u32 reserved    : 8;
> +	/** @result: Result code from firmware */
> +	u32 result      : 8;
> +} __packed;
> +
> +/**
> + * struct xe_sc_mailbox_app_msg_hdr - Application message header
> + */
> +struct xe_sc_mailbox_app_msg_hdr {
> +	/** @group_id: Application group identifier */
> +	u32 group_id  : 8;
> +	/** @command: Specific command within the application group */
> +	u32 command   : 8;
> +	/** @version: Protocol version */
> +	u32 version   : 8;
> +	/** @reserved: Reserved field, must be zero */
> +	u32 reserved  : 8;
> +} __packed;
> +
> +/**
> + * struct xe_sc_mailbox_command - System Controller mailbox command structure
> + */
> +struct xe_sc_mailbox_command {
> +	/** @header: Application message header containing command information */
> +	struct xe_sc_mailbox_app_msg_hdr header;
> +	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
> +	void *data_in;
> +	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
> +	size_t data_in_len;
> +	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
> +	void *data_out;
> +	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
> +	size_t data_out_len;
> +};
> +
> +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
> +
> +#endif /* __XE_SC_MAILBOX_H__ */
> diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
> new file mode 100644
> index 000000000000..5ec2126cebe4
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_types.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SC_TYPES_H_
> +#define _XE_SC_TYPES_H_
> +
> +#include <linux/completion.h>
> +#include <linux/mutex.h>
> +#include <linux/types.h>
> +#include <linux/workqueue.h>
> +
> +#include "xe_device_types.h"
> +#include "xe_sc_mailbox.h"
> +
> +struct xe_device;
> +
> +/**
> + * struct xe_sc - System Controller driver context
> + */
> +struct xe_sc {
> +	/** @xe: Back pointer to xe_device */
> +	struct xe_device *xe;
> +	/** @mmio: MMIO region for SC registers */
> +	struct xe_mmio mmio;
> +
> +	/** @cmd_lock: Mutex protecting mailbox command operations */
> +	struct mutex cmd_lock;
> +
> +	/** @phase_bit: MKHI message boundary phase toggle bit */
> +	u32 phase_bit;
> +};
> +
> +#endif /* _XE_SC_TYPES_H_ */

✗ CI.checkpatch: warning for drm/xe: Add System Controller support for Xe3p dGPU platforms

[Patchwork]

== Series Details ==

Series: drm/xe: Add System Controller support for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/157937/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
2de9a3901bc28757c7906b454717b64e2a214021
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit e173e4fea32a54e3f86631f3b89d04be659286ca
Author: Anoop Vijay <anoop.c.vijay@intel.com>
Date:   Fri Nov 21 20:58:07 2025 -0800

    drm/xe/sc: Add system controller component for Xe3p dGPU platforms
    
    Add a new system controller (SC) component for Intel Xe3p dGPU platforms.
    
    This component provides the foundational infrastructure for communication
    with the SC firmware using the MKHI protocol over a mailbox interface.
    
    Key features introduced:
    - Detection and initialization of the SC interface on Xe3p dGPU platforms
    - Mailbox communication with SC firmware
    - Fragmented message transfer for large command payloads
    
    This implementation establishes the base for future SC feature
    enablement and firmware command handling.
    
    Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
+ /mt/dim checkpatch ed157ca0caebebe3af6d38ca0fb64a403c84ce77 drm-intel
772b3260eca8 drm/xe/soc_remapper: Initialize SoC remapper during Xe probe
-:64: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#64: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 66 lines checked
42aa9b58ef4e drm/xe/soc_remapper: Use SoC remapper herlper from VSEC code
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 70 lines checked
ef0e4c3abd43 drm/xe/soc_remapper: Add system controller config for SoC remapper
ccb35d3c011f drm/xe/remapper: Reprogram remapper index on PM resume events
e173e4fea32a drm/xe/sc: Add system controller component for Xe3p dGPU platforms
-:37: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#37: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 666 lines checked

✓ CI.KUnit: success for drm/xe: Add System Controller support for Xe3p dGPU platforms

[Patchwork]

== Series Details ==

Series: drm/xe: Add System Controller support for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/157937/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[22:25:37] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:25:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:26:12] Starting KUnit Kernel (1/1)...
[22:26:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:26:12] ================== guc_buf (11 subtests) ===================
[22:26:12] [PASSED] test_smallest
[22:26:12] [PASSED] test_largest
[22:26:12] [PASSED] test_granular
[22:26:12] [PASSED] test_unique
[22:26:12] [PASSED] test_overlap
[22:26:12] [PASSED] test_reusable
[22:26:12] [PASSED] test_too_big
[22:26:12] [PASSED] test_flush
[22:26:12] [PASSED] test_lookup
[22:26:12] [PASSED] test_data
[22:26:12] [PASSED] test_class
[22:26:12] ===================== [PASSED] guc_buf =====================
[22:26:12] =================== guc_dbm (7 subtests) ===================
[22:26:12] [PASSED] test_empty
[22:26:12] [PASSED] test_default
[22:26:12] ======================== test_size  ========================
[22:26:12] [PASSED] 4
[22:26:12] [PASSED] 8
[22:26:12] [PASSED] 32
[22:26:12] [PASSED] 256
[22:26:12] ==================== [PASSED] test_size ====================
[22:26:12] ======================= test_reuse  ========================
[22:26:12] [PASSED] 4
[22:26:12] [PASSED] 8
[22:26:12] [PASSED] 32
[22:26:12] [PASSED] 256
[22:26:12] =================== [PASSED] test_reuse ====================
[22:26:12] =================== test_range_overlap  ====================
[22:26:12] [PASSED] 4
[22:26:12] [PASSED] 8
[22:26:12] [PASSED] 32
[22:26:12] [PASSED] 256
[22:26:12] =============== [PASSED] test_range_overlap ================
[22:26:13] =================== test_range_compact  ====================
[22:26:13] [PASSED] 4
[22:26:13] [PASSED] 8
[22:26:13] [PASSED] 32
[22:26:13] [PASSED] 256
[22:26:13] =============== [PASSED] test_range_compact ================
[22:26:13] ==================== test_range_spare  =====================
[22:26:13] [PASSED] 4
[22:26:13] [PASSED] 8
[22:26:13] [PASSED] 32
[22:26:13] [PASSED] 256
[22:26:13] ================ [PASSED] test_range_spare =================
[22:26:13] ===================== [PASSED] guc_dbm =====================
[22:26:13] =================== guc_idm (6 subtests) ===================
[22:26:13] [PASSED] bad_init
[22:26:13] [PASSED] no_init
[22:26:13] [PASSED] init_fini
[22:26:13] [PASSED] check_used
[22:26:13] [PASSED] check_quota
[22:26:13] [PASSED] check_all
[22:26:13] ===================== [PASSED] guc_idm =====================
[22:26:13] ================== no_relay (3 subtests) ===================
[22:26:13] [PASSED] xe_drops_guc2pf_if_not_ready
[22:26:13] [PASSED] xe_drops_guc2vf_if_not_ready
[22:26:13] [PASSED] xe_rejects_send_if_not_ready
[22:26:13] ==================== [PASSED] no_relay =====================
[22:26:13] ================== pf_relay (14 subtests) ==================
[22:26:13] [PASSED] pf_rejects_guc2pf_too_short
[22:26:13] [PASSED] pf_rejects_guc2pf_too_long
[22:26:13] [PASSED] pf_rejects_guc2pf_no_payload
[22:26:13] [PASSED] pf_fails_no_payload
[22:26:13] [PASSED] pf_fails_bad_origin
[22:26:13] [PASSED] pf_fails_bad_type
[22:26:13] [PASSED] pf_txn_reports_error
[22:26:13] [PASSED] pf_txn_sends_pf2guc
[22:26:13] [PASSED] pf_sends_pf2guc
[22:26:13] [SKIPPED] pf_loopback_nop
[22:26:13] [SKIPPED] pf_loopback_echo
[22:26:13] [SKIPPED] pf_loopback_fail
[22:26:13] [SKIPPED] pf_loopback_busy
[22:26:13] [SKIPPED] pf_loopback_retry
[22:26:13] ==================== [PASSED] pf_relay =====================
[22:26:13] ================== vf_relay (3 subtests) ===================
[22:26:13] [PASSED] vf_rejects_guc2vf_too_short
[22:26:13] [PASSED] vf_rejects_guc2vf_too_long
[22:26:13] [PASSED] vf_rejects_guc2vf_no_payload
[22:26:13] ==================== [PASSED] vf_relay =====================
[22:26:13] ================ pf_gt_config (6 subtests) =================
[22:26:13] [PASSED] fair_contexts_1vf
[22:26:13] [PASSED] fair_doorbells_1vf
[22:26:13] [PASSED] fair_ggtt_1vf
[22:26:13] ====================== fair_contexts  ======================
[22:26:13] [PASSED] 1 VF
[22:26:13] [PASSED] 2 VFs
[22:26:13] [PASSED] 3 VFs
[22:26:13] [PASSED] 4 VFs
[22:26:13] [PASSED] 5 VFs
[22:26:13] [PASSED] 6 VFs
[22:26:13] [PASSED] 7 VFs
[22:26:13] [PASSED] 8 VFs
[22:26:13] [PASSED] 9 VFs
[22:26:13] [PASSED] 10 VFs
[22:26:13] [PASSED] 11 VFs
[22:26:13] [PASSED] 12 VFs
[22:26:13] [PASSED] 13 VFs
[22:26:13] [PASSED] 14 VFs
[22:26:13] [PASSED] 15 VFs
[22:26:13] [PASSED] 16 VFs
[22:26:13] [PASSED] 17 VFs
[22:26:13] [PASSED] 18 VFs
[22:26:13] [PASSED] 19 VFs
[22:26:13] [PASSED] 20 VFs
[22:26:13] [PASSED] 21 VFs
[22:26:13] [PASSED] 22 VFs
[22:26:13] [PASSED] 23 VFs
[22:26:13] [PASSED] 24 VFs
[22:26:13] [PASSED] 25 VFs
[22:26:13] [PASSED] 26 VFs
[22:26:13] [PASSED] 27 VFs
[22:26:13] [PASSED] 28 VFs
[22:26:13] [PASSED] 29 VFs
[22:26:13] [PASSED] 30 VFs
[22:26:13] [PASSED] 31 VFs
[22:26:13] [PASSED] 32 VFs
[22:26:13] [PASSED] 33 VFs
[22:26:13] [PASSED] 34 VFs
[22:26:13] [PASSED] 35 VFs
[22:26:13] [PASSED] 36 VFs
[22:26:13] [PASSED] 37 VFs
[22:26:13] [PASSED] 38 VFs
[22:26:13] [PASSED] 39 VFs
[22:26:13] [PASSED] 40 VFs
[22:26:13] [PASSED] 41 VFs
[22:26:13] [PASSED] 42 VFs
[22:26:13] [PASSED] 43 VFs
[22:26:13] [PASSED] 44 VFs
[22:26:13] [PASSED] 45 VFs
[22:26:13] [PASSED] 46 VFs
[22:26:13] [PASSED] 47 VFs
[22:26:13] [PASSED] 48 VFs
[22:26:13] [PASSED] 49 VFs
[22:26:13] [PASSED] 50 VFs
[22:26:13] [PASSED] 51 VFs
[22:26:13] [PASSED] 52 VFs
[22:26:13] [PASSED] 53 VFs
[22:26:13] [PASSED] 54 VFs
[22:26:13] [PASSED] 55 VFs
[22:26:13] [PASSED] 56 VFs
[22:26:13] [PASSED] 57 VFs
[22:26:13] [PASSED] 58 VFs
[22:26:13] [PASSED] 59 VFs
[22:26:13] [PASSED] 60 VFs
[22:26:13] [PASSED] 61 VFs
[22:26:13] [PASSED] 62 VFs
[22:26:13] [PASSED] 63 VFs
[22:26:13] ================== [PASSED] fair_contexts ==================
[22:26:13] ===================== fair_doorbells  ======================
[22:26:13] [PASSED] 1 VF
[22:26:13] [PASSED] 2 VFs
[22:26:13] [PASSED] 3 VFs
[22:26:13] [PASSED] 4 VFs
[22:26:13] [PASSED] 5 VFs
[22:26:13] [PASSED] 6 VFs
[22:26:13] [PASSED] 7 VFs
[22:26:13] [PASSED] 8 VFs
[22:26:13] [PASSED] 9 VFs
[22:26:13] [PASSED] 10 VFs
[22:26:13] [PASSED] 11 VFs
[22:26:13] [PASSED] 12 VFs
[22:26:13] [PASSED] 13 VFs
[22:26:13] [PASSED] 14 VFs
[22:26:13] [PASSED] 15 VFs
[22:26:13] [PASSED] 16 VFs
[22:26:13] [PASSED] 17 VFs
[22:26:13] [PASSED] 18 VFs
[22:26:13] [PASSED] 19 VFs
[22:26:13] [PASSED] 20 VFs
[22:26:13] [PASSED] 21 VFs
[22:26:13] [PASSED] 22 VFs
[22:26:13] [PASSED] 23 VFs
[22:26:13] [PASSED] 24 VFs
[22:26:13] [PASSED] 25 VFs
[22:26:13] [PASSED] 26 VFs
[22:26:13] [PASSED] 27 VFs
[22:26:13] [PASSED] 28 VFs
[22:26:13] [PASSED] 29 VFs
[22:26:13] [PASSED] 30 VFs
[22:26:13] [PASSED] 31 VFs
[22:26:13] [PASSED] 32 VFs
[22:26:13] [PASSED] 33 VFs
[22:26:13] [PASSED] 34 VFs
[22:26:13] [PASSED] 35 VFs
[22:26:13] [PASSED] 36 VFs
[22:26:13] [PASSED] 37 VFs
[22:26:13] [PASSED] 38 VFs
[22:26:13] [PASSED] 39 VFs
[22:26:13] [PASSED] 40 VFs
[22:26:13] [PASSED] 41 VFs
[22:26:13] [PASSED] 42 VFs
[22:26:13] [PASSED] 43 VFs
[22:26:13] [PASSED] 44 VFs
[22:26:13] [PASSED] 45 VFs
[22:26:13] [PASSED] 46 VFs
[22:26:13] [PASSED] 47 VFs
[22:26:13] [PASSED] 48 VFs
[22:26:13] [PASSED] 49 VFs
[22:26:13] [PASSED] 50 VFs
[22:26:13] [PASSED] 51 VFs
[22:26:13] [PASSED] 52 VFs
[22:26:13] [PASSED] 53 VFs
[22:26:13] [PASSED] 54 VFs
[22:26:13] [PASSED] 55 VFs
[22:26:13] [PASSED] 56 VFs
[22:26:13] [PASSED] 57 VFs
[22:26:13] [PASSED] 58 VFs
[22:26:13] [PASSED] 59 VFs
[22:26:13] [PASSED] 60 VFs
[22:26:13] [PASSED] 61 VFs
[22:26:13] [PASSED] 62 VFs
[22:26:13] [PASSED] 63 VFs
[22:26:13] ================= [PASSED] fair_doorbells ==================
[22:26:13] ======================== fair_ggtt  ========================
[22:26:13] [PASSED] 1 VF
[22:26:13] [PASSED] 2 VFs
[22:26:13] [PASSED] 3 VFs
[22:26:13] [PASSED] 4 VFs
[22:26:13] [PASSED] 5 VFs
[22:26:13] [PASSED] 6 VFs
[22:26:13] [PASSED] 7 VFs
[22:26:13] [PASSED] 8 VFs
[22:26:13] [PASSED] 9 VFs
[22:26:13] [PASSED] 10 VFs
[22:26:13] [PASSED] 11 VFs
[22:26:13] [PASSED] 12 VFs
[22:26:13] [PASSED] 13 VFs
[22:26:13] [PASSED] 14 VFs
[22:26:13] [PASSED] 15 VFs
[22:26:13] [PASSED] 16 VFs
[22:26:13] [PASSED] 17 VFs
[22:26:13] [PASSED] 18 VFs
[22:26:13] [PASSED] 19 VFs
[22:26:13] [PASSED] 20 VFs
[22:26:13] [PASSED] 21 VFs
[22:26:13] [PASSED] 22 VFs
[22:26:13] [PASSED] 23 VFs
[22:26:13] [PASSED] 24 VFs
[22:26:13] [PASSED] 25 VFs
[22:26:13] [PASSED] 26 VFs
[22:26:13] [PASSED] 27 VFs
[22:26:13] [PASSED] 28 VFs
[22:26:13] [PASSED] 29 VFs
[22:26:13] [PASSED] 30 VFs
[22:26:13] [PASSED] 31 VFs
[22:26:13] [PASSED] 32 VFs
[22:26:13] [PASSED] 33 VFs
[22:26:13] [PASSED] 34 VFs
[22:26:13] [PASSED] 35 VFs
[22:26:13] [PASSED] 36 VFs
[22:26:13] [PASSED] 37 VFs
[22:26:13] [PASSED] 38 VFs
[22:26:13] [PASSED] 39 VFs
[22:26:13] [PASSED] 40 VFs
[22:26:13] [PASSED] 41 VFs
[22:26:13] [PASSED] 42 VFs
[22:26:13] [PASSED] 43 VFs
[22:26:13] [PASSED] 44 VFs
[22:26:13] [PASSED] 45 VFs
[22:26:13] [PASSED] 46 VFs
[22:26:13] [PASSED] 47 VFs
[22:26:13] [PASSED] 48 VFs
[22:26:13] [PASSED] 49 VFs
[22:26:13] [PASSED] 50 VFs
[22:26:13] [PASSED] 51 VFs
[22:26:13] [PASSED] 52 VFs
[22:26:13] [PASSED] 53 VFs
[22:26:13] [PASSED] 54 VFs
[22:26:13] [PASSED] 55 VFs
[22:26:13] [PASSED] 56 VFs
[22:26:13] [PASSED] 57 VFs
[22:26:13] [PASSED] 58 VFs
[22:26:13] [PASSED] 59 VFs
[22:26:13] [PASSED] 60 VFs
[22:26:13] [PASSED] 61 VFs
[22:26:13] [PASSED] 62 VFs
[22:26:13] [PASSED] 63 VFs
[22:26:13] ==================== [PASSED] fair_ggtt ====================
[22:26:13] ================== [PASSED] pf_gt_config ===================
[22:26:13] ===================== lmtt (1 subtest) =====================
[22:26:13] ======================== test_ops  =========================
[22:26:13] [PASSED] 2-level
[22:26:13] [PASSED] multi-level
[22:26:13] ==================== [PASSED] test_ops =====================
[22:26:13] ====================== [PASSED] lmtt =======================
[22:26:13] ================= pf_service (11 subtests) =================
[22:26:13] [PASSED] pf_negotiate_any
[22:26:13] [PASSED] pf_negotiate_base_match
[22:26:13] [PASSED] pf_negotiate_base_newer
[22:26:13] [PASSED] pf_negotiate_base_next
[22:26:13] [SKIPPED] pf_negotiate_base_older
[22:26:13] [PASSED] pf_negotiate_base_prev
[22:26:13] [PASSED] pf_negotiate_latest_match
[22:26:13] [PASSED] pf_negotiate_latest_newer
[22:26:13] [PASSED] pf_negotiate_latest_next
[22:26:13] [SKIPPED] pf_negotiate_latest_older
[22:26:13] [SKIPPED] pf_negotiate_latest_prev
[22:26:13] =================== [PASSED] pf_service ====================
[22:26:13] ================= xe_guc_g2g (2 subtests) ==================
[22:26:13] ============== xe_live_guc_g2g_kunit_default  ==============
[22:26:13] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[22:26:13] ============== xe_live_guc_g2g_kunit_allmem  ===============
[22:26:13] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[22:26:13] =================== [SKIPPED] xe_guc_g2g ===================
[22:26:13] =================== xe_mocs (2 subtests) ===================
[22:26:13] ================ xe_live_mocs_kernel_kunit  ================
[22:26:13] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[22:26:13] ================ xe_live_mocs_reset_kunit  =================
[22:26:13] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[22:26:13] ==================== [SKIPPED] xe_mocs =====================
[22:26:13] ================= xe_migrate (2 subtests) ==================
[22:26:13] ================= xe_migrate_sanity_kunit  =================
[22:26:13] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[22:26:13] ================== xe_validate_ccs_kunit  ==================
[22:26:13] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[22:26:13] =================== [SKIPPED] xe_migrate ===================
[22:26:13] ================== xe_dma_buf (1 subtest) ==================
[22:26:13] ==================== xe_dma_buf_kunit  =====================
[22:26:13] ================ [SKIPPED] xe_dma_buf_kunit ================
[22:26:13] =================== [SKIPPED] xe_dma_buf ===================
[22:26:13] ================= xe_bo_shrink (1 subtest) =================
[22:26:13] =================== xe_bo_shrink_kunit  ====================
[22:26:13] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[22:26:13] ================== [SKIPPED] xe_bo_shrink ==================
[22:26:13] ==================== xe_bo (2 subtests) ====================
[22:26:13] ================== xe_ccs_migrate_kunit  ===================
[22:26:13] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[22:26:13] ==================== xe_bo_evict_kunit  ====================
[22:26:13] =============== [SKIPPED] xe_bo_evict_kunit ================
[22:26:13] ===================== [SKIPPED] xe_bo ======================
[22:26:13] ==================== args (11 subtests) ====================
[22:26:13] [PASSED] count_args_test
[22:26:13] [PASSED] call_args_example
[22:26:13] [PASSED] call_args_test
[22:26:13] [PASSED] drop_first_arg_example
[22:26:13] [PASSED] drop_first_arg_test
[22:26:13] [PASSED] first_arg_example
[22:26:13] [PASSED] first_arg_test
[22:26:13] [PASSED] last_arg_example
[22:26:13] [PASSED] last_arg_test
[22:26:13] [PASSED] pick_arg_example
[22:26:13] [PASSED] sep_comma_example
[22:26:13] ====================== [PASSED] args =======================
[22:26:13] =================== xe_pci (3 subtests) ====================
[22:26:13] ==================== check_graphics_ip  ====================
[22:26:13] [PASSED] 12.00 Xe_LP
[22:26:13] [PASSED] 12.10 Xe_LP+
[22:26:13] [PASSED] 12.55 Xe_HPG
[22:26:13] [PASSED] 12.60 Xe_HPC
[22:26:13] [PASSED] 12.70 Xe_LPG
[22:26:13] [PASSED] 12.71 Xe_LPG
[22:26:13] [PASSED] 12.74 Xe_LPG+
[22:26:13] [PASSED] 20.01 Xe2_HPG
[22:26:13] [PASSED] 20.02 Xe2_HPG
[22:26:13] [PASSED] 20.04 Xe2_LPG
[22:26:13] [PASSED] 30.00 Xe3_LPG
[22:26:13] [PASSED] 30.01 Xe3_LPG
[22:26:13] [PASSED] 30.03 Xe3_LPG
[22:26:13] [PASSED] 30.04 Xe3_LPG
[22:26:13] [PASSED] 30.05 Xe3_LPG
[22:26:13] [PASSED] 35.11 Xe3p_XPC
[22:26:13] ================ [PASSED] check_graphics_ip ================
[22:26:13] ===================== check_media_ip  ======================
[22:26:13] [PASSED] 12.00 Xe_M
[22:26:13] [PASSED] 12.55 Xe_HPM
[22:26:13] [PASSED] 13.00 Xe_LPM+
[22:26:13] [PASSED] 13.01 Xe2_HPM
[22:26:13] [PASSED] 20.00 Xe2_LPM
[22:26:13] [PASSED] 30.00 Xe3_LPM
[22:26:13] [PASSED] 30.02 Xe3_LPM
[22:26:13] [PASSED] 35.00 Xe3p_LPM
[22:26:13] [PASSED] 35.03 Xe3p_HPM
[22:26:13] ================= [PASSED] check_media_ip ==================
[22:26:13] =================== check_platform_desc  ===================
[22:26:13] [PASSED] 0x9A60 (TIGERLAKE)
[22:26:13] [PASSED] 0x9A68 (TIGERLAKE)
[22:26:13] [PASSED] 0x9A70 (TIGERLAKE)
[22:26:13] [PASSED] 0x9A40 (TIGERLAKE)
[22:26:13] [PASSED] 0x9A49 (TIGERLAKE)
[22:26:13] [PASSED] 0x9A59 (TIGERLAKE)
[22:26:13] [PASSED] 0x9A78 (TIGERLAKE)
[22:26:13] [PASSED] 0x9AC0 (TIGERLAKE)
[22:26:13] [PASSED] 0x9AC9 (TIGERLAKE)
[22:26:13] [PASSED] 0x9AD9 (TIGERLAKE)
[22:26:13] [PASSED] 0x9AF8 (TIGERLAKE)
[22:26:13] [PASSED] 0x4C80 (ROCKETLAKE)
[22:26:13] [PASSED] 0x4C8A (ROCKETLAKE)
[22:26:13] [PASSED] 0x4C8B (ROCKETLAKE)
[22:26:13] [PASSED] 0x4C8C (ROCKETLAKE)
[22:26:13] [PASSED] 0x4C90 (ROCKETLAKE)
[22:26:13] [PASSED] 0x4C9A (ROCKETLAKE)
[22:26:13] [PASSED] 0x4680 (ALDERLAKE_S)
[22:26:13] [PASSED] 0x4682 (ALDERLAKE_S)
[22:26:13] [PASSED] 0x4688 (ALDERLAKE_S)
[22:26:13] [PASSED] 0x468A (ALDERLAKE_S)
[22:26:13] [PASSED] 0x468B (ALDERLAKE_S)
[22:26:13] [PASSED] 0x4690 (ALDERLAKE_S)
[22:26:13] [PASSED] 0x4692 (ALDERLAKE_S)
[22:26:13] [PASSED] 0x4693 (ALDERLAKE_S)
[22:26:13] [PASSED] 0x46A0 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46A1 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46A2 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46A3 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46A6 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46A8 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46AA (ALDERLAKE_P)
[22:26:13] [PASSED] 0x462A (ALDERLAKE_P)
[22:26:13] [PASSED] 0x4626 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x4628 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46B0 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[22:26:13] [PASSED] 0x46B1 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46B2 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46B3 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46C0 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46C1 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46C2 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46C3 (ALDERLAKE_P)
[22:26:13] [PASSED] 0x46D0 (ALDERLAKE_N)
[22:26:13] [PASSED] 0x46D1 (ALDERLAKE_N)
[22:26:13] [PASSED] 0x46D2 (ALDERLAKE_N)
[22:26:13] [PASSED] 0x46D3 (ALDERLAKE_N)
[22:26:13] [PASSED] 0x46D4 (ALDERLAKE_N)
[22:26:13] [PASSED] 0xA721 (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7A1 (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7A9 (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7AC (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7AD (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA720 (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7A0 (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7A8 (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7AA (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA7AB (ALDERLAKE_P)
[22:26:13] [PASSED] 0xA780 (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA781 (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA782 (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA783 (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA788 (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA789 (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA78A (ALDERLAKE_S)
[22:26:13] [PASSED] 0xA78B (ALDERLAKE_S)
[22:26:13] [PASSED] 0x4905 (DG1)
[22:26:13] [PASSED] 0x4906 (DG1)
[22:26:13] [PASSED] 0x4907 (DG1)
[22:26:13] [PASSED] 0x4908 (DG1)
[22:26:13] [PASSED] 0x4909 (DG1)
[22:26:13] [PASSED] 0x56C0 (DG2)
[22:26:13] [PASSED] 0x56C2 (DG2)
[22:26:13] [PASSED] 0x56C1 (DG2)
[22:26:13] [PASSED] 0x7D51 (METEORLAKE)
[22:26:13] [PASSED] 0x7DD1 (METEORLAKE)
[22:26:13] [PASSED] 0x7D41 (METEORLAKE)
[22:26:13] [PASSED] 0x7D67 (METEORLAKE)
[22:26:13] [PASSED] 0xB640 (METEORLAKE)
[22:26:13] [PASSED] 0x56A0 (DG2)
[22:26:13] [PASSED] 0x56A1 (DG2)
[22:26:13] [PASSED] 0x56A2 (DG2)
[22:26:13] [PASSED] 0x56BE (DG2)
[22:26:13] [PASSED] 0x56BF (DG2)
[22:26:13] [PASSED] 0x5690 (DG2)
[22:26:13] [PASSED] 0x5691 (DG2)
[22:26:13] [PASSED] 0x5692 (DG2)
[22:26:13] [PASSED] 0x56A5 (DG2)
[22:26:13] [PASSED] 0x56A6 (DG2)
[22:26:13] [PASSED] 0x56B0 (DG2)
[22:26:13] [PASSED] 0x56B1 (DG2)
[22:26:13] [PASSED] 0x56BA (DG2)
[22:26:13] [PASSED] 0x56BB (DG2)
[22:26:13] [PASSED] 0x56BC (DG2)
[22:26:13] [PASSED] 0x56BD (DG2)
[22:26:13] [PASSED] 0x5693 (DG2)
[22:26:13] [PASSED] 0x5694 (DG2)
[22:26:13] [PASSED] 0x5695 (DG2)
[22:26:13] [PASSED] 0x56A3 (DG2)
[22:26:13] [PASSED] 0x56A4 (DG2)
[22:26:13] [PASSED] 0x56B2 (DG2)
[22:26:13] [PASSED] 0x56B3 (DG2)
[22:26:13] [PASSED] 0x5696 (DG2)
[22:26:13] [PASSED] 0x5697 (DG2)
[22:26:13] [PASSED] 0xB69 (PVC)
[22:26:13] [PASSED] 0xB6E (PVC)
[22:26:13] [PASSED] 0xBD4 (PVC)
[22:26:13] [PASSED] 0xBD5 (PVC)
[22:26:13] [PASSED] 0xBD6 (PVC)
[22:26:13] [PASSED] 0xBD7 (PVC)
[22:26:13] [PASSED] 0xBD8 (PVC)
[22:26:13] [PASSED] 0xBD9 (PVC)
[22:26:13] [PASSED] 0xBDA (PVC)
[22:26:13] [PASSED] 0xBDB (PVC)
[22:26:13] [PASSED] 0xBE0 (PVC)
[22:26:13] [PASSED] 0xBE1 (PVC)
[22:26:13] [PASSED] 0xBE5 (PVC)
[22:26:13] [PASSED] 0x7D40 (METEORLAKE)
[22:26:13] [PASSED] 0x7D45 (METEORLAKE)
[22:26:13] [PASSED] 0x7D55 (METEORLAKE)
[22:26:13] [PASSED] 0x7D60 (METEORLAKE)
[22:26:13] [PASSED] 0x7DD5 (METEORLAKE)
[22:26:13] [PASSED] 0x6420 (LUNARLAKE)
[22:26:13] [PASSED] 0x64A0 (LUNARLAKE)
[22:26:13] [PASSED] 0x64B0 (LUNARLAKE)
[22:26:13] [PASSED] 0xE202 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE209 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE20B (BATTLEMAGE)
[22:26:13] [PASSED] 0xE20C (BATTLEMAGE)
[22:26:13] [PASSED] 0xE20D (BATTLEMAGE)
[22:26:13] [PASSED] 0xE210 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE211 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE212 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE216 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE220 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE221 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE222 (BATTLEMAGE)
[22:26:13] [PASSED] 0xE223 (BATTLEMAGE)
[22:26:13] [PASSED] 0xB080 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB081 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB082 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB083 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB084 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB085 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB086 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB087 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB08F (PANTHERLAKE)
[22:26:13] [PASSED] 0xB090 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB0A0 (PANTHERLAKE)
[22:26:13] [PASSED] 0xB0B0 (PANTHERLAKE)
[22:26:13] [PASSED] 0xD740 (NOVALAKE_S)
[22:26:13] [PASSED] 0xD741 (NOVALAKE_S)
[22:26:13] [PASSED] 0xD742 (NOVALAKE_S)
[22:26:13] [PASSED] 0xD743 (NOVALAKE_S)
[22:26:13] [PASSED] 0xD744 (NOVALAKE_S)
[22:26:13] [PASSED] 0xD745 (NOVALAKE_S)
[22:26:13] [PASSED] 0x674C (CRESCENTISLAND)
[22:26:13] [PASSED] 0xFD80 (PANTHERLAKE)
[22:26:13] [PASSED] 0xFD81 (PANTHERLAKE)
[22:26:13] =============== [PASSED] check_platform_desc ===============
[22:26:13] ===================== [PASSED] xe_pci ======================
[22:26:13] =================== xe_rtp (2 subtests) ====================
[22:26:13] =============== xe_rtp_process_to_sr_tests  ================
[22:26:13] [PASSED] coalesce-same-reg
[22:26:13] [PASSED] no-match-no-add
[22:26:13] [PASSED] match-or
[22:26:13] [PASSED] match-or-xfail
[22:26:13] [PASSED] no-match-no-add-multiple-rules
[22:26:13] [PASSED] two-regs-two-entries
[22:26:13] [PASSED] clr-one-set-other
[22:26:13] [PASSED] set-field
[22:26:13] [PASSED] conflict-duplicate
[22:26:13] [PASSED] conflict-not-disjoint
[22:26:13] [PASSED] conflict-reg-type
[22:26:13] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[22:26:13] ================== xe_rtp_process_tests  ===================
[22:26:13] [PASSED] active1
[22:26:13] [PASSED] active2
[22:26:13] [PASSED] active-inactive
[22:26:13] [PASSED] inactive-active
[22:26:13] [PASSED] inactive-1st_or_active-inactive
[22:26:13] [PASSED] inactive-2nd_or_active-inactive
[22:26:13] [PASSED] inactive-last_or_active-inactive
[22:26:13] [PASSED] inactive-no_or_active-inactive
[22:26:13] ============== [PASSED] xe_rtp_process_tests ===============
[22:26:13] ===================== [PASSED] xe_rtp ======================
[22:26:13] ==================== xe_wa (1 subtest) =====================
[22:26:13] ======================== xe_wa_gt  =========================
[22:26:13] [PASSED] TIGERLAKE B0
[22:26:13] [PASSED] DG1 A0
[22:26:13] [PASSED] DG1 B0
[22:26:13] [PASSED] ALDERLAKE_S A0
[22:26:13] [PASSED] ALDERLAKE_S B0
[22:26:13] [PASSED] ALDERLAKE_S C0
[22:26:13] [PASSED] ALDERLAKE_S D0
[22:26:13] [PASSED] ALDERLAKE_P A0
[22:26:13] [PASSED] ALDERLAKE_P B0
[22:26:13] [PASSED] ALDERLAKE_P C0
[22:26:13] [PASSED] ALDERLAKE_S RPLS D0
[22:26:13] [PASSED] ALDERLAKE_P RPLU E0
[22:26:13] [PASSED] DG2 G10 C0
[22:26:13] [PASSED] DG2 G11 B1
[22:26:13] [PASSED] DG2 G12 A1
[22:26:13] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:26:13] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[22:26:13] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[22:26:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[22:26:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[22:26:13] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[22:26:13] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[22:26:13] ==================== [PASSED] xe_wa_gt =====================
[22:26:13] ====================== [PASSED] xe_wa ======================
[22:26:13] ============================================================
[22:26:13] Testing complete. Ran 510 tests: passed: 492, skipped: 18
[22:26:13] Elapsed time: 35.854s total, 4.266s configuring, 31.072s building, 0.462s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[22:26:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:26:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:26:40] Starting KUnit Kernel (1/1)...
[22:26:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:26:40] ============ drm_test_pick_cmdline (2 subtests) ============
[22:26:40] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[22:26:40] =============== drm_test_pick_cmdline_named  ===============
[22:26:40] [PASSED] NTSC
[22:26:40] [PASSED] NTSC-J
[22:26:40] [PASSED] PAL
[22:26:40] [PASSED] PAL-M
[22:26:40] =========== [PASSED] drm_test_pick_cmdline_named ===========
[22:26:40] ============== [PASSED] drm_test_pick_cmdline ==============
[22:26:40] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[22:26:40] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[22:26:40] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[22:26:40] =========== drm_validate_clone_mode (2 subtests) ===========
[22:26:40] ============== drm_test_check_in_clone_mode  ===============
[22:26:40] [PASSED] in_clone_mode
[22:26:40] [PASSED] not_in_clone_mode
[22:26:40] ========== [PASSED] drm_test_check_in_clone_mode ===========
[22:26:40] =============== drm_test_check_valid_clones  ===============
[22:26:40] [PASSED] not_in_clone_mode
[22:26:40] [PASSED] valid_clone
[22:26:40] [PASSED] invalid_clone
[22:26:40] =========== [PASSED] drm_test_check_valid_clones ===========
[22:26:40] ============= [PASSED] drm_validate_clone_mode =============
[22:26:40] ============= drm_validate_modeset (1 subtest) =============
[22:26:40] [PASSED] drm_test_check_connector_changed_modeset
[22:26:40] ============== [PASSED] drm_validate_modeset ===============
[22:26:40] ====== drm_test_bridge_get_current_state (2 subtests) ======
[22:26:40] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[22:26:40] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[22:26:40] ======== [PASSED] drm_test_bridge_get_current_state ========
[22:26:40] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[22:26:40] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[22:26:40] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[22:26:40] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[22:26:40] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[22:26:40] ============== drm_bridge_alloc (2 subtests) ===============
[22:26:40] [PASSED] drm_test_drm_bridge_alloc_basic
[22:26:40] [PASSED] drm_test_drm_bridge_alloc_get_put
[22:26:40] ================ [PASSED] drm_bridge_alloc =================
[22:26:40] ================== drm_buddy (8 subtests) ==================
[22:26:40] [PASSED] drm_test_buddy_alloc_limit
[22:26:40] [PASSED] drm_test_buddy_alloc_optimistic
[22:26:40] [PASSED] drm_test_buddy_alloc_pessimistic
[22:26:40] [PASSED] drm_test_buddy_alloc_pathological
[22:26:40] [PASSED] drm_test_buddy_alloc_contiguous
[22:26:40] [PASSED] drm_test_buddy_alloc_clear
[22:26:40] [PASSED] drm_test_buddy_alloc_range_bias
[22:26:40] [PASSED] drm_test_buddy_fragmentation_performance
[22:26:40] ==================== [PASSED] drm_buddy ====================
[22:26:40] ============= drm_cmdline_parser (40 subtests) =============
[22:26:40] [PASSED] drm_test_cmdline_force_d_only
[22:26:40] [PASSED] drm_test_cmdline_force_D_only_dvi
[22:26:40] [PASSED] drm_test_cmdline_force_D_only_hdmi
[22:26:40] [PASSED] drm_test_cmdline_force_D_only_not_digital
[22:26:40] [PASSED] drm_test_cmdline_force_e_only
[22:26:40] [PASSED] drm_test_cmdline_res
[22:26:40] [PASSED] drm_test_cmdline_res_vesa
[22:26:40] [PASSED] drm_test_cmdline_res_vesa_rblank
[22:26:40] [PASSED] drm_test_cmdline_res_rblank
[22:26:40] [PASSED] drm_test_cmdline_res_bpp
[22:26:40] [PASSED] drm_test_cmdline_res_refresh
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[22:26:40] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[22:26:40] [PASSED] drm_test_cmdline_res_margins_force_on
[22:26:40] [PASSED] drm_test_cmdline_res_vesa_margins
[22:26:40] [PASSED] drm_test_cmdline_name
[22:26:40] [PASSED] drm_test_cmdline_name_bpp
[22:26:40] [PASSED] drm_test_cmdline_name_option
[22:26:40] [PASSED] drm_test_cmdline_name_bpp_option
[22:26:40] [PASSED] drm_test_cmdline_rotate_0
[22:26:40] [PASSED] drm_test_cmdline_rotate_90
[22:26:40] [PASSED] drm_test_cmdline_rotate_180
[22:26:40] [PASSED] drm_test_cmdline_rotate_270
[22:26:40] [PASSED] drm_test_cmdline_hmirror
[22:26:40] [PASSED] drm_test_cmdline_vmirror
[22:26:40] [PASSED] drm_test_cmdline_margin_options
[22:26:40] [PASSED] drm_test_cmdline_multiple_options
[22:26:40] [PASSED] drm_test_cmdline_bpp_extra_and_option
[22:26:40] [PASSED] drm_test_cmdline_extra_and_option
[22:26:40] [PASSED] drm_test_cmdline_freestanding_options
[22:26:40] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[22:26:40] [PASSED] drm_test_cmdline_panel_orientation
[22:26:40] ================ drm_test_cmdline_invalid  =================
[22:26:40] [PASSED] margin_only
[22:26:40] [PASSED] interlace_only
[22:26:40] [PASSED] res_missing_x
[22:26:40] [PASSED] res_missing_y
[22:26:40] [PASSED] res_bad_y
[22:26:40] [PASSED] res_missing_y_bpp
[22:26:40] [PASSED] res_bad_bpp
[22:26:40] [PASSED] res_bad_refresh
[22:26:40] [PASSED] res_bpp_refresh_force_on_off
[22:26:40] [PASSED] res_invalid_mode
[22:26:40] [PASSED] res_bpp_wrong_place_mode
[22:26:40] [PASSED] name_bpp_refresh
[22:26:40] [PASSED] name_refresh
[22:26:40] [PASSED] name_refresh_wrong_mode
[22:26:40] [PASSED] name_refresh_invalid_mode
[22:26:40] [PASSED] rotate_multiple
[22:26:40] [PASSED] rotate_invalid_val
[22:26:40] [PASSED] rotate_truncated
[22:26:40] [PASSED] invalid_option
[22:26:40] [PASSED] invalid_tv_option
[22:26:40] [PASSED] truncated_tv_option
[22:26:40] ============ [PASSED] drm_test_cmdline_invalid =============
[22:26:40] =============== drm_test_cmdline_tv_options  ===============
[22:26:40] [PASSED] NTSC
[22:26:40] [PASSED] NTSC_443
[22:26:40] [PASSED] NTSC_J
[22:26:40] [PASSED] PAL
[22:26:40] [PASSED] PAL_M
[22:26:40] [PASSED] PAL_N
[22:26:40] [PASSED] SECAM
[22:26:40] [PASSED] MONO_525
[22:26:40] [PASSED] MONO_625
[22:26:40] =========== [PASSED] drm_test_cmdline_tv_options ===========
[22:26:40] =============== [PASSED] drm_cmdline_parser ================
[22:26:40] ========== drmm_connector_hdmi_init (20 subtests) ==========
[22:26:40] [PASSED] drm_test_connector_hdmi_init_valid
[22:26:40] [PASSED] drm_test_connector_hdmi_init_bpc_8
[22:26:40] [PASSED] drm_test_connector_hdmi_init_bpc_10
[22:26:40] [PASSED] drm_test_connector_hdmi_init_bpc_12
[22:26:40] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[22:26:40] [PASSED] drm_test_connector_hdmi_init_bpc_null
[22:26:40] [PASSED] drm_test_connector_hdmi_init_formats_empty
[22:26:40] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[22:26:40] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[22:26:40] [PASSED] supported_formats=0x9 yuv420_allowed=1
[22:26:40] [PASSED] supported_formats=0x9 yuv420_allowed=0
[22:26:40] [PASSED] supported_formats=0x3 yuv420_allowed=1
[22:26:40] [PASSED] supported_formats=0x3 yuv420_allowed=0
[22:26:40] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[22:26:40] [PASSED] drm_test_connector_hdmi_init_null_ddc
[22:26:40] [PASSED] drm_test_connector_hdmi_init_null_product
[22:26:40] [PASSED] drm_test_connector_hdmi_init_null_vendor
[22:26:40] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[22:26:40] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[22:26:40] [PASSED] drm_test_connector_hdmi_init_product_valid
[22:26:40] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[22:26:40] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[22:26:40] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[22:26:40] ========= drm_test_connector_hdmi_init_type_valid  =========
[22:26:40] [PASSED] HDMI-A
[22:26:40] [PASSED] HDMI-B
[22:26:40] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[22:26:40] ======== drm_test_connector_hdmi_init_type_invalid  ========
[22:26:40] [PASSED] Unknown
[22:26:40] [PASSED] VGA
[22:26:40] [PASSED] DVI-I
[22:26:40] [PASSED] DVI-D
[22:26:40] [PASSED] DVI-A
[22:26:40] [PASSED] Composite
[22:26:40] [PASSED] SVIDEO
[22:26:40] [PASSED] LVDS
[22:26:40] [PASSED] Component
[22:26:40] [PASSED] DIN
[22:26:40] [PASSED] DP
[22:26:40] [PASSED] TV
[22:26:40] [PASSED] eDP
[22:26:40] [PASSED] Virtual
[22:26:40] [PASSED] DSI
[22:26:40] [PASSED] DPI
[22:26:40] [PASSED] Writeback
[22:26:40] [PASSED] SPI
[22:26:40] [PASSED] USB
[22:26:40] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[22:26:40] ============ [PASSED] drmm_connector_hdmi_init =============
[22:26:40] ============= drmm_connector_init (3 subtests) =============
[22:26:40] [PASSED] drm_test_drmm_connector_init
[22:26:40] [PASSED] drm_test_drmm_connector_init_null_ddc
[22:26:40] ========= drm_test_drmm_connector_init_type_valid  =========
[22:26:40] [PASSED] Unknown
[22:26:40] [PASSED] VGA
[22:26:40] [PASSED] DVI-I
[22:26:40] [PASSED] DVI-D
[22:26:40] [PASSED] DVI-A
[22:26:40] [PASSED] Composite
[22:26:40] [PASSED] SVIDEO
[22:26:40] [PASSED] LVDS
[22:26:40] [PASSED] Component
[22:26:40] [PASSED] DIN
[22:26:40] [PASSED] DP
[22:26:40] [PASSED] HDMI-A
[22:26:40] [PASSED] HDMI-B
[22:26:40] [PASSED] TV
[22:26:40] [PASSED] eDP
[22:26:40] [PASSED] Virtual
[22:26:40] [PASSED] DSI
[22:26:40] [PASSED] DPI
[22:26:40] [PASSED] Writeback
[22:26:40] [PASSED] SPI
[22:26:40] [PASSED] USB
[22:26:40] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[22:26:40] =============== [PASSED] drmm_connector_init ===============
[22:26:40] ========= drm_connector_dynamic_init (6 subtests) ==========
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_init
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_init_properties
[22:26:40] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[22:26:40] [PASSED] Unknown
[22:26:40] [PASSED] VGA
[22:26:40] [PASSED] DVI-I
[22:26:40] [PASSED] DVI-D
[22:26:40] [PASSED] DVI-A
[22:26:40] [PASSED] Composite
[22:26:40] [PASSED] SVIDEO
[22:26:40] [PASSED] LVDS
[22:26:40] [PASSED] Component
[22:26:40] [PASSED] DIN
[22:26:40] [PASSED] DP
[22:26:40] [PASSED] HDMI-A
[22:26:40] [PASSED] HDMI-B
[22:26:40] [PASSED] TV
[22:26:40] [PASSED] eDP
[22:26:40] [PASSED] Virtual
[22:26:40] [PASSED] DSI
[22:26:40] [PASSED] DPI
[22:26:40] [PASSED] Writeback
[22:26:40] [PASSED] SPI
[22:26:40] [PASSED] USB
[22:26:40] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[22:26:40] ======== drm_test_drm_connector_dynamic_init_name  =========
[22:26:40] [PASSED] Unknown
[22:26:40] [PASSED] VGA
[22:26:40] [PASSED] DVI-I
[22:26:40] [PASSED] DVI-D
[22:26:40] [PASSED] DVI-A
[22:26:40] [PASSED] Composite
[22:26:40] [PASSED] SVIDEO
[22:26:40] [PASSED] LVDS
[22:26:40] [PASSED] Component
[22:26:40] [PASSED] DIN
[22:26:40] [PASSED] DP
[22:26:40] [PASSED] HDMI-A
[22:26:40] [PASSED] HDMI-B
[22:26:40] [PASSED] TV
[22:26:40] [PASSED] eDP
[22:26:40] [PASSED] Virtual
[22:26:40] [PASSED] DSI
[22:26:40] [PASSED] DPI
[22:26:40] [PASSED] Writeback
[22:26:40] [PASSED] SPI
[22:26:40] [PASSED] USB
[22:26:40] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[22:26:40] =========== [PASSED] drm_connector_dynamic_init ============
[22:26:40] ==== drm_connector_dynamic_register_early (4 subtests) =====
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[22:26:40] ====== [PASSED] drm_connector_dynamic_register_early =======
[22:26:40] ======= drm_connector_dynamic_register (7 subtests) ========
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[22:26:40] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[22:26:40] ========= [PASSED] drm_connector_dynamic_register ==========
[22:26:40] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[22:26:40] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[22:26:40] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[22:26:40] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[22:26:40] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[22:26:40] ========== drm_test_get_tv_mode_from_name_valid  ===========
[22:26:40] [PASSED] NTSC
[22:26:40] [PASSED] NTSC-443
[22:26:40] [PASSED] NTSC-J
[22:26:40] [PASSED] PAL
[22:26:40] [PASSED] PAL-M
[22:26:40] [PASSED] PAL-N
[22:26:40] [PASSED] SECAM
[22:26:40] [PASSED] Mono
[22:26:40] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[22:26:40] [PASSED] drm_test_get_tv_mode_from_name_truncated
[22:26:40] ============ [PASSED] drm_get_tv_mode_from_name ============
[22:26:40] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[22:26:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[22:26:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[22:26:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[22:26:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[22:26:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[22:26:40] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[22:26:40] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[22:26:40] [PASSED] VIC 96
[22:26:40] [PASSED] VIC 97
[22:26:40] [PASSED] VIC 101
[22:26:40] [PASSED] VIC 102
[22:26:40] [PASSED] VIC 106
[22:26:40] [PASSED] VIC 107
[22:26:40] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[22:26:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[22:26:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[22:26:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[22:26:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[22:26:40] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[22:26:40] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[22:26:40] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[22:26:40] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[22:26:40] [PASSED] Automatic
[22:26:40] [PASSED] Full
[22:26:40] [PASSED] Limited 16:235
[22:26:40] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[22:26:40] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[22:26:40] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[22:26:40] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[22:26:40] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[22:26:40] [PASSED] RGB
[22:26:40] [PASSED] YUV 4:2:0
[22:26:40] [PASSED] YUV 4:2:2
[22:26:40] [PASSED] YUV 4:4:4
[22:26:40] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[22:26:40] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[22:26:40] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[22:26:40] ============= drm_damage_helper (21 subtests) ==============
[22:26:40] [PASSED] drm_test_damage_iter_no_damage
[22:26:40] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[22:26:40] [PASSED] drm_test_damage_iter_no_damage_src_moved
[22:26:40] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[22:26:40] [PASSED] drm_test_damage_iter_no_damage_not_visible
[22:26:40] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[22:26:40] [PASSED] drm_test_damage_iter_no_damage_no_fb
[22:26:40] [PASSED] drm_test_damage_iter_simple_damage
[22:26:40] [PASSED] drm_test_damage_iter_single_damage
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_outside_src
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_src_moved
[22:26:40] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[22:26:40] [PASSED] drm_test_damage_iter_damage
[22:26:40] [PASSED] drm_test_damage_iter_damage_one_intersect
[22:26:40] [PASSED] drm_test_damage_iter_damage_one_outside
[22:26:40] [PASSED] drm_test_damage_iter_damage_src_moved
[22:26:40] [PASSED] drm_test_damage_iter_damage_not_visible
[22:26:40] ================ [PASSED] drm_damage_helper ================
[22:26:40] ============== drm_dp_mst_helper (3 subtests) ==============
[22:26:40] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[22:26:40] [PASSED] Clock 154000 BPP 30 DSC disabled
[22:26:40] [PASSED] Clock 234000 BPP 30 DSC disabled
[22:26:40] [PASSED] Clock 297000 BPP 24 DSC disabled
[22:26:40] [PASSED] Clock 332880 BPP 24 DSC enabled
[22:26:40] [PASSED] Clock 324540 BPP 24 DSC enabled
[22:26:40] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[22:26:40] ============== drm_test_dp_mst_calc_pbn_div  ===============
[22:26:40] [PASSED] Link rate 2000000 lane count 4
[22:26:40] [PASSED] Link rate 2000000 lane count 2
[22:26:40] [PASSED] Link rate 2000000 lane count 1
[22:26:40] [PASSED] Link rate 1350000 lane count 4
[22:26:40] [PASSED] Link rate 1350000 lane count 2
[22:26:40] [PASSED] Link rate 1350000 lane count 1
[22:26:40] [PASSED] Link rate 1000000 lane count 4
[22:26:40] [PASSED] Link rate 1000000 lane count 2
[22:26:40] [PASSED] Link rate 1000000 lane count 1
[22:26:40] [PASSED] Link rate 810000 lane count 4
[22:26:40] [PASSED] Link rate 810000 lane count 2
[22:26:40] [PASSED] Link rate 810000 lane count 1
[22:26:40] [PASSED] Link rate 540000 lane count 4
[22:26:40] [PASSED] Link rate 540000 lane count 2
[22:26:40] [PASSED] Link rate 540000 lane count 1
[22:26:40] [PASSED] Link rate 270000 lane count 4
[22:26:40] [PASSED] Link rate 270000 lane count 2
[22:26:40] [PASSED] Link rate 270000 lane count 1
[22:26:40] [PASSED] Link rate 162000 lane count 4
[22:26:40] [PASSED] Link rate 162000 lane count 2
[22:26:40] [PASSED] Link rate 162000 lane count 1
[22:26:40] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[22:26:40] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[22:26:40] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[22:26:40] [PASSED] DP_POWER_UP_PHY with port number
[22:26:40] [PASSED] DP_POWER_DOWN_PHY with port number
[22:26:40] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[22:26:40] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[22:26:40] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[22:26:40] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[22:26:40] [PASSED] DP_QUERY_PAYLOAD with port number
[22:26:40] [PASSED] DP_QUERY_PAYLOAD with VCPI
[22:26:40] [PASSED] DP_REMOTE_DPCD_READ with port number
[22:26:40] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[22:26:40] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[22:26:40] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[22:26:40] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[22:26:40] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[22:26:40] [PASSED] DP_REMOTE_I2C_READ with port number
[22:26:40] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[22:26:40] [PASSED] DP_REMOTE_I2C_READ with transactions array
[22:26:40] [PASSED] DP_REMOTE_I2C_WRITE with port number
[22:26:40] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[22:26:40] [PASSED] DP_REMOTE_I2C_WRITE with data array
[22:26:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[22:26:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[22:26:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[22:26:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[22:26:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[22:26:40] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[22:26:40] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[22:26:40] ================ [PASSED] drm_dp_mst_helper ================
[22:26:40] ================== drm_exec (7 subtests) ===================
[22:26:40] [PASSED] sanitycheck
[22:26:40] [PASSED] test_lock
[22:26:40] [PASSED] test_lock_unlock
[22:26:40] [PASSED] test_duplicates
[22:26:40] [PASSED] test_prepare
[22:26:40] [PASSED] test_prepare_array
[22:26:40] [PASSED] test_multiple_loops
[22:26:40] ==================== [PASSED] drm_exec =====================
[22:26:40] =========== drm_format_helper_test (17 subtests) ===========
[22:26:40] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[22:26:40] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[22:26:40] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[22:26:40] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[22:26:40] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[22:26:40] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[22:26:40] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[22:26:40] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[22:26:40] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[22:26:40] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[22:26:40] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[22:26:40] ============== drm_test_fb_xrgb8888_to_mono  ===============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[22:26:40] ==================== drm_test_fb_swab  =====================
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ================ [PASSED] drm_test_fb_swab =================
[22:26:40] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[22:26:40] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[22:26:40] [PASSED] single_pixel_source_buffer
[22:26:40] [PASSED] single_pixel_clip_rectangle
[22:26:40] [PASSED] well_known_colors
[22:26:40] [PASSED] destination_pitch
[22:26:40] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[22:26:40] ================= drm_test_fb_clip_offset  =================
[22:26:40] [PASSED] pass through
[22:26:40] [PASSED] horizontal offset
[22:26:40] [PASSED] vertical offset
[22:26:40] [PASSED] horizontal and vertical offset
[22:26:40] [PASSED] horizontal offset (custom pitch)
[22:26:40] [PASSED] vertical offset (custom pitch)
[22:26:40] [PASSED] horizontal and vertical offset (custom pitch)
[22:26:40] ============= [PASSED] drm_test_fb_clip_offset =============
[22:26:40] =================== drm_test_fb_memcpy  ====================
[22:26:40] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[22:26:40] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[22:26:40] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[22:26:40] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[22:26:40] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[22:26:40] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[22:26:40] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[22:26:40] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[22:26:40] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[22:26:40] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[22:26:40] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[22:26:40] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[22:26:40] =============== [PASSED] drm_test_fb_memcpy ================
[22:26:40] ============= [PASSED] drm_format_helper_test ==============
[22:26:40] ================= drm_format (18 subtests) =================
[22:26:40] [PASSED] drm_test_format_block_width_invalid
[22:26:40] [PASSED] drm_test_format_block_width_one_plane
[22:26:40] [PASSED] drm_test_format_block_width_two_plane
[22:26:40] [PASSED] drm_test_format_block_width_three_plane
[22:26:40] [PASSED] drm_test_format_block_width_tiled
[22:26:40] [PASSED] drm_test_format_block_height_invalid
[22:26:40] [PASSED] drm_test_format_block_height_one_plane
[22:26:40] [PASSED] drm_test_format_block_height_two_plane
[22:26:40] [PASSED] drm_test_format_block_height_three_plane
[22:26:40] [PASSED] drm_test_format_block_height_tiled
[22:26:40] [PASSED] drm_test_format_min_pitch_invalid
[22:26:40] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[22:26:40] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[22:26:40] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[22:26:40] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[22:26:40] [PASSED] drm_test_format_min_pitch_two_plane
[22:26:40] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[22:26:40] [PASSED] drm_test_format_min_pitch_tiled
[22:26:40] =================== [PASSED] drm_format ====================
[22:26:40] ============== drm_framebuffer (10 subtests) ===============
[22:26:40] ========== drm_test_framebuffer_check_src_coords  ==========
[22:26:40] [PASSED] Success: source fits into fb
[22:26:40] [PASSED] Fail: overflowing fb with x-axis coordinate
[22:26:40] [PASSED] Fail: overflowing fb with y-axis coordinate
[22:26:40] [PASSED] Fail: overflowing fb with source width
[22:26:40] [PASSED] Fail: overflowing fb with source height
[22:26:40] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[22:26:40] [PASSED] drm_test_framebuffer_cleanup
[22:26:40] =============== drm_test_framebuffer_create  ===============
[22:26:40] [PASSED] ABGR8888 normal sizes
[22:26:40] [PASSED] ABGR8888 max sizes
[22:26:40] [PASSED] ABGR8888 pitch greater than min required
[22:26:40] [PASSED] ABGR8888 pitch less than min required
[22:26:40] [PASSED] ABGR8888 Invalid width
[22:26:40] [PASSED] ABGR8888 Invalid buffer handle
[22:26:40] [PASSED] No pixel format
[22:26:40] [PASSED] ABGR8888 Width 0
[22:26:40] [PASSED] ABGR8888 Height 0
[22:26:40] [PASSED] ABGR8888 Out of bound height * pitch combination
[22:26:40] [PASSED] ABGR8888 Large buffer offset
[22:26:40] [PASSED] ABGR8888 Buffer offset for inexistent plane
[22:26:40] [PASSED] ABGR8888 Invalid flag
[22:26:40] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[22:26:40] [PASSED] ABGR8888 Valid buffer modifier
[22:26:40] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[22:26:40] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] NV12 Normal sizes
[22:26:40] [PASSED] NV12 Max sizes
[22:26:40] [PASSED] NV12 Invalid pitch
[22:26:40] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[22:26:40] [PASSED] NV12 different  modifier per-plane
[22:26:40] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[22:26:40] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] NV12 Modifier for inexistent plane
[22:26:40] [PASSED] NV12 Handle for inexistent plane
[22:26:40] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[22:26:40] [PASSED] YVU420 Normal sizes
[22:26:40] [PASSED] YVU420 Max sizes
[22:26:40] [PASSED] YVU420 Invalid pitch
[22:26:40] [PASSED] YVU420 Different pitches
[22:26:40] [PASSED] YVU420 Different buffer offsets/pitches
[22:26:40] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[22:26:40] [PASSED] YVU420 Valid modifier
[22:26:40] [PASSED] YVU420 Different modifiers per plane
[22:26:40] [PASSED] YVU420 Modifier for inexistent plane
[22:26:40] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[22:26:40] [PASSED] X0L2 Normal sizes
[22:26:40] [PASSED] X0L2 Max sizes
[22:26:40] [PASSED] X0L2 Invalid pitch
[22:26:40] [PASSED] X0L2 Pitch greater than minimum required
[22:26:40] [PASSED] X0L2 Handle for inexistent plane
[22:26:40] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[22:26:40] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[22:26:40] [PASSED] X0L2 Valid modifier
[22:26:40] [PASSED] X0L2 Modifier for inexistent plane
[22:26:40] =========== [PASSED] drm_test_framebuffer_create ===========
[22:26:40] [PASSED] drm_test_framebuffer_free
[22:26:40] [PASSED] drm_test_framebuffer_init
[22:26:40] [PASSED] drm_test_framebuffer_init_bad_format
[22:26:40] [PASSED] drm_test_framebuffer_init_dev_mismatch
[22:26:40] [PASSED] drm_test_framebuffer_lookup
[22:26:40] [PASSED] drm_test_framebuffer_lookup_inexistent
[22:26:40] [PASSED] drm_test_framebuffer_modifiers_not_supported
[22:26:40] ================= [PASSED] drm_framebuffer =================
[22:26:40] ================ drm_gem_shmem (8 subtests) ================
[22:26:40] [PASSED] drm_gem_shmem_test_obj_create
[22:26:40] [PASSED] drm_gem_shmem_test_obj_create_private
[22:26:40] [PASSED] drm_gem_shmem_test_pin_pages
[22:26:40] [PASSED] drm_gem_shmem_test_vmap
[22:26:40] [PASSED] drm_gem_shmem_test_get_pages_sgt
[22:26:40] [PASSED] drm_gem_shmem_test_get_sg_table
[22:26:40] [PASSED] drm_gem_shmem_test_madvise
[22:26:40] [PASSED] drm_gem_shmem_test_purge
[22:26:40] ================== [PASSED] drm_gem_shmem ==================
[22:26:40] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[22:26:40] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[22:26:40] [PASSED] Automatic
[22:26:40] [PASSED] Full
[22:26:40] [PASSED] Limited 16:235
[22:26:40] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[22:26:40] [PASSED] drm_test_check_disable_connector
[22:26:40] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[22:26:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[22:26:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[22:26:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[22:26:40] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[22:26:40] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[22:26:40] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[22:26:40] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[22:26:40] [PASSED] drm_test_check_output_bpc_dvi
[22:26:40] [PASSED] drm_test_check_output_bpc_format_vic_1
[22:26:40] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[22:26:40] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[22:26:40] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[22:26:40] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[22:26:40] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[22:26:40] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[22:26:40] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[22:26:40] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[22:26:40] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[22:26:40] [PASSED] drm_test_check_broadcast_rgb_value
[22:26:40] [PASSED] drm_test_check_bpc_8_value
[22:26:40] [PASSED] drm_test_check_bpc_10_value
[22:26:40] [PASSED] drm_test_check_bpc_12_value
[22:26:40] [PASSED] drm_test_check_format_value
[22:26:40] [PASSED] drm_test_check_tmds_char_value
[22:26:40] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[22:26:40] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[22:26:40] [PASSED] drm_test_check_mode_valid
[22:26:40] [PASSED] drm_test_check_mode_valid_reject
[22:26:40] [PASSED] drm_test_check_mode_valid_reject_rate
[22:26:40] [PASSED] drm_test_check_mode_valid_reject_max_clock
[22:26:40] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[22:26:40] ================= drm_managed (2 subtests) =================
[22:26:40] [PASSED] drm_test_managed_release_action
[22:26:40] [PASSED] drm_test_managed_run_action
[22:26:40] =================== [PASSED] drm_managed ===================
[22:26:40] =================== drm_mm (6 subtests) ====================
[22:26:40] [PASSED] drm_test_mm_init
[22:26:40] [PASSED] drm_test_mm_debug
[22:26:40] [PASSED] drm_test_mm_align32
[22:26:40] [PASSED] drm_test_mm_align64
[22:26:40] [PASSED] drm_test_mm_lowest
[22:26:40] [PASSED] drm_test_mm_highest
[22:26:40] ===================== [PASSED] drm_mm ======================
[22:26:40] ============= drm_modes_analog_tv (5 subtests) =============
[22:26:40] [PASSED] drm_test_modes_analog_tv_mono_576i
[22:26:40] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[22:26:40] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[22:26:40] [PASSED] drm_test_modes_analog_tv_pal_576i
[22:26:40] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[22:26:40] =============== [PASSED] drm_modes_analog_tv ===============
[22:26:40] ============== drm_plane_helper (2 subtests) ===============
[22:26:40] =============== drm_test_check_plane_state  ================
[22:26:40] [PASSED] clipping_simple
[22:26:40] [PASSED] clipping_rotate_reflect
[22:26:40] [PASSED] positioning_simple
[22:26:40] [PASSED] upscaling
[22:26:40] [PASSED] downscaling
[22:26:40] [PASSED] rounding1
[22:26:40] [PASSED] rounding2
[22:26:40] [PASSED] rounding3
[22:26:40] [PASSED] rounding4
[22:26:40] =========== [PASSED] drm_test_check_plane_state ============
[22:26:40] =========== drm_test_check_invalid_plane_state  ============
[22:26:40] [PASSED] positioning_invalid
[22:26:40] [PASSED] upscaling_invalid
[22:26:40] [PASSED] downscaling_invalid
[22:26:40] ======= [PASSED] drm_test_check_invalid_plane_state ========
[22:26:40] ================ [PASSED] drm_plane_helper =================
[22:26:40] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[22:26:40] ====== drm_test_connector_helper_tv_get_modes_check  =======
[22:26:40] [PASSED] None
[22:26:40] [PASSED] PAL
[22:26:40] [PASSED] NTSC
[22:26:40] [PASSED] Both, NTSC Default
[22:26:40] [PASSED] Both, PAL Default
[22:26:40] [PASSED] Both, NTSC Default, with PAL on command-line
[22:26:40] [PASSED] Both, PAL Default, with NTSC on command-line
[22:26:40] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[22:26:40] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[22:26:40] ================== drm_rect (9 subtests) ===================
[22:26:40] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[22:26:40] [PASSED] drm_test_rect_clip_scaled_not_clipped
[22:26:40] [PASSED] drm_test_rect_clip_scaled_clipped
[22:26:40] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[22:26:40] ================= drm_test_rect_intersect  =================
[22:26:40] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[22:26:40] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[22:26:40] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[22:26:40] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[22:26:40] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[22:26:40] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[22:26:40] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[22:26:40] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[22:26:40] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[22:26:40] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[22:26:40] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[22:26:40] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[22:26:40] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[22:26:40] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[22:26:40] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[22:26:40] ============= [PASSED] drm_test_rect_intersect =============
[22:26:40] ================ drm_test_rect_calc_hscale  ================
[22:26:40] [PASSED] normal use
[22:26:40] [PASSED] out of max range
[22:26:40] [PASSED] out of min range
[22:26:40] [PASSED] zero dst
[22:26:40] [PASSED] negative src
[22:26:40] [PASSED] negative dst
[22:26:40] ============ [PASSED] drm_test_rect_calc_hscale ============
[22:26:40] ================ drm_test_rect_calc_vscale  ================
[22:26:40] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[22:26:40] [PASSED] out of max range
[22:26:40] [PASSED] out of min range
[22:26:40] [PASSED] zero dst
[22:26:40] [PASSED] negative src
[22:26:40] [PASSED] negative dst
[22:26:40] ============ [PASSED] drm_test_rect_calc_vscale ============
[22:26:40] ================== drm_test_rect_rotate  ===================
[22:26:40] [PASSED] reflect-x
[22:26:40] [PASSED] reflect-y
[22:26:40] [PASSED] rotate-0
[22:26:40] [PASSED] rotate-90
[22:26:40] [PASSED] rotate-180
[22:26:40] [PASSED] rotate-270
[22:26:40] ============== [PASSED] drm_test_rect_rotate ===============
[22:26:40] ================ drm_test_rect_rotate_inv  =================
[22:26:40] [PASSED] reflect-x
[22:26:40] [PASSED] reflect-y
[22:26:40] [PASSED] rotate-0
[22:26:40] [PASSED] rotate-90
[22:26:40] [PASSED] rotate-180
[22:26:40] [PASSED] rotate-270
[22:26:40] ============ [PASSED] drm_test_rect_rotate_inv =============
[22:26:40] ==================== [PASSED] drm_rect =====================
[22:26:40] ============ drm_sysfb_modeset_test (1 subtest) ============
[22:26:40] ============ drm_test_sysfb_build_fourcc_list  =============
[22:26:40] [PASSED] no native formats
[22:26:40] [PASSED] XRGB8888 as native format
[22:26:40] [PASSED] remove duplicates
[22:26:40] [PASSED] convert alpha formats
[22:26:40] [PASSED] random formats
[22:26:40] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[22:26:40] ============= [PASSED] drm_sysfb_modeset_test ==============
[22:26:40] ============================================================
[22:26:40] Testing complete. Ran 622 tests: passed: 622
[22:26:40] Elapsed time: 27.430s total, 1.700s configuring, 25.310s building, 0.389s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[22:26:40] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[22:26:42] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[22:26:52] Starting KUnit Kernel (1/1)...
[22:26:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[22:26:52] ================= ttm_device (5 subtests) ==================
[22:26:52] [PASSED] ttm_device_init_basic
[22:26:52] [PASSED] ttm_device_init_multiple
[22:26:52] [PASSED] ttm_device_fini_basic
[22:26:52] [PASSED] ttm_device_init_no_vma_man
[22:26:52] ================== ttm_device_init_pools  ==================
[22:26:52] [PASSED] No DMA allocations, no DMA32 required
[22:26:52] [PASSED] DMA allocations, DMA32 required
[22:26:52] [PASSED] No DMA allocations, DMA32 required
[22:26:52] [PASSED] DMA allocations, no DMA32 required
[22:26:52] ============== [PASSED] ttm_device_init_pools ==============
[22:26:52] =================== [PASSED] ttm_device ====================
[22:26:52] ================== ttm_pool (8 subtests) ===================
[22:26:52] ================== ttm_pool_alloc_basic  ===================
[22:26:52] [PASSED] One page
[22:26:52] [PASSED] More than one page
[22:26:52] [PASSED] Above the allocation limit
[22:26:52] [PASSED] One page, with coherent DMA mappings enabled
[22:26:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:26:52] ============== [PASSED] ttm_pool_alloc_basic ===============
[22:26:52] ============== ttm_pool_alloc_basic_dma_addr  ==============
[22:26:52] [PASSED] One page
[22:26:52] [PASSED] More than one page
[22:26:52] [PASSED] Above the allocation limit
[22:26:52] [PASSED] One page, with coherent DMA mappings enabled
[22:26:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[22:26:52] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[22:26:52] [PASSED] ttm_pool_alloc_order_caching_match
[22:26:52] [PASSED] ttm_pool_alloc_caching_mismatch
[22:26:52] [PASSED] ttm_pool_alloc_order_mismatch
[22:26:52] [PASSED] ttm_pool_free_dma_alloc
[22:26:52] [PASSED] ttm_pool_free_no_dma_alloc
[22:26:52] [PASSED] ttm_pool_fini_basic
[22:26:52] ==================== [PASSED] ttm_pool =====================
[22:26:52] ================ ttm_resource (8 subtests) =================
[22:26:52] ================= ttm_resource_init_basic  =================
[22:26:52] [PASSED] Init resource in TTM_PL_SYSTEM
[22:26:52] [PASSED] Init resource in TTM_PL_VRAM
[22:26:52] [PASSED] Init resource in a private placement
[22:26:52] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[22:26:52] ============= [PASSED] ttm_resource_init_basic =============
[22:26:52] [PASSED] ttm_resource_init_pinned
[22:26:52] [PASSED] ttm_resource_fini_basic
[22:26:52] [PASSED] ttm_resource_manager_init_basic
[22:26:52] [PASSED] ttm_resource_manager_usage_basic
[22:26:52] [PASSED] ttm_resource_manager_set_used_basic
[22:26:52] [PASSED] ttm_sys_man_alloc_basic
[22:26:52] [PASSED] ttm_sys_man_free_basic
[22:26:52] ================== [PASSED] ttm_resource ===================
[22:26:52] =================== ttm_tt (15 subtests) ===================
[22:26:52] ==================== ttm_tt_init_basic  ====================
[22:26:52] [PASSED] Page-aligned size
[22:26:52] [PASSED] Extra pages requested
[22:26:52] ================ [PASSED] ttm_tt_init_basic ================
[22:26:52] [PASSED] ttm_tt_init_misaligned
[22:26:52] [PASSED] ttm_tt_fini_basic
[22:26:52] [PASSED] ttm_tt_fini_sg
[22:26:52] [PASSED] ttm_tt_fini_shmem
[22:26:52] [PASSED] ttm_tt_create_basic
[22:26:52] [PASSED] ttm_tt_create_invalid_bo_type
[22:26:52] [PASSED] ttm_tt_create_ttm_exists
[22:26:52] [PASSED] ttm_tt_create_failed
[22:26:52] [PASSED] ttm_tt_destroy_basic
[22:26:52] [PASSED] ttm_tt_populate_null_ttm
[22:26:52] [PASSED] ttm_tt_populate_populated_ttm
[22:26:52] [PASSED] ttm_tt_unpopulate_basic
[22:26:52] [PASSED] ttm_tt_unpopulate_empty_ttm
[22:26:52] [PASSED] ttm_tt_swapin_basic
[22:26:52] ===================== [PASSED] ttm_tt ======================
[22:26:52] =================== ttm_bo (14 subtests) ===================
[22:26:52] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[22:26:52] [PASSED] Cannot be interrupted and sleeps
[22:26:52] [PASSED] Cannot be interrupted, locks straight away
[22:26:52] [PASSED] Can be interrupted, sleeps
[22:26:52] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[22:26:52] [PASSED] ttm_bo_reserve_locked_no_sleep
[22:26:52] [PASSED] ttm_bo_reserve_no_wait_ticket
[22:26:52] [PASSED] ttm_bo_reserve_double_resv
[22:26:52] [PASSED] ttm_bo_reserve_interrupted
[22:26:52] [PASSED] ttm_bo_reserve_deadlock
[22:26:52] [PASSED] ttm_bo_unreserve_basic
[22:26:52] [PASSED] ttm_bo_unreserve_pinned
[22:26:52] [PASSED] ttm_bo_unreserve_bulk
[22:26:52] [PASSED] ttm_bo_fini_basic
[22:26:52] [PASSED] ttm_bo_fini_shared_resv
[22:26:52] [PASSED] ttm_bo_pin_basic
[22:26:52] [PASSED] ttm_bo_pin_unpin_resource
[22:26:52] [PASSED] ttm_bo_multiple_pin_one_unpin
[22:26:52] ===================== [PASSED] ttm_bo ======================
[22:26:52] ============== ttm_bo_validate (21 subtests) ===============
[22:26:52] ============== ttm_bo_init_reserved_sys_man  ===============
[22:26:52] [PASSED] Buffer object for userspace
[22:26:52] [PASSED] Kernel buffer object
[22:26:52] [PASSED] Shared buffer object
[22:26:52] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[22:26:52] ============== ttm_bo_init_reserved_mock_man  ==============
[22:26:52] [PASSED] Buffer object for userspace
[22:26:52] [PASSED] Kernel buffer object
[22:26:52] [PASSED] Shared buffer object
[22:26:52] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[22:26:52] [PASSED] ttm_bo_init_reserved_resv
[22:26:52] ================== ttm_bo_validate_basic  ==================
[22:26:52] [PASSED] Buffer object for userspace
[22:26:52] [PASSED] Kernel buffer object
[22:26:52] [PASSED] Shared buffer object
[22:26:52] ============== [PASSED] ttm_bo_validate_basic ==============
[22:26:52] [PASSED] ttm_bo_validate_invalid_placement
[22:26:52] ============= ttm_bo_validate_same_placement  ==============
[22:26:52] [PASSED] System manager
[22:26:52] [PASSED] VRAM manager
[22:26:52] ========= [PASSED] ttm_bo_validate_same_placement ==========
[22:26:52] [PASSED] ttm_bo_validate_failed_alloc
[22:26:52] [PASSED] ttm_bo_validate_pinned
[22:26:52] [PASSED] ttm_bo_validate_busy_placement
[22:26:52] ================ ttm_bo_validate_multihop  =================
[22:26:52] [PASSED] Buffer object for userspace
[22:26:52] [PASSED] Kernel buffer object
[22:26:52] [PASSED] Shared buffer object
[22:26:52] ============ [PASSED] ttm_bo_validate_multihop =============
[22:26:52] ========== ttm_bo_validate_no_placement_signaled  ==========
[22:26:52] [PASSED] Buffer object in system domain, no page vector
[22:26:52] [PASSED] Buffer object in system domain with an existing page vector
[22:26:52] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[22:26:52] ======== ttm_bo_validate_no_placement_not_signaled  ========
[22:26:52] [PASSED] Buffer object for userspace
[22:26:52] [PASSED] Kernel buffer object
[22:26:52] [PASSED] Shared buffer object
[22:26:52] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[22:26:52] [PASSED] ttm_bo_validate_move_fence_signaled
[22:26:52] ========= ttm_bo_validate_move_fence_not_signaled  =========
[22:26:52] [PASSED] Waits for GPU
[22:26:52] [PASSED] Tries to lock straight away
[22:26:52] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[22:26:52] [PASSED] ttm_bo_validate_happy_evict
[22:26:52] [PASSED] ttm_bo_validate_all_pinned_evict
[22:26:52] [PASSED] ttm_bo_validate_allowed_only_evict
[22:26:52] [PASSED] ttm_bo_validate_deleted_evict
[22:26:52] [PASSED] ttm_bo_validate_busy_domain_evict
[22:26:52] [PASSED] ttm_bo_validate_evict_gutting
[22:26:52] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[22:26:52] ================= [PASSED] ttm_bo_validate =================
[22:26:52] ============================================================
[22:26:52] Testing complete. Ran 101 tests: passed: 101
[22:26:52] Elapsed time: 11.337s total, 1.685s configuring, 9.436s building, 0.181s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/xe: Add System Controller support for Xe3p dGPU platforms

[Patchwork]

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== Series Details ==

Series: drm/xe: Add System Controller support for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/157937/
State : success

== Summary ==

CI Bug Log - changes from xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77_BAT -> xe-pw-157937v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77 -> xe-pw-157937v1

  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77: ed157ca0caebebe3af6d38ca0fb64a403c84ce77
  xe-pw-157937v1: 157937v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/index.html

[-- Attachment #2: Type: text/html, Size: 1523 bytes --]

✗ Xe.CI.Full: failure for drm/xe: Add System Controller support for Xe3p dGPU platforms

[Patchwork]

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== Series Details ==

Series: drm/xe: Add System Controller support for Xe3p dGPU platforms
URL   : https://patchwork.freedesktop.org/series/157937/
State : failure

== Summary ==

CI Bug Log - changes from xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77_FULL -> xe-pw-157937v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-157937v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-157937v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-157937v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3:
    - shard-bmg:          NOTRUN -> [ABORT][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-2/igt@kms_async_flips@async-flip-suspend-resume@pipe-b-hdmi-a-3.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-edp-1-x:
    - shard-lnl:          NOTRUN -> [FAIL][2] +6 other tests fail
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-tiled@pipe-b-edp-1-x.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][3] -> [ABORT][4] +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-dg2-463/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-dg2-433/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-6.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-adlp:         NOTRUN -> [ABORT][5] +3 other tests abort
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_vblank@ts-continuation-suspend.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-dp-4:
    - shard-dg2-set2:     NOTRUN -> [ABORT][6]
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-dg2-466/igt@kms_vblank@ts-continuation-suspend@pipe-a-dp-4.html

  * igt@xe_pm@s2idle-multiple-execs:
    - shard-lnl:          [PASS][7] -> [ABORT][8]
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-3/igt@xe_pm@s2idle-multiple-execs.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-3/igt@xe_pm@s2idle-multiple-execs.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         [PASS][9] -> [ABORT][10] +5 other tests abort
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-adlp-8/igt@xe_pm@s4-basic.html
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-8/igt@xe_pm@s4-basic.html

  * igt@xe_pm@s4-basic-exec:
    - shard-bmg:          [PASS][11] -> [ABORT][12]
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-2/igt@xe_pm@s4-basic-exec.html
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-7/igt@xe_pm@s4-basic-exec.html

  * igt@xe_pxp@pxp-stale-bo-bind-post-suspend:
    - shard-lnl:          NOTRUN -> [ABORT][13] +1 other test abort
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@xe_pxp@pxp-stale-bo-bind-post-suspend.html

  
Known issues
------------

  Here are the changes found in xe-pw-157937v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-read:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#1125] / [Intel XE#5574])
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-lnl:          NOTRUN -> [SKIP][15] ([Intel XE#3157])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
    - shard-lnl:          [PASS][16] -> [FAIL][17] ([Intel XE#6054])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][18] ([Intel XE#610])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-adlp:         NOTRUN -> [SKIP][19] ([Intel XE#1124]) +5 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][20] ([Intel XE#1407]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-180:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][21] ([Intel XE#4543]) +2 other tests dmesg-fail
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][22] ([Intel XE#316]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#1124]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_bw@linear-tiling-1-displays-2160x1440p:
    - shard-adlp:         NOTRUN -> [SKIP][24] ([Intel XE#367])
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_bw@linear-tiling-1-displays-2160x1440p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#367])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-7/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][27] ([Intel XE#2887]) +6 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][28] ([Intel XE#787]) +11 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][29] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#2669]) +3 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs:
    - shard-dg2-set2:     [PASS][31] -> [INCOMPLETE][32] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4:
    - shard-dg2-set2:     [PASS][33] -> [INCOMPLETE][34] ([Intel XE#6168])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6:
    - shard-dg2-set2:     [PASS][35] -> [DMESG-WARN][36] ([Intel XE#1727] / [Intel XE#3113])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-6.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#306]) +2 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#373]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#373]) +1 other test skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_chamelium_hpd@dp-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#307])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_cursor_crc@cursor-onscreen-64x21:
    - shard-lnl:          NOTRUN -> [SKIP][41] ([Intel XE#1424])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_cursor_crc@cursor-onscreen-64x21.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#2321])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-lnl:          NOTRUN -> [SKIP][43] ([Intel XE#309]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [PASS][44] -> [SKIP][45] ([Intel XE#4302])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-7/igt@kms_display_modes@extended-mode-basic.html
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-2/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats:
    - shard-adlp:         NOTRUN -> [SKIP][46] ([Intel XE#4422])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-different-formats.html

  * igt@kms_feature_discovery@display-4x:
    - shard-adlp:         NOTRUN -> [SKIP][47] ([Intel XE#1138])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-lnl:          NOTRUN -> [SKIP][48] ([Intel XE#1137])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-adlp:         NOTRUN -> [SKIP][49] ([Intel XE#310]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-lnl:          NOTRUN -> [SKIP][50] ([Intel XE#1421]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-plain-flip:
    - shard-bmg:          [PASS][51] -> [SKIP][52] ([Intel XE#2316]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-7/igt@kms_flip@2x-plain-flip.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#1401]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][54] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][55] ([Intel XE#651]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#656]) +15 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][57] ([Intel XE#656]) +9 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw:
    - shard-lnl:          NOTRUN -> [SKIP][58] ([Intel XE#651]) +5 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_frontbuffer_tracking@fbcdrrs-slowdraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][59] ([Intel XE#653]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][60] ([Intel XE#6312]) +2 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_hdr@static-swap:
    - shard-adlp:         NOTRUN -> [SKIP][61] ([Intel XE#455]) +1 other test skip
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][62] ([Intel XE#2925] / [Intel XE#346])
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][63] ([Intel XE#2925])
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-lnl:          NOTRUN -> [SKIP][64] ([Intel XE#4596])
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-adlp:         NOTRUN -> [SKIP][65] ([Intel XE#5020])
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b:
    - shard-lnl:          NOTRUN -> [SKIP][66] ([Intel XE#2763]) +1 other test skip
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-b.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-adlp:         NOTRUN -> [SKIP][67] ([Intel XE#870])
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-lnl:          NOTRUN -> [FAIL][68] ([Intel XE#718])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1439] / [Intel XE#3141])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
    - shard-adlp:         NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][71] ([Intel XE#1128] / [Intel XE#1406])
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1406])
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@psr-basic:
    - shard-adlp:         NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +6 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@kms_psr@psr-basic.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-lnl:          NOTRUN -> [SKIP][74] ([Intel XE#3414] / [Intel XE#3904])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-x-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [FAIL][75] ([Intel XE#4689])
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_rotation_crc@primary-x-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-adlp:         NOTRUN -> [SKIP][76] ([Intel XE#3414])
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-lnl:          NOTRUN -> [SKIP][77] ([Intel XE#1435])
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#362])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@xe_eu_stall@blocking-re-enable:
    - shard-adlp:         NOTRUN -> [SKIP][79] ([Intel XE#5626]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_eu_stall@blocking-re-enable.html

  * igt@xe_eudebug@basic-read-event:
    - shard-adlp:         NOTRUN -> [SKIP][80] ([Intel XE#4837] / [Intel XE#5565]) +6 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@xe_eudebug@basic-read-event.html

  * igt@xe_eudebug_online@single-step-one:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#4837]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@xe_eudebug_online@single-step-one.html

  * igt@xe_evict@evict-beng-large-external-cm:
    - shard-adlp:         NOTRUN -> [SKIP][82] ([Intel XE#261] / [Intel XE#5564]) +2 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@xe_evict@evict-beng-large-external-cm.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-adlp:         NOTRUN -> [SKIP][83] ([Intel XE#261])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_evict@evict-large-external:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#688]) +3 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@xe_evict@evict-large-external.html

  * igt@xe_exec_basic@multigpu-once-basic-defer-mmap:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1392]) +2 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@xe_exec_basic@multigpu-once-basic-defer-mmap.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][86] ([Intel XE#1392] / [Intel XE#5575]) +5 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm:
    - shard-adlp:         NOTRUN -> [SKIP][87] ([Intel XE#288] / [Intel XE#5561]) +8 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@xe_exec_fault_mode@many-execqueues-bindexecqueue-userptr-invalidate-race-imm.html

  * igt@xe_exec_system_allocator@many-large-execqueues-mmap-huge-nomemset:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#4943]) +7 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@xe_exec_system_allocator@many-large-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-single-vma:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#6196])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-wt-single-vma.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free:
    - shard-adlp:         NOTRUN -> [SKIP][90] ([Intel XE#4915]) +99 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@xe_exec_system_allocator@process-many-execqueues-free.html

  * igt@xe_exec_threads@threads-rebind:
    - shard-adlp:         [PASS][91] -> [ABORT][92] ([Intel XE#3970])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-adlp-4/igt@xe_exec_threads@threads-rebind.html
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-9/igt@xe_exec_threads@threads-rebind.html

  * igt@xe_mmap@pci-membarrier-bad-pagesize:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#5100])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@xe_mmap@pci-membarrier-bad-pagesize.html

  * igt@xe_oa@mmio-triggered-reports:
    - shard-adlp:         NOTRUN -> [SKIP][94] ([Intel XE#3573]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_oa@mmio-triggered-reports.html

  * igt@xe_pm@d3cold-basic-exec:
    - shard-adlp:         NOTRUN -> [SKIP][95] ([Intel XE#2284] / [Intel XE#366])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_pm@d3cold-basic-exec.html

  * igt@xe_pmu@engine-activity-accuracy-50:
    - shard-lnl:          [PASS][96] -> [FAIL][97] ([Intel XE#6251]) +2 other tests fail
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-3/igt@xe_pmu@engine-activity-accuracy-50.html
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-1/igt@xe_pmu@engine-activity-accuracy-50.html

  * igt@xe_pmu@engine-activity-most-load@engine-drm_xe_engine_class_video_decode1:
    - shard-adlp:         NOTRUN -> [FAIL][98] ([Intel XE#6458])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_pmu@engine-activity-most-load@engine-drm_xe_engine_class_video_decode1.html

  * igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
    - shard-adlp:         NOTRUN -> [SKIP][99] ([Intel XE#4733] / [Intel XE#5594])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html

  * igt@xe_query@multigpu-query-cs-cycles:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#944])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-3/igt@xe_query@multigpu-query-cs-cycles.html

  * igt@xe_spin_batch@spin-mem-copy:
    - shard-adlp:         NOTRUN -> [SKIP][101] ([Intel XE#4821])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_spin_batch@spin-mem-copy.html

  * igt@xe_sriov_flr@flr-vf1-clear:
    - shard-lnl:          NOTRUN -> [SKIP][102] ([Intel XE#3342])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@xe_sriov_flr@flr-vf1-clear.html

  * igt@xe_sriov_vram@vf-access-beyond:
    - shard-lnl:          NOTRUN -> [SKIP][103] ([Intel XE#6376])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-4/igt@xe_sriov_vram@vf-access-beyond.html

  
#### Possible fixes ####

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-adlp:         [DMESG-FAIL][104] ([Intel XE#4543]) -> [PASS][105]
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][106] ([Intel XE#2291]) -> [PASS][107] +3 other tests pass
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-3/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [SKIP][108] ([Intel XE#2373]) -> [PASS][109]
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-2/igt@kms_feature_discovery@display-2x.html
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-8/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-bmg:          [SKIP][110] ([Intel XE#2316]) -> [PASS][111] +3 other tests pass
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-6/igt@kms_flip@2x-plain-flip-interruptible.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-3/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@basic-plain-flip@c-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][112] ([Intel XE#4543]) -> [PASS][113] +1 other test pass
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-adlp-3/igt@kms_flip@basic-plain-flip@c-hdmi-a1.html
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-4/igt@kms_flip@basic-plain-flip@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][114] ([Intel XE#301]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-lnl:          [ABORT][116] -> [PASS][117] +3 other tests pass
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-2/igt@kms_pm_backlight@fade-with-suspend.html
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-5/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [ABORT][118] -> [PASS][119]
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-dg2-464/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-6.html
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-dg2-466/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-6.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-c-edp-1:
    - shard-lnl:          [INCOMPLETE][120] ([Intel XE#4488]) -> [PASS][121]
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-8/igt@kms_vblank@ts-continuation-suspend@pipe-c-edp-1.html
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-7/igt@kms_vblank@ts-continuation-suspend@pipe-c-edp-1.html

  * igt@xe_exec_system_allocator@process-many-execqueues-free:
    - shard-bmg:          [FAIL][122] -> [PASS][123]
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-2/igt@xe_exec_system_allocator@process-many-execqueues-free.html
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-6/igt@xe_exec_system_allocator@process-many-execqueues-free.html

  * igt@xe_pm@s3-exec-after:
    - shard-adlp:         [ABORT][124] -> [PASS][125]
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-adlp-2/igt@xe_pm@s3-exec-after.html
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-1/igt@xe_pm@s3-exec-after.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic:
    - shard-lnl:          [FAIL][126] -> [FAIL][127] ([Intel XE#6054])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-lnl-7/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic.html

  * igt@kms_content_protection@srm:
    - shard-bmg:          [FAIL][128] ([Intel XE#1178]) -> [SKIP][129] ([Intel XE#2341])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-7/igt@kms_content_protection@srm.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-2/igt@kms_content_protection@srm.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt:
    - shard-bmg:          [SKIP][130] ([Intel XE#2312]) -> [SKIP][131] ([Intel XE#2311]) +9 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][132] ([Intel XE#2311]) -> [SKIP][133] ([Intel XE#2312]) +9 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][134] ([Intel XE#2312]) -> [SKIP][135] ([Intel XE#4141]) +4 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][136] ([Intel XE#4141]) -> [SKIP][137] ([Intel XE#2312]) +6 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][138] ([Intel XE#2313]) -> [SKIP][139] ([Intel XE#2312]) +9 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][140] ([Intel XE#2312]) -> [SKIP][141] ([Intel XE#2313]) +5 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-bmg:          [SKIP][142] ([Intel XE#4596]) -> [SKIP][143] ([Intel XE#5021])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-bmg-2/igt@kms_plane_multiple@2x-tiling-y.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@xe_exec_reset@cm-cat-error:
    - shard-adlp:         [DMESG-WARN][144] ([Intel XE#3868]) -> [DMESG-FAIL][145] ([Intel XE#3868])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77/shard-adlp-4/igt@xe_exec_reset@cm-cat-error.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/shard-adlp-9/igt@xe_exec_reset@cm-cat-error.html

  
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1137]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1137
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3342
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3868]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3868
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#3970]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3970
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
  [Intel XE#4488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4488
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4689]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4689
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4821
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5574]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5574
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#6196]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6196
  [Intel XE#6251]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6251
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#6458]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6458
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/718
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944


Build changes
-------------

  * Linux: xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77 -> xe-pw-157937v1

  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-4140-ed157ca0caebebe3af6d38ca0fb64a403c84ce77: ed157ca0caebebe3af6d38ca0fb64a403c84ce77
  xe-pw-157937v1: 157937v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-157937v1/index.html

[-- Attachment #2: Type: text/html, Size: 49329 bytes --]

Re: [RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Umesh Nerlige Ramappa]

On Fri, Nov 21, 2025 at 08:58:07PM -0800, Anoop, Vijay wrote:
>From: Anoop Vijay <anoop.c.vijay@intel.com>
>
>Add a new system controller (SC) component for Intel Xe3p dGPU platforms.
>
>This component provides the foundational infrastructure for communication
>with the SC firmware using the MKHI protocol over a mailbox interface.
>
>Key features introduced:
>- Detection and initialization of the SC interface on Xe3p dGPU platforms
>- Mailbox communication with SC firmware
>- Fragmented message transfer for large command payloads
>
>This implementation establishes the base for future SC feature
>enablement and firmware command handling.
>
>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
>---
> drivers/gpu/drm/xe/Makefile          |   2 +
> drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
> drivers/gpu/drm/xe/xe_device.c       |   5 +
> drivers/gpu/drm/xe/xe_device_types.h |   5 +
> drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
> drivers/gpu/drm/xe/xe_sc.h           |  15 ++
> drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
> drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
> 9 files changed, 635 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_sc.c
> create mode 100644 drivers/gpu/drm/xe/xe_sc.h
> create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
> create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
> create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h
>
>diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>index 7ebfbf9051bf..50e8dc86d915 100644
>--- a/drivers/gpu/drm/xe/Makefile
>+++ b/drivers/gpu/drm/xe/Makefile
>@@ -114,7 +114,9 @@ xe-y += xe_bb.o \
> 	xe_ring_ops.o \
> 	xe_rtp.o \
> 	xe_sa.o \
>+	xe_sc.o \
> 	xe_sched_job.o \
>+	xe_sc_mailbox.o \
> 	xe_shrinker.o \
> 	xe_step.o \
> 	xe_survivability_mode.o \
>diff --git a/drivers/gpu/drm/xe/regs/xe_sc_regs.h b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
>new file mode 100644
>index 000000000000..2b7053586197
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
>@@ -0,0 +1,49 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_SC_REGS_H_
>+#define _XE_SC_REGS_H_
>+
>+#include "xe_regs.h"
>+
>+#define SYSCTRL_BASE_OFFSET		0xDB000
>+#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
>+#define SYSCTRL_MAILBOX_INDEX		0x03
>+#define SC_BAR_LENGTH			0x1000
>+
>+#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
>+#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
>+#define   SC_MB_CTRL_IRQ		REG_BIT(30)
>+#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
>+#define   SC_MB_CTRL_PARAM3		REG_GENMASK(28, 24)
>+#define   SC_MB_CTRL_PARAM2		REG_GENMASK(23, 16)
>+#define   SC_MB_CTRL_PARAM1		REG_GENMASK(15, 8)
>+#define   SC_MB_CTRL_COMMAND		REG_GENMASK(7, 0)

For MASKs (the above 4 defines) , use _MASK suffix. Same applies to any 
masks below.

>+
>+#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
>+#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
>+#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
>+#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
>+
>+#define MKHI_FRAME_PHASE		REG_BIT(24)
>+#define MKHI_FRAME_CURRENT		REG_GENMASK(21, 16)
>+#define MKHI_FRAME_TOTAL		REG_GENMASK(13, 8)
>+#define MKHI_FRAME_COMMAND		REG_GENMASK(7, 0)
>+
>+#define MKHI_HDR_RESULT			REG_GENMASK(31, 24)
>+#define MKHI_HDR_IS_RESPONSE		REG_BIT(15)
>+#define MKHI_HDR_COMMAND		REG_GENMASK(14, 8)
>+#define MKHI_HDR_GROUP_ID		REG_GENMASK(7, 0)
>+
>+#define SC_MB_FRAME_SIZE		16
>+#define SC_MB_MAX_FRAMES		64
>+#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
>+#define SC_MKHI_COMMAND			5
>+
>+#define SC_MB_DEFAULT_TIMEOUT_MS	500
>+#define SC_MB_RETRY_TIMEOUT_MS		20
>+#define SC_MB_POLL_INTERVAL_US		100
>+
>+#endif /* _XE_SC_REGS_H_ */
>diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>index f15489c100af..9fbd0b084c74 100644
>--- a/drivers/gpu/drm/xe/xe_device.c
>+++ b/drivers/gpu/drm/xe/xe_device.c
>@@ -60,6 +60,7 @@
> #include "xe_psmi.h"
> #include "xe_pxp.h"
> #include "xe_query.h"
>+#include "xe_sc.h"
> #include "xe_soc_remapper.h"
> #include "xe_shrinker.h"
> #include "xe_survivability_mode.h"
>@@ -963,6 +964,10 @@ int xe_device_probe(struct xe_device *xe)
> 	if (err)
> 		goto err_unregister_display;
>
>+	err = xe_sc_init(xe);
>+	if (err)
>+		goto err_unregister_display;
>+
> 	for_each_gt(gt, xe, id)
> 		xe_gt_sanitize_freq(gt);
>
>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>index 3f118c64a124..86a0c83c802d 100644
>--- a/drivers/gpu/drm/xe/xe_device_types.h
>+++ b/drivers/gpu/drm/xe/xe_device_types.h
>@@ -314,6 +314,8 @@ struct xe_device {
> 		u8 has_range_tlb_inval:1;
> 		/** @info.has_sriov: Supports SR-IOV */
> 		u8 has_sriov:1;
>+		/** @info.has_sysctrl: Supports System Controller */
>+		u8 has_sysctrl:1;
> 		/** @info.has_usm: Device has unified shared memory support */
> 		u8 has_usm:1;
> 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
>@@ -576,6 +578,9 @@ struct xe_device {
> 	/** @heci_gsc: graphics security controller */
> 	struct xe_heci_gsc heci_gsc;
>
>+	/** @sc: System Controller */
>+	struct xe_sc *sc;

(1)

It would be simpler to just make this a non-pointer.

	struct xe_sc sc;

or struct xe_sysctrl sc (if you renamed the structs)

This way you don't need to back reference xe from sc. Most of Xe KMD 
code tries not to back reference to parent structs, unless it is 
essential.

>+
> 	/** @nvm: discrete graphics non-volatile memory */
> 	struct intel_dg_nvm_dev *nvm;
>
>diff --git a/drivers/gpu/drm/xe/xe_sc.c b/drivers/gpu/drm/xe/xe_sc.c
>new file mode 100644
>index 000000000000..18448efc173f
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc.c
>@@ -0,0 +1,89 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#include "xe_sc.h"
>+
>+#include <linux/mutex.h>
>+
>+#include <drm/drm_managed.h>
>+#include <drm/drm_print.h>
>+
>+#include "regs/xe_sc_regs.h"
>+#include "xe_device.h"
>+#include "xe_mmio.h"
>+#include "xe_platform_types.h"
>+#include "xe_soc_remapper.h"
>+#include "xe_sc_types.h"
>+#include "xe_tile.h"
>+
>+static void xe_sc_remove(struct drm_device *drm, void *arg)
>+{
>+	struct xe_sc *sc = arg;
>+	struct xe_device *xe;
>+
>+	if (!sc)
>+		return;
>+
>+	xe = to_xe_device(drm);
>+
>+	mutex_destroy(&sc->cmd_lock);
>+
>+	xe_soc_remapper_set_sysctrl_region(xe, 0);
>+
>+	xe->sc = NULL;
>+}
>+

If you made sc a non pointer (xe.sc), then it would look something like 
this:

static void xe_sc_fini(struct drm_device *drm, void *arg)
{
	struct xe_sc *sc = arg;
	struct xe_device *xe = container_of(sc, typeof(*xe), sc);

	mutex_destroy(&sc->cmd_lock);
	xe_soc_remapper_set_sysctrl_region(xe, 0);
}

static int xe_sc_probe(struct xe_device *xe)
{
	struct xe_tile *tile = xe_device_get_root_tile(xe);
	struct xe_sc *sc = &xe.sc;
	int ret;

	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
	if (ret)
		return ret;

	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, le->mmio.regs_size);
	mutex_init(&sc->cmd_lock);

	sc->phase_bit = 0;

	return 0;
}

You could merge the probe into init below and rename xe_sc_remove 
xe_sc_fini().

Also, like Michal mentioned, maybe we should rename functions, structs, 
files to xe_sysctrl. The variable can likely stay as sc. 

>+static int xe_sc_probe(struct xe_device *xe)
>+{
>+	struct xe_tile *tile = xe_device_get_root_tile(xe);
>+	struct xe_sc *sc;
>+	int ret;
>+
>+	sc = drmm_kzalloc(&xe->drm, sizeof(*sc), GFP_KERNEL);
>+	if (!sc)
>+		return -ENOMEM;
>+
>+	sc->xe = xe;
>+	xe->sc = sc;
>+
>+	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
>+	if (ret) {
>+		xe->sc = NULL;
>+		return ret;
>+	}
>+
>+	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
>+
>+	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
>+
>+	mutex_init(&sc->cmd_lock);
>+
>+	sc->phase_bit = 0;
>+
>+	return 0;
>+}
>+
>+/**
>+ * xe_sc_init - Initialize SC subsystem
>+ * @xe: xe device instance
>+ *
>+ * Entry point for SC initialization, called from xe_device_probe().
>+ * This function checks platform support and calls the main probe function.
>+ *
>+ * Return: 0 on success, error code on failure
>+ */
>+int xe_sc_init(struct xe_device *xe)
>+{
>+	int ret;
>+
>+	if (!xe->info.has_sysctrl)
>+		return 0;
>+
>+	ret = xe_sc_probe(xe);
>+	if (ret)
>+		drm_err(&xe->drm, "sysctrl: Probe failed: %d\n", ret);
>+
>+	return ret;
>+}
>diff --git a/drivers/gpu/drm/xe/xe_sc.h b/drivers/gpu/drm/xe/xe_sc.h
>new file mode 100644
>index 000000000000..0e5c89ddc957
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc.h
>@@ -0,0 +1,15 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef __XE_SC_H__
>+#define __XE_SC_H__
>+
>+#include <linux/types.h>
>+
>+struct xe_device;
>+
>+int xe_sc_init(struct xe_device *xe);
>+
>+#endif /* __XE_SC_H__ */
>diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.c b/drivers/gpu/drm/xe/xe_sc_mailbox.c
>new file mode 100644
>index 000000000000..6f2500c63a3c
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc_mailbox.c
>@@ -0,0 +1,374 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#include <linux/bitfield.h>
>+#include <linux/errno.h>
>+#include <linux/minmax.h>
>+#include <linux/mutex.h>
>+#include <linux/slab.h>
>+#include <linux/string.h>
>+#include <linux/types.h>
>+
>+#include <drm/drm_print.h>
>+
>+#include "regs/xe_sc_regs.h"
>+#include "xe_device.h"
>+#include "xe_mmio.h"
>+#include "xe_pm.h"
>+#include "xe_sc.h"
>+#include "xe_sc_mailbox.h"
>+#include "xe_sc_types.h"
>+
>+static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
>+				 unsigned int timeout_ms)
>+{
>+	int ret;
>+
>+	if (timeout_ms == 0) {
>+		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
>+					 0, NULL, false);
>+	} else {
>+		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
>+					 timeout_ms * 1000, NULL, false);
>+	}
>+
>+	return ret == 0;
>+}

The above can be simplified to: 

static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
				 unsigned int timeout_ms)
{
	int ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
				     timeout_ms * 1000, NULL, false);

	return ret == 0;
}


>+
>+static bool sc_mb_wait_bit_set(struct xe_sc *sc, u32 bit_mask,
>+			       unsigned int timeout_ms)
>+{
>+	int ret;

Same here. Can be simplified without conditions.
>+
>+	if (timeout_ms == 0) {
>+		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
>+				     0, NULL, false);
>+	} else {
>+		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
>+				     timeout_ms * 1000, NULL, false);
>+	}
>+
>+	return ret == 0;
>+}
>+
>+static void sc_mb_write_frame(struct xe_sc *sc, const void *buffer,
>+			      size_t offset)
>+{
>+	const u32 *data = (const u32 *)((const u8 *)buffer + offset);
>+
>+	xe_mmio_write32(&sc->mmio, SC_MB_DATA0, data[0]);
>+	xe_mmio_write32(&sc->mmio, SC_MB_DATA1, data[1]);
>+	xe_mmio_write32(&sc->mmio, SC_MB_DATA2, data[2]);
>+	xe_mmio_write32(&sc->mmio, SC_MB_DATA3, data[3]);
>+}
>+
>+static void sc_mb_read_frame(struct xe_sc *sc, void *buffer,
>+			     size_t offset)
>+{
>+	u32 *data = (u32 *)((u8 *)buffer + offset);
>+
>+	data[0] = xe_mmio_read32(&sc->mmio, SC_MB_DATA0);
>+	data[1] = xe_mmio_read32(&sc->mmio, SC_MB_DATA1);
>+	data[2] = xe_mmio_read32(&sc->mmio, SC_MB_DATA2);
>+	data[3] = xe_mmio_read32(&sc->mmio, SC_MB_DATA3);
>+}
>+
>+static void sc_mb_clear_response(struct xe_sc *sc)
>+{
>+	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);

Are you intending to write 0 to bit 30. This looks like it is setting it?

>+}
>+

will continue review from below tomorrow...

Regards,
Umesh
>+static int sc_mb_prepare_command(struct xe_sc *sc,
>+				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+				 const void *data_in, size_t data_in_len,
>+				 u8 **cmd_buffer, size_t *cmd_size)
>+{
>+	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
>+
>+	mkhi_hdr.group_id = msg_hdr->group_id;
>+	mkhi_hdr.command = msg_hdr->command & 0x7F;
>+	mkhi_hdr.is_response = 0;
>+	mkhi_hdr.reserved = 0;
>+	mkhi_hdr.result = 0;
>+
>+	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;
>+
>+	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
>+		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
>+			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
>+		return -EINVAL;
>+	}
>+
>+	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
>+	if (!*cmd_buffer)
>+		return -ENOMEM;
>+
>+	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));
>+	if (data_in && data_in_len)
>+		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
>+		       data_in, data_in_len);
>+
>+	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
>+		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
>+
>+	return 0;
>+}
>+
>+static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
>+			     size_t cmd_size, unsigned int timeout_ms)
>+{
>+	u32 ctrl_reg, total_frames, current_frame;
>+	size_t bytes_sent, bytes_to_send;
>+
>+	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
>+	if (total_frames > SC_MB_MAX_FRAMES) {
>+		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
>+			cmd_size, total_frames, SC_MB_MAX_FRAMES);
>+		return -EINVAL;
>+	}
>+
>+	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>+		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
>+		return -EBUSY;
>+	}
>+
>+	sc->phase_bit ^= 1;
>+
>+	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
>+		cmd_size, total_frames, sc->phase_bit);
>+
>+	bytes_sent = 0;
>+	for (current_frame = 0; current_frame < total_frames; current_frame++) {
>+		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
>+
>+		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);
>+
>+		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
>+			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
>+			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
>+			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
>+		if (sc->phase_bit)
>+			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
>+
>+		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
>+
>+		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
>+			current_frame, total_frames - 1);
>+
>+		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>+			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
>+				current_frame);
>+			return -ETIMEDOUT;
>+		}
>+
>+		bytes_sent += bytes_to_send;
>+	}
>+
>+	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
>+	return 0;
>+}
>+
>+static int sc_mb_validate_response_header(struct xe_sc *sc,
>+					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
>+{
>+	if (!resp_hdr->is_response ||
>+	    resp_hdr->group_id != msg_hdr->group_id ||
>+	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
>+		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
>+		return -EPROTO;
>+	}
>+
>+	if (resp_hdr->result != 0) {
>+		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
>+			resp_hdr->result);
>+		return -EIO;
>+	}
>+
>+	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
>+		resp_hdr->group_id, resp_hdr->command);
>+
>+	return 0;
>+}
>+
>+static int sc_mb_receive_frames(struct xe_sc *sc,
>+				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+				void *data_out, size_t data_out_len,
>+				size_t *bytes_received, unsigned int timeout_ms)
>+{
>+	u32 ctrl_reg, total_frames, current_frame;
>+	size_t payload_size;
>+	int ret;
>+
>+	*bytes_received = 0;
>+
>+	do {
>+		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
>+		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
>+		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
>+
>+		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
>+			current_frame, total_frames - 1);
>+
>+		if (current_frame == 0) {
>+			u32 temp_frame[4];
>+			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
>+
>+			sc_mb_read_frame(sc, temp_frame, 0);
>+			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
>+
>+			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
>+			if (ret)
>+				return ret;
>+
>+			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
>+			if (payload_size > data_out_len) {
>+				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
>+				return -ENOSPC;
>+			}
>+
>+			memcpy(data_out,
>+			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
>+			       payload_size);
>+			*bytes_received = payload_size;
>+		} else {
>+			size_t frame_size = SC_MB_FRAME_SIZE;
>+
>+			if (current_frame == total_frames - 1) {
>+				size_t total_response = (total_frames - 1) *
>+							SC_MB_FRAME_SIZE +
>+							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
>+				size_t remaining = total_response -
>+						   *bytes_received -
>+						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
>+				frame_size = min(frame_size, remaining);
>+			}
>+
>+			if (*bytes_received + frame_size > data_out_len) {
>+				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
>+				return -ENOSPC;
>+			}
>+
>+			sc_mb_read_frame(sc, data_out, *bytes_received);
>+			*bytes_received += frame_size;
>+		}
>+
>+		sc_mb_clear_response(sc);
>+
>+		if (current_frame + 1 < total_frames &&
>+		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
>+			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
>+				current_frame + 1);
>+			return -ETIMEDOUT;
>+		}
>+
>+	} while (current_frame + 1 < total_frames);
>+
>+	return 0;
>+}
>+
>+static int sc_mb_send_command(struct xe_sc *sc,
>+			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+			      const u8 *cmd_buffer, size_t cmd_size,
>+			      void *data_out, size_t data_out_len,
>+			      size_t *rdata_len, unsigned int timeout_ms)
>+{
>+	size_t bytes_received;
>+	int ret;
>+
>+	if (rdata_len)
>+		*rdata_len = 0;
>+
>+	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
>+	if (ret)
>+		return ret;
>+
>+	if (!data_out) {
>+		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
>+		return 0;
>+	}
>+
>+	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
>+		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
>+		return -ETIMEDOUT;
>+	}
>+
>+	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
>+				   &bytes_received, timeout_ms);
>+	if (ret) {
>+		sc_mb_clear_response(sc);
>+		return ret;
>+	}
>+
>+	if (rdata_len)
>+		*rdata_len = bytes_received;
>+
>+	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
>+		bytes_received);
>+
>+	return 0;
>+}
>+
>+/**
>+ * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
>+ * @handle: XE device handle containing the system controller
>+ * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
>+ * @rdata_len: Pointer to store actual response data size (can be NULL)
>+ *
>+ * Send a command to the System Controller using MKHI protocol. Handles
>+ * command preparation, fragmentation, transmission, and response reception.
>+ * Optimized to move memory allocation outside the critical section.
>+ *
>+ * Return: 0 on success, negative error code on failure
>+ */
>+int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
>+{
>+	struct xe_device *xe = handle;
>+	struct xe_sc *sc;
>+	struct xe_sc_mailbox_command *cmd = cmd_buffer;
>+	u8 *command_buffer = NULL;
>+	size_t command_size;
>+	int ret;
>+
>+	if (!xe || !cmd)
>+		return -EINVAL;
>+
>+	sc = xe->sc;
>+	if (!sc)
>+		return -ENODEV;
>+
>+	if (!cmd->data_in && cmd->data_in_len)
>+		return -EINVAL;
>+
>+	if (!cmd->data_out && cmd->data_out_len)
>+		return -EINVAL;
>+
>+	might_sleep();
>+
>+	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
>+				    &command_buffer, &command_size);
>+	if (ret) {
>+		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
>+		return ret;
>+	}
>+
>+	mutex_lock(&sc->cmd_lock);
>+
>+	xe_pm_runtime_get(xe);
>+
>+	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
>+				 cmd->data_out, cmd->data_out_len, rdata_len,
>+				 SC_MB_DEFAULT_TIMEOUT_MS);
>+	if (ret)
>+		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
>+
>+	xe_pm_runtime_put(xe);
>+
>+	mutex_unlock(&sc->cmd_lock);
>+
>+	kfree(command_buffer);
>+
>+	return ret;
>+}
>diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
>new file mode 100644
>index 000000000000..d5ca43c40f1a
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
>@@ -0,0 +1,61 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef __XE_SC_MAILBOX_H__
>+#define __XE_SC_MAILBOX_H__
>+
>+#include <linux/types.h>
>+
>+struct xe_sc;
>+
>+/**
>+ * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
>+ */
>+struct xe_sc_mailbox_mkhi_msg_hdr {
>+	/** @group_id: Message group identifier */
>+	u32 group_id    : 8;
>+	/** @command: Command identifier within the group */
>+	u32 command     : 7;
>+	/** @is_response: Response flag - 0 for request, 1 for response */
>+	u32 is_response : 1;
>+	/** @reserved: Reserved field, must be zero */
>+	u32 reserved    : 8;
>+	/** @result: Result code from firmware */
>+	u32 result      : 8;
>+} __packed;
>+
>+/**
>+ * struct xe_sc_mailbox_app_msg_hdr - Application message header
>+ */
>+struct xe_sc_mailbox_app_msg_hdr {
>+	/** @group_id: Application group identifier */
>+	u32 group_id  : 8;
>+	/** @command: Specific command within the application group */
>+	u32 command   : 8;
>+	/** @version: Protocol version */
>+	u32 version   : 8;
>+	/** @reserved: Reserved field, must be zero */
>+	u32 reserved  : 8;
>+} __packed;
>+
>+/**
>+ * struct xe_sc_mailbox_command - System Controller mailbox command structure
>+ */
>+struct xe_sc_mailbox_command {
>+	/** @header: Application message header containing command information */
>+	struct xe_sc_mailbox_app_msg_hdr header;
>+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
>+	void *data_in;
>+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
>+	size_t data_in_len;
>+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
>+	void *data_out;
>+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
>+	size_t data_out_len;
>+};
>+
>+int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
>+
>+#endif /* __XE_SC_MAILBOX_H__ */
>diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
>new file mode 100644
>index 000000000000..5ec2126cebe4
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc_types.h
>@@ -0,0 +1,35 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_SC_TYPES_H_
>+#define _XE_SC_TYPES_H_
>+
>+#include <linux/completion.h>
>+#include <linux/mutex.h>
>+#include <linux/types.h>
>+#include <linux/workqueue.h>
>+
>+#include "xe_device_types.h"
>+#include "xe_sc_mailbox.h"
>+
>+struct xe_device;
>+
>+/**
>+ * struct xe_sc - System Controller driver context
>+ */
>+struct xe_sc {
>+	/** @xe: Back pointer to xe_device */
>+	struct xe_device *xe;

You can drop this when you do (1) above.

>+	/** @mmio: MMIO region for SC registers */
>+	struct xe_mmio mmio;
>+
>+	/** @cmd_lock: Mutex protecting mailbox command operations */
>+	struct mutex cmd_lock;
>+
>+	/** @phase_bit: MKHI message boundary phase toggle bit */
>+	u32 phase_bit;
>+};
>+
>+#endif /* _XE_SC_TYPES_H_ */
>-- 
>2.43.0
>

Re: [RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Umesh Nerlige Ramappa]

On Fri, Nov 21, 2025 at 08:58:07PM -0800, Anoop, Vijay wrote:
>From: Anoop Vijay <anoop.c.vijay@intel.com>
>
>Add a new system controller (SC) component for Intel Xe3p dGPU platforms.
>
>This component provides the foundational infrastructure for communication
>with the SC firmware using the MKHI protocol over a mailbox interface.
>
>Key features introduced:
>- Detection and initialization of the SC interface on Xe3p dGPU platforms
>- Mailbox communication with SC firmware
>- Fragmented message transfer for large command payloads
>
>This implementation establishes the base for future SC feature
>enablement and firmware command handling.
>
>Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
>---
> drivers/gpu/drm/xe/Makefile          |   2 +
> drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
> drivers/gpu/drm/xe/xe_device.c       |   5 +
> drivers/gpu/drm/xe/xe_device_types.h |   5 +
> drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
> drivers/gpu/drm/xe/xe_sc.h           |  15 ++
> drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
> drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
> 9 files changed, 635 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_sc.c
> create mode 100644 drivers/gpu/drm/xe/xe_sc.h
> create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
> create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
> create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h
>

[snip]

>+static void sc_mb_clear_response(struct xe_sc *sc)
>+{
>+	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);
>+}
>+

... continued from previous review

>+static int sc_mb_prepare_command(struct xe_sc *sc,
>+				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+				 const void *data_in, size_t data_in_len,
>+				 u8 **cmd_buffer, size_t *cmd_size)
>+{
>+	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
>+
>+	mkhi_hdr.group_id = msg_hdr->group_id;
>+	mkhi_hdr.command = msg_hdr->command & 0x7F;
>+	mkhi_hdr.is_response = 0;
>+	mkhi_hdr.reserved = 0;
>+	mkhi_hdr.result = 0;
>+
>+	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;

I recommend using local variables for command size and command buffer 
and update the pointers passed (cmd_size and cmd_buffer) just before 
returning success from this function. That way, when you return an 
error, cmd_size and cmd_buffer are untouched.

>+	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
>+		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
>+			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
>+		return -EINVAL;
>+	}
>+
>+	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
>+	if (!*cmd_buffer)
>+		return -ENOMEM;
>+
>+	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));

why not just use a pointer for mkhi_hdr and allocate cmd_size bytes for 
it? Then you can just fill that with the mkhi header values and then 
memcpy the data_in. Finally you can assign that pointer to cmd_buffer.  
That way only one memcpy is required (for data_in). Something like:

struct xe_sc_mailbox_mkhi_msg_hdr *mkhi_hdr;
size_t size = sizeof(*mkhi_hdr) + data_in_len;

mkhi_hdr = kmalloc(size, GFP_KERNEL);
if (!mkhi_hdr)
	return -ENOMEM;

mkhi_hdr->group_id = msg_hdr->group_id;
mkhi_hdr->command = msg_hdr->command & 0x7F;
mkhi_hdr->is_response = 0;
mkhi_hdr->reserved = 0;
mkhi_hdr->result = 0;

if (data_in && data_in_len)
	memcpy(mkhi_hdr + 1, data_in, data_in_len);

*cmd_size = size;
*cmd_buffer = (u8 *)mkhi_hdr;

>+	if (data_in && data_in_len)
>+		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
>+		       data_in, data_in_len);
>+
>+	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
>+		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
>+
>+	return 0;
>+}
>+
>+static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
>+			     size_t cmd_size, unsigned int timeout_ms)
>+{
>+	u32 ctrl_reg, total_frames, current_frame;
>+	size_t bytes_sent, bytes_to_send;
>+
>+	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
>+	if (total_frames > SC_MB_MAX_FRAMES) {
>+		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
>+			cmd_size, total_frames, SC_MB_MAX_FRAMES);
>+		return -EINVAL;
>+	}
>+
>+	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>+		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
>+		return -EBUSY;
>+	}
>+
>+	sc->phase_bit ^= 1;
>+
>+	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
>+		cmd_size, total_frames, sc->phase_bit);
>+
>+	bytes_sent = 0;
>+	for (current_frame = 0; current_frame < total_frames; current_frame++) {
>+		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
>+
>+		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);

if bytes_to_send is less than 16, you are still writing 16 bytes in
sc_mb_write_frame. Wouldn't that go beyond the command buffer? Maybe you should
pass bytes_to_send to sc_mb_write_frame?

>+
>+		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
>+			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
>+			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
>+			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
>+		if (sc->phase_bit)
>+			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
>+
>+		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
>+
>+		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
>+			current_frame, total_frames - 1);
>+
>+		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
>+			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
>+				current_frame);
>+			return -ETIMEDOUT;
>+		}
>+
>+		bytes_sent += bytes_to_send;
>+	}
>+
>+	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
>+	return 0;
>+}
>+
>+static int sc_mb_validate_response_header(struct xe_sc *sc,
>+					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
>+{
>+	if (!resp_hdr->is_response ||
>+	    resp_hdr->group_id != msg_hdr->group_id ||
>+	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
>+		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
>+		return -EPROTO;
>+	}
>+
>+	if (resp_hdr->result != 0) {
>+		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
>+			resp_hdr->result);
>+		return -EIO;
>+	}
>+
>+	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
>+		resp_hdr->group_id, resp_hdr->command);
>+
>+	return 0;
>+}
>+
>+static int sc_mb_receive_frames(struct xe_sc *sc,
>+				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+				void *data_out, size_t data_out_len,
>+				size_t *bytes_received, unsigned int timeout_ms)
>+{
>+	u32 ctrl_reg, total_frames, current_frame;
>+	size_t payload_size;
>+	int ret;
>+
>+	*bytes_received = 0;

This function could use some refactoring. Maybe something like:

do {
	ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
	current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
	total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;

	if (frame0)
		process_first_frame(ctrl_reg, current_frame, total_frames);
	else
		process_other_frame(ctrl_reg, current_frame, total_frames);
} while (current_frame + 1 < total_frames);


>+
>+	do {
>+		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
>+		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
>+		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
>+
>+		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
>+			current_frame, total_frames - 1);
>+
>+		if (current_frame == 0) {
>+			u32 temp_frame[4];
>+			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
>+
>+			sc_mb_read_frame(sc, temp_frame, 0);
>+			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
>+
>+			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
>+			if (ret)
>+				return ret;
>+
>+			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);

sizeof(*resp_hdr) should do. If payload size is always a constant (16 - 4), then
#define it as a constant.

>+			if (payload_size > data_out_len) {
>+				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
>+				return -ENOSPC;
>+			}
>+
>+			memcpy(data_out,
>+			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),

same here sizeof(*resp_hdr);

>+			       payload_size);
>+			*bytes_received = payload_size;
>+		} else {
>+			size_t frame_size = SC_MB_FRAME_SIZE;
>+
>+			if (current_frame == total_frames - 1) {
>+				size_t total_response = (total_frames - 1) *
>+							SC_MB_FRAME_SIZE +
>+							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
>+				size_t remaining = total_response -
>+						   *bytes_received -
>+						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
>+				frame_size = min(frame_size, remaining);
>+			}
>+
>+			if (*bytes_received + frame_size > data_out_len) {
>+				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
>+				return -ENOSPC;
>+			}
>+
>+			sc_mb_read_frame(sc, data_out, *bytes_received);
>+			*bytes_received += frame_size;
>+		}
>+
>+		sc_mb_clear_response(sc);
>+
>+		if (current_frame + 1 < total_frames &&
>+		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
>+			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
>+				current_frame + 1);
>+			return -ETIMEDOUT;
>+		}

Assuming that the FW is not setting SC_MB_CTRL_RUN_BUSY_OUT on the last frame.
OR Are you intentionally skipping waiting for it? 

Umesh

>+
>+	} while (current_frame + 1 < total_frames);
>+
>+	return 0;
>+}
>+
>+static int sc_mb_send_command(struct xe_sc *sc,
>+			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
>+			      const u8 *cmd_buffer, size_t cmd_size,
>+			      void *data_out, size_t data_out_len,
>+			      size_t *rdata_len, unsigned int timeout_ms)
>+{
>+	size_t bytes_received;
>+	int ret;
>+
>+	if (rdata_len)
>+		*rdata_len = 0;
>+
>+	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
>+	if (ret)
>+		return ret;
>+
>+	if (!data_out) {
>+		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
>+		return 0;
>+	}
>+
>+	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
>+		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
>+		return -ETIMEDOUT;
>+	}
>+
>+	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
>+				   &bytes_received, timeout_ms);
>+	if (ret) {
>+		sc_mb_clear_response(sc);
>+		return ret;
>+	}
>+
>+	if (rdata_len)
>+		*rdata_len = bytes_received;
>+
>+	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
>+		bytes_received);
>+
>+	return 0;
>+}
>+
>+/**
>+ * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
>+ * @handle: XE device handle containing the system controller
>+ * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
>+ * @rdata_len: Pointer to store actual response data size (can be NULL)
>+ *
>+ * Send a command to the System Controller using MKHI protocol. Handles
>+ * command preparation, fragmentation, transmission, and response reception.
>+ * Optimized to move memory allocation outside the critical section.
>+ *
>+ * Return: 0 on success, negative error code on failure
>+ */
>+int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
>+{
>+	struct xe_device *xe = handle;
>+	struct xe_sc *sc;
>+	struct xe_sc_mailbox_command *cmd = cmd_buffer;
>+	u8 *command_buffer = NULL;
>+	size_t command_size;
>+	int ret;
>+
>+	if (!xe || !cmd)
>+		return -EINVAL;
>+
>+	sc = xe->sc;
>+	if (!sc)
>+		return -ENODEV;
>+
>+	if (!cmd->data_in && cmd->data_in_len)
>+		return -EINVAL;
>+
>+	if (!cmd->data_out && cmd->data_out_len)
>+		return -EINVAL;
>+
>+	might_sleep();
>+
>+	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
>+				    &command_buffer, &command_size);
>+	if (ret) {
>+		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
>+		return ret;
>+	}
>+
>+	mutex_lock(&sc->cmd_lock);
>+
>+	xe_pm_runtime_get(xe);
>+
>+	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
>+				 cmd->data_out, cmd->data_out_len, rdata_len,
>+				 SC_MB_DEFAULT_TIMEOUT_MS);
>+	if (ret)
>+		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
>+
>+	xe_pm_runtime_put(xe);
>+
>+	mutex_unlock(&sc->cmd_lock);
>+
>+	kfree(command_buffer);
>+
>+	return ret;
>+}
>diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
>new file mode 100644
>index 000000000000..d5ca43c40f1a
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
>@@ -0,0 +1,61 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef __XE_SC_MAILBOX_H__
>+#define __XE_SC_MAILBOX_H__
>+
>+#include <linux/types.h>
>+
>+struct xe_sc;
>+
>+/**
>+ * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
>+ */
>+struct xe_sc_mailbox_mkhi_msg_hdr {
>+	/** @group_id: Message group identifier */
>+	u32 group_id    : 8;
>+	/** @command: Command identifier within the group */
>+	u32 command     : 7;
>+	/** @is_response: Response flag - 0 for request, 1 for response */
>+	u32 is_response : 1;
>+	/** @reserved: Reserved field, must be zero */
>+	u32 reserved    : 8;
>+	/** @result: Result code from firmware */
>+	u32 result      : 8;
>+} __packed;
>+
>+/**
>+ * struct xe_sc_mailbox_app_msg_hdr - Application message header
>+ */
>+struct xe_sc_mailbox_app_msg_hdr {
>+	/** @group_id: Application group identifier */
>+	u32 group_id  : 8;
>+	/** @command: Specific command within the application group */
>+	u32 command   : 8;
>+	/** @version: Protocol version */
>+	u32 version   : 8;
>+	/** @reserved: Reserved field, must be zero */
>+	u32 reserved  : 8;
>+} __packed;
>+
>+/**
>+ * struct xe_sc_mailbox_command - System Controller mailbox command structure
>+ */
>+struct xe_sc_mailbox_command {
>+	/** @header: Application message header containing command information */
>+	struct xe_sc_mailbox_app_msg_hdr header;
>+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
>+	void *data_in;
>+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
>+	size_t data_in_len;
>+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
>+	void *data_out;
>+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
>+	size_t data_out_len;
>+};
>+
>+int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
>+
>+#endif /* __XE_SC_MAILBOX_H__ */
>diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
>new file mode 100644
>index 000000000000..5ec2126cebe4
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/xe_sc_types.h
>@@ -0,0 +1,35 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2025 Intel Corporation
>+ */
>+
>+#ifndef _XE_SC_TYPES_H_
>+#define _XE_SC_TYPES_H_
>+
>+#include <linux/completion.h>
>+#include <linux/mutex.h>
>+#include <linux/types.h>
>+#include <linux/workqueue.h>
>+
>+#include "xe_device_types.h"
>+#include "xe_sc_mailbox.h"
>+
>+struct xe_device;
>+
>+/**
>+ * struct xe_sc - System Controller driver context
>+ */
>+struct xe_sc {
>+	/** @xe: Back pointer to xe_device */
>+	struct xe_device *xe;
>+	/** @mmio: MMIO region for SC registers */
>+	struct xe_mmio mmio;
>+
>+	/** @cmd_lock: Mutex protecting mailbox command operations */
>+	struct mutex cmd_lock;
>+
>+	/** @phase_bit: MKHI message boundary phase toggle bit */
>+	u32 phase_bit;
>+};
>+
>+#endif /* _XE_SC_TYPES_H_ */
>-- 
>2.43.0
>

Re: [RFC 5/5] drm/xe/sc: Add system controller component for Xe3p dGPU platforms

[Nilawar, Badal]

On 22-11-2025 10:28, Anoop, Vijay wrote:
> From: Anoop Vijay <anoop.c.vijay@intel.com>
>
> Add a new system controller (SC) component for Intel Xe3p dGPU platforms.
>
> This component provides the foundational infrastructure for communication
> with the SC firmware using the MKHI protocol over a mailbox interface.
>
> Key features introduced:
> - Detection and initialization of the SC interface on Xe3p dGPU platforms
> - Mailbox communication with SC firmware
> - Fragmented message transfer for large command payloads
>
> This implementation establishes the base for future SC feature
> enablement and firmware command handling.
>
> Signed-off-by: Anoop Vijay <anoop.c.vijay@intel.com>
> ---
>   drivers/gpu/drm/xe/Makefile          |   2 +
>   drivers/gpu/drm/xe/regs/xe_sc_regs.h |  49 ++++
>   drivers/gpu/drm/xe/xe_device.c       |   5 +
>   drivers/gpu/drm/xe/xe_device_types.h |   5 +
>   drivers/gpu/drm/xe/xe_sc.c           |  89 +++++++
>   drivers/gpu/drm/xe/xe_sc.h           |  15 ++
>   drivers/gpu/drm/xe/xe_sc_mailbox.c   | 374 +++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_sc_mailbox.h   |  61 +++++
>   drivers/gpu/drm/xe/xe_sc_types.h     |  35 +++
>   9 files changed, 635 insertions(+)
>   create mode 100644 drivers/gpu/drm/xe/regs/xe_sc_regs.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sc.c
>   create mode 100644 drivers/gpu/drm/xe/xe_sc.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.c
>   create mode 100644 drivers/gpu/drm/xe/xe_sc_mailbox.h
>   create mode 100644 drivers/gpu/drm/xe/xe_sc_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 7ebfbf9051bf..50e8dc86d915 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -114,7 +114,9 @@ xe-y += xe_bb.o \
>   	xe_ring_ops.o \
>   	xe_rtp.o \
>   	xe_sa.o \
> +	xe_sc.o \
>   	xe_sched_job.o \
> +	xe_sc_mailbox.o \
>   	xe_shrinker.o \
>   	xe_step.o \
>   	xe_survivability_mode.o \
> diff --git a/drivers/gpu/drm/xe/regs/xe_sc_regs.h b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> new file mode 100644
> index 000000000000..2b7053586197
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_sc_regs.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SC_REGS_H_
> +#define _XE_SC_REGS_H_
> +
> +#include "xe_regs.h"
> +
> +#define SYSCTRL_BASE_OFFSET		0xDB000
> +#define SYSCTRL_BASE			(SOC_BASE + SYSCTRL_BASE_OFFSET)
> +#define SYSCTRL_MAILBOX_INDEX		0x03
> +#define SC_BAR_LENGTH			0x1000
> +
> +#define SC_MB_CTRL			XE_REG(SYSCTRL_BASE + 0x10)
> +#define   SC_MB_CTRL_RUN_BUSY		REG_BIT(31)
> +#define   SC_MB_CTRL_IRQ		REG_BIT(30)
> +#define   SC_MB_CTRL_RUN_BUSY_OUT	REG_BIT(29)
> +#define   SC_MB_CTRL_PARAM3		REG_GENMASK(28, 24)
> +#define   SC_MB_CTRL_PARAM2		REG_GENMASK(23, 16)
> +#define   SC_MB_CTRL_PARAM1		REG_GENMASK(15, 8)
> +#define   SC_MB_CTRL_COMMAND		REG_GENMASK(7, 0)
> +
> +#define SC_MB_DATA0			XE_REG(SYSCTRL_BASE + 0x14)
> +#define SC_MB_DATA1			XE_REG(SYSCTRL_BASE + 0x18)
> +#define SC_MB_DATA2			XE_REG(SYSCTRL_BASE + 0x1C)
> +#define SC_MB_DATA3			XE_REG(SYSCTRL_BASE + 0x20)
> +
> +#define MKHI_FRAME_PHASE		REG_BIT(24)
> +#define MKHI_FRAME_CURRENT		REG_GENMASK(21, 16)
> +#define MKHI_FRAME_TOTAL		REG_GENMASK(13, 8)
> +#define MKHI_FRAME_COMMAND		REG_GENMASK(7, 0)
> +
> +#define MKHI_HDR_RESULT			REG_GENMASK(31, 24)
> +#define MKHI_HDR_IS_RESPONSE		REG_BIT(15)
> +#define MKHI_HDR_COMMAND		REG_GENMASK(14, 8)
> +#define MKHI_HDR_GROUP_ID		REG_GENMASK(7, 0)
> +
> +#define SC_MB_FRAME_SIZE		16
> +#define SC_MB_MAX_FRAMES		64
> +#define SC_MB_MAX_MESSAGE_SIZE		(SC_MB_FRAME_SIZE * SC_MB_MAX_FRAMES)
> +#define SC_MKHI_COMMAND			5
> +
> +#define SC_MB_DEFAULT_TIMEOUT_MS	500
> +#define SC_MB_RETRY_TIMEOUT_MS		20
> +#define SC_MB_POLL_INTERVAL_US		100
> +
> +#endif /* _XE_SC_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index f15489c100af..9fbd0b084c74 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -60,6 +60,7 @@
>   #include "xe_psmi.h"
>   #include "xe_pxp.h"
>   #include "xe_query.h"
> +#include "xe_sc.h"
>   #include "xe_soc_remapper.h"
>   #include "xe_shrinker.h"
>   #include "xe_survivability_mode.h"
> @@ -963,6 +964,10 @@ int xe_device_probe(struct xe_device *xe)
>   	if (err)
>   		goto err_unregister_display;
>   
> +	err = xe_sc_init(xe);
> +	if (err)
> +		goto err_unregister_display;
> +
>   	for_each_gt(gt, xe, id)
>   		xe_gt_sanitize_freq(gt);
>   
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 3f118c64a124..86a0c83c802d 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -314,6 +314,8 @@ struct xe_device {
>   		u8 has_range_tlb_inval:1;
>   		/** @info.has_sriov: Supports SR-IOV */
>   		u8 has_sriov:1;
> +		/** @info.has_sysctrl: Supports System Controller */
> +		u8 has_sysctrl:1;
>   		/** @info.has_usm: Device has unified shared memory support */
>   		u8 has_usm:1;
>   		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
> @@ -576,6 +578,9 @@ struct xe_device {
>   	/** @heci_gsc: graphics security controller */
>   	struct xe_heci_gsc heci_gsc;
>   
> +	/** @sc: System Controller */
> +	struct xe_sc *sc;
> +
>   	/** @nvm: discrete graphics non-volatile memory */
>   	struct intel_dg_nvm_dev *nvm;
>   
> diff --git a/drivers/gpu/drm/xe/xe_sc.c b/drivers/gpu/drm/xe/xe_sc.c
> new file mode 100644
> index 000000000000..18448efc173f
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc.c
> @@ -0,0 +1,89 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include "xe_sc.h"
> +
> +#include <linux/mutex.h>
> +
> +#include <drm/drm_managed.h>
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_sc_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_platform_types.h"
> +#include "xe_soc_remapper.h"
> +#include "xe_sc_types.h"
> +#include "xe_tile.h"
> +
> +static void xe_sc_remove(struct drm_device *drm, void *arg)
> +{
> +	struct xe_sc *sc = arg;
> +	struct xe_device *xe;
> +
> +	if (!sc)
> +		return;
> +
> +	xe = to_xe_device(drm);
> +
> +	mutex_destroy(&sc->cmd_lock);
> +
> +	xe_soc_remapper_set_sysctrl_region(xe, 0);
> +
> +	xe->sc = NULL;
> +}
> +
> +static int xe_sc_probe(struct xe_device *xe)
> +{
> +	struct xe_tile *tile = xe_device_get_root_tile(xe);
> +	struct xe_sc *sc;
> +	int ret;
> +
> +	sc = drmm_kzalloc(&xe->drm, sizeof(*sc), GFP_KERNEL);
> +	if (!sc)
> +		return -ENOMEM;
> +
> +	sc->xe = xe;
Using container_of would avoid the need for an explicit back pointer.
> +	xe->sc = sc;
> +
> +	ret = drmm_add_action_or_reset(&xe->drm, xe_sc_remove, sc);
> +	if (ret) {
> +		xe->sc = NULL;
> +		return ret;
> +	}
> +
> +	xe_soc_remapper_set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> +
> +	xe_mmio_init(&sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
Is it necessary to maintain sc->mmio? It seems we could use &tile->mmio 
directly when accessing SC MB registers.
> +
> +	mutex_init(&sc->cmd_lock);
> +
> +	sc->phase_bit = 0;
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sc_init - Initialize SC subsystem
> + * @xe: xe device instance
> + *
> + * Entry point for SC initialization, called from xe_device_probe().
> + * This function checks platform support and calls the main probe function.
> + *
> + * Return: 0 on success, error code on failure
> + */
> +int xe_sc_init(struct xe_device *xe)
> +{
> +	int ret;
> +
> +	if (!xe->info.has_sysctrl)
> +		return 0;
> +
> +	ret = xe_sc_probe(xe);
> +	if (ret)
> +		drm_err(&xe->drm, "sysctrl: Probe failed: %d\n", ret);
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sc.h b/drivers/gpu/drm/xe/xe_sc.h
> new file mode 100644
> index 000000000000..0e5c89ddc957
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __XE_SC_H__
> +#define __XE_SC_H__
> +
> +#include <linux/types.h>
> +
> +struct xe_device;
> +
> +int xe_sc_init(struct xe_device *xe);
> +
> +#endif /* __XE_SC_H__ */
> diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.c b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> new file mode 100644
> index 000000000000..6f2500c63a3c
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.c
> @@ -0,0 +1,374 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/errno.h>
> +#include <linux/minmax.h>
> +#include <linux/mutex.h>
> +#include <linux/slab.h>
> +#include <linux/string.h>
> +#include <linux/types.h>
> +
> +#include <drm/drm_print.h>
> +
> +#include "regs/xe_sc_regs.h"
> +#include "xe_device.h"
> +#include "xe_mmio.h"
> +#include "xe_pm.h"
> +#include "xe_sc.h"
> +#include "xe_sc_mailbox.h"
> +#include "xe_sc_types.h"
> +
> +static bool sc_mb_wait_bit_clear(struct xe_sc *sc, u32 bit_mask,
> +				 unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	if (timeout_ms == 0) {
> +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +					 0, NULL, false);
> +	} else {
> +		ret = xe_mmio_wait32_not(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +					 timeout_ms * 1000, NULL, false);
This code can handle timeout_ms = 0 use case as well.
> +	}
> +
> +	return ret == 0;
> +}
> +
> +static bool sc_mb_wait_bit_set(struct xe_sc *sc, u32 bit_mask,
> +			       unsigned int timeout_ms)
> +{
> +	int ret;
> +
> +	if (timeout_ms == 0) {
> +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +				     0, NULL, false);
> +	} else {
> +		ret = xe_mmio_wait32(&sc->mmio, SC_MB_CTRL, bit_mask, bit_mask,
> +				     timeout_ms * 1000, NULL, false);
Same as above.
> +	}
> +
> +	return ret == 0;
> +}
> +
> +static void sc_mb_write_frame(struct xe_sc *sc, const void *buffer,
> +			      size_t offset)
> +{
> +	const u32 *data = (const u32 *)((const u8 *)buffer + offset);
> +
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA0, data[0]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA1, data[1]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA2, data[2]);
> +	xe_mmio_write32(&sc->mmio, SC_MB_DATA3, data[3]);
> +}
> +
> +static void sc_mb_read_frame(struct xe_sc *sc, void *buffer,
> +			     size_t offset)
> +{
> +	u32 *data = (u32 *)((u8 *)buffer + offset);
> +
> +	data[0] = xe_mmio_read32(&sc->mmio, SC_MB_DATA0);
> +	data[1] = xe_mmio_read32(&sc->mmio, SC_MB_DATA1);
> +	data[2] = xe_mmio_read32(&sc->mmio, SC_MB_DATA2);
> +	data[3] = xe_mmio_read32(&sc->mmio, SC_MB_DATA3);
> +}
> +
> +static void sc_mb_clear_response(struct xe_sc *sc)
> +{
> +	xe_mmio_write32(&sc->mmio, SC_MB_CTRL, SC_MB_CTRL_RUN_BUSY_OUT);
> +}
> +
> +static int sc_mb_prepare_command(struct xe_sc *sc,
> +				 const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +				 const void *data_in, size_t data_in_len,
> +				 u8 **cmd_buffer, size_t *cmd_size)
> +{
> +	struct xe_sc_mailbox_mkhi_msg_hdr mkhi_hdr = {0};
> +
> +	mkhi_hdr.group_id = msg_hdr->group_id;
> +	mkhi_hdr.command = msg_hdr->command & 0x7F;
> +	mkhi_hdr.is_response = 0;
> +	mkhi_hdr.reserved = 0;
> +	mkhi_hdr.result = 0;
> +
> +	*cmd_size = sizeof(struct xe_sc_mailbox_mkhi_msg_hdr) + data_in_len;
> +
> +	if (*cmd_size > SC_MB_MAX_MESSAGE_SIZE) {
> +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (max %u)\n",
> +			*cmd_size, SC_MB_MAX_MESSAGE_SIZE);
> +		return -EINVAL;
> +	}
> +
> +	*cmd_buffer = kmalloc(*cmd_size, GFP_KERNEL);
> +	if (!*cmd_buffer)
> +		return -ENOMEM;
> +
> +	memcpy(*cmd_buffer, &mkhi_hdr, sizeof(struct xe_sc_mailbox_mkhi_msg_hdr));
> +	if (data_in && data_in_len)
> +		memcpy(*cmd_buffer + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> +		       data_in, data_in_len);
> +
> +	drm_dbg(&sc->xe->drm, "SC: request: group=0x%02x cmd=0x%02x payload=%zu bytes\n",
> +		mkhi_hdr.group_id, mkhi_hdr.command, data_in_len);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_send_frames(struct xe_sc *sc, const u8 *cmd_buffer,
> +			     size_t cmd_size, unsigned int timeout_ms)
> +{
> +	u32 ctrl_reg, total_frames, current_frame;
> +	size_t bytes_sent, bytes_to_send;
> +
> +	total_frames = DIV_ROUND_UP(cmd_size, SC_MB_FRAME_SIZE);
> +	if (total_frames > SC_MB_MAX_FRAMES) {
> +		drm_err(&sc->xe->drm, "SC: Message too large: %zu bytes (%u frames, max %u)\n",
> +			cmd_size, total_frames, SC_MB_MAX_FRAMES);
> +		return -EINVAL;
> +	}
> +
> +	if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +		drm_err(&sc->xe->drm, "SC: Mailbox busy (RUN_BUSY timeout)\n");
> +		return -EBUSY;
> +	}
> +
> +	sc->phase_bit ^= 1;
> +
> +	drm_dbg(&sc->xe->drm, "SC: Sending message: %zu bytes, %u frames, phase=%u\n",
> +		cmd_size, total_frames, sc->phase_bit);
> +
> +	bytes_sent = 0;
> +	for (current_frame = 0; current_frame < total_frames; current_frame++) {
> +		bytes_to_send = min(cmd_size - bytes_sent, (size_t)SC_MB_FRAME_SIZE);
> +
> +		sc_mb_write_frame(sc, cmd_buffer, bytes_sent);
> +
> +		ctrl_reg = SC_MB_CTRL_RUN_BUSY |
> +			   FIELD_PREP(MKHI_FRAME_CURRENT, current_frame) |
> +			   FIELD_PREP(MKHI_FRAME_TOTAL, total_frames - 1) |
> +			   FIELD_PREP(MKHI_FRAME_COMMAND, SC_MKHI_COMMAND);
> +		if (sc->phase_bit)
> +			ctrl_reg |= FIELD_PREP(MKHI_FRAME_PHASE, 1);
> +
> +		xe_mmio_write32(&sc->mmio, SC_MB_CTRL, ctrl_reg);
> +
> +		drm_dbg(&sc->xe->drm, "SC: Sent frame %u/%u\n",
> +			current_frame, total_frames - 1);
> +
> +		if (!sc_mb_wait_bit_clear(sc, SC_MB_CTRL_RUN_BUSY, timeout_ms)) {
> +			drm_err(&sc->xe->drm, "SC: Frame %u acknowledgment timeout\n",
> +				current_frame);
> +			return -ETIMEDOUT;
> +		}
> +
> +		bytes_sent += bytes_to_send;
> +	}
> +
> +	drm_dbg(&sc->xe->drm, "SC: All frames sent successfully (%zu bytes)\n", bytes_sent);
> +	return 0;
> +}
> +
> +static int sc_mb_validate_response_header(struct xe_sc *sc,
> +					  const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +					  const struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr)
> +{
> +	if (!resp_hdr->is_response ||
> +	    resp_hdr->group_id != msg_hdr->group_id ||
> +	    resp_hdr->command != (msg_hdr->command & 0x7F)) {
> +		drm_err(&sc->xe->drm, "SC: Invalid response header\n");
> +		return -EPROTO;
> +	}
> +
> +	if (resp_hdr->result != 0) {
> +		drm_err(&sc->xe->drm, "SC: Firmware error: result=0x%02x\n",
> +			resp_hdr->result);
> +		return -EIO;
> +	}
> +
> +	drm_dbg(&sc->xe->drm, "SC: response: group=0x%02x cmd=0x%02x\n",
> +		resp_hdr->group_id, resp_hdr->command);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_receive_frames(struct xe_sc *sc,
> +				const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +				void *data_out, size_t data_out_len,
> +				size_t *bytes_received, unsigned int timeout_ms)
> +{
> +	u32 ctrl_reg, total_frames, current_frame;
> +	size_t payload_size;
> +	int ret;
> +
> +	*bytes_received = 0;
> +
> +	do {
> +		ctrl_reg = xe_mmio_read32(&sc->mmio, SC_MB_CTRL);
> +		current_frame = FIELD_GET(MKHI_FRAME_CURRENT, ctrl_reg);
> +		total_frames = FIELD_GET(MKHI_FRAME_TOTAL, ctrl_reg) + 1;
> +
> +		drm_dbg(&sc->xe->drm, "SC: Receiving frame %u/%u\n",
> +			current_frame, total_frames - 1);
> +
> +		if (current_frame == 0) {
> +			u32 temp_frame[4];
> +			struct xe_sc_mailbox_mkhi_msg_hdr *resp_hdr;
> +
> +			sc_mb_read_frame(sc, temp_frame, 0);
> +			resp_hdr = (struct xe_sc_mailbox_mkhi_msg_hdr *)temp_frame;
> +
> +			ret = sc_mb_validate_response_header(sc, msg_hdr, resp_hdr);
> +			if (ret)
> +				return ret;
> +
> +			payload_size = SC_MB_FRAME_SIZE - sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +			if (payload_size > data_out_len) {
> +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> +				return -ENOSPC;
> +			}
> +
> +			memcpy(data_out,
> +			       (u8 *)temp_frame + sizeof(struct xe_sc_mailbox_mkhi_msg_hdr),
> +			       payload_size);
> +			*bytes_received = payload_size;
> +		} else {
> +			size_t frame_size = SC_MB_FRAME_SIZE;
> +
> +			if (current_frame == total_frames - 1) {
> +				size_t total_response = (total_frames - 1) *
> +							SC_MB_FRAME_SIZE +
> +							sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +				size_t remaining = total_response -
> +						   *bytes_received -
> +						   sizeof(struct xe_sc_mailbox_mkhi_msg_hdr);
> +				frame_size = min(frame_size, remaining);
> +			}
> +
> +			if (*bytes_received + frame_size > data_out_len) {
> +				drm_err(&sc->xe->drm, "SC: Response buffer too small\n");
> +				return -ENOSPC;
> +			}
> +
> +			sc_mb_read_frame(sc, data_out, *bytes_received);
> +			*bytes_received += frame_size;
> +		}
> +
> +		sc_mb_clear_response(sc);
> +
> +		if (current_frame + 1 < total_frames &&
> +		    !sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +			drm_err(&sc->xe->drm, "SC: Response frame %u timeout\n",
> +				current_frame + 1);
> +			return -ETIMEDOUT;
> +		}
> +
> +	} while (current_frame + 1 < total_frames);
> +
> +	return 0;
> +}
> +
> +static int sc_mb_send_command(struct xe_sc *sc,
> +			      const struct xe_sc_mailbox_app_msg_hdr *msg_hdr,
> +			      const u8 *cmd_buffer, size_t cmd_size,
> +			      void *data_out, size_t data_out_len,
> +			      size_t *rdata_len, unsigned int timeout_ms)
> +{
> +	size_t bytes_received;
> +	int ret;
> +
> +	if (rdata_len)
> +		*rdata_len = 0;
> +
> +	ret = sc_mb_send_frames(sc, cmd_buffer, cmd_size, timeout_ms);
> +	if (ret)
> +		return ret;
> +
> +	if (!data_out) {
> +		drm_dbg(&sc->xe->drm, "SC: Command completed (no response expected)\n");
> +		return 0;
> +	}
> +
> +	if (!sc_mb_wait_bit_set(sc, SC_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
> +		drm_err(&sc->xe->drm, "SC: Response timeout (RUN_BUSY_OUT not set)\n");
> +		return -ETIMEDOUT;
> +	}
> +
> +	ret = sc_mb_receive_frames(sc, msg_hdr, data_out, data_out_len,
> +				   &bytes_received, timeout_ms);
> +	if (ret) {
> +		sc_mb_clear_response(sc);
> +		return ret;
> +	}
> +
> +	if (rdata_len)
> +		*rdata_len = bytes_received;
> +
> +	drm_dbg(&sc->xe->drm, "SC: MKHI message completed: %zu bytes payload received\n",
> +		bytes_received);
> +
> +	return 0;
> +}
> +
> +/**
> + * xe_sc_mailbox_send_command - Send command to System Controller via mailbox
> + * @handle: XE device handle containing the system controller
> + * @cmd_buffer: Pointer to xe_sc_mailbox_command structure
> + * @rdata_len: Pointer to store actual response data size (can be NULL)
> + *
> + * Send a command to the System Controller using MKHI protocol. Handles
> + * command preparation, fragmentation, transmission, and response reception.
> + * Optimized to move memory allocation outside the critical section.
> + *
> + * Return: 0 on success, negative error code on failure
> + */
> +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len)
> +{
> +	struct xe_device *xe = handle;
> +	struct xe_sc *sc;
> +	struct xe_sc_mailbox_command *cmd = cmd_buffer;
> +	u8 *command_buffer = NULL;
> +	size_t command_size;
> +	int ret;
> +
> +	if (!xe || !cmd)
> +		return -EINVAL;
> +
> +	sc = xe->sc;
> +	if (!sc)
> +		return -ENODEV;
> +
> +	if (!cmd->data_in && cmd->data_in_len)
> +		return -EINVAL;
> +
> +	if (!cmd->data_out && cmd->data_out_len)
> +		return -EINVAL;
> +
> +	might_sleep();
> +
> +	ret = sc_mb_prepare_command(sc, &cmd->header, cmd->data_in, cmd->data_in_len,
> +				    &command_buffer, &command_size);
> +	if (ret) {
> +		drm_err(&sc->xe->drm, "SC: Failed to prepare command: %d\n", ret);
> +		return ret;
> +	}
> +
> +	mutex_lock(&sc->cmd_lock);
> +
> +	xe_pm_runtime_get(xe);
Will suggest to get lock at this place i.e. after resuming the device.
> +
> +	ret = sc_mb_send_command(sc, &cmd->header, command_buffer, command_size,
> +				 cmd->data_out, cmd->data_out_len, rdata_len,
> +				 SC_MB_DEFAULT_TIMEOUT_MS);
> +	if (ret)
> +		drm_err(&sc->xe->drm, "SC: Mailbox command failed: %d\n", ret);
release lock here.
> +
> +	xe_pm_runtime_put(xe);
> +
> +	mutex_unlock(&sc->cmd_lock);
> +
> +	kfree(command_buffer);
> +
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sc_mailbox.h b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> new file mode 100644
> index 000000000000..d5ca43c40f1a
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_mailbox.h
> @@ -0,0 +1,61 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __XE_SC_MAILBOX_H__
> +#define __XE_SC_MAILBOX_H__
> +
> +#include <linux/types.h>
> +
> +struct xe_sc;
> +
> +/**
> + * struct xe_sc_mailbox_mkhi_msg_hdr - MKHI protocol message header
> + */
> +struct xe_sc_mailbox_mkhi_msg_hdr {
> +	/** @group_id: Message group identifier */
> +	u32 group_id    : 8;
> +	/** @command: Command identifier within the group */
> +	u32 command     : 7;
> +	/** @is_response: Response flag - 0 for request, 1 for response */
> +	u32 is_response : 1;
> +	/** @reserved: Reserved field, must be zero */
> +	u32 reserved    : 8;
> +	/** @result: Result code from firmware */
> +	u32 result      : 8;
> +} __packed;
> +
> +/**
> + * struct xe_sc_mailbox_app_msg_hdr - Application message header
> + */
> +struct xe_sc_mailbox_app_msg_hdr {
> +	/** @group_id: Application group identifier */
> +	u32 group_id  : 8;
> +	/** @command: Specific command within the application group */
> +	u32 command   : 8;
> +	/** @version: Protocol version */
> +	u32 version   : 8;
> +	/** @reserved: Reserved field, must be zero */
> +	u32 reserved  : 8;
> +} __packed;
> +
> +/**
> + * struct xe_sc_mailbox_command - System Controller mailbox command structure
> + */
> +struct xe_sc_mailbox_command {
> +	/** @header: Application message header containing command information */
> +	struct xe_sc_mailbox_app_msg_hdr header;
> +	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
> +	void *data_in;
> +	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
> +	size_t data_in_len;
> +	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
> +	void *data_out;
> +	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
> +	size_t data_out_len;
> +};
> +
> +int xe_sc_mailbox_send_command(void *handle, void *cmd_buffer, size_t *rdata_len);
> +
> +#endif /* __XE_SC_MAILBOX_H__ */
> diff --git a/drivers/gpu/drm/xe/xe_sc_types.h b/drivers/gpu/drm/xe/xe_sc_types.h
> new file mode 100644
> index 000000000000..5ec2126cebe4
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sc_types.h
> @@ -0,0 +1,35 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef _XE_SC_TYPES_H_
> +#define _XE_SC_TYPES_H_
> +
> +#include <linux/completion.h>
> +#include <linux/mutex.h>
> +#include <linux/types.h>
> +#include <linux/workqueue.h>
> +
> +#include "xe_device_types.h"
> +#include "xe_sc_mailbox.h"
> +
> +struct xe_device;
> +
> +/**
> + * struct xe_sc - System Controller driver context
> + */
> +struct xe_sc {
> +	/** @xe: Back pointer to xe_device */
> +	struct xe_device *xe;
As mentioned above, drop this. Either use container_of to get xe or 
instead of passing struct xe_sc to mailbox functions pass struct xe.
> +	/** @mmio: MMIO region for SC registers */
> +	struct xe_mmio mmio;
As mentioned above. No need to maintain this, just use root time mmio.
> +
> +	/** @cmd_lock: Mutex protecting mailbox command operations */
> +	struct mutex cmd_lock;
> +
> +	/** @phase_bit: MKHI message boundary phase toggle bit */
> +	u32 phase_bit;
> +};

This structure can go inside struct xe_device.

Thanks,
Badal

> +
> +#endif /* _XE_SC_TYPES_H_ */