* [PATCH v3 0/3] Fix Cx0 Suspend Resume issue
@ 2026-01-16 8:54 Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier Suraj Kandpal
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Suraj Kandpal @ 2026-01-16 8:54 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
CX0 PHY currently has two issues which cause a hang when we try
to suspend resume machine with a delay of 15mins and 1+ hour.
This happens due to two reasons:
1) We do not follow the Enablement sequence where we need to
enable our clock after PPS Enablement cycle
2) We do not make sure response ready and error bit are cleared
in P2M_MSGBUS_STATUS before writing the transaction pending bit.
This series aims to solve this.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Mika Kahola (1):
drm/i915/pps: Enable panel power earlier
Suraj Kandpal (2):
drm/i915/cx0: Clear response ready & error bit
drm/i915/cx0: Rename intel_clear_response_ready flag
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++++-----
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++
drivers/gpu/drm/i915/display/intel_lt_phy.c | 2 +-
5 files changed, 21 insertions(+), 10 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
@ 2026-01-16 8:54 ` Suraj Kandpal
2026-01-20 13:57 ` Jani Nikula
2026-01-16 8:54 ` [PATCH v3 2/3] drm/i915/cx0: Clear response ready & error bit Suraj Kandpal
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Suraj Kandpal @ 2026-01-16 8:54 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Mika Kahola, Suraj Kandpal
From: Mika Kahola <mika.kahola@intel.com>
Move intel_pps_on() to intel_dpll_mgr PLL enabling
.enable function hook to enable panel power earlier.
We need to do this to make sure we are following the
modeset sequences of Bspec. This had changed when we
moved the PLL PHY enablement for CX0 from .enable_clock
to dpll.enable hook
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
v2 -> v3:
- Rather than splitting the PHY enablement sequence, enable PPS
earlier (Imre)
drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index cb91d07cdaa6..1784fa687c03 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2653,8 +2653,10 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 3. Select Thunderbolt */
mtl_port_buf_ctl_io_selection(encoder);
- /* 4. Enable Panel Power if PPS is required */
- intel_pps_on(intel_dp);
+ /*
+ * 4. Enable Panel Power if PPS is required
+ * moved to intel_dpll_mgr .enable hook
+ */
/* 5. Enable the port PLL */
intel_ddi_enable_clock(encoder, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9aa84a430f09..b5655c734c53 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -40,6 +40,7 @@
#include "intel_hti.h"
#include "intel_mg_phy_regs.h"
#include "intel_pch_refclk.h"
+#include "intel_pps.h"
#include "intel_step.h"
#include "intel_tc.h"
@@ -4401,6 +4402,10 @@ static void mtl_pll_enable(struct intel_display *display,
if (drm_WARN_ON(display->drm, !encoder))
return;
+ /* Enable Panel Power if PPS is required */
+ if (intel_encoder_is_dp(encoder))
+ intel_pps_on(enc_to_intel_dp(encoder));
+
intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 2/3] drm/i915/cx0: Clear response ready & error bit
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier Suraj Kandpal
@ 2026-01-16 8:54 ` Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag Suraj Kandpal
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Suraj Kandpal @ 2026-01-16 8:54 UTC (permalink / raw)
To: intel-xe, intel-gfx
Cc: ankit.k.nautiyal, Suraj Kandpal, Gustavo Sousa,
Michał Grzelak
Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS
before writing the transaction pending bit of
PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done
we find that the PHY hangs since it ends up in a weird state if left
idle for more than 1 hour.
Bspec: 65101
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7288065d2461..5b6b1ce40b0d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -222,6 +222,8 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
return -ETIMEDOUT;
}
+ intel_clear_response_ready_flag(encoder, lane);
+
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
@@ -293,6 +295,8 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
return -ETIMEDOUT;
}
+ intel_clear_response_ready_flag(encoder, lane);
+
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 2/3] drm/i915/cx0: Clear response ready & error bit Suraj Kandpal
@ 2026-01-16 8:54 ` Suraj Kandpal
2026-01-19 6:43 ` Garg, Nemesa
2026-01-16 9:02 ` ✓ CI.KUnit: success for Fix Cx0 Suspend Resume issue (rev3) Patchwork
` (2 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Suraj Kandpal @ 2026-01-16 8:54 UTC (permalink / raw)
To: intel-xe, intel-gfx; +Cc: ankit.k.nautiyal, Suraj Kandpal
Rename the non static intel_clear_response_ready_flag to
intel_cx0_clear_response_ready_flag so that we follow the
naming standards of non static function.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++-------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 ++--
drivers/gpu/drm/i915/display/intel_lt_phy.c | 2 +-
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5b6b1ce40b0d..3ef25c942f44 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -127,8 +127,8 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, struct
intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref);
}
-void intel_clear_response_ready_flag(struct intel_encoder *encoder,
- int lane)
+void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
+ int lane)
{
struct intel_display *display = to_intel_display(encoder);
@@ -155,7 +155,7 @@ void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
return;
}
- intel_clear_response_ready_flag(encoder, lane);
+ intel_cx0_clear_response_ready_flag(encoder, lane);
}
int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
@@ -222,7 +222,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
return -ETIMEDOUT;
}
- intel_clear_response_ready_flag(encoder, lane);
+ intel_cx0_clear_response_ready_flag(encoder, lane);
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
@@ -233,7 +233,7 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
if (ack < 0)
return ack;
- intel_clear_response_ready_flag(encoder, lane);
+ intel_cx0_clear_response_ready_flag(encoder, lane);
/*
* FIXME: Workaround to let HW to settle
@@ -295,7 +295,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
return -ETIMEDOUT;
}
- intel_clear_response_ready_flag(encoder, lane);
+ intel_cx0_clear_response_ready_flag(encoder, lane);
intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
@@ -325,7 +325,7 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
return -EINVAL;
}
- intel_clear_response_ready_flag(encoder, lane);
+ intel_cx0_clear_response_ready_flag(encoder, lane);
/*
* FIXME: Workaround to let HW to settle
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index ae98ac23ea22..87d3bdaca3ec 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -25,8 +25,8 @@ struct intel_dpll_hw_state;
struct intel_encoder;
struct intel_hdmi;
-void intel_clear_response_ready_flag(struct intel_encoder *encoder,
- int lane);
+void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
+ int lane);
bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
void intel_mtl_pll_enable(struct intel_encoder *encoder,
struct intel_dpll *pll,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 6cdae03ee172..e174ca011d50 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1106,7 +1106,7 @@ static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder,
* This is the time PHY takes to settle down after programming the PHY.
*/
udelay(150);
- intel_clear_response_ready_flag(encoder, lane);
+ intel_cx0_clear_response_ready_flag(encoder, lane);
intel_lt_phy_clear_status_p2p(encoder, lane);
return 0;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ CI.KUnit: success for Fix Cx0 Suspend Resume issue (rev3)
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
` (2 preceding siblings ...)
2026-01-16 8:54 ` [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag Suraj Kandpal
@ 2026-01-16 9:02 ` Patchwork
2026-01-16 9:35 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-16 11:41 ` ✗ Xe.CI.Full: failure " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2026-01-16 9:02 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
== Series Details ==
Series: Fix Cx0 Suspend Resume issue (rev3)
URL : https://patchwork.freedesktop.org/series/159539/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:01:37] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:01:41] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:02:13] Starting KUnit Kernel (1/1)...
[09:02:13] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:02:13] ================== guc_buf (11 subtests) ===================
[09:02:13] [PASSED] test_smallest
[09:02:13] [PASSED] test_largest
[09:02:13] [PASSED] test_granular
[09:02:13] [PASSED] test_unique
[09:02:13] [PASSED] test_overlap
[09:02:13] [PASSED] test_reusable
[09:02:13] [PASSED] test_too_big
[09:02:13] [PASSED] test_flush
[09:02:13] [PASSED] test_lookup
[09:02:13] [PASSED] test_data
[09:02:13] [PASSED] test_class
[09:02:13] ===================== [PASSED] guc_buf =====================
[09:02:13] =================== guc_dbm (7 subtests) ===================
[09:02:13] [PASSED] test_empty
[09:02:13] [PASSED] test_default
[09:02:13] ======================== test_size ========================
[09:02:13] [PASSED] 4
[09:02:13] [PASSED] 8
[09:02:13] [PASSED] 32
[09:02:13] [PASSED] 256
[09:02:13] ==================== [PASSED] test_size ====================
[09:02:13] ======================= test_reuse ========================
[09:02:13] [PASSED] 4
[09:02:13] [PASSED] 8
[09:02:13] [PASSED] 32
[09:02:13] [PASSED] 256
[09:02:13] =================== [PASSED] test_reuse ====================
[09:02:13] =================== test_range_overlap ====================
[09:02:13] [PASSED] 4
[09:02:13] [PASSED] 8
[09:02:13] [PASSED] 32
[09:02:13] [PASSED] 256
[09:02:13] =============== [PASSED] test_range_overlap ================
[09:02:13] =================== test_range_compact ====================
[09:02:13] [PASSED] 4
[09:02:13] [PASSED] 8
[09:02:13] [PASSED] 32
[09:02:13] [PASSED] 256
[09:02:13] =============== [PASSED] test_range_compact ================
[09:02:13] ==================== test_range_spare =====================
[09:02:13] [PASSED] 4
[09:02:13] [PASSED] 8
[09:02:13] [PASSED] 32
[09:02:13] [PASSED] 256
[09:02:13] ================ [PASSED] test_range_spare =================
[09:02:13] ===================== [PASSED] guc_dbm =====================
[09:02:13] =================== guc_idm (6 subtests) ===================
[09:02:13] [PASSED] bad_init
[09:02:13] [PASSED] no_init
[09:02:13] [PASSED] init_fini
[09:02:13] [PASSED] check_used
[09:02:13] [PASSED] check_quota
[09:02:13] [PASSED] check_all
[09:02:13] ===================== [PASSED] guc_idm =====================
[09:02:13] ================== no_relay (3 subtests) ===================
[09:02:13] [PASSED] xe_drops_guc2pf_if_not_ready
[09:02:13] [PASSED] xe_drops_guc2vf_if_not_ready
[09:02:13] [PASSED] xe_rejects_send_if_not_ready
[09:02:13] ==================== [PASSED] no_relay =====================
[09:02:13] ================== pf_relay (14 subtests) ==================
[09:02:13] [PASSED] pf_rejects_guc2pf_too_short
[09:02:13] [PASSED] pf_rejects_guc2pf_too_long
[09:02:13] [PASSED] pf_rejects_guc2pf_no_payload
[09:02:13] [PASSED] pf_fails_no_payload
[09:02:13] [PASSED] pf_fails_bad_origin
[09:02:13] [PASSED] pf_fails_bad_type
[09:02:13] [PASSED] pf_txn_reports_error
[09:02:13] [PASSED] pf_txn_sends_pf2guc
[09:02:13] [PASSED] pf_sends_pf2guc
[09:02:13] [SKIPPED] pf_loopback_nop
[09:02:13] [SKIPPED] pf_loopback_echo
[09:02:13] [SKIPPED] pf_loopback_fail
[09:02:13] [SKIPPED] pf_loopback_busy
[09:02:13] [SKIPPED] pf_loopback_retry
[09:02:13] ==================== [PASSED] pf_relay =====================
[09:02:13] ================== vf_relay (3 subtests) ===================
[09:02:13] [PASSED] vf_rejects_guc2vf_too_short
[09:02:13] [PASSED] vf_rejects_guc2vf_too_long
[09:02:13] [PASSED] vf_rejects_guc2vf_no_payload
[09:02:13] ==================== [PASSED] vf_relay =====================
[09:02:13] ================ pf_gt_config (6 subtests) =================
[09:02:13] [PASSED] fair_contexts_1vf
[09:02:13] [PASSED] fair_doorbells_1vf
[09:02:13] [PASSED] fair_ggtt_1vf
[09:02:13] ====================== fair_contexts ======================
[09:02:13] [PASSED] 1 VF
[09:02:13] [PASSED] 2 VFs
[09:02:13] [PASSED] 3 VFs
[09:02:13] [PASSED] 4 VFs
[09:02:13] [PASSED] 5 VFs
[09:02:13] [PASSED] 6 VFs
[09:02:13] [PASSED] 7 VFs
[09:02:13] [PASSED] 8 VFs
[09:02:13] [PASSED] 9 VFs
[09:02:13] [PASSED] 10 VFs
[09:02:13] [PASSED] 11 VFs
[09:02:13] [PASSED] 12 VFs
[09:02:13] [PASSED] 13 VFs
[09:02:13] [PASSED] 14 VFs
[09:02:13] [PASSED] 15 VFs
[09:02:13] [PASSED] 16 VFs
[09:02:13] [PASSED] 17 VFs
[09:02:13] [PASSED] 18 VFs
[09:02:13] [PASSED] 19 VFs
[09:02:13] [PASSED] 20 VFs
[09:02:13] [PASSED] 21 VFs
[09:02:13] [PASSED] 22 VFs
[09:02:13] [PASSED] 23 VFs
[09:02:13] [PASSED] 24 VFs
[09:02:13] [PASSED] 25 VFs
[09:02:13] [PASSED] 26 VFs
[09:02:13] [PASSED] 27 VFs
[09:02:13] [PASSED] 28 VFs
[09:02:13] [PASSED] 29 VFs
[09:02:13] [PASSED] 30 VFs
[09:02:13] [PASSED] 31 VFs
[09:02:13] [PASSED] 32 VFs
[09:02:13] [PASSED] 33 VFs
[09:02:13] [PASSED] 34 VFs
[09:02:13] [PASSED] 35 VFs
[09:02:13] [PASSED] 36 VFs
[09:02:13] [PASSED] 37 VFs
[09:02:13] [PASSED] 38 VFs
[09:02:13] [PASSED] 39 VFs
[09:02:13] [PASSED] 40 VFs
[09:02:13] [PASSED] 41 VFs
[09:02:13] [PASSED] 42 VFs
[09:02:13] [PASSED] 43 VFs
[09:02:13] [PASSED] 44 VFs
[09:02:13] [PASSED] 45 VFs
[09:02:13] [PASSED] 46 VFs
[09:02:13] [PASSED] 47 VFs
[09:02:13] [PASSED] 48 VFs
[09:02:13] [PASSED] 49 VFs
[09:02:13] [PASSED] 50 VFs
[09:02:13] [PASSED] 51 VFs
[09:02:13] [PASSED] 52 VFs
[09:02:13] [PASSED] 53 VFs
[09:02:13] [PASSED] 54 VFs
[09:02:13] [PASSED] 55 VFs
[09:02:13] [PASSED] 56 VFs
[09:02:13] [PASSED] 57 VFs
[09:02:13] [PASSED] 58 VFs
[09:02:13] [PASSED] 59 VFs
[09:02:13] [PASSED] 60 VFs
[09:02:13] [PASSED] 61 VFs
[09:02:13] [PASSED] 62 VFs
[09:02:13] [PASSED] 63 VFs
[09:02:13] ================== [PASSED] fair_contexts ==================
[09:02:13] ===================== fair_doorbells ======================
[09:02:13] [PASSED] 1 VF
[09:02:13] [PASSED] 2 VFs
[09:02:13] [PASSED] 3 VFs
[09:02:13] [PASSED] 4 VFs
[09:02:13] [PASSED] 5 VFs
[09:02:13] [PASSED] 6 VFs
[09:02:13] [PASSED] 7 VFs
[09:02:13] [PASSED] 8 VFs
[09:02:13] [PASSED] 9 VFs
[09:02:13] [PASSED] 10 VFs
[09:02:13] [PASSED] 11 VFs
[09:02:13] [PASSED] 12 VFs
[09:02:13] [PASSED] 13 VFs
[09:02:13] [PASSED] 14 VFs
[09:02:13] [PASSED] 15 VFs
[09:02:13] [PASSED] 16 VFs
[09:02:13] [PASSED] 17 VFs
[09:02:13] [PASSED] 18 VFs
[09:02:13] [PASSED] 19 VFs
[09:02:13] [PASSED] 20 VFs
[09:02:13] [PASSED] 21 VFs
[09:02:13] [PASSED] 22 VFs
[09:02:13] [PASSED] 23 VFs
[09:02:13] [PASSED] 24 VFs
[09:02:13] [PASSED] 25 VFs
[09:02:13] [PASSED] 26 VFs
[09:02:13] [PASSED] 27 VFs
[09:02:13] [PASSED] 28 VFs
[09:02:13] [PASSED] 29 VFs
[09:02:13] [PASSED] 30 VFs
[09:02:13] [PASSED] 31 VFs
[09:02:13] [PASSED] 32 VFs
[09:02:13] [PASSED] 33 VFs
[09:02:13] [PASSED] 34 VFs
[09:02:13] [PASSED] 35 VFs
[09:02:13] [PASSED] 36 VFs
[09:02:13] [PASSED] 37 VFs
[09:02:13] [PASSED] 38 VFs
[09:02:13] [PASSED] 39 VFs
[09:02:13] [PASSED] 40 VFs
[09:02:13] [PASSED] 41 VFs
[09:02:13] [PASSED] 42 VFs
[09:02:13] [PASSED] 43 VFs
[09:02:13] [PASSED] 44 VFs
[09:02:13] [PASSED] 45 VFs
[09:02:13] [PASSED] 46 VFs
[09:02:13] [PASSED] 47 VFs
[09:02:13] [PASSED] 48 VFs
[09:02:13] [PASSED] 49 VFs
[09:02:13] [PASSED] 50 VFs
[09:02:13] [PASSED] 51 VFs
[09:02:13] [PASSED] 52 VFs
[09:02:13] [PASSED] 53 VFs
[09:02:13] [PASSED] 54 VFs
[09:02:13] [PASSED] 55 VFs
[09:02:13] [PASSED] 56 VFs
[09:02:13] [PASSED] 57 VFs
[09:02:13] [PASSED] 58 VFs
[09:02:13] [PASSED] 59 VFs
[09:02:13] [PASSED] 60 VFs
[09:02:13] [PASSED] 61 VFs
[09:02:13] [PASSED] 62 VFs
[09:02:13] [PASSED] 63 VFs
[09:02:13] ================= [PASSED] fair_doorbells ==================
[09:02:13] ======================== fair_ggtt ========================
[09:02:13] [PASSED] 1 VF
[09:02:13] [PASSED] 2 VFs
[09:02:13] [PASSED] 3 VFs
[09:02:13] [PASSED] 4 VFs
[09:02:13] [PASSED] 5 VFs
[09:02:13] [PASSED] 6 VFs
[09:02:13] [PASSED] 7 VFs
[09:02:13] [PASSED] 8 VFs
[09:02:13] [PASSED] 9 VFs
[09:02:13] [PASSED] 10 VFs
[09:02:13] [PASSED] 11 VFs
[09:02:13] [PASSED] 12 VFs
[09:02:13] [PASSED] 13 VFs
[09:02:13] [PASSED] 14 VFs
[09:02:13] [PASSED] 15 VFs
[09:02:13] [PASSED] 16 VFs
[09:02:13] [PASSED] 17 VFs
[09:02:13] [PASSED] 18 VFs
[09:02:13] [PASSED] 19 VFs
[09:02:13] [PASSED] 20 VFs
[09:02:13] [PASSED] 21 VFs
[09:02:13] [PASSED] 22 VFs
[09:02:13] [PASSED] 23 VFs
[09:02:13] [PASSED] 24 VFs
[09:02:13] [PASSED] 25 VFs
[09:02:13] [PASSED] 26 VFs
[09:02:13] [PASSED] 27 VFs
[09:02:13] [PASSED] 28 VFs
[09:02:13] [PASSED] 29 VFs
[09:02:13] [PASSED] 30 VFs
[09:02:13] [PASSED] 31 VFs
[09:02:13] [PASSED] 32 VFs
[09:02:13] [PASSED] 33 VFs
[09:02:13] [PASSED] 34 VFs
[09:02:13] [PASSED] 35 VFs
[09:02:13] [PASSED] 36 VFs
[09:02:13] [PASSED] 37 VFs
[09:02:13] [PASSED] 38 VFs
[09:02:13] [PASSED] 39 VFs
[09:02:13] [PASSED] 40 VFs
[09:02:13] [PASSED] 41 VFs
[09:02:13] [PASSED] 42 VFs
[09:02:13] [PASSED] 43 VFs
[09:02:13] [PASSED] 44 VFs
[09:02:13] [PASSED] 45 VFs
[09:02:13] [PASSED] 46 VFs
[09:02:13] [PASSED] 47 VFs
[09:02:13] [PASSED] 48 VFs
[09:02:13] [PASSED] 49 VFs
[09:02:13] [PASSED] 50 VFs
[09:02:13] [PASSED] 51 VFs
[09:02:13] [PASSED] 52 VFs
[09:02:13] [PASSED] 53 VFs
[09:02:13] [PASSED] 54 VFs
[09:02:13] [PASSED] 55 VFs
[09:02:13] [PASSED] 56 VFs
[09:02:13] [PASSED] 57 VFs
[09:02:13] [PASSED] 58 VFs
[09:02:13] [PASSED] 59 VFs
[09:02:13] [PASSED] 60 VFs
[09:02:13] [PASSED] 61 VFs
[09:02:13] [PASSED] 62 VFs
[09:02:13] [PASSED] 63 VFs
[09:02:13] ==================== [PASSED] fair_ggtt ====================
[09:02:13] ================== [PASSED] pf_gt_config ===================
[09:02:13] ===================== lmtt (1 subtest) =====================
[09:02:13] ======================== test_ops =========================
[09:02:13] [PASSED] 2-level
[09:02:13] [PASSED] multi-level
[09:02:13] ==================== [PASSED] test_ops =====================
[09:02:13] ====================== [PASSED] lmtt =======================
[09:02:13] ================= pf_service (11 subtests) =================
[09:02:13] [PASSED] pf_negotiate_any
[09:02:13] [PASSED] pf_negotiate_base_match
[09:02:13] [PASSED] pf_negotiate_base_newer
[09:02:13] [PASSED] pf_negotiate_base_next
[09:02:13] [SKIPPED] pf_negotiate_base_older
[09:02:13] [PASSED] pf_negotiate_base_prev
[09:02:13] [PASSED] pf_negotiate_latest_match
[09:02:13] [PASSED] pf_negotiate_latest_newer
[09:02:13] [PASSED] pf_negotiate_latest_next
[09:02:13] [SKIPPED] pf_negotiate_latest_older
[09:02:13] [SKIPPED] pf_negotiate_latest_prev
[09:02:13] =================== [PASSED] pf_service ====================
[09:02:13] ================= xe_guc_g2g (2 subtests) ==================
[09:02:13] ============== xe_live_guc_g2g_kunit_default ==============
[09:02:13] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[09:02:13] ============== xe_live_guc_g2g_kunit_allmem ===============
[09:02:13] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[09:02:13] =================== [SKIPPED] xe_guc_g2g ===================
[09:02:13] =================== xe_mocs (2 subtests) ===================
[09:02:13] ================ xe_live_mocs_kernel_kunit ================
[09:02:13] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[09:02:13] ================ xe_live_mocs_reset_kunit =================
[09:02:13] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[09:02:13] ==================== [SKIPPED] xe_mocs =====================
[09:02:13] ================= xe_migrate (2 subtests) ==================
[09:02:13] ================= xe_migrate_sanity_kunit =================
[09:02:13] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[09:02:13] ================== xe_validate_ccs_kunit ==================
[09:02:13] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[09:02:13] =================== [SKIPPED] xe_migrate ===================
[09:02:13] ================== xe_dma_buf (1 subtest) ==================
[09:02:13] ==================== xe_dma_buf_kunit =====================
[09:02:13] ================ [SKIPPED] xe_dma_buf_kunit ================
[09:02:13] =================== [SKIPPED] xe_dma_buf ===================
[09:02:13] ================= xe_bo_shrink (1 subtest) =================
[09:02:13] =================== xe_bo_shrink_kunit ====================
[09:02:13] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[09:02:13] ================== [SKIPPED] xe_bo_shrink ==================
[09:02:13] ==================== xe_bo (2 subtests) ====================
[09:02:13] ================== xe_ccs_migrate_kunit ===================
[09:02:13] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[09:02:13] ==================== xe_bo_evict_kunit ====================
[09:02:13] =============== [SKIPPED] xe_bo_evict_kunit ================
[09:02:13] ===================== [SKIPPED] xe_bo ======================
[09:02:13] ==================== args (13 subtests) ====================
[09:02:13] [PASSED] count_args_test
[09:02:13] [PASSED] call_args_example
[09:02:13] [PASSED] call_args_test
[09:02:13] [PASSED] drop_first_arg_example
[09:02:13] [PASSED] drop_first_arg_test
[09:02:13] [PASSED] first_arg_example
[09:02:13] [PASSED] first_arg_test
[09:02:13] [PASSED] last_arg_example
[09:02:13] [PASSED] last_arg_test
[09:02:13] [PASSED] pick_arg_example
[09:02:13] [PASSED] if_args_example
[09:02:13] [PASSED] if_args_test
[09:02:13] [PASSED] sep_comma_example
[09:02:13] ====================== [PASSED] args =======================
[09:02:13] =================== xe_pci (3 subtests) ====================
[09:02:13] ==================== check_graphics_ip ====================
[09:02:13] [PASSED] 12.00 Xe_LP
[09:02:13] [PASSED] 12.10 Xe_LP+
[09:02:13] [PASSED] 12.55 Xe_HPG
[09:02:13] [PASSED] 12.60 Xe_HPC
[09:02:13] [PASSED] 12.70 Xe_LPG
[09:02:13] [PASSED] 12.71 Xe_LPG
[09:02:13] [PASSED] 12.74 Xe_LPG+
[09:02:13] [PASSED] 20.01 Xe2_HPG
[09:02:13] [PASSED] 20.02 Xe2_HPG
[09:02:13] [PASSED] 20.04 Xe2_LPG
[09:02:13] [PASSED] 30.00 Xe3_LPG
[09:02:13] [PASSED] 30.01 Xe3_LPG
[09:02:13] [PASSED] 30.03 Xe3_LPG
[09:02:13] [PASSED] 30.04 Xe3_LPG
[09:02:13] [PASSED] 30.05 Xe3_LPG
[09:02:13] [PASSED] 35.11 Xe3p_XPC
[09:02:13] ================ [PASSED] check_graphics_ip ================
[09:02:13] ===================== check_media_ip ======================
[09:02:13] [PASSED] 12.00 Xe_M
[09:02:13] [PASSED] 12.55 Xe_HPM
[09:02:13] [PASSED] 13.00 Xe_LPM+
[09:02:13] [PASSED] 13.01 Xe2_HPM
[09:02:13] [PASSED] 20.00 Xe2_LPM
[09:02:13] [PASSED] 30.00 Xe3_LPM
[09:02:13] [PASSED] 30.02 Xe3_LPM
[09:02:13] [PASSED] 35.00 Xe3p_LPM
[09:02:13] [PASSED] 35.03 Xe3p_HPM
[09:02:13] ================= [PASSED] check_media_ip ==================
[09:02:13] =================== check_platform_desc ===================
[09:02:13] [PASSED] 0x9A60 (TIGERLAKE)
[09:02:13] [PASSED] 0x9A68 (TIGERLAKE)
[09:02:13] [PASSED] 0x9A70 (TIGERLAKE)
[09:02:13] [PASSED] 0x9A40 (TIGERLAKE)
[09:02:13] [PASSED] 0x9A49 (TIGERLAKE)
[09:02:13] [PASSED] 0x9A59 (TIGERLAKE)
[09:02:13] [PASSED] 0x9A78 (TIGERLAKE)
[09:02:13] [PASSED] 0x9AC0 (TIGERLAKE)
[09:02:13] [PASSED] 0x9AC9 (TIGERLAKE)
[09:02:13] [PASSED] 0x9AD9 (TIGERLAKE)
[09:02:13] [PASSED] 0x9AF8 (TIGERLAKE)
[09:02:13] [PASSED] 0x4C80 (ROCKETLAKE)
[09:02:13] [PASSED] 0x4C8A (ROCKETLAKE)
[09:02:13] [PASSED] 0x4C8B (ROCKETLAKE)
[09:02:13] [PASSED] 0x4C8C (ROCKETLAKE)
[09:02:13] [PASSED] 0x4C90 (ROCKETLAKE)
[09:02:13] [PASSED] 0x4C9A (ROCKETLAKE)
[09:02:13] [PASSED] 0x4680 (ALDERLAKE_S)
[09:02:13] [PASSED] 0x4682 (ALDERLAKE_S)
[09:02:13] [PASSED] 0x4688 (ALDERLAKE_S)
[09:02:13] [PASSED] 0x468A (ALDERLAKE_S)
[09:02:13] [PASSED] 0x468B (ALDERLAKE_S)
[09:02:13] [PASSED] 0x4690 (ALDERLAKE_S)
[09:02:13] [PASSED] 0x4692 (ALDERLAKE_S)
[09:02:13] [PASSED] 0x4693 (ALDERLAKE_S)
[09:02:13] [PASSED] 0x46A0 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46A1 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46A2 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46A3 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46A6 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46A8 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46AA (ALDERLAKE_P)
[09:02:13] [PASSED] 0x462A (ALDERLAKE_P)
[09:02:13] [PASSED] 0x4626 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x4628 (ALDERLAKE_P)
stty: 'standard input': Inappropriate ioctl for device
[09:02:13] [PASSED] 0x46B0 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46B1 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46B2 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46B3 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46C0 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46C1 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46C2 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46C3 (ALDERLAKE_P)
[09:02:13] [PASSED] 0x46D0 (ALDERLAKE_N)
[09:02:13] [PASSED] 0x46D1 (ALDERLAKE_N)
[09:02:13] [PASSED] 0x46D2 (ALDERLAKE_N)
[09:02:13] [PASSED] 0x46D3 (ALDERLAKE_N)
[09:02:13] [PASSED] 0x46D4 (ALDERLAKE_N)
[09:02:13] [PASSED] 0xA721 (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7A1 (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7A9 (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7AC (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7AD (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA720 (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7A0 (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7A8 (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7AA (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA7AB (ALDERLAKE_P)
[09:02:13] [PASSED] 0xA780 (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA781 (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA782 (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA783 (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA788 (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA789 (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA78A (ALDERLAKE_S)
[09:02:13] [PASSED] 0xA78B (ALDERLAKE_S)
[09:02:13] [PASSED] 0x4905 (DG1)
[09:02:13] [PASSED] 0x4906 (DG1)
[09:02:13] [PASSED] 0x4907 (DG1)
[09:02:13] [PASSED] 0x4908 (DG1)
[09:02:13] [PASSED] 0x4909 (DG1)
[09:02:13] [PASSED] 0x56C0 (DG2)
[09:02:13] [PASSED] 0x56C2 (DG2)
[09:02:13] [PASSED] 0x56C1 (DG2)
[09:02:13] [PASSED] 0x7D51 (METEORLAKE)
[09:02:13] [PASSED] 0x7DD1 (METEORLAKE)
[09:02:13] [PASSED] 0x7D41 (METEORLAKE)
[09:02:13] [PASSED] 0x7D67 (METEORLAKE)
[09:02:13] [PASSED] 0xB640 (METEORLAKE)
[09:02:13] [PASSED] 0x56A0 (DG2)
[09:02:13] [PASSED] 0x56A1 (DG2)
[09:02:13] [PASSED] 0x56A2 (DG2)
[09:02:13] [PASSED] 0x56BE (DG2)
[09:02:13] [PASSED] 0x56BF (DG2)
[09:02:13] [PASSED] 0x5690 (DG2)
[09:02:13] [PASSED] 0x5691 (DG2)
[09:02:13] [PASSED] 0x5692 (DG2)
[09:02:13] [PASSED] 0x56A5 (DG2)
[09:02:13] [PASSED] 0x56A6 (DG2)
[09:02:13] [PASSED] 0x56B0 (DG2)
[09:02:13] [PASSED] 0x56B1 (DG2)
[09:02:13] [PASSED] 0x56BA (DG2)
[09:02:13] [PASSED] 0x56BB (DG2)
[09:02:13] [PASSED] 0x56BC (DG2)
[09:02:13] [PASSED] 0x56BD (DG2)
[09:02:13] [PASSED] 0x5693 (DG2)
[09:02:13] [PASSED] 0x5694 (DG2)
[09:02:13] [PASSED] 0x5695 (DG2)
[09:02:13] [PASSED] 0x56A3 (DG2)
[09:02:13] [PASSED] 0x56A4 (DG2)
[09:02:13] [PASSED] 0x56B2 (DG2)
[09:02:13] [PASSED] 0x56B3 (DG2)
[09:02:13] [PASSED] 0x5696 (DG2)
[09:02:13] [PASSED] 0x5697 (DG2)
[09:02:13] [PASSED] 0xB69 (PVC)
[09:02:13] [PASSED] 0xB6E (PVC)
[09:02:13] [PASSED] 0xBD4 (PVC)
[09:02:13] [PASSED] 0xBD5 (PVC)
[09:02:13] [PASSED] 0xBD6 (PVC)
[09:02:13] [PASSED] 0xBD7 (PVC)
[09:02:13] [PASSED] 0xBD8 (PVC)
[09:02:13] [PASSED] 0xBD9 (PVC)
[09:02:13] [PASSED] 0xBDA (PVC)
[09:02:13] [PASSED] 0xBDB (PVC)
[09:02:13] [PASSED] 0xBE0 (PVC)
[09:02:13] [PASSED] 0xBE1 (PVC)
[09:02:13] [PASSED] 0xBE5 (PVC)
[09:02:13] [PASSED] 0x7D40 (METEORLAKE)
[09:02:13] [PASSED] 0x7D45 (METEORLAKE)
[09:02:13] [PASSED] 0x7D55 (METEORLAKE)
[09:02:13] [PASSED] 0x7D60 (METEORLAKE)
[09:02:13] [PASSED] 0x7DD5 (METEORLAKE)
[09:02:13] [PASSED] 0x6420 (LUNARLAKE)
[09:02:13] [PASSED] 0x64A0 (LUNARLAKE)
[09:02:13] [PASSED] 0x64B0 (LUNARLAKE)
[09:02:13] [PASSED] 0xE202 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE209 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE20B (BATTLEMAGE)
[09:02:13] [PASSED] 0xE20C (BATTLEMAGE)
[09:02:13] [PASSED] 0xE20D (BATTLEMAGE)
[09:02:13] [PASSED] 0xE210 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE211 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE212 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE216 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE220 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE221 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE222 (BATTLEMAGE)
[09:02:13] [PASSED] 0xE223 (BATTLEMAGE)
[09:02:13] [PASSED] 0xB080 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB081 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB082 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB083 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB084 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB085 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB086 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB087 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB08F (PANTHERLAKE)
[09:02:13] [PASSED] 0xB090 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB0A0 (PANTHERLAKE)
[09:02:13] [PASSED] 0xB0B0 (PANTHERLAKE)
[09:02:13] [PASSED] 0xFD80 (PANTHERLAKE)
[09:02:13] [PASSED] 0xFD81 (PANTHERLAKE)
[09:02:13] [PASSED] 0xD740 (NOVALAKE_S)
[09:02:13] [PASSED] 0xD741 (NOVALAKE_S)
[09:02:13] [PASSED] 0xD742 (NOVALAKE_S)
[09:02:13] [PASSED] 0xD743 (NOVALAKE_S)
[09:02:13] [PASSED] 0xD744 (NOVALAKE_S)
[09:02:13] [PASSED] 0xD745 (NOVALAKE_S)
[09:02:13] [PASSED] 0x674C (CRESCENTISLAND)
[09:02:13] =============== [PASSED] check_platform_desc ===============
[09:02:13] ===================== [PASSED] xe_pci ======================
[09:02:13] =================== xe_rtp (2 subtests) ====================
[09:02:13] =============== xe_rtp_process_to_sr_tests ================
[09:02:13] [PASSED] coalesce-same-reg
[09:02:13] [PASSED] no-match-no-add
[09:02:13] [PASSED] match-or
[09:02:13] [PASSED] match-or-xfail
[09:02:13] [PASSED] no-match-no-add-multiple-rules
[09:02:13] [PASSED] two-regs-two-entries
[09:02:13] [PASSED] clr-one-set-other
[09:02:13] [PASSED] set-field
[09:02:13] [PASSED] conflict-duplicate
[09:02:13] [PASSED] conflict-not-disjoint
[09:02:13] [PASSED] conflict-reg-type
[09:02:13] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[09:02:13] ================== xe_rtp_process_tests ===================
[09:02:13] [PASSED] active1
[09:02:13] [PASSED] active2
[09:02:13] [PASSED] active-inactive
[09:02:13] [PASSED] inactive-active
[09:02:13] [PASSED] inactive-1st_or_active-inactive
[09:02:13] [PASSED] inactive-2nd_or_active-inactive
[09:02:13] [PASSED] inactive-last_or_active-inactive
[09:02:13] [PASSED] inactive-no_or_active-inactive
[09:02:13] ============== [PASSED] xe_rtp_process_tests ===============
[09:02:13] ===================== [PASSED] xe_rtp ======================
[09:02:13] ==================== xe_wa (1 subtest) =====================
[09:02:13] ======================== xe_wa_gt =========================
[09:02:13] [PASSED] TIGERLAKE B0
[09:02:13] [PASSED] DG1 A0
[09:02:13] [PASSED] DG1 B0
[09:02:13] [PASSED] ALDERLAKE_S A0
[09:02:13] [PASSED] ALDERLAKE_S B0
[09:02:13] [PASSED] ALDERLAKE_S C0
[09:02:13] [PASSED] ALDERLAKE_S D0
[09:02:13] [PASSED] ALDERLAKE_P A0
[09:02:13] [PASSED] ALDERLAKE_P B0
[09:02:13] [PASSED] ALDERLAKE_P C0
[09:02:13] [PASSED] ALDERLAKE_S RPLS D0
[09:02:13] [PASSED] ALDERLAKE_P RPLU E0
[09:02:13] [PASSED] DG2 G10 C0
[09:02:13] [PASSED] DG2 G11 B1
[09:02:13] [PASSED] DG2 G12 A1
[09:02:13] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:02:13] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:02:13] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[09:02:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[09:02:13] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[09:02:13] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[09:02:13] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[09:02:13] ==================== [PASSED] xe_wa_gt =====================
[09:02:13] ====================== [PASSED] xe_wa ======================
[09:02:13] ============================================================
[09:02:13] Testing complete. Ran 512 tests: passed: 494, skipped: 18
[09:02:13] Elapsed time: 36.275s total, 4.207s configuring, 31.551s building, 0.463s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[09:02:13] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:02:15] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:02:40] Starting KUnit Kernel (1/1)...
[09:02:40] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:02:41] ============ drm_test_pick_cmdline (2 subtests) ============
[09:02:41] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[09:02:41] =============== drm_test_pick_cmdline_named ===============
[09:02:41] [PASSED] NTSC
[09:02:41] [PASSED] NTSC-J
[09:02:41] [PASSED] PAL
[09:02:41] [PASSED] PAL-M
[09:02:41] =========== [PASSED] drm_test_pick_cmdline_named ===========
[09:02:41] ============== [PASSED] drm_test_pick_cmdline ==============
[09:02:41] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[09:02:41] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[09:02:41] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[09:02:41] =========== drm_validate_clone_mode (2 subtests) ===========
[09:02:41] ============== drm_test_check_in_clone_mode ===============
[09:02:41] [PASSED] in_clone_mode
[09:02:41] [PASSED] not_in_clone_mode
[09:02:41] ========== [PASSED] drm_test_check_in_clone_mode ===========
[09:02:41] =============== drm_test_check_valid_clones ===============
[09:02:41] [PASSED] not_in_clone_mode
[09:02:41] [PASSED] valid_clone
[09:02:41] [PASSED] invalid_clone
[09:02:41] =========== [PASSED] drm_test_check_valid_clones ===========
[09:02:41] ============= [PASSED] drm_validate_clone_mode =============
[09:02:41] ============= drm_validate_modeset (1 subtest) =============
[09:02:41] [PASSED] drm_test_check_connector_changed_modeset
[09:02:41] ============== [PASSED] drm_validate_modeset ===============
[09:02:41] ====== drm_test_bridge_get_current_state (2 subtests) ======
[09:02:41] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[09:02:41] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[09:02:41] ======== [PASSED] drm_test_bridge_get_current_state ========
[09:02:41] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[09:02:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[09:02:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[09:02:41] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[09:02:41] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[09:02:41] ============== drm_bridge_alloc (2 subtests) ===============
[09:02:41] [PASSED] drm_test_drm_bridge_alloc_basic
[09:02:41] [PASSED] drm_test_drm_bridge_alloc_get_put
[09:02:41] ================ [PASSED] drm_bridge_alloc =================
[09:02:41] ================== drm_buddy (8 subtests) ==================
[09:02:41] [PASSED] drm_test_buddy_alloc_limit
[09:02:41] [PASSED] drm_test_buddy_alloc_optimistic
[09:02:41] [PASSED] drm_test_buddy_alloc_pessimistic
[09:02:41] [PASSED] drm_test_buddy_alloc_pathological
[09:02:41] [PASSED] drm_test_buddy_alloc_contiguous
[09:02:41] [PASSED] drm_test_buddy_alloc_clear
[09:02:41] [PASSED] drm_test_buddy_alloc_range_bias
[09:02:41] [PASSED] drm_test_buddy_fragmentation_performance
[09:02:41] ==================== [PASSED] drm_buddy ====================
[09:02:41] ============= drm_cmdline_parser (40 subtests) =============
[09:02:41] [PASSED] drm_test_cmdline_force_d_only
[09:02:41] [PASSED] drm_test_cmdline_force_D_only_dvi
[09:02:41] [PASSED] drm_test_cmdline_force_D_only_hdmi
[09:02:41] [PASSED] drm_test_cmdline_force_D_only_not_digital
[09:02:41] [PASSED] drm_test_cmdline_force_e_only
[09:02:41] [PASSED] drm_test_cmdline_res
[09:02:41] [PASSED] drm_test_cmdline_res_vesa
[09:02:41] [PASSED] drm_test_cmdline_res_vesa_rblank
[09:02:41] [PASSED] drm_test_cmdline_res_rblank
[09:02:41] [PASSED] drm_test_cmdline_res_bpp
[09:02:41] [PASSED] drm_test_cmdline_res_refresh
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[09:02:41] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[09:02:41] [PASSED] drm_test_cmdline_res_margins_force_on
[09:02:41] [PASSED] drm_test_cmdline_res_vesa_margins
[09:02:41] [PASSED] drm_test_cmdline_name
[09:02:41] [PASSED] drm_test_cmdline_name_bpp
[09:02:41] [PASSED] drm_test_cmdline_name_option
[09:02:41] [PASSED] drm_test_cmdline_name_bpp_option
[09:02:41] [PASSED] drm_test_cmdline_rotate_0
[09:02:41] [PASSED] drm_test_cmdline_rotate_90
[09:02:41] [PASSED] drm_test_cmdline_rotate_180
[09:02:41] [PASSED] drm_test_cmdline_rotate_270
[09:02:41] [PASSED] drm_test_cmdline_hmirror
[09:02:41] [PASSED] drm_test_cmdline_vmirror
[09:02:41] [PASSED] drm_test_cmdline_margin_options
[09:02:41] [PASSED] drm_test_cmdline_multiple_options
[09:02:41] [PASSED] drm_test_cmdline_bpp_extra_and_option
[09:02:41] [PASSED] drm_test_cmdline_extra_and_option
[09:02:41] [PASSED] drm_test_cmdline_freestanding_options
[09:02:41] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[09:02:41] [PASSED] drm_test_cmdline_panel_orientation
[09:02:41] ================ drm_test_cmdline_invalid =================
[09:02:41] [PASSED] margin_only
[09:02:41] [PASSED] interlace_only
[09:02:41] [PASSED] res_missing_x
[09:02:41] [PASSED] res_missing_y
[09:02:41] [PASSED] res_bad_y
[09:02:41] [PASSED] res_missing_y_bpp
[09:02:41] [PASSED] res_bad_bpp
[09:02:41] [PASSED] res_bad_refresh
[09:02:41] [PASSED] res_bpp_refresh_force_on_off
[09:02:41] [PASSED] res_invalid_mode
[09:02:41] [PASSED] res_bpp_wrong_place_mode
[09:02:41] [PASSED] name_bpp_refresh
[09:02:41] [PASSED] name_refresh
[09:02:41] [PASSED] name_refresh_wrong_mode
[09:02:41] [PASSED] name_refresh_invalid_mode
[09:02:41] [PASSED] rotate_multiple
[09:02:41] [PASSED] rotate_invalid_val
[09:02:41] [PASSED] rotate_truncated
[09:02:41] [PASSED] invalid_option
[09:02:41] [PASSED] invalid_tv_option
[09:02:41] [PASSED] truncated_tv_option
[09:02:41] ============ [PASSED] drm_test_cmdline_invalid =============
[09:02:41] =============== drm_test_cmdline_tv_options ===============
[09:02:41] [PASSED] NTSC
[09:02:41] [PASSED] NTSC_443
[09:02:41] [PASSED] NTSC_J
[09:02:41] [PASSED] PAL
[09:02:41] [PASSED] PAL_M
[09:02:41] [PASSED] PAL_N
[09:02:41] [PASSED] SECAM
[09:02:41] [PASSED] MONO_525
[09:02:41] [PASSED] MONO_625
[09:02:41] =========== [PASSED] drm_test_cmdline_tv_options ===========
[09:02:41] =============== [PASSED] drm_cmdline_parser ================
[09:02:41] ========== drmm_connector_hdmi_init (20 subtests) ==========
[09:02:41] [PASSED] drm_test_connector_hdmi_init_valid
[09:02:41] [PASSED] drm_test_connector_hdmi_init_bpc_8
[09:02:41] [PASSED] drm_test_connector_hdmi_init_bpc_10
[09:02:41] [PASSED] drm_test_connector_hdmi_init_bpc_12
[09:02:41] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[09:02:41] [PASSED] drm_test_connector_hdmi_init_bpc_null
[09:02:41] [PASSED] drm_test_connector_hdmi_init_formats_empty
[09:02:41] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[09:02:41] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:02:41] [PASSED] supported_formats=0x9 yuv420_allowed=1
[09:02:41] [PASSED] supported_formats=0x9 yuv420_allowed=0
[09:02:41] [PASSED] supported_formats=0x3 yuv420_allowed=1
[09:02:41] [PASSED] supported_formats=0x3 yuv420_allowed=0
[09:02:41] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:02:41] [PASSED] drm_test_connector_hdmi_init_null_ddc
[09:02:41] [PASSED] drm_test_connector_hdmi_init_null_product
[09:02:41] [PASSED] drm_test_connector_hdmi_init_null_vendor
[09:02:41] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[09:02:41] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[09:02:41] [PASSED] drm_test_connector_hdmi_init_product_valid
[09:02:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[09:02:41] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[09:02:41] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[09:02:41] ========= drm_test_connector_hdmi_init_type_valid =========
[09:02:41] [PASSED] HDMI-A
[09:02:41] [PASSED] HDMI-B
[09:02:41] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[09:02:41] ======== drm_test_connector_hdmi_init_type_invalid ========
[09:02:41] [PASSED] Unknown
[09:02:41] [PASSED] VGA
[09:02:41] [PASSED] DVI-I
[09:02:41] [PASSED] DVI-D
[09:02:41] [PASSED] DVI-A
[09:02:41] [PASSED] Composite
[09:02:41] [PASSED] SVIDEO
[09:02:41] [PASSED] LVDS
[09:02:41] [PASSED] Component
[09:02:41] [PASSED] DIN
[09:02:41] [PASSED] DP
[09:02:41] [PASSED] TV
[09:02:41] [PASSED] eDP
[09:02:41] [PASSED] Virtual
[09:02:41] [PASSED] DSI
[09:02:41] [PASSED] DPI
[09:02:41] [PASSED] Writeback
[09:02:41] [PASSED] SPI
[09:02:41] [PASSED] USB
[09:02:41] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[09:02:41] ============ [PASSED] drmm_connector_hdmi_init =============
[09:02:41] ============= drmm_connector_init (3 subtests) =============
[09:02:41] [PASSED] drm_test_drmm_connector_init
[09:02:41] [PASSED] drm_test_drmm_connector_init_null_ddc
[09:02:41] ========= drm_test_drmm_connector_init_type_valid =========
[09:02:41] [PASSED] Unknown
[09:02:41] [PASSED] VGA
[09:02:41] [PASSED] DVI-I
[09:02:41] [PASSED] DVI-D
[09:02:41] [PASSED] DVI-A
[09:02:41] [PASSED] Composite
[09:02:41] [PASSED] SVIDEO
[09:02:41] [PASSED] LVDS
[09:02:41] [PASSED] Component
[09:02:41] [PASSED] DIN
[09:02:41] [PASSED] DP
[09:02:41] [PASSED] HDMI-A
[09:02:41] [PASSED] HDMI-B
[09:02:41] [PASSED] TV
[09:02:41] [PASSED] eDP
[09:02:41] [PASSED] Virtual
[09:02:41] [PASSED] DSI
[09:02:41] [PASSED] DPI
[09:02:41] [PASSED] Writeback
[09:02:41] [PASSED] SPI
[09:02:41] [PASSED] USB
[09:02:41] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[09:02:41] =============== [PASSED] drmm_connector_init ===============
[09:02:41] ========= drm_connector_dynamic_init (6 subtests) ==========
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_init
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_init_properties
[09:02:41] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[09:02:41] [PASSED] Unknown
[09:02:41] [PASSED] VGA
[09:02:41] [PASSED] DVI-I
[09:02:41] [PASSED] DVI-D
[09:02:41] [PASSED] DVI-A
[09:02:41] [PASSED] Composite
[09:02:41] [PASSED] SVIDEO
[09:02:41] [PASSED] LVDS
[09:02:41] [PASSED] Component
[09:02:41] [PASSED] DIN
[09:02:41] [PASSED] DP
[09:02:41] [PASSED] HDMI-A
[09:02:41] [PASSED] HDMI-B
[09:02:41] [PASSED] TV
[09:02:41] [PASSED] eDP
[09:02:41] [PASSED] Virtual
[09:02:41] [PASSED] DSI
[09:02:41] [PASSED] DPI
[09:02:41] [PASSED] Writeback
[09:02:41] [PASSED] SPI
[09:02:41] [PASSED] USB
[09:02:41] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[09:02:41] ======== drm_test_drm_connector_dynamic_init_name =========
[09:02:41] [PASSED] Unknown
[09:02:41] [PASSED] VGA
[09:02:41] [PASSED] DVI-I
[09:02:41] [PASSED] DVI-D
[09:02:41] [PASSED] DVI-A
[09:02:41] [PASSED] Composite
[09:02:41] [PASSED] SVIDEO
[09:02:41] [PASSED] LVDS
[09:02:41] [PASSED] Component
[09:02:41] [PASSED] DIN
[09:02:41] [PASSED] DP
[09:02:41] [PASSED] HDMI-A
[09:02:41] [PASSED] HDMI-B
[09:02:41] [PASSED] TV
[09:02:41] [PASSED] eDP
[09:02:41] [PASSED] Virtual
[09:02:41] [PASSED] DSI
[09:02:41] [PASSED] DPI
[09:02:41] [PASSED] Writeback
[09:02:41] [PASSED] SPI
[09:02:41] [PASSED] USB
[09:02:41] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[09:02:41] =========== [PASSED] drm_connector_dynamic_init ============
[09:02:41] ==== drm_connector_dynamic_register_early (4 subtests) =====
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[09:02:41] ====== [PASSED] drm_connector_dynamic_register_early =======
[09:02:41] ======= drm_connector_dynamic_register (7 subtests) ========
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[09:02:41] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[09:02:41] ========= [PASSED] drm_connector_dynamic_register ==========
[09:02:41] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[09:02:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[09:02:41] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[09:02:41] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[09:02:41] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[09:02:41] ========== drm_test_get_tv_mode_from_name_valid ===========
[09:02:41] [PASSED] NTSC
[09:02:41] [PASSED] NTSC-443
[09:02:41] [PASSED] NTSC-J
[09:02:41] [PASSED] PAL
[09:02:41] [PASSED] PAL-M
[09:02:41] [PASSED] PAL-N
[09:02:41] [PASSED] SECAM
[09:02:41] [PASSED] Mono
[09:02:41] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[09:02:41] [PASSED] drm_test_get_tv_mode_from_name_truncated
[09:02:41] ============ [PASSED] drm_get_tv_mode_from_name ============
[09:02:41] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[09:02:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[09:02:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[09:02:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[09:02:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[09:02:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[09:02:41] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[09:02:41] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[09:02:41] [PASSED] VIC 96
[09:02:41] [PASSED] VIC 97
[09:02:41] [PASSED] VIC 101
[09:02:41] [PASSED] VIC 102
[09:02:41] [PASSED] VIC 106
[09:02:41] [PASSED] VIC 107
[09:02:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[09:02:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[09:02:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[09:02:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[09:02:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[09:02:41] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[09:02:41] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[09:02:41] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[09:02:41] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[09:02:41] [PASSED] Automatic
[09:02:41] [PASSED] Full
[09:02:41] [PASSED] Limited 16:235
[09:02:41] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[09:02:41] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[09:02:41] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[09:02:41] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[09:02:41] === drm_test_drm_hdmi_connector_get_output_format_name ====
[09:02:41] [PASSED] RGB
[09:02:41] [PASSED] YUV 4:2:0
[09:02:41] [PASSED] YUV 4:2:2
[09:02:41] [PASSED] YUV 4:4:4
[09:02:41] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[09:02:41] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[09:02:41] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[09:02:41] ============= drm_damage_helper (21 subtests) ==============
[09:02:41] [PASSED] drm_test_damage_iter_no_damage
[09:02:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[09:02:41] [PASSED] drm_test_damage_iter_no_damage_src_moved
[09:02:41] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[09:02:41] [PASSED] drm_test_damage_iter_no_damage_not_visible
[09:02:41] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[09:02:41] [PASSED] drm_test_damage_iter_no_damage_no_fb
[09:02:41] [PASSED] drm_test_damage_iter_simple_damage
[09:02:41] [PASSED] drm_test_damage_iter_single_damage
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_outside_src
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_src_moved
[09:02:41] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[09:02:41] [PASSED] drm_test_damage_iter_damage
[09:02:41] [PASSED] drm_test_damage_iter_damage_one_intersect
[09:02:41] [PASSED] drm_test_damage_iter_damage_one_outside
[09:02:41] [PASSED] drm_test_damage_iter_damage_src_moved
[09:02:41] [PASSED] drm_test_damage_iter_damage_not_visible
[09:02:41] ================ [PASSED] drm_damage_helper ================
[09:02:41] ============== drm_dp_mst_helper (3 subtests) ==============
[09:02:41] ============== drm_test_dp_mst_calc_pbn_mode ==============
[09:02:41] [PASSED] Clock 154000 BPP 30 DSC disabled
[09:02:41] [PASSED] Clock 234000 BPP 30 DSC disabled
[09:02:41] [PASSED] Clock 297000 BPP 24 DSC disabled
[09:02:41] [PASSED] Clock 332880 BPP 24 DSC enabled
[09:02:41] [PASSED] Clock 324540 BPP 24 DSC enabled
[09:02:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[09:02:41] ============== drm_test_dp_mst_calc_pbn_div ===============
[09:02:41] [PASSED] Link rate 2000000 lane count 4
[09:02:41] [PASSED] Link rate 2000000 lane count 2
[09:02:41] [PASSED] Link rate 2000000 lane count 1
[09:02:41] [PASSED] Link rate 1350000 lane count 4
[09:02:41] [PASSED] Link rate 1350000 lane count 2
[09:02:41] [PASSED] Link rate 1350000 lane count 1
[09:02:41] [PASSED] Link rate 1000000 lane count 4
[09:02:41] [PASSED] Link rate 1000000 lane count 2
[09:02:41] [PASSED] Link rate 1000000 lane count 1
[09:02:41] [PASSED] Link rate 810000 lane count 4
[09:02:41] [PASSED] Link rate 810000 lane count 2
[09:02:41] [PASSED] Link rate 810000 lane count 1
[09:02:41] [PASSED] Link rate 540000 lane count 4
[09:02:41] [PASSED] Link rate 540000 lane count 2
[09:02:41] [PASSED] Link rate 540000 lane count 1
[09:02:41] [PASSED] Link rate 270000 lane count 4
[09:02:41] [PASSED] Link rate 270000 lane count 2
[09:02:41] [PASSED] Link rate 270000 lane count 1
[09:02:41] [PASSED] Link rate 162000 lane count 4
[09:02:41] [PASSED] Link rate 162000 lane count 2
[09:02:41] [PASSED] Link rate 162000 lane count 1
[09:02:41] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[09:02:41] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[09:02:41] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[09:02:41] [PASSED] DP_POWER_UP_PHY with port number
[09:02:41] [PASSED] DP_POWER_DOWN_PHY with port number
[09:02:41] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[09:02:41] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[09:02:41] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[09:02:41] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[09:02:41] [PASSED] DP_QUERY_PAYLOAD with port number
[09:02:41] [PASSED] DP_QUERY_PAYLOAD with VCPI
[09:02:41] [PASSED] DP_REMOTE_DPCD_READ with port number
[09:02:41] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[09:02:41] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[09:02:41] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[09:02:41] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[09:02:41] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[09:02:41] [PASSED] DP_REMOTE_I2C_READ with port number
[09:02:41] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[09:02:41] [PASSED] DP_REMOTE_I2C_READ with transactions array
[09:02:41] [PASSED] DP_REMOTE_I2C_WRITE with port number
[09:02:41] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[09:02:41] [PASSED] DP_REMOTE_I2C_WRITE with data array
[09:02:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[09:02:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[09:02:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[09:02:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[09:02:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[09:02:41] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[09:02:41] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[09:02:41] ================ [PASSED] drm_dp_mst_helper ================
[09:02:41] ================== drm_exec (7 subtests) ===================
[09:02:41] [PASSED] sanitycheck
[09:02:41] [PASSED] test_lock
[09:02:41] [PASSED] test_lock_unlock
[09:02:41] [PASSED] test_duplicates
[09:02:41] [PASSED] test_prepare
[09:02:41] [PASSED] test_prepare_array
[09:02:41] [PASSED] test_multiple_loops
[09:02:41] ==================== [PASSED] drm_exec =====================
[09:02:41] =========== drm_format_helper_test (17 subtests) ===========
[09:02:41] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[09:02:41] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[09:02:41] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[09:02:41] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[09:02:41] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[09:02:41] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[09:02:41] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[09:02:41] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[09:02:41] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[09:02:41] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[09:02:41] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[09:02:41] ============== drm_test_fb_xrgb8888_to_mono ===============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[09:02:41] ==================== drm_test_fb_swab =====================
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ================ [PASSED] drm_test_fb_swab =================
[09:02:41] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[09:02:41] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[09:02:41] [PASSED] single_pixel_source_buffer
[09:02:41] [PASSED] single_pixel_clip_rectangle
[09:02:41] [PASSED] well_known_colors
[09:02:41] [PASSED] destination_pitch
[09:02:41] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[09:02:41] ================= drm_test_fb_clip_offset =================
[09:02:41] [PASSED] pass through
[09:02:41] [PASSED] horizontal offset
[09:02:41] [PASSED] vertical offset
[09:02:41] [PASSED] horizontal and vertical offset
[09:02:41] [PASSED] horizontal offset (custom pitch)
[09:02:41] [PASSED] vertical offset (custom pitch)
[09:02:41] [PASSED] horizontal and vertical offset (custom pitch)
[09:02:41] ============= [PASSED] drm_test_fb_clip_offset =============
[09:02:41] =================== drm_test_fb_memcpy ====================
[09:02:41] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[09:02:41] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[09:02:41] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[09:02:41] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[09:02:41] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[09:02:41] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[09:02:41] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[09:02:41] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[09:02:41] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[09:02:41] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[09:02:41] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[09:02:41] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[09:02:41] =============== [PASSED] drm_test_fb_memcpy ================
[09:02:41] ============= [PASSED] drm_format_helper_test ==============
[09:02:41] ================= drm_format (18 subtests) =================
[09:02:41] [PASSED] drm_test_format_block_width_invalid
[09:02:41] [PASSED] drm_test_format_block_width_one_plane
[09:02:41] [PASSED] drm_test_format_block_width_two_plane
[09:02:41] [PASSED] drm_test_format_block_width_three_plane
[09:02:41] [PASSED] drm_test_format_block_width_tiled
[09:02:41] [PASSED] drm_test_format_block_height_invalid
[09:02:41] [PASSED] drm_test_format_block_height_one_plane
[09:02:41] [PASSED] drm_test_format_block_height_two_plane
[09:02:41] [PASSED] drm_test_format_block_height_three_plane
[09:02:41] [PASSED] drm_test_format_block_height_tiled
[09:02:41] [PASSED] drm_test_format_min_pitch_invalid
[09:02:41] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[09:02:41] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[09:02:41] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[09:02:41] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[09:02:41] [PASSED] drm_test_format_min_pitch_two_plane
[09:02:41] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[09:02:41] [PASSED] drm_test_format_min_pitch_tiled
[09:02:41] =================== [PASSED] drm_format ====================
[09:02:41] ============== drm_framebuffer (10 subtests) ===============
[09:02:41] ========== drm_test_framebuffer_check_src_coords ==========
[09:02:41] [PASSED] Success: source fits into fb
[09:02:41] [PASSED] Fail: overflowing fb with x-axis coordinate
[09:02:41] [PASSED] Fail: overflowing fb with y-axis coordinate
[09:02:41] [PASSED] Fail: overflowing fb with source width
[09:02:41] [PASSED] Fail: overflowing fb with source height
[09:02:41] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[09:02:41] [PASSED] drm_test_framebuffer_cleanup
[09:02:41] =============== drm_test_framebuffer_create ===============
[09:02:41] [PASSED] ABGR8888 normal sizes
[09:02:41] [PASSED] ABGR8888 max sizes
[09:02:41] [PASSED] ABGR8888 pitch greater than min required
[09:02:41] [PASSED] ABGR8888 pitch less than min required
[09:02:41] [PASSED] ABGR8888 Invalid width
[09:02:41] [PASSED] ABGR8888 Invalid buffer handle
[09:02:41] [PASSED] No pixel format
[09:02:41] [PASSED] ABGR8888 Width 0
[09:02:41] [PASSED] ABGR8888 Height 0
[09:02:41] [PASSED] ABGR8888 Out of bound height * pitch combination
[09:02:41] [PASSED] ABGR8888 Large buffer offset
[09:02:41] [PASSED] ABGR8888 Buffer offset for inexistent plane
[09:02:41] [PASSED] ABGR8888 Invalid flag
[09:02:41] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[09:02:41] [PASSED] ABGR8888 Valid buffer modifier
[09:02:41] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[09:02:41] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] NV12 Normal sizes
[09:02:41] [PASSED] NV12 Max sizes
[09:02:41] [PASSED] NV12 Invalid pitch
[09:02:41] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[09:02:41] [PASSED] NV12 different modifier per-plane
[09:02:41] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[09:02:41] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] NV12 Modifier for inexistent plane
[09:02:41] [PASSED] NV12 Handle for inexistent plane
[09:02:41] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[09:02:41] [PASSED] YVU420 Normal sizes
[09:02:41] [PASSED] YVU420 Max sizes
[09:02:41] [PASSED] YVU420 Invalid pitch
[09:02:41] [PASSED] YVU420 Different pitches
[09:02:41] [PASSED] YVU420 Different buffer offsets/pitches
[09:02:41] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[09:02:41] [PASSED] YVU420 Valid modifier
[09:02:41] [PASSED] YVU420 Different modifiers per plane
[09:02:41] [PASSED] YVU420 Modifier for inexistent plane
[09:02:41] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[09:02:41] [PASSED] X0L2 Normal sizes
[09:02:41] [PASSED] X0L2 Max sizes
[09:02:41] [PASSED] X0L2 Invalid pitch
[09:02:41] [PASSED] X0L2 Pitch greater than minimum required
[09:02:41] [PASSED] X0L2 Handle for inexistent plane
[09:02:41] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[09:02:41] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[09:02:41] [PASSED] X0L2 Valid modifier
[09:02:41] [PASSED] X0L2 Modifier for inexistent plane
[09:02:41] =========== [PASSED] drm_test_framebuffer_create ===========
[09:02:41] [PASSED] drm_test_framebuffer_free
[09:02:41] [PASSED] drm_test_framebuffer_init
[09:02:41] [PASSED] drm_test_framebuffer_init_bad_format
[09:02:41] [PASSED] drm_test_framebuffer_init_dev_mismatch
[09:02:41] [PASSED] drm_test_framebuffer_lookup
[09:02:41] [PASSED] drm_test_framebuffer_lookup_inexistent
[09:02:41] [PASSED] drm_test_framebuffer_modifiers_not_supported
[09:02:41] ================= [PASSED] drm_framebuffer =================
[09:02:41] ================ drm_gem_shmem (8 subtests) ================
[09:02:41] [PASSED] drm_gem_shmem_test_obj_create
[09:02:41] [PASSED] drm_gem_shmem_test_obj_create_private
[09:02:41] [PASSED] drm_gem_shmem_test_pin_pages
[09:02:41] [PASSED] drm_gem_shmem_test_vmap
[09:02:41] [PASSED] drm_gem_shmem_test_get_sg_table
[09:02:41] [PASSED] drm_gem_shmem_test_get_pages_sgt
[09:02:41] [PASSED] drm_gem_shmem_test_madvise
[09:02:41] [PASSED] drm_gem_shmem_test_purge
[09:02:41] ================== [PASSED] drm_gem_shmem ==================
[09:02:41] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[09:02:41] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[09:02:41] [PASSED] Automatic
[09:02:41] [PASSED] Full
[09:02:41] [PASSED] Limited 16:235
[09:02:41] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[09:02:41] [PASSED] drm_test_check_disable_connector
[09:02:41] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[09:02:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[09:02:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[09:02:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[09:02:41] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[09:02:41] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[09:02:41] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[09:02:41] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[09:02:41] [PASSED] drm_test_check_output_bpc_dvi
[09:02:41] [PASSED] drm_test_check_output_bpc_format_vic_1
[09:02:41] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[09:02:41] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[09:02:41] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[09:02:41] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[09:02:41] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[09:02:41] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[09:02:41] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[09:02:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[09:02:41] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[09:02:41] [PASSED] drm_test_check_broadcast_rgb_value
[09:02:41] [PASSED] drm_test_check_bpc_8_value
[09:02:41] [PASSED] drm_test_check_bpc_10_value
[09:02:41] [PASSED] drm_test_check_bpc_12_value
[09:02:41] [PASSED] drm_test_check_format_value
[09:02:41] [PASSED] drm_test_check_tmds_char_value
[09:02:41] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[09:02:41] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[09:02:41] [PASSED] drm_test_check_mode_valid
[09:02:41] [PASSED] drm_test_check_mode_valid_reject
[09:02:41] [PASSED] drm_test_check_mode_valid_reject_rate
[09:02:41] [PASSED] drm_test_check_mode_valid_reject_max_clock
[09:02:41] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[09:02:41] ================= drm_managed (2 subtests) =================
[09:02:41] [PASSED] drm_test_managed_release_action
[09:02:41] [PASSED] drm_test_managed_run_action
[09:02:41] =================== [PASSED] drm_managed ===================
[09:02:41] =================== drm_mm (6 subtests) ====================
[09:02:41] [PASSED] drm_test_mm_init
[09:02:41] [PASSED] drm_test_mm_debug
[09:02:41] [PASSED] drm_test_mm_align32
[09:02:41] [PASSED] drm_test_mm_align64
[09:02:41] [PASSED] drm_test_mm_lowest
[09:02:41] [PASSED] drm_test_mm_highest
[09:02:41] ===================== [PASSED] drm_mm ======================
[09:02:41] ============= drm_modes_analog_tv (5 subtests) =============
[09:02:41] [PASSED] drm_test_modes_analog_tv_mono_576i
[09:02:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[09:02:41] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[09:02:41] [PASSED] drm_test_modes_analog_tv_pal_576i
[09:02:41] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[09:02:41] =============== [PASSED] drm_modes_analog_tv ===============
[09:02:41] ============== drm_plane_helper (2 subtests) ===============
[09:02:41] =============== drm_test_check_plane_state ================
[09:02:41] [PASSED] clipping_simple
[09:02:41] [PASSED] clipping_rotate_reflect
[09:02:41] [PASSED] positioning_simple
[09:02:41] [PASSED] upscaling
[09:02:41] [PASSED] downscaling
[09:02:41] [PASSED] rounding1
[09:02:41] [PASSED] rounding2
[09:02:41] [PASSED] rounding3
[09:02:41] [PASSED] rounding4
[09:02:41] =========== [PASSED] drm_test_check_plane_state ============
[09:02:41] =========== drm_test_check_invalid_plane_state ============
[09:02:41] [PASSED] positioning_invalid
[09:02:41] [PASSED] upscaling_invalid
[09:02:41] [PASSED] downscaling_invalid
[09:02:41] ======= [PASSED] drm_test_check_invalid_plane_state ========
[09:02:41] ================ [PASSED] drm_plane_helper =================
[09:02:41] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[09:02:41] ====== drm_test_connector_helper_tv_get_modes_check =======
[09:02:41] [PASSED] None
[09:02:41] [PASSED] PAL
[09:02:41] [PASSED] NTSC
[09:02:41] [PASSED] Both, NTSC Default
[09:02:41] [PASSED] Both, PAL Default
[09:02:41] [PASSED] Both, NTSC Default, with PAL on command-line
[09:02:41] [PASSED] Both, PAL Default, with NTSC on command-line
[09:02:41] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[09:02:41] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[09:02:41] ================== drm_rect (9 subtests) ===================
[09:02:41] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[09:02:41] [PASSED] drm_test_rect_clip_scaled_not_clipped
[09:02:41] [PASSED] drm_test_rect_clip_scaled_clipped
[09:02:41] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[09:02:41] ================= drm_test_rect_intersect =================
[09:02:41] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[09:02:41] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[09:02:41] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[09:02:41] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[09:02:41] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[09:02:41] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[09:02:41] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[09:02:41] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[09:02:41] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[09:02:41] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[09:02:41] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[09:02:41] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[09:02:41] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[09:02:41] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[09:02:41] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[09:02:41] ============= [PASSED] drm_test_rect_intersect =============
[09:02:41] ================ drm_test_rect_calc_hscale ================
[09:02:41] [PASSED] normal use
[09:02:41] [PASSED] out of max range
[09:02:41] [PASSED] out of min range
[09:02:41] [PASSED] zero dst
[09:02:41] [PASSED] negative src
[09:02:41] [PASSED] negative dst
[09:02:41] ============ [PASSED] drm_test_rect_calc_hscale ============
[09:02:41] ================ drm_test_rect_calc_vscale ================
[09:02:41] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[09:02:41] [PASSED] out of max range
[09:02:41] [PASSED] out of min range
[09:02:41] [PASSED] zero dst
[09:02:41] [PASSED] negative src
[09:02:41] [PASSED] negative dst
[09:02:41] ============ [PASSED] drm_test_rect_calc_vscale ============
[09:02:41] ================== drm_test_rect_rotate ===================
[09:02:41] [PASSED] reflect-x
[09:02:41] [PASSED] reflect-y
[09:02:41] [PASSED] rotate-0
[09:02:41] [PASSED] rotate-90
[09:02:41] [PASSED] rotate-180
[09:02:41] [PASSED] rotate-270
[09:02:41] ============== [PASSED] drm_test_rect_rotate ===============
[09:02:41] ================ drm_test_rect_rotate_inv =================
[09:02:41] [PASSED] reflect-x
[09:02:41] [PASSED] reflect-y
[09:02:41] [PASSED] rotate-0
[09:02:41] [PASSED] rotate-90
[09:02:41] [PASSED] rotate-180
[09:02:41] [PASSED] rotate-270
[09:02:41] ============ [PASSED] drm_test_rect_rotate_inv =============
[09:02:41] ==================== [PASSED] drm_rect =====================
[09:02:41] ============ drm_sysfb_modeset_test (1 subtest) ============
[09:02:41] ============ drm_test_sysfb_build_fourcc_list =============
[09:02:41] [PASSED] no native formats
[09:02:41] [PASSED] XRGB8888 as native format
[09:02:41] [PASSED] remove duplicates
[09:02:41] [PASSED] convert alpha formats
[09:02:41] [PASSED] random formats
[09:02:41] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[09:02:41] ============= [PASSED] drm_sysfb_modeset_test ==============
[09:02:41] ================== drm_fixp (2 subtests) ===================
[09:02:41] [PASSED] drm_test_int2fixp
[09:02:41] [PASSED] drm_test_sm2fixp
[09:02:41] ==================== [PASSED] drm_fixp =====================
[09:02:41] ============================================================
[09:02:41] Testing complete. Ran 624 tests: passed: 624
[09:02:41] Elapsed time: 27.385s total, 1.715s configuring, 25.253s building, 0.377s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[09:02:41] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:02:43] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:02:52] Starting KUnit Kernel (1/1)...
[09:02:52] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:02:52] ================= ttm_device (5 subtests) ==================
[09:02:52] [PASSED] ttm_device_init_basic
[09:02:52] [PASSED] ttm_device_init_multiple
[09:02:52] [PASSED] ttm_device_fini_basic
[09:02:52] [PASSED] ttm_device_init_no_vma_man
[09:02:52] ================== ttm_device_init_pools ==================
[09:02:52] [PASSED] No DMA allocations, no DMA32 required
[09:02:52] [PASSED] DMA allocations, DMA32 required
[09:02:52] [PASSED] No DMA allocations, DMA32 required
[09:02:52] [PASSED] DMA allocations, no DMA32 required
[09:02:52] ============== [PASSED] ttm_device_init_pools ==============
[09:02:52] =================== [PASSED] ttm_device ====================
[09:02:52] ================== ttm_pool (8 subtests) ===================
[09:02:52] ================== ttm_pool_alloc_basic ===================
[09:02:52] [PASSED] One page
[09:02:52] [PASSED] More than one page
[09:02:52] [PASSED] Above the allocation limit
[09:02:52] [PASSED] One page, with coherent DMA mappings enabled
[09:02:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:02:52] ============== [PASSED] ttm_pool_alloc_basic ===============
[09:02:52] ============== ttm_pool_alloc_basic_dma_addr ==============
[09:02:52] [PASSED] One page
[09:02:52] [PASSED] More than one page
[09:02:52] [PASSED] Above the allocation limit
[09:02:52] [PASSED] One page, with coherent DMA mappings enabled
[09:02:52] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:02:52] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[09:02:52] [PASSED] ttm_pool_alloc_order_caching_match
[09:02:52] [PASSED] ttm_pool_alloc_caching_mismatch
[09:02:52] [PASSED] ttm_pool_alloc_order_mismatch
[09:02:52] [PASSED] ttm_pool_free_dma_alloc
[09:02:52] [PASSED] ttm_pool_free_no_dma_alloc
[09:02:52] [PASSED] ttm_pool_fini_basic
[09:02:52] ==================== [PASSED] ttm_pool =====================
[09:02:52] ================ ttm_resource (8 subtests) =================
[09:02:52] ================= ttm_resource_init_basic =================
[09:02:52] [PASSED] Init resource in TTM_PL_SYSTEM
[09:02:52] [PASSED] Init resource in TTM_PL_VRAM
[09:02:52] [PASSED] Init resource in a private placement
[09:02:52] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[09:02:52] ============= [PASSED] ttm_resource_init_basic =============
[09:02:52] [PASSED] ttm_resource_init_pinned
[09:02:52] [PASSED] ttm_resource_fini_basic
[09:02:52] [PASSED] ttm_resource_manager_init_basic
[09:02:52] [PASSED] ttm_resource_manager_usage_basic
[09:02:52] [PASSED] ttm_resource_manager_set_used_basic
[09:02:52] [PASSED] ttm_sys_man_alloc_basic
[09:02:52] [PASSED] ttm_sys_man_free_basic
[09:02:52] ================== [PASSED] ttm_resource ===================
[09:02:52] =================== ttm_tt (15 subtests) ===================
[09:02:52] ==================== ttm_tt_init_basic ====================
[09:02:52] [PASSED] Page-aligned size
[09:02:52] [PASSED] Extra pages requested
[09:02:52] ================ [PASSED] ttm_tt_init_basic ================
[09:02:52] [PASSED] ttm_tt_init_misaligned
[09:02:52] [PASSED] ttm_tt_fini_basic
[09:02:52] [PASSED] ttm_tt_fini_sg
[09:02:52] [PASSED] ttm_tt_fini_shmem
[09:02:52] [PASSED] ttm_tt_create_basic
[09:02:52] [PASSED] ttm_tt_create_invalid_bo_type
[09:02:52] [PASSED] ttm_tt_create_ttm_exists
[09:02:52] [PASSED] ttm_tt_create_failed
[09:02:52] [PASSED] ttm_tt_destroy_basic
[09:02:52] [PASSED] ttm_tt_populate_null_ttm
[09:02:52] [PASSED] ttm_tt_populate_populated_ttm
[09:02:52] [PASSED] ttm_tt_unpopulate_basic
[09:02:52] [PASSED] ttm_tt_unpopulate_empty_ttm
[09:02:52] [PASSED] ttm_tt_swapin_basic
[09:02:52] ===================== [PASSED] ttm_tt ======================
[09:02:52] =================== ttm_bo (14 subtests) ===================
[09:02:52] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[09:02:52] [PASSED] Cannot be interrupted and sleeps
[09:02:52] [PASSED] Cannot be interrupted, locks straight away
[09:02:52] [PASSED] Can be interrupted, sleeps
[09:02:52] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[09:02:52] [PASSED] ttm_bo_reserve_locked_no_sleep
[09:02:52] [PASSED] ttm_bo_reserve_no_wait_ticket
[09:02:52] [PASSED] ttm_bo_reserve_double_resv
[09:02:52] [PASSED] ttm_bo_reserve_interrupted
[09:02:52] [PASSED] ttm_bo_reserve_deadlock
[09:02:52] [PASSED] ttm_bo_unreserve_basic
[09:02:52] [PASSED] ttm_bo_unreserve_pinned
[09:02:52] [PASSED] ttm_bo_unreserve_bulk
[09:02:52] [PASSED] ttm_bo_fini_basic
[09:02:52] [PASSED] ttm_bo_fini_shared_resv
[09:02:52] [PASSED] ttm_bo_pin_basic
[09:02:52] [PASSED] ttm_bo_pin_unpin_resource
[09:02:52] [PASSED] ttm_bo_multiple_pin_one_unpin
[09:02:52] ===================== [PASSED] ttm_bo ======================
[09:02:52] ============== ttm_bo_validate (21 subtests) ===============
[09:02:52] ============== ttm_bo_init_reserved_sys_man ===============
[09:02:52] [PASSED] Buffer object for userspace
[09:02:52] [PASSED] Kernel buffer object
[09:02:52] [PASSED] Shared buffer object
[09:02:52] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[09:02:52] ============== ttm_bo_init_reserved_mock_man ==============
[09:02:52] [PASSED] Buffer object for userspace
[09:02:52] [PASSED] Kernel buffer object
[09:02:52] [PASSED] Shared buffer object
[09:02:52] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[09:02:52] [PASSED] ttm_bo_init_reserved_resv
[09:02:52] ================== ttm_bo_validate_basic ==================
[09:02:52] [PASSED] Buffer object for userspace
[09:02:52] [PASSED] Kernel buffer object
[09:02:52] [PASSED] Shared buffer object
[09:02:52] ============== [PASSED] ttm_bo_validate_basic ==============
[09:02:52] [PASSED] ttm_bo_validate_invalid_placement
[09:02:52] ============= ttm_bo_validate_same_placement ==============
[09:02:52] [PASSED] System manager
[09:02:52] [PASSED] VRAM manager
[09:02:52] ========= [PASSED] ttm_bo_validate_same_placement ==========
[09:02:52] [PASSED] ttm_bo_validate_failed_alloc
[09:02:52] [PASSED] ttm_bo_validate_pinned
[09:02:52] [PASSED] ttm_bo_validate_busy_placement
[09:02:52] ================ ttm_bo_validate_multihop =================
[09:02:52] [PASSED] Buffer object for userspace
[09:02:52] [PASSED] Kernel buffer object
[09:02:52] [PASSED] Shared buffer object
[09:02:52] ============ [PASSED] ttm_bo_validate_multihop =============
[09:02:52] ========== ttm_bo_validate_no_placement_signaled ==========
[09:02:52] [PASSED] Buffer object in system domain, no page vector
[09:02:52] [PASSED] Buffer object in system domain with an existing page vector
[09:02:52] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[09:02:52] ======== ttm_bo_validate_no_placement_not_signaled ========
[09:02:52] [PASSED] Buffer object for userspace
[09:02:52] [PASSED] Kernel buffer object
[09:02:52] [PASSED] Shared buffer object
[09:02:52] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[09:02:52] [PASSED] ttm_bo_validate_move_fence_signaled
[09:02:52] ========= ttm_bo_validate_move_fence_not_signaled =========
[09:02:52] [PASSED] Waits for GPU
[09:02:52] [PASSED] Tries to lock straight away
[09:02:52] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[09:02:52] [PASSED] ttm_bo_validate_happy_evict
[09:02:52] [PASSED] ttm_bo_validate_all_pinned_evict
[09:02:52] [PASSED] ttm_bo_validate_allowed_only_evict
[09:02:52] [PASSED] ttm_bo_validate_deleted_evict
[09:02:52] [PASSED] ttm_bo_validate_busy_domain_evict
[09:02:52] [PASSED] ttm_bo_validate_evict_gutting
[09:02:52] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[09:02:52] ================= [PASSED] ttm_bo_validate =================
[09:02:52] ============================================================
[09:02:52] Testing complete. Ran 101 tests: passed: 101
[09:02:52] Elapsed time: 10.956s total, 1.657s configuring, 9.083s building, 0.184s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Xe.CI.BAT: success for Fix Cx0 Suspend Resume issue (rev3)
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
` (3 preceding siblings ...)
2026-01-16 9:02 ` ✓ CI.KUnit: success for Fix Cx0 Suspend Resume issue (rev3) Patchwork
@ 2026-01-16 9:35 ` Patchwork
2026-01-16 11:41 ` ✗ Xe.CI.Full: failure " Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2026-01-16 9:35 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 858 bytes --]
== Series Details ==
Series: Fix Cx0 Suspend Resume issue (rev3)
URL : https://patchwork.freedesktop.org/series/159539/
State : success
== Summary ==
CI Bug Log - changes from xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205_BAT -> xe-pw-159539v3_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205 -> xe-pw-159539v3
IGT_8704: 8704
xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205: d398f90fc4dec55932a257eba5392e91c9bc2205
xe-pw-159539v3: 159539v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/index.html
[-- Attachment #2: Type: text/html, Size: 1406 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Xe.CI.Full: failure for Fix Cx0 Suspend Resume issue (rev3)
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
` (4 preceding siblings ...)
2026-01-16 9:35 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-01-16 11:41 ` Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2026-01-16 11:41 UTC (permalink / raw)
To: Suraj Kandpal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 23435 bytes --]
== Series Details ==
Series: Fix Cx0 Suspend Resume issue (rev3)
URL : https://patchwork.freedesktop.org/series/159539/
State : failure
== Summary ==
CI Bug Log - changes from xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205_FULL -> xe-pw-159539v3_FULL
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-159539v3_FULL absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-159539v3_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-159539v3_FULL:
### IGT changes ###
#### Possible regressions ####
* igt@kms_flip@modeset-vs-vblank-race-interruptible@d-dp2:
- shard-bmg: [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-9/igt@kms_flip@modeset-vs-vblank-race-interruptible@d-dp2.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-3/igt@kms_flip@modeset-vs-vblank-race-interruptible@d-dp2.html
* igt@xe_waitfence@abstime:
- shard-bmg: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-1/igt@xe_waitfence@abstime.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-7/igt@xe_waitfence@abstime.html
Known issues
------------
Here are the changes found in xe-pw-159539v3_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-bmg: NOTRUN -> [SKIP][5] ([Intel XE#2327]) +1 other test skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#1124]) +2 other tests skip
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][7] ([Intel XE#610]) +1 other test skip
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_bw@linear-tiling-1-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#367])
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_bw@linear-tiling-1-displays-2560x1440p.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs:
- shard-bmg: NOTRUN -> [SKIP][9] ([Intel XE#2887]) +7 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][10] ([Intel XE#3432])
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#2252]) +5 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
- shard-bmg: NOTRUN -> [FAIL][12] ([Intel XE#1178] / [Intel XE#3304]) +1 other test fail
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][13] ([Intel XE#2390] / [Intel XE#6974])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_cursor_crc@cursor-offscreen-256x85:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2320]) +2 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_cursor_crc@cursor-offscreen-256x85.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#2321])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#1508])
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#4422])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_fbc_dirty_rect@fbc-dirty-rectangle-dirtyfb-tests.html
* igt@kms_feature_discovery@display-3x:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2373])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_feature_discovery@display-3x.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2293] / [Intel XE#2380]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2293]) +1 other test skip
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#4141]) +7 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2311]) +13 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#2313]) +17 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#7061]) +3 other tests skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-argb161616f-draw-mmap-wc.html
* igt@kms_hdr@static-swap:
- shard-bmg: NOTRUN -> [ABORT][25] ([Intel XE#6740]) +1 other test abort
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@kms_hdr@static-swap.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2501])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#6886]) +4 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-a.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#836])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#1406] / [Intel XE#1489]) +3 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html
* igt@kms_psr@fbc-psr-primary-render:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +6 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_psr@fbc-psr-primary-render.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#1406] / [Intel XE#2414])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@primary-rotation-270:
- shard-bmg: NOTRUN -> [SKIP][32] ([Intel XE#3414] / [Intel XE#3904])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@kms_rotation_crc@primary-rotation-270.html
* igt@kms_sharpness_filter@invalid-filter-with-scaling-mode:
- shard-bmg: NOTRUN -> [SKIP][33] ([Intel XE#6503]) +2 other tests skip
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@kms_sharpness_filter@invalid-filter-with-scaling-mode.html
* igt@testdisplay:
- shard-bmg: [PASS][34] -> [ABORT][35] ([Intel XE#6740] / [Intel XE#6976])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-10/igt@testdisplay.html
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@testdisplay.html
* igt@xe_compute@ccs-mode-basic:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#6599])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@xe_compute@ccs-mode-basic.html
* igt@xe_create@multigpu-create-massive-size:
- shard-bmg: NOTRUN -> [SKIP][37] ([Intel XE#2504])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_eudebug@basic-vm-bind-extended:
- shard-bmg: NOTRUN -> [SKIP][38] ([Intel XE#4837]) +1 other test skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_eudebug@basic-vm-bind-extended.html
* igt@xe_eudebug_online@pagefault-write:
- shard-bmg: NOTRUN -> [SKIP][39] ([Intel XE#4837] / [Intel XE#6665]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@xe_eudebug_online@pagefault-write.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate:
- shard-bmg: NOTRUN -> [SKIP][40] ([Intel XE#2322]) +4 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority:
- shard-bmg: NOTRUN -> [SKIP][41] ([Intel XE#6874]) +15 other tests skip
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_exec_multi_queue@max-queues-preempt-mode-fault-dyn-priority.html
* igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset:
- shard-bmg: NOTRUN -> [SKIP][42] ([Intel XE#5007])
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_exec_system_allocator@many-64k-mmap-huge-nomemset.html
* igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge:
- shard-bmg: NOTRUN -> [SKIP][43] ([Intel XE#4943]) +12 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@xe_exec_system_allocator@process-many-execqueues-mmap-free-huge.html
* igt@xe_multigpu_svm@mgpu-migration-basic:
- shard-bmg: NOTRUN -> [SKIP][44] ([Intel XE#6964]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@xe_multigpu_svm@mgpu-migration-basic.html
* igt@xe_peer2peer@read:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2427] / [Intel XE#6953])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_peer2peer@read.html
* igt@xe_pm@s3-d3cold-basic-exec:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2284])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_pm@s3-d3cold-basic-exec.html
* igt@xe_pxp@regular-src-to-pxp-dest-rendercopy:
- shard-bmg: NOTRUN -> [SKIP][47] ([Intel XE#4733]) +1 other test skip
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-1/igt@xe_pxp@regular-src-to-pxp-dest-rendercopy.html
* igt@xe_query@multigpu-query-invalid-size:
- shard-bmg: NOTRUN -> [SKIP][48] ([Intel XE#944]) +1 other test skip
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@xe_query@multigpu-query-invalid-size.html
#### Possible fixes ####
* igt@kms_async_flips@alternate-sync-async-flip-atomic:
- shard-bmg: [FAIL][49] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][50] +1 other test pass
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-8/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
* igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1:
- shard-lnl: [FAIL][51] ([Intel XE#6054]) -> [PASS][52] +3 other tests pass
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear-atomic@pipe-c-edp-1.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [DMESG-WARN][53] ([Intel XE#5354]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-9/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-2/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][55] ([Intel XE#301]) -> [PASS][56] +3 other tests pass
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_hdr@static-toggle@pipe-a-dp-2:
- shard-bmg: [ABORT][57] ([Intel XE#6740]) -> [PASS][58] +1 other test pass
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-9/igt@kms_hdr@static-toggle@pipe-a-dp-2.html
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-10/igt@kms_hdr@static-toggle@pipe-a-dp-2.html
* {igt@xe_exec_basic@no-exec-bindexecqueue-userptr-invalidate@rcs0}:
- shard-lnl: [DMESG-WARN][59] ([Intel XE#7063]) -> [PASS][60] +1 other test pass
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-lnl-3/igt@xe_exec_basic@no-exec-bindexecqueue-userptr-invalidate@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-lnl-3/igt@xe_exec_basic@no-exec-bindexecqueue-userptr-invalidate@rcs0.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma:
- shard-lnl: [FAIL][61] ([Intel XE#5625]) -> [PASS][62] +1 other test pass
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-lnl-2/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-multi-vma.html
#### Warnings ####
* igt@kms_hdr@brightness-with-hdr:
- shard-bmg: [SKIP][63] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][64] ([Intel XE#3544])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-bmg-2/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf:
- shard-lnl: [DMESG-WARN][65] ([Intel XE#4537] / [Intel XE#7063]) -> [DMESG-WARN][66] ([Intel XE#7063])
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-lnl-3/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-lnl-3/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-sf.html
* igt@xe_pat@pat-sanity:
- shard-lnl: [DMESG-WARN][67] ([Intel XE#7063]) -> [DMESG-WARN][68] ([Intel XE#4537] / [Intel XE#7063])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205/shard-lnl-3/igt@xe_pat@pat-sanity.html
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/shard-lnl-3/igt@xe_pat@pat-sanity.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2427
[Intel XE#2501]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2501
[Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
[Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#4422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4422
[Intel XE#4537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4537
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5007
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#6054]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6054
[Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6503
[Intel XE#6599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6599
[Intel XE#6665]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6665
[Intel XE#6740]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6740
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#6953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6953
[Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
[Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
[Intel XE#6976]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6976
[Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
[Intel XE#7063]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7063
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205 -> xe-pw-159539v3
IGT_8704: 8704
xe-4393-d398f90fc4dec55932a257eba5392e91c9bc2205: d398f90fc4dec55932a257eba5392e91c9bc2205
xe-pw-159539v3: 159539v3
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-159539v3/index.html
[-- Attachment #2: Type: text/html, Size: 26030 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag
2026-01-16 8:54 ` [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag Suraj Kandpal
@ 2026-01-19 6:43 ` Garg, Nemesa
0 siblings, 0 replies; 12+ messages in thread
From: Garg, Nemesa @ 2026-01-19 6:43 UTC (permalink / raw)
To: Kandpal, Suraj, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: Nautiyal, Ankit K, Kandpal, Suraj
> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Suraj
> Kandpal
> Sent: Friday, January 16, 2026 2:25 PM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready
> flag
>
> Rename the non static intel_clear_response_ready_flag to
> intel_cx0_clear_response_ready_flag so that we follow the naming standards
> of non static function.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++-------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 4 ++--
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 2 +-
> 3 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 5b6b1ce40b0d..3ef25c942f44 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -127,8 +127,8 @@ static void intel_cx0_phy_transaction_end(struct
> intel_encoder *encoder, struct
> intel_display_power_put(display, POWER_DOMAIN_DC_OFF,
> wakeref); }
>
> -void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> - int lane)
> +void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
> + int lane)
> {
> struct intel_display *display = to_intel_display(encoder);
>
> @@ -155,7 +155,7 @@ void intel_cx0_bus_reset(struct intel_encoder
> *encoder, int lane)
> return;
> }
>
> - intel_clear_response_ready_flag(encoder, lane);
> + intel_cx0_clear_response_ready_flag(encoder, lane);
> }
>
> int intel_cx0_wait_for_ack(struct intel_encoder *encoder, @@ -222,7 +222,7
> @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
> return -ETIMEDOUT;
> }
>
> - intel_clear_response_ready_flag(encoder, lane);
> + intel_cx0_clear_response_ready_flag(encoder, lane);
>
> intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display,
> port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING | @@ -
> 233,7 +233,7 @@ static int __intel_cx0_read_once(struct intel_encoder
> *encoder,
> if (ack < 0)
> return ack;
>
> - intel_clear_response_ready_flag(encoder, lane);
> + intel_cx0_clear_response_ready_flag(encoder, lane);
>
> /*
> * FIXME: Workaround to let HW to settle @@ -295,7 +295,7 @@
> static int __intel_cx0_write_once(struct intel_encoder *encoder,
> return -ETIMEDOUT;
> }
>
> - intel_clear_response_ready_flag(encoder, lane);
> + intel_cx0_clear_response_ready_flag(encoder, lane);
>
> intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display,
> port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING | @@ -
> 325,7 +325,7 @@ static int __intel_cx0_write_once(struct intel_encoder
> *encoder,
> return -EINVAL;
> }
>
> - intel_clear_response_ready_flag(encoder, lane);
> + intel_cx0_clear_response_ready_flag(encoder, lane);
>
> /*
> * FIXME: Workaround to let HW to settle diff --git
> a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index ae98ac23ea22..87d3bdaca3ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -25,8 +25,8 @@ struct intel_dpll_hw_state; struct intel_encoder; struct
> intel_hdmi;
>
> -void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> - int lane);
> +void intel_cx0_clear_response_ready_flag(struct intel_encoder *encoder,
> + int lane);
> bool intel_encoder_is_c10phy(struct intel_encoder *encoder); void
> intel_mtl_pll_enable(struct intel_encoder *encoder,
> struct intel_dpll *pll,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 6cdae03ee172..e174ca011d50 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1106,7 +1106,7 @@ static int __intel_lt_phy_p2p_write_once(struct
> intel_encoder *encoder,
> * This is the time PHY takes to settle down after programming the
> PHY.
> */
> udelay(150);
> - intel_clear_response_ready_flag(encoder, lane);
> + intel_cx0_clear_response_ready_flag(encoder, lane);
> intel_lt_phy_clear_status_p2p(encoder, lane);
>
> return 0;
> --
LGTM,
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
> 2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier
2026-01-16 8:54 ` [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier Suraj Kandpal
@ 2026-01-20 13:57 ` Jani Nikula
2026-01-20 13:57 ` Jani Nikula
2026-01-21 6:13 ` Dibin Moolakadan Subrahmanian
0 siblings, 2 replies; 12+ messages in thread
From: Jani Nikula @ 2026-01-20 13:57 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, Mika Kahola, Suraj Kandpal
On Fri, 16 Jan 2026, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> Move intel_pps_on() to intel_dpll_mgr PLL enabling
> .enable function hook to enable panel power earlier.
> We need to do this to make sure we are following the
> modeset sequences of Bspec. This had changed when we
> moved the PLL PHY enablement for CX0 from .enable_clock
> to dpll.enable hook
So I really hate this.
Yeah, maybe it follows the spec now, but what connection does the DPLL
manager have with the panel power sequencing?
Absolutely nothing.
The DPLL manager has no business calling PPS functions.
Currently only the g4x and DDI encoder code does PPS power calls, and
they're the only ones who should manage PPS.
>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>
> v2 -> v3:
> - Rather than splitting the PHY enablement sequence, enable PPS
> earlier (Imre)
Please point me at the review comment. I couldn't find anything that
would suggest moving the PPS calls to the DPLL manager.
Please let's not do this.
BR,
Jani.
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index cb91d07cdaa6..1784fa687c03 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2653,8 +2653,10 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> /* 3. Select Thunderbolt */
> mtl_port_buf_ctl_io_selection(encoder);
>
> - /* 4. Enable Panel Power if PPS is required */
> - intel_pps_on(intel_dp);
> + /*
> + * 4. Enable Panel Power if PPS is required
> + * moved to intel_dpll_mgr .enable hook
> + */
>
> /* 5. Enable the port PLL */
> intel_ddi_enable_clock(encoder, crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 9aa84a430f09..b5655c734c53 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -40,6 +40,7 @@
> #include "intel_hti.h"
> #include "intel_mg_phy_regs.h"
> #include "intel_pch_refclk.h"
> +#include "intel_pps.h"
> #include "intel_step.h"
> #include "intel_tc.h"
>
> @@ -4401,6 +4402,10 @@ static void mtl_pll_enable(struct intel_display *display,
> if (drm_WARN_ON(display->drm, !encoder))
> return;
>
> + /* Enable Panel Power if PPS is required */
> + if (intel_encoder_is_dp(encoder))
> + intel_pps_on(enc_to_intel_dp(encoder));
> +
> intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier
2026-01-20 13:57 ` Jani Nikula
@ 2026-01-20 13:57 ` Jani Nikula
2026-01-22 18:02 ` Imre Deak
2026-01-21 6:13 ` Dibin Moolakadan Subrahmanian
1 sibling, 1 reply; 12+ messages in thread
From: Jani Nikula @ 2026-01-20 13:57 UTC (permalink / raw)
To: Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, Mika Kahola, Suraj Kandpal, imre.deak
On Tue, 20 Jan 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 16 Jan 2026, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
>> From: Mika Kahola <mika.kahola@intel.com>
>>
>> Move intel_pps_on() to intel_dpll_mgr PLL enabling
>> .enable function hook to enable panel power earlier.
>> We need to do this to make sure we are following the
>> modeset sequences of Bspec. This had changed when we
>> moved the PLL PHY enablement for CX0 from .enable_clock
>> to dpll.enable hook
>
> So I really hate this.
>
> Yeah, maybe it follows the spec now, but what connection does the DPLL
> manager have with the panel power sequencing?
>
> Absolutely nothing.
>
> The DPLL manager has no business calling PPS functions.
>
> Currently only the g4x and DDI encoder code does PPS power calls, and
> they're the only ones who should manage PPS.
>
>>
>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>>
>> v2 -> v3:
>> - Rather than splitting the PHY enablement sequence, enable PPS
>> earlier (Imre)
>
> Please point me at the review comment. I couldn't find anything that
> would suggest moving the PPS calls to the DPLL manager.
>
> Please let's not do this.
Cc: Imre
>
> BR,
> Jani.
>
>
>>
>> drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
>> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++
>> 2 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index cb91d07cdaa6..1784fa687c03 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2653,8 +2653,10 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>> /* 3. Select Thunderbolt */
>> mtl_port_buf_ctl_io_selection(encoder);
>>
>> - /* 4. Enable Panel Power if PPS is required */
>> - intel_pps_on(intel_dp);
>> + /*
>> + * 4. Enable Panel Power if PPS is required
>> + * moved to intel_dpll_mgr .enable hook
>> + */
>>
>> /* 5. Enable the port PLL */
>> intel_ddi_enable_clock(encoder, crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> index 9aa84a430f09..b5655c734c53 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> @@ -40,6 +40,7 @@
>> #include "intel_hti.h"
>> #include "intel_mg_phy_regs.h"
>> #include "intel_pch_refclk.h"
>> +#include "intel_pps.h"
>> #include "intel_step.h"
>> #include "intel_tc.h"
>>
>> @@ -4401,6 +4402,10 @@ static void mtl_pll_enable(struct intel_display *display,
>> if (drm_WARN_ON(display->drm, !encoder))
>> return;
>>
>> + /* Enable Panel Power if PPS is required */
>> + if (intel_encoder_is_dp(encoder))
>> + intel_pps_on(enc_to_intel_dp(encoder));
>> +
>> intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
>> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier
2026-01-20 13:57 ` Jani Nikula
2026-01-20 13:57 ` Jani Nikula
@ 2026-01-21 6:13 ` Dibin Moolakadan Subrahmanian
1 sibling, 0 replies; 12+ messages in thread
From: Dibin Moolakadan Subrahmanian @ 2026-01-21 6:13 UTC (permalink / raw)
To: Jani Nikula, Suraj Kandpal, intel-xe, intel-gfx
Cc: ankit.k.nautiyal, Mika Kahola
[-- Attachment #1: Type: text/plain, Size: 3027 bytes --]
On 20-01-2026 19:27, Jani Nikula wrote:
> On Fri, 16 Jan 2026, Suraj Kandpal<suraj.kandpal@intel.com> wrote:
>> From: Mika Kahola<mika.kahola@intel.com>
>>
>> Move intel_pps_on() to intel_dpll_mgr PLL enabling
>> .enable function hook to enable panel power earlier.
>> We need to do this to make sure we are following the
>> modeset sequences of Bspec. This had changed when we
>> moved the PLL PHY enablement for CX0 from .enable_clock
>> to dpll.enable hook
> So I really hate this.
>
> Yeah, maybe it follows the spec now, but what connection does the DPLL
> manager have with the panel power sequencing?
>
> Absolutely nothing.
>
> The DPLL manager has no business calling PPS functions.
>
> Currently only the g4x and DDI encoder code does PPS power calls, and
> they're the only ones who should manage PPS.
>
>> Signed-off-by: Mika Kahola<mika.kahola@intel.com>
>> Signed-off-by: Suraj Kandpal<suraj.kandpal@intel.com>
>> ---
>>
>> v2 -> v3:
>> - Rather than splitting the PHY enablement sequence, enable PPS
>> earlier (Imre)
> Please point me at the review comment. I couldn't find anything that
> would suggest moving the PPS calls to the DPLL manager.
>
> Please let's not do this.
>
> BR,
> Jani.
>
>
>>
>> drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
>> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++
>> 2 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index cb91d07cdaa6..1784fa687c03 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -2653,8 +2653,10 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
>> /* 3. Select Thunderbolt */
>> mtl_port_buf_ctl_io_selection(encoder);
>>
>> - /* 4. Enable Panel Power if PPS is required */
>> - intel_pps_on(intel_dp);
>> + /*
>> + * 4. Enable Panel Power if PPS is required
>> + * moved to intel_dpll_mgr .enable hook
>> + */
Moving pps on alone wont help here,
as new sequence will be 6 -> 4 -> 5.
Regards,
Dibin
>>
>> /* 5. Enable the port PLL */
>> intel_ddi_enable_clock(encoder, crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> index 9aa84a430f09..b5655c734c53 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
>> @@ -40,6 +40,7 @@
>> #include "intel_hti.h"
>> #include "intel_mg_phy_regs.h"
>> #include "intel_pch_refclk.h"
>> +#include "intel_pps.h"
>> #include "intel_step.h"
>> #include "intel_tc.h"
>>
>> @@ -4401,6 +4402,10 @@ static void mtl_pll_enable(struct intel_display *display,
>> if (drm_WARN_ON(display->drm, !encoder))
>> return;
>>
>> + /* Enable Panel Power if PPS is required */
>> + if (intel_encoder_is_dp(encoder))
>> + intel_pps_on(enc_to_intel_dp(encoder));
>> +
>> intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
>> }
[-- Attachment #2: Type: text/html, Size: 4228 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier
2026-01-20 13:57 ` Jani Nikula
@ 2026-01-22 18:02 ` Imre Deak
0 siblings, 0 replies; 12+ messages in thread
From: Imre Deak @ 2026-01-22 18:02 UTC (permalink / raw)
To: Jani Nikula
Cc: Suraj Kandpal, intel-xe, intel-gfx, ankit.k.nautiyal, Mika Kahola
On Tue, Jan 20, 2026 at 03:57:56PM +0200, Jani Nikula wrote:
> On Tue, 20 Jan 2026, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Fri, 16 Jan 2026, Suraj Kandpal <suraj.kandpal@intel.com> wrote:
> >> From: Mika Kahola <mika.kahola@intel.com>
> >>
> >> Move intel_pps_on() to intel_dpll_mgr PLL enabling
> >> .enable function hook to enable panel power earlier.
> >> We need to do this to make sure we are following the
> >> modeset sequences of Bspec. This had changed when we
> >> moved the PLL PHY enablement for CX0 from .enable_clock
> >> to dpll.enable hook
> >
> > So I really hate this.
> >
> > Yeah, maybe it follows the spec now, but what connection does the DPLL
> > manager have with the panel power sequencing?
> >
> > Absolutely nothing.
> >
> > The DPLL manager has no business calling PPS functions.
> >
> > Currently only the g4x and DDI encoder code does PPS power calls, and
> > they're the only ones who should manage PPS.
> >
> >>
> >> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> >> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> >> ---
> >>
> >> v2 -> v3:
> >> - Rather than splitting the PHY enablement sequence, enable PPS
> >> earlier (Imre)
> >
> > Please point me at the review comment. I couldn't find anything that
> > would suggest moving the PPS calls to the DPLL manager.
> >
> > Please let's not do this.
>
> Cc: Imre
Yes, moving the intel_pps_on() call from the DDI code to PLL code is not
correct and it's not what I suggested (offline). Based on Suraj's and
Mika's testing the ordering of intel_pps_on() vs. enabling the PLL did
make a difference, avoiding a PLL enabling timeout. This rationale for
the change should've been also added to the commit log, as I requested
in an earlier version of the patchset addressing the same issue in:
https://lore.kernel.org/all/aWeybp1JaC99Rf8L@ideak-desk
If bspec is actually correct and PPS must be enabled before enabling the
PLL, then the correct way to do that would be moving intel_pps_on() to
intel_ddi_pre_pll_enable(). But I have doubt that bspec is correct and
this ordering must be followed. As I pointed out in my earlier review
comment above, I'm not sure what happens then if the PLL must be in an
enabled state already (due to CMTG) before a DDI output using the same
PLL is enabled. So I'd prefer more evidence that following the bspec
order is actually a requirement (for instance a confirmation about that
from HW folks).
> > BR,
> > Jani.
> >
> >
> >>
> >> drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++++--
> >> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 5 +++++
> >> 2 files changed, 9 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> index cb91d07cdaa6..1784fa687c03 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> >> @@ -2653,8 +2653,10 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
> >> /* 3. Select Thunderbolt */
> >> mtl_port_buf_ctl_io_selection(encoder);
> >>
> >> - /* 4. Enable Panel Power if PPS is required */
> >> - intel_pps_on(intel_dp);
> >> + /*
> >> + * 4. Enable Panel Power if PPS is required
> >> + * moved to intel_dpll_mgr .enable hook
> >> + */
> >>
> >> /* 5. Enable the port PLL */
> >> intel_ddi_enable_clock(encoder, crtc_state);
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> index 9aa84a430f09..b5655c734c53 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> @@ -40,6 +40,7 @@
> >> #include "intel_hti.h"
> >> #include "intel_mg_phy_regs.h"
> >> #include "intel_pch_refclk.h"
> >> +#include "intel_pps.h"
> >> #include "intel_step.h"
> >> #include "intel_tc.h"
> >>
> >> @@ -4401,6 +4402,10 @@ static void mtl_pll_enable(struct intel_display *display,
> >> if (drm_WARN_ON(display->drm, !encoder))
> >> return;
> >>
> >> + /* Enable Panel Power if PPS is required */
> >> + if (intel_encoder_is_dp(encoder))
> >> + intel_pps_on(enc_to_intel_dp(encoder));
> >> +
> >> intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
> >> }
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2026-01-22 18:02 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-01-16 8:54 [PATCH v3 0/3] Fix Cx0 Suspend Resume issue Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 1/3] drm/i915/pps: Enable panel power earlier Suraj Kandpal
2026-01-20 13:57 ` Jani Nikula
2026-01-20 13:57 ` Jani Nikula
2026-01-22 18:02 ` Imre Deak
2026-01-21 6:13 ` Dibin Moolakadan Subrahmanian
2026-01-16 8:54 ` [PATCH v3 2/3] drm/i915/cx0: Clear response ready & error bit Suraj Kandpal
2026-01-16 8:54 ` [PATCH v3 3/3] drm/i915/cx0: Rename intel_clear_response_ready flag Suraj Kandpal
2026-01-19 6:43 ` Garg, Nemesa
2026-01-16 9:02 ` ✓ CI.KUnit: success for Fix Cx0 Suspend Resume issue (rev3) Patchwork
2026-01-16 9:35 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-16 11:41 ` ✗ Xe.CI.Full: failure " Patchwork
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