[PATCH v2 00/56] Enable HDMI FRL for MTL+

[PATCH v2 00/56] Enable HDMI FRL for MTL+

[Ankit Nautiyal]

FRL is a high-bandwidth transmission mode required for modes that exceed
the TMDS bandwidth limit.

The series covers the core enabling:
- SCDC helper additions for FRL link training
- FRL link training state machine (LTS:2, LTS:3, LTS:P)
- DDI enable/disable sequence updates for FRL mode
- DFM (Data Flow Metering) computation and register programming
- PHY (CX0/LT PHY) support for FRL rates
- Mode validation and clock computation for FRL

This is a work in progress. The primary goal at this stage is to get the
overall design reviewed and the foundational patches landed before building
on top.

Lightly tested on PTL. Modes like 4K@120 are working. Higher resolution
modes (e.g. 8K) require DSC which is not yet covered in this series, that
work is ongoing.

Testing on other MTL+ platforms is also ongoing.
Known gaps:
- DSC over FRL not yet supported
- Testing limited to MTL, PTL so far

Feedback on the design and approach is welcome.

Rev 2:
- Addressed review comments from Jani and Suraj on VBT parsing.
- Added pipe joiner support for HDMI.
- Added audio pruning for HDMI FRL mode.
- Tweaked the vswing presets and removed test-only presets.
- Fixed potential integer overflows in FRL DFM calculations.
- Tested on MTL, PTL, NVL with AORUS FO32U2P HDMI 2.1 panel.

Note: DSC support is WIP. Working patches are available in my public tree:
https://github.com/aknautiyal/tip/tree/hdmi21_dev  (based on drm-tip, may be rebased)
Tested working for most modes.

Ankit Nautiyal (38):
  drm/i915/hdmi: Add new data members for FRL configuration
  drm/i915/hdmi: Add FRL link rate cap
  drm/drm_scdc_helper: Add SCDC helper funcs for FRL
  drm/i915/display: Add registers for HDMI FRL configuration
  drm/i915/display: Add new members in crtc_state for FRL configuration
  drm/i915/intel_cx0_phy_regs: Add HDMI FRL SHIFT EN bit in
    PORT_BUF_CTL_1
  drm/i915/ddi: Update Transcoder/DDI registers with the frl bits
  drm/i915/hdmi: Enable Scrambling only for TMDS mode
  drm/i915/ddi: Simplify intel_ddi_enable()
  drm/i915/ddi: Factor out common transcoder/vblank enable sequence
  drm/i915/ddi: Update HDMI modeset sequence for MTL+
  drm/i915/hdmi: Add function to prepare registers for FRL mode
  drm/i915/hdmi: Add functions for FRL training state machine
  drm/i915/intel_hdmi: Add helper to disable FRL
  drm/i915/hdmi: Reduce FRL rate cap on rate change during training
  drm/i915/hdmi: Add provision for FRL mode while computing output
    format
  drm/i915/cx0: Add helper to check if the FRL rate is valid
  drm/i915/lt_phy: Add helper to check if the FRL rate is valid
  drm/i915/hdmi_frl_dfm: Add support for DFM calculation with DSC
  drm/i915/hdmi: Add helper to write FRL CFG register
  drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers
  drm/i915/hdmi: Validate FRL modes in mode_valid using the FRL DFM
  drm/i915/hdmi: Add FRL clock computation based on DFM
  drm/i915/hdmi: Add support for sending uevent to user for FRL training
    failure
  drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path
  drm/i915/ltphy: Fix HDMI FRL per-lane TX mapping
  drm/i915/hdmi: Add read out for FRL state
  drm/i915/hdmi: Use the real pixel clock as crtc_clock for FRL
  drm/i915/display: Add FRL members to the state checker
  drm/i915/hdmi: Compute output format for HDMI FRL mode
  drm/i915/hdmi: Add a helper to check non DSC audio support for HDMI
    FRL
  drm/i915/audio: Add the mode pruning logic for HDMI FRL
  drm/i915/joiner: Prepare to move joiner helpers to a new file
  drm/i915/joiner: Move joiner candidate helpers to intel_joiner.c
  drm/i915/joiner: Move joiner pipe mask helper to intel_joiner.c
  drm/i915/hdmi: Iterate through joiner candidates in compute_config
    path
  drm/i915/hdmi: Iterate through joiner candidates in mode_valid path
  drm/i915/hdmi: Allow Pipe joiner for HDMI

Suraj Kandpal (7):
  drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE
  drm/i915/hdmi: Drive per-lane TxFFE during FRL link training
  drm/i915/ltphy: Add PLL tables for HDMI FRL
  drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state
  drm/i915/ltphy: Calculate port clock for HDMI FRL
  drm/i915/ltphy: Verify HDMI FRL tables
  drm/i915/ddi_buf: Add Vswing table for HDMI FRL

Vandita Kulkarni (11):
  drm/i915/hdmi: Parse FRL max link rate from VBT
  drm/i915/hdmi_frl_dfm_regs: Define DFM registers
  drm/i915/hdmi_frl_dfm: Define frl_dfm structure
  drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers
  drm/i915/hdmi: Rename port clock limit to specify tmds clock
  drm/i915/hdmi: Rename port clock valid to specify tmds clock
  drm/i915/hdmi: Rename mode clock valid to specify tmds clock
  drm/i915/hdmi: Add FRL port clock valid
  drm/i915/hdmi: Compute FRL Link M/N
  drm/i915/hdmi_frl_dfm: Write and read back FRL Link M/N
  drm/i915/hdmi: Enable FRL based mode clock valid

 drivers/gpu/drm/display/drm_scdc_helper.c     |  109 ++
 drivers/gpu/drm/i915/Makefile                 |    2 +
 drivers/gpu/drm/i915/display/intel_audio.c    |   14 +-
 drivers/gpu/drm/i915/display/intel_bios.c     |   39 +
 drivers/gpu/drm/i915/display/intel_bios.h     |    1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   23 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |    1 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |    1 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  159 ++-
 .../drm/i915/display/intel_ddi_buf_trans.c    |   17 +
 drivers/gpu/drm/i915/display/intel_display.c  |   55 +-
 .../drm/i915/display/intel_display_debugfs.c  |    6 +-
 .../gpu/drm/i915/display/intel_display_regs.h |   27 +
 .../drm/i915/display/intel_display_types.h    |   38 +
 drivers/gpu/drm/i915/display/intel_dp.c       |   54 +-
 drivers/gpu/drm/i915/display/intel_dp.h       |   11 -
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |    5 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |    2 +-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 1051 ++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.h     |   16 +-
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c |  787 ++++++++++++
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.h |  123 ++
 .../i915/display/intel_hdmi_frl_dfm_regs.h    |   36 +
 drivers/gpu/drm/i915/display/intel_joiner.c   |  108 ++
 drivers/gpu/drm/i915/display/intel_joiner.h   |   27 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  348 +++++-
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |    1 +
 .../drm/i915/display/intel_modeset_verify.c   |   18 +
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |    7 +
 drivers/gpu/drm/xe/Makefile                   |    2 +
 include/drm/display/drm_scdc.h                |    3 +
 include/drm/display/drm_scdc_helper.h         |   23 +
 32 files changed, 2886 insertions(+), 228 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.h

-- 
2.50.1

[PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Parse the maximum FRL link rate from VBT and store it for use
during FRL mode selection and link training.

v3:
- Bail out early for VBT version < 237 and resolve the max FRL rate in a
  single switch, handling hdmi_max_frl_rate_valid == 0 up front. (Jani)
- Drop the intel_bios_hdmi_max_frl_rate() encoder wrapper and take the
  encoder devdata directly. (Jani)
- Use the standard VBT debug message format. (Jani)
- Spell FRL and VBT in caps in the subject and debug message. (Suraj, Jani)
- Move the hdmi_max_frl_rate_valid == 0 comment onto the check it
  describes. (Suraj)
- Add Bspec reference. (Suraj)

Bspec: XXXXX
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 39 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_bios.h     |  1 +
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++
 3 files changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 7b6a6f8c3cf1..7181237508b3 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2788,12 +2788,45 @@ static bool is_port_valid(struct intel_display *display, enum port port)
 	return true;
 }
 
+int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data *devdata)
+{
+	struct intel_display *display = devdata->display;
+
+	if (display->vbt.version < 237)
+		return 0;
+
+	/*
+	 * When hdmi_max_frl_rate_valid is 0 the VBT does not specify a maximum
+	 * FRL rate, so don't use it to limit the FRL rate on FRL-capable
+	 * platforms.
+	 */
+	if (!devdata->child.hdmi_max_frl_rate_valid)
+		return display->platform.meteorlake ? 12000000 : 0;
+
+	switch (devdata->child.hdmi_max_frl_rate) {
+	default:
+	case HDMI_MAX_FRL_RATE_PLATFORM:
+		return 0;
+	case HDMI_MAX_FRL_RATE_3G:
+		return 3000000;
+	case HDMI_MAX_FRL_RATE_6G:
+		return 6000000;
+	case HDMI_MAX_FRL_RATE_8G:
+		return 8000000;
+	case HDMI_MAX_FRL_RATE_10G:
+		return 10000000;
+	case HDMI_MAX_FRL_RATE_12G:
+		return 12000000;
+	}
+}
+
 static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
 {
 	struct intel_display *display = devdata->display;
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt;
 	int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock;
 	enum port port;
+	int hdmi_max_frl_rate;
 
 	port = intel_bios_encoder_port(devdata);
 	if (port == PORT_NONE)
@@ -2863,6 +2896,12 @@ static void print_ddi_port(const struct intel_bios_encoder_data *devdata)
 		drm_dbg_kms(display->drm,
 			    "Port %c VBT DP max link rate: %d\n",
 			    port_name(port), dp_max_link_rate);
+
+	hdmi_max_frl_rate = intel_bios_hdmi_max_frl_rate(devdata);
+	if (hdmi_max_frl_rate)
+		drm_dbg_kms(display->drm,
+			    "Port %c VBT HDMI max FRL rate: %d\n",
+			    port_name(port), hdmi_max_frl_rate);
 }
 
 static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 196b8b3f434f..b89f72d90c1f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -112,6 +112,7 @@ int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata);
 int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata);
 int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata);
 int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata);
+int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data *devdata);
 
 void intel_bios_for_each_encoder(struct intel_display *display,
 				 void (*func)(struct intel_display *display,
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 0dc13d080e8a..db7484542dc0 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -381,6 +381,13 @@ struct bdb_general_features {
 #define HDMI_MAX_DATA_RATE_340		4			/* 249+ */
 #define HDMI_MAX_DATA_RATE_300		5			/* 249+ */
 
+#define HDMI_MAX_FRL_RATE_PLATFORM	0			/* 237 */
+#define HDMI_MAX_FRL_RATE_3G		1			/* 237 */
+#define HDMI_MAX_FRL_RATE_6G		2			/* 237 */
+#define HDMI_MAX_FRL_RATE_8G		3			/* 237 */
+#define HDMI_MAX_FRL_RATE_10G		4			/* 237 */
+#define HDMI_MAX_FRL_RATE_12G		5			/* 237 */
+
 #define LEGACY_CHILD_DEVICE_CONFIG_SIZE		33
 
 /* DDC Bus DDI Type 155+ */
-- 
2.50.1

[PATCH v2 02/56] drm/i915/hdmi: Add new data members for FRL configuration

[Ankit Nautiyal]

HDMI supports higher resolutions using Fixed Rate Link.
Source needs to do FRL link training on the 4 lanes before video
stream transmission.

Add the members to crtc_state and intel_hdmi for identifying the FRL
supporting HDMI sink and to maintain the FRL training information after
successful training.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  9 +++++
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 36 +++++++++++++++++++
 2 files changed, 45 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 79f30660c2b6..89333c9ddcc8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1709,8 +1709,17 @@ struct intel_hdmi {
 		enum drm_dp_dual_mode_type type;
 		int max_tmds_clock;
 	} dp_dual_mode;
+	bool has_sink_hdmi_21;
+	int max_frl_rate;
+	int max_dsc_frl_rate;
 	struct intel_connector *attached_connector;
 	struct cec_notifier *cec_notifier;
+	struct {
+		bool trained;
+		int lanes;
+		int rate_gbps;
+		int ffe_level;
+	} frl;
 };
 
 struct intel_dp_mst_encoder;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b6fa1a1558b8..69534eea78a1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2485,6 +2485,8 @@ intel_hdmi_unset_edid(struct drm_connector *_connector)
 	struct intel_connector *connector = to_intel_connector(_connector);
 	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 
+	intel_hdmi->has_sink_hdmi_21 = false;
+
 	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
 	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
 
@@ -2545,6 +2547,38 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector)
 	}
 }
 
+static void
+intel_hdmi_reset_frl_config(struct intel_hdmi *intel_hdmi)
+{
+	intel_hdmi->frl.trained = false;
+	intel_hdmi->frl.lanes = 0;
+	intel_hdmi->frl.rate_gbps = 0;
+	intel_hdmi->frl.ffe_level = 0;
+}
+
+static void
+intel_hdmi_init_frl_config(struct intel_connector *connector)
+{
+	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
+	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
+	int max_src_frl_rate =
+		DIV_ROUND_UP(intel_bios_hdmi_max_frl_rate(encoder->devdata), 1000000) * 4;
+	int max_sink_dsc_frl_rate =
+		intel_hdmi_sink_dsc_max_frl_rate(&connector->base);
+	int max_sink_frl_rate =
+		intel_hdmi_sink_max_frl_rate(&connector->base);
+
+	intel_hdmi->has_sink_hdmi_21 = max_sink_frl_rate > 0;
+
+	intel_hdmi->max_frl_rate = min(max_sink_frl_rate,
+				       max_src_frl_rate);
+
+	intel_hdmi->max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
+					   max_src_frl_rate);
+
+	intel_hdmi_reset_frl_config(intel_hdmi);
+}
+
 static bool
 intel_hdmi_set_edid(struct drm_connector *_connector)
 {
@@ -2576,6 +2610,8 @@ intel_hdmi_set_edid(struct drm_connector *_connector)
 	if (drm_edid_is_digital(drm_edid)) {
 		intel_hdmi_dp_dual_mode_detect(&connector->base);
 
+		intel_hdmi_init_frl_config(connector);
+
 		connected = true;
 	}
 
-- 
2.50.1

[PATCH v2 03/56] drm/i915/hdmi: Add FRL link rate cap

[Ankit Nautiyal]

Add a member rate_cap to store the highest FRL rate the link is believed
to sustain. This is initially set based on the source and sink FRL
capabilities, and updated only when the capabilities change. To achieve
this, the reset is gated by a reset_rate_cap flag, so that rate_cap is
left as is on a plain re-probe.

Also reset the rate cap when the status changes to disconnected, so that
a re-plug of the same sink starts again from the full capability.

Later during a Link training failure at a specific rate, rate_cap can be
lowered, and since it is retained across a re-probe, the next training
attempt will honor the reduced cap. No user for now, this will be used
in the later changes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 33 ++++++++++++++++---
 2 files changed, 30 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 89333c9ddcc8..8a2128473f4f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1719,6 +1719,8 @@ struct intel_hdmi {
 		int lanes;
 		int rate_gbps;
 		int ffe_level;
+		int rate_cap;
+		bool reset_rate_cap;
 	} frl;
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 69534eea78a1..5c57f81d971b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2567,14 +2567,30 @@ intel_hdmi_init_frl_config(struct intel_connector *connector)
 		intel_hdmi_sink_dsc_max_frl_rate(&connector->base);
 	int max_sink_frl_rate =
 		intel_hdmi_sink_max_frl_rate(&connector->base);
+	int max_frl_rate, max_dsc_frl_rate;
 
 	intel_hdmi->has_sink_hdmi_21 = max_sink_frl_rate > 0;
 
-	intel_hdmi->max_frl_rate = min(max_sink_frl_rate,
-				       max_src_frl_rate);
+	max_frl_rate = min(max_sink_frl_rate, max_src_frl_rate);
 
-	intel_hdmi->max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
-					   max_src_frl_rate);
+	max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
+			       max_src_frl_rate);
+	/*
+	 * Set the FRL rate cap on connect / capability change only.
+	 * Leaving it untouched on a plain re-probe lets a future
+	 * training-driven reduction persist across the retry.
+	 */
+	if (max_frl_rate != intel_hdmi->max_frl_rate ||
+	    max_dsc_frl_rate != intel_hdmi->max_dsc_frl_rate)
+		intel_hdmi->frl.reset_rate_cap = true;
+
+	intel_hdmi->max_frl_rate = max_frl_rate;
+	intel_hdmi->max_dsc_frl_rate = max_dsc_frl_rate;
+
+	if (intel_hdmi->frl.reset_rate_cap) {
+		intel_hdmi->frl.rate_cap = max(max_frl_rate, max_dsc_frl_rate);
+		intel_hdmi->frl.reset_rate_cap = false;
+	}
 
 	intel_hdmi_reset_frl_config(intel_hdmi);
 }
@@ -2656,9 +2672,16 @@ intel_hdmi_detect(struct drm_connector *_connector, bool force)
 out:
 	intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
 
-	if (status != connector_status_connected)
+	if (status != connector_status_connected) {
 		cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
 
+		/*
+		 * Reset the rate cap so that the next connect re-initializes
+		 * frl.rate_cap to the capability ceiling.
+		 */
+		intel_hdmi->frl.reset_rate_cap = true;
+	}
+
 	return status;
 }
 
-- 
2.50.1

[PATCH v2 04/56] drm/drm_scdc_helper: Add SCDC helper funcs for FRL

[Ankit Nautiyal]

FRL (Fixed Rate Link) uses a set of SCDC registers to configure and
monitor link training between the source and sink.

Add the register definitions and helper functions to read and
configure these SCDC registers for FRL link training.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/display/drm_scdc_helper.c | 109 ++++++++++++++++++++++
 include/drm/display/drm_scdc.h            |   3 +
 include/drm/display/drm_scdc_helper.h     |  23 +++++
 3 files changed, 135 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_scdc_helper.c b/drivers/gpu/drm/display/drm_scdc_helper.c
index 74388481fc55..968a6587585f 100644
--- a/drivers/gpu/drm/display/drm_scdc_helper.c
+++ b/drivers/gpu/drm/display/drm_scdc_helper.c
@@ -350,6 +350,115 @@ int drm_scdc_set_source_version(struct drm_connector *connector, u8 ver)
 }
 EXPORT_SYMBOL(drm_scdc_set_source_version);
 
+int drm_scdc_read_update_flags(struct i2c_adapter *adapter, u8 *update_flags)
+{
+	return drm_scdc_readb(adapter, SCDC_UPDATE_0, update_flags);
+}
+EXPORT_SYMBOL(drm_scdc_read_update_flags);
+
+int drm_scdc_clear_update_flags(struct i2c_adapter *adapter, u8 update_flags)
+{
+	if (update_flags & SCDC_READ_REQUEST_TEST)
+		return -EINVAL;
+
+	return drm_scdc_writeb(adapter, SCDC_UPDATE_0, update_flags);
+}
+EXPORT_SYMBOL(drm_scdc_clear_update_flags);
+
+int drm_scdc_read_status_flags(struct i2c_adapter *adapter, u8 *status_flags)
+{
+	return drm_scdc_readb(adapter, SCDC_STATUS_FLAGS_0, status_flags);
+}
+EXPORT_SYMBOL(drm_scdc_read_status_flags);
+
+int drm_scdc_config_frl(struct i2c_adapter *adapter, int frl_rate,
+			int num_lanes, int ffe_levels)
+{
+	enum drm_scdc_frl_rate rate;
+	u8 config;
+
+	if (ffe_levels < 0 || ffe_levels > 3)
+		return -EINVAL;
+
+	switch (frl_rate) {
+	case 3:
+		if (num_lanes != 3)
+			return -EINVAL;
+		rate = SCDC_FRL_RATE_3X3;
+		break;
+	case 6:
+		if (num_lanes == 3)
+			rate = SCDC_FRL_RATE_6X3;
+		else if (num_lanes == 4)
+			rate = SCDC_FRL_RATE_6X4;
+		else
+			return -EINVAL;
+		break;
+	case 8:
+		if (num_lanes != 4)
+			return -EINVAL;
+		rate = SCDC_FRL_RATE_8X4;
+		break;
+	case 10:
+		if (num_lanes != 4)
+			return -EINVAL;
+		rate = SCDC_FRL_RATE_10X4;
+		break;
+	case 12:
+		if (num_lanes != 4)
+			return -EINVAL;
+		rate = SCDC_FRL_RATE_12X4;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	config = FIELD_PREP(SCDC_FRL_RATE, rate) |
+		 FIELD_PREP(SCDC_FFE_LEVELS, ffe_levels);
+
+	return drm_scdc_writeb(adapter, SCDC_CONFIG_1, config);
+}
+EXPORT_SYMBOL(drm_scdc_config_frl);
+
+int drm_scdc_disable_frl(struct i2c_adapter *adapter)
+{
+	u8 config;
+	int ret;
+
+	ret = drm_scdc_readb(adapter, SCDC_CONFIG_1, &config);
+	if (ret)
+		return ret;
+
+	config &= ~SCDC_FRL_RATE;
+
+	return drm_scdc_writeb(adapter, SCDC_CONFIG_1, config);
+}
+EXPORT_SYMBOL(drm_scdc_disable_frl);
+
+int drm_scdc_get_ltp(struct i2c_adapter *adapter,
+		     enum drm_scdc_frl_ltp ltp[4])
+{
+	u8 status_flags;
+	int ret;
+
+	ret = drm_scdc_readb(adapter, SCDC_STATUS_FLAGS_1, &status_flags);
+	if (ret)
+		return ret;
+
+	ltp[0] = FIELD_GET(SCDC_LN_EVEN_TRAIN_PTRN, status_flags);
+	ltp[1] = FIELD_GET(SCDC_LN_ODD_TRAIN_PTRN, status_flags);
+
+	ret = drm_scdc_readb(adapter, SCDC_STATUS_FLAGS_2, &status_flags);
+	if (ret)
+		return ret;
+
+	ltp[2] = FIELD_GET(SCDC_LN_EVEN_TRAIN_PTRN, status_flags);
+	ltp[3] = FIELD_GET(SCDC_LN_ODD_TRAIN_PTRN, status_flags);
+
+	return 0;
+}
+EXPORT_SYMBOL(drm_scdc_get_ltp);
+
 static void
 drm_scdc_parse_status0_flags(u8 val, struct drm_scdc_status_flags *flags)
 {
diff --git a/include/drm/display/drm_scdc.h b/include/drm/display/drm_scdc.h
index 7f0b05b2f280..694f10b81dd6 100644
--- a/include/drm/display/drm_scdc.h
+++ b/include/drm/display/drm_scdc.h
@@ -29,8 +29,11 @@
 #define SCDC_SOURCE_VERSION 0x02
 
 #define SCDC_UPDATE_0 0x10
+#define  SCDC_LIP_UPDATE (1 << 7)
 #define  SCDC_RSED_UPDATE (1 << 6)
 #define  SCDC_FLT_UPDATE (1 << 5)
+#define  SCDC_FRL_START (1 << 4)
+#define  SCDC_SOURCE_TEST_UPDATE (1 << 3)
 #define  SCDC_READ_REQUEST_TEST (1 << 2)
 #define  SCDC_CED_UPDATE (1 << 1)
 #define  SCDC_STATUS_UPDATE (1 << 0)
diff --git a/include/drm/display/drm_scdc_helper.h b/include/drm/display/drm_scdc_helper.h
index 6a8be1f16ce0..616afd0cf8b2 100644
--- a/include/drm/display/drm_scdc_helper.h
+++ b/include/drm/display/drm_scdc_helper.h
@@ -33,6 +33,20 @@ struct drm_connector;
 struct i2c_adapter;
 struct dentry;
 
+enum drm_scdc_frl_ltp {
+	SCDC_FRL_NO_LTP = 0,
+	SCDC_FRL_LTP1,
+	SCDC_FRL_LTP2,
+	SCDC_FRL_LTP3,
+	SCDC_FRL_LTP4,
+	SCDC_FRL_LTP5,
+	SCDC_FRL_LTP6,
+	SCDC_FRL_LTP7,
+	SCDC_FRL_LTP8,
+	SCDC_FRL_CHNG_FFE = 0xE,
+	SCDC_FRL_CHNG_RATE = 0xF,
+};
+
 struct drm_scdc_status_flags {
 	/* Status Register 0 */
 	bool clock_detected;
@@ -174,4 +188,13 @@ int drm_scdc_read_state(struct drm_connector *connector,
 			struct drm_scdc_state *state);
 void drm_scdc_debugfs_init(struct drm_connector *connector, struct dentry *root);
 
+int drm_scdc_read_update_flags(struct i2c_adapter *adapter, u8 *update_flags);
+int drm_scdc_clear_update_flags(struct i2c_adapter *adapter, u8 update_flags);
+int drm_scdc_read_status_flags(struct i2c_adapter *adapter, u8 *status_flags);
+int drm_scdc_config_frl(struct i2c_adapter *adapter, int frl_rate,
+			int num_lanes, int ffe_levels);
+int drm_scdc_disable_frl(struct i2c_adapter *adapter);
+int drm_scdc_get_ltp(struct i2c_adapter *adapter,
+		     enum drm_scdc_frl_ltp ltp[4]);
+
 #endif
-- 
2.50.1

[PATCH v2 05/56] drm/i915/display: Add registers for HDMI FRL configuration

[Ankit Nautiyal]

Add registers for HDMI FRL configuration and link training.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 8251ec15190b..1abd221f966b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -550,6 +550,32 @@
 #define _TRANS_MULT_B		0x6102c
 #define TRANS_MULT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
+/* HDMI FRL Configuration */
+#define _TRANS_HDMI_FRL_CFG_A				0x600b0
+#define TRANS_HDMI_FRL_CFG(dev_priv, trans)		_MMIO_TRANS2(dev_priv, \
+								     (trans), \
+								     _TRANS_HDMI_FRL_CFG_A)
+#define  TRANS_HDMI_FRL_ENABLE				REG_BIT(31)
+#define  TRANS_HDMI_TMDS_ENABLE				0
+#define  TRANS_HDMI_FRL_TRAINING_COMPLETE		REG_BIT(28)
+#define  TRANS_HDMI_DISABLE_DFM_MASKING			REG_BIT(20)
+#define  TRANS_HDMI_R_B_SCHED_ENABLE_MASK		REG_BIT(19)
+#define  TRANS_HDMI_R_B_SCHED_ENABLE(val)		REG_FIELD_PREP(TRANS_HDMI_R_B_SCHED_ENABLE_MASK, val)
+#define  TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK		REG_GENMASK(18, 16)
+#define  TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(val)		REG_FIELD_PREP(TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, val)
+#define  TRANS_HDMI_MIN_BLANK_CHAR_MASK			REG_GENMASK(15, 12)
+#define  TRANS_HDMI_MIN_BLANK_CHAR(val)			REG_FIELD_PREP(TRANS_HDMI_MIN_BLANK_CHAR_MASK, val)
+#define  TRANS_HDMI_MIN_BLANK_CHAR_VAL			0xa
+#define  TRANS_HDMI_FRL_PKT_PAYLOAD_MAX_MASK		REG_GENMASK(9, 0)
+#define  TRANS_HDMI_FRL_PKT_PAYLOAD_MAX(val)		REG_FIELD_PREP(TRANS_HDMI_FRL_PKT_PAYLOAD_MAX_MASK, val)
+#define  TRANS_HDMI_PAYLOAD_UPPER_BOUND			0x3fe
+
+#define _TRANS_HDMI_FRL_TRAIN_A				0x600b4
+#define TRANS_HDMI_FRL_TRAIN(dev_priv, trans)		_MMIO_TRANS2(dev_priv, \
+								     (trans), \
+								     _TRANS_HDMI_FRL_TRAIN_A)
+#define  TRANS_HDMI_FRL_LTP(pattern, lane) ((pattern) << (lane) * 8)
+
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN(dev_priv)		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
 #define   PORTB_HOTPLUG_INT_EN			(1 << 29)
-- 
2.50.1

[PATCH v2 06/56] drm/i915/display: Add new members in crtc_state for FRL configuration

[Ankit Nautiyal]

Add new struture to store FRL related configurations for a pipe.
These members to be calculated during compute config phase, when FRL
mode is to be used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_types.h    | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 8a2128473f4f..019f7b1b7c29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1467,6 +1467,32 @@ struct intel_crtc_state {
 
 	/* to track changes in plane color blocks */
 	bool plane_color_changed;
+
+	struct {
+		/* Go for FRL training */
+		bool enable;
+
+		/* Enable resource based scheduling */
+		bool rsrc_sched_en;
+
+		/* can be either 3 or 4 lanes */
+		u8 required_lanes;
+
+		/* required rate - can be 3, 6, 8, 10, 12 Gbps */
+		u8 required_rate;
+
+		/* FRL DFM Parameters */
+		u32 tb_borrowed, tb_actual, tb_threshold_min, active_char_buf_threshold;
+
+		/* FRL DFM DSC Tribytes */
+		u32 hcactive_tb, hctotal_tb;
+
+		/* Clock parameters in KHz */
+		u32 div18;
+
+		/* link m/n */
+		u32 link_m, link_n;
+	} frl;
 };
 
 enum intel_pipe_crc_source {
-- 
2.50.1

[PATCH v2 07/56] drm/i915/intel_cx0_phy_regs: Add HDMI FRL SHIFT EN bit in PORT_BUF_CTL_1

[Ankit Nautiyal]

Add HDMI_FRL_SHFTR_EN bit in PORT_BUF_CTL_1.
This bit enables the HDMI FRL 18b to 20b shifting and data output.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 152a4e751bdc..64fdf84b98ab 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -112,6 +112,7 @@
 #define   XELPDP_TCSS_POWER_REQUEST			REG_BIT(5)
 #define   XELPDP_TCSS_POWER_STATE			REG_BIT(4)
 #define   XELPDP_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
+#define   XELPDP_PORT_HDMI_FRL_SHFTR_EN			REG_BIT(0)
 #define   XELPDP_PORT_WIDTH(width)			REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \
 								       ((width) == 3 ? 4 : (width) - 1))
 
-- 
2.50.1

[PATCH v2 08/56] drm/i915/ddi: Update Transcoder/DDI registers with the frl bits

[Ankit Nautiyal]

For platforms supporting HDMI FRL we need to fill the lane count
in Transcoder and DDI/PORT registers for FRL mode.
Similarly, FRL SHIFTER ENABLE, and DATA_WIDTH bits are to be set
in FRL mode. These bits are written in both the DDI_BUF_CTL and
PORT_BUF_CTL registers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 25 +++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a46ab5d3d70f..576e66774678 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3121,12 +3121,20 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum port port = encoder->port;
+	u32 val;
 
 	intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
 
 	if (DISPLAY_VER(display) >= 14)
 		intel_wait_ddi_buf_idle(display, port);
 
+	/* Clear PORT_BUF_CTL HDMI FRL Shifter Enable to 0 */
+	if (crtc_state->frl.enable) {
+		val = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, port));
+		intel_de_write(display, XELPDP_PORT_BUF_CTL1(display, port),
+			       val & ~XELPDP_PORT_HDMI_FRL_SHFTR_EN);
+	}
+
 	mtl_ddi_disable_d2d(encoder);
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
@@ -3496,8 +3504,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 	 * On ADL_P the PHY link rate and lane count must be programmed but
 	 * these are both 0 for HDMI.
 	 *
-	 * But MTL onwards HDMI2.1 is supported and in TMDS mode this
-	 * is filled with lane count, already set in the crtc_state.
+	 * But MTL onwards HDMI FRL is supported and in FRL mode, port width
+	 * needs to be filled with either 3 or 4 lanes. For TMDS mode this
+	 * is always filled with 4 lanes, already set in the crtc_state.
 	 * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
 	 */
 	if (dig_port->lane_reversal)
@@ -3513,8 +3522,18 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 		if (dig_port->lane_reversal)
 			port_buf |= XELPDP_PORT_REVERSAL;
 
+		if (crtc_state->frl.enable) {
+			port_buf |= XELPDP_PORT_HDMI_FRL_SHFTR_EN;
+			port_buf |= XELPDP_PORT_BUF_PORT_DATA_20BIT;
+			buf_ctl |= DDI_BUF_PORT_DATA_20BIT;
+		} else {
+			buf_ctl &= ~DDI_BUF_PORT_DATA_MASK;
+		}
+
 		intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
-			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
+			     XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL |
+			     XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK |
+			     XELPDP_PORT_HDMI_FRL_SHFTR_EN, port_buf);
 
 		buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
-- 
2.50.1

[PATCH v2 09/56] drm/i915/hdmi: Enable Scrambling only for TMDS mode

[Ankit Nautiyal]

Enable scrambling in SCDC only for TMDS mode. For FRL mode scrambling
is handled as part of the FRL protocol and should not be configured
via the TMDS scrambling path.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 5c57f81d971b..ac655d9e4d79 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2430,7 +2430,8 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 
 	pipe_config->lane_count = 4;
 
-	if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
+	if (scdc->scrambling.supported && source_supports_scrambling(encoder) &&
+	    !pipe_config->frl.enable) {
 		if (scdc->scrambling.low_rates)
 			pipe_config->hdmi_scrambling = true;
 
-- 
2.50.1

[PATCH v2 10/56] drm/i915/ddi: Simplify intel_ddi_enable()

[Ankit Nautiyal]

Currently, intel_ddi_enable() has more HDMI- and DP-specific steps
than shared ones. Furthermore, from MTL onwards the sequence of
enabling the Port and TRANS_CONF has also diverged, which is not
currently accounted for.

Move the encoder-specific steps into their respective helpers and
simplify intel_ddi_enable(), which now simply dispatches to
intel_ddi_enable_{hdmi,dp}() and calls intel_hdcp_enable() at the
end.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 102 +++++++++++++----------
 1 file changed, 56 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 576e66774678..c4ca98510747 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3399,8 +3399,47 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_crtc *pipe_crtc;
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum port port = encoder->port;
 
+	/* 128b/132b SST */
+	if (intel_dp_is_uhbr(crtc_state)) {
+		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
+
+		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
+			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
+		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
+			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
+	}
+
+	intel_ddi_enable_transcoder_func(encoder, crtc_state);
+
+	intel_vrr_transcoder_enable(crtc_state);
+
+	/* 128b/132b SST */
+	if (intel_dp_is_uhbr(crtc_state)) {
+		intel_ddi_clear_act_sent(encoder, crtc_state);
+
+		intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
+			     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
+
+		intel_ddi_wait_for_act_sent(encoder, crtc_state);
+		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
+	}
+
+	intel_enable_transcoder(crtc_state);
+
+	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
+
+	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
+		const struct intel_crtc_state *pipe_crtc_state =
+			intel_atomic_get_new_crtc_state(state, pipe_crtc);
+
+		intel_crtc_vblank_on(pipe_crtc_state);
+	}
+
 	if (port == PORT_A && DISPLAY_VER(display) < 9)
 		intel_dp_stop_link_train(intel_dp, crtc_state);
 
@@ -3442,9 +3481,25 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_connector *connector = conn_state->connector;
+	struct intel_crtc *pipe_crtc;
 	enum port port = encoder->port;
 	u32 buf_ctl = 0;
 
+	intel_ddi_enable_transcoder_func(encoder, crtc_state);
+
+	intel_vrr_transcoder_enable(crtc_state);
+
+	intel_enable_transcoder(crtc_state);
+
+	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
+
+	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
+		const struct intel_crtc_state *pipe_crtc_state =
+			intel_atomic_get_new_crtc_state(state, pipe_crtc);
+
+		intel_crtc_vblank_on(pipe_crtc_state);
+	}
+
 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
 					       crtc_state->hdmi_high_tmds_clock_ratio,
 					       crtc_state->hdmi_scrambling))
@@ -3554,57 +3609,12 @@ static void intel_ddi_enable(struct intel_atomic_state *state,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state)
 {
-	struct intel_display *display = to_intel_display(encoder);
-	struct intel_crtc *pipe_crtc;
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	bool is_hdmi = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
-
-	/* 128b/132b SST */
-	if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
-		const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
-		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
-
-		intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
-			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
-		intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
-			       TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
-	}
-
-	intel_ddi_enable_transcoder_func(encoder, crtc_state);
-
-	intel_vrr_transcoder_enable(crtc_state);
-
-	/* 128b/132b SST */
-	if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
-		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
-
-		intel_ddi_clear_act_sent(encoder, crtc_state);
-
-		intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), 0,
-			     TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
-
-		intel_ddi_wait_for_act_sent(encoder, crtc_state);
-		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
-	}
-
-	intel_enable_transcoder(crtc_state);
-
-	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
-
-	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
-		const struct intel_crtc_state *pipe_crtc_state =
-			intel_atomic_get_new_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_on(pipe_crtc_state);
-	}
-
-	if (is_hdmi)
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
 	else
 		intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
 
 	intel_hdcp_enable(state, encoder, crtc_state, conn_state);
-
 }
 
 static void intel_ddi_disable_dp(struct intel_atomic_state *state,
-- 
2.50.1

[PATCH v2 11/56] drm/i915/ddi: Factor out common transcoder/vblank enable sequence

[Ankit Nautiyal]

intel_ddi_enable_dp() and intel_ddi_enable_hdmi() both contain an
identical sequence to enable the transcoder, wait for FEC status,
and turn on vblank for each pipe. Move this into a new helper,
intel_ddi_enable_transcoder_and_vblank(), to avoid the duplication.

No functional change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 43 ++++++++++++------------
 1 file changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c4ca98510747..a5a5a4f37262 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3391,6 +3391,25 @@ static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
 				 crtc_state);
 }
 
+static void intel_ddi_enable_transcoder_and_vblank(struct intel_atomic_state *state,
+						   struct intel_encoder *encoder,
+						   const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_crtc *pipe_crtc;
+
+	intel_enable_transcoder(crtc_state);
+
+	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
+
+	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
+		const struct intel_crtc_state *pipe_crtc_state =
+			intel_atomic_get_new_crtc_state(state, pipe_crtc);
+
+		intel_crtc_vblank_on(pipe_crtc_state);
+	}
+}
+
 static void intel_ddi_enable_dp(struct intel_atomic_state *state,
 				struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state,
@@ -3399,7 +3418,6 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_crtc *pipe_crtc;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	enum port port = encoder->port;
 
@@ -3429,16 +3447,7 @@ static void intel_ddi_enable_dp(struct intel_atomic_state *state,
 		drm_dp_dpcd_poll_act_handled(&intel_dp->aux, 0);
 	}
 
-	intel_enable_transcoder(crtc_state);
-
-	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
-
-	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
-		const struct intel_crtc_state *pipe_crtc_state =
-			intel_atomic_get_new_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_on(pipe_crtc_state);
-	}
+	intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
 
 	if (port == PORT_A && DISPLAY_VER(display) < 9)
 		intel_dp_stop_link_train(intel_dp, crtc_state);
@@ -3481,7 +3490,6 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_connector *connector = conn_state->connector;
-	struct intel_crtc *pipe_crtc;
 	enum port port = encoder->port;
 	u32 buf_ctl = 0;
 
@@ -3489,16 +3497,7 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 
 	intel_vrr_transcoder_enable(crtc_state);
 
-	intel_enable_transcoder(crtc_state);
-
-	intel_ddi_wait_for_fec_status(encoder, crtc_state, true);
-
-	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state) {
-		const struct intel_crtc_state *pipe_crtc_state =
-			intel_atomic_get_new_crtc_state(state, pipe_crtc);
-
-		intel_crtc_vblank_on(pipe_crtc_state);
-	}
+	intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
 
 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
 					       crtc_state->hdmi_high_tmds_clock_ratio,
-- 
2.50.1

[PATCH v2 12/56] drm/i915/ddi: Update HDMI modeset sequence for MTL+

[Ankit Nautiyal]

Per BSpec, the HDMI enable sequence differs starting MTL+: the port
must be fully configured and enabled (DDI_CTL_DE) before enabling the
transcoder (TRANS_CONF), whereas pre-MTL platforms enable the
transcoder before the port (DDI_BUF_CTL).

Today the HDMI path still uses the pre-MTL ordering: when the MTL+ DDI
sequences were implemented, HDMI was left enabling the transcoder before
the port. This does not cause any visible issue with current TMDS usage,
but it needs to be corrected before FRL can be wired up.

Bspec: 49191, 54145 (pre-MTL)
Bspec: 65750, 68848 (MTL+)
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a5a5a4f37262..1e08ffe19447 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3497,7 +3497,8 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 
 	intel_vrr_transcoder_enable(crtc_state);
 
-	intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
+	if (DISPLAY_VER(display) < 14)
+		intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
 
 	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
 					       crtc_state->hdmi_high_tmds_clock_ratio,
@@ -3600,6 +3601,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 
 	intel_ddi_buf_enable(encoder, buf_ctl);
 
+	if (DISPLAY_VER(display) >= 14)
+		intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
+
 	intel_hdmi_poll_for_scrambling_enable(crtc_state, connector);
 }
 
-- 
2.50.1

[PATCH v2 13/56] drm/i915/hdmi: Add function to prepare registers for FRL mode

[Ankit Nautiyal]

Add intel_hdmi_prepare_for_frl_mode() to arm the FRL function and reset
the training pattern to the default LTP1 on all active lanes, before the
Link training sequence starts.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  2 +-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index ac655d9e4d79..692480311c74 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3501,3 +3501,25 @@ int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector)
 
 	return max_lanes * rate_per_lane;
 }
+
+void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder trans = crtc_state->cpu_transcoder;
+	int num_lanes = crtc_state->frl.required_lanes;
+	u32 write_buf = 0;
+	int lane;
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, trans),
+		     TRANS_HDMI_FRL_TRAINING_COMPLETE,
+		     TRANS_HDMI_FRL_ENABLE);
+
+	/* Reset Training Pattern to default 0x1 */
+	for (lane = 0; lane < num_lanes; lane++)
+		write_buf |= TRANS_HDMI_FRL_LTP(0x1, lane);
+
+	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index c95ed37bcc0c..6283305b5274 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -63,7 +63,7 @@ int intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 				  int hdmi_max_slices, int hdmi_throughput);
 int intel_hdmi_dsc_get_slice_height(int vactive);
 bool intel_hdmi_is_frl(u32 clock);
-
+void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state);
 void hsw_write_infoframe(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state,
 			 unsigned int type,
-- 
2.50.1

[PATCH v2 14/56] drm/i915/hdmi: Add functions for FRL training state machine

[Ankit Nautiyal]

Add the FRL link training state machine and the helpers to drive it
with an HDMI FRL sink over SCDC: prepare for LTS:2, train the lanes in
LTS:3, complete training in LTS:P and fall back to legacy TMDS in LTS:L.

intel_hdmi_start_frl() drives these states for the requested rate and
lanes.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 301 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |   2 +
 2 files changed, 303 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 692480311c74..47d10ae0b07f 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3523,3 +3523,304 @@ void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state)
 
 	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
 }
+
+static int is_flt_ready(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct i2c_adapter *adapter =
+		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
+	u8 status_flags;
+	int ret;
+
+	ret = drm_scdc_read_status_flags(adapter, &status_flags);
+	if (ret)
+		return ret;
+
+	return !!(status_flags & SCDC_FLT_READY);
+}
+
+static int get_frl_update_flags(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct i2c_adapter *adapter =
+		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
+	u8 update_flags;
+	int ret;
+
+	ret = drm_scdc_read_update_flags(adapter, &update_flags);
+	if (ret)
+		return ret;
+
+	return update_flags;
+}
+
+static int clear_scdc_update_flags(struct intel_encoder *encoder, u8 flags)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct i2c_adapter *adapter =
+		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
+
+	return drm_scdc_clear_update_flags(adapter, flags);
+}
+
+static bool
+intel_hdmi_frl_prepare_lts2(struct intel_encoder *encoder,
+			    int frl_rate, int frl_lanes,
+			    int ffe_level)
+{
+#define TIMEOUT_FLT_READY_MS 250
+	struct intel_display *display = to_intel_display(encoder);
+	struct i2c_adapter *adapter =
+		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
+	int flt_ready;
+	int ret;
+
+	if (!frl_rate || !frl_lanes)
+		return false;
+
+	ret = read_poll_timeout(is_flt_ready, flt_ready,
+				flt_ready, 1000,
+				TIMEOUT_FLT_READY_MS * USEC_PER_MSEC,
+				false, encoder);
+	if (flt_ready < 0) {
+		drm_dbg_kms(display->drm,
+			    "Failed to read SCDC status flags: %d\n", flt_ready);
+		return false;
+	}
+	if (ret) {
+		drm_dbg_kms(display->drm,
+			    "HDMI sink not ready for FRL in %d\n",
+			    TIMEOUT_FLT_READY_MS);
+		return false;
+	}
+
+	ret = get_frl_update_flags(encoder);
+	if (ret < 0) {
+		drm_dbg_kms(display->drm,
+			    "Failed to read SCDC update flags: %d\n", ret);
+		return false;
+	}
+	if (ret & SCDC_FLT_UPDATE)
+		clear_scdc_update_flags(encoder, SCDC_FLT_UPDATE);
+
+	/* #TODO: Source shall program TxFFE = 0 for all active lanes */
+
+	if (drm_scdc_config_frl(adapter, frl_rate, frl_lanes, ffe_level) < 0) {
+		drm_dbg_kms(display->drm,
+			    "Failed to write SCDC config regs for FRL\n");
+		return false;
+	}
+
+	return flt_ready;
+}
+
+enum frl_lt_status {
+	FRL_TRAINING_PASSED,
+	FRL_CHANGE_RATE,
+	FRL_TRAIN_CONTINUE,
+	FRL_TRAIN_RETRAIN,
+	FRL_TRAIN_STOP,
+};
+
+static int get_link_training_patterns(struct intel_encoder *encoder,
+				      enum drm_scdc_frl_ltp ltp[4])
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct i2c_adapter *adapter =
+		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
+
+	return drm_scdc_get_ltp(adapter, ltp);
+}
+
+static enum frl_lt_status
+intel_hdmi_train_lanes(struct intel_encoder *encoder,
+		       const struct intel_crtc_state *crtc_state,
+		       int ffe_level)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	enum transcoder trans = crtc_state->cpu_transcoder;
+	int num_lanes = crtc_state->frl.required_lanes;
+	enum drm_scdc_frl_ltp ltp[4];
+	u32 write_buf = 0;
+	int update_flags;
+	int lane;
+
+	update_flags = get_frl_update_flags(encoder);
+	if (update_flags < 0)
+		return FRL_TRAIN_STOP;
+
+	if (!(update_flags & SCDC_FLT_UPDATE))
+		return FRL_TRAIN_CONTINUE;
+
+	if (get_link_training_patterns(encoder, ltp) < 0)
+		return FRL_TRAIN_STOP;
+
+	if (ltp[0] == ltp[1] && ltp[1] == ltp[2]) {
+		if (num_lanes == 3 || (num_lanes == 4 && ltp[2] == ltp[3])) {
+			if (ltp[0] == SCDC_FRL_NO_LTP)
+				return FRL_TRAINING_PASSED;
+			if (ltp[0] == SCDC_FRL_CHNG_RATE)
+				return FRL_CHANGE_RATE;
+		}
+	}
+
+	for (lane = 0; lane < num_lanes; lane++) {
+		if (ltp[lane] == SCDC_FRL_LTP3)
+			continue;
+
+		if (ltp[lane] >= SCDC_FRL_LTP1 && ltp[lane] <= SCDC_FRL_LTP8)
+			write_buf |= TRANS_HDMI_FRL_LTP(ltp[lane], lane);
+
+		/* #TODO handle FFE change */
+		else if (ltp[lane] == SCDC_FRL_CHNG_FFE)
+			continue;
+	}
+
+	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
+
+	clear_scdc_update_flags(encoder, SCDC_FLT_UPDATE);
+
+	return FRL_TRAIN_CONTINUE;
+}
+
+static enum frl_lt_status
+frl_train_complete_ltsp(struct intel_encoder *encoder,
+			const struct intel_crtc_state *crtc_state)
+{
+#define FLT_UPDATE_TIMEOUT_MS 200
+	struct intel_display *display = to_intel_display(encoder);
+	enum transcoder trans = crtc_state->cpu_transcoder;
+	int update_flags;
+	u8 clear_flags = 0;
+	u32 buf;
+	int ret;
+
+	buf = intel_de_read(display, TRANS_HDMI_FRL_CFG(display, trans));
+	intel_de_write(display, TRANS_HDMI_FRL_CFG(display, trans),
+		       buf | TRANS_HDMI_FRL_TRAINING_COMPLETE);
+
+	if (clear_scdc_update_flags(encoder, SCDC_FLT_UPDATE) < 0)
+		return FRL_TRAIN_STOP;
+
+	ret = read_poll_timeout(get_frl_update_flags, update_flags,
+				update_flags < 0 ||
+				(update_flags & (SCDC_FRL_START | SCDC_FLT_UPDATE)),
+				1000, FLT_UPDATE_TIMEOUT_MS * USEC_PER_MSEC,
+				false, encoder);
+	if (update_flags < 0) {
+		drm_dbg_kms(display->drm,
+			    "Failed to read SCDC update flags: %d\n", update_flags);
+		return FRL_TRAIN_STOP;
+	}
+	if (!ret && (update_flags & (SCDC_FRL_START | SCDC_FLT_UPDATE))) {
+		if (update_flags & SCDC_FLT_UPDATE)
+			clear_flags |= SCDC_FLT_UPDATE;
+		if (update_flags & SCDC_FRL_START) {
+			clear_flags |= SCDC_FRL_START;
+			clear_scdc_update_flags(encoder, clear_flags);
+			return FRL_TRAINING_PASSED;
+		}
+		drm_dbg_kms(display->drm,
+			    "FRL update received for retraining the lanes\n");
+		clear_scdc_update_flags(encoder, clear_flags);
+		return FRL_TRAIN_RETRAIN;
+	}
+
+	drm_err(display->drm, "FRL TRAINING: FRL update timedout\n");
+	return FRL_TRAIN_STOP;
+}
+
+static enum frl_lt_status
+intel_hdmi_frl_train_lts3(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state,
+			  int ffe_level)
+{
+#define FLT_TIMEOUT_MS 200
+	struct intel_display *display = to_intel_display(encoder);
+	enum frl_lt_status status;
+	enum transcoder trans = crtc_state->cpu_transcoder;
+	u32 buf;
+
+	buf = intel_de_read(display, TRANS_HDMI_FRL_CFG(display, trans));
+	intel_de_write(display, TRANS_HDMI_FRL_CFG(display, trans),
+		       buf | TRANS_HDMI_FRL_ENABLE);
+
+#define done (status != FRL_TRAIN_CONTINUE)
+	status = FRL_TRAIN_CONTINUE;
+	read_poll_timeout(intel_hdmi_train_lanes, status,
+			  done,
+			  1000, FLT_TIMEOUT_MS * USEC_PER_MSEC,
+			  false, encoder, crtc_state, ffe_level);
+
+	if (status == FRL_TRAIN_CONTINUE) {
+		drm_err(display->drm, "FRL TRAINING: FLT TIMEDOUT\n");
+		return FRL_TRAIN_STOP;
+	}
+
+	if (status != FRL_TRAINING_PASSED)
+		return status;
+
+	return frl_train_complete_ltsp(encoder, crtc_state);
+}
+
+static int get_ffe_level(int rate_gbps)
+{
+	return 0;
+}
+
+int intel_hdmi_start_frl(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
+	struct intel_connector *intel_connector = intel_hdmi->attached_connector;
+	struct drm_connector *connector = &intel_connector->base;
+	int req_rate = crtc_state->frl.required_lanes * crtc_state->frl.required_rate;
+	int ffe_level = get_ffe_level(req_rate);
+	enum frl_lt_status status;
+
+	if (!crtc_state->frl.enable)
+		return 0;
+
+	if (intel_hdmi->frl.trained &&
+	    intel_hdmi->frl.rate_gbps >= req_rate) {
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] FRL Already trained with rate=%d\n",
+			    connector->base.id, connector->name,
+			    intel_hdmi->frl.rate_gbps);
+		return 0;
+	}
+
+	intel_hdmi_reset_frl_config(intel_hdmi);
+
+	if (!intel_hdmi_frl_prepare_lts2(encoder,
+					 crtc_state->frl.required_rate,
+					 crtc_state->frl.required_lanes,
+					 ffe_level))
+		status = FRL_TRAIN_STOP;
+	else
+		status = intel_hdmi_frl_train_lts3(encoder, crtc_state, ffe_level);
+
+	switch (status) {
+	case FRL_TRAINING_PASSED:
+		intel_hdmi->frl.trained = true;
+		intel_hdmi->frl.rate_gbps = req_rate;
+		intel_hdmi->frl.ffe_level = ffe_level;
+		drm_dbg_kms(display->drm,
+			    "[CONNECTOR:%d:%s] FRL Training Passed with rate=%d\n",
+			    connector->base.id, connector->name,
+			    intel_hdmi->frl.rate_gbps);
+		return 0;
+	default:
+		break;
+	}
+
+	if (crtc_state->frl.enable && !intel_hdmi->frl.trained)
+		drm_err(display->drm,
+			"[CONNECTOR:%d:%s] FRL Training Failed with rate=%d\n",
+			connector->base.id, connector->name,
+			req_rate);
+
+	return -EINVAL;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 6283305b5274..1724e6075a9b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -64,6 +64,8 @@ int intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 int intel_hdmi_dsc_get_slice_height(int vactive);
 bool intel_hdmi_is_frl(u32 clock);
 void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state);
+int intel_hdmi_start_frl(struct intel_encoder *encoder,
+			 const struct intel_crtc_state *crtc_state);
 void hsw_write_infoframe(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state,
 			 unsigned int type,
-- 
2.50.1

[PATCH v2 15/56] drm/i915/intel_hdmi: Add helper to disable FRL

[Ankit Nautiyal]

Add function to reset the SCDC FRL configuration and
Transcoder FRL configuration registers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 28 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  2 ++
 2 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 47d10ae0b07f..fa4e5f0f567b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3824,3 +3824,31 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 
 	return -EINVAL;
 }
+
+static void intel_hdmi_frl_ltsl(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct i2c_adapter *adapter =
+		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
+
+	drm_scdc_disable_frl(adapter);
+	drm_scdc_clear_update_flags(adapter, SCDC_FLT_UPDATE);
+}
+
+void intel_hdmi_disable_frl(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state)
+{
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	struct intel_display *display = to_intel_display(encoder);
+	enum transcoder trans = crtc_state->cpu_transcoder;
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	intel_hdmi_frl_ltsl(encoder, crtc_state);
+	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, trans),
+		     TRANS_HDMI_FRL_ENABLE | TRANS_HDMI_FRL_TRAINING_COMPLETE, 0);
+
+	intel_hdmi_reset_frl_config(intel_hdmi);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 1724e6075a9b..59a561ad28e0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -66,6 +66,8 @@ bool intel_hdmi_is_frl(u32 clock);
 void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state);
 int intel_hdmi_start_frl(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state);
+void intel_hdmi_disable_frl(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state);
 void hsw_write_infoframe(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state,
 			 unsigned int type,
-- 
2.50.1

[PATCH v2 16/56] drm/i915/hdmi: Reduce FRL rate cap on rate change during training

[Ankit Nautiyal]

If the sink requests a rate change during FRL Link training, reduce
frl.rate_cap to the next lower FRL rate. The next mode compute then
uses this lower rate cap, so we do not attempt the failing rate again.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 27 ++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index fa4e5f0f567b..11b4554e87bd 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3763,6 +3763,18 @@ intel_hdmi_frl_train_lts3(struct intel_encoder *encoder,
 	return frl_train_complete_ltsp(encoder, crtc_state);
 }
 
+static int get_next_frl_rate(int curr_rate_gbps)
+{
+	int valid_rate[] = { 48, 40, 32, 24, 18, 9 };
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(valid_rate); i++)
+		if (valid_rate[i] < curr_rate_gbps)
+			return valid_rate[i];
+
+	return -EINVAL;
+}
+
 static int get_ffe_level(int rate_gbps)
 {
 	return 0;
@@ -3779,6 +3791,7 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 	int req_rate = crtc_state->frl.required_lanes * crtc_state->frl.required_rate;
 	int ffe_level = get_ffe_level(req_rate);
 	enum frl_lt_status status;
+	int next_rate = -EINVAL;
 
 	if (!crtc_state->frl.enable)
 		return 0;
@@ -3812,10 +3825,22 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 			    connector->base.id, connector->name,
 			    intel_hdmi->frl.rate_gbps);
 		return 0;
-	default:
+	case FRL_TRAIN_STOP:
+		next_rate = 0;
+		break;
+	case FRL_CHANGE_RATE:
+		next_rate = get_next_frl_rate(req_rate);
 		break;
+	case FRL_TRAIN_RETRAIN:
+		fallthrough;
+	default:
+		goto ltsl_tmds_mode;
 	}
 
+	if (next_rate >= 0)
+		intel_hdmi->frl.rate_cap = next_rate;
+
+ltsl_tmds_mode:
 	if (crtc_state->frl.enable && !intel_hdmi->frl.trained)
 		drm_err(display->drm,
 			"[CONNECTOR:%d:%s] FRL Training Failed with rate=%d\n",
-- 
2.50.1

[PATCH v2 17/56] drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

HDMI FRL link training tracks the TxFFE preset per lane: the sink
issues per-lane Ln(x)_LTP_req requests over SCDC and the source owns
an independent TxFFE counter for each lane.

Convert struct intel_hdmi.frl from a single link-wide ffe_level into
a per-lane ffe_level[4] array plus a max_ffe_level cap, and expose
intel_hdmi_frl_level(encoder, lane) which returns the buf-trans index
that the PHY set_signal_levels() callback should program for that
lane.

Wire it into intel_ddi_level(): on FRL the per-lane index is used,
TMDS keeps the existing intel_ddi_hdmi_level() VBT/default path.

No functional change yet: ffe_level[] is always zero, so
intel_hdmi_frl_level() returns the TxFFE0 row (index 1) on every
lane, matching pre-existing behaviour. The training-side updates
that drive ffe_level[] arrive in a follow-up change.

v2: Drop Test TxFFE levels. (Ankit)

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      | 10 ++++++---
 .../drm/i915/display/intel_display_types.h    |  3 ++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 21 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_hdmi.h     |  2 ++
 4 files changed, 30 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1e08ffe19447..53e889c0d022 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1518,11 +1518,15 @@ int intel_ddi_level(struct intel_encoder *encoder,
 	if (drm_WARN_ON_ONCE(display->drm, !trans))
 		return 0;
 
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		level = intel_ddi_hdmi_level(encoder, trans);
-	else
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+		if (intel_hdmi_is_frl(crtc_state->port_clock))
+			level = intel_hdmi_frl_level(encoder, lane);
+		else
+			level = intel_ddi_hdmi_level(encoder, trans);
+	} else {
 		level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
 					   lane);
+	}
 
 	if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))
 		level = n_entries - 1;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 019f7b1b7c29..db08eb613d89 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1744,9 +1744,10 @@ struct intel_hdmi {
 		bool trained;
 		int lanes;
 		int rate_gbps;
-		int ffe_level;
 		int rate_cap;
 		bool reset_rate_cap;
+		u8 max_ffe_level;
+		u8 ffe_level[4];
 	} frl;
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 11b4554e87bd..0873ecd6ef71 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2554,7 +2554,23 @@ intel_hdmi_reset_frl_config(struct intel_hdmi *intel_hdmi)
 	intel_hdmi->frl.trained = false;
 	intel_hdmi->frl.lanes = 0;
 	intel_hdmi->frl.rate_gbps = 0;
-	intel_hdmi->frl.ffe_level = 0;
+	intel_hdmi->frl.max_ffe_level = 0;
+	memset(intel_hdmi->frl.ffe_level, 0, sizeof(intel_hdmi->frl.ffe_level));
+}
+
+/*
+ * HDMI FRL training level is encoded as follows:
+ *   0		: No FFE (LTP4 test mode)
+ *   1..3	: TxFFE 1-3 levels
+ */
+int intel_hdmi_frl_level(struct intel_encoder *encoder, int lane)
+{
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+
+	if (lane < 0 || lane >= ARRAY_SIZE(intel_hdmi->frl.ffe_level))
+		return 1;
+
+	return 1 + intel_hdmi->frl.ffe_level[lane];
 }
 
 static void
@@ -3806,6 +3822,7 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 	}
 
 	intel_hdmi_reset_frl_config(intel_hdmi);
+	intel_hdmi->frl.max_ffe_level = ffe_level;
 
 	if (!intel_hdmi_frl_prepare_lts2(encoder,
 					 crtc_state->frl.required_rate,
@@ -3819,7 +3836,7 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 	case FRL_TRAINING_PASSED:
 		intel_hdmi->frl.trained = true;
 		intel_hdmi->frl.rate_gbps = req_rate;
-		intel_hdmi->frl.ffe_level = ffe_level;
+		intel_hdmi->frl.max_ffe_level = ffe_level;
 		drm_dbg_kms(display->drm,
 			    "[CONNECTOR:%d:%s] FRL Training Passed with rate=%d\n",
 			    connector->base.id, connector->name,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 59a561ad28e0..5baa38d326e5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -68,6 +68,8 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state);
 void intel_hdmi_disable_frl(struct intel_encoder *encoder,
 			    const struct intel_crtc_state *crtc_state);
+void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state);
+int intel_hdmi_frl_level(struct intel_encoder *encoder, int lane);
 void hsw_write_infoframe(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state,
 			 unsigned int type,
-- 
2.50.1

[PATCH v2 18/56] drm/i915/hdmi: Drive per-lane TxFFE during FRL link training

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

Hook the per-lane TxFFE state added by the previous patch into the
HDMI FRL Link Training Sequence (LTS:3):

 - Advertise FFE_Levels=3 (TxFFE0..TxFFE3) in SCDC 0x31, matching the
   four TxFFE rows present in the PHY HDMI FRL buf-trans table.

 - On LTS:3 entry, after enabling TRANS_HDMI_FRL_ENABLE, call
   encoder->set_signal_levels() so the PHY is programmed to TxFFE0
   on every lane before the sink starts emitting Ln(x)_LTP_req.

 - In intel_hdmi_train_lanes(), handle SCDC_FRL_CHNG_FFE (0xE) by
   incrementing intel_hdmi->frl.ffe_level[lane], capped at
   max_ffe_level. When any lane changed, reprogram the PHY via
   encoder->set_signal_levels() before acknowledging the request.

 - Always clear SCDC FLT_update (0x10 bit 5) after acting on a sink
   request, as required by the HDMI spec.

A forward declaration of clear_scdc_update_flags() is added so it
can be called from intel_hdmi_train_lanes() without reordering the
file.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 27 +++++++++++++++--------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0873ecd6ef71..1aa6f71fbfce 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3581,6 +3581,7 @@ static int clear_scdc_update_flags(struct intel_encoder *encoder, u8 flags)
 
 static bool
 intel_hdmi_frl_prepare_lts2(struct intel_encoder *encoder,
+			    const struct intel_crtc_state *crtc_state,
 			    int frl_rate, int frl_lanes,
 			    int ffe_level)
 {
@@ -3619,7 +3620,8 @@ intel_hdmi_frl_prepare_lts2(struct intel_encoder *encoder,
 	if (ret & SCDC_FLT_UPDATE)
 		clear_scdc_update_flags(encoder, SCDC_FLT_UPDATE);
 
-	/* #TODO: Source shall program TxFFE = 0 for all active lanes */
+	/* ffe_level[] was cleared by intel_hdmi_reset_frl_config(). */
+	encoder->set_signal_levels(encoder, crtc_state);
 
 	if (drm_scdc_config_frl(adapter, frl_rate, frl_lanes, ffe_level) < 0) {
 		drm_dbg_kms(display->drm,
@@ -3654,9 +3656,11 @@ intel_hdmi_train_lanes(struct intel_encoder *encoder,
 		       int ffe_level)
 {
 	struct intel_display *display = to_intel_display(encoder);
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 	enum transcoder trans = crtc_state->cpu_transcoder;
 	int num_lanes = crtc_state->frl.required_lanes;
 	enum drm_scdc_frl_ltp ltp[4];
+	bool ffe_changed = false;
 	u32 write_buf = 0;
 	int update_flags;
 	int lane;
@@ -3684,16 +3688,20 @@ intel_hdmi_train_lanes(struct intel_encoder *encoder,
 		if (ltp[lane] == SCDC_FRL_LTP3)
 			continue;
 
-		if (ltp[lane] >= SCDC_FRL_LTP1 && ltp[lane] <= SCDC_FRL_LTP8)
+		if (ltp[lane] >= SCDC_FRL_LTP1 && ltp[lane] <= SCDC_FRL_LTP8) {
 			write_buf |= TRANS_HDMI_FRL_LTP(ltp[lane], lane);
-
-		/* #TODO handle FFE change */
-		else if (ltp[lane] == SCDC_FRL_CHNG_FFE)
-			continue;
+		} else if (ltp[lane] == SCDC_FRL_CHNG_FFE &&
+			   intel_hdmi->frl.ffe_level[lane] < intel_hdmi->frl.max_ffe_level) {
+			intel_hdmi->frl.ffe_level[lane]++;
+			ffe_changed = true;
+		}
 	}
 
 	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
 
+	if (ffe_changed)
+		encoder->set_signal_levels(encoder, crtc_state);
+
 	clear_scdc_update_flags(encoder, SCDC_FLT_UPDATE);
 
 	return FRL_TRAIN_CONTINUE;
@@ -3791,9 +3799,9 @@ static int get_next_frl_rate(int curr_rate_gbps)
 	return -EINVAL;
 }
 
-static int get_ffe_level(int rate_gbps)
+static int get_max_ffe_level(int rate_gbps)
 {
-	return 0;
+	return 3;
 }
 
 int intel_hdmi_start_frl(struct intel_encoder *encoder,
@@ -3805,7 +3813,7 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 	struct intel_connector *intel_connector = intel_hdmi->attached_connector;
 	struct drm_connector *connector = &intel_connector->base;
 	int req_rate = crtc_state->frl.required_lanes * crtc_state->frl.required_rate;
-	int ffe_level = get_ffe_level(req_rate);
+	int ffe_level = get_max_ffe_level(req_rate);
 	enum frl_lt_status status;
 	int next_rate = -EINVAL;
 
@@ -3825,6 +3833,7 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
 	intel_hdmi->frl.max_ffe_level = ffe_level;
 
 	if (!intel_hdmi_frl_prepare_lts2(encoder,
+					 crtc_state,
 					 crtc_state->frl.required_rate,
 					 crtc_state->frl.required_lanes,
 					 ffe_level))
-- 
2.50.1

[PATCH v2 19/56] drm/i915/ltphy: Add PLL tables for HDMI FRL

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

Add HDMI FRL Tables for LT PHY i.e for the rates of 3G, 6G, 8G,
10G and 12G.

Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 270 ++++++++++++++++++++
 1 file changed, 270 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 86492651b01d..61bad87eefec 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -950,11 +950,281 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = {
 	},
 };
 
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_3g0 = {
+	.config = {
+		0x85,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x5,  0xa,  0x27, 0x0  },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0x4,  0x9,  0x1,  0x28 },
+		{ 0xf2, 0x2e, 0x83, 0x10 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x24, 0x0,  0x0  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x40, 0xa0, 0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_6g0 = {
+	.config = {
+		0x8d,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x2,  0x8a, 0x27, 0x0  },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0x4,  0x4,  0x80, 0xa8 },
+		{ 0xf2, 0x2e, 0x83, 0x10 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x24, 0x0,  0x0  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x40, 0xa0, 0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_8g0 = {
+	.config = {
+		0x95,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x2,  0x8a, 0x34, 0x0  },
+		{ 0xaa, 0xaa, 0xaa, 0xaa },
+		{ 0x5,  0x4,  0x80, 0xa8 },
+		{ 0xf2, 0x22, 0x83, 0x10 },
+		{ 0x80, 0x0f, 0xf9, 0xb5 },
+		{ 0x84, 0x24, 0x0,  0x0  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x13, 0x29, 0x13 },
+		{ 0x0,  0x40, 0xa0, 0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_10g0 = {
+	.config = {
+		0x1d,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x85,
+		0x85,
+		0x85,
+		0x85,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x86,
+		0x00,
+		0x86,
+		0x86,
+		0x86,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x00,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0x49, 0x20, 0x80 },
+		{ 0x6a, 0xaa, 0xaa, 0xab },
+		{ 0x0,  0x6,  0x4,  0x94 },
+		{ 0xfa, 0x1c, 0x83, 0x11 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x26, 0x4,  0x4  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x45, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x14, 0x2a, 0x14 },
+		{ 0x0,  0x5b, 0xe0, 0x8  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
+static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_12g0 = {
+	.config = {
+		0xa5,
+		0x2d,
+		0x0,
+	},
+	.addr_msb = {
+		0x87,
+		0x87,
+		0x87,
+		0x87,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+		0x88,
+	},
+	.addr_lsb = {
+		0x10,
+		0x0c,
+		0x14,
+		0xe4,
+		0x0c,
+		0x10,
+		0x14,
+		0x18,
+		0x48,
+		0x40,
+		0x4c,
+		0x24,
+		0x44,
+	},
+	.data = {
+		{ 0x0,  0x4c, 0x2,  0x0  },
+		{ 0x1,  0x49, 0x27, 0x0  },
+		{ 0x80, 0x0,  0x0,  0x0  },
+		{ 0x8,  0x4,  0x80, 0xb2 },
+		{ 0xf2, 0x2e, 0x83, 0x10 },
+		{ 0x80, 0x0f, 0xf9, 0x53 },
+		{ 0x84, 0x24, 0x0,  0x0  },
+		{ 0x0,  0xe0, 0x1,  0x0  },
+		{ 0x4b, 0x48, 0x0,  0x0  },
+		{ 0x27, 0x8,  0x0,  0x0  },
+		{ 0x5a, 0x14, 0x29, 0x14 },
+		{ 0x0,  0x40, 0xa0, 0x0  },
+		{ 0x0,  0x0,  0x0,  0x0  },
+	},
+};
+
 static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = {
 	LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252),
 	LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5),
 	LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485),
 	LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94),
+	LT_PHY_PLL_HDMI_PARAMS(300000, xe3plpd_lt_hdmi_3g0),
+	LT_PHY_PLL_HDMI_PARAMS(600000, xe3plpd_lt_hdmi_6g0),
+	LT_PHY_PLL_HDMI_PARAMS(800000, xe3plpd_lt_hdmi_8g0),
+	LT_PHY_PLL_HDMI_PARAMS(1000000, xe3plpd_lt_hdmi_10g0),
+	LT_PHY_PLL_HDMI_PARAMS(1200000, xe3plpd_lt_hdmi_12g0),
 	{}
 };
 
-- 
2.50.1

[PATCH v2 20/56] drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

intel_lt_phy_pll_calc_state() will also take into account the
HDMI FRL tables and use them when the DPLL matches. We
still add a safegaurd to not calculate hdmi pll state if we are
using HDMI FRL.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 61bad87eefec..0e2ebd550bc5 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2042,7 +2042,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
 		}
 	}
 
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+	    !intel_hdmi_is_frl(crtc_state->port_clock)) {
 		hw_state->ltpll.lane_count = crtc_state->lane_count;
 		return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
 							 crtc_state->port_clock);
-- 
2.50.1

[PATCH v2 21/56] drm/i915/ltphy: Calculate port clock for HDMI FRL

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

Define function to get the port clock after we read VDR0_CONFIG.
This helps us determine the port clock for HDMI FRL use case in LT
PHY.

Bspec: 74667, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 23 +++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 0e2ebd550bc5..7ac0888cdf45 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -1501,6 +1501,25 @@ intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
 		     XELPDP_SSC_ENABLE_PLLB, val);
 }
 
+static u32 intel_lt_phy_get_hdmi_frl_clock(u8 rate)
+{
+	switch (rate) {
+	case 0:
+		return 300000;
+	case 1:
+		return 600000;
+	case 2:
+		return 800000;
+	case 3:
+		return 1000000;
+	case 4:
+		return 1200000;
+	default:
+		MISSING_CASE(rate);
+		return 0;
+	}
+}
+
 static u32 intel_lt_phy_get_dp_clock(u8 rate)
 {
 	switch (rate) {
@@ -2000,6 +2019,10 @@ intel_lt_phy_calc_port_clock(struct intel_display *display,
 		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
 				      lt_state->config[0]);
 		clk = intel_lt_phy_get_dp_clock(rate);
+	} else if (mode == MODE_HDMI_FRL) {
+		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
+				      lt_state->config[0]);
+		clk = intel_lt_phy_get_hdmi_frl_clock(rate);
 	} else if (mode == MODE_HDMI_20) {
 		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
 	} else {
-- 
2.50.1

[PATCH v2 22/56] drm/i915/ltphy: Verify HDMI FRL tables

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

Verify the HDMI FRL tables now that they are defined.
Also skip recalculating the HDMI state via port clock for HDMI
FRL use case.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 7ac0888cdf45..4223d806ffd7 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2630,6 +2630,9 @@ static void intel_lt_phy_pll_verify_params(struct intel_display *display,
 	if (!pll_params->is_hdmi)
 		return;
 
+	if (intel_hdmi_is_frl(pll_params->clock_rate))
+		return;
+
 	if (intel_lt_phy_calculate_hdmi_state(&pll_state, pll_params->clock_rate) != 0)
 		return;
 
-- 
2.50.1

[PATCH v2 23/56] drm/i915/ddi_buf: Add Vswing table for HDMI FRL

[Ankit Nautiyal]

From: Suraj Kandpal <suraj.kandpal@intel.com>

Define Vswing table for HDMI FRL to set the signal levels.
This is done for LT PHY which is Xe3PLPD onwards.

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_ddi_buf_trans.c  | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index cc5912178d9c..597bf1c78104 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -10,6 +10,7 @@
 #include "intel_display_types.h"
 #include "intel_display_utils.h"
 #include "intel_dp.h"
+#include "intel_hdmi.h"
 #include "intel_lt_phy.h"
 
 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
@@ -1164,6 +1165,14 @@ static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
 	{ .lt = { 1, 3, 0, 26, 0 } },
 };
 
+static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_hdmi_frl[] = {
+	{ .lt = { 0, 0, 0, 48, 0  } },
+	{ .lt = { 0, 0, 4, 38, 6  } },
+	{ .lt = { 0, 0, 4, 36, 8  } },
+	{ .lt = { 0, 0, 4, 34, 10 } },
+	{ .lt = { 0, 0, 4, 32, 12 } },
+};
+
 static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
 	.entries = _xe3plpd_lt_trans_dp14,
 	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
@@ -1179,6 +1188,11 @@ static const struct intel_ddi_buf_trans xe3plpd_lt_trans_edp = {
 	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_edp),
 };
 
+static const struct intel_ddi_buf_trans xe3plpd_lt_trans_hdmi_frl = {
+	.entries = _xe3plpd_lt_trans_hdmi_frl,
+	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_hdmi_frl),
+};
+
 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
 {
 	return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
@@ -1780,6 +1794,9 @@ xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
 		return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
 		return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
+	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+		 intel_hdmi_is_frl(crtc_state->port_clock))
+		return intel_get_buf_trans(&xe3plpd_lt_trans_hdmi_frl, n_entries);
 	else
 		return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
 }
-- 
2.50.1

[PATCH v2 24/56] drm/i915/hdmi: Add provision for FRL mode while computing output format

[Ankit Nautiyal]

Add a check in compute_config to select FRL mode when TMDS cannot
support the required bandwidth, passing frl_mode flag to the output
format computation.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 34 +++++++++++++++++------
 1 file changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 1aa6f71fbfce..bfec1a808af5 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2195,9 +2195,9 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
 	return -EINVAL;
 }
 
-static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
-				    struct intel_crtc_state *crtc_state,
-				    bool respect_downstream_limits)
+static int intel_hdmi_compute_tmds_clock(struct intel_encoder *encoder,
+					 struct intel_crtc_state *crtc_state,
+					 bool respect_downstream_limits)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	const struct drm_display_mode *adjusted_mode =
@@ -2229,6 +2229,17 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
+				    struct intel_crtc_state *crtc_state,
+				    bool respect_downstream_limits,
+				    bool enable_frl)
+{
+	if (enable_frl)
+		return -EINVAL;
+
+	return intel_hdmi_compute_tmds_clock(encoder, crtc_state, respect_downstream_limits);
+}
+
 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state)
 {
@@ -2284,7 +2295,8 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 					    struct intel_crtc_state *crtc_state,
 					    struct intel_connector *connector,
 					    bool respect_downstream_limits,
-					    enum intel_output_format sink_format)
+					    enum intel_output_format sink_format,
+					    bool enable_frl)
 {
 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 
@@ -2295,7 +2307,7 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 	crtc_state->sink_format = sink_format;
 	crtc_state->output_format = intel_hdmi_output_format(crtc_state);
 
-	return intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
+	return intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits, enable_frl);
 }
 
 static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
@@ -2312,7 +2324,8 @@ static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
 	if (drm_mode_is_420_only(info, adjusted_mode)) {
 		ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 						       respect_downstream_limits,
-						       INTEL_OUTPUT_FORMAT_YCBCR420);
+						       INTEL_OUTPUT_FORMAT_YCBCR420,
+						       false);
 
 		if (ret && !respect_downstream_limits) {
 			drm_dbg_kms(display->drm,
@@ -2320,17 +2333,20 @@ static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
 
 			ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 							       respect_downstream_limits,
-							       INTEL_OUTPUT_FORMAT_RGB);
+							       INTEL_OUTPUT_FORMAT_RGB,
+							       false);
 		}
 	} else {
 		ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 						       respect_downstream_limits,
-						       INTEL_OUTPUT_FORMAT_RGB);
+						       INTEL_OUTPUT_FORMAT_RGB,
+						       false);
 
 		if (ret && drm_mode_is_420_also(info, adjusted_mode))
 			ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 							       respect_downstream_limits,
-							       INTEL_OUTPUT_FORMAT_YCBCR420);
+							       INTEL_OUTPUT_FORMAT_YCBCR420,
+							       false);
 	}
 
 	return ret;
-- 
2.50.1

[PATCH v2 25/56] drm/i915/cx0: Add helper to check if the FRL rate is valid

[Ankit Nautiyal]

Introduce helper intel_cx0_phy_hdmi_frl_rate_valid() to check if the
given FRL rate is supported for the c10/20 Phys.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 23 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 +
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b83f0afaa9b5..d7fefb4871b7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3870,3 +3870,26 @@ void intel_cx0pll_verify_plls(struct intel_display *display)
 	intel_cx0pll_verify_tables(display, xe3lpd_c20_dp_edp_tables);
 	intel_cx0pll_verify_tables(display, mtl_c20_hdmi_tables);
 }
+
+enum drm_mode_status
+intel_cx0_phy_hdmi_frl_rate_valid(struct intel_hdmi *hdmi, int clock_rate)
+{
+	struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
+	const struct intel_cx0pll_params *tables;
+	int i;
+
+	if (intel_encoder_is_c10phy(&dig_port->base))
+		tables = mtl_c10_hdmi_tables;
+	else
+		tables = mtl_c20_hdmi_tables;
+
+	for (i = 0; tables[i].name; i++) {
+		if (!intel_hdmi_is_frl(tables[i].clock_rate))
+			continue;
+
+		if (clock_rate == tables[i].clock_rate)
+			return MODE_OK;
+	}
+
+	return MODE_CLOCK_RANGE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 95c20eb4b4b7..b7785bcebecb 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -84,5 +84,6 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *crtc_state);
 void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder);
+enum drm_mode_status intel_cx0_phy_hdmi_frl_rate_valid(struct intel_hdmi *hdmi, int clock_rate);
 
 #endif /* __INTEL_CX0_PHY_H__ */
-- 
2.50.1

[PATCH v2 26/56] drm/i915/lt_phy: Add helper to check if the FRL rate is valid

[Ankit Nautiyal]

Introduce helper intel_lt_phy_hdmi_frl_rate_valid() to check if the
given FRL rate is supported for the LT Phy.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 4223d806ffd7..ba03e5f1bb87 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2654,3 +2654,19 @@ void intel_lt_phy_verify_plls(struct intel_display *display)
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
 }
+
+enum drm_mode_status intel_lt_phy_hdmi_frl_rate_valid(int clock_rate)
+{
+	const struct intel_lt_phy_pll_params *tables = xe3plpd_lt_hdmi_tables;
+	int i;
+
+	for (i = 0; tables[i].name; i++) {
+		if (!intel_hdmi_is_frl(tables[i].clock_rate))
+			continue;
+
+		if (clock_rate == tables[i].clock_rate)
+			return MODE_OK;
+	}
+
+	return MODE_CLOCK_RANGE;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 16de39484779..20714ecd9f62 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -49,5 +49,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 void intel_lt_phy_verify_plls(struct intel_display *display);
+enum drm_mode_status intel_lt_phy_hdmi_frl_rate_valid(int clock_rate);
 
 #endif /* __INTEL_LT_PHY_H__ */
-- 
2.50.1

[PATCH v2 27/56] drm/i915/hdmi_frl_dfm_regs: Define DFM registers

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add defines for HDMI FRL dataflow metering registers
to take care of DFM values.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../i915/display/intel_hdmi_frl_dfm_regs.h    | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h
new file mode 100644
index 000000000000..bb5cb76b3806
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_HDMI_FRL_DFM_REGS_H__
+#define __INTEL_HDMI_FRL_DFM_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _TRANS_HDMI_FRL_DFMRDCTL_A			0x600bc
+#define TRANS_HDMI_FRL_DFMRDCTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _TRANS_HDMI_FRL_DFMRDCTL_A)
+#define   TB_DIFF_MAX_OFFSET_MASK			REG_GENMASK(8, 0)
+#define   TB_DIFF_MAX_OFFSET(val)			REG_FIELD_PREP(TB_DIFF_MAX_OFFSET_MASK, val)
+
+#define _TRANS_HDMI_FRL_DFMWRCTL_A			0x600c0
+#define TRANS_HDMI_FRL_DFMWRCTL(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _TRANS_HDMI_FRL_DFMWRCTL_A)
+#define  TB_ACTUAL_OFFSET_MASK				REG_GENMASK(8, 0)
+#define  TB_ACTUAL_OFFSET(val)				REG_FIELD_PREP(TB_ACTUAL_OFFSET_MASK, val)
+
+#define _TRANS_HDMI_FRL_DFMTHRSH_A			0x600c4
+#define TRANS_HDMI_FRL_DFMTHRSH(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
+								     trans, \
+								     _TRANS_HDMI_FRL_DFMTHRSH_A)
+#define  RUN_LEN_THRESHOLD_MASK				REG_GENMASK(31, 24)
+#define  RUN_LEN_THRESHOLD(val)				REG_FIELD_PREP(RUN_LEN_THRESHOLD_MASK, val)
+#define  TB_MAX_THRESHOLD_MASK				REG_GENMASK(21, 12)
+#define  TB_MAX_THRESHOLD(val)				REG_FIELD_PREP(TB_MAX_THRESHOLD_MASK, val)
+#define  TB_MIN_THESHOLD_MASK				REG_GENMASK(9, 0)
+#define  TB_MIN_THESHOLD(val)				REG_FIELD_PREP(TB_MIN_THESHOLD_MASK, val)
+
+#endif /* __INTEL_HDMI_FRL_DFM_REGS_H__ */
-- 
2.50.1

[PATCH v2 28/56] drm/i915/hdmi_frl_dfm: Define frl_dfm structure

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Define frl_dfm structure to hold frl characteristics
needed for frl capacity computation in order to
meet the data flow metering requirement.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.h | 113 ++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
new file mode 100644
index 000000000000..c619073eef9b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: MIT
+ * Copyright © 2022 Intel Corp
+ */
+
+#ifndef __INTEL_HDMI_FRL_DFM_H__
+#define __INTEL_HDMI_FRL_DFM_H__
+
+#include <linux/types.h>
+
+/* All the input config needed to compute DFM requirements */
+struct intel_hdmi_frl_dfm_input_config {
+	/*
+	 * Pixel clock rate kHz, when FVA is
+	 * enabled this rate is the rate after adjustment
+	 */
+	u32 pixel_clock_nominal_khz;
+
+	/* active pixels per line */
+	u32 hactive;
+
+	/* Blanking pixels per line */
+	u32 hblank;
+
+	/* Bits per component */
+	u32 bpc;
+
+	/* Pixel encoding */
+	u32 color_format;
+
+	/* FRL bit rate in kbps */
+	u32 bit_rate_kbps;
+
+	/* FRL lanes */
+	u32 lanes;
+
+	/* Number of audio channels */
+	u32 audio_channels;
+
+	/* Audio rate in Hz */
+	u32 audio_hz;
+
+	/* Selected bpp target value */
+	u32 target_bpp_16;
+
+	/*
+	 * Number of horizontal pixels in a slice.
+	 * Equivalent to PPS parameter slice_width
+	 */
+	u32 slice_width;
+};
+
+/* Computed dfm parameters for FRL */
+struct intel_hdmi_frl_dfm_params {
+	/*
+	 * Link overhead in percentage
+	 * multiplied by 1000 (efficiency multiplier)
+	 */
+	u32 overhead_max;
+
+	/* Maximum pixel rate in kHz */
+	u32 pixel_clock_max_khz;
+
+	/* Minimum video line period in nano sec */
+	u32 line_time_ns;
+
+	/* worst case slow frl character rate in kbps */
+	u32 char_rate_min_kbps;
+
+	/* minimum total frl charecters per line period */
+	u32 cfrl_line;
+
+	/* Average tribyte rate in khz */
+	u32 ftb_avg_k;
+
+	/* Audio characteristics */
+
+	/*  number of audio packets needed during hblank */
+	u32 num_audio_pkts_line;
+
+	/*
+	 *  Minimum required hblank assuming no control period
+	 *  RC compression
+	 */
+	u32 hblank_audio_min;
+
+	/* Number of tribytes required to carry active video */
+	u32 tb_active;
+
+	/* Total available tribytes during the blanking period */
+	u32 tb_blank;
+
+	/*
+	 * Number of tribytes required to be transmitted during
+	 * the hblank period
+	 */
+	u32 tb_borrowed;
+
+	/* DSC frl characteristics */
+
+	/* Tribytes required to carry the target bpp */
+	u32 hcactive_target;
+
+	/* tribytes available during blanking with target bpp */
+	u32 hcblank_target;
+};
+
+/* FRL DFM structure to hold data involved in DFM computation */
+struct intel_hdmi_frl_dfm {
+	struct intel_hdmi_frl_dfm_input_config config;
+	struct intel_hdmi_frl_dfm_params params;
+};
+
+#endif
-- 
2.50.1

[PATCH v2 29/56] drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add helper functions for computing non dsc frl
link characteristics

v2:
- Add macro PPM used by the Audio rate and FRl rate Tolerances. (Ankit)
- Derive L-PCM AP factor from channel count instead of hardcoding. (Ankit)
- Return early if available hblank tribytes are not sufficient for
  audio. (Ankit)
- Use 64-bit math for the DFM tri-byte/timing products to avoid u32
  overflow. (Ankit)

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 426 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.h |   2 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 4 files changed, 430 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d4e7764621e1..d6abb79d5696 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -368,6 +368,7 @@ i915-y += \
 	display/intel_encoder.o \
 	display/intel_gmbus.o \
 	display/intel_hdmi.o \
+	display/intel_hdmi_frl_dfm.o \
 	display/intel_lspcon.o \
 	display/intel_lt_phy.o \
 	display/intel_lvds.o \
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
new file mode 100644
index 000000000000..2381ad2a3fc4
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corp
+ */
+
+#include <linux/kernel.h>
+
+#include <drm/drm_connector.h>
+
+#include "intel_hdmi_frl_dfm.h"
+
+/* DFM constraints and tolerance values */
+#define TB_BORROWED_MAX			400
+#define FRL_CHAR_PER_CHAR_BLK		510
+/* Tolerance pixel clock unit is in  mHz */
+#define TOLERANCE_PIXEL_CLOCK		5
+
+/* ppm base for the tolerances below */
+#define PARTS_PER_MILLION		1000000
+#define TOLERANCE_FRL_BIT_RATE		300
+#define TOLERANCE_AUDIO_CLOCK		1000
+#define ACR_RATE_MAX			1500
+#define EFFICIENCY_MULTIPLIER		1000
+#define OVERHEAD_M			(3 * EFFICIENCY_MULTIPLIER / 1000)
+#define BPP_MULTIPLIER			16
+#define FRL_TIMING_NS_MULTIPLIER	1000000000
+
+/* Total FRL characters per super block */
+static u32 get_frl_char_per_super_blk(u32 lanes)
+{
+	return (4 * FRL_CHAR_PER_CHAR_BLK) + lanes;
+}
+
+/* Total minimum overhead multiplied by EFFICIENCY_MULIPLIER */
+static u32 get_total_minimum_overhead(u32 lanes)
+{
+	u32 overhead_sb;
+	u32 overhead_rs;
+	u32 overhead_map;
+
+	/*
+	 * Determine the overhead due to the inclusion of
+	 * the SR and SSB FRL characters used for
+	 * super block framing
+	 */
+	overhead_sb = (lanes * EFFICIENCY_MULTIPLIER) / get_frl_char_per_super_blk(lanes);
+
+	/*
+	 * Determine the overhead due to the inclusion of RS FEC pairity
+	 * symbols. Each character block uses 8 FRL characters for RS Pairity
+	 * and there are 4 character blocks per super block
+	 */
+	overhead_rs = (8 * 4 * EFFICIENCY_MULTIPLIER) /  get_frl_char_per_super_blk(lanes);
+
+	/*
+	 * Determine the overhead due to FRL Map characters.
+	 * In a bandwidth constrained application, the FRL packets will be long,
+	 * there will typically be two FRL Map Characters per Super Block most of the time.
+	 * When a tracnsition occurs between Hactive and Hblank (uncomperssed video) or
+	 * HCactive and HCblank (compressed video transport), there may be a
+	 * third FRL Map Charecter. Therefore this spec assumes 2.5 FRL Map Characters
+	 * per Super Block.
+	 */
+	overhead_map =
+		(25  * EFFICIENCY_MULTIPLIER) / (10 * get_frl_char_per_super_blk(lanes));
+
+	return overhead_sb + overhead_rs + overhead_map;
+}
+
+/* Audio Support Verification Computations */
+
+/*
+ * During the Hblank period, Audio packets (32 frl characters each),
+ * ACR packets (32 frl characters each), Island guard band (4 total frl characters)
+ * and Video guard band (3 frl characters) do not benefit from RC compression
+ * Therefore start by determining the number of Control Characters that maybe
+ * RC compressible
+ */
+static u32
+get_num_char_rc_compressible(u32 color_format, u32 bpc,
+			     u32 audio_packets_line, u32 hblank)
+{
+	u32 cfrl_free;
+	u32 kcdx100, k420;
+
+	if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
+		k420 = 2;
+	else
+		k420 = 1;
+
+	if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422)
+		kcdx100 = 100;
+	else
+		kcdx100 = (100 * bpc) / 8;
+
+	cfrl_free = max(((hblank * kcdx100) / (100 * k420) - 32 * audio_packets_line - 7),
+			U32_MIN);
+
+	return cfrl_free;
+}
+
+/*
+ * Determine the actual number of characters made available by
+ * RC compression
+ */
+static u32
+get_num_char_compression_savings(u32 cfrl_free)
+{
+	/*
+	 * In order to be conservative, situations are considered where
+	 * maximum RC compression may not be possible.
+	 * Add one character each for RC break caused by:
+	 * • Island Preamble not aligned to the RC Compression
+	 * • Video Preamble not aligned to the RC Compression
+	 * • HSYNC lead edge not aligned to the RC Compression
+	 * • HSYNC trail edge not aligned to the RC Compression
+	 */
+	const u32 cfrl_margin = 4;
+	u32 cfrl_savings = max(((7 * cfrl_free) / 8) - cfrl_margin, U32_MIN);
+
+	return cfrl_savings;
+}
+
+static u32
+get_frl_bits_per_pixel(u32 color_format, u32 bpc)
+{
+	u32 kcdx100, k420;
+
+	if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
+		k420 = 2;
+	else
+		k420 = 1;
+
+	if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422)
+		kcdx100 = 100;
+	else
+		kcdx100 = (100 * bpc) / 8;
+
+	return (24 * kcdx100) / (100 * k420);
+}
+
+/* Determine the total available tribytes during the blanking period */
+static u32
+get_blanking_tribytes_avail(u32 color_format,
+			    u32 hblank, u32 bpc)
+{
+	u32 kcdx100, k420;
+
+	if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR420)
+		k420 = 2;
+	else
+		k420 = 1;
+
+	if (color_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422)
+		kcdx100 = 100;
+	else
+		kcdx100 = (100 * bpc) / 8;
+
+	return DIV_ROUND_UP((hblank * kcdx100), (100 * k420));
+}
+
+/*
+ * Determine the minimum time necessary to transmit the active tribytes
+ * considering frl bandwidth limitation.
+ * Given the available bandwidth (i.e after overhead is considered),
+ * tactive_min represents the amount of time needed to transmit all the
+ * active data
+ */
+static u32
+get_tactive_min(u32 num_lanes, u32 tribyte_active,
+		u32 overhead_max_k, u32 frl_char_min_rate_k)
+{
+	u32 active_bytes, rate_kbps, efficiency_k, effective_rate_kbps;
+
+	active_bytes = (3 * tribyte_active) / 2;
+	rate_kbps = num_lanes * frl_char_min_rate_k;
+	efficiency_k = EFFICIENCY_MULTIPLIER - overhead_max_k;
+	effective_rate_kbps = mult_frac(rate_kbps, efficiency_k, EFFICIENCY_MULTIPLIER);
+
+	return div_u64(mul_u32_u32(FRL_TIMING_NS_MULTIPLIER, active_bytes),
+		       effective_rate_kbps) / 1000;
+}
+
+/*
+ * Determine the minimum time necessary to transmit the video blanking
+ * tribytes considering frl bandwidth limitations
+ */
+static u32
+get_tblank_min(u32 num_lanes, u32 tribyte_blank,
+	       u32 overhead_max_k, u32 frl_char_min_rate_k)
+{
+	u32 blank_bytes, rate_kbps, efficiency_k, effective_rate_kbps;
+
+	blank_bytes = (3 * tribyte_blank) / 2;
+	rate_kbps = num_lanes * frl_char_min_rate_k;
+	efficiency_k = EFFICIENCY_MULTIPLIER - overhead_max_k;
+	effective_rate_kbps = mult_frac(rate_kbps, efficiency_k, EFFICIENCY_MULTIPLIER);
+
+	return div_u64(mul_u32_u32(FRL_TIMING_NS_MULTIPLIER, blank_bytes),
+		       effective_rate_kbps) / 1000;
+}
+
+/* Collect link characteristics */
+static void
+compute_link_characteristics(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 frl_bit_rate_min_kbps, line_width, rate_m;
+
+	/* Determine the maximum legal pixel rate */
+	frl_dfm->params.pixel_clock_max_khz =
+		(frl_dfm->config.pixel_clock_nominal_khz * (1000 + TOLERANCE_PIXEL_CLOCK)) / 1000;
+
+	/* Determine the minimum Video Line period */
+	line_width = frl_dfm->config.hactive + frl_dfm->config.hblank;
+
+	frl_dfm->params.line_time_ns =
+		div_u64(mul_u32_u32(FRL_TIMING_NS_MULTIPLIER, line_width),
+			frl_dfm->params.pixel_clock_max_khz) / 1000;
+
+	/* Determine the worst-case slow FRL Bit Rate in kbps*/
+	frl_bit_rate_min_kbps =
+		(frl_dfm->config.bit_rate_kbps / PARTS_PER_MILLION) *
+		(PARTS_PER_MILLION - TOLERANCE_FRL_BIT_RATE);
+
+	/* Determine the worst-case slow FRL Character Rate */
+	frl_dfm->params.char_rate_min_kbps = frl_bit_rate_min_kbps / 18;
+
+	/* Character rate in mega chars/sec */
+	rate_m = DIV_ROUND_UP(frl_dfm->params.char_rate_min_kbps * frl_dfm->config.lanes, 1000);
+
+	/* Determine the Minimum Total FRL characters per line period */
+	frl_dfm->params.cfrl_line = DIV_ROUND_UP(frl_dfm->params.line_time_ns * rate_m,
+						 FRL_TIMING_NS_MULTIPLIER / 1000000);
+}
+
+/* Determine FRL link overhead */
+static void compute_max_frl_link_overhead(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 overhead_min = get_total_minimum_overhead(frl_dfm->config.lanes);
+
+	/*
+	 * Additional margin to the overhead is provided to account for the possibility
+	 * of more Map Characters, zero padding at the end of HCactive, and other minor
+	 * items
+	 */
+	frl_dfm->params.overhead_max = overhead_min + OVERHEAD_M;
+}
+
+/* Audio support Verification computations */
+static void
+compute_audio_hblank_min(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u64 num_audio_pkt_x100, rate;
+	u32 audio_pkt_rate;
+
+	/*
+	 * #TODO: get the actual audio pkt type for the AP factor
+	 * For now consider only L-PCM:
+	 * Layout 0 (<= 2ch) AP = 0.25
+	 * Layout 1 (> 2 ch) AP = 1.0
+	 * Scale x100.
+	 */
+	num_audio_pkt_x100 = (frl_dfm->config.audio_channels <= 2) ? 25 : 100;
+
+	/*
+	 * Determine Audio Related Packet Rate considering the audio clock
+	 * increased to maximim rate permitted by Tolerance Audio clock
+	 */
+	rate = frl_dfm->config.audio_hz *  num_audio_pkt_x100 + (2 * ACR_RATE_MAX * 100);
+
+	audio_pkt_rate = DIV64_U64_ROUND_UP(rate * (PARTS_PER_MILLION + TOLERANCE_AUDIO_CLOCK),
+					    (u64)PARTS_PER_MILLION * 100);
+
+	/*
+	 * Average required packets per line is
+	 * number of audio packets needed during Hblank
+	 */
+	frl_dfm->params.num_audio_pkts_line =
+		DIV_ROUND_UP(audio_pkt_rate * frl_dfm->params.line_time_ns,
+			     FRL_TIMING_NS_MULTIPLIER);
+
+	/*
+	 * Minimum required Hblank assuming no Control Period RC Compression
+	 * This includes Video Guard band, Two Island Guard bands, two 12 character
+	 * Control Periods and 32 * AudioPackets_Line.
+	 * In addition, 32 character periods are allocated for the transmission of an
+	 * ACR packet
+	 */
+	frl_dfm->params.hblank_audio_min = 32 + 32 * frl_dfm->params.num_audio_pkts_line;
+}
+
+/*
+ * Determine the number of tribytes required for active video , blanking period
+ * with the pixel configuration
+ */
+static void
+compute_tbactive_tbblank(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 bpp, bytes_per_line;
+
+	bpp = get_frl_bits_per_pixel(frl_dfm->config.color_format, frl_dfm->config.bpc);
+	bytes_per_line = (bpp * frl_dfm->config.hactive) / 8;
+
+	frl_dfm->params.tb_active = DIV_ROUND_UP(bytes_per_line, 3);
+
+	frl_dfm->params.tb_blank =
+		get_blanking_tribytes_avail(frl_dfm->config.color_format,
+					    frl_dfm->config.hblank,
+					    frl_dfm->config.bpc);
+}
+
+/* Verify the configuration meets the capacity requirements for the FRL configuration*/
+static bool
+verify_frl_capacity_requirement(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 tactive_ref_ns, tblank_ref_ns, tactive_min_ns, tblank_min_ns;
+	u32 tborrowed_ns;
+	u32 line_time_ns = frl_dfm->params.line_time_ns;
+	u32 hactive = frl_dfm->config.hactive;
+	u32 hblank = frl_dfm->config.hblank;
+
+	/* Determine the average tribyte rate in kilo tribytes per sec */
+	frl_dfm->params.ftb_avg_k =
+		div_u64(mul_u32_u32(frl_dfm->params.pixel_clock_max_khz,
+				    frl_dfm->params.tb_active + frl_dfm->params.tb_blank),
+			frl_dfm->config.hactive + frl_dfm->config.hblank);
+	/*
+	 * Determine the time required to transmit the active portion of the
+	 * minimum possible active line period in the base timing
+	 */
+	tactive_ref_ns = (line_time_ns * hactive) / (hblank + hactive);
+
+	/*
+	 * Determine the time required to transmit the Video blanking portion
+	 * of the minimum possible active line period in the base timing
+	 */
+	tblank_ref_ns = (line_time_ns * hblank) / (hblank + hactive);
+
+	tactive_min_ns = get_tactive_min(frl_dfm->config.lanes,
+					 frl_dfm->params.tb_active,
+					 frl_dfm->params.overhead_max,
+					 frl_dfm->params.char_rate_min_kbps);
+	tblank_min_ns = get_tblank_min(frl_dfm->config.lanes,
+				       frl_dfm->params.tb_blank,
+				       frl_dfm->params.overhead_max,
+				       frl_dfm->params.char_rate_min_kbps);
+
+	if (tactive_ref_ns >= tactive_min_ns &&
+	    tblank_ref_ns >= tblank_min_ns) {
+		tborrowed_ns = 0;
+		frl_dfm->params.tb_borrowed = 0;
+
+		return true;
+	}
+
+	if (tactive_ref_ns < tactive_min_ns &&
+	    tblank_ref_ns >= tblank_min_ns) {
+		tborrowed_ns = tactive_min_ns - tactive_ref_ns;
+		/* Determine the disparity in tribytes */
+		frl_dfm->params.tb_borrowed =
+			DIV_ROUND_UP_ULL(mul_u32_u32(tborrowed_ns, frl_dfm->params.ftb_avg_k) * 1000,
+					 FRL_TIMING_NS_MULTIPLIER);
+
+		if (frl_dfm->params.tb_borrowed <= TB_BORROWED_MAX)
+			return true;
+	}
+
+	return false;
+}
+
+/* Verify utilization does not exceed capacity */
+static bool
+verify_utilization_possible(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 cfrl_free, cfrl_savings, frl_char_payload_actual;
+	u32 utilization, margin;
+
+	cfrl_free = get_num_char_rc_compressible(frl_dfm->config.color_format,
+						 frl_dfm->config.bpc,
+						 frl_dfm->params.num_audio_pkts_line,
+						 frl_dfm->config.hblank);
+	cfrl_savings = get_num_char_compression_savings(cfrl_free);
+
+	/*
+	 * Determine the actual number of payload FRL characters required to
+	 * carry each video line
+	 */
+	frl_char_payload_actual =
+		DIV_ROUND_UP(3 * frl_dfm->params.tb_active, 2) +
+		frl_dfm->params.tb_blank - cfrl_savings;
+
+	/*
+	 * Determine the payload utilization of the total number of
+	 * FRL characters
+	 */
+	utilization = (frl_char_payload_actual * EFFICIENCY_MULTIPLIER) / frl_dfm->params.cfrl_line;
+
+	margin = 1000 - (utilization + frl_dfm->params.overhead_max);
+
+	if (margin > 0)
+		return true;
+
+	return false;
+}
+
+/* Check if DFM requirement is met */
+bool
+intel_hdmi_frl_dfm_nondsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	bool frl_capacity_req_met;
+
+	compute_max_frl_link_overhead(frl_dfm);
+	compute_link_characteristics(frl_dfm);
+	compute_audio_hblank_min(frl_dfm);
+	compute_tbactive_tbblank(frl_dfm);
+
+	if (frl_dfm->params.hblank_audio_min > frl_dfm->params.tb_blank)
+		return false;
+
+	frl_capacity_req_met = verify_frl_capacity_requirement(frl_dfm);
+
+	if (frl_capacity_req_met)
+		return verify_utilization_possible(frl_dfm);
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
index c619073eef9b..83d5b0d6370b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
@@ -110,4 +110,6 @@ struct intel_hdmi_frl_dfm {
 	struct intel_hdmi_frl_dfm_params params;
 };
 
+bool intel_hdmi_frl_dfm_nondsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm);
+
 #endif
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 563c2f859361..b950ea6bb303 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -308,6 +308,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_hdcp.o \
 	i915-display/intel_hdcp_gsc_message.o \
 	i915-display/intel_hdmi.o \
+	i915-display/intel_hdmi_frl_dfm.o \
 	i915-display/intel_hotplug.o \
 	i915-display/intel_hotplug_irq.o \
 	i915-display/intel_hti.o \
-- 
2.50.1

[PATCH v2 30/56] drm/i915/hdmi_frl_dfm: Add support for DFM calculation with DSC

[Ankit Nautiyal]

Add helper functions for calculating FRL capacity and DFM
requirements with given compressed bpp.

v2: Fix misc issues seen while testing (Mitul)
v3: Compute the DSC tri-byte time and tb_delta/tb_borrowed with 64-bit
    helpers (mul_u32_u32/div64_u64) to avoid u32 overflow.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 295 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.h |   3 +
 2 files changed, 298 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
index 2381ad2a3fc4..fe1df69a1096 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
@@ -424,3 +424,298 @@ intel_hdmi_frl_dfm_nondsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm)
 
 	return false;
 }
+
+/* Get required no. of tribytes (estimate1) during HCBlank */
+static u32
+get_frl_hcblank_tb_est1_target(u32 hcactive_target_tb,
+			       u32 hactive, u32 hblank)
+{
+	return DIV_ROUND_UP(hcactive_target_tb * hblank, hactive);
+}
+
+/* Get required no. of tribytes during HCBlank */
+static u32
+get_frl_hcblank_tb_target(u32 hcactive_target_tb, u32 hactive,
+			  u32 hblank, u32 hcblank_audio_min,
+			  u32 cfrl_available)
+{
+	u32 hcblank_target_tb1 = get_frl_hcblank_tb_est1_target(hcactive_target_tb,
+									 hactive, hblank);
+	u32 hcblank_target_tb2 = max(hcblank_target_tb1, hcblank_audio_min);
+
+	return 4 * (min(hcblank_target_tb2,
+			(2 * cfrl_available - 3 * hcactive_target_tb) / 2) / 4);
+}
+
+static u32
+get_dsc_tribyte_time(u32 num_tribyte,
+		     u32 tribyte_rate_k)
+{
+	u32 time_multiplier;
+	u64 tribyte_time;
+
+	/*
+	 * tribyte_rate_k is the num of kilo tribytes in 1 sec, on an average.
+	 *
+	 * time taken for:
+	 * (tribyte_rate_k * 1000) tribytes -> 1 sec
+	 * (tribyte_rate_k * 1000) tribytes -> 10^9 nsec
+	 * 1000 tribytes                    -> (10^9 / tribyte_rate_k) nsec
+	 * 1 tribyte                        -> 10^9 / tribyte_rate_k * 1000)
+	 * 1 tribyte                        -> 10^6 / tribyte_rate_k
+	 * tribyte_time			    -> num_tribyte * 10 ^ 6 / (tribyte_rate_k)
+	 *
+	 * So, avg time for tribyte_time in nsec =
+	 *				num_tribyte * 10 ^ 6 / (tribyte_rate_k)
+	 */
+	time_multiplier = DIV_ROUND_UP(FRL_TIMING_NS_MULTIPLIER, 1000);
+	tribyte_time = mul_u32_u32(num_tribyte, time_multiplier);
+
+	return DIV_ROUND_UP_ULL(tribyte_time, tribyte_rate_k);
+}
+
+/* Get time to send all tribytes in hcactive region in nsec*/
+static u32
+get_dsc_tactive_target_ns(u32 frl_lanes, u32 hcactive_target_tb,
+			  u32 ftb_avg_k, u32 min_frl_char_rate_k,
+			  u32 overhead_max)
+{
+	u32 avg_tribyte_time_ns, tribyte_time_ns;
+	u32 num_chars_hcactive;
+	u32 frl_char_rate_k;
+
+	/* Avg time to transmit all active region tribytes */
+	avg_tribyte_time_ns = get_dsc_tribyte_time(hcactive_target_tb, ftb_avg_k);
+
+	/*
+	 * 2 bytes in active region = 1 FRL characters
+	 * 1 Tribyte in active region = 3/2 FRL characters
+	 */
+	num_chars_hcactive = DIV_ROUND_UP(hcactive_target_tb * 3, 2);
+
+	/*
+	 * FRL rate = lanes * frl character rate
+	 * But actual bandwidth wil be less, due to FRL limitations so account
+	 * for the overhead involved.
+	 * FRL rate with overhead = FRL rate * (100 - overhead %) / 100
+	 */
+	frl_char_rate_k = frl_lanes * min_frl_char_rate_k;
+	frl_char_rate_k = DIV_ROUND_UP_ULL(mul_u32_u32(frl_char_rate_k,
+						       EFFICIENCY_MULTIPLIER - overhead_max),
+					   EFFICIENCY_MULTIPLIER);
+
+	/* Time to transmit all characters with FRL limitations */
+	tribyte_time_ns	= get_dsc_tribyte_time(num_chars_hcactive, frl_char_rate_k);
+	return max(avg_tribyte_time_ns, tribyte_time_ns);
+}
+
+/* Get TBdelta : borrowing in tribytes relative to avg tribyte rate */
+static u32
+get_dsc_tri_bytes_delta(u32 tactive_target_ns, u32 tblank_target_ns,
+			u32 tactive_ref_ns, u32 tblank_ref_ns,
+			u32 hcactive_target_tb, u32 ftb_avg_k,
+			u32 hactive, u32 hblank,
+			u32 line_time_ns)
+{
+	u32 tb_delta_limit;
+	u32 hcblank_target_tb1 = get_frl_hcblank_tb_est1_target(hcactive_target_tb,
+								    hactive, hblank);
+	u32 tribytes = (hcactive_target_tb + hcblank_target_tb1);
+	u32 tactive_avg_ns;
+
+	if (tblank_ref_ns < tblank_target_ns) {
+		tactive_avg_ns =
+			div64_u64(mul_u32_u32(FRL_TIMING_NS_MULTIPLIER, hcactive_target_tb),
+				  mul_u32_u32(ftb_avg_k, 1000));
+		tb_delta_limit =
+			DIV_ROUND_UP_ULL(mul_u32_u32(tactive_ref_ns - tactive_avg_ns, tribytes),
+					 line_time_ns);
+	} else {
+		u32 t_delta_ns;
+
+		if (tactive_target_ns > tactive_ref_ns)
+			t_delta_ns = tactive_target_ns - tactive_ref_ns;
+		else
+			t_delta_ns = tactive_ref_ns - tactive_target_ns;
+		tb_delta_limit = div_u64(mul_u32_u32(t_delta_ns, tribytes), line_time_ns);
+	}
+
+	return tb_delta_limit;
+}
+
+static u32
+get_dsc_tri_bytes_borrowed(u32 ftb_avg_k,
+			   u32 tactive_target_ns,
+			   u32 hcactive_target)
+{
+	u32 hactive, tb_borrowed;
+
+	hactive = DIV_ROUND_UP_ULL(mul_u32_u32(tactive_target_ns,
+					       DIV_ROUND_UP(ftb_avg_k, 1000)),
+				   1000);
+	tb_borrowed = hactive - hcactive_target;
+
+	return tb_borrowed;
+}
+
+/* Compute hcactive and hcblank tribytes for given dsc bpp setting */
+static void
+compute_dsc_tribytes(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 hcactive_target_tb;
+	u32 hcblank_target_tb;
+	u32 cfrl_available;
+	u32 num_slices;
+	u32 bytes_target;
+
+	/* Assert for slice width ?*/
+	if (!frl_dfm->config.slice_width)
+		return;
+
+	num_slices = DIV_ROUND_UP(frl_dfm->config.hactive, frl_dfm->config.slice_width);
+
+	/* Get required no. of tribytes during HCActive */
+	bytes_target = num_slices *
+		       DIV_ROUND_UP(frl_dfm->config.target_bpp_16 * frl_dfm->config.slice_width,
+				    8 * BPP_MULTIPLIER);
+
+	hcactive_target_tb = DIV_ROUND_UP(bytes_target, 3);
+
+	/* Get FRL Available characters */
+	cfrl_available = ((EFFICIENCY_MULTIPLIER - frl_dfm->params.overhead_max) *
+			  frl_dfm->params.cfrl_line) / EFFICIENCY_MULTIPLIER;
+
+	hcblank_target_tb =
+		get_frl_hcblank_tb_target(hcactive_target_tb,
+					  frl_dfm->config.hactive,
+					  frl_dfm->config.hblank,
+					  frl_dfm->params.hblank_audio_min,
+					  cfrl_available);
+
+	frl_dfm->params.hcactive_target = hcactive_target_tb;
+	frl_dfm->params.hcblank_target = hcblank_target_tb;
+}
+
+/* Check if audio supported with given dsc bpp and frl bandwidth */
+static bool
+audio_supported_with_dsc(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	return frl_dfm->params.hcblank_target >= frl_dfm->params.hblank_audio_min;
+}
+
+/* Is DFM timing requirement is met with DSC */
+static
+bool timing_req_met_with_dsc(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 ftb_avg_k;
+	u32 tactive_ref_ns, tblank_ref_ns, tactive_target_ns, tblank_target_ns;
+	u32 tb_borrowed, tb_delta, tb_worst;
+
+	/* Get the avg no of tribytes sent per sec (Kbps) */
+	ftb_avg_k = (frl_dfm->params.hcactive_target + frl_dfm->params.hcblank_target) *
+		    DIV_ROUND_UP(frl_dfm->params.pixel_clock_max_khz,
+				 frl_dfm->config.hactive + frl_dfm->config.hblank);
+
+	/* Time to send Active tribytes in nanoseconds */
+	tactive_ref_ns = DIV_ROUND_UP(frl_dfm->params.line_time_ns * frl_dfm->config.hactive,
+				      frl_dfm->config.hactive + frl_dfm->config.hblank);
+
+	/* Time to send Blanking tribytes in nanoseconds */
+	tblank_ref_ns = DIV_ROUND_UP(frl_dfm->params.line_time_ns * frl_dfm->config.hblank,
+				     frl_dfm->config.hactive + frl_dfm->config.hblank);
+
+	tactive_target_ns = get_dsc_tactive_target_ns(frl_dfm->config.lanes,
+						      frl_dfm->params.hcactive_target,
+						      ftb_avg_k,
+						      frl_dfm->params.char_rate_min_kbps,
+						      frl_dfm->params.overhead_max);
+
+	tblank_target_ns = frl_dfm->params.line_time_ns - tactive_target_ns;
+
+	/* Get no. of tri bytes borrowed with DSC enabled */
+	tb_borrowed = get_dsc_tri_bytes_borrowed(ftb_avg_k,
+						 tactive_target_ns,
+						 frl_dfm->params.hcactive_target);
+
+	tb_delta = get_dsc_tri_bytes_delta(tactive_target_ns,
+					   tblank_target_ns,
+					   tactive_ref_ns,
+					   tblank_ref_ns,
+					   frl_dfm->params.hcactive_target,
+					   ftb_avg_k,
+					   frl_dfm->config.hactive,
+					   frl_dfm->config.hblank,
+					   frl_dfm->params.line_time_ns);
+
+	tb_worst = max(tb_borrowed, tb_delta);
+	if (tb_worst > TB_BORROWED_MAX)
+		return false;
+
+	frl_dfm->params.ftb_avg_k = ftb_avg_k;
+	frl_dfm->params.tb_borrowed = tb_borrowed;
+
+	return true;
+}
+
+/* Check Utilization constraint with DSC */
+static bool
+utilization_constraints_met_with_dsc(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	u32 hcactive_target_tb = frl_dfm->params.hcactive_target;
+	u32 hcblank_target_tb = frl_dfm->params.hcblank_target;
+	u32 frl_char_per_line = frl_dfm->params.cfrl_line;
+	u32 overhead_max = frl_dfm->params.overhead_max;
+	u32 utilization_with_overhead;
+	u32 actual_frl_char_payload;
+	u32 utilization;
+
+	/*
+	 * Note:
+	 * 1 FRL characters per 2 bytes in active period
+	 * 1 FRL char per byte in Blanking period
+	 */
+	actual_frl_char_payload = DIV_ROUND_UP(3 * hcactive_target_tb, 2) +
+				  hcblank_target_tb;
+
+	utilization = (actual_frl_char_payload * EFFICIENCY_MULTIPLIER) /
+		      frl_char_per_line;
+
+	/*
+	 * Utilization with overhead = utlization% +overhead %
+	 * should be less than 100%
+	 */
+	utilization_with_overhead = utilization + overhead_max;
+	if (utilization_with_overhead  > EFFICIENCY_MULTIPLIER)
+		return false;
+
+	return true;
+}
+
+/*
+ * intel_hdmi_frl_dfm_dsc_requirement_met : Check if FRL DFM requirements are met with
+ * the given bpp.
+ * @frl_dfm: dfm structure
+ *
+ * Returns true if the frl dfm requirements are met, else returns false.
+ */
+bool intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm)
+{
+	if (!frl_dfm->config.slice_width || !frl_dfm->config.target_bpp_16)
+		return false;
+
+	compute_max_frl_link_overhead(frl_dfm);
+	compute_link_characteristics(frl_dfm);
+	compute_audio_hblank_min(frl_dfm);
+	compute_dsc_tribytes(frl_dfm);
+
+	if (!audio_supported_with_dsc(frl_dfm))
+		return false;
+
+	if (!timing_req_met_with_dsc(frl_dfm))
+		return false;
+
+	if (!utilization_constraints_met_with_dsc(frl_dfm))
+		return false;
+
+	return true;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
index 83d5b0d6370b..70a66679bdbc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
@@ -112,4 +112,7 @@ struct intel_hdmi_frl_dfm {
 
 bool intel_hdmi_frl_dfm_nondsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm);
 
+bool
+intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm);
+
 #endif
-- 
2.50.1

[PATCH v2 31/56] drm/i915/hdmi: Add helper to write FRL CFG register

[Ankit Nautiyal]

Introduce helpers to write FRL CFG refister bits.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 16 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  1 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index bfec1a808af5..db996b696847 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3919,3 +3919,19 @@ void intel_hdmi_disable_frl(struct intel_encoder *encoder,
 
 	intel_hdmi_reset_frl_config(intel_hdmi);
 }
+
+void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	val = TRANS_HDMI_R_B_SCHED_ENABLE(crtc_state->frl.rsrc_sched_en);
+	val |= TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(crtc_state->frl.active_char_buf_threshold);
+	val |= TRANS_HDMI_MIN_BLANK_CHAR(TRANS_HDMI_MIN_BLANK_CHAR_VAL);
+
+	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 5baa38d326e5..6e0b5fb1930a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -83,5 +83,6 @@ void intel_hdmi_poll_for_scrambling_enable(const struct intel_crtc_state *crtc_s
 
 int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector);
 int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector);
+void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_HDMI_H__ */
-- 
2.50.1

[PATCH v2 32/56] drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers

[Ankit Nautiyal]

Introduce helpers to read/write FRL Data Flow Metering registers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 42 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.h |  5 +++
 2 files changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
index fe1df69a1096..8062baed63db 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
@@ -7,7 +7,12 @@
 
 #include <drm/drm_connector.h>
 
+#include "intel_de.h"
+#include "intel_display_driver.h"
+#include "intel_display_regs.h"
+#include "intel_display_types.h"
 #include "intel_hdmi_frl_dfm.h"
+#include "intel_hdmi_frl_dfm_regs.h"
 
 /* DFM constraints and tolerance values */
 #define TB_BORROWED_MAX			400
@@ -719,3 +724,40 @@ bool intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm)
 
 	return true;
 }
+
+void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+	i915_reg_t reg;
+	u32 val;
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	reg = TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans);
+	val = TB_ACTUAL_OFFSET(crtc_state->frl.tb_actual);
+	intel_de_rmw(display, reg, TB_ACTUAL_OFFSET_MASK, val);
+
+	reg = TRANS_HDMI_FRL_DFMTHRSH(display, cpu_trans);
+	val = TB_MIN_THESHOLD(crtc_state->frl.tb_threshold_min);
+	intel_de_rmw(display, reg, TB_MIN_THESHOLD_MASK, val);
+}
+
+void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	val = intel_de_read(display, TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans));
+	crtc_state->frl.tb_actual =
+		REG_FIELD_GET(TB_ACTUAL_OFFSET_MASK, val);
+
+	val = intel_de_read(display, TRANS_HDMI_FRL_DFMTHRSH(display, cpu_trans));
+	crtc_state->frl.tb_threshold_min =
+		REG_FIELD_GET(TB_MIN_THESHOLD_MASK, val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
index 70a66679bdbc..1bfc70067518 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.h
@@ -7,6 +7,8 @@
 
 #include <linux/types.h>
 
+struct intel_crtc_state;
+
 /* All the input config needed to compute DFM requirements */
 struct intel_hdmi_frl_dfm_input_config {
 	/*
@@ -115,4 +117,7 @@ bool intel_hdmi_frl_dfm_nondsc_requirement_met(struct intel_hdmi_frl_dfm *frl_df
 bool
 intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm);
 
+void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state);
+void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state);
+
 #endif
-- 
2.50.1

[PATCH v2 33/56] drm/i915/hdmi: Rename port clock limit to specify tmds clock

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

The existing port clock limit function takes care of the TMDS mode of
transmission. Specify the port clock limit type explicitly as tmds.
This will pave way to add a separate port clock limit function for
FRL mode.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index db996b696847..7aee10ae2e1c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1858,9 +1858,9 @@ static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
 	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
 }
 
-static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
-				 bool respect_downstream_limits,
-				 bool has_hdmi_sink)
+static int hdmi_port_tmds_clock_limit(struct intel_hdmi *hdmi,
+				      bool respect_downstream_limits,
+				      bool has_hdmi_sink)
 {
 	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
 	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
@@ -1893,8 +1893,8 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
 
 	if (clock < 25000)
 		return MODE_CLOCK_LOW;
-	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
-					  has_hdmi_sink))
+	if (clock > hdmi_port_tmds_clock_limit(hdmi, respect_downstream_limits,
+					       has_hdmi_sink))
 		return MODE_CLOCK_HIGH;
 
 	/* GLK DPLL can't generate 446-480 MHz */
-- 
2.50.1

[PATCH v2 34/56] drm/i915/hdmi: Rename port clock valid to specify tmds clock

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

The existing port clock valid function takes care of the TMDS mode of
transmission. Specify the port clock valid type explicitly as tmds.
This will pave way to add a separate port clock valid function for
FRL mode.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7aee10ae2e1c..01476f659717 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1884,9 +1884,9 @@ static int hdmi_port_tmds_clock_limit(struct intel_hdmi *hdmi,
 }
 
 static enum drm_mode_status
-hdmi_port_clock_valid(struct intel_hdmi *hdmi,
-		      int clock, bool respect_downstream_limits,
-		      bool has_hdmi_sink)
+hdmi_port_tmds_clock_valid(struct intel_hdmi *hdmi,
+			   int clock, bool respect_downstream_limits,
+			   bool has_hdmi_sink)
 {
 	struct intel_display *display = to_intel_display(hdmi);
 	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
@@ -2010,7 +2010,7 @@ intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock,
 						  sink_format))
 			continue;
 
-		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
+		status = hdmi_port_tmds_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
 		if (status == MODE_OK)
 			return MODE_OK;
 	}
@@ -2186,9 +2186,9 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
 						       crtc_state->sink_format);
 
 		if (hdmi_bpc_possible(crtc_state, bpc) &&
-		    hdmi_port_clock_valid(intel_hdmi, tmds_clock,
-					  respect_downstream_limits,
-					  crtc_state->has_hdmi_sink) == MODE_OK)
+		    hdmi_port_tmds_clock_valid(intel_hdmi, tmds_clock,
+					       respect_downstream_limits,
+					       crtc_state->has_hdmi_sink) == MODE_OK)
 			return bpc;
 	}
 
-- 
2.50.1

[PATCH v2 35/56] drm/i915/hdmi: Rename mode clock valid to specify tmds clock

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

The existing mode clock valid function takes care of the TMDS mode of
transmission. Specify the mode clock valid type explicitly as tmds.
This will pave way to add a separate mode clock valid function for
FRL mode.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 01476f659717..67228b538e81 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1985,9 +1985,9 @@ static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector,
 }
 
 static enum drm_mode_status
-intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock,
-			    bool has_hdmi_sink,
-			    enum intel_output_format sink_format)
+intel_hdmi_tmds_mode_clock_valid(struct drm_connector *_connector, int clock,
+				 bool has_hdmi_sink,
+				 enum intel_output_format sink_format)
 {
 	struct intel_connector *connector = to_intel_connector(_connector);
 	struct intel_display *display = to_intel_display(connector);
@@ -2063,7 +2063,7 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
+	return intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
 }
 
 static enum drm_mode_status
-- 
2.50.1

[PATCH v2 36/56] drm/i915/hdmi: Validate FRL modes in mode_valid using the FRL DFM

[Ankit Nautiyal]

Modes above the TMDS limits can still be driven over FRL. When the
TMDS check fails, fall back to an FRL check that runs the non-DSC FRL DFM
at the best case (min bpc, max FRL rate, min audio) to confirm the mode
fits.

The fallback is gated on intel_hdmi_can_support_frl(), added here as a
placeholder returning false, so the FRL path stays inactive until FRL
support is completed in a later change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 61 ++++++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 67228b538e81..b82c636b46f9 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -62,6 +62,7 @@
 #include "intel_hdcp_regs.h"
 #include "intel_hdcp_shim.h"
 #include "intel_hdmi.h"
+#include "intel_hdmi_frl_dfm.h"
 #include "intel_link_bw.h"
 #include "intel_lspcon.h"
 #include "intel_panel.h"
@@ -2021,6 +2022,51 @@ intel_hdmi_tmds_mode_clock_valid(struct drm_connector *_connector, int clock,
 	return status;
 }
 
+static u32
+get_drm_color_format(enum intel_output_format output_format)
+{
+	switch (output_format) {
+	case INTEL_OUTPUT_FORMAT_RGB:
+		return DRM_OUTPUT_COLOR_FORMAT_RGB444;
+	case INTEL_OUTPUT_FORMAT_YCBCR420:
+		return DRM_OUTPUT_COLOR_FORMAT_YCBCR420;
+	case INTEL_OUTPUT_FORMAT_YCBCR444:
+		return DRM_OUTPUT_COLOR_FORMAT_YCBCR444;
+	default:
+		return DRM_OUTPUT_COLOR_FORMAT_RGB444;
+	}
+}
+
+static enum drm_mode_status
+intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
+				const struct drm_display_mode *mode,
+				enum intel_output_format output_format)
+{
+	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
+	struct intel_hdmi_frl_dfm frl_dfm = {};
+	int max_rate = hdmi->max_frl_rate;
+	int lanes = max_rate < 24 ? 3 : 4;
+
+	frl_dfm.config.pixel_clock_nominal_khz = mode->clock;
+	frl_dfm.config.hactive = mode->hdisplay;
+	frl_dfm.config.hblank = mode->htotal - mode->hdisplay;
+
+	/* Use min bpc to check if mode can be supported */
+	frl_dfm.config.bpc = 8;
+	frl_dfm.config.color_format = get_drm_color_format(output_format);
+	frl_dfm.config.lanes = lanes;
+	frl_dfm.config.bit_rate_kbps = (max_rate * 1000000) / lanes;
+
+	/* min audio */
+	frl_dfm.config.audio_channels = 2;
+	frl_dfm.config.audio_hz = 48000;
+
+	if (!intel_hdmi_frl_dfm_nondsc_requirement_met(&frl_dfm))
+		return MODE_CLOCK_HIGH;
+
+	return MODE_OK;
+}
+
 static enum drm_mode_status
 intel_hdmi_sink_format_valid(struct intel_connector *connector,
 			     const struct drm_display_mode *mode,
@@ -2045,6 +2091,13 @@ intel_hdmi_sink_format_valid(struct intel_connector *connector,
 	}
 }
 
+static bool
+intel_hdmi_can_support_frl(struct intel_hdmi *intel_hdmi)
+{
+	/* TODO check for FRL support */
+	return false;
+}
+
 static enum drm_mode_status
 intel_hdmi_mode_valid_format(struct intel_connector *connector,
 			     const struct drm_display_mode *mode,
@@ -2052,6 +2105,7 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
 			     enum intel_output_format sink_format)
 {
 	struct intel_display *display = to_intel_display(connector);
+	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
 	enum drm_mode_status status;
 
 	status = intel_hdmi_sink_format_valid(connector, mode,
@@ -2063,7 +2117,12 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
 	if (status != MODE_OK)
 		return status;
 
-	return intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
+	status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
+
+	if (status != MODE_OK && intel_hdmi_can_support_frl(hdmi))
+		status = intel_hdmi_frl_mode_clock_valid(connector, mode, sink_format);
+
+	return status;
 }
 
 static enum drm_mode_status
-- 
2.50.1

[PATCH v2 37/56] drm/i915/hdmi: Add FRL port clock valid

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Introduce hdmi_port_frl_clock_valid() which validates the FRL link
rate against the maximum FRL rate and the source PHY (c10/c20 or LT).

Call this from the FRL mode_valid path.

Since PHY PLL table units are in 10 kbps, add a macro to convert FRL
rate per lane in Gbps to 10 kbps.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.h |  3 +++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b82c636b46f9..8e742165a50a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -65,6 +65,7 @@
 #include "intel_hdmi_frl_dfm.h"
 #include "intel_link_bw.h"
 #include "intel_lspcon.h"
+#include "intel_lt_phy.h"
 #include "intel_panel.h"
 #include "intel_pfit.h"
 #include "intel_snps_phy.h"
@@ -1922,6 +1923,20 @@ hdmi_port_tmds_clock_valid(struct intel_hdmi *hdmi,
 	return MODE_OK;
 }
 
+static enum drm_mode_status
+hdmi_port_frl_clock_valid(struct intel_hdmi *hdmi, int clock)
+{
+	struct intel_display *display = to_intel_display(hdmi);
+
+	if (DISPLAY_VER(display) >= 35)
+		return intel_lt_phy_hdmi_frl_rate_valid(clock);
+
+	if (DISPLAY_VER(display) >= 14)
+		return intel_cx0_phy_hdmi_frl_rate_valid(hdmi, clock);
+
+	return MODE_CLOCK_RANGE;
+}
+
 int intel_hdmi_tmds_clock(int clock, int bpc,
 			  enum intel_output_format sink_format)
 {
@@ -2046,6 +2061,7 @@ intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
 	struct intel_hdmi_frl_dfm frl_dfm = {};
 	int max_rate = hdmi->max_frl_rate;
 	int lanes = max_rate < 24 ? 3 : 4;
+	int port_clock;
 
 	frl_dfm.config.pixel_clock_nominal_khz = mode->clock;
 	frl_dfm.config.hactive = mode->hdisplay;
@@ -2064,7 +2080,9 @@ intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
 	if (!intel_hdmi_frl_dfm_nondsc_requirement_met(&frl_dfm))
 		return MODE_CLOCK_HIGH;
 
-	return MODE_OK;
+	port_clock = FRL_GBPS_TO_10KBPS(max_rate / lanes);
+
+	return hdmi_port_frl_clock_valid(hdmi, port_clock);
 }
 
 static enum drm_mode_status
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 6e0b5fb1930a..a70b56258cd4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -85,4 +85,7 @@ int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector);
 int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector);
 void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state);
 
+/* FRL rate per lane (Gbps) -> PHY PLL table units (10 kbps) */
+#define FRL_GBPS_TO_10KBPS(rate)	((rate) * 100000)
+
 #endif /* __INTEL_HDMI_H__ */
-- 
2.50.1

[PATCH v2 38/56] drm/i915/hdmi: Add FRL clock computation based on DFM

[Ankit Nautiyal]

Compute the FRL port clock for a mode using the DFM helper.
Starting with the lowest FRL rate that meets the DFM requirements, check
if the mode can be supported with FRL and derive the port clock from the
selected FRL rate and lane count.

Use the min audio requirement (L-PCM 2ch/48KHz) to make sure FRL rate
chosen can support baseline audio. The pruning of un-supported audio is
handled as a separate change.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 118 +++++++++++++++++++++-
 1 file changed, 117 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 8e742165a50a..0391597c9847 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2306,13 +2306,129 @@ static int intel_hdmi_compute_tmds_clock(struct intel_encoder *encoder,
 	return 0;
 }
 
+static int
+intel_hdmi_compute_frl_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *crtc_state)
+{
+	static const int rate[] = {9, 18, 24, 32, 40, 48};
+	struct intel_hdmi_frl_dfm frl_dfm = {0};
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	int max_rate = intel_hdmi->max_frl_rate;
+	bool can_support_frl_mode = false;
+	int i;
+
+	/* Fill mode related input params */
+	frl_dfm.config.pixel_clock_nominal_khz = adjusted_mode->clock;
+	frl_dfm.config.hactive = adjusted_mode->hdisplay;
+	frl_dfm.config.hblank = adjusted_mode->htotal - adjusted_mode->hdisplay;
+
+	/* Fill color related input params */
+	frl_dfm.config.bpc = crtc_state->pipe_bpp / 3;
+	frl_dfm.config.color_format = get_drm_color_format(crtc_state->output_format);
+
+	/*
+	 * Using fixed 2ch / 48 kHz baseline makes the chosen rate carry video + basic
+	 * stereo (L-PCM), so the guaranteed floor is never pruned.
+	 * Since overhead is only a few packets/line, it almost never bumps the FRL rate,
+	 * but it avoids the situation where a rate is chosen with no room for audio gap.
+	 *
+	 * Everything above the baseline is decided by pruning the ELD at the committed
+	 * rate.
+	 */
+	frl_dfm.config.audio_hz = 48000;
+	frl_dfm.config.audio_channels = 2;
+
+	/*
+	 * Check if the resolution can be supported in FRL mode.
+	 * We try with the lowest FRL rate first — the minimum rate that
+	 * satisfies DFM requirements — for better SI margin and lower power.
+	 */
+	for (i = 0; i < ARRAY_SIZE(rate); i++) {
+		if (rate[i] > max_rate)
+			continue;
+		/* Fill the bw related input parameters */
+		frl_dfm.config.lanes = rate[i] < 24 ? 3 : 4;
+		frl_dfm.config.bit_rate_kbps = (rate[i] * 1000000) / frl_dfm.config.lanes;
+
+		if (intel_hdmi_frl_dfm_nondsc_requirement_met(&frl_dfm)) {
+			can_support_frl_mode = true;
+			break;
+		}
+	}
+
+	if (!can_support_frl_mode) {
+		memset(&crtc_state->frl, 0, sizeof(crtc_state->frl));
+		return -EINVAL;
+	}
+
+	/* Fill crtc_state frl DFM output params */
+	crtc_state->frl.required_lanes = frl_dfm.config.lanes;
+	crtc_state->frl.required_rate = frl_dfm.config.bit_rate_kbps / 1000000;
+	crtc_state->frl.tb_borrowed = frl_dfm.params.tb_borrowed;
+	crtc_state->frl.tb_actual = frl_dfm.params.tb_borrowed / 2;
+	drm_dbg_kms(display->drm, "FRL DFM config: tb_borrowed = %d, tb_actual = %d\n",
+		    crtc_state->frl.tb_borrowed, crtc_state->frl.tb_actual);
+
+	if (frl_dfm.params.tb_borrowed && (frl_dfm.params.tb_borrowed / 2) <= 492)
+		crtc_state->frl.tb_threshold_min = 492 - (frl_dfm.params.tb_borrowed / 2);
+	else
+		crtc_state->frl.tb_threshold_min = 492;
+
+	/*
+	 * TODO
+	 * 1. Calculate condition for Reseource based scheduling enable.
+	 * Disabling resource based scheduling for now.
+	 * 2. Active Character buffer threshold depends on cd clock bw.
+	 * Setting default value of 0.
+	 */
+	crtc_state->frl.rsrc_sched_en = false;
+	crtc_state->frl.active_char_buf_threshold = 0;
+
+	return 0;
+}
+
+static int
+intel_hdmi_compute_frl_clock(struct intel_encoder *encoder,
+			     struct intel_crtc_state *crtc_state)
+{
+	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
+	int max_bpc = max(crtc_state->pipe_bpp / 3, 8);
+	int port_clock;
+	int bpc;
+
+	for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
+		int ret;
+
+		if (!hdmi_bpc_possible(crtc_state, bpc))
+			continue;
+
+		crtc_state->pipe_bpp = bpc * 3;
+
+		ret = intel_hdmi_compute_frl_config(encoder, crtc_state);
+		if (ret)
+			continue;
+
+		/* Port clock for FRL rates is bitrate in 10Kbps */
+		port_clock = FRL_GBPS_TO_10KBPS(crtc_state->frl.required_rate);
+
+		if (hdmi_port_frl_clock_valid(hdmi, port_clock) == MODE_OK) {
+			crtc_state->port_clock = port_clock;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 				    struct intel_crtc_state *crtc_state,
 				    bool respect_downstream_limits,
 				    bool enable_frl)
 {
 	if (enable_frl)
-		return -EINVAL;
+		return intel_hdmi_compute_frl_clock(encoder, crtc_state);
 
 	return intel_hdmi_compute_tmds_clock(encoder, crtc_state, respect_downstream_limits);
 }
-- 
2.50.1

[PATCH v2 39/56] drm/i915/hdmi: Add support for sending uevent to user for FRL training failure

[Ankit Nautiyal]

In case of HDMI FRL training failure for a given mode, the user
should be sent a uevent signalling Link failure.

Add support for sending uevent to userspace in case of link training
failure.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 32 +++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0391597c9847..69612ebe80f0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -71,6 +71,8 @@
 #include "intel_snps_phy.h"
 #include "intel_vrr.h"
 
+#define HAS_HDMI_FRL(__display)		(DISPLAY_VER((__display)) >= 14)
+
 bool intel_hdmi_is_frl(u32 clock)
 {
 	static const u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 };
@@ -3397,6 +3399,31 @@ void intel_infoframe_init(struct intel_digital_port *dig_port)
 	}
 }
 
+/* Common code with DP, need to put in a common place */
+static void intel_hdmi_modeset_retry_work_fn(struct work_struct *work)
+{
+	struct intel_connector *intel_connector;
+	struct drm_connector *connector;
+
+	intel_connector = container_of(work, typeof(*intel_connector),
+				       modeset_retry_work);
+	connector = &intel_connector->base;
+	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
+		      connector->name);
+
+	/* Grab the locks before changing connector property*/
+	mutex_lock(&connector->dev->mode_config.mutex);
+	/*
+	 * Set connector link status to BAD and send a Uevent to notify
+	 * userspace to do a modeset.
+	 */
+	drm_connector_set_link_status_property(connector,
+					       DRM_MODE_LINK_STATUS_BAD);
+	mutex_unlock(&connector->dev->mode_config.mutex);
+	/* Send Hotplug uevent so userspace can reprobe */
+	drm_kms_helper_hotplug_event(connector->dev);
+}
+
 bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
 			       struct intel_connector *intel_connector)
 {
@@ -3470,6 +3497,11 @@ bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
 	if (!intel_hdmi->cec_notifier)
 		drm_dbg_kms(display->drm, "CEC notifier get failed\n");
 
+	/* Initialize the work for modeset in case of link train failure */
+	if (HAS_HDMI_FRL(display))
+		INIT_WORK(&intel_connector->modeset_retry_work,
+			  intel_hdmi_modeset_retry_work_fn);
+
 	return true;
 }
 
-- 
2.50.1

[PATCH v2 40/56] drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path

[Ankit Nautiyal]

Enable HDMI FRL in the DDI enable and disable sequences for MTL+:

Enable path (intel_ddi_enable_hdmi):
-Prepare for FRL mode before enabling D2D link.
-After the DDI buffer is enabled, run FRL link training. If FRL link
training fails, notify userspace. On success, write DFM registers and
enable the transcoder.

Disable path (intel_ddi_post_disable_hdmi):
Call intel_hdmi_disable_frl() after the DDI buffer is disabled to perform
LTS:L teardown and clear the FRL function registers.

Bspec:65750
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 53e889c0d022..22a49eb50b20 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -71,6 +71,7 @@
 #include "intel_gmbus.h"
 #include "intel_hdcp.h"
 #include "intel_hdmi.h"
+#include "intel_hdmi_frl_dfm.h"
 #include "intel_hotplug.h"
 #include "intel_hti.h"
 #include "intel_lspcon.h"
@@ -3240,6 +3241,8 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
 		intel_ddi_disable_transcoder_clock(old_crtc_state);
 
 	intel_ddi_buf_disable(encoder, old_crtc_state);
+	if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
+		intel_hdmi_disable_frl(encoder, old_crtc_state);
 
 	if (DISPLAY_VER(display) >= 12)
 		intel_ddi_disable_transcoder_clock(old_crtc_state);
@@ -3494,6 +3497,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_connector *connector = conn_state->connector;
+	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
+	struct intel_connector *intel_connector =
+		intel_hdmi->attached_connector;
 	enum port port = encoder->port;
 	u32 buf_ctl = 0;
 
@@ -3514,6 +3520,9 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 	if (has_buf_trans_select(display))
 		hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
 
+	if (DISPLAY_VER(display) >= 14 && crtc_state->frl.enable)
+		intel_hdmi_prepare_for_frl_mode(crtc_state);
+
 	/* e. Enable D2D Link for C10/C20 Phy */
 	mtl_ddi_enable_d2d(encoder);
 
@@ -3605,8 +3614,15 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
 
 	intel_ddi_buf_enable(encoder, buf_ctl);
 
-	if (DISPLAY_VER(display) >= 14)
+	if (DISPLAY_VER(display) >= 14) {
+		if (crtc_state->frl.enable &&
+		    intel_hdmi_start_frl(encoder, crtc_state) < 0)
+			schedule_work(&intel_connector->modeset_retry_work);
+
+		intel_hdmi_frl_cfg_write(crtc_state);
+		intel_hdmi_frl_dfm_write(crtc_state);
 		intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
+	}
 
 	intel_hdmi_poll_for_scrambling_enable(crtc_state, connector);
 }
-- 
2.50.1

[PATCH v2 41/56] drm/i915/ltphy: Fix HDMI FRL per-lane TX mapping

[Ankit Nautiyal]

intel_lt_phy_set_signal_levels() currently maps DDI lane N to PHY lane
N / 2, TX N % 2, which matches the DisplayPort lane mapping. HDMI FRL
uses a different mapping because the LT PHY swaps main links 0 and 2 to
support DP++, with the swap applied before port reversal.

The resulting HDMI lane-to-transmitter mapping is:

  HDMI lane    Normal         Reversed
  ---------    ------------   ------------
  0            LN1_TX1        LN0_TX2
  1            LN0_TX2        LN1_TX1
  2            LN0_TX1        LN1_TX2
  3            LN1_TX2        LN0_TX1   (x4 only)

Using the DP mapping for HDMI FRL causes per-lane FFE settings to be
programmed on the wrong transmitter. For example, an FFE request for
lane 0 is applied to lane 2 and vice versa.

Fix this by using an HDMI FRL-specific lookup table indexed by lane
reversal state and HDMI lane number. Retain the existing mapping for
DisplayPort and HDMI TMDS, where lane-specific signal levels are not
required.

The TX enable masks in intel_lt_phy_enable_disable_tx() already match
the Bspec-defined HDMI FRL mapping and require no changes.

Bspec: 74701
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lt_phy.c | 33 +++++++++++++++++++--
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index ba03e5f1bb87..6d6ff9fbcce8 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2419,6 +2419,24 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 	struct ref_tracker *wakeref;
 	int n_entries, ln;
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	/*
+	 * HDMI 2.1 FRL distributes the DDI lanes across the PHY transmitters in
+	 * a fixed, non-identity order unlike DP which uses
+	 * lane = ln / 2, tx = ln % 2. tx selects LT_PHY_TXY_*(tx)
+	 * within the message-bus lane. Indexed [lane_reversal][ddi_lane]; the
+	 * x3 case uses the first three entries of each row.
+	 */
+	static const struct {
+		u8 lane_mask;
+		u8 tx;
+	} frl_lane_map[2][4] = {
+		/* not reversed: LN1_TX1, LN0_TX2, LN0_TX1, LN1_TX2 */
+		{ { INTEL_LT_PHY_LANE1, 0 }, { INTEL_LT_PHY_LANE0, 1 },
+		  { INTEL_LT_PHY_LANE0, 0 }, { INTEL_LT_PHY_LANE1, 1 } },
+		/* reversed:     LN0_TX2, LN1_TX1, LN1_TX2, LN0_TX1 */
+		{ { INTEL_LT_PHY_LANE0, 1 }, { INTEL_LT_PHY_LANE1, 0 },
+		  { INTEL_LT_PHY_LANE1, 1 }, { INTEL_LT_PHY_LANE0, 0 } },
+	};
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		return;
@@ -2435,9 +2453,18 @@ void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder,
 
 	for (ln = 0; ln < crtc_state->lane_count; ln++) {
 		int level = intel_ddi_level(encoder, crtc_state, ln);
-		int lane = ln / 2;
-		int tx = ln % 2;
-		u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
+		u8 lane_mask;
+		int tx;
+
+		if (crtc_state->frl.enable) {
+			lane_mask = frl_lane_map[dig_port->lane_reversal][ln].lane_mask;
+			tx = frl_lane_map[dig_port->lane_reversal][ln].tx;
+		} else {
+			lane_mask = (ln / 2) == 0 ? INTEL_LT_PHY_LANE0 :
+						    INTEL_LT_PHY_LANE1;
+			tx = ln % 2;
+		}
+
 
 		if (!(lane_mask & owned_lane_mask))
 			continue;
-- 
2.50.1

[PATCH v2 42/56] drm/i915/hdmi: Add read out for FRL state

[Ankit Nautiyal]

Read out the FRL configuration and Data Flow Metering registers and
fill the FRL members in crtc_state.

In subsequent changes these are added to the state checker and compared
bwteen two crtc_states in intel_pipe_config_compare().

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  3 ++
 drivers/gpu/drm/i915/display/intel_hdmi.c | 35 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  1 +
 3 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 22a49eb50b20..f7cbe330e19e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4302,6 +4302,9 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_dip_sdp_transmission_line_get_config(pipe_config);
 
 	intel_audio_codec_get_config(encoder, pipe_config);
+
+	if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI))
+		intel_hdmi_frl_get_config(pipe_config);
 }
 
 void intel_ddi_get_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 69612ebe80f0..c5f25d2d6331 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -4160,3 +4160,38 @@ void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state)
 
 	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);
 }
+
+static void intel_hdmi_frl_cfg_read(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+	u32 val;
+
+	val = intel_de_read(display, TRANS_HDMI_FRL_CFG(display, cpu_trans));
+
+	if (val & TRANS_HDMI_FRL_ENABLE)
+		crtc_state->frl.enable = true;
+
+	crtc_state->frl.rsrc_sched_en =
+		REG_FIELD_GET(TRANS_HDMI_R_B_SCHED_ENABLE_MASK, val);
+	crtc_state->frl.active_char_buf_threshold =
+		REG_FIELD_GET(TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, val);
+}
+
+void intel_hdmi_frl_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_HDMI_FRL(display))
+		return;
+
+	intel_hdmi_frl_cfg_read(crtc_state);
+
+	if (!crtc_state->frl.enable)
+		return;
+
+	crtc_state->frl.required_rate = crtc_state->port_clock / 100000;
+	crtc_state->frl.required_lanes = crtc_state->lane_count;
+
+	intel_hdmi_frl_dfm_read(crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index a70b56258cd4..305ee1186d0b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -84,6 +84,7 @@ void intel_hdmi_poll_for_scrambling_enable(const struct intel_crtc_state *crtc_s
 int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector);
 int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector);
 void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state);
+void intel_hdmi_frl_get_config(struct intel_crtc_state *crtc_state);
 
 /* FRL rate per lane (Gbps) -> PHY PLL table units (10 kbps) */
 #define FRL_GBPS_TO_10KBPS(rate)	((rate) * 100000)
-- 
2.50.1

[PATCH v2 43/56] drm/i915/hdmi: Compute FRL Link M/N

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

For HDMI FRL, the transcoder Link M/N carries the ratio of the average
tribyte rate (ftb_avg) to the FRL div18 clock, unlike the pixel/link
clock ratio used for DP.

Compute link_m/link_n from ftb_avg and the required FRL rate, reduced by
their gcd. As PIPE_LINK_M1/N1 are 32-bit wide, scale both down preserving
the ratio until they fit, and store them in crtc_state.

v2: Use full 32 bits for LINK_M/N for HDMI2.1.

Bspec: 68848
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 38 +++++++++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 1abd221f966b..7e1c12560a00 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -863,6 +863,7 @@
 #define  TU_SIZE(x)		REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
 #define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
 #define  DATA_LINK_N_MAX	(0x800000)
+#define  HDMI_FRL_LINK_M_N_MAX	REG_GENMASK(31, 0)
 
 #define _PIPEA_DATA_N_G4X	0x70054
 #define _PIPEB_DATA_N_G4X	0x71054
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c5f25d2d6331..ce6ad9e28bee 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -27,6 +27,7 @@
  */
 
 #include <linux/delay.h>
+#include <linux/gcd.h>
 #include <linux/hdmi.h>
 #include <linux/i2c.h>
 #include <linux/iopoll.h>
@@ -2308,6 +2309,38 @@ static int intel_hdmi_compute_tmds_clock(struct intel_encoder *encoder,
 	return 0;
 }
 
+static void
+compute_frl_mn(struct intel_crtc_state *crtc_state, u32 ftb_avg_k)
+{
+	u64 ftb_avg, div_18_clk, gcd_val;
+	u64 link_m, link_n;
+
+	ftb_avg = (u64)ftb_avg_k * 1000;
+	div_18_clk = mult_frac(1000000000, crtc_state->frl.required_rate, 18);
+	gcd_val = gcd(ftb_avg, div_18_clk);
+
+	link_m = DIV_ROUND_UP_ULL(ftb_avg, gcd_val);
+	link_n = DIV_ROUND_UP_ULL(div_18_clk, gcd_val);
+
+	/*
+	 * PIPE_LINK_M1/N1 are 32-bit for HDMI2.1. Scale both
+	 * down preserving the ratio until they fit the register width.
+	 *
+	 * #TODO check if intel_reduce_m_n_ratio() can be exported.
+	 */
+	while (link_m > HDMI_FRL_LINK_M_N_MAX ||
+	       link_n > HDMI_FRL_LINK_M_N_MAX) {
+		link_m >>= 1;
+		link_n >>= 1;
+	}
+
+	crtc_state->frl.link_m = (u32)link_m;
+	crtc_state->frl.link_n = (u32)link_n;
+
+	/* Frl div 18 stored in Khz */
+	crtc_state->frl.div18 = DIV_ROUND_UP_ULL(div_18_clk, 1000);
+}
+
 static int
 intel_hdmi_compute_frl_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *crtc_state)
@@ -2378,6 +2411,11 @@ intel_hdmi_compute_frl_config(struct intel_encoder *encoder,
 	else
 		crtc_state->frl.tb_threshold_min = 492;
 
+	compute_frl_mn(crtc_state, frl_dfm.params.ftb_avg_k);
+	drm_dbg_kms(display->drm, "FRL Clock: link_m = %dHz, link_n = %dHz, div18 = %dKHz\n",
+		    crtc_state->frl.link_m, crtc_state->frl.link_n,
+		    crtc_state->frl.div18);
+
 	/*
 	 * TODO
 	 * 1. Calculate condition for Reseource based scheduling enable.
-- 
2.50.1

[PATCH v2 44/56] drm/i915/hdmi_frl_dfm: Write and read back FRL Link M/N

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Program the computed FRL Link M/N into the transcoder PIPE_LINK_M1/N1
registers along with the other FRL DFM registers, just before enabling
the transcoder.

Read it back in the FRL DFM readout for the state checker.

v2: Read full 31 bits from LINK_M/N for HDMI FRL.

Bspec: 68848
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../gpu/drm/i915/display/intel_hdmi_frl_dfm.c | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
index 8062baed63db..384e92d89e29 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
@@ -725,6 +725,26 @@ bool intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm)
 	return true;
 }
 
+static void frl_set_m_n(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	intel_de_write(display, PIPE_LINK_M1(display, cpu_transcoder),
+		       crtc_state->frl.link_m);
+	intel_de_write(display, PIPE_LINK_N1(display, cpu_transcoder),
+		       crtc_state->frl.link_n);
+}
+
+static void frl_get_m_n(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	crtc_state->frl.link_m = intel_de_read(display, PIPE_LINK_M1(display, cpu_transcoder));
+	crtc_state->frl.link_n = intel_de_read(display, PIPE_LINK_N1(display, cpu_transcoder));
+}
+
 void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -735,6 +755,8 @@ void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state)
 	if (!crtc_state->frl.enable)
 		return;
 
+	frl_set_m_n(crtc_state);
+
 	reg = TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans);
 	val = TB_ACTUAL_OFFSET(crtc_state->frl.tb_actual);
 	intel_de_rmw(display, reg, TB_ACTUAL_OFFSET_MASK, val);
@@ -753,6 +775,8 @@ void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state)
 	if (!crtc_state->frl.enable)
 		return;
 
+	frl_get_m_n(crtc_state);
+
 	val = intel_de_read(display, TRANS_HDMI_FRL_DFMWRCTL(display, cpu_trans));
 	crtc_state->frl.tb_actual =
 		REG_FIELD_GET(TB_ACTUAL_OFFSET_MASK, val);
-- 
2.50.1

[PATCH v2 45/56] drm/i915/hdmi: Use the real pixel clock as crtc_clock for FRL

[Ankit Nautiyal]

For FRL, port_clock is the link rate, decoupled from the pixel clock, so
hsw_crtc_compute_clock() must not overwrite crtc_clock via
intel_crtc_dotclock().
The FRL pixel clock isn't recoverable from hardware (the FRL M/N is the DFM
tri-byte ratio), so take the sw value in verify_crtc_state()
for the derived clock fields.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c      |  2 +-
 .../drm/i915/display/intel_modeset_verify.c    | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 20fd091cb9db..851a4abf2448 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1171,7 +1171,7 @@ static int hsw_crtc_compute_clock(struct intel_atomic_state *state,
 		return 0;
 
 	/* CRT dotclock is determined via other means */
-	if (!crtc_state->has_pch_encoder)
+	if (!crtc_state->has_pch_encoder && !crtc_state->frl.enable)
 		crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index f0761d8a7437..54ec1f439b90 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -218,6 +218,24 @@ verify_crtc_state(struct intel_atomic_state *state,
 	if (!sw_crtc_state->hw.active)
 		goto destroy_state;
 
+	/*
+	 * The HDMI FRL pixel clock is decoupled from port_clock and cannot be
+	 * recovered from hardware readout. The FRL M/N is the DFM tri-byte ratio, not
+	 * a pixel:link ratio so we cannot derive the pixel clock accurately.
+	 * To avoid mismatches and to avoid handling PIPE_CONF_CHECK for FRL,
+	 * copy the software value to the hardware state.
+	 */
+	if (sw_crtc_state->frl.enable) {
+		hw_crtc_state->hw.adjusted_mode.crtc_clock =
+			sw_crtc_state->hw.adjusted_mode.crtc_clock;
+		hw_crtc_state->hw.pipe_mode.crtc_clock =
+			sw_crtc_state->hw.pipe_mode.crtc_clock;
+		hw_crtc_state->pixel_rate =
+			sw_crtc_state->pixel_rate;
+		hw_crtc_state->pixel_rate_cdclk =
+			sw_crtc_state->pixel_rate_cdclk;
+	}
+
 	intel_pipe_config_sanity_check(hw_crtc_state);
 
 	if (!intel_pipe_config_compare(sw_crtc_state,
-- 
2.50.1

[PATCH v2 46/56] drm/i915/display: Add FRL members to the state checker

[Ankit Nautiyal]

Plug in the FRL members to the state checker.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5d4453f283b..f9233b5f5b6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5626,6 +5626,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(set_context_latency);
 
+	PIPE_CONF_CHECK_BOOL(frl.enable);
+	PIPE_CONF_CHECK_BOOL(frl.rsrc_sched_en);
+	PIPE_CONF_CHECK_I(frl.required_lanes);
+	PIPE_CONF_CHECK_I(frl.tb_actual);
+	PIPE_CONF_CHECK_I(frl.active_char_buf_threshold);
+	PIPE_CONF_CHECK_I(frl.link_m);
+	PIPE_CONF_CHECK_I(frl.link_n);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_LLI
-- 
2.50.1

[PATCH v2 47/56] drm/i915/hdmi: Compute output format for HDMI FRL mode

[Ankit Nautiyal]

If the source and sink support FRL, then compute output format
that can support HDMI FRL mode. This in turn calculates the FRL
configuration, clocks etc required to support a video mode with
FRL transmission.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 66 +++++++++++++++++------
 1 file changed, 50 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index ce6ad9e28bee..425971d8927a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2543,10 +2543,11 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 	return intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits, enable_frl);
 }
 
-static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
-				      struct intel_crtc_state *crtc_state,
-				      const struct drm_connector_state *conn_state,
-				      bool respect_downstream_limits)
+static int _intel_hdmi_compute_formats(struct intel_encoder *encoder,
+				       struct intel_crtc_state *crtc_state,
+				       const struct drm_connector_state *conn_state,
+				       bool respect_downstream_limits,
+				       bool enable_frl)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
@@ -2558,7 +2559,7 @@ static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
 		ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 						       respect_downstream_limits,
 						       INTEL_OUTPUT_FORMAT_YCBCR420,
-						       false);
+						       enable_frl);
 
 		if (ret && !respect_downstream_limits) {
 			drm_dbg_kms(display->drm,
@@ -2567,19 +2568,19 @@ static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
 			ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 							       respect_downstream_limits,
 							       INTEL_OUTPUT_FORMAT_RGB,
-							       false);
+							       enable_frl);
 		}
 	} else {
 		ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 						       respect_downstream_limits,
 						       INTEL_OUTPUT_FORMAT_RGB,
-						       false);
+						       enable_frl);
 
 		if (ret && drm_mode_is_420_also(info, adjusted_mode))
 			ret = intel_hdmi_compute_output_format(encoder, crtc_state, connector,
 							       respect_downstream_limits,
 							       INTEL_OUTPUT_FORMAT_YCBCR420,
-							       false);
+							       enable_frl);
 	}
 
 	return ret;
@@ -2620,6 +2621,26 @@ bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
 		!intel_hdmi_is_cloned(crtc_state);
 }
 
+static int intel_hdmi_compute_formats(struct intel_encoder *encoder,
+				      struct intel_crtc_state *crtc_state,
+				      const struct drm_connector_state *conn_state,
+				      bool enable_frl)
+{
+	int ret;
+
+	/*
+	 * Try to respect downstream TMDS clock limits first, if
+	 * that fails assume the user might know something we don't.
+	 */
+	ret = _intel_hdmi_compute_formats(encoder, crtc_state,
+					  conn_state, true, enable_frl);
+	if (ret)
+		ret = _intel_hdmi_compute_formats(encoder, crtc_state,
+						  conn_state, false, enable_frl);
+
+	return ret;
+}
+
 int intel_hdmi_compute_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config,
 			      struct drm_connector_state *conn_state)
@@ -2628,6 +2649,9 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
 	struct intel_connector *connector = to_intel_connector(conn_state->connector);
 	struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc;
+	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
+	bool enable_frl = false;
+	int lane_count = 4;
 	int ret;
 
 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
@@ -2648,13 +2672,23 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 	if (!intel_link_bw_compute_pipe_bpp(pipe_config))
 		return -EINVAL;
 
-	/*
-	 * Try to respect downstream TMDS clock limits first, if
-	 * that fails assume the user might know something we don't.
-	 */
-	ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, true);
-	if (ret)
-		ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, false);
+	if (HAS_HDMI_FRL(display) &&
+	    intel_bios_hdmi_max_frl_rate(encoder->devdata) &&
+	    intel_hdmi->has_sink_hdmi_21)
+		enable_frl = true;
+
+	ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, false);
+
+	if (ret && enable_frl) {
+		ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, true);
+		drm_dbg_kms(display->drm,
+			    "Enabling FRL mode with lanes = %d rate = %d\n",
+			    pipe_config->frl.required_lanes,
+			    pipe_config->frl.required_rate);
+		pipe_config->frl.enable = true;
+		lane_count = pipe_config->frl.required_lanes;
+	}
+
 	if (ret) {
 		drm_dbg_kms(display->drm,
 			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
@@ -2677,7 +2711,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
 		adjusted_mode->picture_aspect_ratio =
 			conn_state->picture_aspect_ratio;
 
-	pipe_config->lane_count = 4;
+	pipe_config->lane_count = lane_count;
 
 	if (scdc->scrambling.supported && source_supports_scrambling(encoder) &&
 	    !pipe_config->frl.enable) {
-- 
2.50.1

[PATCH v2 48/56] drm/i915/hdmi: Add a helper to check non DSC audio support for HDMI FRL

[Ankit Nautiyal]

For HDMI TMDS we need to check if the Hblank tribytes are sufficient for
HDMI audio packets tribytes for a given audio configuration.

For FRL we need to check the above and also that the whole line meets
the line budget for a given FRL rate.

Add a helper to check whether a given audio configuration (L-PCM sample
rate + channel count) fits the committed non DSC FRL video config, using
the FRL DFM.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  2 ++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 425971d8927a..c57d99195ed0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2341,6 +2341,28 @@ compute_frl_mn(struct intel_crtc_state *crtc_state, u32 ftb_avg_k)
 	crtc_state->frl.div18 = DIV_ROUND_UP_ULL(div_18_clk, 1000);
 }
 
+bool intel_hdmi_frl_audio_rate_supported(const struct intel_crtc_state *crtc_state,
+					 int audio_rate, int channels)
+{
+	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+	struct intel_hdmi_frl_dfm frl_dfm = {};
+
+	frl_dfm.config.pixel_clock_nominal_khz = adjusted_mode->clock;
+	frl_dfm.config.hactive = adjusted_mode->hdisplay;
+	frl_dfm.config.hblank = adjusted_mode->htotal - adjusted_mode->hdisplay;
+	frl_dfm.config.bpc = crtc_state->pipe_bpp / 3;
+	frl_dfm.config.color_format = get_drm_color_format(crtc_state->output_format);
+
+	frl_dfm.config.lanes = crtc_state->frl.required_lanes;
+	frl_dfm.config.bit_rate_kbps = crtc_state->frl.required_rate * 1000000;
+
+	/* Audio config under test */
+	frl_dfm.config.audio_hz = audio_rate;
+	frl_dfm.config.audio_channels = channels;
+
+	return intel_hdmi_frl_dfm_nondsc_requirement_met(&frl_dfm);
+}
+
 static int
 intel_hdmi_compute_frl_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 305ee1186d0b..71b12f557d75 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -63,6 +63,8 @@ int intel_hdmi_dsc_get_num_slices(const struct drm_display_mode *mode,
 				  int hdmi_max_slices, int hdmi_throughput);
 int intel_hdmi_dsc_get_slice_height(int vactive);
 bool intel_hdmi_is_frl(u32 clock);
+bool intel_hdmi_frl_audio_rate_supported(const struct intel_crtc_state *crtc_state,
+					 int audio_rate, int channels);
 void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state);
 int intel_hdmi_start_frl(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state);
-- 
2.50.1

[PATCH v2 49/56] drm/i915/audio: Add the mode pruning logic for HDMI FRL

[Ankit Nautiyal]

Prune the audio modes that are not supported with given HDMI FRL
configuration.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 32f8c5e55319..fd62eaf14a3c 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -39,6 +39,7 @@
 #include "intel_display_types.h"
 #include "intel_display_wa.h"
 #include "intel_dp.h"
+#include "intel_hdmi.h"
 #include "intel_lpe_audio.h"
 
 /**
@@ -817,10 +818,19 @@ static void intel_audio_hdmi_eld_compute_config(struct intel_crtc_state *crtc_st
 		channels = sad.channels + 1;
 
 		for (bit = 0; bit < 7; bit++) {
+			bool supported;
+
 			if (!(sad.freq & BIT(bit)))
 				continue;
-			if (hdmi_audio_rate_supported(crtc_state, available_tmds,
-						      sad_freqs[bit], channels))
+
+			if (crtc_state->frl.enable)
+				supported = intel_hdmi_frl_audio_rate_supported(crtc_state,
+										sad_freqs[bit],
+										channels);
+			else
+				supported = hdmi_audio_rate_supported(crtc_state, available_tmds,
+								      sad_freqs[bit], channels);
+			if (supported)
 				new_freq_mask |= BIT(bit);
 		}
 
-- 
2.50.1

[PATCH v2 50/56] drm/i915/hdmi: Enable FRL based mode clock valid

[Ankit Nautiyal]

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Higher resolution modes like 8K@60, 4K@120 need FRL support. Platforms
before MTL do not support FRL, so allow modes requiring more than 600MHz
dotclock to be enumerated only on MTL+ where FRL is supported.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c57d99195ed0..e3dbd71a3652 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2115,8 +2115,11 @@ intel_hdmi_sink_format_valid(struct intel_connector *connector,
 static bool
 intel_hdmi_can_support_frl(struct intel_hdmi *intel_hdmi)
 {
-	/* TODO check for FRL support */
-	return false;
+	struct intel_display *display = to_intel_display(intel_hdmi);
+
+	return HAS_HDMI_FRL(display) &&
+	       intel_hdmi->has_sink_hdmi_21 &&
+	       intel_hdmi->max_frl_rate;
 }
 
 static enum drm_mode_status
@@ -2176,12 +2179,10 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
 	}
 
 	/*
-	 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
-	 * enumerated only if FRL is supported. Current platforms do not support
-	 * FRL so prune the higher resolution modes that require doctclock more
-	 * than 600MHz.
+	 * Platforms < MTL do not support FRL so prune the higher resolution
+	 * modes that require doctclock more than 600MHz.
 	 */
-	if (clock > 600000)
+	if (!intel_hdmi_can_support_frl(hdmi) && clock > 600000)
 		return MODE_CLOCK_HIGH;
 
 	if (drm_mode_is_420_only(info, mode)) {
-- 
2.50.1

[PATCH v2 51/56] drm/i915/joiner: Prepare to move joiner helpers to a new file

[Ankit Nautiyal]

Currently pipe-joiner is supported only for DP. To enable higher resolution
for HDMI, joiner support is required for HDMI also.

Create a new file intel_joiner.c to have the common joiner helpers that
can be used by any encoder.

Start with moving intel_dp_joiner_needs_dsc() helper from intel_dp.c
to the new file.

In subsequent changes other joiner helpers will follow.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile               |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c     | 18 +++--------------
 drivers/gpu/drm/i915/display/intel_dp.h     |  2 --
 drivers/gpu/drm/i915/display/intel_dp_mst.c |  5 +++--
 drivers/gpu/drm/i915/display/intel_joiner.c | 22 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_joiner.h | 16 +++++++++++++++
 drivers/gpu/drm/xe/Makefile                 |  1 +
 7 files changed, 46 insertions(+), 19 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_joiner.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d6abb79d5696..be5fe25ca314 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -369,6 +369,7 @@ i915-y += \
 	display/intel_gmbus.o \
 	display/intel_hdmi.o \
 	display/intel_hdmi_frl_dfm.o \
+	display/intel_joiner.o \
 	display/intel_lspcon.o \
 	display/intel_lt_phy.o \
 	display/intel_lvds.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d8c0d9381471..49e4c77b5142 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -86,6 +86,7 @@
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
 #include "intel_hotplug_irq.h"
+#include "intel_joiner.h"
 #include "intel_lspcon.h"
 #include "intel_lvds.h"
 #include "intel_modeset_lock.h"
@@ -1390,7 +1391,7 @@ intel_dp_mode_valid_format(struct intel_connector *connector,
 			}
 		}
 
-		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
+		if (intel_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
 			status = MODE_CLOCK_HIGH;
 			continue;
 		}
@@ -2794,19 +2795,6 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
 				      link_bpp_x16, 0);
 }
 
-bool intel_dp_joiner_needs_dsc(struct intel_display *display,
-			       int num_joined_pipes)
-{
-	/*
-	 * Pipe joiner needs compression up to display 12 due to bandwidth
-	 * limitation. DG2 onwards pipe joiner can be enabled without
-	 * compression.
-	 * Ultrajoiner always needs compression.
-	 */
-	return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
-		num_joined_pipes == 4;
-}
-
 static int
 intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
 				       struct intel_crtc_state *pipe_config,
@@ -2826,7 +2814,7 @@ intel_dp_compute_link_for_joined_pipes(struct intel_encoder *encoder,
 
 	intel_dp_dsc_reset_config(pipe_config);
 
-	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
+	joiner_needs_dsc = intel_joiner_needs_dsc(display, num_joined_pipes);
 
 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
 		     !intel_dp_compute_config_limits(intel_dp, conn_state, pipe_config,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..17b6e270b05e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -125,8 +125,6 @@ int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
 				 int bw_overhead);
 int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
 				int max_dprx_rate, int max_dprx_lanes);
-bool intel_dp_joiner_needs_dsc(struct intel_display *display,
-			       int num_joined_pipes);
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7023619aaaba..89f107b8271c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -55,6 +55,7 @@
 #include "intel_dpio_phy.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
+#include "intel_joiner.h"
 #include "intel_link_bw.h"
 #include "intel_pfit.h"
 #include "intel_psr.h"
@@ -652,7 +653,7 @@ static int mst_stream_compute_link_for_joined_pipes(struct intel_encoder *encode
 
 	intel_dp_dsc_reset_config(pipe_config);
 
-	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
+	joiner_needs_dsc = intel_joiner_needs_dsc(display, num_joined_pipes);
 
 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
 		!mst_stream_compute_config_limits(intel_dp, conn_state,
@@ -1621,7 +1622,7 @@ mst_connector_mode_valid_ctx(struct drm_connector *_connector,
 							   bw_overhead_flags);
 		}
 
-		if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
+		if (intel_joiner_needs_dsc(display, num_joined_pipes) && !dsc) {
 			*status = MODE_CLOCK_HIGH;
 			continue;
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
new file mode 100644
index 000000000000..b9d7c9bfd1a6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+#include "intel_dp.h"
+#include "intel_joiner.h"
+
+bool intel_joiner_needs_dsc(struct intel_display *display,
+			    int num_joined_pipes)
+{
+	/*
+	 * Pipe joiner needs compression up to display 12 due to bandwidth
+	 * limitation. DG2 onwards pipe joiner can be enabled without
+	 * compression.
+	 * Ultrajoiner always needs compression.
+	 */
+	return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
+		num_joined_pipes == 4;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
new file mode 100644
index 000000000000..a091eab2f86d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_JOINER_H__
+#define __INTEL_JOINER_H__
+
+#include <linux/types.h>
+
+struct intel_display;
+
+bool intel_joiner_needs_dsc(struct intel_display *display,
+			    int num_joined_pipes);
+
+#endif /* __INTEL_JOINER_H__ */
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index b950ea6bb303..a920db3232e0 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -313,6 +313,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_hotplug_irq.o \
 	i915-display/intel_hti.o \
 	i915-display/intel_initial_plane.o \
+	i915-display/intel_joiner.o \
 	i915-display/intel_link_bw.o \
 	i915-display/intel_lspcon.o \
 	i915-display/intel_lt_phy.o \
-- 
2.50.1

[PATCH v2 52/56] drm/i915/joiner: Move joiner candidate helpers to intel_joiner.c

[Ankit Nautiyal]

Move intel_dp_joiner_candidate_valid() and the max hdisplay helper to
intel_joiner.c so any encoder can use them.
Replace the DP-only check with intel_joiner_connector_can_join(),
which uses connector type, allowing HDMI to be added later.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |  6 ++--
 drivers/gpu/drm/i915/display/intel_dp.c       | 36 -------------------
 drivers/gpu/drm/i915/display/intel_dp.h       |  9 -----
 drivers/gpu/drm/i915/display/intel_joiner.c   | 35 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_joiner.h   |  9 +++++
 5 files changed, 46 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 3e302f23f247..7c0864ed0384 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -43,6 +43,7 @@
 #include "intel_hdcp.h"
 #include "intel_hdmi.h"
 #include "intel_hotplug.h"
+#include "intel_joiner.h"
 #include "intel_link_bw.h"
 #include "intel_panel.h"
 #include "intel_pps.h"
@@ -1352,12 +1353,9 @@ void intel_connector_debugfs_add(struct intel_connector *connector)
 				    connector, &i915_dsc_fractional_bpp_fops);
 	}
 
-	if ((connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
-	     connector_type == DRM_MODE_CONNECTOR_eDP) &&
-	    intel_dp_has_joiner(intel_attached_dp(connector))) {
+	if (intel_joiner_connector_can_join(connector))
 		debugfs_create_file("i915_joiner_force_enable", 0644, root,
 				    connector, &i915_joiner_fops);
-	}
 
 	if (connector_type == DRM_MODE_CONNECTOR_DSI ||
 	    connector_type == DRM_MODE_CONNECTOR_eDP ||
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 49e4c77b5142..ba724c2e16f6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1243,11 +1243,6 @@ intel_dp_sink_format_valid(struct intel_connector *connector,
 	}
 }
 
-int intel_dp_max_hdisplay_per_pipe(struct intel_display *display)
-{
-	return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
-}
-
 bool intel_dp_has_dsc(const struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(connector);
@@ -1268,18 +1263,6 @@ bool intel_dp_has_dsc(const struct intel_connector *connector)
 	return true;
 }
 
-static
-bool intel_dp_can_join(struct intel_dp *intel_dp,
-		       int num_joined_pipes)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	if (num_joined_pipes > 1 && !intel_dp_has_joiner(intel_dp))
-		return false;
-
-	return intel_joiner_valid_primary_pipe_mask(display, num_joined_pipes);
-}
-
 bool intel_dp_dotclk_valid(struct intel_display *display,
 			   int target_clock,
 			   int htotal,
@@ -7515,25 +7498,6 @@ int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 	return sdp_guardband;
 }
 
-bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
-				     int hdisplay,
-				     int num_joined_pipes)
-{
-	struct intel_display *display = to_intel_display(connector);
-	struct intel_dp *intel_dp = intel_attached_dp(connector);
-
-	if (!intel_dp_can_join(intel_dp, num_joined_pipes))
-		return false;
-
-	if (hdisplay > num_joined_pipes * intel_dp_max_hdisplay_per_pipe(display))
-		return false;
-
-	if (connector->force_joined_pipes && connector->force_joined_pipes != num_joined_pipes)
-		return false;
-
-	return true;
-}
-
 u8 intel_dp_as_sdp_transmission_time(void)
 {
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 17b6e270b05e..26d2313f2662 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -221,20 +221,11 @@ int intel_dp_compute_config_late(struct intel_encoder *encoder,
 				 struct drm_connector_state *conn_state);
 int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
 			       bool assume_all_enabled);
-int intel_dp_max_hdisplay_per_pipe(struct intel_display *display);
 bool intel_dp_dotclk_valid(struct intel_display *display,
 			   int target_clock,
 			   int htotal,
 			   int dsc_slice_count,
 			   int num_joined_pipes);
-bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
-				     int hdisplay,
-				     int num_joined_pipes);
-
-#define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
-	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
-		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
-
 u8 intel_dp_as_sdp_transmission_time(void);
 
 int intel_dp_link_init(struct intel_dp *intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index b9d7c9bfd1a6..4c50f226199d 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -20,3 +20,38 @@ bool intel_joiner_needs_dsc(struct intel_display *display,
 	return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
 		num_joined_pipes == 4;
 }
+
+static
+int intel_joiner_max_hdisplay_per_pipe(struct intel_display *display)
+{
+	return DISPLAY_VER(display) >= 30 ? 6144 : 5120;
+}
+
+bool intel_joiner_connector_can_join(struct intel_connector *connector)
+{
+	switch (connector->base.connector_type) {
+	case DRM_MODE_CONNECTOR_DisplayPort:
+	case DRM_MODE_CONNECTOR_eDP:
+		return intel_dp_has_joiner(intel_attached_dp(connector));
+	default:
+		return false;
+	}
+}
+
+bool intel_joiner_candidate_valid(struct intel_connector *connector,
+				  int hdisplay,
+				  int num_joined_pipes)
+{
+	struct intel_display *display = to_intel_display(connector);
+
+	if (hdisplay > num_joined_pipes * intel_joiner_max_hdisplay_per_pipe(display))
+		return false;
+
+	if (connector->force_joined_pipes && connector->force_joined_pipes != num_joined_pipes)
+		return false;
+
+	if (num_joined_pipes > 1 && !intel_joiner_connector_can_join(connector))
+		return false;
+
+	return intel_joiner_valid_primary_pipe_mask(display, num_joined_pipes);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index a091eab2f86d..85e19ed1527f 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -8,9 +8,18 @@
 
 #include <linux/types.h>
 
+struct intel_connector;
 struct intel_display;
 
 bool intel_joiner_needs_dsc(struct intel_display *display,
 			    int num_joined_pipes);
+bool intel_joiner_connector_can_join(struct intel_connector *connector);
+bool intel_joiner_candidate_valid(struct intel_connector *connector,
+				  int hdisplay,
+				  int num_joined_pipes);
+
+#define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
+	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
+		for_each_if(intel_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
 #endif /* __INTEL_JOINER_H__ */
-- 
2.50.1

[PATCH v2 53/56] drm/i915/joiner: Move joiner pipe mask helper to intel_joiner.c

[Ankit Nautiyal]

intel_joiner_valid_primary_pipe_mask() implements joiner-specific
pipe validation logic and is only used by the joiner code.

Move the helper, along with find_consecutive_bits() dependency, from
intel_display.c to intel_joiner.c to keep joiner-related functionality
grouped together.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 47 --------------------
 drivers/gpu/drm/i915/display/intel_joiner.c  | 47 ++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_joiner.h  |  2 +
 3 files changed, 49 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f9233b5f5b6a..ea41432a86b7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -192,53 +192,6 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 		is_trans_port_sync_slave(crtc_state);
 }
 
-/*
- * Return a bitmask of all the start indices of consecutive bitfields of size
- * width in mask.
- */
-static unsigned long find_consecutive_bits(unsigned long mask, int width)
-{
-	unsigned long bit, out_mask = 0;
-
-	if (!width)
-		return 0;
-
-	for_each_set_bit(bit, &mask, BITS_PER_TYPE(mask)) {
-		/* For each set bit, see if the following bits are set also */
-		unsigned long bitfield = GENMASK(bit + width - 1, bit);
-
-		if ((mask & bitfield) == bitfield)
-			out_mask |= BIT(bit);
-	}
-
-	return out_mask;
-}
-
-/*
- * Return a bitmask of all valid joiner primary pipes for joining
- * num_joined_pipes pipes. For completeness, return all valid pipes for
- * num_joined_pipes == 1.
- *
- * Return 0 if the platform doesn't support joining for the requested number of
- * pipes, or there are not enough consecutive pipes available.
- */
-u8 intel_joiner_valid_primary_pipe_mask(struct intel_display *display, int num_joined_pipes)
-{
-	if (num_joined_pipes == 1) {
-		return DISPLAY_RUNTIME_INFO(display)->pipe_mask;
-	} else if (num_joined_pipes == 2) {
-		if (!HAS_UNCOMPRESSED_JOINER(display) && !HAS_BIGJOINER(display))
-			return 0;
-	} else if (num_joined_pipes == 4) {
-		if (!HAS_ULTRAJOINER(display))
-			return 0;
-	} else {
-		return 0;
-	}
-
-	return find_consecutive_bits(DISPLAY_RUNTIME_INFO(display)->pipe_mask, num_joined_pipes);
-}
-
 static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
 {
 	return ffs(crtc_state->joiner_pipes) - 1;
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index 4c50f226199d..9dfe855f5668 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -55,3 +55,50 @@ bool intel_joiner_candidate_valid(struct intel_connector *connector,
 
 	return intel_joiner_valid_primary_pipe_mask(display, num_joined_pipes);
 }
+
+/*
+ * Return a bitmask of all the start indices of consecutive bitfields of size
+ * width in mask.
+ */
+static unsigned long find_consecutive_bits(unsigned long mask, int width)
+{
+	unsigned long bit, out_mask = 0;
+
+	if (!width)
+		return 0;
+
+	for_each_set_bit(bit, &mask, BITS_PER_TYPE(mask)) {
+		/* For each set bit, see if the following bits are set also */
+		unsigned long bitfield = GENMASK(bit + width - 1, bit);
+
+		if ((mask & bitfield) == bitfield)
+			out_mask |= BIT(bit);
+	}
+
+	return out_mask;
+}
+
+/*
+ * Return a bitmask of all valid joiner primary pipes for joining
+ * num_joined_pipes pipes. For completeness, return all valid pipes for
+ * num_joined_pipes == 1.
+ *
+ * Return 0 if the platform doesn't support joining for the requested number of
+ * pipes, or there are not enough consecutive pipes available.
+ */
+u8 intel_joiner_valid_primary_pipe_mask(struct intel_display *display, int num_joined_pipes)
+{
+	if (num_joined_pipes == 1) {
+		return DISPLAY_RUNTIME_INFO(display)->pipe_mask;
+	} else if (num_joined_pipes == 2) {
+		if (!HAS_UNCOMPRESSED_JOINER(display) && !HAS_BIGJOINER(display))
+			return 0;
+	} else if (num_joined_pipes == 4) {
+		if (!HAS_ULTRAJOINER(display))
+			return 0;
+	} else {
+		return 0;
+	}
+
+	return find_consecutive_bits(DISPLAY_RUNTIME_INFO(display)->pipe_mask, num_joined_pipes);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
index 85e19ed1527f..962b9724c112 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.h
+++ b/drivers/gpu/drm/i915/display/intel_joiner.h
@@ -22,4 +22,6 @@ bool intel_joiner_candidate_valid(struct intel_connector *connector,
 	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
 		for_each_if(intel_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
+u8 intel_joiner_valid_primary_pipe_mask(struct intel_display *display, int num_joined_pipes);
+
 #endif /* __INTEL_JOINER_H__ */
-- 
2.50.1

[PATCH v2 54/56] drm/i915/hdmi: Iterate through joiner candidates in compute_config path

[Ankit Nautiyal]

A mode that exceeds a single pipe's max dotclock can still be driven by
splitting it across joined pipes. Iterate over the joiner candidates in the
HDMI compute_config path, and pick the first pipe count
that can carry the mode, setting crtc_state->joiner_pipes accordingly.

Allowing these joiner-capable modes in the mode_valid path is handled in
a subsequent change.

Some joiner configurations need DSC to work. Since HDMI DSC will be enabled
in subsequent changes, such configurations are skipped for now.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 67 +++++++++++++++++++++--
 1 file changed, 63 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index e3dbd71a3652..2ec7d2a5e7d4 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -64,6 +64,7 @@
 #include "intel_hdcp_shim.h"
 #include "intel_hdmi.h"
 #include "intel_hdmi_frl_dfm.h"
+#include "intel_joiner.h"
 #include "intel_link_bw.h"
 #include "intel_lspcon.h"
 #include "intel_lt_phy.h"
@@ -2453,8 +2454,8 @@ intel_hdmi_compute_frl_config(struct intel_encoder *encoder,
 }
 
 static int
-intel_hdmi_compute_frl_clock(struct intel_encoder *encoder,
-			     struct intel_crtc_state *crtc_state)
+_intel_hdmi_compute_frl_clock(struct intel_encoder *encoder,
+			      struct intel_crtc_state *crtc_state)
 {
 	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
 	int max_bpc = max(crtc_state->pipe_bpp / 3, 8);
@@ -2485,13 +2486,70 @@ intel_hdmi_compute_frl_clock(struct intel_encoder *encoder,
 	return -EINVAL;
 }
 
+static int
+intel_hdmi_compute_clock_for_joined_pipes(struct intel_encoder *encoder,
+					  struct intel_crtc_state *crtc_state,
+					  struct intel_connector *connector)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	int ret;
+
+	if (intel_joiner_needs_dsc(display, num_joined_pipes))
+		return -EINVAL;
+
+	ret = _intel_hdmi_compute_frl_clock(encoder, crtc_state);
+	if (ret || !intel_dp_dotclk_valid(display,
+					  adjusted_mode->crtc_clock,
+					  adjusted_mode->crtc_htotal,
+					  0,
+					  num_joined_pipes))
+		return -EINVAL;
+
+	return 0;
+}
+
+static int
+intel_hdmi_compute_frl_clock(struct intel_encoder *encoder,
+			     struct intel_crtc_state *crtc_state,
+			     struct intel_connector *connector)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct drm_display_mode *adjusted_mode =
+		&crtc_state->hw.adjusted_mode;
+	int num_joined_pipes;
+	int ret = -EINVAL;
+
+	for_each_joiner_candidate(connector, adjusted_mode, num_joined_pipes) {
+		if (!(intel_joiner_valid_primary_pipe_mask(display, num_joined_pipes) & BIT(crtc->pipe)))
+			continue;
+
+		if (num_joined_pipes > 1)
+			crtc_state->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1,
+							   crtc->pipe);
+		ret = intel_hdmi_compute_clock_for_joined_pipes(encoder, crtc_state, connector);
+
+		if (ret == 0)
+			break;
+	}
+
+	if (ret < 0)
+		crtc_state->joiner_pipes = 0;
+
+	return ret;
+}
+
 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
 				    struct intel_crtc_state *crtc_state,
+				    struct intel_connector *connector,
 				    bool respect_downstream_limits,
 				    bool enable_frl)
 {
 	if (enable_frl)
-		return intel_hdmi_compute_frl_clock(encoder, crtc_state);
+		return intel_hdmi_compute_frl_clock(encoder, crtc_state, connector);
 
 	return intel_hdmi_compute_tmds_clock(encoder, crtc_state, respect_downstream_limits);
 }
@@ -2563,7 +2621,8 @@ static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
 	crtc_state->sink_format = sink_format;
 	crtc_state->output_format = intel_hdmi_output_format(crtc_state);
 
-	return intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits, enable_frl);
+	return intel_hdmi_compute_clock(encoder, crtc_state, connector,
+					respect_downstream_limits, enable_frl);
 }
 
 static int _intel_hdmi_compute_formats(struct intel_encoder *encoder,
-- 
2.50.1

[PATCH v2 55/56] drm/i915/hdmi: Iterate through joiner candidates in mode_valid path

[Ankit Nautiyal]

Modes exceeding a single pipe's dotclock were rejected in mode_valid even
when they could be driven by joining pipes. Iterate the joiner candidates
and allow a mode if it fits with joining, relaxing the dotclock ceiling by
the joined pipe count. Joiner configs needing DSC are pruned for
now, since HDMI DSC comes later.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 51 ++++++++++++++++++-----
 1 file changed, 40 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 2ec7d2a5e7d4..2c7c47a3c61d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2132,20 +2132,55 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
 	struct intel_display *display = to_intel_display(connector);
 	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
 	enum drm_mode_status status;
+	int num_joined_pipes;
 
 	status = intel_hdmi_sink_format_valid(connector, mode,
 					      has_hdmi_sink, sink_format);
 	if (status != MODE_OK)
 		return status;
 
-	status = intel_pfit_mode_valid(display, mode, sink_format, 0);
-	if (status != MODE_OK)
+	status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock,
+						  has_hdmi_sink, sink_format);
+
+	if (status == MODE_OK)
+		return status;
+
+	/*
+	 * Joiner is supported only with FRL mode.
+	 * If a mode is not supported with TMDS and FRL is not supported,
+	 * prune the mode.
+	 */
+	if (status != MODE_OK && !intel_hdmi_can_support_frl(hdmi))
 		return status;
 
-	status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
+	for_each_joiner_candidate(connector, mode, num_joined_pipes) {
+		if (intel_joiner_needs_dsc(display, num_joined_pipes)) {
+			status = MODE_CLOCK_HIGH;
+			continue;
+		}
+
+		status = intel_pfit_mode_valid(display, mode, sink_format,
+					       num_joined_pipes);
+		if (status != MODE_OK)
+			continue;
+
+		status = intel_mode_valid_max_plane_size(display, mode,
+							 num_joined_pipes);
+		if (status != MODE_OK)
+			continue;
+
+		if (!intel_dp_dotclk_valid(display, clock, mode->htotal, 0,
+					   num_joined_pipes)) {
+			status = MODE_CLOCK_HIGH;
+			continue;
+		}
 
-	if (status != MODE_OK && intel_hdmi_can_support_frl(hdmi))
 		status = intel_hdmi_frl_mode_clock_valid(connector, mode, sink_format);
+		if (status != MODE_OK)
+			continue;
+
+		break;
+	}
 
 	return status;
 }
@@ -2160,7 +2195,6 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
 	const struct drm_display_info *info = &connector->base.display_info;
 	enum drm_mode_status status;
 	int clock = mode->clock;
-	int max_dotclk = display->cdclk.max_dotclk_freq;
 	bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state);
 
 	status = intel_cpu_transcoder_mode_valid(display, mode);
@@ -2170,9 +2204,6 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
 	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
 		clock *= 2;
 
-	if (clock > max_dotclk)
-		return MODE_CLOCK_HIGH;
-
 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
 		if (!has_hdmi_sink)
 			return MODE_CLOCK_LOW;
@@ -2197,10 +2228,8 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
 			status = intel_hdmi_mode_valid_format(connector, mode, clock, has_hdmi_sink,
 							      INTEL_OUTPUT_FORMAT_YCBCR420);
 	}
-	if (status != MODE_OK)
-		return status;
 
-	return intel_mode_valid_max_plane_size(display, mode, 1);
+	return status;
 }
 
 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
-- 
2.50.1

[PATCH v2 56/56] drm/i915/hdmi: Allow Pipe joiner for HDMI

[Ankit Nautiyal]

Pipe joiner is used only with FRL mode, so allow it only when the platform
and the sink both support FRL.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c   | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h   | 1 +
 drivers/gpu/drm/i915/display/intel_joiner.c | 4 ++++
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 2c7c47a3c61d..2955ab5880fe 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -4378,3 +4378,11 @@ void intel_hdmi_frl_get_config(struct intel_crtc_state *crtc_state)
 
 	intel_hdmi_frl_dfm_read(crtc_state);
 }
+
+bool intel_hdmi_has_joiner(struct intel_hdmi *intel_hdmi)
+{
+	struct intel_display *display = to_intel_display(intel_hdmi);
+	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
+
+	return HAS_HDMI_FRL(display) && intel_bios_hdmi_max_frl_rate(encoder->devdata);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 71b12f557d75..b0b40e46b568 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -87,6 +87,7 @@ int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector);
 int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector);
 void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state);
 void intel_hdmi_frl_get_config(struct intel_crtc_state *crtc_state);
+bool intel_hdmi_has_joiner(struct intel_hdmi *intel_hdmi);
 
 /* FRL rate per lane (Gbps) -> PHY PLL table units (10 kbps) */
 #define FRL_GBPS_TO_10KBPS(rate)	((rate) * 100000)
diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
index 9dfe855f5668..9330d53e3cb4 100644
--- a/drivers/gpu/drm/i915/display/intel_joiner.c
+++ b/drivers/gpu/drm/i915/display/intel_joiner.c
@@ -6,6 +6,7 @@
 #include "intel_display_core.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_hdmi.h"
 #include "intel_joiner.h"
 
 bool intel_joiner_needs_dsc(struct intel_display *display,
@@ -33,6 +34,9 @@ bool intel_joiner_connector_can_join(struct intel_connector *connector)
 	case DRM_MODE_CONNECTOR_DisplayPort:
 	case DRM_MODE_CONNECTOR_eDP:
 		return intel_dp_has_joiner(intel_attached_dp(connector));
+	case DRM_MODE_CONNECTOR_HDMIA:
+	case DRM_MODE_CONNECTOR_HDMIB:
+		return intel_hdmi_has_joiner(intel_attached_hdmi(connector));
 	default:
 		return false;
 	}
-- 
2.50.1

Re: [PATCH v2 19/56] drm/i915/ltphy: Add PLL tables for HDMI FRL

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: typo in xe3plpd_lt_hdmi_10g0 PLL table causes write to register 0x0000
--

commit 42b740d6bfd04d2cc3cafcf973149a0f98931b3a
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/ltphy: Add PLL tables for HDMI FRL

Add HDMI FRL Tables for LT PHY i.e for the rates of 3G, 6G, 8G,
10G and 12G.

> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 86492651b01d5..61bad87eefec2 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c

[ ... ]

> +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_10g0 = {
> +	.config = {
> +		0x1d,

[Severity: High]
Is this config value a typo? The progression in other FRL tables appears to
increment by 8 for the top nibble (3G=0x85, 6G=0x8d, 8G=0x95, 12G=0xa5).
Should this be 0x9d instead of 0x1d?

> +		0x2d,
> +		0x0,
> +	},
> +	.addr_msb = {
> +		0x85,
> +		0x85,
> +		0x85,
> +		0x85,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x86,
> +		0x00,

[Severity: High]
Is 0x00 the intended value for addr_msb[9]? When combined with addr_lsb[9],
this will cause the configuration data to be written to hardware register
0x0000. It looks like it might be a typo for 0x86.

> +		0x86,
> +		0x86,
> +		0x86,
> +	},
> +	.addr_lsb = {
> +		0x10,
> +		0x0c,
> +		0x14,
> +		0xe4,
> +		0x0c,
> +		0x10,
> +		0x14,
> +		0x18,
> +		0x48,
> +		0x00,

[Severity: High]
Could this 0x00 value for addr_lsb[9] also be a typo? This completes the
invalid register address 0x0000. Writing the corresponding data payload
{ 0x27, 0x8, 0x0, 0x0 } to register 0x0000 could overwrite unrelated hardware
state, and failing to program the intended register (likely 0x8640) might
prevent successful link training for 10Gbps HDMI FRL.

> +		0x4c,
> +		0x24,
> +		0x44,
> +	},

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=19

Re: [PATCH v2 04/56] drm/drm_scdc_helper: Add SCDC helper funcs for FRL

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/display: Unnecessary I2C read in drm_scdc_disable_frl()
--

commit 4f7a237d2d408c021d966e908effa3af04d82b79
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/drm_scdc_helper: Add SCDC helper funcs for FRL

This commit introduces SCDC register definitions and helper functions
to configure and monitor FRL (Fixed Rate Link) link training between
the source and sink.

> diff --git a/drivers/gpu/drm/display/drm_scdc_helper.c b/drivers/gpu/drm/display/drm_scdc_helper.c
> --- a/drivers/gpu/drm/display/drm_scdc_helper.c
> +++ b/drivers/gpu/drm/display/drm_scdc_helper.c
[ ... ]
> +int drm_scdc_disable_frl(struct i2c_adapter *adapter)
> +{
> +	u8 config;
> +	int ret;
> +
> +	ret = drm_scdc_readb(adapter, SCDC_CONFIG_1, &config);
> +	if (ret)
> +		return ret;
> +
> +	config &= ~SCDC_FRL_RATE;
> +
> +	return drm_scdc_writeb(adapter, SCDC_CONFIG_1, config);

[Severity: Low]
Is this read-modify-write sequence strictly necessary here?

The SCDC_CONFIG_1 register contains only SCDC_FRL_RATE (bits 0-3) and
SCDC_FFE_LEVELS (bits 4-7). Since FFE levels are only meaningful when FRL is
enabled, preserving them during disable is likely unnecessary.

Given that reading over the slow I2C DDC bus adds measurable latency, and
drm_scdc_config_frl() successfully treats the register as fully known by
issuing a direct write without a preceding read, would it be better to just
issue a direct write of 0 to clear the register entirely?

> +}
> +EXPORT_SYMBOL(drm_scdc_disable_frl);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=4

Re: [PATCH v2 31/56] drm/i915/hdmi: Add helper to write FRL CFG register

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915: missing clear mask in intel_hdmi_frl_cfg_write() causes register corruption
--

commit 0a0fe491d4ed801c5c5d75f8cf1134e058f90bcb
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Add helper to write FRL CFG register

This commit introduces a helper function, intel_hdmi_frl_cfg_write(), to
write FRL CFG register bits.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> +void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_trans = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	if (!crtc_state->frl.enable)
> +		return;
> +
> +	val = TRANS_HDMI_R_B_SCHED_ENABLE(crtc_state->frl.rsrc_sched_en);
> +	val |= TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(crtc_state->frl.active_char_buf_threshold);
> +	val |= TRANS_HDMI_MIN_BLANK_CHAR(TRANS_HDMI_MIN_BLANK_CHAR_VAL);
> +
> +	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);

[Severity: Medium]
Will this read-modify-write operation accumulate stale bits across multiple
modesets?

The intel_de_rmw() implementation computes the new register value using
(old_val & ~clear) | set. Because 0 is passed as the clear mask here, the new
configuration values are simply bitwise OR'd against the old register state.

This means multi-bit fields like active_char_buf_threshold could accumulate
bits (e.g. changing from 010 to 001 results in 011), and boolean flags like
rsrc_sched_en might not transition from true to false once set.

Should the clear mask explicitly include TRANS_HDMI_R_B_SCHED_ENABLE_MASK,
TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, and TRANS_HDMI_MIN_BLANK_CHAR_MASK?

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=31

Re: [PATCH v2 23/56] drm/i915/ddi_buf: Add Vswing table for HDMI FRL

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: HDMI TMDS mode restricted from using new Vswing table
--

commit 1071ffaee88538fd9a5d81d11c59c1e1061c15b6
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/ddi_buf: Add Vswing table for HDMI FRL

This commit defines a Vswing table for HDMI FRL to set signal levels
for LT PHY on Xe3PLPD and onwards.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index cc5912178d9cd..597bf1c781045 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
[ ... ]
> @@ -1164,6 +1165,14 @@ static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_edp[] = {
>  	{ .lt = { 1, 3, 0, 26, 0 } },
>  };
>  
> +static const union intel_ddi_buf_trans_entry _xe3plpd_lt_trans_hdmi_frl[] = {
> +	{ .lt = { 0, 0, 0, 48, 0  } },
> +	{ .lt = { 0, 0, 4, 38, 6  } },
> +	{ .lt = { 0, 0, 4, 36, 8  } },
> +	{ .lt = { 0, 0, 4, 34, 10 } },
> +	{ .lt = { 0, 0, 4, 32, 12 } },
> +};
> +
>  static const struct intel_ddi_buf_trans xe3plpd_lt_trans_dp14 = {
>  	.entries = _xe3plpd_lt_trans_dp14,
>  	.num_entries = ARRAY_SIZE(_xe3plpd_lt_trans_dp14),
>  };

[Severity: High]
Because xe3plpd_lt_trans_dp14 lacks an explicit .hdmi_default_entry,
intel_ddi_hdmi_level() will silently default to index 0.

Index 0 of the dp14 table is { .lt = { 1, 0, 0, 21, 0 } }, which provides
a very low voltage swing of 21 instead of the 48 that is intended for
HDMI TMDS.

[ ... ]
> @@ -1780,6 +1794,9 @@ xe3plpd_get_lt_buf_trans(struct intel_encoder *encoder,
>  		return intel_get_buf_trans(&xe3plpd_lt_trans_uhbr, n_entries);
>  	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
>  		return intel_get_buf_trans(&xe3plpd_lt_trans_edp, n_entries);
> +	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> +		 intel_hdmi_is_frl(crtc_state->port_clock))
> +		return intel_get_buf_trans(&xe3plpd_lt_trans_hdmi_frl, n_entries);
>  	else
>  		return intel_get_buf_trans(&xe3plpd_lt_trans_dp14, n_entries);
>  }

[Severity: High]
Does this condition incorrectly restrict HDMI TMDS outputs from utilizing
the new _xe3plpd_lt_trans_hdmi_frl table?

The newly introduced _xe3plpd_lt_trans_hdmi_frl table contains the entry
{ .lt = { 0, 0, 0, 48, 0 } } at index 0. This index is never accessed
during FRL training because intel_hdmi_frl_level() strictly returns 1-4.
The index 0 entry (voltage swing 48) appears to be explicitly designed
for HDMI TMDS.

However, by gating the use of this table with intel_hdmi_is_frl() here
in xe3plpd_get_lt_buf_trans(), HDMI TMDS configurations bypass it and
fall through to the xe3plpd_lt_trans_dp14 fallback table.

Because of the missing .hdmi_default_entry discussed above, this fallback
causes HDMI TMDS outputs to resolve to an invalid voltage swing of 21.

Could this result in poor signal integrity or link training failures for
TMDS HDMI sinks?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=23

Re: [PATCH v2 18/56] drm/i915/hdmi: Drive per-lane TxFFE during FRL link training

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] drm/i915/hdmi: FRL link training pattern dropped and hardware update inverted on FFE change
- [Medium] drm/i915/hdmi: FFE_Levels unconditionally advertised as 3 for all FRL rates
- [Medium] drm/i915/hdmi: Premature PHY TxFFE0 programming in LTS:2 before FRL is enabled
--

commit 87ef0f5ae2b4f4dd3dfe980d42af7aa5011177a4
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/hdmi: Drive per-lane TxFFE during FRL link training

This commit hooks the per-lane TxFFE state into the HDMI FRL Link
Training Sequence. It configures the SCDC FFE_Levels, sets initial
TxFFE0 levels upon FRL enable, and handles sink-requested FFE
changes during LTS:3 lane training.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0873ecd6ef714..1aa6f71fbfce2 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -3619,7 +3620,8 @@ intel_hdmi_frl_prepare_lts2(struct intel_encoder *encoder,
>  	if (ret & SCDC_FLT_UPDATE)
>  		clear_scdc_update_flags(encoder, SCDC_FLT_UPDATE);
>  
> -	/* #TODO: Source shall program TxFFE = 0 for all active lanes */
> +	/* ffe_level[] was cleared by intel_hdmi_reset_frl_config(). */
> +	encoder->set_signal_levels(encoder, crtc_state);

[Severity: Medium]
The commit message explicitly states: "On LTS:3 entry, after enabling
TRANS_HDMI_FRL_ENABLE, call encoder->set_signal_levels() so the PHY is
programmed to TxFFE0".

However, does this code call encoder->set_signal_levels() prematurely? It
appears to execute inside intel_hdmi_frl_prepare_lts2(), which runs during
the LTS:2 phase before FRL mode is actually enabled via
TRANS_HDMI_FRL_ENABLE in intel_hdmi_frl_train_lts3().

If the underlying PHY requires the transcoder to be in FRL mode to accept
or apply FRL signal levels properly, could this premature sequence cause
hardware misconfiguration?

[ ... ]
> @@ -3684,16 +3688,20 @@ intel_hdmi_train_lanes(struct intel_encoder *encoder,
>  		if (ltp[lane] == SCDC_FRL_LTP3)
>  			continue;
>  
> -		if (ltp[lane] >= SCDC_FRL_LTP1 && ltp[lane] <= SCDC_FRL_LTP8)
> +		if (ltp[lane] >= SCDC_FRL_LTP1 && ltp[lane] <= SCDC_FRL_LTP8) {
>  			write_buf |= TRANS_HDMI_FRL_LTP(ltp[lane], lane);
> -
> -		/* #TODO handle FFE change */
> -		else if (ltp[lane] == SCDC_FRL_CHNG_FFE)
> -			continue;
> +		} else if (ltp[lane] == SCDC_FRL_CHNG_FFE &&
> +			   intel_hdmi->frl.ffe_level[lane] < intel_hdmi->frl.max_ffe_level) {
> +			intel_hdmi->frl.ffe_level[lane]++;
> +			ffe_changed = true;
> +		}
>  	}
>  
>  	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
>  
> +	if (ffe_changed)
> +		encoder->set_signal_levels(encoder, crtc_state);

[Severity: High]
Does this implementation inadvertently clear the link training pattern when
the sink requests an FFE change?

When ltp[lane] == SCDC_FRL_CHNG_FFE is evaluated, the FFE level is
incremented, but no pattern bits are preserved in write_buf for that lane.
Since write_buf is initially 0, intel_de_write() will overwrite the
TRANS_HDMI_FRL_TRAIN register with 0 (NO_LTP) for that lane, which could
break the link training sequence.

Additionally, the HDMI 2.1 specification dictates that when a sink requests
an FFE level change (0xE), the source must first update the FFE level on
the lane and then re-transmit the same Link Training Pattern. Here,
intel_de_write() is executed before the PHY FFE level update in
encoder->set_signal_levels(). Does this ordering violate the hardware
sequencing requirement?

[ ... ]
> @@ -3791,9 +3799,9 @@ static int get_next_frl_rate(int curr_rate_gbps)
>  	return -EINVAL;
>  }
>  
> -static int get_ffe_level(int rate_gbps)
> +static int get_max_ffe_level(int rate_gbps)
>  {
> -	return 0;
> +	return 3;
>  }

[Severity: Medium]
Does unconditionally returning 3 here violate the HDMI 2.1 specification
for lower FRL rates?

The specification (Section 10.3.3.4.1) mandates that for FRL rates of 3
Gbps and 6 Gbps (total link rates of 9, 18, 24 Gbps), the source shall set
the FFE_Levels field to 0.

Advertising 3 at these lower rates is a spec violation and might lead to
unexpected sink behavior, false FFE adjustment requests, or compliance test
failures. Should this function evaluate rate_gbps before returning the max
level?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=18

Re: [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm: hardcoded platform check disables FRL on newer hardware
- [High] drm/hdmi: FRL incorrectly disabled when VBT specifies platform default rate
--

commit df17bdb1a2102d3ca65a52512220409d6c6fe624
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi: Parse FRL max link rate from VBT

Parse the maximum FRL link rate from VBT and store it for use
during FRL mode selection and link training.

> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 7b6a6f8c3cf19..7181237508b3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
[ ... ]
> @@ -2788,12 +2788,45 @@ static bool is_port_valid(struct intel_display *display, enum port port)
>  	return true;
>  }
>  
> +int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data *devdata)
> +{
> +	struct intel_display *display = devdata->display;
> +
> +	if (display->vbt.version < 237)
> +		return 0;
> +
> +	/*
> +	 * When hdmi_max_frl_rate_valid is 0 the VBT does not specify a maximum
> +	 * FRL rate, so don't use it to limit the FRL rate on FRL-capable
> +	 * platforms.
> +	 */
> +	if (!devdata->child.hdmi_max_frl_rate_valid)
> +		return display->platform.meteorlake ? 12000000 : 0;

[Severity: High]
Does this hardcoded check disable FRL on newer hardware?

By restricting the fallback rate exclusively to Meteorlake, 0 is returned
for all newer FRL-capable platforms (e.g., Lunar Lake, Panther Lake) when
the VBT lacks a valid max FRL rate.

Downstream callers like intel_hdmi_compute_config() in intel_hdmi.c use
the return value as a boolean condition:

    if (HAS_HDMI_FRL(display) && intel_bios_hdmi_max_frl_rate(encoder->devdata) && ...)
        enable_frl = true;

Returning 0 causes enable_frl to evaluate to false, which means FRL will
never be enabled on newer hardware architectures under these conditions.

> +
> +	switch (devdata->child.hdmi_max_frl_rate) {
> +	default:
> +	case HDMI_MAX_FRL_RATE_PLATFORM:
> +		return 0;

[Severity: High]
Does returning 0 here inadvertently disable FRL when the VBT specifies
the platform default rate?

Although the comment above mentions that a missing VBT specification
should not limit the FRL rate, returning 0 signals callers to completely
disable FRL rather than applying a platform fallback.

Later in the series, the caller logic in intel_hdmi_compute_config()
treats 0 as a strict boolean requirement and cap:

    if (HAS_HDMI_FRL(display) &&
        intel_bios_hdmi_max_frl_rate(encoder->devdata) &&
        intel_hdmi->has_sink_hdmi_21)
        enable_frl = true;

Because intel_bios_hdmi_max_frl_rate() returns 0, enable_frl stays false
and the rate cap becomes 0. This completely disables HDMI 2.1 Fixed
Rate Link capabilities on any platform where the VBT is configured to use
the platform's native default or if the VBT is older than version 237.

> +	case HDMI_MAX_FRL_RATE_3G:
> +		return 3000000;
> +	case HDMI_MAX_FRL_RATE_6G:
> +		return 6000000;
> +	case HDMI_MAX_FRL_RATE_8G:
> +		return 8000000;
> +	case HDMI_MAX_FRL_RATE_10G:
> +		return 10000000;
> +	case HDMI_MAX_FRL_RATE_12G:
> +		return 12000000;
> +	}
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=1

Re: [PATCH v2 27/56] drm/i915/hdmi_frl_dfm_regs: Define DFM registers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] drm/i915: Typo in TB_MIN_THESHOLD macro names
--

commit 630f464ba2dd2b53e20d33d3caf2861bb55f1fa9
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi_frl_dfm_regs: Define DFM registers

This commit adds definitions for HDMI FRL dataflow metering registers to
handle DFM values.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h
> new file mode 100644
> index 0000000000000..bb5cb76b3806b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm_regs.h

[ ... ]

> +#define _TRANS_HDMI_FRL_DFMTHRSH_A			0x600c4
> +#define TRANS_HDMI_FRL_DFMTHRSH(dev_priv, trans)	_MMIO_TRANS2(dev_priv, \
> +								     trans, \
> +								     _TRANS_HDMI_FRL_DFMTHRSH_A)
> +#define  RUN_LEN_THRESHOLD_MASK				REG_GENMASK(31, 24)
> +#define  RUN_LEN_THRESHOLD(val)				REG_FIELD_PREP(RUN_LEN_THRESHOLD_MASK, val)
> +#define  TB_MAX_THRESHOLD_MASK				REG_GENMASK(21, 12)
> +#define  TB_MAX_THRESHOLD(val)				REG_FIELD_PREP(TB_MAX_THRESHOLD_MASK, val)
> +#define  TB_MIN_THESHOLD_MASK				REG_GENMASK(9, 0)
> +#define  TB_MIN_THESHOLD(val)				REG_FIELD_PREP(TB_MIN_THESHOLD_MASK, val)

[Severity: Low]
This isn't a bug, but there appears to be a typo in the names of these
minimum threshold macros where THRESHOLD is spelled as THESHOLD. Could
these be updated to include the missing R for consistency with the
TB_MAX_THRESHOLD macros defined just above?

> +
> +#endif /* __INTEL_HDMI_FRL_DFM_REGS_H__ */

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=27

Re: [PATCH v2 08/56] drm/i915/ddi: Update Transcoder/DDI registers with the frl bits

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/ddi: RMW race on XELPDP_PORT_BUF_CTL1 drops concurrent updates
--

commit b719c1e4da553224ed64e6f2c9076a3b63adb0c1
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/ddi: Update Transcoder/DDI registers with the frl bits

This commit updates the Transcoder and DDI/PORT registers for HDMI FRL mode.
It sets the lane count, FRL shifter enable, and data width bits in both the
DDI_BUF_CTL and PORT_BUF_CTL registers.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index a46ab5d3d70fc..576e667746782 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3121,12 +3121,20 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum port port = encoder->port;
> +	u32 val;
>  
>  	intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
>  
>  	if (DISPLAY_VER(display) >= 14)
>  		intel_wait_ddi_buf_idle(display, port);
>  
> +	/* Clear PORT_BUF_CTL HDMI FRL Shifter Enable to 0 */
> +	if (crtc_state->frl.enable) {
> +		val = intel_de_read(display, XELPDP_PORT_BUF_CTL1(display, port));
> +		intel_de_write(display, XELPDP_PORT_BUF_CTL1(display, port),
> +			       val & ~XELPDP_PORT_HDMI_FRL_SHFTR_EN);

[Severity: High]
Can this manual read-modify-write sequence race with concurrent register
updates?

Looking at intel_ddi_buf_disable(), the sequence uses intel_de_read() followed
by intel_de_write() to clear the XELPDP_PORT_HDMI_FRL_SHFTR_EN bit in the
XELPDP_PORT_BUF_CTL1 register.

Because this manual sequence drops the uncore spinlock and DMC wakelock
between the read and the write, it creates a window where asynchronous Type-C
hotplug workers in intel_tc.c might concurrently modify shared bits in the
same register, such as XELPDP_TCSS_POWER_REQUEST or XELPDP_TC_PHY_OWNERSHIP.

Any concurrent update by a TC worker or another intel_de_rmw() operation
during this window could be permanently overwritten and lost by the subsequent
intel_de_write(), leading to potential display or Type-C PHY state corruption.

Should this use intel_de_rmw() instead to guarantee atomicity and continuity
of the uncore lock and DMC wakelock?

> +	}
> +
>  	mtl_ddi_disable_d2d(encoder);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=8

Re: [PATCH v2 21/56] drm/i915/ltphy: Calculate port clock for HDMI FRL

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/ltphy: Fragile FRL mode check misidentifies 300MHz/600MHz TMDS as FRL
--

commit c8e5d35c7adb72d4a07659a9da4c78974ed1e816
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/ltphy: Calculate port clock for HDMI FRL

Define function to get the port clock after we read VDR0_CONFIG.
This helps us determine the port clock for HDMI FRL use case in LT
PHY.

> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 0e2ebd550bc5e..7ac0888cdf452 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2000,6 +2019,10 @@ intel_lt_phy_calc_port_clock(struct intel_display *display,
>  		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
>  				      lt_state->config[0]);
>  		clk = intel_lt_phy_get_dp_clock(rate);
> +	} else if (mode == MODE_HDMI_FRL) {
> +		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
> +				      lt_state->config[0]);
> +		clk = intel_lt_phy_get_hdmi_frl_clock(rate);

[Severity: High]
Does returning valid FRL clocks from readout here expose an issue where 300MHz
and 600MHz TMDS modes are misidentified as FRL?

The driver relies on clock value guessing via intel_hdmi_is_frl(port_clock)
instead of checking protocol state (like crtc_state->frl.enable or
ltpll->config[0]) to distinguish FRL modes from TMDS.

Because 300MHz and 600MHz are both valid TMDS character rates and FRL link
rates, a TMDS mode running at exactly 300MHz or 600MHz (such as custom 4K or
1440p timings) will be misidentified as FRL.

This leads to incorrect PHY PLL state calculation and wrong port clock
programming in intel_lt_phy_program_port_clock_ctl():

	if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
	else
		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

Programming DIV18CLK instead of MAXPCLK will cause display failure for these
TMDS modes.

>  	} else if (mode == MODE_HDMI_20) {
>  		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
>  	} else {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=21

Re: [PATCH v2 02/56] drm/i915/hdmi: Add new data members for FRL configuration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm: NULL pointer dereference in intel_bios_hdmi_max_frl_rate() via devdata
- [Medium] drm/i915: FRL rate incorrectly clamped to 0 when VBT specifies platform limit
--

commit 7ad38de828b7ee44dcbd47b61d9385aa21e165af
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Add new data members for FRL configuration

This commit adds new members to crtc_state and intel_hdmi to identify
FRL-supporting HDMI sinks. It also tracks the FRL training information
after a successful link training.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b6fa1a1558b82..69534eea78a15 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -2545,6 +2547,38 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector)
>  	}
>  }
>  
> +static void
> +intel_hdmi_reset_frl_config(struct intel_hdmi *intel_hdmi)
> +{
> +	intel_hdmi->frl.trained = false;
> +	intel_hdmi->frl.lanes = 0;
> +	intel_hdmi->frl.rate_gbps = 0;
> +	intel_hdmi->frl.ffe_level = 0;
> +}
> +
> +static void
> +intel_hdmi_init_frl_config(struct intel_connector *connector)
> +{
> +	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
> +	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
> +	int max_src_frl_rate =
> +		DIV_ROUND_UP(intel_bios_hdmi_max_frl_rate(encoder->devdata), 1000000) * 4;

[Severity: High]
Is there a risk of a NULL pointer dereference here?

When intel_hdmi_set_edid() detects a digital display, it calls
intel_hdmi_init_frl_config() which unconditionally evaluates encoder->devdata
in the call to intel_bios_hdmi_max_frl_rate().

However, the devdata field in struct intel_encoder is documented as:
/* VBT information for this encoder (may be NULL for older platforms) */

If devdata is NULL, intel_bios_hdmi_max_frl_rate() will immediately
dereference it:

int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data *devdata)
{
	struct intel_display *display = devdata->display;
    ...

Could this cause a crash upon connecting an HDMI display on platforms that
lack VBT port data?

> +	int max_sink_dsc_frl_rate =
> +		intel_hdmi_sink_dsc_max_frl_rate(&connector->base);
> +	int max_sink_frl_rate =
> +		intel_hdmi_sink_max_frl_rate(&connector->base);
> +
> +	intel_hdmi->has_sink_hdmi_21 = max_sink_frl_rate > 0;
> +
> +	intel_hdmi->max_frl_rate = min(max_sink_frl_rate,
> +				       max_src_frl_rate);

[Severity: Medium]
Does this clamp the maximum FRL rate to 0 Gbps for capable platforms?

When the VBT specifies HDMI_MAX_FRL_RATE_PLATFORM, or when no limit is
provided for platforms other than Meteorlake, intel_bios_hdmi_max_frl_rate()
returns 0.

This 0 value is converted to a max_src_frl_rate of 0, which is then passed
into this min() assignment. As a result, intel_hdmi->max_frl_rate becomes 0.

Will this unintentionally disable FRL on capable platforms that rely on the
default platform limit?

> +
> +	intel_hdmi->max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
> +					   max_src_frl_rate);
> +
> +	intel_hdmi_reset_frl_config(intel_hdmi);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=2

Re: [PATCH v2 20/56] drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/ltphy: Valid TMDS modes with FRL-like clocks get misidentified as FRL
--

commit 24fcf65234b436b2c1d8a2379615e06c2dcf0888
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state

This commit adds a safeguard in intel_lt_phy_pll_calc_state() to skip the
HDMI TMDS dynamic PLL calculation when an HDMI FRL mode is in use. It
determines this by checking if the port clock matches an FRL rate.

> drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state

This isn't a bug, but there is a typo (safegaurd) in the subject line.

> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 61bad87eefec2..0e2ebd550bc5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2042,7 +2042,8 @@ intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state,
>  		}
>  	}
>  
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
> +	    !intel_hdmi_is_frl(crtc_state->port_clock)) {

[Severity: Medium]
Does this logic mistakenly prevent the TMDS dynamic calculation for 300MHz
and 600MHz TMDS modes?

Looking at intel_hdmi_is_frl(), it only checks if the numeric clock rate
matches one of the FRL rates:

drivers/gpu/drm/i915/display/intel_hdmi.c:intel_hdmi_is_frl() {
	static const u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 };
	...
	for (i = 0; i < ARRAY_SIZE(rates); i++)
		if (intel_dpll_clock_matches(clock, rates[i]))
			return true;

	return false;
}

Since 300MHz and 600MHz can also be valid TMDS pixel clocks, a TMDS mode
with exactly these clock rates would cause intel_hdmi_is_frl() to return
true.

This would block the fallback intel_lt_phy_calculate_hdmi_state()
calculation for those valid TMDS modes.

Should this check verify the protocol state instead, for example by checking
if crtc_state->frl.enable is true?

>  		hw_state->ltpll.lane_count = crtc_state->lane_count;
>  		return intel_lt_phy_calculate_hdmi_state(&hw_state->ltpll,
>  							 crtc_state->port_clock);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=20

Re: [PATCH v2 32/56] drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] i915/display: spelling mistake in TB_MIN_THESHOLD macro usage
--

commit 468a8e227948c1192c42e05f62742d8315145e2f
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers

This commit introduces helpers to read and write FRL Data Flow Metering
registers.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
> index fe1df69a10968..8062baed63db8 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c
[ ... ]
> @@ -719,3 +724,40 @@ bool intel_hdmi_frl_dfm_dsc_requirement_met(struct intel_hdmi_frl_dfm *frl_dfm)
[ ... ]
> +void intel_hdmi_frl_dfm_write(const struct intel_crtc_state *crtc_state)
> +{
[ ... ]
> +	reg = TRANS_HDMI_FRL_DFMTHRSH(display, cpu_trans);
> +	val = TB_MIN_THESHOLD(crtc_state->frl.tb_threshold_min);
> +	intel_de_rmw(display, reg, TB_MIN_THESHOLD_MASK, val);

[Severity: Low]
This isn't a bug, but there appears to be a typo in the macro names
TB_MIN_THESHOLD and TB_MIN_THESHOLD_MASK (missing the 'R' in THRESHOLD).

Would it be worth updating the spelling to maintain consistency with
adjacent macros and the struct field tb_threshold_min?

> +}
> +
> +void intel_hdmi_frl_dfm_read(struct intel_crtc_state *crtc_state)
> +{
[ ... ]
> +	val = intel_de_read(display, TRANS_HDMI_FRL_DFMTHRSH(display, cpu_trans));
> +	crtc_state->frl.tb_threshold_min =
> +		REG_FIELD_GET(TB_MIN_THESHOLD_MASK, val);

[Severity: Low]
This isn't a bug, but the same typo (THESHOLD instead of THRESHOLD) is also
present here.

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=32

Re: [PATCH v2 15/56] drm/i915/intel_hdmi: Add helper to disable FRL

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915: NULL pointer deref in intel_hdmi_frl_ltsl() on systems with broken VBT
- [Low] drm/i915: unused crtc_state parameter in intel_hdmi_frl_ltsl()
--

commit bf532cf416aeac573dbb2724089b2e009ada86f1
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/intel_hdmi: Add helper to disable FRL

This commit adds a function to reset the SCDC FRL configuration and
Transcoder FRL configuration registers.

> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -3824,3 +3824,31 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
>  
>  	return -EINVAL;
>  }
> +
> +static void intel_hdmi_frl_ltsl(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state)

[Severity: Low]
Is the crtc_state parameter needed here? Looking at the function body, it
appears to be passed in but never referenced. Removing it might help clean
up the function signature.

> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct i2c_adapter *adapter =
> +		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
> +
> +	drm_scdc_disable_frl(adapter);

[Severity: High]
Could this lead to a NULL pointer dereference on systems with a misconfigured
VBT?

If a system has a missing or conflicting DDC pin, intel_hdmi_ddc_pin() can
return 0. Consequently, intel_hdmi_init_connector() fails and no HDMI
connector is registered.

However, if the BIOS left the port enabled in HDMI FRL mode, the driver's
hardware state readout (intel_hdmi_frl_get_config()) will still set
crtc_state->frl.enable = true because it unconditionally trusts the hardware
register state.

When intel_sanitize_encoder() later cleans up this connector-less encoder,
it calls the newly added intel_hdmi_disable_frl(). Since frl.enable is true,
this invokes intel_hdmi_frl_ltsl(), which fetches the adapter for pin 0
(GMBUS_PIN_DISABLED), receiving a NULL pointer.

Passing this NULL adapter to drm_scdc_disable_frl() will then cause a crash
when it is subsequently dereferenced in i2c_transfer(). Should there be a
NULL check for the adapter before calling drm_scdc_disable_frl()?

> +	drm_scdc_clear_update_flags(adapter, SCDC_FLT_UPDATE);
> +}
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=15

Re: [PATCH v2 16/56] drm/i915/hdmi: Reduce FRL rate cap on rate change during training

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915/hdmi: FRL training infinite retry loop on rate change at 9 Gbps
- [High] drm/i915/hdmi: Sleeping function read_poll_timeout called in atomic encoder enable callback
--

commit 3ebcdfcc6e404185a2b52af7506a3997a1901b79
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Reduce FRL rate cap on rate change during training

If the sink requests a rate change during FRL Link training, reduce
frl.rate_cap to the next lower FRL rate. The next mode compute then
uses this lower rate cap, so we do not attempt the failing rate again.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index fa4e5f0f567b0..11b4554e87bd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -3779,6 +3791,7 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
>  	int req_rate = crtc_state->frl.required_lanes * crtc_state->frl.required_rate;
>  	int ffe_level = get_ffe_level(req_rate);
>  	enum frl_lt_status status;
> +	int next_rate = -EINVAL;
>  
>  	if (!crtc_state->frl.enable)
>  		return 0;

[Severity: High]
Does this code call sleeping functions from an atomic context?

The DRM subsystem guide explicitly defines encoder atomic enable/disable
callbacks as executing in an atomic context where sleeping is forbidden. This
patch modifies intel_hdmi_start_frl() which is wired into the atomic encoder
enable callback path later in this patch series.

intel_hdmi_start_frl() relies on frl_train_complete_ltsp() and
intel_hdmi_frl_train_lts3() which both use the read_poll_timeout() macro
with a sleep_us parameter of 1000:

frl_train_complete_ltsp():
	ret = read_poll_timeout(get_frl_update_flags, update_flags,
				update_flags < 0 ||
				(update_flags & (SCDC_FRL_START | SCDC_FLT_UPDATE)),
				1000, FLT_UPDATE_TIMEOUT_MS * USEC_PER_MSEC,
				false, encoder);

intel_hdmi_frl_train_lts3():
	read_poll_timeout(intel_hdmi_train_lanes, status,
			  done,
			  1000, FLT_TIMEOUT_MS * USEC_PER_MSEC,
			  false, encoder, crtc_state, ffe_level);

Providing a non-zero sleep parameter causes the macro to use usleep_range()
internally, which sleeps. Executing usleep_range() in this atomic context
violates subsystem guidelines and causes kernel warnings and potential
deadlocks.

[ ... ]
> @@ -3812,10 +3825,22 @@ int intel_hdmi_start_frl(struct intel_encoder *encoder,
>  			    connector->base.id, connector->name,
>  			    intel_hdmi->frl.rate_gbps);
>  		return 0;
> -	default:
> +	case FRL_TRAIN_STOP:
> +		next_rate = 0;
> +		break;
> +	case FRL_CHANGE_RATE:
> +		next_rate = get_next_frl_rate(req_rate);
>  		break;
> +	case FRL_TRAIN_RETRAIN:
> +		fallthrough;
> +	default:
> +		goto ltsl_tmds_mode;
>  	}
>  
> +	if (next_rate >= 0)
> +		intel_hdmi->frl.rate_cap = next_rate;

[Severity: High]
Can this result in an infinite retry loop when the rate change happens at
9 Gbps?

If the current rate is already the minimum valid FRL rate (9 Gbps),
get_next_frl_rate(9) returns -EINVAL. In intel_hdmi_start_frl(), next_rate
becomes -EINVAL (< 0), causing the code to skip updating
intel_hdmi->frl.rate_cap, leaving it at 9 Gbps.

Because the rate cap was not lowered to 0 (which is required to disable FRL
and force a TMDS fallback, as correctly handled for FRL_TRAIN_STOP), the next
mode compute will see the exact same 9 Gbps rate cap and attempt FRL
training at 9 Gbps again, leading to an infinite retry loop.

> +
> +ltsl_tmds_mode:
>  	if (crtc_state->frl.enable && !intel_hdmi->frl.trained)
>  		drm_err(display->drm,
>  			"[CONNECTOR:%d:%s] FRL Training Failed with rate=%d\n",

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=16

Re: [PATCH v2 29/56] drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] drm/i915: unsigned underflow defeats max() zero-clamping in FRL payload logic
- [High] drm/i915: unsigned underflow in margin calculation bypasses FRL capacity validation
- [High] drm/i915: 32-bit integer overflow artificially truncates required audio packet count
- [Medium] drm/i915/hdmi_frl: 32-bit integer overflows in DFM timing calculations
--

commit 6d21cc13348026a7ea42c4821a0b77f14d185b3e
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers

This commit adds helper functions to the i915 DRM driver for computing
non-DSC FRL link characteristics. It includes computations for DFM
constraints, link overheads, audio hblank requirements, and capacity
verifications.

[Severity: High]
In drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c, within the
get_num_char_rc_compressible() function, the calculation for cfrl_free is:

    cfrl_free = max(((hblank * kcdx100) / (100 * k420) - 32 * 
                     audio_packets_line - 7), U32_MIN);

Since these variables are unsigned 32-bit integers, does this subtraction
underflow when the required audio blanking space exceeds the available
hardware hblank? If an underflow occurs, the value wraps to a huge positive
number. Because the comparison is unsigned, the max() macro would simply
return this huge positive value rather than clamping it to zero.

This huge value then propagates into get_num_char_compression_savings():

    u32 cfrl_savings = max(((7 * cfrl_free) / 8) - cfrl_margin, U32_MIN);

Could this corrupt the downstream link utilization checks and cause the
driver to incorrectly validate video modes that lack sufficient blanking
intervals?

[Severity: High]
In the verify_utilization_possible() function, the link capacity margin is
calculated as:

    margin = 1000 - (utilization + frl_dfm->params.overhead_max);

    if (margin > 0)
        return true;

If an over-utilized video mode requires more than 100 percent capacity
(where utilization + overhead_max > 1000), does the unsigned subtraction
underflow to a large positive value? This would cause the subsequent margin
greater than 0 check to evaluate to true, which might lead the driver to
validate modes that actually exceed the maximum FRL hardware bandwidth.

[Severity: High]
In the compute_audio_hblank_min() function, the required audio packets are
calculated using standard 32-bit multiplication:

    frl_dfm->params.num_audio_pkts_line =
        DIV_ROUND_UP(audio_pkt_rate * frl_dfm->params.line_time_ns,
                     FRL_TIMING_NS_MULTIPLIER);

For standard low-refresh display timings transmitting high sample-rate
audio (for instance, 192kHz multi-channel where audio_pkt_rate reaches
around 195,195, and a 1080p24 line time of around 37,037ns), the product
exceeds 7.2 billion. Does this overflow the U32_MAX limit of 4.29 billion,
causing silent integer truncation before the division?

Should this use mul_u32_u32() and DIV_ROUND_UP_ULL() to avoid calculating
artificially small audio packet requirements?

[Severity: Medium]
In the verify_frl_capacity_requirement() function, timing requirements are
calculated with direct 32-bit multiplication:

    tactive_ref_ns = (line_time_ns * hactive) / (hblank + hactive);
    tblank_ref_ns = (line_time_ns * hblank) / (hblank + hactive);

Although the commit message mentions using 64-bit math for DFM timing
products to avoid u32 overflow, these lines still appear to use 32-bit
arithmetic. If a user-space client requests a mode with a very low pixel
clock (where line_time_ns is large) and a large horizontal resolution, can
line_time_ns * hactive overflow a 32-bit integer?

If this wraps, it might trick the capacity check into returning true and
bypassing mode rejection for invalid display modes. Does this require a
transition to 64-bit arithmetic to safely handle edge-case timing values?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=29

Re: [PATCH v2 17/56] drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] drm/i915/ddi: flawed TMDS/FRL identification via port_clock in intel_ddi_level
- [Medium] drm/i915: intel_ddi_level misidentifies 300/600MHz TMDS modes as FRL
--

commit 0e9b38d21314c92fdb8c138db211c81ea24f573c
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE

This commit introduces a per-lane TxFFE level tracking for HDMI FRL and
exposes intel_hdmi_frl_level() to retrieve the buffer translation index.
It modifies intel_ddi_level() to use this new function for FRL modes
while preserving the existing behavior for TMDS.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 1e08ffe19447f..53e889c0d0223 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
[ ... ]
> @@ -1518,11 +1518,15 @@ int intel_ddi_level(struct intel_encoder *encoder,
>  	if (drm_WARN_ON_ONCE(display->drm, !trans))
>  		return 0;
>  
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		level = intel_ddi_hdmi_level(encoder, trans);
> -	else
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> +		if (intel_hdmi_is_frl(crtc_state->port_clock))
> +			level = intel_hdmi_frl_level(encoder, lane);

[Severity: Medium]
Does this incorrectly misidentify 300MHz and 600MHz TMDS modes as FRL modes?

Because intel_hdmi_is_frl() checks if the clock exactly matches one of the
FRL rates (e.g., 300000 kHz or 600000 kHz), it will return true if a custom
display mode has a TMDS character clock of exactly 300 MHz or 600 MHz. There
is no check in hdmi_port_tmds_clock_valid() preventing TMDS clocks from
exactly matching FRL rates.

If that happens, this branch will call intel_hdmi_frl_level() (returning
index 1) instead of the correct VBT-defined TMDS level via
intel_ddi_hdmi_level(). On older PHYs like C10 where FRL is unsupported,
returning index 1 applies a random DP preset with pre-emphasis instead of
the correct default HDMI level.

Could this check use the more reliable crtc_state->frl.enable flag instead?

A check forward through the series to commit ede50d511c51 confirms this logic
is not fixed.

> +		else
> +			level = intel_ddi_hdmi_level(encoder, trans);
> +	} else {
>  		level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
>  					   lane);
> +	}
>  
>  	if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))
>  		level = n_entries - 1;

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=17

Re: [PATCH v2 14/56] drm/i915/hdmi: Add functions for FRL training state machine

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] drm: missing read-modify-write in intel_hdmi_train_lanes overwrites hardware state
- [High] drm: usleep_range() called in atomic context via read_poll_timeout during FRL training
- [High] drm: lockless traversal of global encoder_list during FRL polling
- [High] drm/i915/hdmi: FRL link training pattern overwritten with 0 (NO_LTP) on FFE change
- [Low] drm: un-undef'd macro 'done' pollutes file scope in intel_hdmi.c
--

commit 786a188382d5678ef07d3ee398364ffb41065e98
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Add functions for FRL training state machine

This commit adds the FRL link training state machine and helpers to drive it
with an HDMI FRL sink over SCDC. It prepares for LTS:2, trains lanes in
LTS:3, completes training in LTS:P, and falls back to legacy TMDS in LTS:L.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 692480311c745..47d10ae0b07fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -3523,3 +3523,304 @@ void intel_hdmi_prepare_for_frl_mode(const struct intel_crtc_state *crtc_state)
>  
>  	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);
>  }
> +
> +static int is_flt_ready(struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct i2c_adapter *adapter =
> +		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));

[Severity: High]
Does this code perform an unsafe lockless traversal of the global encoder
list?

The intel_hdmi_ddc_pin() function calls get_encoder_by_ddc_pin(), which
uses for_each_intel_encoder() to iterate over the global encoder list. This
is called repeatedly from the read_poll_timeout() loop in
intel_hdmi_frl_prepare_lts2().

Since this runs during the asynchronous atomic commit tail where the modeset
locks (like connection_mutex) are not held, could this list traversal race
against concurrent MST hotplugs adding or removing encoders? Resolving the
DDC pin adapter once before the polling loop might avoid both the locking
issue and the overhead of an O(N) traversal inside a high-frequency polling
loop.

[ ... ]
> +static bool
> +intel_hdmi_frl_prepare_lts2(struct intel_encoder *encoder,
> +			    int frl_rate, int frl_lanes,
> +			    int ffe_level)
> +{
> +#define TIMEOUT_FLT_READY_MS 250
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct i2c_adapter *adapter =
> +		intel_gmbus_get_adapter(display, intel_hdmi_ddc_pin(encoder));
> +	int flt_ready;
> +	int ret;
> +
> +	if (!frl_rate || !frl_lanes)
> +		return false;
> +
> +	ret = read_poll_timeout(is_flt_ready, flt_ready,
> +				flt_ready, 1000,
> +				TIMEOUT_FLT_READY_MS * USEC_PER_MSEC,
> +				false, encoder);

[Severity: High]
Could this polling loop cause system instability by sleeping in atomic
context?

The read_poll_timeout() macro expands to a loop invoking usleep_range()
because a non-zero sleep duration (1000) is passed. Because
intel_hdmi_start_frl() is called within the encoder atomic enable or
pre_enable path, sleeping is strictly forbidden. Should this use a
non-sleeping delay such as read_poll_timeout_atomic() with udelay instead?

[ ... ]
> +static enum frl_lt_status
> +intel_hdmi_train_lanes(struct intel_encoder *encoder,
> +		       const struct intel_crtc_state *crtc_state,
> +		       int ffe_level)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum transcoder trans = crtc_state->cpu_transcoder;
> +	int num_lanes = crtc_state->frl.required_lanes;
> +	enum drm_scdc_frl_ltp ltp[4];
> +	u32 write_buf = 0;
> +	int update_flags;
> +	int lane;
[ ... ]
> +	for (lane = 0; lane < num_lanes; lane++) {
> +		if (ltp[lane] == SCDC_FRL_LTP3)
> +			continue;
> +
> +		if (ltp[lane] >= SCDC_FRL_LTP1 && ltp[lane] <= SCDC_FRL_LTP8)
> +			write_buf |= TRANS_HDMI_FRL_LTP(ltp[lane], lane);
> +
> +		/* #TODO handle FFE change */
> +		else if (ltp[lane] == SCDC_FRL_CHNG_FFE)
> +			continue;
> +	}
> +
> +	intel_de_write(display, TRANS_HDMI_FRL_TRAIN(display, trans), write_buf);

[Severity: High]
Will this direct overwrite unintentionally clear the link training pattern for
lanes undergoing an FFE change?

Because write_buf is initialized to 0, if any lane requires an FFE change
(SCDC_FRL_CHNG_FFE) or LTP3, the loop continues without setting bits for
that lane. Using intel_de_write() will then directly overwrite the entire
multi-field TRANS_HDMI_FRL_TRAIN register, forcing 0 (SCDC_FRL_NO_LTP) into
those skipped lanes.

The HDMI specification requires the source to preserve the current link
training pattern while adjusting FFE levels. Does this need a
read-modify-write sequence to ensure the hardware state of untouched lanes
is properly preserved?

[ ... ]
> +static enum frl_lt_status
> +intel_hdmi_frl_train_lts3(struct intel_encoder *encoder,
> +			  const struct intel_crtc_state *crtc_state,
> +			  int ffe_level)
> +{
> +#define FLT_TIMEOUT_MS 200
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum frl_lt_status status;
> +	enum transcoder trans = crtc_state->cpu_transcoder;
> +	u32 buf;
> +
> +	buf = intel_de_read(display, TRANS_HDMI_FRL_CFG(display, trans));
> +	intel_de_write(display, TRANS_HDMI_FRL_CFG(display, trans),
> +		       buf | TRANS_HDMI_FRL_ENABLE);
> +
> +#define done (status != FRL_TRAIN_CONTINUE)
> +	status = FRL_TRAIN_CONTINUE;
> +	read_poll_timeout(intel_hdmi_train_lanes, status,
> +			  done,
> +			  1000, FLT_TIMEOUT_MS * USEC_PER_MSEC,
> +			  false, encoder, crtc_state, ffe_level);

[Severity: Low]
This isn't a severe bug, but does the done macro need to be undefined?

Because C macros do not have block scope, defining done here without a
corresponding #undef pollutes the file scope of intel_hdmi.c. This might
cause confusing compilation errors if subsequent code uses the common word
done as a variable or struct member.

[Severity: High]
As noted above with intel_hdmi_frl_prepare_lts2(), this read_poll_timeout()
call also passes a 1000 microsecond sleep duration. This will invoke
usleep_range() while inside an atomic encoder callback. Does this need to be
changed to a non-sleeping polling function to avoid scheduling while atomic?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=14

Re: [PATCH v2 39/56] drm/i915/hdmi: Add support for sending uevent to user for FRL training failure

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915: missing drm_connector_put() in FRL modeset retry work causes refcount leak or UAF
- [High] drm/i915: refcount underflow and UAF in HDMI FRL modeset retry work
--

commit a06323f8771fc01d3d18f7c00ae7725f251aafec
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Add support for sending uevent to user for FRL training failure

This commit adds an HDMI-specific work function for handling modeset retries
on link training failure. It also overrides the default connector work item
to use this new function when FRL is supported.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 0391597c9847f..69612ebe80f04 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3397,6 +3399,31 @@ void intel_infoframe_init(struct intel_digital_port *dig_port)
>  	}
>  }
>  
> +/* Common code with DP, need to put in a common place */
> +static void intel_hdmi_modeset_retry_work_fn(struct work_struct *work)
> +{
> +	struct intel_connector *intel_connector;
> +	struct drm_connector *connector;
> +
> +	intel_connector = container_of(work, typeof(*intel_connector),
> +				       modeset_retry_work);
> +	connector = &intel_connector->base;
> +	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
> +		      connector->name);
> +
> +	/* Grab the locks before changing connector property*/
> +	mutex_lock(&connector->dev->mode_config.mutex);
> +	/*
> +	 * Set connector link status to BAD and send a Uevent to notify
> +	 * userspace to do a modeset.
> +	 */
> +	drm_connector_set_link_status_property(connector,
> +					       DRM_MODE_LINK_STATUS_BAD);
> +	mutex_unlock(&connector->dev->mode_config.mutex);
> +	/* Send Hotplug uevent so userspace can reprobe */
> +	drm_kms_helper_hotplug_event(connector->dev);
> +}

[Severity: High]
Does this function leak a connector reference, or leave the connector open to
a use-after-free?

The generic intel_connector_modeset_retry_work_fn expects a connector
reference to be taken before queueing, and balances it by calling
drm_connector_put() at the end of the work function.

This HDMI-specific function appears functionally identical to the generic
counterpart but omits the drm_connector_put() call.

If the work is queued via intel_connector_queue_modeset_retry_work(), which
acquires a reference, the missing put causes a permanent memory leak.

If the work is instead queued directly via schedule_work() without taking
a reference, no reference is held while the work executes. This allows a
concurrent teardown to free the connector out from under the running work
item.

[ ... ]

> @@ -3470,6 +3497,11 @@ bool intel_hdmi_init_connector(struct intel_digital_port *dig_port,
>  	if (!intel_hdmi->cec_notifier)
>  		drm_dbg_kms(display->drm, "CEC notifier get failed\n");
>  
> +	/* Initialize the work for modeset in case of link train failure */
> +	if (HAS_HDMI_FRL(display))
> +		INIT_WORK(&intel_connector->modeset_retry_work,
> +			  intel_hdmi_modeset_retry_work_fn);
> +

[Severity: High]
Does overriding the modeset_retry_work function here break the lifecycle
contract for the workqueue?

intel_connector_alloc() initializes modeset_retry_work with the generic
intel_connector_modeset_retry_work_fn, which manages connector refcounts.

If this work is queued directly using schedule_work() without acquiring a
connector reference first, and then cancelled during teardown via
intel_connector_cancel_modeset_retry_work() (called from
intel_hpd_poll_fini()), it will unconditionally call drm_connector_put()
upon successful cancellation.

Since no reference was acquired before scheduling the work, this cancellation
drops a reference that was never acquired, causing a refcount underflow and
premature freeing of the connector.

>  	return true;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=39

Re: [PATCH v2 36/56] drm/i915/hdmi: Validate FRL modes in mode_valid using the FRL DFM

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: FRL mode valid misses 3D frame packing clock doubling
--

commit 357e437906e7e9f540a08210f7b85cf2f3e109aa
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
drm/i915/hdmi: Validate FRL modes in mode_valid using the FRL DFM

This commit adds a fallback FRL capability check to
intel_hdmi_mode_valid_format() using the non-DSC FRL DFM parameters to
validate modes that exceed TMDS limits. It also introduces
intel_hdmi_can_support_frl() as a placeholder returning false until FRL
support is completed.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 67228b538e81a..b82c636b46f93 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -2021,6 +2022,51 @@ intel_hdmi_tmds_mode_clock_valid(struct drm_connector *_connector, int clock,
>  	return status;
>  }
>  
[ ... ]
> +static enum drm_mode_status
> +intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
> +				const struct drm_display_mode *mode,
> +				enum intel_output_format output_format)
> +{
> +	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
> +	struct intel_hdmi_frl_dfm frl_dfm = {};
> +	int max_rate = hdmi->max_frl_rate;
> +	int lanes = max_rate < 24 ? 3 : 4;
> +
> +	frl_dfm.config.pixel_clock_nominal_khz = mode->clock;

[Severity: High]
Does this code miss the 3D frame packing clock doubling?

In intel_hdmi_mode_valid(), the clock variable is doubled for 3D Frame
Packing modes:

	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
		clock *= 2;

This adjusted clock is passed to intel_hdmi_mode_valid_format() and used by
the TMDS validation path.

However, intel_hdmi_frl_mode_clock_valid() directly reads mode->clock, which
means it uses the unadjusted clock.

Could this cause the FRL Data Flow Management (DFM) capacity check to
underestimate the required bandwidth by a factor of 2 for 3D Frame Packing
modes, erroneously accepting modes that exceed the physical capacity of the
FRL link?

> +	frl_dfm.config.hactive = mode->hdisplay;
> +	frl_dfm.config.hblank = mode->htotal - mode->hdisplay;
> +
[ ... ]
> @@ -2052,6 +2105,7 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
>  			     enum intel_output_format sink_format)
>  {
>  	struct intel_display *display = to_intel_display(connector);
> +	struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
>  	enum drm_mode_status status;
>  
>  	status = intel_hdmi_sink_format_valid(connector, mode,
> @@ -2063,7 +2117,12 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
>  	if (status != MODE_OK)
>  		return status;
>  
> -	return intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
> +	status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
> +
> +	if (status != MODE_OK && intel_hdmi_can_support_frl(hdmi))
> +		status = intel_hdmi_frl_mode_clock_valid(connector, mode, sink_format);

[Severity: High]
Since intel_hdmi_frl_mode_clock_valid() is called without the adjusted clock
parameter, it will use the unadjusted mode->clock.

Should we pass the adjusted clock variable to
intel_hdmi_frl_mode_clock_valid() similar to how it is passed to
intel_hdmi_tmds_mode_clock_valid()?

> +
> +	return status;
>  }
>  
>  static enum drm_mode_status

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=36

Re: [PATCH v2 53/56] drm/i915/joiner: Move joiner pipe mask helper to intel_joiner.c

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] refactor: duplicate intel_joiner_valid_primary_pipe_mask() declaration
--

commit 8219a04938cb40be1f657190cac49de622685e24
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/joiner: Move joiner pipe mask helper to intel_joiner.c

This commit moves the intel_joiner_valid_primary_pipe_mask() helper and
its dependencies from intel_display.c to intel_joiner.c to group joiner
functionality together. It also adds the function declaration to
intel_joiner.h.

> diff --git a/drivers/gpu/drm/i915/display/intel_joiner.h b/drivers/gpu/drm/i915/display/intel_joiner.h
> index 85e19ed1527f5..962b9724c1126 100644
> --- a/drivers/gpu/drm/i915/display/intel_joiner.h
> +++ b/drivers/gpu/drm/i915/display/intel_joiner.h
> @@ -22,4 +22,6 @@ bool intel_joiner_candidate_valid(struct intel_connector *connector,
>  	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
>  		for_each_if(intel_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
>  
> +u8 intel_joiner_valid_primary_pipe_mask(struct intel_display *display, int num_joined_pipes);
> +

[Severity: Low]
This isn't a bug, but should the existing declaration of
intel_joiner_valid_primary_pipe_mask() in intel_display.h also be removed?

When this function was moved to intel_joiner.c, a new declaration was added
here, but the original prototype was left behind in intel_display.h. This
creates a duplicate function prototype. Callers in intel_display.c might
continue to compile by implicitly relying on the stale declaration instead
of properly including intel_joiner.h.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=53

Re: [PATCH v2 42/56] drm/i915/hdmi: Add read out for FRL state

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915: unconditional extraction of FRL configuration fields causes state mismatches
--

commit 7fe3edceb823d24a4b2a0a493b7dfd96cc58cbdd
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Add read out for FRL state

Read out the FRL configuration and Data Flow Metering registers and fill the
FRL members in crtc_state. In subsequent changes these are added to the
state checker and compared bwteen two crtc_states in
intel_pipe_config_compare().

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 69612ebe80f04..c5f25d2d6331c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c

[ ... ]

> @@ -4160,3 +4160,38 @@ void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state)
>  
>  	intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);
>  }
> +
> +static void intel_hdmi_frl_cfg_read(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_trans = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	val = intel_de_read(display, TRANS_HDMI_FRL_CFG(display, cpu_trans));
> +
> +	if (val & TRANS_HDMI_FRL_ENABLE)
> +		crtc_state->frl.enable = true;
> +
> +	crtc_state->frl.rsrc_sched_en =
> +		REG_FIELD_GET(TRANS_HDMI_R_B_SCHED_ENABLE_MASK, val);
> +	crtc_state->frl.active_char_buf_threshold =
> +		REG_FIELD_GET(TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, val);

[Severity: Medium]
Will this unconditional extraction cause state mismatch warnings during
fastset?

When FRL is disabled, it typically only clears the TRANS_HDMI_FRL_ENABLE bit,
potentially leaving stale non-zero values in the other bitfields of this
register. Because these fields are extracted and stored in the hardware state
without being guarded by a check for TRANS_HDMI_FRL_ENABLE, the hardware state
will contain these stale values even for non-FRL (TMDS) modes.

If these fields are then compared in intel_pipe_config_compare(), it may
trigger a state mismatch because the computed software state has these fields
properly zeroed out for TMDS modes.

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=42

Re: [PATCH v2 38/56] drm/i915/hdmi: Add FRL clock computation based on DFM

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/hdmi: pipe_bpp corruption in intel_hdmi_compute_frl_clock restricts fallback
--

commit e2a7d5ac5410d9fb50137634f445228551f6d758
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: drm/i915/hdmi: Add FRL clock computation based on DFM

This commit computes the FRL port clock for a mode using the DFM helper.
It starts with the lowest FRL rate meeting the DFM requirements and checks
if FRL can support the mode.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 8e742165a50ad..0391597c9847f 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c

[ ... ]

> +static int
> +intel_hdmi_compute_frl_clock(struct intel_encoder *encoder,
> +			     struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
> +	int max_bpc = max(crtc_state->pipe_bpp / 3, 8);
> +	int port_clock;
> +	int bpc;
> +
> +	for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
> +		int ret;
> +
> +		if (!hdmi_bpc_possible(crtc_state, bpc))
> +			continue;
> +
> +		crtc_state->pipe_bpp = bpc * 3;
> +
> +		ret = intel_hdmi_compute_frl_config(encoder, crtc_state);
> +		if (ret)
> +			continue;
> +
> +		/* Port clock for FRL rates is bitrate in 10Kbps */
> +		port_clock = FRL_GBPS_TO_10KBPS(crtc_state->frl.required_rate);
> +
> +		if (hdmi_port_frl_clock_valid(hdmi, port_clock) == MODE_OK) {
> +			crtc_state->port_clock = port_clock;
> +			return 0;
> +		}
> +	}
> +
> +	return -EINVAL;

[Severity: Medium]
Does returning -EINVAL here leave crtc_state->pipe_bpp corrupted?

Because pipe_bpp is modified in-place within the loop, if all FRL
configurations fail, the function exits with pipe_bpp retaining the last
tested value (typically 24).

When this happens, the caller intel_hdmi_compute_formats() will reuse
the exact same crtc_state object for a YCbCr420 fallback attempt:

intel_hdmi_compute_formats() {
	ret = intel_hdmi_compute_output_format(..., INTEL_OUTPUT_FORMAT_RGB, ...);
	
	if (ret && drm_mode_is_420_also(...))
		ret = intel_hdmi_compute_output_format(..., INTEL_OUTPUT_FORMAT_YCBCR420, ...);
}

Since max_bpc is derived from crtc_state->pipe_bpp, the fallback is then
artificially restricted to only testing 8 bpc, missing valid 10/12 bpc
capabilities.

Should pipe_bpp be saved before the loop and restored to its original value 
before returning -EINVAL?

> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=38

Re: [PATCH v2 47/56] drm/i915/hdmi: Compute output format for HDMI FRL mode

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] drm/i915/hdmi: out-of-spec TMDS fallback takes precedence over valid FRL modes
- [High] drm/i915/hdmi: FRL bypassed for modes exceeding sink TMDS limits
- [Medium] drm/i915/hdmi: FRL clock computation corrupts crtc_state->pipe_bpp on failure
- [Low] drm/i915: unconditional FRL enablement logging on error path
--

commit 53b28248132a15ea6972675cb5d3f48a3d13e3b3
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Compute output format for HDMI FRL mode

If the source and sink support FRL, then compute output format
that can support HDMI FRL mode.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c

[ ... ]

> @@ -2648,13 +2672,23 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
>  	if (!intel_link_bw_compute_pipe_bpp(pipe_config))
>  		return -EINVAL;
>  
> -	/*
> -	 * Try to respect downstream TMDS clock limits first, if
> -	 * that fails assume the user might know something we don't.
> -	 */
> -	ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, true);
> -	if (ret)
> -		ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, false);
> +	if (HAS_HDMI_FRL(display) &&
> +	    intel_bios_hdmi_max_frl_rate(encoder->devdata) &&
> +	    intel_hdmi->has_sink_hdmi_21)
> +		enable_frl = true;
> +
> +	ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, false);
> +
> +	if (ret && enable_frl) {

[Severity: High]
Does this sequence bypass FRL completely for displays with low TMDS limits?

When connecting an HDMI 2.1 sink that supports FRL but has a lower max
TMDS clock than the mode requires, the call to intel_hdmi_compute_formats
with enable_frl=false will first fail the strict limit check, but then
internally fall back to ignoring downstream limits:

intel_hdmi_compute_formats() {
    ...
    ret = _intel_hdmi_compute_formats(..., true, enable_frl);
    if (ret)
        ret = _intel_hdmi_compute_formats(..., false, enable_frl);
    ...
}

If the mode's clock is within the source's max TMDS capability, this
fallback succeeds and returns 0, masking the downstream limit failure.
Because ret evaluates to 0, this FRL configuration block is skipped,
and the driver outputs an out-of-spec TMDS signal instead of attempting
FRL.

Additionally, in intel_hdmi_compute_frl_config, there is a strict
check against max_rate:

intel_hdmi_compute_frl_config() {
    ...
    for (i = 0; i < ARRAY_SIZE(rate); i++) {
        if (rate[i] > max_rate)
            continue;
    ...
}

This means the fallback mechanism to ignore downstream limits doesn't
actually allow users to override FRL bandwidth limits either. Could we
attempt FRL before falling back to out-of-spec TMDS formats?

> +		ret = intel_hdmi_compute_formats(encoder, pipe_config, conn_state, true);

[Severity: Medium]
Can intel_hdmi_compute_formats corrupt crtc_state->pipe_bpp if the FRL
computation fails?

When FRL computation is attempted, it calls down to
intel_hdmi_compute_frl_clock which iterates over bpc:

intel_hdmi_compute_frl_clock() {
    ...
    for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
        ...
        crtc_state->pipe_bpp = bpc * 3;

        ret = intel_hdmi_compute_frl_config(encoder, crtc_state);
        if (ret)
            continue;
    ...
}

If the FRL computation fails across all iterations, crtc_state->pipe_bpp
remains permanently lowered (e.g., to 24). When
_intel_hdmi_compute_formats subsequently falls back to trying the YCBCR420
format, it reads this corrupted pipe_bpp to determine its starting max_bpc.
This artificially restricts the fallback to 8 BPC, skipping 10 and 12 BPC
which require less bandwidth under YCBCR420 and might have otherwise
succeeded.

> +		drm_dbg_kms(display->drm,
> +			    "Enabling FRL mode with lanes = %d rate = %d\n",
> +			    pipe_config->frl.required_lanes,
> +			    pipe_config->frl.required_rate);
> +		pipe_config->frl.enable = true;
> +		lane_count = pipe_config->frl.required_lanes;
> +	}

[Severity: Low]
Is it intentional that this block executes unconditionally, even if
intel_hdmi_compute_formats fails?

If the intel_hdmi_compute_formats call above returns a non-zero error
code, the code still executes this drm_dbg_kms claiming FRL is being
enabled with uninitialized or stale lane/rate values, and mutates
pipe_config->frl.enable. While the atomic check will subsequently reject
the mode and discard the state, the debug trace will misleadingly indicate
FRL mode was successfully computed before the mode rejection.

> +
>  	if (ret) {
>  		drm_dbg_kms(display->drm,
>  			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
> @@ -2677,7 +2711,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder,
>  		adjusted_mode->picture_aspect_ratio =
>  			conn_state->picture_aspect_ratio;
>  
> -	pipe_config->lane_count = 4;
> +	pipe_config->lane_count = lane_count;
>  
>  	if (scdc->scrambling.supported && source_supports_scrambling(encoder) &&
>  	    !pipe_config->frl.enable) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=47

Re: [PATCH v2 55/56] drm/i915/hdmi: Iterate through joiner candidates in mode_valid path

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/hdmi: TMDS modes bypass max dotclock and plane size checks
--

commit fcc107a6617c907f4675cb58944ba1cef59c27ff
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
drm/i915/hdmi: Iterate through joiner candidates in mode_valid path

This commit updates the HDMI mode validation path to iterate through joiner
candidates, relaxing the dotclock ceiling when multiple pipes are joined.
The single-pipe validation checks were relocated from the main mode validation
function into the format-specific validation function.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 2ec7d2a5e7d4d..2c7c47a3c61d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2132,20 +2132,55 @@ intel_hdmi_mode_valid_format(struct intel_connector *connector,
[ ... ]
> +	status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock,
> +						  has_hdmi_sink, sink_format);
> +
> +	if (status == MODE_OK)
> +		return status;

[Severity: High]
Does this early return cause TMDS modes to bypass the max dotclock and plane
size limits? 

It looks like if a mode fits within the TMDS link bandwidth, the function
returns immediately, skipping the newly relocated intel_pfit_mode_valid(),
intel_mode_valid_max_plane_size(), and intel_dp_dotclk_valid() checks inside
the for_each_joiner_candidate() loop below.

[ ... ]
> @@ -2160,7 +2195,6 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
[ ... ]
>  	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
>  		clock *= 2;
>  
> -	if (clock > max_dotclk)
> -		return MODE_CLOCK_HIGH;
> -

[Severity: High]
Since this overarching max_dotclk check was removed from the parent function
intel_hdmi_mode_valid(), and TMDS modes now return early in 
intel_hdmi_mode_valid_format() before reaching the new validation loop, could
this allow user-provided TMDS modes that exceed the display engine's max CDCLK
dotclock to pass validation?

[ ... ]
> @@ -2197,10 +2228,8 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
>  			status = intel_hdmi_mode_valid_format(connector, mode, clock, has_hdmi_sink,
>  							      INTEL_OUTPUT_FORMAT_YCBCR420);
>  	}
> -	if (status != MODE_OK)
> -		return status;
>  
> -	return intel_mode_valid_max_plane_size(display, mode, 1);
> +	return status;

[Severity: High]
Similarly, since intel_mode_valid_max_plane_size() is also removed here,
it seems TMDS modes might bypass plane width and panel fitter checks too,
potentially leading to atomic commit failures or hardware pipeline errors.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=55

Re: [PATCH v2 40/56] drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] drm/i915/hdmi: connector refcount underflow via modeset_retry_work
- [Medium] drm/i915/hdmi: intel_hdmi_frl_cfg_write corrupts register by omitting clear mask
- [Medium] drm/i915: unconditional FRL configuration and transcoder enablement contrary to commit message
--

commit cfc5e8ca998b654bfa60f35c76733a4d8332204f
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Subject: drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path

This commit enables HDMI FRL in the DDI enable and disable sequences for
MTL+. It prepares for FRL mode, starts FRL link training, and configures
the FRL registers if enabled. On disable, it handles LTS:L teardown and
register cleanup.

> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 53e889c0d0223..22a49eb50b203 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
[ ... ]
> @@ -3605,8 +3614,15 @@ static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
>  
>  	intel_ddi_buf_enable(encoder, buf_ctl);
>  
> -	if (DISPLAY_VER(display) >= 14)
> +	if (DISPLAY_VER(display) >= 14) {
> +		if (crtc_state->frl.enable &&
> +		    intel_hdmi_start_frl(encoder, crtc_state) < 0)
> +			schedule_work(&intel_connector->modeset_retry_work);

[Severity: High]
Does this code underflow the connector reference count?

If intel_hdmi_start_frl() fails, schedule_work() is called directly without
taking a reference via drm_connector_get(). If the driver suspends, unbinds,
or calls intel_hpd_cancel_work(), it calls
intel_connector_cancel_modeset_retry_work(). This generic cancel helper
invokes cancel_work_sync() and unconditionally calls drm_connector_put() if
the work was pending. Because the work was queued without taking a reference,
this drops an unowned reference.

> +
> +		intel_hdmi_frl_cfg_write(crtc_state);

[Severity: Medium]
Does intel_hdmi_frl_cfg_write() corrupt the register by omitting a clear mask?

When this function is called here, it performs a read-modify-write on the
TRANS_HDMI_FRL_CFG register:

intel_hdmi.c:intel_hdmi_frl_cfg_write() {
    ...
    val = TRANS_HDMI_R_B_SCHED_ENABLE(crtc_state->frl.rsrc_sched_en);
    val |= TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(crtc_state->frl.active_char_buf_threshold);
    val |= TRANS_HDMI_MIN_BLANK_CHAR(TRANS_HDMI_MIN_BLANK_CHAR_VAL);

    intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);
}

Because the clear mask is 0, intel_de_rmw() performs a read, leaves all
existing bits intact, and then bitwise ORs the new val. This could
permanently corrupt the hardware configuration if the previous register
value had bits set that should be zero in the new configuration.

[Severity: Medium]
Does this execute hardware configuration unconditionally despite failures?

The commit message explicitly states: "If FRL link training fails, notify
userspace. On success, write DFM registers and enable the transcoder."
However, the code unconditionally calls intel_hdmi_frl_cfg_write(),
intel_hdmi_frl_dfm_write(), and intel_ddi_enable_transcoder_and_vblank()
even if intel_hdmi_start_frl() returns an error. While this might be
architecturally consistent with how DisplayPort handles link training
failures, is there a discrepancy between the documented intent and the
actual implementation?

> +		intel_hdmi_frl_dfm_write(crtc_state);
>  		intel_ddi_enable_transcoder_and_vblank(state, encoder, crtc_state);
> +	}
>  
>  	intel_hdmi_poll_for_scrambling_enable(crtc_state, connector);
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=40

Re: [PATCH v2 46/56] drm/i915/display: Add FRL members to the state checker

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] drm/i915/display: Incomplete FRL state verification missing tb_threshold_min and required_rate
- [Medium] drm/i915: spurious WARN_ON in state checker due to uncleared FRL config bits
--

commit 5c7a8a2a5c09104f1fb54f2b4082592bd27316bb
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/display: Add FRL members to the state checker

This commit introduces hardware state verification for FRL (Fixed Rate Link)
by adding several FRL configuration members to the state checker.

> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5626,6 +5626,14 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  	PIPE_CONF_CHECK_I(set_context_latency);
>  
> +	PIPE_CONF_CHECK_BOOL(frl.enable);
> +	PIPE_CONF_CHECK_BOOL(frl.rsrc_sched_en);
> +	PIPE_CONF_CHECK_I(frl.required_lanes);
> +	PIPE_CONF_CHECK_I(frl.tb_actual);
> +	PIPE_CONF_CHECK_I(frl.active_char_buf_threshold);

[Severity: Medium]
Will checking frl.rsrc_sched_en and frl.active_char_buf_threshold trigger
spurious WARN_ON state mismatches due to uncleared hardware bits?

Looking at intel_hdmi_frl_cfg_write() in intel_hdmi.c, it appears to use
intel_de_rmw() with a clear mask of 0:

intel_hdmi.c:intel_hdmi_frl_cfg_write() {
    ...
    val = TRANS_HDMI_R_B_SCHED_ENABLE(crtc_state->frl.rsrc_sched_en);
    val |= TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(crtc_state->frl.active_char_buf_threshold);
    ...
    intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);
}

Since the clear mask is 0, preexisting bits from BIOS or prior configurations
will persist in the hardware register. Will the state checker trip over these
leftover bits when it compares them against the software state?

> +	PIPE_CONF_CHECK_I(frl.link_m);
> +	PIPE_CONF_CHECK_I(frl.link_n);

[Severity: Medium]
Should frl.tb_threshold_min and frl.required_rate also be verified here?

The driver actively populates tb_threshold_min from hardware during state
readout in intel_hdmi_frl_dfm_read():

intel_hdmi_frl_dfm.c:intel_hdmi_frl_dfm_read() {
    ...
    val = intel_de_read(display, TRANS_HDMI_FRL_DFMTHRSH(display, cpu_trans));
    crtc_state->frl.tb_threshold_min = REG_FIELD_GET(TB_MIN_THESHOLD_MASK, val);
    ...
}

Similarly, frl.required_rate is populated during hardware readout in
intel_hdmi_frl_get_config(). Without adding these fields to the state checker,
can hardware state corruption or mismatches for the minimum threshold and
required rate go undetected?

> +
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_LLI

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=46

Re: [PATCH v2 37/56] drm/i915/hdmi: Add FRL port clock valid

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/hdmi: FRL mode_valid rejects valid modes by checking max_rate instead of required rate
--

commit a29948ea9df1fcfe40f2c9e5a0c8d6354286b145
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi: Add FRL port clock valid

Introduce hdmi_port_frl_clock_valid() which validates the FRL link
rate against the maximum FRL rate and the source PHY (c10/c20 or LT).

Call this from the FRL mode_valid path.

Since PHY PLL table units are in 10 kbps, add a macro to convert FRL
rate per lane in Gbps to 10 kbps.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b82c636b46f93..8e742165a50ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -2046,6 +2061,7 @@ intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
>  	struct intel_hdmi_frl_dfm frl_dfm = {};
>  	int max_rate = hdmi->max_frl_rate;
>  	int lanes = max_rate < 24 ? 3 : 4;
> +	int port_clock;
>  
>  	frl_dfm.config.pixel_clock_nominal_khz = mode->clock;
>  	frl_dfm.config.hactive = mode->hdisplay;
> @@ -2064,7 +2080,9 @@ intel_hdmi_frl_mode_clock_valid(struct intel_connector *connector,
>  	if (!intel_hdmi_frl_dfm_nondsc_requirement_met(&frl_dfm))
>  		return MODE_CLOCK_HIGH;
>  
> -	return MODE_OK;
> +	port_clock = FRL_GBPS_TO_10KBPS(max_rate / lanes);
> +
> +	return hdmi_port_frl_clock_valid(hdmi, port_clock);
>  }

[Severity: Medium]
Does this code reject valid modes by checking the absolute maximum FRL rate
rather than the rate required by the mode?

In intel_hdmi_frl_mode_clock_valid(), port_clock is computed from the absolute
maximum FRL rate (hdmi->max_frl_rate) allowed by the sink EDID and VBT. The
function then checks if the PHY supports this exact max_rate.

However, hdmi->max_frl_rate is never clamped to the PHY's actual capabilities
during initialization. If max_frl_rate exceeds the PHY's capabilities, or if
it evaluates to an invalid non-standard rate, hdmi_port_frl_clock_valid()
returns MODE_CLOCK_RANGE, rejecting all FRL modes.

For example, if an OEM limits the VBT to HDMI_MAX_FRL_RATE_3G,
max_src_frl_rate incorrectly evaluates to 12 Gbps (3 * 4). If the sink supports
>= 18 Gbps, max_frl_rate becomes 12. The port_clock is then computed as
12 / 3 = 4 Gbps (400000 10kbps). Because 400000 is not in the PHY tables, the
PHY check fails.

Does this break FRL entirely on that platform, rejecting even low-bandwidth
modes the PHY could support?

While compute_config iterates through supported rates in later patches,
mode_valid remains hardcoded to test max_rate through the end of the series.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=37

Re: [PATCH v2 50/56] drm/i915/hdmi: Enable FRL based mode clock valid

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/hdmi: 4K120 4:2:0 bypasses FRL and fails via TMDS
--

commit 4c023e7cde26d2644e793aa505b046a46b2d33ef
Author: Vandita Kulkarni <vandita.kulkarni@intel.com>

drm/i915/hdmi: Enable FRL based mode clock valid

Higher resolution modes like 8K@60, 4K@120 need FRL support. Platforms
before MTL do not support FRL, so allow modes requiring more than 600MHz
dotclock to be enumerated only on MTL+ where FRL is supported.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index c57d99195ed03..e3dbd71a3652e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c

[ ... ]

> @@ -2176,12 +2179,10 @@ intel_hdmi_mode_valid(struct drm_connector *_connector,
>  	}
>  
>  	/*
> -	 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
> -	 * enumerated only if FRL is supported. Current platforms do not support
> -	 * FRL so prune the higher resolution modes that require doctclock more
> -	 * than 600MHz.
> +	 * Platforms < MTL do not support FRL so prune the higher resolution
> +	 * modes that require doctclock more than 600MHz.
>  	 */
> -	if (clock > 600000)
> +	if (!intel_hdmi_can_support_frl(hdmi) && clock > 600000)
>  		return MODE_CLOCK_HIGH;

[Severity: High]
Does this allow high-bandwidth 4:2:0 modes to bypass FRL validation and
fail later during atomic commit?

By restricting the 600MHz dotclock limit to non-FRL platforms here,
dotclocks up to 1200MHz can reach format validation on FRL platforms.
However, when a mode like 4K@120Hz (1188MHz) in YCbCr 4:2:0 format reaches
intel_hdmi_mode_valid_format(), the TMDS clock check executes first:

intel_hdmi_mode_valid_format() {
    ...
    status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock,
                                              has_hdmi_sink, sink_format);

    if (status != MODE_OK && intel_hdmi_can_support_frl(hdmi))
        status = intel_hdmi_frl_mode_clock_valid(connector, mode,
                                                 sink_format);
    ...
}

For 4:2:0 formats, intel_hdmi_tmds_mode_clock_valid() halves the 1188MHz
dotclock to 594MHz, which successfully passes the TMDS limit check and
returns MODE_OK.

Since the status is MODE_OK, intel_hdmi_frl_mode_clock_valid() is
completely bypassed. The mode is incorrectly validated as TMDS instead of
FRL. Because TMDS configuration does not support pipe joiner, the single-pipe
dotclock limits will be exceeded during compute_config, causing the atomic
commit to fail for advertised modes.

>  
>  	if (drm_mode_is_420_only(info, mode)) {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=50

✗ CI.checkpatch: warning for Enable HDMI FRL for MTL+ (rev2)

[Patchwork]

== Series Details ==

Series: Enable HDMI FRL for MTL+ (rev2)
URL   : https://patchwork.freedesktop.org/series/171757/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
6bef5ce5c74dc76b4ee69ab2832c0d1fd63c91c7
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1e8db5a1ca680ddeb7382f067c49e50ee65cff4a
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Date:   Mon Oct 12 09:28:05 2026 +0530

    drm/i915/hdmi: Allow Pipe joiner for HDMI
    
    Pipe joiner is used only with FRL mode, so allow it only when the platform
    and the sink both support FRL.
    
    Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
+ /mt/dim checkpatch 0f28405022887336d4fc1fe1a0e1429146c2d431 drm-intel
ff78645a20a2 drm/i915/hdmi: Parse FRL max link rate from VBT
358750e518db drm/i915/hdmi: Add new data members for FRL configuration
6676d55f6bf1 drm/i915/hdmi: Add FRL link rate cap
0ccb693a6bf1 drm/drm_scdc_helper: Add SCDC helper funcs for FRL
16948ec0bca7 drm/i915/display: Add registers for HDMI FRL configuration
-:28: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:563:
+#define  TRANS_HDMI_R_B_SCHED_ENABLE(val)		REG_FIELD_PREP(TRANS_HDMI_R_B_SCHED_ENABLE_MASK, val)

-:30: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#30: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:565:
+#define  TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(val)		REG_FIELD_PREP(TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH_MASK, val)

-:32: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#32: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:567:
+#define  TRANS_HDMI_MIN_BLANK_CHAR(val)			REG_FIELD_PREP(TRANS_HDMI_MIN_BLANK_CHAR_MASK, val)

-:35: WARNING:LONG_LINE: line length of 112 exceeds 100 columns
#35: FILE: drivers/gpu/drm/i915/display/intel_display_regs.h:570:
+#define  TRANS_HDMI_FRL_PKT_PAYLOAD_MAX(val)		REG_FIELD_PREP(TRANS_HDMI_FRL_PKT_PAYLOAD_MAX_MASK, val)

total: 0 errors, 4 warnings, 0 checks, 32 lines checked
91c0c459a690 drm/i915/display: Add new members in crtc_state for FRL configuration
fd5908592a62 drm/i915/intel_cx0_phy_regs: Add HDMI FRL SHIFT EN bit in PORT_BUF_CTL_1
4af81f55c76e drm/i915/ddi: Update Transcoder/DDI registers with the frl bits
25101d4e57fa drm/i915/hdmi: Enable Scrambling only for TMDS mode
d125dffe95e9 drm/i915/ddi: Simplify intel_ddi_enable()
1fc37d0f8e28 drm/i915/ddi: Factor out common transcoder/vblank enable sequence
a1de60d8f0b5 drm/i915/ddi: Update HDMI modeset sequence for MTL+
54ee959c6cc3 drm/i915/hdmi: Add function to prepare registers for FRL mode
d4e8732bbd3d drm/i915/hdmi: Add functions for FRL training state machine
55e38ec9d191 drm/i915/intel_hdmi: Add helper to disable FRL
1e54ce562714 drm/i915/hdmi: Reduce FRL rate cap on rate change during training
650fe55c10a7 drm/i915/hdmi: Introduce intel_hdmi_frl_level() for per-lane TxFFE
b740290f2e7a drm/i915/hdmi: Drive per-lane TxFFE during FRL link training
364dce97db8d drm/i915/ltphy: Add PLL tables for HDMI FRL
8fa6652d1dcb drm/i915/ltphy: Add safegaurd when calculation HDMI FRL state
573e973fd390 drm/i915/ltphy: Calculate port clock for HDMI FRL
a7d5f1c8695f drm/i915/ltphy: Verify HDMI FRL tables
016b3aa9dfab drm/i915/ddi_buf: Add Vswing table for HDMI FRL
729a80635c21 drm/i915/hdmi: Add provision for FRL mode while computing output format
eb1ecc9829a2 drm/i915/cx0: Add helper to check if the FRL rate is valid
54ac347bf3a0 drm/i915/lt_phy: Add helper to check if the FRL rate is valid
bfc486aba88d drm/i915/hdmi_frl_dfm_regs: Define DFM registers
-:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#13: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 36 lines checked
24d08fbda098 drm/i915/hdmi_frl_dfm: Define frl_dfm structure
-:14: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#14: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 113 lines checked
6e49debf38bc drm/i915/hdmi_frl_dfm: Add non dsc frl capacity computation helpers
-:34: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

-:399: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#399: FILE: drivers/gpu/drm/i915/display/intel_hdmi_frl_dfm.c:361:
+			DIV_ROUND_UP_ULL(mul_u32_u32(tborrowed_ns, frl_dfm->params.ftb_avg_k) * 1000,

total: 0 errors, 2 warnings, 0 checks, 446 lines checked
10afc87b52ad drm/i915/hdmi_frl_dfm: Add support for DFM calculation with DSC
59c22f2365b7 drm/i915/hdmi: Add helper to write FRL CFG register
b94fbfb9ed23 drm/i915/hdmi_frl_dfm: Add helpers to read/write FRL DFM registers
f52b17990f4a drm/i915/hdmi: Rename port clock limit to specify tmds clock
c538705c186b drm/i915/hdmi: Rename port clock valid to specify tmds clock
4d19a5fef4a6 drm/i915/hdmi: Rename mode clock valid to specify tmds clock
-:36: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#36: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:2066:
+	return intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);

total: 0 errors, 1 warnings, 0 checks, 20 lines checked
414c3d62a587 drm/i915/hdmi: Validate FRL modes in mode_valid using the FRL DFM
-:109: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#109: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:2120:
+	status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);

total: 0 errors, 1 warnings, 0 checks, 91 lines checked
1772f3279b6d drm/i915/hdmi: Add FRL port clock valid
-:16: WARNING:BAD_SIGN_OFF: Duplicate signature
#16: 
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

-:17: WARNING:BAD_SIGN_OFF: Duplicate signature
#17: 
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

total: 0 errors, 2 warnings, 0 checks, 51 lines checked
82042d54836c drm/i915/hdmi: Add FRL clock computation based on DFM
7a81ad151b9e drm/i915/hdmi: Add support for sending uevent to user for FRL training failure
76901f6d2fc2 drm/i915/ddi: Wire FRL into the HDMI DDI enable/disable path
224b9e5d886a drm/i915/ltphy: Fix HDMI FRL per-lane TX mapping
ebc600fffd37 drm/i915/hdmi: Add read out for FRL state
884988221bd3 drm/i915/hdmi: Compute FRL Link M/N
ad5dc42a4020 drm/i915/hdmi_frl_dfm: Write and read back FRL Link M/N
b64c1a84b436 drm/i915/hdmi: Use the real pixel clock as crtc_clock for FRL
7973082039d2 drm/i915/display: Add FRL members to the state checker
6e75acf53411 drm/i915/hdmi: Compute output format for HDMI FRL mode
75f3a54085bf drm/i915/hdmi: Add a helper to check non DSC audio support for HDMI FRL
032791495e50 drm/i915/audio: Add the mode pruning logic for HDMI FRL
009b9e678be7 drm/i915/hdmi: Enable FRL based mode clock valid
a2906c5189e0 drm/i915/joiner: Prepare to move joiner helpers to a new file
-:125: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#125: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 125 lines checked
c246a9bac550 drm/i915/joiner: Move joiner candidate helpers to intel_joiner.c
-:187: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__num_joined_pipes' - possible side-effects?
#187: FILE: drivers/gpu/drm/i915/display/intel_joiner.h:21:
+#define for_each_joiner_candidate(__connector, __mode, __num_joined_pipes) \
+	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \
+		for_each_if(intel_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))

-:188: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#188: FILE: drivers/gpu/drm/i915/display/intel_joiner.h:22:
+	for ((__num_joined_pipes) = 1; (__num_joined_pipes) <= (I915_MAX_PIPES); (__num_joined_pipes)++) \

-:189: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#189: FILE: drivers/gpu/drm/i915/display/intel_joiner.h:23:
+		for_each_if(intel_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))

total: 0 errors, 2 warnings, 1 checks, 150 lines checked
94b57270b8af drm/i915/joiner: Move joiner pipe mask helper to intel_joiner.c
e16a18ff1586 drm/i915/hdmi: Iterate through joiner candidates in compute_config path
-:85: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#85: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:2527:
+		if (!(intel_joiner_valid_primary_pipe_mask(display, num_joined_pipes) & BIT(crtc->pipe)))

total: 0 errors, 1 warnings, 0 checks, 97 lines checked
76f7666565ef drm/i915/hdmi: Iterate through joiner candidates in mode_valid path
1e8db5a1ca68 drm/i915/hdmi: Allow Pipe joiner for HDMI

Re: [PATCH v2 56/56] drm/i915/hdmi: Allow Pipe joiner for HDMI

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915/hdmi: TMDS validation bypasses max plane size, breaking wide modes and FRL joiner fallback
- [High] drm/i915: NULL pointer deref in intel_hdmi_has_joiner for SDVO
--

commit ede50d511c51a1eac2ca7425fa38667d98b1e4a1
Author: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

drm/i915/hdmi: Allow Pipe joiner for HDMI

Pipe joiner is used only with FRL mode, so allow it only when the platform
and the sink both support FRL.

> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
[ ... ]
> @@ -4378,3 +4378,11 @@ void intel_hdmi_frl_get_config(struct intel_crtc_state *crtc_state)
>  
>  	intel_hdmi_frl_dfm_read(crtc_state);
>  }
> +
> +bool intel_hdmi_has_joiner(struct intel_hdmi *intel_hdmi)
> +{
> +	struct intel_display *display = to_intel_display(intel_hdmi);
> +	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
> +
> +	return HAS_HDMI_FRL(display) && intel_bios_hdmi_max_frl_rate(encoder->devdata);
> +}

[Severity: High]
Does the existing TMDS validation bypass the max plane size, breaking the wide
modes and the FRL joiner fallback that this patch relies on?

In intel_hdmi_mode_valid_format(), if the TMDS clock is valid, it returns
MODE_OK immediately:

        status = intel_hdmi_tmds_mode_clock_valid(&connector->base, clock,
                                                  has_hdmi_sink, sink_format);

        if (status == MODE_OK)
                return status;

This bypasses intel_mode_valid_max_plane_size(), meaning a mode with an
hdisplay greater than 5120 but a valid TMDS clock (like 7680x1080@60Hz) is
incorrectly advertised as valid to userspace.

Then during atomic commit in intel_hdmi_compute_config(), it tries TMDS first:

        ret = intel_hdmi_compute_formats(encoder, pipe_config,
                                         conn_state, false);

        if (ret && enable_frl) {
                ret = intel_hdmi_compute_formats(encoder, pipe_config,
                                                 conn_state, true);

Since TMDS only checks the clock and ignores the plane size, it succeeds and
skips the FRL fallback. Later, intel_plane_atomic_check() calling
skl_plane_check() rejects the un-split plane because the width exceeds the max
width of 5120, returning -EINVAL. This causes atomic commits to fail for
advertised modes and prevents the driver from falling back to FRL, where the
pipe joiner could have correctly handled the wide mode.

> diff --git a/drivers/gpu/drm/i915/display/intel_joiner.c b/drivers/gpu/drm/i915/display/intel_joiner.c
> --- a/drivers/gpu/drm/i915/display/intel_joiner.c
> +++ b/drivers/gpu/drm/i915/display/intel_joiner.c
[ ... ]
> @@ -33,6 +34,9 @@ bool intel_joiner_connector_can_join(struct intel_connector *connector)
>  	case DRM_MODE_CONNECTOR_DisplayPort:
>  	case DRM_MODE_CONNECTOR_eDP:
>  		return intel_dp_has_joiner(intel_attached_dp(connector));
> +	case DRM_MODE_CONNECTOR_HDMIA:
> +	case DRM_MODE_CONNECTOR_HDMIB:
> +		return intel_hdmi_has_joiner(intel_attached_hdmi(connector));

[Severity: High]
Does this code handle SDVO HDMI connectors correctly? When this is called for
SDVO HDMI connectors on older platforms, the connector type is initialized to
DRM_MODE_CONNECTOR_HDMIA. However, SDVO HDMI connectors are not backed by an
intel_digital_port.

When intel_attached_hdmi() is called for an SDVO connector, it calls
enc_to_dig_port(), which evaluates to NULL because the encoder type is
INTEL_OUTPUT_SDVO. Then enc_to_intel_hdmi() takes the address of &NULL->hdmi,
resulting in an invalid pointer offset.

When this invalid pointer is passed to intel_hdmi_has_joiner(), the
to_intel_display() macro calls hdmi_to_dig_port(). This reverses the offset
back to NULL and dereferences it to find the device pointer, causing an
unconditional kernel panic during boot.

>  	default:
>  		return false;
>  	}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=56

✓ CI.KUnit: success for Enable HDMI FRL for MTL+ (rev2)

[Patchwork]

== Series Details ==

Series: Enable HDMI FRL for MTL+ (rev2)
URL   : https://patchwork.freedesktop.org/series/171757/
State : success

== Summary ==

+ trap cleanup EXIT
+ kunitconfigs=('/kernel/drivers/gpu/tests/.kunitconfig' '/kernel/drivers/gpu/drm/xe/.kunitconfig' '/kernel/drivers/gpu/drm/tests/.kunitconfig' '/kernel/drivers/gpu/drm/ttm/tests/.kunitconfig' '/kernel/drivers/dma-buf/.kunitconfig')
+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/tests/.kunitconfig
[04:59:51] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[04:59:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:00:16] Starting KUnit Kernel (1/1)...
[05:00:16] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:00:16] ================= gpu_buddy (14 subtests) ==================
[05:00:16] [PASSED] gpu_test_buddy_alloc_limit
[05:00:16] [PASSED] gpu_test_buddy_alloc_optimistic
[05:00:16] [PASSED] gpu_test_buddy_alloc_pessimistic
[05:00:16] [PASSED] gpu_test_buddy_alloc_pathological
[05:00:16] [PASSED] gpu_test_buddy_alloc_contiguous
[05:00:16] [PASSED] gpu_test_buddy_alloc_clear
[05:00:16] [PASSED] gpu_test_buddy_alloc_range
[05:00:16] [PASSED] gpu_test_buddy_alloc_range_bias
[05:00:17] [PASSED] gpu_test_buddy_fragmentation_performance
[05:00:18] [PASSED] gpu_test_buddy_dirty_tracker_performance
[05:00:18] [PASSED] gpu_test_buddy_alloc_exceeds_max_order
[05:00:18] [PASSED] gpu_test_buddy_offset_aligned_allocation
[05:00:18] [PASSED] gpu_test_buddy_subtree_offset_alignment_stress
[05:00:18] [PASSED] gpu_test_buddy_addr_to_block
[05:00:18] ==================== [PASSED] gpu_buddy ====================
[05:00:18] ============================================================
[05:00:18] Testing complete. Ran 14 tests: passed: 14
[05:00:18] Elapsed time: 26.565s total, 4.410s configuring, 20.287s building, 1.832s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/xe/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[05:00:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:00:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:00:53] Starting KUnit Kernel (1/1)...
[05:00:53] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:00:53] ================== guc_buf (11 subtests) ===================
[05:00:53] [PASSED] test_smallest
[05:00:53] [PASSED] test_largest
[05:00:53] [PASSED] test_granular
[05:00:53] [PASSED] test_unique
[05:00:53] [PASSED] test_overlap
[05:00:53] [PASSED] test_reusable
[05:00:53] [PASSED] test_too_big
[05:00:53] [PASSED] test_flush
[05:00:53] [PASSED] test_lookup
[05:00:53] [PASSED] test_data
[05:00:53] [PASSED] test_class
[05:00:53] ===================== [PASSED] guc_buf =====================
[05:00:53] =================== guc_dbm (7 subtests) ===================
[05:00:53] [PASSED] test_empty
[05:00:53] [PASSED] test_default
[05:00:53] ======================== test_size  ========================
[05:00:53] [PASSED] 4
[05:00:53] [PASSED] 8
[05:00:53] [PASSED] 32
[05:00:53] [PASSED] 256
[05:00:53] ==================== [PASSED] test_size ====================
[05:00:53] ======================= test_reuse  ========================
[05:00:53] [PASSED] 4
[05:00:53] [PASSED] 8
[05:00:53] [PASSED] 32
[05:00:53] [PASSED] 256
[05:00:53] =================== [PASSED] test_reuse ====================
[05:00:53] =================== test_range_overlap  ====================
[05:00:53] [PASSED] 4
[05:00:53] [PASSED] 8
[05:00:53] [PASSED] 32
[05:00:53] [PASSED] 256
[05:00:53] =============== [PASSED] test_range_overlap ================
[05:00:53] =================== test_range_compact  ====================
[05:00:53] [PASSED] 4
[05:00:53] [PASSED] 8
[05:00:53] [PASSED] 32
[05:00:53] [PASSED] 256
[05:00:53] =============== [PASSED] test_range_compact ================
[05:00:53] ==================== test_range_spare  =====================
[05:00:53] [PASSED] 4
[05:00:53] [PASSED] 8
[05:00:53] [PASSED] 32
[05:00:53] [PASSED] 256
[05:00:53] ================ [PASSED] test_range_spare =================
[05:00:53] ===================== [PASSED] guc_dbm =====================
[05:00:53] =================== guc_idm (6 subtests) ===================
[05:00:53] [PASSED] bad_init
[05:00:53] [PASSED] no_init
[05:00:53] [PASSED] init_fini
[05:00:53] [PASSED] check_used
[05:00:53] [PASSED] check_quota
[05:00:53] [PASSED] check_all
[05:00:53] ===================== [PASSED] guc_idm =====================
[05:00:53] ============== guc_klv_helpers (13 subtests) ===============
[05:00:53] [PASSED] test_count
[05:00:53] [PASSED] test_encode_u32
[05:00:53] [PASSED] test_encode_u64
[05:00:53] [PASSED] test_encode_string
[05:00:53] [PASSED] test_encode_object_raw
[05:00:53] [PASSED] test_encode_object_klv
[05:00:53] [PASSED] test_encode_object_nested
[05:00:53] [PASSED] test_encode_object_basic
[05:00:53] ===================== test_decode_u16  =====================
[05:00:53] [PASSED] empty
[05:00:53] [PASSED] valid
[05:00:53] [PASSED] max
[05:00:53] [PASSED] big
[05:00:53] [PASSED] long
[05:00:53] ================= [PASSED] test_decode_u16 =================
[05:00:53] ===================== test_decode_u32  =====================
[05:00:53] [PASSED] empty
[05:00:53] [PASSED] valid
[05:00:53] [PASSED] max
[05:00:53] [PASSED] long
[05:00:53] ================= [PASSED] test_decode_u32 =================
[05:00:53] ===================== test_decode_u64  =====================
[05:00:53] [PASSED] empty
[05:00:53] [PASSED] short
[05:00:53] [PASSED] valid
[05:00:53] [PASSED] max
[05:00:53] [PASSED] long
[05:00:53] ================= [PASSED] test_decode_u64 =================
[05:00:53] ===================== test_decode_str  =====================
[05:00:53] [PASSED] empty
[05:00:53] [PASSED] one
[05:00:53] [PASSED] one_trash
[05:00:53] [PASSED] two
[05:00:53] [PASSED] two_trash
[05:00:53] [PASSED] three
[05:00:53] [PASSED] dword
[05:00:53] [PASSED] four
[05:00:53] [PASSED] five
[05:00:53] [PASSED] six
[05:00:53] [PASSED] seven
[05:00:53] [PASSED] qword
[05:00:53] ================= [PASSED] test_decode_str =================
[05:00:53] [PASSED] test_print
[05:00:53] ================= [PASSED] guc_klv_helpers =================
[05:00:53] =================== xe_log (4 subtests) ====================
[05:00:53] [PASSED] demo_cper
[05:00:53] [PASSED] demo_dmesg
[05:00:53] ======================= test_dmesg  ========================
[05:00:53] [PASSED] test_fatal
[05:00:53] [PASSED] test_fatal_tile
[05:00:53] [PASSED] test_fatal_gt
[05:00:53] [PASSED] test_fatal_comp
[05:00:53] [PASSED] test_fatal_comp_tile
[05:00:53] [PASSED] test_fatal_comp_gt
[05:00:53] [PASSED] test_fatal_all
[05:00:53] [PASSED] test_recoverable
[05:00:53] [PASSED] test_recoverable_tile
[05:00:53] [PASSED] test_recoverable_gt
[05:00:53] [PASSED] test_recoverable_comp
[05:00:53] [PASSED] test_recoverable_comp_tile
[05:00:53] [PASSED] test_recoverable_comp_gt
[05:00:53] [PASSED] test_recoverable_all
[05:00:53] [PASSED] test_info
[05:00:53] [PASSED] test_info_tile
[05:00:53] [PASSED] test_info_gt
[05:00:53] [PASSED] test_info_err
[05:00:53] [PASSED] test_info_comp
[05:00:53] [PASSED] test_info_comp_tile
[05:00:53] [PASSED] test_info_comp_gt
[05:00:53] [PASSED] test_info_all
[05:00:53] [PASSED] test_hw_fatal
[05:00:53] [PASSED] test_hw_recoverable
[05:00:53] [PASSED] test_hw_corrected
[05:00:53] [PASSED] test_hw_informational
[05:00:53] =================== [PASSED] test_dmesg ====================
[05:00:53] ====================== test_invalid  =======================
[05:00:53] [SKIPPED] no-component no-location no-warn (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] reserved location (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] unknown location (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] nonzero-device-id location (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] invalid-tile-id location (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] invalid-gt-id location (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] unknown component class (requires CONFIG_DRM_XE_DEBUG)
[05:00:53] [SKIPPED] unknown system component (requires CONFIG_DRM_XE_DEBUG)
[05:00:54] [SKIPPED] unknown hardware component (requires CONFIG_DRM_XE_DEBUG)
[05:00:54] [SKIPPED] unknown component and location (requires CONFIG_DRM_XE_DEBUG)
[05:00:54] ================== [SKIPPED] test_invalid ==================
[05:00:54] ===================== [PASSED] xe_log ======================
[05:00:54] ================== no_relay (3 subtests) ===================
[05:00:54] [PASSED] xe_drops_guc2pf_if_not_ready
[05:00:54] [PASSED] xe_drops_guc2vf_if_not_ready
[05:00:54] [PASSED] xe_rejects_send_if_not_ready
[05:00:54] ==================== [PASSED] no_relay =====================
[05:00:54] ================== pf_relay (14 subtests) ==================
[05:00:54] [PASSED] pf_rejects_guc2pf_too_short
[05:00:54] [PASSED] pf_rejects_guc2pf_too_long
[05:00:54] [PASSED] pf_rejects_guc2pf_no_payload
[05:00:54] [PASSED] pf_fails_no_payload
[05:00:54] [PASSED] pf_fails_bad_origin
[05:00:54] [PASSED] pf_fails_bad_type
[05:00:54] [PASSED] pf_txn_reports_error
[05:00:54] [PASSED] pf_txn_sends_pf2guc
[05:00:54] [PASSED] pf_sends_pf2guc
[05:00:54] [SKIPPED] pf_loopback_nop (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:00:54] [SKIPPED] pf_loopback_echo (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:00:54] [SKIPPED] pf_loopback_fail (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:00:54] [SKIPPED] pf_loopback_busy (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:00:54] [SKIPPED] pf_loopback_retry (requires CONFIG_DRM_XE_DEBUG_SRIOV)
[05:00:54] ==================== [PASSED] pf_relay =====================
[05:00:54] ================== vf_relay (3 subtests) ===================
[05:00:54] [PASSED] vf_rejects_guc2vf_too_short
[05:00:54] [PASSED] vf_rejects_guc2vf_too_long
[05:00:54] [PASSED] vf_rejects_guc2vf_no_payload
[05:00:54] ==================== [PASSED] vf_relay =====================
[05:00:54] ================ pf_gt_config (9 subtests) =================
[05:00:54] [PASSED] fair_contexts_1vf
[05:00:54] [PASSED] fair_doorbells_1vf
[05:00:54] [PASSED] fair_ggtt_1vf
[05:00:54] ====================== fair_vram_1vf  ======================
[05:00:54] [PASSED] 3.50 GiB
[05:00:54] [PASSED] 11.5 GiB
[05:00:54] [PASSED] 15.5 GiB
[05:00:54] [PASSED] 31.5 GiB
[05:00:54] [PASSED] 63.5 GiB
[05:00:54] [PASSED] 1.91 GiB
[05:00:54] ================== [PASSED] fair_vram_1vf ==================
[05:00:54] ================ fair_vram_1vf_admin_only  =================
[05:00:54] [PASSED] 3.50 GiB
[05:00:54] [PASSED] 11.5 GiB
[05:00:54] [PASSED] 15.5 GiB
[05:00:54] [PASSED] 31.5 GiB
[05:00:54] [PASSED] 63.5 GiB
[05:00:54] [PASSED] 1.91 GiB
[05:00:54] ============ [PASSED] fair_vram_1vf_admin_only =============
[05:00:54] ====================== fair_contexts  ======================
[05:00:54] [PASSED] 1 VF
[05:00:54] [PASSED] 2 VFs
[05:00:54] [PASSED] 3 VFs
[05:00:54] [PASSED] 4 VFs
[05:00:54] [PASSED] 5 VFs
[05:00:54] [PASSED] 6 VFs
[05:00:54] [PASSED] 7 VFs
[05:00:54] [PASSED] 8 VFs
[05:00:54] [PASSED] 9 VFs
[05:00:54] [PASSED] 10 VFs
[05:00:54] [PASSED] 11 VFs
[05:00:54] [PASSED] 12 VFs
[05:00:54] [PASSED] 13 VFs
[05:00:54] [PASSED] 14 VFs
[05:00:54] [PASSED] 15 VFs
[05:00:54] [PASSED] 16 VFs
[05:00:54] [PASSED] 17 VFs
[05:00:54] [PASSED] 18 VFs
[05:00:54] [PASSED] 19 VFs
[05:00:54] [PASSED] 20 VFs
[05:00:54] [PASSED] 21 VFs
[05:00:54] [PASSED] 22 VFs
[05:00:54] [PASSED] 23 VFs
[05:00:54] [PASSED] 24 VFs
[05:00:54] [PASSED] 25 VFs
[05:00:54] [PASSED] 26 VFs
[05:00:54] [PASSED] 27 VFs
[05:00:54] [PASSED] 28 VFs
[05:00:54] [PASSED] 29 VFs
[05:00:54] [PASSED] 30 VFs
[05:00:54] [PASSED] 31 VFs
[05:00:54] [PASSED] 32 VFs
[05:00:54] [PASSED] 33 VFs
[05:00:54] [PASSED] 34 VFs
[05:00:54] [PASSED] 35 VFs
[05:00:54] [PASSED] 36 VFs
[05:00:54] [PASSED] 37 VFs
[05:00:54] [PASSED] 38 VFs
[05:00:54] [PASSED] 39 VFs
[05:00:54] [PASSED] 40 VFs
[05:00:54] [PASSED] 41 VFs
[05:00:54] [PASSED] 42 VFs
[05:00:54] [PASSED] 43 VFs
[05:00:54] [PASSED] 44 VFs
[05:00:54] [PASSED] 45 VFs
[05:00:54] [PASSED] 46 VFs
[05:00:54] [PASSED] 47 VFs
[05:00:54] [PASSED] 48 VFs
[05:00:54] [PASSED] 49 VFs
[05:00:54] [PASSED] 50 VFs
[05:00:54] [PASSED] 51 VFs
[05:00:54] [PASSED] 52 VFs
[05:00:54] [PASSED] 53 VFs
[05:00:54] [PASSED] 54 VFs
[05:00:54] [PASSED] 55 VFs
[05:00:54] [PASSED] 56 VFs
[05:00:54] [PASSED] 57 VFs
[05:00:54] [PASSED] 58 VFs
[05:00:54] [PASSED] 59 VFs
[05:00:54] [PASSED] 60 VFs
[05:00:54] [PASSED] 61 VFs
[05:00:54] [PASSED] 62 VFs
[05:00:54] [PASSED] 63 VFs
[05:00:54] ================== [PASSED] fair_contexts ==================
[05:00:54] ===================== fair_doorbells  ======================
[05:00:54] [PASSED] 1 VF
[05:00:54] [PASSED] 2 VFs
[05:00:54] [PASSED] 3 VFs
[05:00:54] [PASSED] 4 VFs
[05:00:54] [PASSED] 5 VFs
[05:00:54] [PASSED] 6 VFs
[05:00:54] [PASSED] 7 VFs
[05:00:54] [PASSED] 8 VFs
[05:00:54] [PASSED] 9 VFs
[05:00:54] [PASSED] 10 VFs
[05:00:54] [PASSED] 11 VFs
[05:00:54] [PASSED] 12 VFs
[05:00:54] [PASSED] 13 VFs
[05:00:54] [PASSED] 14 VFs
[05:00:54] [PASSED] 15 VFs
[05:00:54] [PASSED] 16 VFs
[05:00:54] [PASSED] 17 VFs
[05:00:54] [PASSED] 18 VFs
[05:00:54] [PASSED] 19 VFs
[05:00:54] [PASSED] 20 VFs
[05:00:54] [PASSED] 21 VFs
[05:00:54] [PASSED] 22 VFs
[05:00:54] [PASSED] 23 VFs
[05:00:54] [PASSED] 24 VFs
[05:00:54] [PASSED] 25 VFs
[05:00:54] [PASSED] 26 VFs
[05:00:54] [PASSED] 27 VFs
[05:00:54] [PASSED] 28 VFs
[05:00:54] [PASSED] 29 VFs
[05:00:54] [PASSED] 30 VFs
[05:00:54] [PASSED] 31 VFs
[05:00:54] [PASSED] 32 VFs
[05:00:54] [PASSED] 33 VFs
[05:00:54] [PASSED] 34 VFs
[05:00:54] [PASSED] 35 VFs
[05:00:54] [PASSED] 36 VFs
[05:00:54] [PASSED] 37 VFs
[05:00:54] [PASSED] 38 VFs
[05:00:54] [PASSED] 39 VFs
[05:00:54] [PASSED] 40 VFs
[05:00:54] [PASSED] 41 VFs
[05:00:54] [PASSED] 42 VFs
[05:00:54] [PASSED] 43 VFs
[05:00:54] [PASSED] 44 VFs
[05:00:54] [PASSED] 45 VFs
[05:00:54] [PASSED] 46 VFs
[05:00:54] [PASSED] 47 VFs
[05:00:54] [PASSED] 48 VFs
[05:00:54] [PASSED] 49 VFs
[05:00:54] [PASSED] 50 VFs
[05:00:54] [PASSED] 51 VFs
[05:00:54] [PASSED] 52 VFs
[05:00:54] [PASSED] 53 VFs
[05:00:54] [PASSED] 54 VFs
[05:00:54] [PASSED] 55 VFs
[05:00:54] [PASSED] 56 VFs
[05:00:54] [PASSED] 57 VFs
[05:00:54] [PASSED] 58 VFs
[05:00:54] [PASSED] 59 VFs
[05:00:54] [PASSED] 60 VFs
[05:00:54] [PASSED] 61 VFs
[05:00:54] [PASSED] 62 VFs
[05:00:54] [PASSED] 63 VFs
[05:00:54] ================= [PASSED] fair_doorbells ==================
[05:00:54] ======================== fair_ggtt  ========================
[05:00:54] [PASSED] 1 VF
[05:00:54] [PASSED] 2 VFs
[05:00:54] [PASSED] 3 VFs
[05:00:54] [PASSED] 4 VFs
[05:00:54] [PASSED] 5 VFs
[05:00:54] [PASSED] 6 VFs
[05:00:54] [PASSED] 7 VFs
[05:00:54] [PASSED] 8 VFs
[05:00:54] [PASSED] 9 VFs
[05:00:54] [PASSED] 10 VFs
[05:00:54] [PASSED] 11 VFs
[05:00:54] [PASSED] 12 VFs
[05:00:54] [PASSED] 13 VFs
[05:00:54] [PASSED] 14 VFs
[05:00:54] [PASSED] 15 VFs
[05:00:54] [PASSED] 16 VFs
[05:00:54] [PASSED] 17 VFs
[05:00:54] [PASSED] 18 VFs
[05:00:54] [PASSED] 19 VFs
[05:00:54] [PASSED] 20 VFs
[05:00:54] [PASSED] 21 VFs
[05:00:54] [PASSED] 22 VFs
[05:00:54] [PASSED] 23 VFs
[05:00:54] [PASSED] 24 VFs
[05:00:54] [PASSED] 25 VFs
[05:00:54] [PASSED] 26 VFs
[05:00:54] [PASSED] 27 VFs
[05:00:54] [PASSED] 28 VFs
[05:00:54] [PASSED] 29 VFs
[05:00:54] [PASSED] 30 VFs
[05:00:54] [PASSED] 31 VFs
[05:00:54] [PASSED] 32 VFs
[05:00:54] [PASSED] 33 VFs
[05:00:54] [PASSED] 34 VFs
[05:00:54] [PASSED] 35 VFs
[05:00:54] [PASSED] 36 VFs
[05:00:54] [PASSED] 37 VFs
[05:00:54] [PASSED] 38 VFs
[05:00:54] [PASSED] 39 VFs
[05:00:54] [PASSED] 40 VFs
[05:00:54] [PASSED] 41 VFs
[05:00:54] [PASSED] 42 VFs
[05:00:54] [PASSED] 43 VFs
[05:00:54] [PASSED] 44 VFs
[05:00:54] [PASSED] 45 VFs
[05:00:54] [PASSED] 46 VFs
[05:00:54] [PASSED] 47 VFs
[05:00:54] [PASSED] 48 VFs
[05:00:54] [PASSED] 49 VFs
[05:00:54] [PASSED] 50 VFs
[05:00:54] [PASSED] 51 VFs
[05:00:54] [PASSED] 52 VFs
[05:00:54] [PASSED] 53 VFs
[05:00:54] [PASSED] 54 VFs
[05:00:54] [PASSED] 55 VFs
[05:00:54] [PASSED] 56 VFs
[05:00:54] [PASSED] 57 VFs
[05:00:54] [PASSED] 58 VFs
[05:00:54] [PASSED] 59 VFs
[05:00:54] [PASSED] 60 VFs
[05:00:54] [PASSED] 61 VFs
[05:00:54] [PASSED] 62 VFs
[05:00:54] [PASSED] 63 VFs
[05:00:54] ==================== [PASSED] fair_ggtt ====================
[05:00:54] ======================== fair_vram  ========================
[05:00:54] [PASSED] 1 VF
[05:00:54] [PASSED] 2 VFs
[05:00:54] [PASSED] 3 VFs
[05:00:54] [PASSED] 4 VFs
[05:00:54] [PASSED] 5 VFs
[05:00:54] [PASSED] 6 VFs
[05:00:54] [PASSED] 7 VFs
[05:00:54] [PASSED] 8 VFs
[05:00:54] [PASSED] 9 VFs
[05:00:54] [PASSED] 10 VFs
[05:00:54] [PASSED] 11 VFs
[05:00:54] [PASSED] 12 VFs
[05:00:54] [PASSED] 13 VFs
[05:00:54] [PASSED] 14 VFs
[05:00:54] [PASSED] 15 VFs
[05:00:54] [PASSED] 16 VFs
[05:00:54] [PASSED] 17 VFs
[05:00:54] [PASSED] 18 VFs
[05:00:54] [PASSED] 19 VFs
[05:00:54] [PASSED] 20 VFs
[05:00:54] [PASSED] 21 VFs
[05:00:54] [PASSED] 22 VFs
[05:00:54] [PASSED] 23 VFs
[05:00:54] [PASSED] 24 VFs
[05:00:54] [PASSED] 25 VFs
[05:00:54] [PASSED] 26 VFs
[05:00:54] [PASSED] 27 VFs
[05:00:54] [PASSED] 28 VFs
[05:00:54] [PASSED] 29 VFs
[05:00:54] [PASSED] 30 VFs
[05:00:54] [PASSED] 31 VFs
[05:00:54] [PASSED] 32 VFs
[05:00:54] [PASSED] 33 VFs
[05:00:54] [PASSED] 34 VFs
[05:00:54] [PASSED] 35 VFs
[05:00:54] [PASSED] 36 VFs
[05:00:54] [PASSED] 37 VFs
[05:00:54] [PASSED] 38 VFs
[05:00:54] [PASSED] 39 VFs
[05:00:54] [PASSED] 40 VFs
[05:00:54] [PASSED] 41 VFs
[05:00:54] [PASSED] 42 VFs
[05:00:54] [PASSED] 43 VFs
[05:00:54] [PASSED] 44 VFs
[05:00:54] [PASSED] 45 VFs
[05:00:54] [PASSED] 46 VFs
[05:00:54] [PASSED] 47 VFs
[05:00:54] [PASSED] 48 VFs
[05:00:54] [PASSED] 49 VFs
[05:00:54] [PASSED] 50 VFs
[05:00:54] [PASSED] 51 VFs
[05:00:54] [PASSED] 52 VFs
[05:00:54] [PASSED] 53 VFs
[05:00:54] [PASSED] 54 VFs
[05:00:54] [PASSED] 55 VFs
[05:00:54] [PASSED] 56 VFs
[05:00:54] [PASSED] 57 VFs
[05:00:54] [PASSED] 58 VFs
[05:00:54] [PASSED] 59 VFs
[05:00:54] [PASSED] 60 VFs
[05:00:54] [PASSED] 61 VFs
[05:00:54] [PASSED] 62 VFs
[05:00:54] [PASSED] 63 VFs
[05:00:54] ==================== [PASSED] fair_vram ====================
[05:00:54] ================== [PASSED] pf_gt_config ===================
[05:00:54] ===================== lmtt (1 subtest) =====================
[05:00:54] ======================== test_ops  =========================
[05:00:54] [PASSED] 2-level
[05:00:54] [PASSED] multi-level
[05:00:54] ==================== [PASSED] test_ops =====================
[05:00:54] ====================== [PASSED] lmtt =======================
[05:00:54] ================= sriov_packet (1 subtest) =================
[05:00:54] [PASSED] test_descriptor_init
[05:00:54] ================== [PASSED] sriov_packet ===================
[05:00:54] ================= pf_service (11 subtests) =================
[05:00:54] [PASSED] pf_negotiate_any
[05:00:54] [PASSED] pf_negotiate_base_match
[05:00:54] [PASSED] pf_negotiate_base_newer
[05:00:54] [PASSED] pf_negotiate_base_next
[05:00:54] [SKIPPED] pf_negotiate_base_older (no older minor)
[05:00:54] [PASSED] pf_negotiate_base_prev
[05:00:54] [PASSED] pf_negotiate_latest_match
[05:00:54] [PASSED] pf_negotiate_latest_newer
[05:00:54] [PASSED] pf_negotiate_latest_next
[05:00:54] [SKIPPED] pf_negotiate_latest_older (no older minor)
[05:00:54] [SKIPPED] pf_negotiate_latest_prev (no prev major)
[05:00:54] =================== [PASSED] pf_service ====================
[05:00:54] ================= xe_guc_g2g (2 subtests) ==================
[05:00:54] ============== xe_live_guc_g2g_kunit_default  ==============
[05:00:54] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[05:00:54] ============== xe_live_guc_g2g_kunit_allmem  ===============
[05:00:54] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[05:00:54] =================== [SKIPPED] xe_guc_g2g ===================
[05:00:54] =================== xe_mocs (2 subtests) ===================
[05:00:54] ================ xe_live_mocs_kernel_kunit  ================
[05:00:54] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[05:00:54] ================ xe_live_mocs_reset_kunit  =================
[05:00:54] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[05:00:54] ==================== [SKIPPED] xe_mocs =====================
[05:00:54] ================= xe_migrate (2 subtests) ==================
[05:00:54] ================= xe_migrate_sanity_kunit  =================
[05:00:54] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[05:00:54] ================== xe_validate_ccs_kunit  ==================
[05:00:54] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[05:00:54] =================== [SKIPPED] xe_migrate ===================
[05:00:54] ================== xe_dma_buf (1 subtest) ==================
[05:00:54] ==================== xe_dma_buf_kunit  =====================
[05:00:54] ================ [SKIPPED] xe_dma_buf_kunit ================
[05:00:54] =================== [SKIPPED] xe_dma_buf ===================
[05:00:54] ================= xe_bo_shrink (1 subtest) =================
[05:00:54] =================== xe_bo_shrink_kunit  ====================
[05:00:54] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[05:00:54] ================== [SKIPPED] xe_bo_shrink ==================
[05:00:54] ==================== xe_bo (2 subtests) ====================
[05:00:54] ================== xe_ccs_migrate_kunit  ===================
[05:00:54] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[05:00:54] ==================== xe_bo_evict_kunit  ====================
[05:00:54] =============== [SKIPPED] xe_bo_evict_kunit ================
[05:00:54] ===================== [SKIPPED] xe_bo ======================
[05:00:54] =================== xe_any (9 subtests) ====================
[05:00:54] [PASSED] test_to_xe
[05:00:54] [PASSED] test_to_dev
[05:00:54] [PASSED] test_to_pdev
[05:00:54] [PASSED] test_to_drm
[05:00:54] [PASSED] test_if_pdev
[05:00:54] [PASSED] test_if_xe
[05:00:54] [PASSED] test_if_tile
[05:00:54] [PASSED] test_if_gt
[05:00:54] [PASSED] test_to_id
[05:00:54] ===================== [PASSED] xe_any ======================
[05:00:54] ==================== args (13 subtests) ====================
[05:00:54] [PASSED] count_args_test
[05:00:54] [PASSED] call_args_example
[05:00:54] [PASSED] call_args_test
[05:00:54] [PASSED] drop_first_arg_example
[05:00:54] [PASSED] drop_first_arg_test
[05:00:54] [PASSED] first_arg_example
[05:00:54] [PASSED] first_arg_test
[05:00:54] [PASSED] last_arg_example
[05:00:54] [PASSED] last_arg_test
[05:00:54] [PASSED] pick_arg_example
[05:00:54] [PASSED] if_args_example
[05:00:54] [PASSED] if_args_test
[05:00:54] [PASSED] sep_comma_example
[05:00:54] ====================== [PASSED] args =======================
[05:00:54] =================== xe_pci (3 subtests) ====================
[05:00:54] ==================== check_graphics_ip  ====================
[05:00:54] [PASSED] 12.00 Xe_LP
[05:00:54] [PASSED] 12.10 Xe_LP+
[05:00:54] [PASSED] 12.55 Xe_HPG
[05:00:54] [PASSED] 12.60 Xe_HPC
[05:00:54] [PASSED] 12.70 Xe_LPG
[05:00:54] [PASSED] 12.71 Xe_LPG
[05:00:54] [PASSED] 12.74 Xe_LPG+
[05:00:54] [PASSED] 20.01 Xe2_HPG
[05:00:54] [PASSED] 20.02 Xe2_HPG
[05:00:54] [PASSED] 20.04 Xe2_LPG
[05:00:54] [PASSED] 30.00 Xe3_LPG
[05:00:54] [PASSED] 30.01 Xe3_LPG
[05:00:54] [PASSED] 30.03 Xe3_LPG
[05:00:54] [PASSED] 30.04 Xe3_LPG
[05:00:54] [PASSED] 30.05 Xe3_LPG
[05:00:54] [PASSED] 35.10 Xe3p_LPG
[05:00:54] [PASSED] 35.11 Xe3p_XPC
[05:00:54] ================ [PASSED] check_graphics_ip ================
[05:00:54] ===================== check_media_ip  ======================
[05:00:54] [PASSED] 12.00 Xe_M
[05:00:54] [PASSED] 12.55 Xe_HPM
[05:00:54] [PASSED] 13.00 Xe_LPM+
[05:00:54] [PASSED] 13.01 Xe2_HPM
[05:00:54] [PASSED] 20.00 Xe2_LPM
[05:00:54] [PASSED] 30.00 Xe3_LPM
[05:00:54] [PASSED] 30.02 Xe3_LPM
[05:00:54] [PASSED] 35.00 Xe3p_LPM
[05:00:54] [PASSED] 35.03 Xe3p_HPM
[05:00:54] ================= [PASSED] check_media_ip ==================
[05:00:54] =================== check_platform_desc  ===================
[05:00:54] [PASSED] 0x9A60 (TIGERLAKE)
[05:00:54] [PASSED] 0x9A68 (TIGERLAKE)
[05:00:54] [PASSED] 0x9A70 (TIGERLAKE)
[05:00:54] [PASSED] 0x9A40 (TIGERLAKE)
[05:00:54] [PASSED] 0x9A49 (TIGERLAKE)
[05:00:54] [PASSED] 0x9A59 (TIGERLAKE)
[05:00:54] [PASSED] 0x9A78 (TIGERLAKE)
[05:00:54] [PASSED] 0x9AC0 (TIGERLAKE)
[05:00:54] [PASSED] 0x9AC9 (TIGERLAKE)
[05:00:54] [PASSED] 0x9AD9 (TIGERLAKE)
[05:00:54] [PASSED] 0x9AF8 (TIGERLAKE)
[05:00:54] [PASSED] 0x4C80 (ROCKETLAKE)
[05:00:54] [PASSED] 0x4C8A (ROCKETLAKE)
[05:00:54] [PASSED] 0x4C8B (ROCKETLAKE)
[05:00:54] [PASSED] 0x4C8C (ROCKETLAKE)
[05:00:54] [PASSED] 0x4C90 (ROCKETLAKE)
[05:00:54] [PASSED] 0x4C9A (ROCKETLAKE)
[05:00:54] [PASSED] 0x4680 (ALDERLAKE_S)
[05:00:54] [PASSED] 0x4682 (ALDERLAKE_S)
[05:00:54] [PASSED] 0x4688 (ALDERLAKE_S)
[05:00:54] [PASSED] 0x468A (ALDERLAKE_S)
[05:00:54] [PASSED] 0x468B (ALDERLAKE_S)
[05:00:54] [PASSED] 0x4690 (ALDERLAKE_S)
[05:00:54] [PASSED] 0x4692 (ALDERLAKE_S)
[05:00:54] [PASSED] 0x4693 (ALDERLAKE_S)
[05:00:54] [PASSED] 0x46A0 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46A1 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46A2 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46A3 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46A6 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46A8 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46AA (ALDERLAKE_P)
[05:00:54] [PASSED] 0x462A (ALDERLAKE_P)
[05:00:54] [PASSED] 0x4626 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x4628 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46B0 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46B1 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46B2 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46B3 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46C0 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46C1 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46C2 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46C3 (ALDERLAKE_P)
[05:00:54] [PASSED] 0x46D0 (ALDERLAKE_N)
[05:00:54] [PASSED] 0x46D1 (ALDERLAKE_N)
[05:00:54] [PASSED] 0x46D2 (ALDERLAKE_N)
[05:00:54] [PASSED] 0x46D3 (ALDERLAKE_N)
[05:00:54] [PASSED] 0x46D4 (ALDERLAKE_N)
[05:00:54] [PASSED] 0xA721 (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7A1 (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7A9 (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7AC (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7AD (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA720 (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7A0 (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7A8 (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7AA (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA7AB (ALDERLAKE_P)
[05:00:54] [PASSED] 0xA780 (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA781 (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA782 (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA783 (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA788 (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA789 (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA78A (ALDERLAKE_S)
[05:00:54] [PASSED] 0xA78B (ALDERLAKE_S)
[05:00:54] [PASSED] 0x4905 (DG1)
[05:00:54] [PASSED] 0x4906 (DG1)
[05:00:54] [PASSED] 0x4907 (DG1)
[05:00:54] [PASSED] 0x4908 (DG1)
[05:00:54] [PASSED] 0x4909 (DG1)
[05:00:54] [PASSED] 0x56C0 (DG2)
[05:00:54] [PASSED] 0x56C2 (DG2)
[05:00:54] [PASSED] 0x56C1 (DG2)
[05:00:54] [PASSED] 0x7D51 (METEORLAKE)
[05:00:54] [PASSED] 0x7DD1 (METEORLAKE)
[05:00:54] [PASSED] 0x7D41 (METEORLAKE)
[05:00:54] [PASSED] 0x7D67 (METEORLAKE)
[05:00:54] [PASSED] 0xB640 (METEORLAKE)
[05:00:54] [PASSED] 0x56A0 (DG2)
[05:00:54] [PASSED] 0x56A1 (DG2)
[05:00:54] [PASSED] 0x56A2 (DG2)
[05:00:54] [PASSED] 0x56BE (DG2)
[05:00:54] [PASSED] 0x56BF (DG2)
[05:00:54] [PASSED] 0x5690 (DG2)
[05:00:54] [PASSED] 0x5691 (DG2)
[05:00:54] [PASSED] 0x5692 (DG2)
[05:00:54] [PASSED] 0x56A5 (DG2)
[05:00:54] [PASSED] 0x56A6 (DG2)
[05:00:54] [PASSED] 0x56B0 (DG2)
[05:00:54] [PASSED] 0x56B1 (DG2)
[05:00:54] [PASSED] 0x56BA (DG2)
[05:00:54] [PASSED] 0x56BB (DG2)
[05:00:54] [PASSED] 0x56BC (DG2)
[05:00:54] [PASSED] 0x56BD (DG2)
[05:00:54] [PASSED] 0x5693 (DG2)
[05:00:54] [PASSED] 0x5694 (DG2)
[05:00:54] [PASSED] 0x5695 (DG2)
[05:00:54] [PASSED] 0x56A3 (DG2)
[05:00:54] [PASSED] 0x56A4 (DG2)
[05:00:54] [PASSED] 0x56B2 (DG2)
[05:00:54] [PASSED] 0x56B3 (DG2)
[05:00:54] [PASSED] 0x5696 (DG2)
[05:00:54] [PASSED] 0x5697 (DG2)
[05:00:54] [PASSED] 0xB69 (PVC)
[05:00:54] [PASSED] 0xB6E (PVC)
[05:00:54] [PASSED] 0xBD4 (PVC)
[05:00:54] [PASSED] 0xBD5 (PVC)
[05:00:54] [PASSED] 0xBD6 (PVC)
[05:00:54] [PASSED] 0xBD7 (PVC)
[05:00:54] [PASSED] 0xBD8 (PVC)
[05:00:54] [PASSED] 0xBD9 (PVC)
[05:00:54] [PASSED] 0xBDA (PVC)
[05:00:54] [PASSED] 0xBDB (PVC)
[05:00:54] [PASSED] 0xBE0 (PVC)
[05:00:54] [PASSED] 0xBE1 (PVC)
[05:00:54] [PASSED] 0xBE5 (PVC)
[05:00:54] [PASSED] 0x7D40 (METEORLAKE)
[05:00:54] [PASSED] 0x7D45 (METEORLAKE)
[05:00:54] [PASSED] 0x7D55 (METEORLAKE)
[05:00:54] [PASSED] 0x7D60 (METEORLAKE)
[05:00:54] [PASSED] 0x7DD5 (METEORLAKE)
[05:00:54] [PASSED] 0x6420 (LUNARLAKE)
[05:00:54] [PASSED] 0x64A0 (LUNARLAKE)
[05:00:54] [PASSED] 0x64B0 (LUNARLAKE)
[05:00:54] [PASSED] 0xE202 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE209 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE20B (BATTLEMAGE)
[05:00:54] [PASSED] 0xE20C (BATTLEMAGE)
[05:00:54] [PASSED] 0xE20D (BATTLEMAGE)
[05:00:54] [PASSED] 0xE210 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE211 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE212 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE216 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE220 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE221 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE222 (BATTLEMAGE)
[05:00:54] [PASSED] 0xE223 (BATTLEMAGE)
[05:00:54] [PASSED] 0xB080 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB081 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB082 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB083 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB084 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB085 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB086 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB087 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB08F (PANTHERLAKE)
[05:00:54] [PASSED] 0xB090 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB0A0 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB0A1 (PANTHERLAKE)
[05:00:54] [PASSED] 0xB0B0 (PANTHERLAKE)
[05:00:54] [PASSED] 0xFD80 (PANTHERLAKE)
[05:00:54] [PASSED] 0xFD81 (PANTHERLAKE)
[05:00:54] [PASSED] 0xD740 (NOVALAKE_S)
[05:00:54] [PASSED] 0xD741 (NOVALAKE_S)
[05:00:54] [PASSED] 0xD742 (NOVALAKE_S)
[05:00:54] [PASSED] 0xD743 (NOVALAKE_S)
[05:00:54] [PASSED] 0xD745 (NOVALAKE_S)
[05:00:54] [PASSED] 0xD74A (NOVALAKE_S)
[05:00:54] [PASSED] 0xD74B (NOVALAKE_S)
[05:00:54] [PASSED] 0x674C (CRESCENTISLAND)
[05:00:54] [PASSED] 0x674D (CRESCENTISLAND)
[05:00:54] [PASSED] 0x674E (CRESCENTISLAND)
[05:00:54] [PASSED] 0x674F (CRESCENTISLAND)
[05:00:54] [PASSED] 0x6750 (CRESCENTISLAND)
[05:00:54] [PASSED] 0x6751 (CRESCENTISLAND)
[05:00:54] [PASSED] 0xD750 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD751 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD752 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD753 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD754 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD755 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD756 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD757 (NOVALAKE_P)
[05:00:54] [PASSED] 0xD75F (NOVALAKE_P)
[05:00:54] =============== [PASSED] check_platform_desc ===============
[05:00:54] ===================== [PASSED] xe_pci ======================
[05:00:54] ============= xe_rtp_tables_test (5 subtests) ==============
[05:00:54] ================== xe_rtp_table_gt_test  ===================
[05:00:54] [PASSED] gt_was/14011060649
[05:00:54] [PASSED] gt_was/14011059788
[05:00:54] [PASSED] gt_was/14015795083
[05:00:54] [PASSED] gt_was/16021867713
[05:00:54] [PASSED] gt_was/14019449301
[05:00:54] [PASSED] gt_was/16028005424
[05:00:54] [PASSED] gt_was/14026578760
[05:00:54] [PASSED] gt_was/1409420604
[05:00:54] [PASSED] gt_was/1408615072
[05:00:54] [PASSED] gt_was/22010523718
[05:00:54] [PASSED] gt_was/14011006942
[05:00:54] [PASSED] gt_was/14014830051
[05:00:54] [PASSED] gt_was/18018781329
[05:00:54] [PASSED] gt_was/1509235366
[05:00:54] [PASSED] gt_was/18018781329
[05:00:54] [PASSED] gt_was/16016694945
[05:00:54] [PASSED] gt_was/14018575942
[05:00:54] [PASSED] gt_was/22016670082
[05:00:54] [PASSED] gt_was/22016670082
[05:00:54] [PASSED] gt_was/14017421178
[05:00:54] [PASSED] gt_was/16025250150
[05:00:54] [PASSED] gt_was/14021871409
[05:00:54] [PASSED] gt_was/16021865536
[05:00:54] [PASSED] gt_was/14021486841
[05:00:54] [PASSED] gt_was/14025160223
[05:00:54] [PASSED] gt_was/14026144927, 16029437861, 14026127056
[05:00:54] [PASSED] gt_was/14025635424
[05:00:54] [PASSED] gt_was/16028005424
[05:00:54] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:00:54] ================== xe_rtp_table_gt_test  ===================
[05:00:54] [PASSED] gt_tunings/Tuning: Blend Fill Caching Optimization Disable
[05:00:54] [PASSED] gt_tunings/Tuning: 32B Access Enable
[05:00:54] [PASSED] gt_tunings/Tuning: L3 cache
[05:00:54] [PASSED] gt_tunings/Tuning: L3 cache - media
[05:00:54] [PASSED] gt_tunings/Tuning: Compression Overfetch
[05:00:54] [PASSED] gt_tunings/Tuning: Compression Overfetch - media
[05:00:54] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3
[05:00:54] [PASSED] gt_tunings/Tuning: Enable compressible partial write overfetch in L3 - media
[05:00:54] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only
[05:00:54] [PASSED] gt_tunings/Tuning: L2 Overfetch Compressible Only - media
[05:00:54] [PASSED] gt_tunings/Tuning: Stateless compression control
[05:00:54] [PASSED] gt_tunings/Tuning: Stateless compression control - media
[05:00:54] [PASSED] gt_tunings/Tuning: L3 RW flush all Cache
[05:00:54] [PASSED] gt_tunings/Tuning: L3 RW flush all cache - media
[05:00:54] [PASSED] gt_tunings/Tuning: Set STLB Bank Hash Mode to 4KB
[05:00:54] [PASSED] gt_tunings/Tuning: Force All Non-Compressible Memory Reads to be 256B Overfetches
[05:00:54] ============== [PASSED] xe_rtp_table_gt_test ===============
[05:00:54] ================== xe_rtp_table_oob_test  ==================
[05:00:54] [PASSED] oob_was/1607983814
[05:00:54] [PASSED] oob_was/16010904313
[05:00:54] [PASSED] oob_was/18022495364
[05:00:54] [PASSED] oob_was/22012773006
[05:00:54] [PASSED] oob_was/14014475959
[05:00:54] [PASSED] oob_was/22011391025
[05:00:54] [PASSED] oob_was/22012727170
[05:00:54] [PASSED] oob_was/22012727685
[05:00:54] [PASSED] oob_was/22016596838
[05:00:54] [PASSED] oob_was/18020744125
[05:00:54] [PASSED] oob_was/1409600907
[05:00:54] [PASSED] oob_was/22014953428
[05:00:54] [PASSED] oob_was/16017236439
[05:00:54] [PASSED] oob_was/14019821291
[05:00:54] [PASSED] oob_was/14015076503
[05:00:54] [PASSED] oob_was/22016122933
[05:00:54] [PASSED] oob_was/14018913170
[05:00:54] [PASSED] oob_was/14018094691
[05:00:54] [PASSED] oob_was/18024947630
[05:00:54] [PASSED] oob_was/16022287689
[05:00:54] [PASSED] oob_was/13011645652
[05:00:54] [PASSED] oob_was/14022293748
[05:00:54] [PASSED] oob_was/22019794406
[05:00:54] [PASSED] oob_was/22019338487
[05:00:54] [PASSED] oob_was/16023588340
[05:00:54] [PASSED] oob_was/14019789679
[05:00:54] [PASSED] oob_was/14022866841
[05:00:54] [PASSED] oob_was/16021333562
[05:00:54] [PASSED] oob_was/14016712196
[05:00:54] [PASSED] oob_was/14015568240
[05:00:54] [PASSED] oob_was/18013179988
[05:00:54] [PASSED] oob_was/1508761755
[05:00:54] [PASSED] oob_was/16023105232
[05:00:54] [PASSED] oob_was/16026508708
[05:00:54] [PASSED] oob_was/14020001231
[05:00:54] [PASSED] oob_was/16023683509
[05:00:54] [PASSED] oob_was/14025515070
[05:00:54] [PASSED] oob_was/15015404425_disable
[05:00:54] [PASSED] oob_was/16026007364
[05:00:54] [PASSED] oob_was/14020316580
[05:00:54] [PASSED] oob_was/14025883347
[05:00:54] [PASSED] oob_was/16029380221
[05:00:54] [PASSED] oob_was/22022079272
[05:00:54] [PASSED] oob_was/16029897822
[05:00:54] [PASSED] oob_was/14027054324
[05:00:54] [PASSED] oob_was/14025941587
[05:00:54] [PASSED] oob_was/16030224309
[05:00:54] ============== [PASSED] xe_rtp_table_oob_test ==============
[05:00:54] ================ xe_rtp_table_dev_oob_test  ================
[05:00:54] [PASSED] device_oob_was/22010954014
[05:00:54] [PASSED] device_oob_was/15015404425
[05:00:54] [PASSED] device_oob_was/22019338487_display
[05:00:54] [PASSED] device_oob_was/14022085890
[05:00:54] [PASSED] device_oob_was/14026539277
[05:00:54] [PASSED] device_oob_was/14026633728
[05:00:54] [PASSED] device_oob_was/14026746987
[05:00:54] [PASSED] device_oob_was/14026779378
[05:00:54] ============ [PASSED] xe_rtp_table_dev_oob_test ============
[05:00:54] ========== xe_rtp_table_missing_upper_bound_test  ==========
[05:00:54] [PASSED] register_whitelist/WaAllowPMDepthAndInvocationCountAccessFromUMD, 1408556865
[05:00:54] [PASSED] register_whitelist/1508744258, 14012131227, 1808121037
[05:00:54] [PASSED] register_whitelist/1806527549
[05:00:54] [PASSED] register_whitelist/allow_read_ctx_timestamp
[05:00:54] [PASSED] register_whitelist/allow_read_queue_timestamp
[05:00:54] [PASSED] register_whitelist/16014440446
[05:00:54] [PASSED] register_whitelist/16017236439
[05:00:54] [PASSED] register_whitelist/16020183090
[05:00:54] [PASSED] register_whitelist/14024997852
[05:00:54] [PASSED] register_whitelist/14024997852
[05:00:54] ====== [PASSED] xe_rtp_table_missing_upper_bound_test ======
[05:00:54] =============== [PASSED] xe_rtp_tables_test ================
[05:00:54] =================== xe_rtp (3 subtests) ====================
[05:00:54] =================== xe_rtp_rules_tests  ====================
[05:00:54] [PASSED] no
[05:00:54] [PASSED] yes
[05:00:54] [PASSED] no-and-no
[05:00:54] [PASSED] no-and-yes
[05:00:54] [PASSED] yes-and-no
[05:00:54] [PASSED] yes-and-yes
[05:00:54] [PASSED] no-or-no
[05:00:54] [PASSED] no-or-yes
[05:00:54] [PASSED] yes-or-no
[05:00:54] [PASSED] yes-or-yes
[05:00:54] [PASSED] no-yes-or-yes-no
[05:00:54] [PASSED] no-yes-or-yes-yes
[05:00:54] [PASSED] yes-yes-or-no-yes
[05:00:54] [PASSED] yes-yes-or-yes-yes
[05:00:54] [PASSED] no-no-or-yes-or-no
[05:00:54] [PASSED] or
[05:00:54] [PASSED] or-yes
[05:00:54] [PASSED] or-no
[05:00:54] [PASSED] yes-or
[05:00:54] [PASSED] no-or
[05:00:54] [PASSED] no-or-or-yes
[05:00:54] [PASSED] yes-or-or-no
[05:00:54] [PASSED] no-or-or-no
[05:00:54] [PASSED] missing-context-engine-class
[05:00:54] [PASSED] missing-context-engine-class-or-yes
[05:00:54] [PASSED] missing-context-engine-class-or-or-yes
[05:00:54] =============== [PASSED] xe_rtp_rules_tests ================
[05:00:54] =============== xe_rtp_process_to_sr_tests  ================
[05:00:54] [PASSED] coalesce-same-reg
[05:00:54] [PASSED] coalesce-same-reg-literal-and-func
[05:00:54] [PASSED] no-match-no-add
[05:00:54] [PASSED] two-regs-two-entries
[05:00:54] [PASSED] clr-one-set-other
[05:00:54] [PASSED] set-field
[05:00:54] [PASSED] conflict-duplicate
[05:00:54] [PASSED] conflict-not-disjoint
[05:00:54] [PASSED] conflict-not-disjoint-literal-and-func
[05:00:54] [PASSED] conflict-reg-type
[05:00:54] [PASSED] bad-mcr-reg-forced-to-regular
[05:00:54] [PASSED] bad-regular-reg-forced-to-mcr
[05:00:54] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[05:00:54] ================== xe_rtp_process_tests  ===================
[05:00:54] [PASSED] active1
[05:00:54] [PASSED] active2
[05:00:54] [PASSED] active-inactive
[05:00:54] [PASSED] inactive-active
[05:00:54] [PASSED] inactive-active-inactive
[05:00:54] [PASSED] inactive-inactive-inactive
[05:00:54] ============== [PASSED] xe_rtp_process_tests ===============
[05:00:54] ===================== [PASSED] xe_rtp ======================
[05:00:54] ==================== xe_wa (1 subtest) =====================
[05:00:54] ======================== xe_wa_gt  =========================
[05:00:54] [PASSED] TIGERLAKE B0
[05:00:54] [PASSED] DG1 A0
[05:00:54] [PASSED] DG1 B0
[05:00:54] [PASSED] ALDERLAKE_S A0
[05:00:54] [PASSED] ALDERLAKE_S B0
[05:00:54] [PASSED] ALDERLAKE_S C0
[05:00:54] [PASSED] ALDERLAKE_S D0
[05:00:54] [PASSED] ALDERLAKE_P A0
[05:00:54] [PASSED] ALDERLAKE_P B0
[05:00:54] [PASSED] ALDERLAKE_P C0
[05:00:54] [PASSED] ALDERLAKE_S RPLS D0
[05:00:54] [PASSED] ALDERLAKE_P RPLU E0
[05:00:54] [PASSED] DG2 G10 C0
[05:00:54] [PASSED] DG2 G11 B1
[05:00:54] [PASSED] DG2 G12 A1
[05:00:54] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:00:54] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[05:00:54] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[05:00:54] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[05:00:54] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[05:00:54] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[05:00:54] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[05:00:54] ==================== [PASSED] xe_wa_gt =====================
[05:00:54] ====================== [PASSED] xe_wa ======================
[05:00:54] ============================================================
[05:00:54] Testing complete. Ran 821 tests: passed: 793, skipped: 28
[05:00:54] Elapsed time: 36.130s total, 1.793s configuring, 33.571s building, 0.715s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[05:00:54] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:00:56] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:01:21] Starting KUnit Kernel (1/1)...
[05:01:21] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:01:21] ============ drm_test_pick_cmdline (2 subtests) ============
[05:01:21] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[05:01:21] =============== drm_test_pick_cmdline_named  ===============
[05:01:21] [PASSED] NTSC
[05:01:21] [PASSED] NTSC-J
[05:01:21] [PASSED] PAL
[05:01:21] [PASSED] PAL-M
[05:01:21] =========== [PASSED] drm_test_pick_cmdline_named ===========
[05:01:21] ============== [PASSED] drm_test_pick_cmdline ==============
[05:01:21] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[05:01:21] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[05:01:21] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[05:01:21] =========== drm_validate_clone_mode (2 subtests) ===========
[05:01:21] ============== drm_test_check_in_clone_mode  ===============
[05:01:21] [PASSED] in_clone_mode
[05:01:21] [PASSED] not_in_clone_mode
[05:01:21] ========== [PASSED] drm_test_check_in_clone_mode ===========
[05:01:21] =============== drm_test_check_valid_clones  ===============
[05:01:21] [PASSED] not_in_clone_mode
[05:01:21] [PASSED] valid_clone
[05:01:21] [PASSED] invalid_clone
[05:01:21] =========== [PASSED] drm_test_check_valid_clones ===========
[05:01:21] ============= [PASSED] drm_validate_clone_mode =============
[05:01:21] ============= drm_validate_modeset (1 subtest) =============
[05:01:21] [PASSED] drm_test_check_connector_changed_modeset
[05:01:21] ============== [PASSED] drm_validate_modeset ===============
[05:01:21] ====== drm_test_bridge_get_current_state (1 subtest) =======
[05:01:21] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[05:01:21] ======== [PASSED] drm_test_bridge_get_current_state ========
[05:01:21] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[05:01:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[05:01:21] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[05:01:21] [PASSED] drm_test_drm_bridge_helper_hdmi_output_bus_fmts
[05:01:21] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[05:01:21] ============== drm_bridge_alloc (2 subtests) ===============
[05:01:21] [PASSED] drm_test_drm_bridge_alloc_basic
[05:01:21] [PASSED] drm_test_drm_bridge_alloc_get_put
[05:01:21] ================ [PASSED] drm_bridge_alloc =================
[05:01:21] ============= drm_bridge_bus_fmt (5 subtests) ==============
[05:01:21] [PASSED] drm_test_bridge_rgb_yuv_rgb
[05:01:21] [PASSED] drm_test_bridge_must_convert_to_yuv444
[05:01:21] [PASSED] drm_test_bridge_hdmi_auto_rgb
[05:01:21] [PASSED] drm_test_bridge_auto_first
[05:01:21] [PASSED] drm_test_bridge_rgb_yuv_no_path
[05:01:21] =============== [PASSED] drm_bridge_bus_fmt ================
[05:01:21] ============= drm_cmdline_parser (40 subtests) =============
[05:01:21] [PASSED] drm_test_cmdline_force_d_only
[05:01:21] [PASSED] drm_test_cmdline_force_D_only_dvi
[05:01:21] [PASSED] drm_test_cmdline_force_D_only_hdmi
[05:01:21] [PASSED] drm_test_cmdline_force_D_only_not_digital
[05:01:21] [PASSED] drm_test_cmdline_force_e_only
[05:01:21] [PASSED] drm_test_cmdline_res
[05:01:21] [PASSED] drm_test_cmdline_res_vesa
[05:01:21] [PASSED] drm_test_cmdline_res_vesa_rblank
[05:01:21] [PASSED] drm_test_cmdline_res_rblank
[05:01:21] [PASSED] drm_test_cmdline_res_bpp
[05:01:21] [PASSED] drm_test_cmdline_res_refresh
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[05:01:21] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[05:01:21] [PASSED] drm_test_cmdline_res_margins_force_on
[05:01:21] [PASSED] drm_test_cmdline_res_vesa_margins
[05:01:21] [PASSED] drm_test_cmdline_name
[05:01:21] [PASSED] drm_test_cmdline_name_bpp
[05:01:21] [PASSED] drm_test_cmdline_name_option
[05:01:21] [PASSED] drm_test_cmdline_name_bpp_option
[05:01:21] [PASSED] drm_test_cmdline_rotate_0
[05:01:21] [PASSED] drm_test_cmdline_rotate_90
[05:01:21] [PASSED] drm_test_cmdline_rotate_180
[05:01:21] [PASSED] drm_test_cmdline_rotate_270
[05:01:21] [PASSED] drm_test_cmdline_hmirror
[05:01:21] [PASSED] drm_test_cmdline_vmirror
[05:01:21] [PASSED] drm_test_cmdline_margin_options
[05:01:21] [PASSED] drm_test_cmdline_multiple_options
[05:01:21] [PASSED] drm_test_cmdline_bpp_extra_and_option
[05:01:21] [PASSED] drm_test_cmdline_extra_and_option
[05:01:21] [PASSED] drm_test_cmdline_freestanding_options
[05:01:21] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[05:01:21] [PASSED] drm_test_cmdline_panel_orientation
[05:01:21] ================ drm_test_cmdline_invalid  =================
[05:01:21] [PASSED] margin_only
[05:01:21] [PASSED] interlace_only
[05:01:21] [PASSED] res_missing_x
[05:01:21] [PASSED] res_missing_y
[05:01:21] [PASSED] res_bad_y
[05:01:21] [PASSED] res_missing_y_bpp
[05:01:21] [PASSED] res_bad_bpp
[05:01:21] [PASSED] res_bad_refresh
[05:01:21] [PASSED] res_bpp_refresh_force_on_off
[05:01:21] [PASSED] res_invalid_mode
[05:01:21] [PASSED] res_bpp_wrong_place_mode
[05:01:21] [PASSED] name_bpp_refresh
[05:01:21] [PASSED] name_refresh
[05:01:21] [PASSED] name_refresh_wrong_mode
[05:01:21] [PASSED] name_refresh_invalid_mode
[05:01:21] [PASSED] rotate_multiple
[05:01:21] [PASSED] rotate_invalid_val
[05:01:21] [PASSED] rotate_truncated
[05:01:21] [PASSED] invalid_option
[05:01:21] [PASSED] invalid_tv_option
[05:01:21] [PASSED] truncated_tv_option
[05:01:21] ============ [PASSED] drm_test_cmdline_invalid =============
[05:01:21] =============== drm_test_cmdline_tv_options  ===============
[05:01:21] [PASSED] NTSC
[05:01:21] [PASSED] NTSC_443
[05:01:21] [PASSED] NTSC_J
[05:01:21] [PASSED] PAL
[05:01:21] [PASSED] PAL_M
[05:01:21] [PASSED] PAL_N
[05:01:21] [PASSED] SECAM
[05:01:21] [PASSED] MONO_525
[05:01:21] [PASSED] MONO_625
[05:01:21] =========== [PASSED] drm_test_cmdline_tv_options ===========
[05:01:21] =============== [PASSED] drm_cmdline_parser ================
[05:01:21] ========== drmm_connector_hdmi_init (20 subtests) ==========
[05:01:21] [PASSED] drm_test_connector_hdmi_init_valid
[05:01:21] [PASSED] drm_test_connector_hdmi_init_bpc_8
[05:01:21] [PASSED] drm_test_connector_hdmi_init_bpc_10
[05:01:21] [PASSED] drm_test_connector_hdmi_init_bpc_12
[05:01:21] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[05:01:21] [PASSED] drm_test_connector_hdmi_init_bpc_null
[05:01:21] [PASSED] drm_test_connector_hdmi_init_formats_empty
[05:01:21] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[05:01:21] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[05:01:21] [PASSED] supported_formats=0x9 yuv420_allowed=1
[05:01:21] [PASSED] supported_formats=0x9 yuv420_allowed=0
[05:01:21] [PASSED] supported_formats=0x5 yuv420_allowed=1
[05:01:21] [PASSED] supported_formats=0x5 yuv420_allowed=0
[05:01:21] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[05:01:21] [PASSED] drm_test_connector_hdmi_init_null_ddc
[05:01:21] [PASSED] drm_test_connector_hdmi_init_null_product
[05:01:21] [PASSED] drm_test_connector_hdmi_init_null_vendor
[05:01:21] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[05:01:21] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[05:01:21] [PASSED] drm_test_connector_hdmi_init_product_valid
[05:01:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[05:01:21] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[05:01:21] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[05:01:21] ========= drm_test_connector_hdmi_init_type_valid  =========
[05:01:21] [PASSED] HDMI-A
[05:01:21] [PASSED] HDMI-B
[05:01:21] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[05:01:21] ======== drm_test_connector_hdmi_init_type_invalid  ========
[05:01:21] [PASSED] Unknown
[05:01:21] [PASSED] VGA
[05:01:21] [PASSED] DVI-I
[05:01:21] [PASSED] DVI-D
[05:01:21] [PASSED] DVI-A
[05:01:21] [PASSED] Composite
[05:01:21] [PASSED] SVIDEO
[05:01:21] [PASSED] LVDS
[05:01:21] [PASSED] Component
[05:01:21] [PASSED] DIN
[05:01:21] [PASSED] DP
[05:01:21] [PASSED] TV
[05:01:21] [PASSED] eDP
[05:01:21] [PASSED] Virtual
[05:01:21] [PASSED] DSI
[05:01:21] [PASSED] DPI
[05:01:21] [PASSED] Writeback
[05:01:21] [PASSED] SPI
[05:01:21] [PASSED] USB
[05:01:21] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[05:01:21] ============ [PASSED] drmm_connector_hdmi_init =============
[05:01:21] ============= drmm_connector_init (3 subtests) =============
[05:01:21] [PASSED] drm_test_drmm_connector_init
[05:01:21] [PASSED] drm_test_drmm_connector_init_null_ddc
[05:01:21] ========= drm_test_drmm_connector_init_type_valid  =========
[05:01:21] [PASSED] Unknown
[05:01:21] [PASSED] VGA
[05:01:21] [PASSED] DVI-I
[05:01:21] [PASSED] DVI-D
[05:01:21] [PASSED] DVI-A
[05:01:21] [PASSED] Composite
[05:01:21] [PASSED] SVIDEO
[05:01:21] [PASSED] LVDS
[05:01:21] [PASSED] Component
[05:01:21] [PASSED] DIN
[05:01:21] [PASSED] DP
[05:01:21] [PASSED] HDMI-A
[05:01:21] [PASSED] HDMI-B
[05:01:21] [PASSED] TV
[05:01:21] [PASSED] eDP
[05:01:21] [PASSED] Virtual
[05:01:21] [PASSED] DSI
[05:01:21] [PASSED] DPI
[05:01:21] [PASSED] Writeback
[05:01:21] [PASSED] SPI
[05:01:21] [PASSED] USB
[05:01:21] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[05:01:21] =============== [PASSED] drmm_connector_init ===============
[05:01:21] ========= drm_connector_dynamic_init (6 subtests) ==========
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_init
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_init_properties
[05:01:21] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[05:01:21] [PASSED] Unknown
[05:01:21] [PASSED] VGA
[05:01:21] [PASSED] DVI-I
[05:01:21] [PASSED] DVI-D
[05:01:21] [PASSED] DVI-A
[05:01:21] [PASSED] Composite
[05:01:21] [PASSED] SVIDEO
[05:01:21] [PASSED] LVDS
[05:01:21] [PASSED] Component
[05:01:21] [PASSED] DIN
[05:01:21] [PASSED] DP
[05:01:21] [PASSED] HDMI-A
[05:01:21] [PASSED] HDMI-B
[05:01:21] [PASSED] TV
[05:01:21] [PASSED] eDP
[05:01:21] [PASSED] Virtual
[05:01:21] [PASSED] DSI
[05:01:21] [PASSED] DPI
[05:01:21] [PASSED] Writeback
[05:01:21] [PASSED] SPI
[05:01:21] [PASSED] USB
[05:01:21] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[05:01:21] ======== drm_test_drm_connector_dynamic_init_name  =========
[05:01:21] [PASSED] Unknown
[05:01:21] [PASSED] VGA
[05:01:21] [PASSED] DVI-I
[05:01:21] [PASSED] DVI-D
[05:01:21] [PASSED] DVI-A
[05:01:21] [PASSED] Composite
[05:01:21] [PASSED] SVIDEO
[05:01:21] [PASSED] LVDS
[05:01:21] [PASSED] Component
[05:01:21] [PASSED] DIN
[05:01:21] [PASSED] DP
[05:01:21] [PASSED] HDMI-A
[05:01:21] [PASSED] HDMI-B
[05:01:21] [PASSED] TV
[05:01:21] [PASSED] eDP
[05:01:21] [PASSED] Virtual
[05:01:21] [PASSED] DSI
[05:01:21] [PASSED] DPI
[05:01:21] [PASSED] Writeback
[05:01:21] [PASSED] SPI
[05:01:21] [PASSED] USB
[05:01:21] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[05:01:21] =========== [PASSED] drm_connector_dynamic_init ============
[05:01:21] ==== drm_connector_dynamic_register_early (4 subtests) =====
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[05:01:21] ====== [PASSED] drm_connector_dynamic_register_early =======
[05:01:21] ======= drm_connector_dynamic_register (7 subtests) ========
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[05:01:21] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[05:01:21] ========= [PASSED] drm_connector_dynamic_register ==========
[05:01:21] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[05:01:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[05:01:21] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[05:01:21] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[05:01:21] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[05:01:21] ========== drm_test_get_tv_mode_from_name_valid  ===========
[05:01:21] [PASSED] NTSC
[05:01:21] [PASSED] NTSC-443
[05:01:21] [PASSED] NTSC-J
[05:01:21] [PASSED] PAL
[05:01:21] [PASSED] PAL-M
[05:01:21] [PASSED] PAL-N
[05:01:21] [PASSED] SECAM
[05:01:21] [PASSED] Mono
[05:01:21] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[05:01:21] [PASSED] drm_test_get_tv_mode_from_name_truncated
[05:01:21] ============ [PASSED] drm_get_tv_mode_from_name ============
[05:01:21] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[05:01:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[05:01:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[05:01:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[05:01:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[05:01:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[05:01:21] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[05:01:21] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[05:01:21] [PASSED] VIC 96
[05:01:21] [PASSED] VIC 97
[05:01:21] [PASSED] VIC 101
[05:01:21] [PASSED] VIC 102
[05:01:21] [PASSED] VIC 106
[05:01:21] [PASSED] VIC 107
[05:01:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[05:01:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[05:01:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[05:01:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[05:01:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[05:01:21] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[05:01:21] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[05:01:21] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[05:01:21] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[05:01:21] [PASSED] Automatic
[05:01:21] [PASSED] Full
[05:01:21] [PASSED] Limited 16:235
[05:01:21] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[05:01:21] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[05:01:21] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[05:01:21] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[05:01:21] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[05:01:21] [PASSED] RGB
[05:01:21] [PASSED] YUV 4:2:0
[05:01:21] [PASSED] YUV 4:2:2
[05:01:21] [PASSED] YUV 4:4:4
[05:01:21] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[05:01:21] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[05:01:21] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[05:01:21] ============= drm_damage_helper (21 subtests) ==============
[05:01:21] [PASSED] drm_test_damage_iter_no_damage
[05:01:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[05:01:21] [PASSED] drm_test_damage_iter_no_damage_src_moved
[05:01:21] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[05:01:21] [PASSED] drm_test_damage_iter_no_damage_not_visible
[05:01:21] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[05:01:21] [PASSED] drm_test_damage_iter_no_damage_no_fb
[05:01:21] [PASSED] drm_test_damage_iter_simple_damage
[05:01:21] [PASSED] drm_test_damage_iter_single_damage
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_outside_src
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_src_moved
[05:01:21] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[05:01:21] [PASSED] drm_test_damage_iter_damage
[05:01:21] [PASSED] drm_test_damage_iter_damage_one_intersect
[05:01:21] [PASSED] drm_test_damage_iter_damage_one_outside
[05:01:21] [PASSED] drm_test_damage_iter_damage_src_moved
[05:01:21] [PASSED] drm_test_damage_iter_damage_not_visible
[05:01:21] ================ [PASSED] drm_damage_helper ================
[05:01:21] ============== drm_dp_mst_helper (3 subtests) ==============
[05:01:21] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[05:01:21] [PASSED] Clock 154000 BPP 30 DSC disabled
[05:01:21] [PASSED] Clock 234000 BPP 30 DSC disabled
[05:01:21] [PASSED] Clock 297000 BPP 24 DSC disabled
[05:01:21] [PASSED] Clock 332880 BPP 24 DSC enabled
[05:01:21] [PASSED] Clock 324540 BPP 24 DSC enabled
[05:01:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[05:01:21] ============== drm_test_dp_mst_calc_pbn_div  ===============
[05:01:21] [PASSED] Link rate 2000000 lane count 4
[05:01:21] [PASSED] Link rate 2000000 lane count 2
[05:01:21] [PASSED] Link rate 2000000 lane count 1
[05:01:21] [PASSED] Link rate 1350000 lane count 4
[05:01:21] [PASSED] Link rate 1350000 lane count 2
[05:01:21] [PASSED] Link rate 1350000 lane count 1
[05:01:21] [PASSED] Link rate 1000000 lane count 4
[05:01:21] [PASSED] Link rate 1000000 lane count 2
[05:01:21] [PASSED] Link rate 1000000 lane count 1
[05:01:21] [PASSED] Link rate 810000 lane count 4
[05:01:21] [PASSED] Link rate 810000 lane count 2
[05:01:21] [PASSED] Link rate 810000 lane count 1
[05:01:21] [PASSED] Link rate 540000 lane count 4
[05:01:21] [PASSED] Link rate 540000 lane count 2
[05:01:21] [PASSED] Link rate 540000 lane count 1
[05:01:21] [PASSED] Link rate 270000 lane count 4
[05:01:21] [PASSED] Link rate 270000 lane count 2
[05:01:21] [PASSED] Link rate 270000 lane count 1
[05:01:21] [PASSED] Link rate 162000 lane count 4
[05:01:21] [PASSED] Link rate 162000 lane count 2
[05:01:21] [PASSED] Link rate 162000 lane count 1
[05:01:21] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[05:01:21] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[05:01:21] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[05:01:21] [PASSED] DP_POWER_UP_PHY with port number
[05:01:21] [PASSED] DP_POWER_DOWN_PHY with port number
[05:01:21] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[05:01:21] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[05:01:21] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[05:01:21] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[05:01:21] [PASSED] DP_QUERY_PAYLOAD with port number
[05:01:21] [PASSED] DP_QUERY_PAYLOAD with VCPI
[05:01:21] [PASSED] DP_REMOTE_DPCD_READ with port number
[05:01:21] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[05:01:21] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[05:01:21] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[05:01:21] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[05:01:21] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[05:01:21] [PASSED] DP_REMOTE_I2C_READ with port number
[05:01:21] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[05:01:21] [PASSED] DP_REMOTE_I2C_READ with transactions array
[05:01:21] [PASSED] DP_REMOTE_I2C_WRITE with port number
[05:01:21] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[05:01:21] [PASSED] DP_REMOTE_I2C_WRITE with data array
[05:01:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[05:01:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[05:01:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[05:01:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[05:01:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[05:01:21] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[05:01:21] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[05:01:21] ================ [PASSED] drm_dp_mst_helper ================
[05:01:21] ================== drm_exec (7 subtests) ===================
[05:01:21] [PASSED] sanitycheck
[05:01:21] [PASSED] test_lock
[05:01:21] [PASSED] test_lock_unlock
[05:01:21] [PASSED] test_duplicates
[05:01:21] [PASSED] test_prepare
[05:01:21] [PASSED] test_prepare_array
[05:01:21] [PASSED] test_multiple_loops
[05:01:21] ==================== [PASSED] drm_exec =====================
[05:01:21] =========== drm_format_helper_test (17 subtests) ===========
[05:01:21] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[05:01:21] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[05:01:21] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[05:01:21] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[05:01:21] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[05:01:21] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[05:01:21] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[05:01:21] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[05:01:21] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[05:01:21] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[05:01:21] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[05:01:21] ============== drm_test_fb_xrgb8888_to_mono  ===============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[05:01:21] ==================== drm_test_fb_swab  =====================
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ================ [PASSED] drm_test_fb_swab =================
[05:01:21] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[05:01:21] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[05:01:21] [PASSED] single_pixel_source_buffer
[05:01:21] [PASSED] single_pixel_clip_rectangle
[05:01:21] [PASSED] well_known_colors
[05:01:21] [PASSED] destination_pitch
[05:01:21] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[05:01:21] ================= drm_test_fb_clip_offset  =================
[05:01:21] [PASSED] pass through
[05:01:21] [PASSED] horizontal offset
[05:01:21] [PASSED] vertical offset
[05:01:21] [PASSED] horizontal and vertical offset
[05:01:21] [PASSED] horizontal offset (custom pitch)
[05:01:21] [PASSED] vertical offset (custom pitch)
[05:01:21] [PASSED] horizontal and vertical offset (custom pitch)
[05:01:21] ============= [PASSED] drm_test_fb_clip_offset =============
[05:01:21] =================== drm_test_fb_memcpy  ====================
[05:01:21] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[05:01:21] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[05:01:21] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[05:01:21] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[05:01:21] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[05:01:21] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[05:01:21] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[05:01:21] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[05:01:21] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[05:01:21] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[05:01:21] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[05:01:21] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[05:01:21] =============== [PASSED] drm_test_fb_memcpy ================
[05:01:21] ============= [PASSED] drm_format_helper_test ==============
[05:01:21] ================= drm_format (18 subtests) =================
[05:01:21] [PASSED] drm_test_format_block_width_invalid
[05:01:21] [PASSED] drm_test_format_block_width_one_plane
[05:01:21] [PASSED] drm_test_format_block_width_two_plane
[05:01:21] [PASSED] drm_test_format_block_width_three_plane
[05:01:21] [PASSED] drm_test_format_block_width_tiled
[05:01:21] [PASSED] drm_test_format_block_height_invalid
[05:01:21] [PASSED] drm_test_format_block_height_one_plane
[05:01:21] [PASSED] drm_test_format_block_height_two_plane
[05:01:21] [PASSED] drm_test_format_block_height_three_plane
[05:01:21] [PASSED] drm_test_format_block_height_tiled
[05:01:21] [PASSED] drm_test_format_min_pitch_invalid
[05:01:21] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[05:01:21] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[05:01:21] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[05:01:21] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[05:01:21] [PASSED] drm_test_format_min_pitch_two_plane
[05:01:21] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[05:01:21] [PASSED] drm_test_format_min_pitch_tiled
[05:01:21] =================== [PASSED] drm_format ====================
[05:01:21] ============== drm_framebuffer (10 subtests) ===============
[05:01:21] ========== drm_test_framebuffer_check_src_coords  ==========
[05:01:21] [PASSED] Success: source fits into fb
[05:01:21] [PASSED] Fail: overflowing fb with x-axis coordinate
[05:01:21] [PASSED] Fail: overflowing fb with y-axis coordinate
[05:01:21] [PASSED] Fail: overflowing fb with source width
[05:01:21] [PASSED] Fail: overflowing fb with source height
[05:01:21] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[05:01:21] [PASSED] drm_test_framebuffer_cleanup
[05:01:21] =============== drm_test_framebuffer_create  ===============
[05:01:21] [PASSED] ABGR8888 normal sizes
[05:01:21] [PASSED] ABGR8888 max sizes
[05:01:21] [PASSED] ABGR8888 pitch greater than min required
[05:01:21] [PASSED] ABGR8888 pitch less than min required
[05:01:21] [PASSED] ABGR8888 Invalid width
[05:01:21] [PASSED] ABGR8888 Invalid buffer handle
[05:01:21] [PASSED] No pixel format
[05:01:21] [PASSED] ABGR8888 Width 0
[05:01:21] [PASSED] ABGR8888 Height 0
[05:01:21] [PASSED] ABGR8888 Out of bound height * pitch combination
[05:01:21] [PASSED] ABGR8888 Large buffer offset
[05:01:21] [PASSED] ABGR8888 Buffer offset for inexistent plane
[05:01:21] [PASSED] ABGR8888 Invalid flag
[05:01:21] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[05:01:21] [PASSED] ABGR8888 Valid buffer modifier
[05:01:21] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[05:01:21] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] NV12 Normal sizes
[05:01:21] [PASSED] NV12 Max sizes
[05:01:21] [PASSED] NV12 Invalid pitch
[05:01:21] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[05:01:21] [PASSED] NV12 different  modifier per-plane
[05:01:21] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[05:01:21] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] NV12 Modifier for inexistent plane
[05:01:21] [PASSED] NV12 Handle for inexistent plane
[05:01:21] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[05:01:21] [PASSED] YVU420 Normal sizes
[05:01:21] [PASSED] YVU420 Max sizes
[05:01:21] [PASSED] YVU420 Invalid pitch
[05:01:21] [PASSED] YVU420 Different pitches
[05:01:21] [PASSED] YVU420 Different buffer offsets/pitches
[05:01:21] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[05:01:21] [PASSED] YVU420 Valid modifier
[05:01:21] [PASSED] YVU420 Different modifiers per plane
[05:01:21] [PASSED] YVU420 Modifier for inexistent plane
[05:01:21] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[05:01:21] [PASSED] X0L2 Normal sizes
[05:01:21] [PASSED] X0L2 Max sizes
[05:01:21] [PASSED] X0L2 Invalid pitch
[05:01:21] [PASSED] X0L2 Pitch greater than minimum required
[05:01:21] [PASSED] X0L2 Handle for inexistent plane
[05:01:21] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[05:01:21] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[05:01:21] [PASSED] X0L2 Valid modifier
[05:01:21] [PASSED] X0L2 Modifier for inexistent plane
[05:01:21] =========== [PASSED] drm_test_framebuffer_create ===========
[05:01:21] [PASSED] drm_test_framebuffer_free
[05:01:21] [PASSED] drm_test_framebuffer_init
[05:01:21] [PASSED] drm_test_framebuffer_init_bad_format
[05:01:21] [PASSED] drm_test_framebuffer_init_dev_mismatch
[05:01:21] [PASSED] drm_test_framebuffer_lookup
[05:01:21] [PASSED] drm_test_framebuffer_lookup_inexistent
[05:01:21] [PASSED] drm_test_framebuffer_modifiers_not_supported
[05:01:21] ================= [PASSED] drm_framebuffer =================
[05:01:21] ================ drm_gem_shmem (8 subtests) ================
[05:01:21] [PASSED] drm_gem_shmem_test_obj_create
[05:01:21] [PASSED] drm_gem_shmem_test_obj_create_private
[05:01:21] [PASSED] drm_gem_shmem_test_pin_pages
[05:01:21] [PASSED] drm_gem_shmem_test_vmap
[05:01:21] [PASSED] drm_gem_shmem_test_get_sg_table
[05:01:21] [PASSED] drm_gem_shmem_test_get_pages_sgt
[05:01:21] [PASSED] drm_gem_shmem_test_madvise
[05:01:21] [PASSED] drm_gem_shmem_test_purge
[05:01:21] ================== [PASSED] drm_gem_shmem ==================
[05:01:21] === drm_atomic_helper_connector_hdmi_check (29 subtests) ===
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[05:01:21] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[05:01:21] [PASSED] Automatic
[05:01:21] [PASSED] Full
[05:01:21] [PASSED] Limited 16:235
[05:01:21] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[05:01:21] [PASSED] drm_test_check_disable_connector
[05:01:21] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[05:01:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[05:01:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[05:01:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[05:01:21] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[05:01:21] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[05:01:21] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[05:01:21] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[05:01:21] [PASSED] drm_test_check_output_bpc_dvi
[05:01:21] [PASSED] drm_test_check_output_bpc_format_vic_1
[05:01:21] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[05:01:21] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[05:01:21] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[05:01:21] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[05:01:21] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[05:01:21] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[05:01:21] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[05:01:21] ============ drm_test_check_hdmi_color_format  =============
[05:01:21] [PASSED] AUTO -> RGB
[05:01:21] [PASSED] YCBCR422 -> YUV422
[05:01:21] [PASSED] YCBCR420 -> YUV420
[05:01:21] [PASSED] YCBCR444 -> YUV444
[05:01:21] [PASSED] RGB -> RGB
[05:01:21] ======== [PASSED] drm_test_check_hdmi_color_format =========
[05:01:21] ======== drm_test_check_hdmi_color_format_420_only  ========
[05:01:21] [PASSED] RGB should fail
[05:01:21] [PASSED] YUV444 should fail
[05:01:21] [PASSED] YUV422 should fail
[05:01:21] [PASSED] YUV420 should work
[05:01:21] ==== [PASSED] drm_test_check_hdmi_color_format_420_only ====
[05:01:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[05:01:21] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[05:01:21] [PASSED] drm_test_check_broadcast_rgb_value
[05:01:21] [PASSED] drm_test_check_bpc_8_value
[05:01:21] [PASSED] drm_test_check_bpc_10_value
[05:01:21] [PASSED] drm_test_check_bpc_12_value
[05:01:21] [PASSED] drm_test_check_format_value
[05:01:21] [PASSED] drm_test_check_tmds_char_value
[05:01:21] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[05:01:21] = drm_atomic_helper_connector_hdmi_mode_valid (7 subtests) =
[05:01:21] [PASSED] drm_test_check_mode_valid
[05:01:21] [PASSED] drm_test_check_mode_valid_reject
[05:01:21] [PASSED] drm_test_check_mode_valid_reject_rate
[05:01:21] [PASSED] drm_test_check_mode_valid_reject_max_clock
[05:01:21] [PASSED] drm_test_check_mode_valid_yuv420_only_max_clock
[05:01:21] [PASSED] drm_test_check_mode_valid_reject_yuv420_only_connector
[05:01:21] [PASSED] drm_test_check_mode_valid_accept_yuv420_also_connector_rgb
[05:01:21] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[05:01:21] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[05:01:21] [PASSED] drm_test_check_infoframes
[05:01:21] [PASSED] drm_test_check_reject_avi_infoframe
[05:01:21] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[05:01:21] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[05:01:21] [PASSED] drm_test_check_reject_audio_infoframe
[05:01:21] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[05:01:21] ================= drm_managed (2 subtests) =================
[05:01:21] [PASSED] drm_test_managed_release_action
[05:01:21] [PASSED] drm_test_managed_run_action
[05:01:21] =================== [PASSED] drm_managed ===================
[05:01:21] =================== drm_mm (6 subtests) ====================
[05:01:21] [PASSED] drm_test_mm_init
[05:01:21] [PASSED] drm_test_mm_debug
[05:01:21] [PASSED] drm_test_mm_align32
[05:01:21] [PASSED] drm_test_mm_align64
[05:01:21] [PASSED] drm_test_mm_lowest
[05:01:21] [PASSED] drm_test_mm_highest
[05:01:21] ===================== [PASSED] drm_mm ======================
[05:01:21] ============= drm_modes_analog_tv (5 subtests) =============
[05:01:21] [PASSED] drm_test_modes_analog_tv_mono_576i
[05:01:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[05:01:21] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[05:01:21] [PASSED] drm_test_modes_analog_tv_pal_576i
[05:01:21] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[05:01:21] =============== [PASSED] drm_modes_analog_tv ===============
[05:01:21] ============== drm_panic_helper (3 subtests) ===============
[05:01:21] ============= drm_test_panic_screen_user_map  ==============
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[05:01:21] ========= [PASSED] drm_test_panic_screen_user_map ==========
[05:01:21] ============= drm_test_panic_screen_user_page  =============
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[05:01:21] ========= [PASSED] drm_test_panic_screen_user_page =========
[05:01:21] ========== drm_test_panic_screen_user_set_pixel  ===========
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 494 x 494 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[05:01:21] [PASSED] Panic screen user, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 494 x 494 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1920 x 1080 	XR24 little-endian (0x34325258)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG16 little-endian (0x36314752)
[05:01:21] [PASSED] Panic screen kmsg, mode: 1024 x 768 	RG24 little-endian (0x34324752)
[05:01:21] ====== [PASSED] drm_test_panic_screen_user_set_pixel =======
[05:01:21] ================ [PASSED] drm_panic_helper =================
[05:01:21] ============== drm_plane_helper (2 subtests) ===============
[05:01:21] =============== drm_test_check_plane_state  ================
[05:01:21] [PASSED] clipping_simple
[05:01:21] [PASSED] clipping_rotate_reflect
[05:01:21] [PASSED] positioning_simple
[05:01:21] [PASSED] upscaling
[05:01:21] [PASSED] downscaling
[05:01:21] [PASSED] rounding1
[05:01:21] [PASSED] rounding2
[05:01:21] [PASSED] rounding3
[05:01:21] [PASSED] rounding4
[05:01:21] =========== [PASSED] drm_test_check_plane_state ============
[05:01:21] =========== drm_test_check_invalid_plane_state  ============
[05:01:21] [PASSED] positioning_invalid
[05:01:21] [PASSED] upscaling_invalid
[05:01:21] [PASSED] downscaling_invalid
[05:01:21] ======= [PASSED] drm_test_check_invalid_plane_state ========
[05:01:21] ================ [PASSED] drm_plane_helper =================
[05:01:21] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[05:01:21] ====== drm_test_connector_helper_tv_get_modes_check  =======
[05:01:21] [PASSED] None
[05:01:21] [PASSED] PAL
[05:01:21] [PASSED] NTSC
[05:01:21] [PASSED] Both, NTSC Default
[05:01:21] [PASSED] Both, PAL Default
[05:01:21] [PASSED] Both, NTSC Default, with PAL on command-line
[05:01:21] [PASSED] Both, PAL Default, with NTSC on command-line
[05:01:21] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[05:01:21] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[05:01:21] ================== drm_rect (9 subtests) ===================
[05:01:21] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[05:01:21] [PASSED] drm_test_rect_clip_scaled_not_clipped
[05:01:21] [PASSED] drm_test_rect_clip_scaled_clipped
[05:01:21] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[05:01:21] ================= drm_test_rect_intersect  =================
[05:01:21] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[05:01:21] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[05:01:21] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[05:01:21] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[05:01:21] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[05:01:21] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[05:01:21] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[05:01:21] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[05:01:21] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[05:01:21] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[05:01:21] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[05:01:21] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[05:01:21] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[05:01:21] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[05:01:21] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[05:01:21] ============= [PASSED] drm_test_rect_intersect =============
[05:01:21] ================ drm_test_rect_calc_hscale  ================
[05:01:21] [PASSED] normal use
[05:01:21] [PASSED] out of max range
[05:01:21] [PASSED] out of min range
[05:01:21] [PASSED] zero dst
[05:01:21] [PASSED] negative src
[05:01:21] [PASSED] negative dst
[05:01:21] ============ [PASSED] drm_test_rect_calc_hscale ============
[05:01:21] ================ drm_test_rect_calc_vscale  ================
[05:01:21] [PASSED] normal use
[05:01:21] [PASSED] out of max range
[05:01:21] [PASSED] out of min range
[05:01:21] [PASSED] zero dst
[05:01:21] [PASSED] negative src
[05:01:21] [PASSED] negative dst
[05:01:21] ============ [PASSED] drm_test_rect_calc_vscale ============
[05:01:21] ================== drm_test_rect_rotate  ===================
[05:01:21] [PASSED] reflect-x
[05:01:21] [PASSED] reflect-y
[05:01:21] [PASSED] rotate-0
[05:01:21] [PASSED] rotate-90
[05:01:21] [PASSED] rotate-180
[05:01:21] [PASSED] rotate-270
[05:01:21] ============== [PASSED] drm_test_rect_rotate ===============
[05:01:21] ================ drm_test_rect_rotate_inv  =================
[05:01:21] [PASSED] reflect-x
[05:01:21] [PASSED] reflect-y
[05:01:21] [PASSED] rotate-0
[05:01:21] [PASSED] rotate-90
[05:01:21] [PASSED] rotate-180
[05:01:21] [PASSED] rotate-270
[05:01:21] ============ [PASSED] drm_test_rect_rotate_inv =============
[05:01:21] ==================== [PASSED] drm_rect =====================
[05:01:21] ============ drm_sysfb_modeset_test (1 subtest) ============
[05:01:21] ============ drm_test_sysfb_build_fourcc_list  =============
[05:01:21] [PASSED] no native formats
[05:01:21] [PASSED] XRGB8888 as native format
[05:01:21] [PASSED] remove duplicates
[05:01:21] [PASSED] convert alpha formats
[05:01:21] [PASSED] random formats
[05:01:21] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[05:01:21] ============= [PASSED] drm_sysfb_modeset_test ==============
[05:01:21] ================== drm_fixp (2 subtests) ===================
[05:01:21] [PASSED] drm_test_int2fixp
[05:01:21] [PASSED] drm_test_sm2fixp
[05:01:21] ==================== [PASSED] drm_fixp =====================
[05:01:21] ============================================================
[05:01:21] Testing complete. Ran 667 tests: passed: 667
[05:01:21] Elapsed time: 26.890s total, 1.823s configuring, 24.651s building, 0.410s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[05:01:21] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:01:23] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:01:33] Starting KUnit Kernel (1/1)...
[05:01:33] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:01:33] ================= ttm_device (5 subtests) ==================
[05:01:33] [PASSED] ttm_device_init_basic
[05:01:33] [PASSED] ttm_device_init_multiple
[05:01:33] [PASSED] ttm_device_fini_basic
[05:01:33] [PASSED] ttm_device_init_no_vma_man
[05:01:33] ================== ttm_device_init_pools  ==================
[05:01:33] [PASSED] No DMA allocations, no DMA32 required
[05:01:33] [PASSED] DMA allocations, DMA32 required
[05:01:33] [PASSED] No DMA allocations, DMA32 required
[05:01:33] [PASSED] DMA allocations, no DMA32 required
[05:01:33] ============== [PASSED] ttm_device_init_pools ==============
[05:01:33] =================== [PASSED] ttm_device ====================
[05:01:33] ================== ttm_pool (8 subtests) ===================
[05:01:33] ================== ttm_pool_alloc_basic  ===================
[05:01:33] [PASSED] One page
[05:01:33] [PASSED] More than one page
[05:01:33] [PASSED] Above the allocation limit
[05:01:33] [PASSED] One page, with coherent DMA mappings enabled
[05:01:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:01:33] ============== [PASSED] ttm_pool_alloc_basic ===============
[05:01:33] ============== ttm_pool_alloc_basic_dma_addr  ==============
[05:01:33] [PASSED] One page
[05:01:33] [PASSED] More than one page
[05:01:33] [PASSED] Above the allocation limit
[05:01:33] [PASSED] One page, with coherent DMA mappings enabled
[05:01:33] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[05:01:33] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[05:01:33] [PASSED] ttm_pool_alloc_order_caching_match
[05:01:33] [PASSED] ttm_pool_alloc_caching_mismatch
[05:01:33] [PASSED] ttm_pool_alloc_order_mismatch
[05:01:33] [PASSED] ttm_pool_free_dma_alloc
[05:01:33] [PASSED] ttm_pool_free_no_dma_alloc
[05:01:33] [PASSED] ttm_pool_fini_basic
[05:01:33] ==================== [PASSED] ttm_pool =====================
[05:01:33] ================ ttm_resource (8 subtests) =================
[05:01:33] ================= ttm_resource_init_basic  =================
[05:01:33] [PASSED] Init resource in TTM_PL_SYSTEM
[05:01:33] [PASSED] Init resource in TTM_PL_VRAM
[05:01:33] [PASSED] Init resource in a private placement
[05:01:33] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[05:01:33] ============= [PASSED] ttm_resource_init_basic =============
[05:01:33] [PASSED] ttm_resource_init_pinned
[05:01:33] [PASSED] ttm_resource_fini_basic
[05:01:33] [PASSED] ttm_resource_manager_init_basic
[05:01:33] [PASSED] ttm_resource_manager_usage_basic
[05:01:33] [PASSED] ttm_resource_manager_set_used_basic
[05:01:33] [PASSED] ttm_sys_man_alloc_basic
[05:01:33] [PASSED] ttm_sys_man_free_basic
[05:01:33] ================== [PASSED] ttm_resource ===================
[05:01:33] =================== ttm_tt (15 subtests) ===================
[05:01:33] ==================== ttm_tt_init_basic  ====================
[05:01:33] [PASSED] Page-aligned size
[05:01:33] [PASSED] Extra pages requested
[05:01:33] ================ [PASSED] ttm_tt_init_basic ================
[05:01:33] [PASSED] ttm_tt_init_misaligned
[05:01:33] [PASSED] ttm_tt_fini_basic
[05:01:33] [PASSED] ttm_tt_fini_sg
[05:01:33] [PASSED] ttm_tt_fini_shmem
[05:01:33] [PASSED] ttm_tt_create_basic
[05:01:33] [PASSED] ttm_tt_create_invalid_bo_type
[05:01:33] [PASSED] ttm_tt_create_ttm_exists
[05:01:33] [PASSED] ttm_tt_create_failed
[05:01:33] [PASSED] ttm_tt_destroy_basic
[05:01:33] [PASSED] ttm_tt_populate_null_ttm
[05:01:33] [PASSED] ttm_tt_populate_populated_ttm
[05:01:33] [PASSED] ttm_tt_unpopulate_basic
[05:01:33] [PASSED] ttm_tt_unpopulate_empty_ttm
[05:01:33] [PASSED] ttm_tt_swapin_basic
[05:01:33] ===================== [PASSED] ttm_tt ======================
[05:01:33] =================== ttm_bo (14 subtests) ===================
[05:01:33] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[05:01:33] [PASSED] Cannot be interrupted and sleeps
[05:01:33] [PASSED] Cannot be interrupted, locks straight away
[05:01:33] [PASSED] Can be interrupted, sleeps
[05:01:33] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[05:01:33] [PASSED] ttm_bo_reserve_locked_no_sleep
[05:01:33] [PASSED] ttm_bo_reserve_no_wait_ticket
[05:01:33] [PASSED] ttm_bo_reserve_double_resv
[05:01:33] [PASSED] ttm_bo_reserve_interrupted
[05:01:33] [PASSED] ttm_bo_reserve_deadlock
[05:01:33] [PASSED] ttm_bo_unreserve_basic
[05:01:33] [PASSED] ttm_bo_unreserve_pinned
[05:01:33] [PASSED] ttm_bo_unreserve_bulk
[05:01:33] [PASSED] ttm_bo_fini_basic
[05:01:33] [PASSED] ttm_bo_fini_shared_resv
[05:01:33] [PASSED] ttm_bo_pin_basic
[05:01:33] [PASSED] ttm_bo_pin_unpin_resource
[05:01:33] [PASSED] ttm_bo_multiple_pin_one_unpin
[05:01:33] ===================== [PASSED] ttm_bo ======================
[05:01:33] ============== ttm_bo_validate (22 subtests) ===============
[05:01:33] ============== ttm_bo_init_reserved_sys_man  ===============
[05:01:33] [PASSED] Buffer object for userspace
[05:01:33] [PASSED] Kernel buffer object
[05:01:33] [PASSED] Shared buffer object
[05:01:33] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[05:01:33] ============== ttm_bo_init_reserved_mock_man  ==============
[05:01:33] [PASSED] Buffer object for userspace
[05:01:33] [PASSED] Kernel buffer object
[05:01:33] [PASSED] Shared buffer object
[05:01:33] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[05:01:33] [PASSED] ttm_bo_init_reserved_resv
[05:01:33] ================== ttm_bo_validate_basic  ==================
[05:01:33] [PASSED] Buffer object for userspace
[05:01:33] [PASSED] Kernel buffer object
[05:01:33] [PASSED] Shared buffer object
[05:01:33] ============== [PASSED] ttm_bo_validate_basic ==============
[05:01:33] [PASSED] ttm_bo_validate_invalid_placement
[05:01:33] ============= ttm_bo_validate_same_placement  ==============
[05:01:33] [PASSED] System manager
[05:01:33] [PASSED] VRAM manager
[05:01:33] ========= [PASSED] ttm_bo_validate_same_placement ==========
[05:01:33] [PASSED] ttm_bo_validate_failed_alloc
[05:01:33] [PASSED] ttm_bo_validate_pinned
[05:01:33] [PASSED] ttm_bo_validate_busy_placement
[05:01:33] ================ ttm_bo_validate_multihop  =================
[05:01:33] [PASSED] Buffer object for userspace
[05:01:33] [PASSED] Kernel buffer object
[05:01:33] [PASSED] Shared buffer object
[05:01:33] ============ [PASSED] ttm_bo_validate_multihop =============
[05:01:33] ========== ttm_bo_validate_no_placement_signaled  ==========
[05:01:33] [PASSED] Buffer object in system domain, no page vector
[05:01:33] [PASSED] Buffer object in system domain with an existing page vector
[05:01:33] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[05:01:33] ======== ttm_bo_validate_no_placement_not_signaled  ========
[05:01:33] [PASSED] Buffer object for userspace
[05:01:33] [PASSED] Kernel buffer object
[05:01:33] [PASSED] Shared buffer object
[05:01:33] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[05:01:33] [PASSED] ttm_bo_validate_move_fence_signaled
[05:01:33] ========= ttm_bo_validate_move_fence_not_signaled  =========
[05:01:33] [PASSED] Waits for GPU
[05:01:33] [PASSED] Tries to lock straight away
[05:01:33] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[05:01:33] [PASSED] ttm_bo_validate_swapout
[05:01:33] [PASSED] ttm_bo_validate_happy_evict
[05:01:33] [PASSED] ttm_bo_validate_all_pinned_evict
[05:01:33] [PASSED] ttm_bo_validate_allowed_only_evict
[05:01:33] [PASSED] ttm_bo_validate_deleted_evict
[05:01:33] [PASSED] ttm_bo_validate_busy_domain_evict
[05:01:33] [PASSED] ttm_bo_validate_evict_gutting
[05:01:33] [PASSED] ttm_bo_validate_recrusive_evict
[05:01:33] ================= [PASSED] ttm_bo_validate =================
[05:01:33] ============================================================
[05:01:33] Testing complete. Ran 102 tests: passed: 102
[05:01:33] Elapsed time: 12.216s total, 1.859s configuring, 10.142s building, 0.185s running

+ for kcfg in "${kunitconfigs[@]}"
+ [[ ! -f /kernel/drivers/dma-buf/.kunitconfig ]]
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/dma-buf/.kunitconfig
[05:01:33] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[05:01:35] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[05:01:44] Starting KUnit Kernel (1/1)...
[05:01:44] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[05:01:44] =============== dma-buf-fence (12 subtests) ================
[05:01:44] [PASSED] test_sanitycheck
[05:01:44] [PASSED] test_signaling
[05:01:44] [PASSED] test_add_callback
[05:01:44] [PASSED] test_late_add_callback
[05:01:44] [PASSED] test_rm_callback
[05:01:44] [PASSED] test_late_rm_callback
[05:01:44] [PASSED] test_status
[05:01:44] [PASSED] test_error
[05:01:44] [PASSED] test_wait
[05:01:44] [PASSED] test_wait_timeout
[05:01:44] [PASSED] test_stub
[05:01:44] [SKIPPED] test_race_signal_callback (requires at least 2 CPUs)
[05:01:44] ================== [PASSED] dma-buf-fence ==================
[05:01:44] ============ dma-buf-fence-chain (11 subtests) =============
[05:01:44] [PASSED] test_sanitycheck
[05:01:44] [PASSED] test_find_seqno
[05:01:44] [PASSED] test_find_signaled
[05:01:44] [PASSED] test_find_out_of_order
[05:01:49] [PASSED] test_find_gap
[05:01:49] [PASSED] test_find_race
[05:01:49] [PASSED] test_signal_forward
[05:01:50] [PASSED] test_signal_backward
[05:01:50] [PASSED] test_wait_forward
[05:01:50] [PASSED] test_wait_backward
[05:01:50] [PASSED] test_wait_random
[05:01:50] =============== [PASSED] dma-buf-fence-chain ===============
[05:01:50] ============ dma-buf-fence-unwrap (10 subtests) ============
[05:01:50] [PASSED] test_sanitycheck
[05:01:50] [PASSED] test_unwrap_array
[05:01:50] [PASSED] test_unwrap_chain
[05:01:50] [PASSED] test_unwrap_chain_array
[05:01:50] [PASSED] test_unwrap_merge
[05:01:50] [PASSED] test_unwrap_merge_duplicate
[05:01:50] [PASSED] test_unwrap_merge_seqno
[05:01:50] [PASSED] test_unwrap_merge_order
[05:01:50] [PASSED] test_unwrap_merge_complex
[05:01:50] [PASSED] test_unwrap_merge_complex_seqno
[05:01:50] ============== [PASSED] dma-buf-fence-unwrap ===============
[05:01:50] ================ dma-buf-resv (5 subtests) =================
[05:01:50] [PASSED] test_sanitycheck
[05:01:50] ===================== test_signaling  ======================
[05:01:50] [PASSED] kernel
[05:01:50] [PASSED] write
[05:01:50] [PASSED] read
[05:01:50] [PASSED] bookkeep
[05:01:50] ================= [PASSED] test_signaling ==================
[05:01:50] ====================== test_for_each  ======================
[05:01:50] [PASSED] kernel
[05:01:50] [PASSED] write
[05:01:50] [PASSED] read
[05:01:50] [PASSED] bookkeep
[05:01:50] ================== [PASSED] test_for_each ==================
[05:01:50] ================= test_for_each_unlocked  ==================
[05:01:50] [PASSED] kernel
[05:01:50] [PASSED] write
[05:01:50] [PASSED] read
[05:01:50] [PASSED] bookkeep
[05:01:50] ============= [PASSED] test_for_each_unlocked ==============
[05:01:50] ===================== test_get_fences  =====================
[05:01:50] [PASSED] kernel
[05:01:50] [PASSED] write
[05:01:50] [PASSED] read
[05:01:50] [PASSED] bookkeep
[05:01:50] ================= [PASSED] test_get_fences =================
[05:01:50] ================== [PASSED] dma-buf-resv ===================
[05:01:50] ============================================================
[05:01:50] Testing complete. Ran 50 tests: passed: 49, skipped: 1
[05:01:50] Elapsed time: 16.097s total, 1.872s configuring, 8.853s building, 5.345s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for Enable HDMI FRL for MTL+ (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1418 bytes --]

== Series Details ==

Series: Enable HDMI FRL for MTL+ (rev2)
URL   : https://patchwork.freedesktop.org/series/171757/
State : success

== Summary ==

CI Bug Log - changes from xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431_BAT -> xe-pw-171757v2_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-171757v2_BAT that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-bmg-2:          [ABORT][1] ([Intel XE#9463]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/bat-bmg-2/igt@core_hotunplug@unbind-rebind.html

  
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463


Build changes
-------------

  * Linux: xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431 -> xe-pw-171757v2

  IGT_9138: 9138
  xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431: 0f28405022887336d4fc1fe1a0e1429146c2d431
  xe-pw-171757v2: 171757v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/index.html

[-- Attachment #2: Type: text/html, Size: 1983 bytes --]

✗ Xe.CI.FULL: failure for Enable HDMI FRL for MTL+ (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 81261 bytes --]

== Series Details ==

Series: Enable HDMI FRL for MTL+ (rev2)
URL   : https://patchwork.freedesktop.org/series/171757/
State : failure

== Summary ==

CI Bug Log - changes from xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431_FULL -> xe-pw-171757v2_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-171757v2_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-171757v2_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (3 -> 3)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-171757v2_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-race-nomemset:
    - shard-lnl:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-lnl-3/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-race-nomemset.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-2/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-race-nomemset.html

  
Known issues
------------

  Here are the changes found in xe-pw-171757v2_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-read:
    - shard-lnl:          NOTRUN -> [SKIP][3] ([Intel XE#1125] / [Intel XE#7312])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-ptl:          NOTRUN -> [SKIP][4] ([Intel XE#3157])
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-ptl:          [PASS][5] -> [FAIL][6] ([Intel XE#6078]) +1 other test fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-3/igt@kms_async_flips@alternate-sync-async-flip.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-7/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-d-edp-1:
    - shard-ptl:          [PASS][7] -> [ABORT][8] ([Intel XE#9375])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-7/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-edp-1.html
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-8/igt@kms_async_flips@async-flip-suspend-resume@pipe-d-edp-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#3658] / [Intel XE#7360])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-ptl:          NOTRUN -> [SKIP][10] ([Intel XE#6925])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-ptl:          NOTRUN -> [SKIP][11] ([Intel XE#5901])
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-2/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-ptl:          NOTRUN -> [SKIP][12] ([Intel XE#5808]) +8 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
    - shard-bmg:          NOTRUN -> [SKIP][13] ([Intel XE#2327]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-lnl:          NOTRUN -> [SKIP][14] ([Intel XE#1407]) +2 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-ptl:          NOTRUN -> [SKIP][15] ([Intel XE#5851])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#1477] / [Intel XE#7361])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#1124]) +6 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#1124])
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#7679])
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_bw@connected-linear-tiling-2-displays-target-2160x1440p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p:
    - shard-ptl:          NOTRUN -> [SKIP][20] ([Intel XE#7679]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p.html
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#7679])
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_bw@connected-linear-tiling-3-displays-target-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-target-3840x2160p:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#367])
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_bw@linear-tiling-3-displays-target-3840x2160p.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - shard-ptl:          NOTRUN -> [SKIP][23] ([Intel XE#5822]) +7 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-3/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-ptl:          NOTRUN -> [SKIP][24] ([Intel XE#5823] / [Intel XE#6918]) +4 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#2669] / [Intel XE#7389]) +7 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][26] ([Intel XE#2887]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [INCOMPLETE][27] ([Intel XE#7084] / [Intel XE#8150])
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][28] ([Intel XE#3432])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
    - shard-bmg:          NOTRUN -> [SKIP][29] ([Intel XE#3432])
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs:
    - shard-lnl:          NOTRUN -> [SKIP][30] ([Intel XE#2887]) +9 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][31] ([Intel XE#2652]) +3 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_chamelium_color@degamma:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#306] / [Intel XE#7358])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_color@gamma:
    - shard-ptl:          NOTRUN -> [SKIP][33] ([Intel XE#5824]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_chamelium_color@gamma.html
    - shard-bmg:          NOTRUN -> [SKIP][34] ([Intel XE#2325] / [Intel XE#7358])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lut1d:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#7358]) +3 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt601-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d:
    - shard-ptl:          NOTRUN -> [SKIP][36] ([Intel XE#8391]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-3/igt@kms_chamelium_color_pipeline@plane-fixed-matrix-yuv-rgb-bt709-lut1d.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-ptl:          NOTRUN -> [SKIP][37] ([Intel XE#2252]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-bmg:          NOTRUN -> [SKIP][38] ([Intel XE#2252]) +1 other test skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-lnl:          NOTRUN -> [SKIP][39] ([Intel XE#373]) +4 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-1:
    - shard-bmg:          NOTRUN -> [FAIL][40] ([Intel XE#3304] / [Intel XE#7374])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-7/igt@kms_content_protection@atomic-dpms@pipe-a-dp-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-bmg:          NOTRUN -> [SKIP][41] ([Intel XE#2390] / [Intel XE#6974])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_content_protection@dp-mst-type-1.html
    - shard-ptl:          NOTRUN -> [SKIP][42] ([Intel XE#5832] / [Intel XE#6974])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-ptl:          NOTRUN -> [SKIP][43] ([Intel XE#7642])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_content_protection@legacy-hdcp14.html
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#7642]) +2 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][45] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-2/igt@kms_content_protection@legacy-hdcp14@pipe-a-dp-2.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-ptl:          NOTRUN -> [SKIP][46] ([Intel XE#5846])
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
    - shard-bmg:          NOTRUN -> [SKIP][47] ([Intel XE#2321] / [Intel XE#7355])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-ptl:          NOTRUN -> [SKIP][48] ([Intel XE#5900])
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-256x85:
    - shard-lnl:          NOTRUN -> [SKIP][49] ([Intel XE#1424]) +3 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_cursor_crc@cursor-rapid-movement-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-bmg:          NOTRUN -> [SKIP][50] ([Intel XE#2320])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
    - shard-lnl:          NOTRUN -> [SKIP][51] ([Intel XE#309] / [Intel XE#7343]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-ptl:          NOTRUN -> [SKIP][52] ([Intel XE#5962]) +4 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_dp_link_training@uhbr-sst-tbtalt-train:
    - shard-lnl:          NOTRUN -> [SKIP][53] ([Intel XE#9537])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_dp_link_training@uhbr-sst-tbtalt-train.html

  * igt@kms_dsc@dsc-basic:
    - shard-ptl:          NOTRUN -> [SKIP][54] ([Intel XE#5907]) +1 other test skip
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-lnl:          NOTRUN -> [SKIP][55] ([Intel XE#8265]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_feature_discovery@display-4x:
    - shard-lnl:          NOTRUN -> [SKIP][56] ([Intel XE#1138] / [Intel XE#7344])
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dsc:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#8586])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_feature_discovery@dsc.html

  * igt@kms_feature_discovery@psr1:
    - shard-bmg:          NOTRUN -> [SKIP][58] ([Intel XE#2374] / [Intel XE#6127])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-ptl:          NOTRUN -> [SKIP][59] ([Intel XE#2316]) +1 other test skip
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
    - shard-lnl:          NOTRUN -> [SKIP][60] ([Intel XE#1421]) +4 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3:
    - shard-bmg:          [PASS][61] -> [FAIL][62] ([Intel XE#3149] / [Intel XE#3321]) +1 other test fail
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@d-hdmi-a3.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][63] ([Intel XE#301]) +1 other test fail
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip@flip-vs-expired-vblank@c-edp1:
    - shard-lnl:          NOTRUN -> [FAIL][64] ([Intel XE#301] / [Intel XE#3149]) +1 other test fail
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [PASS][65] -> [INCOMPLETE][66] ([Intel XE#2049] / [Intel XE#2597] / [Intel XE#8155]) +1 other test incomplete
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-6/igt@kms_flip@flip-vs-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-3/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-ptl:          NOTRUN -> [ABORT][67] ([Intel XE#9362]) +1 other test abort
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#7178] / [Intel XE#7351]) +3 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-ptl:          NOTRUN -> [SKIP][69] ([Intel XE#7178]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-bmg:          NOTRUN -> [SKIP][70] ([Intel XE#7178] / [Intel XE#7349])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-ptl:          NOTRUN -> [SKIP][71] ([Intel XE#5828]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][72] ([Intel XE#1397] / [Intel XE#1745] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#1397] / [Intel XE#7385] / [Intel XE#9144]) +1 other test skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
    - shard-bmg:          NOTRUN -> [SKIP][74] ([Intel XE#7178] / [Intel XE#7351])
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render:
    - shard-ptl:          NOTRUN -> [SKIP][75] ([Intel XE#5800] / [Intel XE#6312]) +5 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#6312] / [Intel XE#651]) +6 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][77] ([Intel XE#7061] / [Intel XE#7356]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_frontbuffer_tracking@drrs-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt:
    - shard-ptl:          NOTRUN -> [SKIP][78] ([Intel XE#6312]) +7 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt.html
    - shard-lnl:          NOTRUN -> [SKIP][79] ([Intel XE#6312]) +8 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_frontbuffer_tracking@drrshdr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#7905]) +34 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_frontbuffer_tracking@drrshdr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@drrshdr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-bmg:          NOTRUN -> [SKIP][81] ([Intel XE#2311]) +9 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_frontbuffer_tracking@drrshdr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt:
    - shard-lnl:          NOTRUN -> [SKIP][82] ([Intel XE#656] / [Intel XE#7905]) +29 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          NOTRUN -> [SKIP][83] ([Intel XE#4141]) +2 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#1469] / [Intel XE#7399])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][86] ([Intel XE#7061] / [Intel XE#7356]) +2 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrs-argb161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc:
    - shard-bmg:          NOTRUN -> [SKIP][87] ([Intel XE#7061]) +2 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc.html
    - shard-ptl:          NOTRUN -> [SKIP][88] ([Intel XE#7061]) +4 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_frontbuffer_tracking@fbcdrrshdr-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff:
    - shard-ptl:          NOTRUN -> [SKIP][89] ([Intel XE#5812]) +55 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt:
    - shard-bmg:          NOTRUN -> [SKIP][90] ([Intel XE#2313]) +10 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-ptl:          NOTRUN -> [SKIP][91] ([Intel XE#5865] / [Intel XE#7399])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-modesetfrombusy:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#7865]) +23 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-wc:
    - shard-ptl:          NOTRUN -> [SKIP][93] ([Intel XE#7865]) +17 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-mmap-wc:
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#7061]) +3 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_frontbuffer_tracking@hdr-argb161616f-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#3374] / [Intel XE#3544])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-ptl:          NOTRUN -> [SKIP][96] ([Intel XE#5917] / [Intel XE#6174])
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_hdr@static-toggle.html
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#1503])
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][98] ([Intel XE#6900])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-3/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-ptl:          NOTRUN -> [SKIP][99] ([Intel XE#6901])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-2/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][100] ([Intel XE#7173] / [Intel XE#7294])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
    - shard-lnl:          NOTRUN -> [SKIP][101] ([Intel XE#7283])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-bmg:          NOTRUN -> [SKIP][102] ([Intel XE#7283])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html
    - shard-ptl:          NOTRUN -> [SKIP][103] ([Intel XE#7283])
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-bmg:          [PASS][104] -> [ABORT][105] ([Intel XE#9422]) +1 other test abort
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-9/igt@kms_plane@plane-panning-bottom-right-suspend.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-7/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_cursor@viewport:
    - shard-bmg:          [PASS][106] -> [DMESG-FAIL][107] ([Intel XE#7774]) +1 other test dmesg-fail
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_plane_cursor@viewport.html
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_plane_cursor@viewport.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-ptl:          NOTRUN -> [SKIP][108] ([Intel XE#4596] / [Intel XE#5854])
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-lnl:          NOTRUN -> [SKIP][109] ([Intel XE#3309] / [Intel XE#7368])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@deep-pkgc:
    - shard-lnl:          [PASS][110] -> [FAIL][111] ([Intel XE#2029] / [Intel XE#7395])
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-lnl-3/igt@kms_pm_dc@deep-pkgc.html
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-2/igt@kms_pm_dc@deep-pkgc.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-lnl:          NOTRUN -> [SKIP][112] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-ptl:          NOTRUN -> [SKIP][113] ([Intel XE#7304]) +2 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-2/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
    - shard-bmg:          NOTRUN -> [SKIP][114] ([Intel XE#1489]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#2893] / [Intel XE#4608] / [Intel XE#7304])
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#4608])
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][117] ([Intel XE#4608] / [Intel XE#7304])
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-plane-move-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][118] ([Intel XE#2893] / [Intel XE#7304]) +3 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr2_sf@pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#1128] / [Intel XE#7413])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#1406] / [Intel XE#7345])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr@fbc-psr2-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][121] ([Intel XE#1406] / [Intel XE#4609] / [Intel XE#7345])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr@fbc-psr2-cursor-plane-move@edp-1.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-bmg:          NOTRUN -> [SKIP][122] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@pr-no-drrs:
    - shard-ptl:          NOTRUN -> [SKIP][123] ([Intel XE#1406]) +1 other test skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@kms_psr@pr-no-drrs.html

  * igt@kms_psr@pr-sprite-blt:
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#1406]) +2 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_psr@pr-sprite-blt.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#3414] / [Intel XE#3904] / [Intel XE#7342]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-ptl:          NOTRUN -> [SKIP][126] ([Intel XE#5813])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-lnl:          NOTRUN -> [SKIP][127] ([Intel XE#1127] / [Intel XE#5813]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-90:
    - shard-ptl:          NOTRUN -> [SKIP][128] ([Intel XE#5821]) +2 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-3/igt@kms_rotation_crc@primary-y-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-bmg:          NOTRUN -> [SKIP][129] ([Intel XE#2413])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-ptl:          NOTRUN -> [SKIP][130] ([Intel XE#5910])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-lnl:          NOTRUN -> [SKIP][131] ([Intel XE#1435] / [Intel XE#9142]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-bmg:          NOTRUN -> [SKIP][132] ([Intel XE#2426] / [Intel XE#5848])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#330] / [Intel XE#5857])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vrr@cmrr-desktop-mode:
    - shard-lnl:          NOTRUN -> [SKIP][134] ([Intel XE#9271]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@kms_vrr@cmrr-desktop-mode.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-ptl:          [PASS][135] -> [FAIL][136] ([Intel XE#4227] / [Intel XE#7397]) +4 other tests fail
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-7/igt@kms_vrr@flip-basic-fastset.html
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-8/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1:
    - shard-ptl:          [PASS][137] -> [FAIL][138] ([Intel XE#6293] / [Intel XE#7397])
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-7/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-8/igt@kms_vrr@flip-basic-fastset@pipe-a-edp-1.html

  * igt@xe_compute@ccs-mode-basic:
    - shard-lnl:          NOTRUN -> [SKIP][139] ([Intel XE#1447] / [Intel XE#7471])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_compute@ccs-mode-basic.html

  * igt@xe_create@create-big-vram:
    - shard-ptl:          NOTRUN -> [SKIP][140] ([Intel XE#5853] / [Intel XE#7457])
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@xe_create@create-big-vram.html

  * igt@xe_evict@evict-beng-threads-small:
    - shard-lnl:          NOTRUN -> [SKIP][141] ([Intel XE#6540] / [Intel XE#688]) +7 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_evict@evict-beng-threads-small.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-bmg:          [PASS][142] -> [INCOMPLETE][143] ([Intel XE#6321] / [Intel XE#8355])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-3/igt@xe_evict@evict-mixed-many-threads-small.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-6/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-threads-small-multi-vm:
    - shard-ptl:          NOTRUN -> [SKIP][144] ([Intel XE#5764]) +6 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_evict@evict-threads-small-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd:
    - shard-ptl:          NOTRUN -> [SKIP][145] ([Intel XE#6144])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_evict_ccs@evict-overcommit-standalone-instantfree-samefd.html

  * igt@xe_exec_balancer@many-parallel-userptr-invalidate-race:
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#7482]) +13 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_exec_balancer@many-parallel-userptr-invalidate-race.html

  * igt@xe_exec_balancer@no-exec-parallel-userptr-rebind:
    - shard-ptl:          NOTRUN -> [SKIP][147] ([Intel XE#7482]) +11 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_exec_balancer@no-exec-parallel-userptr-rebind.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr:
    - shard-lnl:          NOTRUN -> [SKIP][148] ([Intel XE#1392]) +5 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race:
    - shard-bmg:          NOTRUN -> [SKIP][149] ([Intel XE#2322] / [Intel XE#7372]) +1 other test skip
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-userptr-invalidate-race.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race:
    - shard-ptl:          NOTRUN -> [SKIP][150] ([Intel XE#5575] / [Intel XE#7484]) +5 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@xe_exec_basic@multigpu-once-bindexecqueue-userptr-invalidate-race.html

  * igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch:
    - shard-lnl:          NOTRUN -> [SKIP][151] ([Intel XE#8374]) +7 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_exec_fault_mode@many-multi-queue-userptr-prefetch.html

  * igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race:
    - shard-ptl:          NOTRUN -> [SKIP][152] ([Intel XE#8374]) +7 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html
    - shard-bmg:          NOTRUN -> [SKIP][153] ([Intel XE#8374])
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race.html

  * igt@xe_exec_multi_queue@one-queue-basic:
    - shard-ptl:          NOTRUN -> [SKIP][154] ([Intel XE#8364]) +20 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_exec_multi_queue@one-queue-basic.html

  * igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate:
    - shard-lnl:          NOTRUN -> [SKIP][155] ([Intel XE#8364]) +20 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_exec_multi_queue@one-queue-preempt-mode-fault-userptr-invalidate.html

  * igt@xe_exec_multi_queue@two-queues-close-fd:
    - shard-bmg:          NOTRUN -> [SKIP][156] ([Intel XE#8364]) +6 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_exec_multi_queue@two-queues-close-fd.html

  * igt@xe_exec_reset@cm-multi-queue-cat-error:
    - shard-lnl:          NOTRUN -> [SKIP][157] ([Intel XE#8369])
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_exec_reset@cm-multi-queue-cat-error.html

  * igt@xe_exec_system_allocator@threads-many-stride-mmap-huge-nomemset:
    - shard-lnl:          [PASS][158] -> [FAIL][159] ([Intel XE#8058] / [Intel XE#9570])
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-lnl-4/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge-nomemset.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-5/igt@xe_exec_system_allocator@threads-many-stride-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-new-prefetch:
    - shard-bmg:          [PASS][160] -> [SKIP][161] ([Intel XE#8589]) +60 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@xe_exec_system_allocator@threads-shared-vm-many-new-prefetch.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@xe_exec_system_allocator@threads-shared-vm-many-new-prefetch.html

  * igt@xe_exec_threads@threads-hang-userptr-invalidate-race:
    - shard-bmg:          [PASS][162] -> [FAIL][163] ([Intel XE#9096])
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-1/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-4/igt@xe_exec_threads@threads-hang-userptr-invalidate-race.html

  * igt@xe_exec_threads@threads-multi-queue-fd-userptr:
    - shard-ptl:          NOTRUN -> [SKIP][164] ([Intel XE#8378]) +5 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-1/igt@xe_exec_threads@threads-multi-queue-fd-userptr.html

  * igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-invalidate:
    - shard-bmg:          NOTRUN -> [SKIP][165] ([Intel XE#8378]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_exec_threads@threads-multi-queue-mixed-shared-vm-userptr-invalidate.html

  * igt@xe_exec_threads@threads-multi-queue-userptr-rebind:
    - shard-lnl:          NOTRUN -> [SKIP][166] ([Intel XE#8378]) +6 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_exec_threads@threads-multi-queue-userptr-rebind.html

  * igt@xe_fault_injection@exec-queue-create-fail-xe_hw_engine_group_add_exec_queue:
    - shard-bmg:          [PASS][167] -> [ABORT][168] ([Intel XE#9463])
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-10/igt@xe_fault_injection@exec-queue-create-fail-xe_hw_engine_group_add_exec_queue.html
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-4/igt@xe_fault_injection@exec-queue-create-fail-xe_hw_engine_group_add_exec_queue.html

  * igt@xe_media_fill@media-fill:
    - shard-lnl:          NOTRUN -> [SKIP][169] ([Intel XE#560] / [Intel XE#7321] / [Intel XE#7453])
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_media_fill@media-fill.html

  * igt@xe_mmap@vram:
    - shard-lnl:          NOTRUN -> [SKIP][170] ([Intel XE#1416])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_mmap@vram.html

  * igt@xe_multigpu_svm@mgpu-coherency-fail-basic:
    - shard-lnl:          NOTRUN -> [SKIP][171] ([Intel XE#6964]) +2 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_multigpu_svm@mgpu-coherency-fail-basic.html

  * igt@xe_multigpu_svm@mgpu-latency-basic:
    - shard-bmg:          NOTRUN -> [SKIP][172] ([Intel XE#6964])
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_multigpu_svm@mgpu-latency-basic.html
    - shard-ptl:          NOTRUN -> [SKIP][173] ([Intel XE#6964]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_multigpu_svm@mgpu-latency-basic.html

  * igt@xe_page_reclaim@boundary-split:
    - shard-lnl:          NOTRUN -> [SKIP][174] ([Intel XE#7793])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_page_reclaim@boundary-split.html

  * igt@xe_peer2peer@write:
    - shard-lnl:          NOTRUN -> [SKIP][175] ([Intel XE#1061] / [Intel XE#7326] / [Intel XE#7353])
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_peer2peer@write.html

  * igt@xe_pm@d3cold-i2c:
    - shard-ptl:          NOTRUN -> [SKIP][176] ([Intel XE#5741]) +1 other test skip
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-3/igt@xe_pm@d3cold-i2c.html

  * igt@xe_pm@d3cold-mmap-system:
    - shard-bmg:          NOTRUN -> [SKIP][177] ([Intel XE#2284] / [Intel XE#7370])
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_pm@d3cold-mmap-system.html

  * igt@xe_pm@s3-multiple-execs:
    - shard-lnl:          NOTRUN -> [SKIP][178] ([Intel XE#584] / [Intel XE#7369]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_pm@s3-multiple-execs.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [PASS][179] -> [ABORT][180] ([Intel XE#9362]) +1 other test abort
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-lnl-2/igt@xe_pm@s4-mocs.html
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@xe_pm@s4-mocs.html

  * igt@xe_pmu@all-fn-engine-activity-load:
    - shard-lnl:          NOTRUN -> [SKIP][181] ([Intel XE#4650] / [Intel XE#7347])
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_pmu@all-fn-engine-activity-load.html

  * igt@xe_pmu@engine-activity-suspend:
    - shard-ptl:          [PASS][182] -> [ABORT][183] ([Intel XE#9362]) +4 other tests abort
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-2/igt@xe_pmu@engine-activity-suspend.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-7/igt@xe_pmu@engine-activity-suspend.html

  * igt@xe_prefetch_fault@prefetch-fault-svm:
    - shard-bmg:          NOTRUN -> [SKIP][184] ([Intel XE#7599])
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_prefetch_fault@prefetch-fault-svm.html
    - shard-ptl:          NOTRUN -> [SKIP][185] ([Intel XE#7599])
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_prefetch_fault@prefetch-fault-svm.html

  * igt@xe_query@multigpu-query-hwconfig:
    - shard-lnl:          NOTRUN -> [SKIP][186] ([Intel XE#944])
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@xe_query@multigpu-query-hwconfig.html

  * igt@xe_query@multigpu-query-topology:
    - shard-ptl:          NOTRUN -> [SKIP][187] ([Intel XE#6019]) +1 other test skip
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-6/igt@xe_query@multigpu-query-topology.html
    - shard-bmg:          NOTRUN -> [SKIP][188] ([Intel XE#944])
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_query@multigpu-query-topology.html

  * igt@xe_sriov_admin@sched-priority-vf-write-denied:
    - shard-lnl:          NOTRUN -> [SKIP][189] ([Intel XE#7174]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@xe_sriov_admin@sched-priority-vf-write-denied.html

  * igt@xe_sriov_scheduling@default-enabled-fair-scheduling:
    - shard-lnl:          NOTRUN -> [SKIP][190] ([Intel XE#8339])
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_sriov_scheduling@default-enabled-fair-scheduling.html

  * igt@xe_sriov_vram@vf-access-beyond:
    - shard-lnl:          NOTRUN -> [SKIP][191] ([Intel XE#6376] / [Intel XE#7330] / [Intel XE#7422])
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_sriov_vram@vf-access-beyond.html

  * igt@xe_vm@overcommit-nonfault-vram-lr-defer:
    - shard-lnl:          NOTRUN -> [SKIP][192] ([Intel XE#7892])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_vm@overcommit-nonfault-vram-lr-defer.html

  * igt@xe_wedged@basic-wedged:
    - shard-lnl:          NOTRUN -> [DMESG-WARN][193] ([Intel XE#8963])
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-3/igt@xe_wedged@basic-wedged.html

  
#### Possible fixes ####

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-bmg:          [FAIL][194] ([Intel XE#3718] / [Intel XE#6078]) -> [PASS][195] +2 other tests pass
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-3/igt@kms_async_flips@alternate-sync-async-flip.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-6/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2:
    - shard-bmg:          [FAIL][196] ([Intel XE#6078]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-9/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-8/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-dp-2.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-edp-1:
    - shard-ptl:          [ABORT][198] ([Intel XE#9362]) -> [PASS][199] +7 other tests pass
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-7/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-edp-1.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-8/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-edp-1.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-bmg:          [FAIL][200] ([Intel XE#8098] / [Intel XE#9561]) -> [PASS][201] +1 other test pass
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-8/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-10/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [FAIL][202] ([Intel XE#7809]) -> [PASS][203]
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-bmg:          [INCOMPLETE][204] ([Intel XE#6321] / [Intel XE#8355]) -> [PASS][205]
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-1/igt@xe_evict@evict-beng-mixed-many-threads-small.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  * igt@xe_fault_injection@inject-fault-probe-function-xe_device_probe_early:
    - shard-bmg:          [ABORT][206] ([Intel XE#9463]) -> [PASS][207]
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-4/igt@xe_fault_injection@inject-fault-probe-function-xe_device_probe_early.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-9/igt@xe_fault_injection@inject-fault-probe-function-xe_device_probe_early.html

  * igt@xe_pm@s4-vm-bind-userptr:
    - shard-lnl:          [ABORT][208] ([Intel XE#9362]) -> [PASS][209]
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-lnl-7/igt@xe_pm@s4-vm-bind-userptr.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-4/igt@xe_pm@s4-vm-bind-userptr.html

  
#### Warnings ####

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-ptl:          [ABORT][210] ([Intel XE#9362]) -> [ABORT][211] ([Intel XE#9375])
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-7/igt@kms_async_flips@async-flip-suspend-resume.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-8/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-bmg:          [SKIP][212] ([Intel XE#1124]) -> [SKIP][213] ([Intel XE#8589])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs:
    - shard-bmg:          [SKIP][214] ([Intel XE#2887]) -> [SKIP][215] ([Intel XE#8589]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_edid@dp-edid-resolution-list:
    - shard-bmg:          [SKIP][216] ([Intel XE#2252]) -> [SKIP][217] ([Intel XE#8589]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_chamelium_edid@dp-edid-resolution-list.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_chamelium_edid@dp-edid-resolution-list.html

  * igt@kms_content_protection@lic-type-0:
    - shard-bmg:          [FAIL][218] ([Intel XE#1178] / [Intel XE#3304] / [Intel XE#7374]) -> [SKIP][219] ([Intel XE#8589])
   [218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_content_protection@lic-type-0.html
   [219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-random-64x21:
    - shard-bmg:          [SKIP][220] ([Intel XE#2320]) -> [SKIP][221] ([Intel XE#8589])
   [220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_cursor_crc@cursor-random-64x21.html
   [221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_cursor_crc@cursor-random-64x21.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
    - shard-lnl:          [SKIP][222] ([Intel XE#309] / [Intel XE#7343]) -> [SKIP][223] ([Intel XE#309] / [Intel XE#7343] / [Intel XE#7935])
   [222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-lnl-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
   [223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-lnl-8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-bmg:          [SKIP][224] ([Intel XE#7178] / [Intel XE#7351]) -> [SKIP][225] ([Intel XE#8589])
   [224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
   [225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][226] ([Intel XE#2311]) -> [SKIP][227] ([Intel XE#8589]) +6 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html
   [227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][228] ([Intel XE#4141]) -> [SKIP][229] ([Intel XE#8589])
   [228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
   [229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc:
    - shard-bmg:          [SKIP][230] ([Intel XE#7061] / [Intel XE#7356]) -> [SKIP][231] ([Intel XE#8589])
   [230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc.html
   [231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcdrrs-abgr161616f-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render:
    - shard-bmg:          [SKIP][232] ([Intel XE#7061]) -> [SKIP][233] ([Intel XE#8589])
   [232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html
   [233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbchdr-abgr161616f-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][234] ([Intel XE#2313]) -> [SKIP][235] ([Intel XE#8589]) +8 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html
   [235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][236] ([Intel XE#3544]) -> [SKIP][237] ([Intel XE#3374] / [Intel XE#3544])
   [236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-5/igt@kms_hdr@brightness-with-hdr.html
   [237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping:
    - shard-bmg:          [SKIP][238] ([Intel XE#7283]) -> [SKIP][239] ([Intel XE#8589])
   [238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping.html
   [239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5:
    - shard-bmg:          [SKIP][240] ([Intel XE#2763] / [Intel XE#6886]) -> [SKIP][241] ([Intel XE#8589])
   [240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_plane_scaling@planes-downscale-factor-0-5.html
   [241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_plane_scaling@planes-downscale-factor-0-5.html

  * igt@kms_psr@fbc-pr-sprite-blt:
    - shard-bmg:          [SKIP][242] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][243] ([Intel XE#8589]) +2 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@kms_psr@fbc-pr-sprite-blt.html
   [243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@kms_psr@fbc-pr-sprite-blt.html

  * igt@xe_exec_basic@multigpu-no-exec-userptr:
    - shard-bmg:          [SKIP][244] ([Intel XE#2322] / [Intel XE#7372]) -> [SKIP][245] ([Intel XE#8589])
   [244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@xe_exec_basic@multigpu-no-exec-userptr.html
   [245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@xe_exec_basic@multigpu-no-exec-userptr.html

  * igt@xe_exec_fault_mode@once-multi-queue:
    - shard-bmg:          [SKIP][246] ([Intel XE#8374]) -> [SKIP][247] ([Intel XE#8589])
   [246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@xe_exec_fault_mode@once-multi-queue.html
   [247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@xe_exec_fault_mode@once-multi-queue.html

  * igt@xe_exec_multi_queue@many-queues-preempt-mode-basic:
    - shard-bmg:          [SKIP][248] ([Intel XE#8364]) -> [SKIP][249] ([Intel XE#8589]) +2 other tests skip
   [248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@xe_exec_multi_queue@many-queues-preempt-mode-basic.html
   [249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@xe_exec_multi_queue@many-queues-preempt-mode-basic.html

  * igt@xe_exec_reset@cm-multi-queue-close-fd:
    - shard-bmg:          [SKIP][250] ([Intel XE#8369]) -> [SKIP][251] ([Intel XE#8589])
   [250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@xe_exec_reset@cm-multi-queue-close-fd.html
   [251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@xe_exec_reset@cm-multi-queue-close-fd.html

  * igt@xe_pat@pat-sw-hw-suspend:
    - shard-ptl:          [FAIL][252] ([Intel XE#7695]) -> [ABORT][253] ([Intel XE#9362])
   [252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-8/igt@xe_pat@pat-sw-hw-suspend.html
   [253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-7/igt@xe_pat@pat-sw-hw-suspend.html

  * igt@xe_pm@s4-mocs:
    - shard-ptl:          [DMESG-WARN][254] ([Intel XE#7727]) -> [ABORT][255] ([Intel XE#9362])
   [254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-ptl-1/igt@xe_pm@s4-mocs.html
   [255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-ptl-5/igt@xe_pm@s4-mocs.html

  * igt@xe_query@multigpu-query-oa-units:
    - shard-bmg:          [SKIP][256] ([Intel XE#944]) -> [SKIP][257] ([Intel XE#8589])
   [256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431/shard-bmg-2/igt@xe_query@multigpu-query-oa-units.html
   [257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/shard-bmg-5/igt@xe_query@multigpu-query-oa-units.html

  
  [Intel XE#1061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1061
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1416
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
  [Intel XE#1447]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1447
  [Intel XE#1469]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1469
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#2029]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2029
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
  [Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
  [Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
  [Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
  [Intel XE#2374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2374
  [Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
  [Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
  [Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
  [Intel XE#3157]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3157
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3304
  [Intel XE#3309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3309
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3658]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3658
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#3718]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3718
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4227]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4227
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4609]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4609
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#560]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/560
  [Intel XE#5741]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5741
  [Intel XE#5764]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5764
  [Intel XE#5800]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5800
  [Intel XE#5808]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5808
  [Intel XE#5812]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5812
  [Intel XE#5813]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5813
  [Intel XE#5821]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5821
  [Intel XE#5822]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5822
  [Intel XE#5823]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5823
  [Intel XE#5824]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5824
  [Intel XE#5828]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5828
  [Intel XE#5832]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5832
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#5846]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5846
  [Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
  [Intel XE#5851]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5851
  [Intel XE#5853]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5853
  [Intel XE#5854]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5854
  [Intel XE#5857]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5857
  [Intel XE#5865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5865
  [Intel XE#5900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5900
  [Intel XE#5901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5901
  [Intel XE#5907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5907
  [Intel XE#5910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5910
  [Intel XE#5917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5917
  [Intel XE#5962]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5962
  [Intel XE#6019]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6019
  [Intel XE#6078]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6078
  [Intel XE#6127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6127
  [Intel XE#6144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6144
  [Intel XE#6174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6174
  [Intel XE#6293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6293
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
  [Intel XE#6376]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6376
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#6540]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6540
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
  [Intel XE#6900]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6900
  [Intel XE#6901]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6901
  [Intel XE#6918]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6918
  [Intel XE#6925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6925
  [Intel XE#6964]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6964
  [Intel XE#6974]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6974
  [Intel XE#7061]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7061
  [Intel XE#7084]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7084
  [Intel XE#7173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7173
  [Intel XE#7174]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7174
  [Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
  [Intel XE#7283]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7283
  [Intel XE#7294]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7294
  [Intel XE#7304]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7304
  [Intel XE#7312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7312
  [Intel XE#7321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7321
  [Intel XE#7326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7326
  [Intel XE#7330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7330
  [Intel XE#7342]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7342
  [Intel XE#7343]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7343
  [Intel XE#7344]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7344
  [Intel XE#7345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7345
  [Intel XE#7347]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7347
  [Intel XE#7349]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7349
  [Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
  [Intel XE#7353]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7353
  [Intel XE#7355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7355
  [Intel XE#7356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7356
  [Intel XE#7358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7358
  [Intel XE#7360]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7360
  [Intel XE#7361]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7361
  [Intel XE#7368]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7368
  [Intel XE#7369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7369
  [Intel XE#7370]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7370
  [Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
  [Intel XE#7374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7374
  [Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
  [Intel XE#7385]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7385
  [Intel XE#7389]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7389
  [Intel XE#7395]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7395
  [Intel XE#7397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7397
  [Intel XE#7399]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7399
  [Intel XE#7413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7413
  [Intel XE#7422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7422
  [Intel XE#7453]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7453
  [Intel XE#7457]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7457
  [Intel XE#7471]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7471
  [Intel XE#7482]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7482
  [Intel XE#7484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7484
  [Intel XE#7599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7599
  [Intel XE#7642]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7642
  [Intel XE#7679]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7679
  [Intel XE#7695]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7695
  [Intel XE#7727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7727
  [Intel XE#7774]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7774
  [Intel XE#7793]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7793
  [Intel XE#7809]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7809
  [Intel XE#7865]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7865
  [Intel XE#7892]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7892
  [Intel XE#7905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7905
  [Intel XE#7935]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7935
  [Intel XE#8058]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8058
  [Intel XE#8098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8098
  [Intel XE#8150]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8150
  [Intel XE#8155]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8155
  [Intel XE#8265]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8265
  [Intel XE#8339]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8339
  [Intel XE#8355]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8355
  [Intel XE#8364]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8364
  [Intel XE#8369]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8369
  [Intel XE#8374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8374
  [Intel XE#8378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8378
  [Intel XE#8391]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8391
  [Intel XE#8586]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8586
  [Intel XE#8589]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8589
  [Intel XE#8963]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/8963
  [Intel XE#9096]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9096
  [Intel XE#9142]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9142
  [Intel XE#9144]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9144
  [Intel XE#9271]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9271
  [Intel XE#9362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9362
  [Intel XE#9375]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9375
  [Intel XE#9422]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9422
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [Intel XE#9463]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9463
  [Intel XE#9537]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9537
  [Intel XE#9561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9561
  [Intel XE#9570]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/9570


Build changes
-------------

  * Linux: xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431 -> xe-pw-171757v2

  IGT_9138: 9138
  xe-5928-0f28405022887336d4fc1fe1a0e1429146c2d431: 0f28405022887336d4fc1fe1a0e1429146c2d431
  xe-pw-171757v2: 171757v2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-171757v2/index.html

[-- Attachment #2: Type: text/html, Size: 94126 bytes --]

RE: [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Monday, October 12, 2026 9:27 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; ville.syrjala@linux.intel.com; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT
> 
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Parse the maximum FRL link rate from VBT and store it for use during FRL mode
> selection and link training.

There is nothing getting stored here, maybe rephrase it to expose helper to get
FRL max link rate.

> 
> v3:
> - Bail out early for VBT version < 237 and resolve the max FRL rate in a
>   single switch, handling hdmi_max_frl_rate_valid == 0 up front. (Jani)
> - Drop the intel_bios_hdmi_max_frl_rate() encoder wrapper and take the
>   encoder devdata directly. (Jani)
> - Use the standard VBT debug message format. (Jani)
> - Spell FRL and VBT in caps in the subject and debug message. (Suraj, Jani)
> - Move the hdmi_max_frl_rate_valid == 0 comment onto the check it
>   describes. (Suraj)
> - Add Bspec reference. (Suraj)
> 
> Bspec: XXXXX

Put a valid number here or drop it altogether.

> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 39 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_bios.h     |  1 +
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++
>  3 files changed, 47 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 7b6a6f8c3cf1..7181237508b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2788,12 +2788,45 @@ static bool is_port_valid(struct intel_display *display,
> enum port port)
>  	return true;
>  }
> 
> +int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data
> +*devdata) {
> +	struct intel_display *display = devdata->display;
> +

Add a check for devdata as well to protect against any NULL pointer dereference.
Good to combine that with below check.

> +	if (display->vbt.version < 237)
> +		return 0;
> +
> +	/*
> +	 * When hdmi_max_frl_rate_valid is 0 the VBT does not specify a
> maximum
> +	 * FRL rate, so don't use it to limit the FRL rate on FRL-capable
> +	 * platforms.
> +	 */
> +	if (!devdata->child.hdmi_max_frl_rate_valid)
> +		return display->platform.meteorlake ? 12000000 : 0;
> +

Why special casing for MTL, or update the comment.

> +	switch (devdata->child.hdmi_max_frl_rate) {
> +	default:
> +	case HDMI_MAX_FRL_RATE_PLATFORM:
> +		return 0;
> +	case HDMI_MAX_FRL_RATE_3G:
> +		return 3000000;
> +	case HDMI_MAX_FRL_RATE_6G:
> +		return 6000000;
> +	case HDMI_MAX_FRL_RATE_8G:
> +		return 8000000;
> +	case HDMI_MAX_FRL_RATE_10G:
> +		return 10000000;
> +	case HDMI_MAX_FRL_RATE_12G:
> +		return 12000000;
> +	}
> +}
> +
>  static void print_ddi_port(const struct intel_bios_encoder_data *devdata)  {
>  	struct intel_display *display = devdata->display;
>  	bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb,
> supports_tbt;
>  	int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift,
> max_tmds_clock;
>  	enum port port;
> +	int hdmi_max_frl_rate;
> 
>  	port = intel_bios_encoder_port(devdata);
>  	if (port == PORT_NONE)
> @@ -2863,6 +2896,12 @@ static void print_ddi_port(const struct
> intel_bios_encoder_data *devdata)
>  		drm_dbg_kms(display->drm,
>  			    "Port %c VBT DP max link rate: %d\n",
>  			    port_name(port), dp_max_link_rate);
> +
> +	hdmi_max_frl_rate = intel_bios_hdmi_max_frl_rate(devdata);
> +	if (hdmi_max_frl_rate)
> +		drm_dbg_kms(display->drm,
> +			    "Port %c VBT HDMI max FRL rate: %d\n",
> +			    port_name(port), hdmi_max_frl_rate);
>  }
> 
>  static void parse_ddi_port(struct intel_bios_encoder_data *devdata) diff --git
> a/drivers/gpu/drm/i915/display/intel_bios.h
> b/drivers/gpu/drm/i915/display/intel_bios.h
> index 196b8b3f434f..b89f72d90c1f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -112,6 +112,7 @@ int intel_bios_hdmi_boost_level(const struct
> intel_bios_encoder_data *devdata);  int intel_bios_hdmi_ddc_pin(const struct
> intel_bios_encoder_data *devdata);  int intel_bios_hdmi_level_shift(const struct
> intel_bios_encoder_data *devdata);  int intel_bios_hdmi_max_tmds_clock(const
> struct intel_bios_encoder_data *devdata);
> +int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data
> +*devdata);
> 
>  void intel_bios_for_each_encoder(struct intel_display *display,
>  				 void (*func)(struct intel_display *display, diff --git
> a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 0dc13d080e8a..db7484542dc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -381,6 +381,13 @@ struct bdb_general_features {
>  #define HDMI_MAX_DATA_RATE_340		4			/* 249+ */
>  #define HDMI_MAX_DATA_RATE_300		5			/* 249+ */
> 
> +#define HDMI_MAX_FRL_RATE_PLATFORM	0			/* 237 */

Use 237+ to remain consistent, do it for all.

> +#define HDMI_MAX_FRL_RATE_3G		1			/* 237 */
> +#define HDMI_MAX_FRL_RATE_6G		2			/* 237 */
> +#define HDMI_MAX_FRL_RATE_8G		3			/* 237 */
> +#define HDMI_MAX_FRL_RATE_10G		4			/* 237 */
> +#define HDMI_MAX_FRL_RATE_12G		5			/* 237 */
> +
>  #define LEGACY_CHILD_DEVICE_CONFIG_SIZE		33
> 
>  /* DDC Bus DDI Type 155+ */
> --
> 2.50.1

RE: [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT

[Shankar, Uma]

> -----Original Message-----
> From: Shankar, Uma
> Sent: Monday, October 12, 2026 1:31 PM
> To: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; jani.nikula@linux.intel.com;
> ville.syrjala@linux.intel.com; Kandpal, Suraj <suraj.kandpal@intel.com>
> Subject: RE: [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from VBT
> 
> 
> 
> > -----Original Message-----
> > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> > Sent: Monday, October 12, 2026 9:27 AM
> > To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org; jani.nikula@linux.intel.com;
> > Shankar, Uma <uma.shankar@intel.com>; ville.syrjala@linux.intel.com;
> > Kandpal, Suraj <suraj.kandpal@intel.com>
> > Subject: [PATCH v2 01/56] drm/i915/hdmi: Parse FRL max link rate from
> > VBT
> >
> > From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >
> > Parse the maximum FRL link rate from VBT and store it for use during
> > FRL mode selection and link training.
> 
> There is nothing getting stored here, maybe rephrase it to expose helper to get
> FRL max link rate.
> 
> >
> > v3:
> > - Bail out early for VBT version < 237 and resolve the max FRL rate in a
> >   single switch, handling hdmi_max_frl_rate_valid == 0 up front.
> > (Jani)
> > - Drop the intel_bios_hdmi_max_frl_rate() encoder wrapper and take the
> >   encoder devdata directly. (Jani)
> > - Use the standard VBT debug message format. (Jani)
> > - Spell FRL and VBT in caps in the subject and debug message. (Suraj,
> > Jani)
> > - Move the hdmi_max_frl_rate_valid == 0 comment onto the check it
> >   describes. (Suraj)
> > - Add Bspec reference. (Suraj)
> >
> > Bspec: XXXXX
> 
> Put a valid number here or drop it altogether.
> 
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_bios.c     | 39 +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_bios.h     |  1 +
> >  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++
> >  3 files changed, 47 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> > b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 7b6a6f8c3cf1..7181237508b3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -2788,12 +2788,45 @@ static bool is_port_valid(struct intel_display
> > *display, enum port port)
> >  	return true;
> >  }
> >
> > +int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data
> > +*devdata) {
> > +	struct intel_display *display = devdata->display;
> > +
> 
> Add a check for devdata as well to protect against any NULL pointer dereference.
> Good to combine that with below check.
> 
> > +	if (display->vbt.version < 237)
> > +		return 0;
> > +
> > +	/*
> > +	 * When hdmi_max_frl_rate_valid is 0 the VBT does not specify a
> > maximum
> > +	 * FRL rate, so don't use it to limit the FRL rate on FRL-capable
> > +	 * platforms.
> > +	 */
> > +	if (!devdata->child.hdmi_max_frl_rate_valid)
> > +		return display->platform.meteorlake ? 12000000 : 0;
> > +
> 
> Why special casing for MTL, or update the comment.

One additional thing I missed, this will cause disable FRL on newer platforms
if this VBT setting is missed.

enable_frl = true is dependant on an AND condition with this expected to be
non zero.

> 
> > +	switch (devdata->child.hdmi_max_frl_rate) {
> > +	default:
> > +	case HDMI_MAX_FRL_RATE_PLATFORM:
> > +		return 0;

Also as per VBT spec, 
000 = Default (Software should choose the maximum data rate as supported by platform BSpec)

However if we return 0 here, it will disable FRL altogether. Please check once.

> > +	case HDMI_MAX_FRL_RATE_3G:
> > +		return 3000000;
> > +	case HDMI_MAX_FRL_RATE_6G:
> > +		return 6000000;
> > +	case HDMI_MAX_FRL_RATE_8G:
> > +		return 8000000;
> > +	case HDMI_MAX_FRL_RATE_10G:
> > +		return 10000000;
> > +	case HDMI_MAX_FRL_RATE_12G:
> > +		return 12000000;
> > +	}
> > +}
> > +
> >  static void print_ddi_port(const struct intel_bios_encoder_data *devdata)  {
> >  	struct intel_display *display = devdata->display;
> >  	bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt,
> > supports_typec_usb, supports_tbt;
> >  	int dp_boost_level, dp_max_link_rate, hdmi_boost_level,
> > hdmi_level_shift, max_tmds_clock;
> >  	enum port port;
> > +	int hdmi_max_frl_rate;
> >
> >  	port = intel_bios_encoder_port(devdata);
> >  	if (port == PORT_NONE)
> > @@ -2863,6 +2896,12 @@ static void print_ddi_port(const struct
> > intel_bios_encoder_data *devdata)
> >  		drm_dbg_kms(display->drm,
> >  			    "Port %c VBT DP max link rate: %d\n",
> >  			    port_name(port), dp_max_link_rate);
> > +
> > +	hdmi_max_frl_rate = intel_bios_hdmi_max_frl_rate(devdata);
> > +	if (hdmi_max_frl_rate)
> > +		drm_dbg_kms(display->drm,
> > +			    "Port %c VBT HDMI max FRL rate: %d\n",
> > +			    port_name(port), hdmi_max_frl_rate);
> >  }
> >
> >  static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> > b/drivers/gpu/drm/i915/display/intel_bios.h
> > index 196b8b3f434f..b89f72d90c1f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> > @@ -112,6 +112,7 @@ int intel_bios_hdmi_boost_level(const struct
> > intel_bios_encoder_data *devdata);  int intel_bios_hdmi_ddc_pin(const
> > struct intel_bios_encoder_data *devdata);  int
> > intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data
> > *devdata);  int intel_bios_hdmi_max_tmds_clock(const
> > struct intel_bios_encoder_data *devdata);
> > +int intel_bios_hdmi_max_frl_rate(const struct intel_bios_encoder_data
> > +*devdata);
> >
> >  void intel_bios_for_each_encoder(struct intel_display *display,
> >  				 void (*func)(struct intel_display *display, diff --git
> > a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 0dc13d080e8a..db7484542dc0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -381,6 +381,13 @@ struct bdb_general_features {
> >  #define HDMI_MAX_DATA_RATE_340		4			/*
> 249+ */
> >  #define HDMI_MAX_DATA_RATE_300		5			/*
> 249+ */
> >
> > +#define HDMI_MAX_FRL_RATE_PLATFORM	0			/*
> 237 */
> 
> Use 237+ to remain consistent, do it for all.
> 
> > +#define HDMI_MAX_FRL_RATE_3G		1			/* 237 */
> > +#define HDMI_MAX_FRL_RATE_6G		2			/* 237 */
> > +#define HDMI_MAX_FRL_RATE_8G		3			/* 237 */
> > +#define HDMI_MAX_FRL_RATE_10G		4			/*
> 237 */
> > +#define HDMI_MAX_FRL_RATE_12G		5			/*
> 237 */
> > +
> >  #define LEGACY_CHILD_DEVICE_CONFIG_SIZE		33
> >
> >  /* DDC Bus DDI Type 155+ */
> > --
> > 2.50.1

RE: [PATCH v2 02/56] drm/i915/hdmi: Add new data members for FRL configuration

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Monday, October 12, 2026 9:27 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; ville.syrjala@linux.intel.com; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH v2 02/56] drm/i915/hdmi: Add new data members for FRL
> configuration
> 
> HDMI supports higher resolutions using Fixed Rate Link.
> Source needs to do FRL link training on the 4 lanes before video stream
> transmission.
> 
> Add the members to crtc_state and intel_hdmi for identifying the FRL supporting
> HDMI sink and to maintain the FRL training information after successful training.

Seems only intel_hdmi is touched here, drop crtc_state from comment.

> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  9 +++++
>  drivers/gpu/drm/i915/display/intel_hdmi.c     | 36 +++++++++++++++++++
>  2 files changed, 45 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 79f30660c2b6..89333c9ddcc8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1709,8 +1709,17 @@ struct intel_hdmi {
>  		enum drm_dp_dual_mode_type type;
>  		int max_tmds_clock;
>  	} dp_dual_mode;
> +	bool has_sink_hdmi_21;
> +	int max_frl_rate;
> +	int max_dsc_frl_rate;
>  	struct intel_connector *attached_connector;
>  	struct cec_notifier *cec_notifier;
> +	struct {
> +		bool trained;
> +		int lanes;
> +		int rate_gbps;
> +		int ffe_level;
> +	} frl;
>  };
> 
>  struct intel_dp_mst_encoder;
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index b6fa1a1558b8..69534eea78a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2485,6 +2485,8 @@ intel_hdmi_unset_edid(struct drm_connector
> *_connector)
>  	struct intel_connector *connector = to_intel_connector(_connector);
>  	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
> 
> +	intel_hdmi->has_sink_hdmi_21 = false;

but max_frl_rate, max_dsc_frl_rate, and the frl.* training state are left behind. On unplug,
these carry stale values from the previous sink. unset_edid should also zero
max_frl_rate/max_dsc_frl_rate and call intel_hdmi_reset_frl_config()

> +
>  	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
>  	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
> 
> @@ -2545,6 +2547,38 @@ intel_hdmi_dp_dual_mode_detect(struct
> drm_connector *_connector)
>  	}
>  }
> 
> +static void
> +intel_hdmi_reset_frl_config(struct intel_hdmi *intel_hdmi) {
> +	intel_hdmi->frl.trained = false;
> +	intel_hdmi->frl.lanes = 0;
> +	intel_hdmi->frl.rate_gbps = 0;
> +	intel_hdmi->frl.ffe_level = 0;
> +}
> +
> +static void
> +intel_hdmi_init_frl_config(struct intel_connector *connector) {
> +	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
> +	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
> +	int max_src_frl_rate =
> +		DIV_ROUND_UP(intel_bios_hdmi_max_frl_rate(encoder-
> >devdata), 1000000) * 4;

We should maybe check the validity of encoder->devdata before going further.
Also define a MACRO for the magic number. For 4 as well you can use MAX_FRL_LANES.

> +	int max_sink_dsc_frl_rate =
> +		intel_hdmi_sink_dsc_max_frl_rate(&connector->base);
> +	int max_sink_frl_rate =
> +		intel_hdmi_sink_max_frl_rate(&connector->base);
> +
> +	intel_hdmi->has_sink_hdmi_21 = max_sink_frl_rate > 0;
> +
> +	intel_hdmi->max_frl_rate = min(max_sink_frl_rate,
> +				       max_src_frl_rate);

Per the previous patch, intel_bios_hdmi_max_frl_rate() returns 0 to mean "no VBT limit / use platform default".
Here src == 0 makes max_src_frl_rate == 0, and min(sink, 0) == 0 - so FRL is fully disabled even when
the sink supports it. Only MTL escapes this, every very other FRL-capable platform collapses to 0. Clamp only
when source value is non-zero (e.g. if (max_src_frl_rate) rate = min(rate, max_src_frl_rate)), same for max_dsc_frl_rate.

> +
> +	intel_hdmi->max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
> +					   max_src_frl_rate);
> +
> +	intel_hdmi_reset_frl_config(intel_hdmi);
> +}
> +
>  static bool
>  intel_hdmi_set_edid(struct drm_connector *_connector)  { @@ -2576,6 +2610,8
> @@ intel_hdmi_set_edid(struct drm_connector *_connector)
>  	if (drm_edid_is_digital(drm_edid)) {
>  		intel_hdmi_dp_dual_mode_detect(&connector->base);
> 
> +		intel_hdmi_init_frl_config(connector);
> +
>  		connected = true;
>  	}
> 
> --
> 2.50.1

RE: [PATCH v2 03/56] drm/i915/hdmi: Add FRL link rate cap

[Shankar, Uma]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Monday, October 12, 2026 9:27 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; jani.nikula@linux.intel.com; Shankar, Uma
> <uma.shankar@intel.com>; ville.syrjala@linux.intel.com; Kandpal, Suraj
> <suraj.kandpal@intel.com>
> Subject: [PATCH v2 03/56] drm/i915/hdmi: Add FRL link rate cap
> 
> Add a member rate_cap to store the highest FRL rate the link is believed to
> sustain. This is initially set based on the source and sink FRL capabilities, and
> updated only when the capabilities change. To achieve this, the reset is gated by a
> reset_rate_cap flag, so that rate_cap is left as is on a plain re-probe.
> 
> Also reset the rate cap when the status changes to disconnected, so that a re-plug
> of the same sink starts again from the full capability.
> 
> Later during a Link training failure at a specific rate, rate_cap can be lowered, and
> since it is retained across a re-probe, the next training attempt will honor the
> reduced cap. No user for now, this will be used in the later changes.

Change Looks Good to me. With comments in earlier patches fixed this is:
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_hdmi.c     | 33 ++++++++++++++++---
>  2 files changed, 30 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 89333c9ddcc8..8a2128473f4f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1719,6 +1719,8 @@ struct intel_hdmi {
>  		int lanes;
>  		int rate_gbps;
>  		int ffe_level;
> +		int rate_cap;
> +		bool reset_rate_cap;
>  	} frl;
>  };
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 69534eea78a1..5c57f81d971b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2567,14 +2567,30 @@ intel_hdmi_init_frl_config(struct intel_connector
> *connector)
>  		intel_hdmi_sink_dsc_max_frl_rate(&connector->base);
>  	int max_sink_frl_rate =
>  		intel_hdmi_sink_max_frl_rate(&connector->base);
> +	int max_frl_rate, max_dsc_frl_rate;
> 
>  	intel_hdmi->has_sink_hdmi_21 = max_sink_frl_rate > 0;
> 
> -	intel_hdmi->max_frl_rate = min(max_sink_frl_rate,
> -				       max_src_frl_rate);
> +	max_frl_rate = min(max_sink_frl_rate, max_src_frl_rate);
> 
> -	intel_hdmi->max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
> -					   max_src_frl_rate);
> +	max_dsc_frl_rate = min(max_sink_dsc_frl_rate,
> +			       max_src_frl_rate);
> +	/*
> +	 * Set the FRL rate cap on connect / capability change only.
> +	 * Leaving it untouched on a plain re-probe lets a future
> +	 * training-driven reduction persist across the retry.
> +	 */
> +	if (max_frl_rate != intel_hdmi->max_frl_rate ||
> +	    max_dsc_frl_rate != intel_hdmi->max_dsc_frl_rate)
> +		intel_hdmi->frl.reset_rate_cap = true;
> +
> +	intel_hdmi->max_frl_rate = max_frl_rate;
> +	intel_hdmi->max_dsc_frl_rate = max_dsc_frl_rate;
> +
> +	if (intel_hdmi->frl.reset_rate_cap) {
> +		intel_hdmi->frl.rate_cap = max(max_frl_rate, max_dsc_frl_rate);
> +		intel_hdmi->frl.reset_rate_cap = false;
> +	}
> 
>  	intel_hdmi_reset_frl_config(intel_hdmi);
>  }
> @@ -2656,9 +2672,16 @@ intel_hdmi_detect(struct drm_connector *_connector,
> bool force)
>  out:
>  	intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref);
> 
> -	if (status != connector_status_connected)
> +	if (status != connector_status_connected) {
>  		cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
> 
> +		/*
> +		 * Reset the rate cap so that the next connect re-initializes
> +		 * frl.rate_cap to the capability ceiling.
> +		 */
> +		intel_hdmi->frl.reset_rate_cap = true;
> +	}
> +
>  	return status;
>  }
> 
> --
> 2.50.1